1/* 2 Copyright 1999, Be Incorporated. All Rights Reserved. 3 This file may be used under the terms of the Be Sample Code License. 4 5 Other authors: 6 Mark Watson; 7 Apsed; 8 Rudolf Cornelissen 10/2002-4/2006. 9*/ 10 11#ifndef DRIVERINTERFACE_H 12#define DRIVERINTERFACE_H 13 14#include <Accelerant.h> 15#include "video_overlay.h" 16#include <Drivers.h> 17#include <PCI.h> 18#include <OS.h> 19 20#define DRIVER_PREFIX "matrox" // apsed 21#define DEVICE_FORMAT "%04x_%04x_%02x%02x%02x" // apsed 22 23/* 24 Internal driver state (also for sharing info between driver and accelerant) 25*/ 26#if defined(__cplusplus) 27extern "C" { 28#endif 29 30typedef struct { 31 sem_id sem; 32 int32 ben; 33} benaphore; 34 35#define INIT_BEN(x) x.sem = create_sem(0, "G400 "#x" benaphore"); x.ben = 0; 36#define AQUIRE_BEN(x) if((atomic_add(&(x.ben), 1)) >= 1) acquire_sem(x.sem); 37#define RELEASE_BEN(x) if((atomic_add(&(x.ben), -1)) > 1) release_sem(x.sem); 38#define DELETE_BEN(x) delete_sem(x.sem); 39 40 41#define GX00_PRIVATE_DATA_MAGIC 0x0009 /* a private driver rev, of sorts */ 42 43/*dualhead extensions to flags*/ 44#define DUALHEAD_OFF (0<<6) 45#define DUALHEAD_CLONE (1<<6) 46#define DUALHEAD_ON (2<<6) 47#define DUALHEAD_SWITCH (3<<6) 48#define DUALHEAD_BITS (3<<6) 49#define DUALHEAD_CAPABLE (1<<8) 50#define TV_BITS (3<<9) 51#define TV_MON (0<<9 52#define TV_PAL (1<<9) 53#define TV_NTSC (2<<9) 54#define TV_CAPABLE (1<<11) 55#define TV_VIDEO (1<<12) 56#define TV_PRIMARY (1<<13) 57 58#define SKD_MOVE_CURSOR 0x00000001 59#define SKD_PROGRAM_CLUT 0x00000002 60#define SKD_SET_START_ADDR 0x00000004 61#define SKD_SET_CURSOR 0x00000008 62#define SKD_HANDLER_INSTALLED 0x80000000 63 64enum { 65 GX00_GET_PRIVATE_DATA = B_DEVICE_OP_CODES_END + 1, 66 GX00_GET_PCI, 67 GX00_SET_PCI, 68 GX00_DEVICE_NAME, 69 GX00_RUN_INTERRUPTS 70}; 71 72/* max. number of overlay buffers */ 73#define MAXBUFFERS 3 74/* max. pixelclock speed the BES supports */ 75#define BESMAXSPEED 135000 76 77/* internal used info on overlay buffers */ 78typedef struct 79{ 80 uint16 slopspace; 81 uint32 size; 82} int_buf_info; 83 84typedef struct settings { // apsed, see comments in mga.settings 85 // for driver 86 char accelerant[B_FILE_NAME_LENGTH]; 87 char primary[B_FILE_NAME_LENGTH]; 88 bool dumprom; 89 // for accelerant 90 uint32 logmask; 91 uint32 memory; 92 bool usebios; 93 bool hardcursor; 94 bool greensync; 95} settings; 96 97/* shared info */ 98typedef struct { 99 /* a few ID things */ 100 uint16 vendor_id; /* PCI vendor ID, from pci_info */ 101 uint16 device_id; /* PCI device ID, from pci_info */ 102 uint8 revision; /* PCI device revsion, from pci_info */ 103 uint8 bus; /* PCI bus number, from pci_info */ 104 uint8 device; /* PCI device number on bus, from pci_info */ 105 uint8 function; /* PCI function number in device, from pci_info */ 106 107 /* used to return status for INIT_ACCELERANT and CLONE_ACCELERANT */ 108 bool accelerant_in_use; 109 110 /* bug workaround for 4.5.0 */ 111 uint32 use_clone_bugfix; /*for 4.5.0, cloning of physical memory does not work*/ 112 uint32 * clone_bugfix_regs; 113 114 /*memory mappings*/ 115 area_id regs_area; /* Kernel's area_id for the memory mapped registers. 116 It will be cloned into the accelerant's address 117 space. */ 118 119 area_id fb_area; /* Frame buffer's area_id. The addresses are shared with all teams. */ 120 area_id pseudo_dma_area; /* Pseudo dma area_id. Shared by all teams. */ 121 area_id dma_buffer_area; /* Area assigned for dma*/ 122 123 void *framebuffer; /* As viewed from virtual memory */ 124 void *framebuffer_pci; /* As viewed from the PCI bus (for DMA) */ 125 126 void *pseudo_dma; /* As viewed from virtual memory */ 127 128 void *dma_buffer; /* buffer for dma*/ 129 void *dma_buffer_pci; /* buffer for dma - from PCI bus*/ 130 131 /*screenmode list*/ 132 area_id mode_area; /* Contains the list of display modes the driver supports */ 133 uint32 mode_count; /* Number of display modes in the list */ 134 135 /*flags - used by driver*/ 136 uint32 flags; 137 138 /*vblank semaphore*/ 139 sem_id vblank; /* The vertical blank semaphore. Ownership will be 140 transfered to the team opening the device first */ 141 /*cursor information*/ 142 struct { 143 uint16 hot_x; /* Cursor hot spot. The top left corner of the cursor */ 144 uint16 hot_y; /* is 0,0 */ 145 uint16 x; /* The location of the cursor hot spot on the */ 146 uint16 y; /* desktop */ 147 uint16 width; /* Width and height of the cursor shape (always 16!) */ 148 uint16 height; 149 bool is_visible; /* Is the cursor currently displayed? */ 150 } cursor; 151 152 /*colour lookup table*/ 153 uint8 color_data[3 * 256]; /* Colour lookup table - as used by DAC */ 154 155 /*more display mode stuff*/ 156 display_mode dm; /* current display mode configuration: head1 */ 157 display_mode dm2; /* current display mode configuration: head2 */ 158 uint32 dpms_flags; /* current DPMS mode */ 159 bool switched_crtcs; /* dualhead stretch and switch mode info */ 160 bool acc_mode; /* signals (non)accelerated mode */ 161 bool interlaced_tv_mode;/* signals interlaced CRTC TV output mode */ 162 163 /*frame buffer config - for BDirectScreen*/ 164 frame_buffer_config fbc; /* bytes_per_row and start of frame buffer: head1 */ 165 frame_buffer_config fbc2; /* bytes_per_row and start of frame buffer: head2 */ 166 accelerant_device_info adi; /* as returned by hook GET_ACCELERANT_DEVICE_INFO */ 167 168 /*acceleration engine*/ 169 struct { 170 uint32 count; /* last dwgsync slot used */ 171 uint32 last_idle; /* last dwgsync slot we *know* the engine was idle after */ 172 benaphore lock; /* for serializing access to the acceleration engine */ 173 uint32 src_dst; /* G100 pre SRCORG/DSTORG registers */ 174 uint8 y_lin; /* MIL1/2 adress linearisation does not always work */ 175 uint8 depth; 176 } engine; 177 178 /* card info - information gathered from PINS (and other sources) */ 179 enum 180 { // card_type in order of date of MGA chip design 181 MIL1 = 0, 182 MYST, 183 MIL2, 184 G100, 185 G200, 186 G400, 187 G400MAX, 188 G450, 189 G550 190 } card_type; 191 struct 192 { 193 /* specialised registers for card initialisation read from MGA BIOS (pins) */ 194 195 /* general card information */ 196 uint32 card_type; /* see card_type enum above */ 197 bool int_assigned; /* card has a useable INT assigned to it */ 198 status_t pins_status; /* B_OK if read correctly, B_ERROR if faked */ 199 bool sdram; /* TRUE if SDRAM card: needed info for 2D acceleration */ 200 201 /* PINS */ 202 float f_ref; /* PLL reference-oscillator frequency (Mhz) */ 203 uint32 max_system_vco; /* graphics engine PLL VCO limits (Mhz) */ 204 uint32 min_system_vco; 205 uint32 max_pixel_vco; /* dac1 PLL VCO limits (Mhz) */ 206 uint32 min_pixel_vco; 207 uint32 max_video_vco; /* dac2, maven PLL VCO limits (Mhz) */ 208 uint32 min_video_vco; 209 uint32 std_engine_clock; /* graphics engine clock speed needed (Mhz) */ 210 uint32 std_engine_clock_dh; 211 uint32 max_dac1_clock; /* dac1 limits (Mhz) */ 212 uint32 max_dac1_clock_8; /* dac1 limits correlated to RAMspeed limits (Mhz) */ 213 uint32 max_dac1_clock_16; 214 uint32 max_dac1_clock_24; 215 uint32 max_dac1_clock_32; 216 uint32 max_dac1_clock_32dh; 217 uint32 max_dac2_clock; /* dac2 limits (Mhz) */ 218 uint32 max_dac2_clock_8; /* dac2, maven limits correlated to RAMspeed limits (Mhz) */ 219 uint32 max_dac2_clock_16; 220 uint32 max_dac2_clock_24; 221 uint32 max_dac2_clock_32; 222 uint32 max_dac2_clock_32dh; 223 bool secondary_head; /* presence of functions */ 224 bool tvout; 225 bool primary_dvi; 226 bool secondary_dvi; 227 uint32 memory_size; /* memory (Mb) */ 228 uint32 mctlwtst_reg; /* memory control waitstate register */ 229 uint32 memrdbk_reg; /* memory readback register */ 230 uint32 option_reg; /* option register */ 231 uint32 option2_reg; /* option2 register */ 232 uint32 option3_reg; /* option3 register */ 233 uint32 option4_reg; /* option4 register */ 234 uint8 v3_option2_reg; /* pins v3 option2 register, not used for G100 */ 235 uint8 v3_clk_div; /* pins v3 memory and system clock division factors */ 236 uint8 v3_mem_type; /* pins v3 memory type info */ 237 uint16 v5_mem_type; /* pins v5 memory type info */ 238 } ps; 239 240 /* mirror of the ROM (copied in driver, because may not be mapped permanently - only over fb) */ 241 uint8 rom_mirror[32768]; 242 243 /* CRTC delay -> used in timing for MAVEN, depending on which CRTC is driving it */ 244 uint8 crtc_delay; 245 246 /* MAVEN sync polarity offset from 'reset' situation: MAVEN sync polarity setup 247 * works in a serial fashion without readback or handy reset options! */ 248 uint8 maven_syncpol_offset; 249 250 /* On G450/G550 we need this info for secondary head DPMS functionality */ 251 bool crossed_conns; 252 253 /* apsed: some configuration settings from ~/config/settings/kernel/drivers/mga.settings if exists */ 254 settings settings; 255 256 struct 257 { 258 overlay_buffer myBuffer[MAXBUFFERS];/* scaler input buffers */ 259 int_buf_info myBufInfo[MAXBUFFERS]; /* extra info on scaler input buffers */ 260 overlay_token myToken; /* scaler is free/in use */ 261 benaphore lock; /* for creating buffers and aquiring overlay unit routines */ 262 /* variables needed for virtualscreens (move_overlay()): */ 263 bool active; /* true is overlay currently in use */ 264 overlay_window ow; /* current position of overlay output window */ 265 overlay_buffer ob; /* current inputbuffer in use */ 266 overlay_view my_ov; /* current corrected view in inputbuffer */ 267 uint32 h_ifactor; /* current 'unclipped' horizontal inverse scaling factor */ 268 uint32 v_ifactor; /* current 'unclipped' vertical inverse scaling factor */ 269 } overlay; 270 271} shared_info; 272 273/* Read or write a value in PCI configuration space */ 274typedef struct { 275 uint32 magic; /* magic number to make sure the caller groks us */ 276 uint32 offset; /* Offset to read/write */ 277 uint32 size; /* Number of bytes to transfer */ 278 uint32 value; /* The value read or written */ 279} gx00_get_set_pci; 280 281/* Set some boolean condition (like enabling or disabling interrupts) */ 282typedef struct { 283 uint32 magic; /* magic number to make sure the caller groks us */ 284 bool do_it; /* state to set */ 285} gx00_set_bool_state; 286 287/* Retrieve the area_id of the kernel/accelerant shared info */ 288typedef struct { 289 uint32 magic; /* magic number to make sure the caller groks us */ 290 area_id shared_info_area; /* area_id containing the shared information */ 291} gx00_get_private_data; 292 293/* Retrieve the device name. Usefull for when we have a file handle, but want 294to know the device name (like when we are cloning the accelerant) */ 295typedef struct { 296 uint32 magic; /* magic number to make sure the caller groks us */ 297 char *name; /* The name of the device, less the /dev root */ 298} gx00_device_name; 299 300enum { 301 GX00_WAIT_FOR_VBLANK = (1 << 0) 302}; 303 304#if defined(__cplusplus) 305} 306#endif 307 308 309#endif 310