Searched refs:ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE (Results 1 - 16 of 16) sorted by path

/linux-master/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_1_0_offset.h13874 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE macro
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H A Ddcn_2_0_0_offset.h17298 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE macro
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H A Ddcn_2_1_0_offset.h13634 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE macro
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H A Ddcn_3_0_0_offset.h17674 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE macro
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H A Ddcn_3_0_1_offset.h13030 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE macro
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H A Ddcn_3_0_2_offset.h15943 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE macro
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H A Ddcn_3_0_3_offset.h8215 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 macro
H A Ddcn_3_1_2_offset.h14848 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE macro
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H A Ddcn_3_1_4_offset.h945 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 macro
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H A Ddcn_3_1_5_offset.h14954 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE macro
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H A Ddcn_3_1_6_offset.h15445 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE macro
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H A Ddcn_3_2_0_offset.h14401 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE macro
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H A Ddcn_3_2_1_offset.h14355 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE macro
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H A Ddcn_3_5_0_offset.h905 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 macro
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H A Ddcn_3_5_1_offset.h884 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 macro
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/linux-master/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_12_0_offset.h17687 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE macro
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