1/* 2 * Copyright (C) 2022 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included 12 * in all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 20 */ 21#ifndef _dcn_3_2_0_OFFSET_HEADER 22#define _dcn_3_2_0_OFFSET_HEADER 23 24 25 26// addressBlock: dcn_dc_dccg_dccg_dfs_dispdec 27// base address: 0x0 28#define regDENTIST_DISPCLK_CNTL 0x0064 29#define regDENTIST_DISPCLK_CNTL_BASE_IDX 1 30 31 32// addressBlock: dcn_dc_dccg_dccg_dispdec 33// base address: 0x0 34#define regPHYPLLA_PIXCLK_RESYNC_CNTL 0x0040 35#define regPHYPLLA_PIXCLK_RESYNC_CNTL_BASE_IDX 1 36#define regPHYPLLB_PIXCLK_RESYNC_CNTL 0x0041 37#define regPHYPLLB_PIXCLK_RESYNC_CNTL_BASE_IDX 1 38#define regPHYPLLC_PIXCLK_RESYNC_CNTL 0x0042 39#define regPHYPLLC_PIXCLK_RESYNC_CNTL_BASE_IDX 1 40#define regPHYPLLD_PIXCLK_RESYNC_CNTL 0x0043 41#define regPHYPLLD_PIXCLK_RESYNC_CNTL_BASE_IDX 1 42#define regDP_DTO_DBUF_EN 0x0044 43#define regDP_DTO_DBUF_EN_BASE_IDX 1 44#define regDSCCLK3_DTO_PARAM 0x0045 45#define regDSCCLK3_DTO_PARAM_BASE_IDX 1 46#define regDPREFCLK_CGTT_BLK_CTRL_REG 0x0048 47#define regDPREFCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1 48#define regDCCG_GATE_DISABLE_CNTL4 0x0049 49#define regDCCG_GATE_DISABLE_CNTL4_BASE_IDX 1 50#define regDPSTREAMCLK_CNTL 0x004a 51#define regDPSTREAMCLK_CNTL_BASE_IDX 1 52#define regREFCLK_CGTT_BLK_CTRL_REG 0x004b 53#define regREFCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1 54#define regPHYPLLE_PIXCLK_RESYNC_CNTL 0x004c 55#define regPHYPLLE_PIXCLK_RESYNC_CNTL_BASE_IDX 1 56#define regDCCG_GLOBAL_FGCG_REP_CNTL 0x0050 57#define regDCCG_GLOBAL_FGCG_REP_CNTL_BASE_IDX 1 58#define regDCCG_DS_DTO_INCR 0x0053 59#define regDCCG_DS_DTO_INCR_BASE_IDX 1 60#define regDCCG_DS_DTO_MODULO 0x0054 61#define regDCCG_DS_DTO_MODULO_BASE_IDX 1 62#define regDCCG_DS_CNTL 0x0055 63#define regDCCG_DS_CNTL_BASE_IDX 1 64#define regDCCG_DS_HW_CAL_INTERVAL 0x0056 65#define regDCCG_DS_HW_CAL_INTERVAL_BASE_IDX 1 66#define regDPREFCLK_CNTL 0x0058 67#define regDPREFCLK_CNTL_BASE_IDX 1 68#define regDCE_VERSION 0x005e 69#define regDCE_VERSION_BASE_IDX 1 70#define regDCCG_GTC_CNTL 0x0060 71#define regDCCG_GTC_CNTL_BASE_IDX 1 72#define regDCCG_GTC_DTO_INCR 0x0061 73#define regDCCG_GTC_DTO_INCR_BASE_IDX 1 74#define regDCCG_GTC_DTO_MODULO 0x0062 75#define regDCCG_GTC_DTO_MODULO_BASE_IDX 1 76#define regDCCG_GTC_CURRENT 0x0063 77#define regDCCG_GTC_CURRENT_BASE_IDX 1 78#define regSYMCLK32_SE_CNTL 0x0065 79#define regSYMCLK32_SE_CNTL_BASE_IDX 1 80#define regSYMCLK32_LE_CNTL 0x0066 81#define regSYMCLK32_LE_CNTL_BASE_IDX 1 82#define regDTBCLK_P_CNTL 0x0068 83#define regDTBCLK_P_CNTL_BASE_IDX 1 84#define regDCCG_GATE_DISABLE_CNTL5 0x0069 85#define regDCCG_GATE_DISABLE_CNTL5_BASE_IDX 1 86#define regDSCCLK0_DTO_PARAM 0x006c 87#define regDSCCLK0_DTO_PARAM_BASE_IDX 1 88#define regDSCCLK1_DTO_PARAM 0x006d 89#define regDSCCLK1_DTO_PARAM_BASE_IDX 1 90#define regDSCCLK2_DTO_PARAM 0x006e 91#define regDSCCLK2_DTO_PARAM_BASE_IDX 1 92#define regOTG_PIXEL_RATE_DIV 0x006f 93#define regOTG_PIXEL_RATE_DIV_BASE_IDX 1 94#define regMILLISECOND_TIME_BASE_DIV 0x0070 95#define regMILLISECOND_TIME_BASE_DIV_BASE_IDX 1 96#define regDISPCLK_FREQ_CHANGE_CNTL 0x0071 97#define regDISPCLK_FREQ_CHANGE_CNTL_BASE_IDX 1 98#define regDC_MEM_GLOBAL_PWR_REQ_CNTL 0x0072 99#define regDC_MEM_GLOBAL_PWR_REQ_CNTL_BASE_IDX 1 100#define regDCCG_GATE_DISABLE_CNTL 0x0074 101#define regDCCG_GATE_DISABLE_CNTL_BASE_IDX 1 102#define regDISPCLK_CGTT_BLK_CTRL_REG 0x0075 103#define regDISPCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1 104#define regSOCCLK_CGTT_BLK_CTRL_REG 0x0076 105#define regSOCCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1 106#define regDCCG_CAC_STATUS 0x0077 107#define regDCCG_CAC_STATUS_BASE_IDX 1 108#define regMICROSECOND_TIME_BASE_DIV 0x007b 109#define regMICROSECOND_TIME_BASE_DIV_BASE_IDX 1 110#define regDCCG_GATE_DISABLE_CNTL2 0x007c 111#define regDCCG_GATE_DISABLE_CNTL2_BASE_IDX 1 112#define regSYMCLK_CGTT_BLK_CTRL_REG 0x007d 113#define regSYMCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1 114#define regDCCG_DISP_CNTL_REG 0x007f 115#define regDCCG_DISP_CNTL_REG_BASE_IDX 1 116#define regOTG0_PIXEL_RATE_CNTL 0x0080 117#define regOTG0_PIXEL_RATE_CNTL_BASE_IDX 1 118#define regDP_DTO0_PHASE 0x0081 119#define regDP_DTO0_PHASE_BASE_IDX 1 120#define regDP_DTO0_MODULO 0x0082 121#define regDP_DTO0_MODULO_BASE_IDX 1 122#define regOTG0_PHYPLL_PIXEL_RATE_CNTL 0x0083 123#define regOTG0_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1 124#define regOTG1_PIXEL_RATE_CNTL 0x0084 125#define regOTG1_PIXEL_RATE_CNTL_BASE_IDX 1 126#define regDP_DTO1_PHASE 0x0085 127#define regDP_DTO1_PHASE_BASE_IDX 1 128#define regDP_DTO1_MODULO 0x0086 129#define regDP_DTO1_MODULO_BASE_IDX 1 130#define regOTG1_PHYPLL_PIXEL_RATE_CNTL 0x0087 131#define regOTG1_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1 132#define regOTG2_PIXEL_RATE_CNTL 0x0088 133#define regOTG2_PIXEL_RATE_CNTL_BASE_IDX 1 134#define regDP_DTO2_PHASE 0x0089 135#define regDP_DTO2_PHASE_BASE_IDX 1 136#define regDP_DTO2_MODULO 0x008a 137#define regDP_DTO2_MODULO_BASE_IDX 1 138#define regOTG2_PHYPLL_PIXEL_RATE_CNTL 0x008b 139#define regOTG2_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1 140#define regOTG3_PIXEL_RATE_CNTL 0x008c 141#define regOTG3_PIXEL_RATE_CNTL_BASE_IDX 1 142#define regDP_DTO3_PHASE 0x008d 143#define regDP_DTO3_PHASE_BASE_IDX 1 144#define regDP_DTO3_MODULO 0x008e 145#define regDP_DTO3_MODULO_BASE_IDX 1 146#define regOTG3_PHYPLL_PIXEL_RATE_CNTL 0x008f 147#define regOTG3_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1 148#define regDPPCLK_CGTT_BLK_CTRL_REG 0x0098 149#define regDPPCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1 150#define regDPPCLK0_DTO_PARAM 0x0099 151#define regDPPCLK0_DTO_PARAM_BASE_IDX 1 152#define regDPPCLK1_DTO_PARAM 0x009a 153#define regDPPCLK1_DTO_PARAM_BASE_IDX 1 154#define regDPPCLK2_DTO_PARAM 0x009b 155#define regDPPCLK2_DTO_PARAM_BASE_IDX 1 156#define regDPPCLK3_DTO_PARAM 0x009c 157#define regDPPCLK3_DTO_PARAM_BASE_IDX 1 158#define regDCCG_CAC_STATUS2 0x009f 159#define regDCCG_CAC_STATUS2_BASE_IDX 1 160#define regSYMCLKA_CLOCK_ENABLE 0x00a0 161#define regSYMCLKA_CLOCK_ENABLE_BASE_IDX 1 162#define regSYMCLKB_CLOCK_ENABLE 0x00a1 163#define regSYMCLKB_CLOCK_ENABLE_BASE_IDX 1 164#define regSYMCLKC_CLOCK_ENABLE 0x00a2 165#define regSYMCLKC_CLOCK_ENABLE_BASE_IDX 1 166#define regSYMCLKD_CLOCK_ENABLE 0x00a3 167#define regSYMCLKD_CLOCK_ENABLE_BASE_IDX 1 168#define regSYMCLKE_CLOCK_ENABLE 0x00a4 169#define regSYMCLKE_CLOCK_ENABLE_BASE_IDX 1 170#define regDCCG_SOFT_RESET 0x00a6 171#define regDCCG_SOFT_RESET_BASE_IDX 1 172#define regDSCCLK_DTO_CTRL 0x00a7 173#define regDSCCLK_DTO_CTRL_BASE_IDX 1 174#define regDCCG_AUDIO_DTO_SOURCE 0x00ab 175#define regDCCG_AUDIO_DTO_SOURCE_BASE_IDX 1 176#define regDCCG_AUDIO_DTO0_PHASE 0x00ac 177#define regDCCG_AUDIO_DTO0_PHASE_BASE_IDX 1 178#define regDCCG_AUDIO_DTO0_MODULE 0x00ad 179#define regDCCG_AUDIO_DTO0_MODULE_BASE_IDX 1 180#define regDCCG_AUDIO_DTO1_PHASE 0x00ae 181#define regDCCG_AUDIO_DTO1_PHASE_BASE_IDX 1 182#define regDCCG_AUDIO_DTO1_MODULE 0x00af 183#define regDCCG_AUDIO_DTO1_MODULE_BASE_IDX 1 184#define regDCCG_VSYNC_OTG0_LATCH_VALUE 0x00b0 185#define regDCCG_VSYNC_OTG0_LATCH_VALUE_BASE_IDX 1 186#define regDCCG_VSYNC_OTG1_LATCH_VALUE 0x00b1 187#define regDCCG_VSYNC_OTG1_LATCH_VALUE_BASE_IDX 1 188#define regDCCG_VSYNC_OTG2_LATCH_VALUE 0x00b2 189#define regDCCG_VSYNC_OTG2_LATCH_VALUE_BASE_IDX 1 190#define regDCCG_VSYNC_OTG3_LATCH_VALUE 0x00b3 191#define regDCCG_VSYNC_OTG3_LATCH_VALUE_BASE_IDX 1 192#define regDCCG_VSYNC_OTG4_LATCH_VALUE 0x00b4 193#define regDCCG_VSYNC_OTG4_LATCH_VALUE_BASE_IDX 1 194#define regDCCG_VSYNC_OTG5_LATCH_VALUE 0x00b5 195#define regDCCG_VSYNC_OTG5_LATCH_VALUE_BASE_IDX 1 196#define regDPPCLK_DTO_CTRL 0x00b6 197#define regDPPCLK_DTO_CTRL_BASE_IDX 1 198#define regDCCG_VSYNC_CNT_CTRL 0x00b8 199#define regDCCG_VSYNC_CNT_CTRL_BASE_IDX 1 200#define regDCCG_VSYNC_CNT_INT_CTRL 0x00b9 201#define regDCCG_VSYNC_CNT_INT_CTRL_BASE_IDX 1 202#define regFORCE_SYMCLK_DISABLE 0x00ba 203#define regFORCE_SYMCLK_DISABLE_BASE_IDX 1 204#define regDCCG_TEST_CLK_SEL 0x00be 205#define regDCCG_TEST_CLK_SEL_BASE_IDX 1 206#define regDTBCLK_DTO0_PHASE 0x0018 207#define regDTBCLK_DTO0_PHASE_BASE_IDX 2 208#define regDTBCLK_DTO1_PHASE 0x0019 209#define regDTBCLK_DTO1_PHASE_BASE_IDX 2 210#define regDTBCLK_DTO2_PHASE 0x001a 211#define regDTBCLK_DTO2_PHASE_BASE_IDX 2 212#define regDTBCLK_DTO3_PHASE 0x001b 213#define regDTBCLK_DTO3_PHASE_BASE_IDX 2 214#define regDTBCLK_DTO0_MODULO 0x001f 215#define regDTBCLK_DTO0_MODULO_BASE_IDX 2 216#define regDTBCLK_DTO1_MODULO 0x0020 217#define regDTBCLK_DTO1_MODULO_BASE_IDX 2 218#define regDTBCLK_DTO2_MODULO 0x0021 219#define regDTBCLK_DTO2_MODULO_BASE_IDX 2 220#define regDTBCLK_DTO3_MODULO 0x0022 221#define regDTBCLK_DTO3_MODULO_BASE_IDX 2 222#define regHDMICHARCLK0_CLOCK_CNTL 0x004a 223#define regHDMICHARCLK0_CLOCK_CNTL_BASE_IDX 2 224#define regPHYASYMCLK_CLOCK_CNTL 0x0052 225#define regPHYASYMCLK_CLOCK_CNTL_BASE_IDX 2 226#define regPHYBSYMCLK_CLOCK_CNTL 0x0053 227#define regPHYBSYMCLK_CLOCK_CNTL_BASE_IDX 2 228#define regPHYCSYMCLK_CLOCK_CNTL 0x0054 229#define regPHYCSYMCLK_CLOCK_CNTL_BASE_IDX 2 230#define regPHYDSYMCLK_CLOCK_CNTL 0x0055 231#define regPHYDSYMCLK_CLOCK_CNTL_BASE_IDX 2 232#define regPHYESYMCLK_CLOCK_CNTL 0x0056 233#define regPHYESYMCLK_CLOCK_CNTL_BASE_IDX 2 234#define regHDMISTREAMCLK_CNTL 0x0059 235#define regHDMISTREAMCLK_CNTL_BASE_IDX 2 236#define regDCCG_GATE_DISABLE_CNTL3 0x005a 237#define regDCCG_GATE_DISABLE_CNTL3_BASE_IDX 2 238#define regHDMISTREAMCLK0_DTO_PARAM 0x005b 239#define regHDMISTREAMCLK0_DTO_PARAM_BASE_IDX 2 240#define regDCCG_AUDIO_DTBCLK_DTO_PHASE 0x0061 241#define regDCCG_AUDIO_DTBCLK_DTO_PHASE_BASE_IDX 2 242#define regDCCG_AUDIO_DTBCLK_DTO_MODULO 0x0062 243#define regDCCG_AUDIO_DTBCLK_DTO_MODULO_BASE_IDX 2 244#define regDTBCLK_DTO_DBUF_EN 0x0063 245#define regDTBCLK_DTO_DBUF_EN_BASE_IDX 2 246#define regDMCUBCLK_CNTL 0x0067 247#define regDMCUBCLK_CNTL_BASE_IDX 2 248 249 250// addressBlock: dcn_dc_dmu_rbbmif_dispdec 251// base address: 0x0 252#define regRBBMIF_TIMEOUT 0x017f 253#define regRBBMIF_TIMEOUT_BASE_IDX 2 254#define regRBBMIF_STATUS 0x0180 255#define regRBBMIF_STATUS_BASE_IDX 2 256#define regRBBMIF_STATUS_2 0x0181 257#define regRBBMIF_STATUS_2_BASE_IDX 2 258#define regRBBMIF_INT_STATUS 0x0182 259#define regRBBMIF_INT_STATUS_BASE_IDX 2 260#define regRBBMIF_TIMEOUT_DIS 0x0183 261#define regRBBMIF_TIMEOUT_DIS_BASE_IDX 2 262#define regRBBMIF_TIMEOUT_DIS_2 0x0184 263#define regRBBMIF_TIMEOUT_DIS_2_BASE_IDX 2 264#define regRBBMIF_STATUS_FLAG 0x0185 265#define regRBBMIF_STATUS_FLAG_BASE_IDX 2 266 267 268// addressBlock: dcn_dc_dmu_ihc_dispdec 269// base address: 0x0 270#define regDC_GPU_TIMER_START_POSITION_V_UPDATE 0x0126 271#define regDC_GPU_TIMER_START_POSITION_V_UPDATE_BASE_IDX 2 272#define regDC_GPU_TIMER_START_POSITION_VSTARTUP 0x0127 273#define regDC_GPU_TIMER_START_POSITION_VSTARTUP_BASE_IDX 2 274#define regDC_GPU_TIMER_READ 0x0128 275#define regDC_GPU_TIMER_READ_BASE_IDX 2 276#define regDC_GPU_TIMER_READ_CNTL 0x0129 277#define regDC_GPU_TIMER_READ_CNTL_BASE_IDX 2 278#define regDISP_INTERRUPT_STATUS 0x012a 279#define regDISP_INTERRUPT_STATUS_BASE_IDX 2 280#define regDISP_INTERRUPT_STATUS_CONTINUE 0x012b 281#define regDISP_INTERRUPT_STATUS_CONTINUE_BASE_IDX 2 282#define regDISP_INTERRUPT_STATUS_CONTINUE2 0x012c 283#define regDISP_INTERRUPT_STATUS_CONTINUE2_BASE_IDX 2 284#define regDISP_INTERRUPT_STATUS_CONTINUE3 0x012d 285#define regDISP_INTERRUPT_STATUS_CONTINUE3_BASE_IDX 2 286#define regDISP_INTERRUPT_STATUS_CONTINUE4 0x012e 287#define regDISP_INTERRUPT_STATUS_CONTINUE4_BASE_IDX 2 288#define regDISP_INTERRUPT_STATUS_CONTINUE5 0x012f 289#define regDISP_INTERRUPT_STATUS_CONTINUE5_BASE_IDX 2 290#define regDISP_INTERRUPT_STATUS_CONTINUE6 0x0130 291#define regDISP_INTERRUPT_STATUS_CONTINUE6_BASE_IDX 2 292#define regDISP_INTERRUPT_STATUS_CONTINUE7 0x0131 293#define regDISP_INTERRUPT_STATUS_CONTINUE7_BASE_IDX 2 294#define regDISP_INTERRUPT_STATUS_CONTINUE8 0x0132 295#define regDISP_INTERRUPT_STATUS_CONTINUE8_BASE_IDX 2 296#define regDISP_INTERRUPT_STATUS_CONTINUE9 0x0133 297#define regDISP_INTERRUPT_STATUS_CONTINUE9_BASE_IDX 2 298#define regDISP_INTERRUPT_STATUS_CONTINUE10 0x0134 299#define regDISP_INTERRUPT_STATUS_CONTINUE10_BASE_IDX 2 300#define regDISP_INTERRUPT_STATUS_CONTINUE11 0x0135 301#define regDISP_INTERRUPT_STATUS_CONTINUE11_BASE_IDX 2 302#define regDISP_INTERRUPT_STATUS_CONTINUE12 0x0136 303#define regDISP_INTERRUPT_STATUS_CONTINUE12_BASE_IDX 2 304#define regDISP_INTERRUPT_STATUS_CONTINUE13 0x0137 305#define regDISP_INTERRUPT_STATUS_CONTINUE13_BASE_IDX 2 306#define regDISP_INTERRUPT_STATUS_CONTINUE14 0x0138 307#define regDISP_INTERRUPT_STATUS_CONTINUE14_BASE_IDX 2 308#define regDISP_INTERRUPT_STATUS_CONTINUE15 0x0139 309#define regDISP_INTERRUPT_STATUS_CONTINUE15_BASE_IDX 2 310#define regDISP_INTERRUPT_STATUS_CONTINUE16 0x013a 311#define regDISP_INTERRUPT_STATUS_CONTINUE16_BASE_IDX 2 312#define regDISP_INTERRUPT_STATUS_CONTINUE17 0x013b 313#define regDISP_INTERRUPT_STATUS_CONTINUE17_BASE_IDX 2 314#define regDISP_INTERRUPT_STATUS_CONTINUE18 0x013c 315#define regDISP_INTERRUPT_STATUS_CONTINUE18_BASE_IDX 2 316#define regDISP_INTERRUPT_STATUS_CONTINUE19 0x013d 317#define regDISP_INTERRUPT_STATUS_CONTINUE19_BASE_IDX 2 318#define regDISP_INTERRUPT_STATUS_CONTINUE20 0x013e 319#define regDISP_INTERRUPT_STATUS_CONTINUE20_BASE_IDX 2 320#define regDISP_INTERRUPT_STATUS_CONTINUE21 0x013f 321#define regDISP_INTERRUPT_STATUS_CONTINUE21_BASE_IDX 2 322#define regDISP_INTERRUPT_STATUS_CONTINUE22 0x0140 323#define regDISP_INTERRUPT_STATUS_CONTINUE22_BASE_IDX 2 324#define regDC_GPU_TIMER_START_POSITION_VREADY 0x0141 325#define regDC_GPU_TIMER_START_POSITION_VREADY_BASE_IDX 2 326#define regDC_GPU_TIMER_START_POSITION_FLIP 0x0142 327#define regDC_GPU_TIMER_START_POSITION_FLIP_BASE_IDX 2 328#define regDC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK 0x0143 329#define regDC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK_BASE_IDX 2 330#define regDC_GPU_TIMER_START_POSITION_FLIP_AWAY 0x0144 331#define regDC_GPU_TIMER_START_POSITION_FLIP_AWAY_BASE_IDX 2 332#define regDISP_INTERRUPT_STATUS_CONTINUE23 0x0145 333#define regDISP_INTERRUPT_STATUS_CONTINUE23_BASE_IDX 2 334#define regDISP_INTERRUPT_STATUS_CONTINUE24 0x0146 335#define regDISP_INTERRUPT_STATUS_CONTINUE24_BASE_IDX 2 336#define regDISP_INTERRUPT_STATUS_CONTINUE25 0x0147 337#define regDISP_INTERRUPT_STATUS_CONTINUE25_BASE_IDX 2 338#define regDCCG_INTERRUPT_DEST 0x0148 339#define regDCCG_INTERRUPT_DEST_BASE_IDX 2 340#define regDMU_INTERRUPT_DEST 0x0149 341#define regDMU_INTERRUPT_DEST_BASE_IDX 2 342#define regDMU_INTERRUPT_DEST2 0x014a 343#define regDMU_INTERRUPT_DEST2_BASE_IDX 2 344#define regDCPG_INTERRUPT_DEST 0x014b 345#define regDCPG_INTERRUPT_DEST_BASE_IDX 2 346#define regDCPG_INTERRUPT_DEST2 0x014c 347#define regDCPG_INTERRUPT_DEST2_BASE_IDX 2 348#define regMMHUBBUB_INTERRUPT_DEST 0x014d 349#define regMMHUBBUB_INTERRUPT_DEST_BASE_IDX 2 350#define regWB_INTERRUPT_DEST 0x014e 351#define regWB_INTERRUPT_DEST_BASE_IDX 2 352#define regDCHUB_INTERRUPT_DEST 0x014f 353#define regDCHUB_INTERRUPT_DEST_BASE_IDX 2 354#define regDCHUB_PERFCOUNTER_INTERRUPT_DEST 0x0150 355#define regDCHUB_PERFCOUNTER_INTERRUPT_DEST_BASE_IDX 2 356#define regDCHUB_INTERRUPT_DEST2 0x0151 357#define regDCHUB_INTERRUPT_DEST2_BASE_IDX 2 358#define regDPP_PERFCOUNTER_INTERRUPT_DEST 0x0152 359#define regDPP_PERFCOUNTER_INTERRUPT_DEST_BASE_IDX 2 360#define regMPC_INTERRUPT_DEST 0x0153 361#define regMPC_INTERRUPT_DEST_BASE_IDX 2 362#define regOPP_INTERRUPT_DEST 0x0154 363#define regOPP_INTERRUPT_DEST_BASE_IDX 2 364#define regOPTC_INTERRUPT_DEST 0x0155 365#define regOPTC_INTERRUPT_DEST_BASE_IDX 2 366#define regOTG0_INTERRUPT_DEST 0x0156 367#define regOTG0_INTERRUPT_DEST_BASE_IDX 2 368#define regOTG1_INTERRUPT_DEST 0x0157 369#define regOTG1_INTERRUPT_DEST_BASE_IDX 2 370#define regOTG2_INTERRUPT_DEST 0x0158 371#define regOTG2_INTERRUPT_DEST_BASE_IDX 2 372#define regOTG3_INTERRUPT_DEST 0x0159 373#define regOTG3_INTERRUPT_DEST_BASE_IDX 2 374#define regOTG4_INTERRUPT_DEST 0x015a 375#define regOTG4_INTERRUPT_DEST_BASE_IDX 2 376#define regOTG5_INTERRUPT_DEST 0x015b 377#define regOTG5_INTERRUPT_DEST_BASE_IDX 2 378#define regDIG_INTERRUPT_DEST 0x015c 379#define regDIG_INTERRUPT_DEST_BASE_IDX 2 380#define regI2C_DDC_HPD_INTERRUPT_DEST 0x015d 381#define regI2C_DDC_HPD_INTERRUPT_DEST_BASE_IDX 2 382#define regDIO_INTERRUPT_DEST 0x015f 383#define regDIO_INTERRUPT_DEST_BASE_IDX 2 384#define regDCIO_INTERRUPT_DEST 0x0160 385#define regDCIO_INTERRUPT_DEST_BASE_IDX 2 386#define regHPD_INTERRUPT_DEST 0x0161 387#define regHPD_INTERRUPT_DEST_BASE_IDX 2 388#define regAZ_INTERRUPT_DEST 0x0162 389#define regAZ_INTERRUPT_DEST_BASE_IDX 2 390#define regAUX_INTERRUPT_DEST 0x0163 391#define regAUX_INTERRUPT_DEST_BASE_IDX 2 392#define regDSC_INTERRUPT_DEST 0x0164 393#define regDSC_INTERRUPT_DEST_BASE_IDX 2 394#define regHPO_INTERRUPT_DEST 0x0165 395#define regHPO_INTERRUPT_DEST_BASE_IDX 2 396 397 398// addressBlock: dcn_dc_dmu_dmu_misc_dispdec 399// base address: 0x0 400#define regCC_DC_PIPE_DIS 0x00ca 401#define regCC_DC_PIPE_DIS_BASE_IDX 2 402#define regDMU_CLK_CNTL 0x00cb 403#define regDMU_CLK_CNTL_BASE_IDX 2 404#define regDMCUB_SMU_INTERRUPT_CNTL 0x00cd 405#define regDMCUB_SMU_INTERRUPT_CNTL_BASE_IDX 2 406#define regSMU_INTERRUPT_CONTROL 0x00ce 407#define regSMU_INTERRUPT_CONTROL_BASE_IDX 2 408#define regDMU_MISC_ALLOW_DS_FORCE 0x00d6 409#define regDMU_MISC_ALLOW_DS_FORCE_BASE_IDX 2 410 411 412// addressBlock: dcn_dc_dmu_dc_pg_dispdec 413// base address: 0x0 414#define regDOMAIN0_PG_CONFIG 0x0080 415#define regDOMAIN0_PG_CONFIG_BASE_IDX 2 416#define regDOMAIN0_PG_STATUS 0x0081 417#define regDOMAIN0_PG_STATUS_BASE_IDX 2 418#define regDOMAIN1_PG_CONFIG 0x0082 419#define regDOMAIN1_PG_CONFIG_BASE_IDX 2 420#define regDOMAIN1_PG_STATUS 0x0083 421#define regDOMAIN1_PG_STATUS_BASE_IDX 2 422#define regDOMAIN2_PG_CONFIG 0x0084 423#define regDOMAIN2_PG_CONFIG_BASE_IDX 2 424#define regDOMAIN2_PG_STATUS 0x0085 425#define regDOMAIN2_PG_STATUS_BASE_IDX 2 426#define regDOMAIN3_PG_CONFIG 0x0086 427#define regDOMAIN3_PG_CONFIG_BASE_IDX 2 428#define regDOMAIN3_PG_STATUS 0x0087 429#define regDOMAIN3_PG_STATUS_BASE_IDX 2 430#define regDOMAIN16_PG_CONFIG 0x0089 431#define regDOMAIN16_PG_CONFIG_BASE_IDX 2 432#define regDOMAIN16_PG_STATUS 0x008a 433#define regDOMAIN16_PG_STATUS_BASE_IDX 2 434#define regDOMAIN17_PG_CONFIG 0x008b 435#define regDOMAIN17_PG_CONFIG_BASE_IDX 2 436#define regDOMAIN17_PG_STATUS 0x008c 437#define regDOMAIN17_PG_STATUS_BASE_IDX 2 438#define regDOMAIN18_PG_CONFIG 0x008d 439#define regDOMAIN18_PG_CONFIG_BASE_IDX 2 440#define regDOMAIN18_PG_STATUS 0x008e 441#define regDOMAIN18_PG_STATUS_BASE_IDX 2 442#define regDOMAIN19_PG_CONFIG 0x008f 443#define regDOMAIN19_PG_CONFIG_BASE_IDX 2 444#define regDOMAIN19_PG_STATUS 0x0090 445#define regDOMAIN19_PG_STATUS_BASE_IDX 2 446#define regDCPG_INTERRUPT_STATUS 0x0091 447#define regDCPG_INTERRUPT_STATUS_BASE_IDX 2 448#define regDCPG_INTERRUPT_STATUS_2 0x0092 449#define regDCPG_INTERRUPT_STATUS_2_BASE_IDX 2 450#define regDCPG_INTERRUPT_CONTROL_1 0x0093 451#define regDCPG_INTERRUPT_CONTROL_1_BASE_IDX 2 452#define regDCPG_INTERRUPT_CONTROL_3 0x0094 453#define regDCPG_INTERRUPT_CONTROL_3_BASE_IDX 2 454#define regDC_IP_REQUEST_CNTL 0x0095 455#define regDC_IP_REQUEST_CNTL_BASE_IDX 2 456 457 458// addressBlock: dcn_dc_dmu_dmcub_dispdec 459// base address: 0x0 460#define regDMCUB_REGION0_OFFSET 0x018e 461#define regDMCUB_REGION0_OFFSET_BASE_IDX 2 462#define regDMCUB_REGION0_OFFSET_HIGH 0x018f 463#define regDMCUB_REGION0_OFFSET_HIGH_BASE_IDX 2 464#define regDMCUB_REGION1_OFFSET 0x0190 465#define regDMCUB_REGION1_OFFSET_BASE_IDX 2 466#define regDMCUB_REGION1_OFFSET_HIGH 0x0191 467#define regDMCUB_REGION1_OFFSET_HIGH_BASE_IDX 2 468#define regDMCUB_REGION2_OFFSET 0x0192 469#define regDMCUB_REGION2_OFFSET_BASE_IDX 2 470#define regDMCUB_REGION2_OFFSET_HIGH 0x0193 471#define regDMCUB_REGION2_OFFSET_HIGH_BASE_IDX 2 472#define regDMCUB_REGION4_OFFSET 0x0196 473#define regDMCUB_REGION4_OFFSET_BASE_IDX 2 474#define regDMCUB_REGION4_OFFSET_HIGH 0x0197 475#define regDMCUB_REGION4_OFFSET_HIGH_BASE_IDX 2 476#define regDMCUB_REGION5_OFFSET 0x0198 477#define regDMCUB_REGION5_OFFSET_BASE_IDX 2 478#define regDMCUB_REGION5_OFFSET_HIGH 0x0199 479#define regDMCUB_REGION5_OFFSET_HIGH_BASE_IDX 2 480#define regDMCUB_REGION6_OFFSET 0x019a 481#define regDMCUB_REGION6_OFFSET_BASE_IDX 2 482#define regDMCUB_REGION6_OFFSET_HIGH 0x019b 483#define regDMCUB_REGION6_OFFSET_HIGH_BASE_IDX 2 484#define regDMCUB_REGION7_OFFSET 0x019c 485#define regDMCUB_REGION7_OFFSET_BASE_IDX 2 486#define regDMCUB_REGION7_OFFSET_HIGH 0x019d 487#define regDMCUB_REGION7_OFFSET_HIGH_BASE_IDX 2 488#define regDMCUB_REGION0_TOP_ADDRESS 0x019e 489#define regDMCUB_REGION0_TOP_ADDRESS_BASE_IDX 2 490#define regDMCUB_REGION1_TOP_ADDRESS 0x019f 491#define regDMCUB_REGION1_TOP_ADDRESS_BASE_IDX 2 492#define regDMCUB_REGION2_TOP_ADDRESS 0x01a0 493#define regDMCUB_REGION2_TOP_ADDRESS_BASE_IDX 2 494#define regDMCUB_REGION4_TOP_ADDRESS 0x01a1 495#define regDMCUB_REGION4_TOP_ADDRESS_BASE_IDX 2 496#define regDMCUB_REGION5_TOP_ADDRESS 0x01a2 497#define regDMCUB_REGION5_TOP_ADDRESS_BASE_IDX 2 498#define regDMCUB_REGION6_TOP_ADDRESS 0x01a3 499#define regDMCUB_REGION6_TOP_ADDRESS_BASE_IDX 2 500#define regDMCUB_REGION7_TOP_ADDRESS 0x01a4 501#define regDMCUB_REGION7_TOP_ADDRESS_BASE_IDX 2 502#define regDMCUB_REGION3_CW0_BASE_ADDRESS 0x01a5 503#define regDMCUB_REGION3_CW0_BASE_ADDRESS_BASE_IDX 2 504#define regDMCUB_REGION3_CW1_BASE_ADDRESS 0x01a6 505#define regDMCUB_REGION3_CW1_BASE_ADDRESS_BASE_IDX 2 506#define regDMCUB_REGION3_CW2_BASE_ADDRESS 0x01a7 507#define regDMCUB_REGION3_CW2_BASE_ADDRESS_BASE_IDX 2 508#define regDMCUB_REGION3_CW3_BASE_ADDRESS 0x01a8 509#define regDMCUB_REGION3_CW3_BASE_ADDRESS_BASE_IDX 2 510#define regDMCUB_REGION3_CW4_BASE_ADDRESS 0x01a9 511#define regDMCUB_REGION3_CW4_BASE_ADDRESS_BASE_IDX 2 512#define regDMCUB_REGION3_CW5_BASE_ADDRESS 0x01aa 513#define regDMCUB_REGION3_CW5_BASE_ADDRESS_BASE_IDX 2 514#define regDMCUB_REGION3_CW6_BASE_ADDRESS 0x01ab 515#define regDMCUB_REGION3_CW6_BASE_ADDRESS_BASE_IDX 2 516#define regDMCUB_REGION3_CW7_BASE_ADDRESS 0x01ac 517#define regDMCUB_REGION3_CW7_BASE_ADDRESS_BASE_IDX 2 518#define regDMCUB_REGION3_CW0_TOP_ADDRESS 0x01ad 519#define regDMCUB_REGION3_CW0_TOP_ADDRESS_BASE_IDX 2 520#define regDMCUB_REGION3_CW1_TOP_ADDRESS 0x01ae 521#define regDMCUB_REGION3_CW1_TOP_ADDRESS_BASE_IDX 2 522#define regDMCUB_REGION3_CW2_TOP_ADDRESS 0x01af 523#define regDMCUB_REGION3_CW2_TOP_ADDRESS_BASE_IDX 2 524#define regDMCUB_REGION3_CW3_TOP_ADDRESS 0x01b0 525#define regDMCUB_REGION3_CW3_TOP_ADDRESS_BASE_IDX 2 526#define regDMCUB_REGION3_CW4_TOP_ADDRESS 0x01b1 527#define regDMCUB_REGION3_CW4_TOP_ADDRESS_BASE_IDX 2 528#define regDMCUB_REGION3_CW5_TOP_ADDRESS 0x01b2 529#define regDMCUB_REGION3_CW5_TOP_ADDRESS_BASE_IDX 2 530#define regDMCUB_REGION3_CW6_TOP_ADDRESS 0x01b3 531#define regDMCUB_REGION3_CW6_TOP_ADDRESS_BASE_IDX 2 532#define regDMCUB_REGION3_CW7_TOP_ADDRESS 0x01b4 533#define regDMCUB_REGION3_CW7_TOP_ADDRESS_BASE_IDX 2 534#define regDMCUB_REGION3_CW0_OFFSET 0x01b5 535#define regDMCUB_REGION3_CW0_OFFSET_BASE_IDX 2 536#define regDMCUB_REGION3_CW0_OFFSET_HIGH 0x01b6 537#define regDMCUB_REGION3_CW0_OFFSET_HIGH_BASE_IDX 2 538#define regDMCUB_REGION3_CW1_OFFSET 0x01b7 539#define regDMCUB_REGION3_CW1_OFFSET_BASE_IDX 2 540#define regDMCUB_REGION3_CW1_OFFSET_HIGH 0x01b8 541#define regDMCUB_REGION3_CW1_OFFSET_HIGH_BASE_IDX 2 542#define regDMCUB_REGION3_CW2_OFFSET 0x01b9 543#define regDMCUB_REGION3_CW2_OFFSET_BASE_IDX 2 544#define regDMCUB_REGION3_CW2_OFFSET_HIGH 0x01ba 545#define regDMCUB_REGION3_CW2_OFFSET_HIGH_BASE_IDX 2 546#define regDMCUB_REGION3_CW3_OFFSET 0x01bb 547#define regDMCUB_REGION3_CW3_OFFSET_BASE_IDX 2 548#define regDMCUB_REGION3_CW3_OFFSET_HIGH 0x01bc 549#define regDMCUB_REGION3_CW3_OFFSET_HIGH_BASE_IDX 2 550#define regDMCUB_REGION3_CW4_OFFSET 0x01bd 551#define regDMCUB_REGION3_CW4_OFFSET_BASE_IDX 2 552#define regDMCUB_REGION3_CW4_OFFSET_HIGH 0x01be 553#define regDMCUB_REGION3_CW4_OFFSET_HIGH_BASE_IDX 2 554#define regDMCUB_REGION3_CW5_OFFSET 0x01bf 555#define regDMCUB_REGION3_CW5_OFFSET_BASE_IDX 2 556#define regDMCUB_REGION3_CW5_OFFSET_HIGH 0x01c0 557#define regDMCUB_REGION3_CW5_OFFSET_HIGH_BASE_IDX 2 558#define regDMCUB_REGION3_CW6_OFFSET 0x01c1 559#define regDMCUB_REGION3_CW6_OFFSET_BASE_IDX 2 560#define regDMCUB_REGION3_CW6_OFFSET_HIGH 0x01c2 561#define regDMCUB_REGION3_CW6_OFFSET_HIGH_BASE_IDX 2 562#define regDMCUB_REGION3_CW7_OFFSET 0x01c3 563#define regDMCUB_REGION3_CW7_OFFSET_BASE_IDX 2 564#define regDMCUB_REGION3_CW7_OFFSET_HIGH 0x01c4 565#define regDMCUB_REGION3_CW7_OFFSET_HIGH_BASE_IDX 2 566#define regDMCUB_INTERRUPT_ENABLE 0x01c5 567#define regDMCUB_INTERRUPT_ENABLE_BASE_IDX 2 568#define regDMCUB_INTERRUPT_ACK 0x01c6 569#define regDMCUB_INTERRUPT_ACK_BASE_IDX 2 570#define regDMCUB_INTERRUPT_STATUS 0x01c7 571#define regDMCUB_INTERRUPT_STATUS_BASE_IDX 2 572#define regDMCUB_INTERRUPT_TYPE 0x01c8 573#define regDMCUB_INTERRUPT_TYPE_BASE_IDX 2 574#define regDMCUB_EXT_INTERRUPT_STATUS 0x01c9 575#define regDMCUB_EXT_INTERRUPT_STATUS_BASE_IDX 2 576#define regDMCUB_EXT_INTERRUPT_CTXID 0x01ca 577#define regDMCUB_EXT_INTERRUPT_CTXID_BASE_IDX 2 578#define regDMCUB_EXT_INTERRUPT_ACK 0x01cb 579#define regDMCUB_EXT_INTERRUPT_ACK_BASE_IDX 2 580#define regDMCUB_INST_FETCH_FAULT_ADDR 0x01cc 581#define regDMCUB_INST_FETCH_FAULT_ADDR_BASE_IDX 2 582#define regDMCUB_DATA_WRITE_FAULT_ADDR 0x01cd 583#define regDMCUB_DATA_WRITE_FAULT_ADDR_BASE_IDX 2 584#define regDMCUB_SEC_CNTL 0x01ce 585#define regDMCUB_SEC_CNTL_BASE_IDX 2 586#define regDMCUB_MEM_CNTL 0x01cf 587#define regDMCUB_MEM_CNTL_BASE_IDX 2 588#define regDMCUB_INBOX0_BASE_ADDRESS 0x01d0 589#define regDMCUB_INBOX0_BASE_ADDRESS_BASE_IDX 2 590#define regDMCUB_INBOX0_SIZE 0x01d1 591#define regDMCUB_INBOX0_SIZE_BASE_IDX 2 592#define regDMCUB_INBOX0_WPTR 0x01d2 593#define regDMCUB_INBOX0_WPTR_BASE_IDX 2 594#define regDMCUB_INBOX0_RPTR 0x01d3 595#define regDMCUB_INBOX0_RPTR_BASE_IDX 2 596#define regDMCUB_INBOX1_BASE_ADDRESS 0x01d4 597#define regDMCUB_INBOX1_BASE_ADDRESS_BASE_IDX 2 598#define regDMCUB_INBOX1_SIZE 0x01d5 599#define regDMCUB_INBOX1_SIZE_BASE_IDX 2 600#define regDMCUB_INBOX1_WPTR 0x01d6 601#define regDMCUB_INBOX1_WPTR_BASE_IDX 2 602#define regDMCUB_INBOX1_RPTR 0x01d7 603#define regDMCUB_INBOX1_RPTR_BASE_IDX 2 604#define regDMCUB_OUTBOX0_BASE_ADDRESS 0x01d8 605#define regDMCUB_OUTBOX0_BASE_ADDRESS_BASE_IDX 2 606#define regDMCUB_OUTBOX0_SIZE 0x01d9 607#define regDMCUB_OUTBOX0_SIZE_BASE_IDX 2 608#define regDMCUB_OUTBOX0_WPTR 0x01da 609#define regDMCUB_OUTBOX0_WPTR_BASE_IDX 2 610#define regDMCUB_OUTBOX0_RPTR 0x01db 611#define regDMCUB_OUTBOX0_RPTR_BASE_IDX 2 612#define regDMCUB_OUTBOX1_BASE_ADDRESS 0x01dc 613#define regDMCUB_OUTBOX1_BASE_ADDRESS_BASE_IDX 2 614#define regDMCUB_OUTBOX1_SIZE 0x01dd 615#define regDMCUB_OUTBOX1_SIZE_BASE_IDX 2 616#define regDMCUB_OUTBOX1_WPTR 0x01de 617#define regDMCUB_OUTBOX1_WPTR_BASE_IDX 2 618#define regDMCUB_OUTBOX1_RPTR 0x01df 619#define regDMCUB_OUTBOX1_RPTR_BASE_IDX 2 620#define regDMCUB_TIMER_TRIGGER0 0x01e0 621#define regDMCUB_TIMER_TRIGGER0_BASE_IDX 2 622#define regDMCUB_TIMER_TRIGGER1 0x01e1 623#define regDMCUB_TIMER_TRIGGER1_BASE_IDX 2 624#define regDMCUB_TIMER_WINDOW 0x01e2 625#define regDMCUB_TIMER_WINDOW_BASE_IDX 2 626#define regDMCUB_SCRATCH0 0x01e3 627#define regDMCUB_SCRATCH0_BASE_IDX 2 628#define regDMCUB_SCRATCH1 0x01e4 629#define regDMCUB_SCRATCH1_BASE_IDX 2 630#define regDMCUB_SCRATCH2 0x01e5 631#define regDMCUB_SCRATCH2_BASE_IDX 2 632#define regDMCUB_SCRATCH3 0x01e6 633#define regDMCUB_SCRATCH3_BASE_IDX 2 634#define regDMCUB_SCRATCH4 0x01e7 635#define regDMCUB_SCRATCH4_BASE_IDX 2 636#define regDMCUB_SCRATCH5 0x01e8 637#define regDMCUB_SCRATCH5_BASE_IDX 2 638#define regDMCUB_SCRATCH6 0x01e9 639#define regDMCUB_SCRATCH6_BASE_IDX 2 640#define regDMCUB_SCRATCH7 0x01ea 641#define regDMCUB_SCRATCH7_BASE_IDX 2 642#define regDMCUB_SCRATCH8 0x01eb 643#define regDMCUB_SCRATCH8_BASE_IDX 2 644#define regDMCUB_SCRATCH9 0x01ec 645#define regDMCUB_SCRATCH9_BASE_IDX 2 646#define regDMCUB_SCRATCH10 0x01ed 647#define regDMCUB_SCRATCH10_BASE_IDX 2 648#define regDMCUB_SCRATCH11 0x01ee 649#define regDMCUB_SCRATCH11_BASE_IDX 2 650#define regDMCUB_SCRATCH12 0x01ef 651#define regDMCUB_SCRATCH12_BASE_IDX 2 652#define regDMCUB_SCRATCH13 0x01f0 653#define regDMCUB_SCRATCH13_BASE_IDX 2 654#define regDMCUB_SCRATCH14 0x01f1 655#define regDMCUB_SCRATCH14_BASE_IDX 2 656#define regDMCUB_SCRATCH15 0x01f2 657#define regDMCUB_SCRATCH15_BASE_IDX 2 658#define regDMCUB_SCRATCH16 0x01f3 659#define regDMCUB_SCRATCH16_BASE_IDX 2 660#define regDMCUB_SCRATCH17 0x01f4 661#define regDMCUB_SCRATCH17_BASE_IDX 2 662#define regDMCUB_SCRATCH18 0x01f5 663#define regDMCUB_SCRATCH18_BASE_IDX 2 664#define regDMCUB_CNTL 0x01f6 665#define regDMCUB_CNTL_BASE_IDX 2 666#define regDMCUB_GPINT_DATAIN0 0x01f7 667#define regDMCUB_GPINT_DATAIN0_BASE_IDX 2 668#define regDMCUB_GPINT_DATAIN1 0x01f8 669#define regDMCUB_GPINT_DATAIN1_BASE_IDX 2 670#define regDMCUB_GPINT_DATAOUT 0x01f9 671#define regDMCUB_GPINT_DATAOUT_BASE_IDX 2 672#define regDMCUB_UNDEFINED_ADDRESS_FAULT_ADDR 0x01fa 673#define regDMCUB_UNDEFINED_ADDRESS_FAULT_ADDR_BASE_IDX 2 674#define regDMCUB_LS_WAKE_INT_ENABLE 0x01fb 675#define regDMCUB_LS_WAKE_INT_ENABLE_BASE_IDX 2 676#define regDMCUB_MEM_PWR_CNTL 0x01fc 677#define regDMCUB_MEM_PWR_CNTL_BASE_IDX 2 678#define regDMCUB_TIMER_CURRENT 0x01fd 679#define regDMCUB_TIMER_CURRENT_BASE_IDX 2 680#define regDMCUB_PROC_ID 0x01ff 681#define regDMCUB_PROC_ID_BASE_IDX 2 682#define regDMCUB_CNTL2 0x0200 683#define regDMCUB_CNTL2_BASE_IDX 2 684#define regDMCUB_GPINT_DATAIN2 0x0215 685#define regDMCUB_GPINT_DATAIN2_BASE_IDX 2 686#define regDMCUB_GPINT_DATAIN3 0x0216 687#define regDMCUB_GPINT_DATAIN3_BASE_IDX 2 688#define regDMCUB_GPINT_DATAIN4 0x0217 689#define regDMCUB_GPINT_DATAIN4_BASE_IDX 2 690#define regDMCUB_GPINT_DATAIN5 0x0218 691#define regDMCUB_GPINT_DATAIN5_BASE_IDX 2 692#define regDMCUB_GPINT_DATAIN6 0x0219 693#define regDMCUB_GPINT_DATAIN6_BASE_IDX 2 694#define regDMCUB_REGION3_TMR_AXI_SPACE 0x021a 695#define regDMCUB_REGION3_TMR_AXI_SPACE_BASE_IDX 2 696#define regDMCUB_SCRATCH19 0x022e 697#define regDMCUB_SCRATCH19_BASE_IDX 2 698#define regDMCUB_SCRATCH20 0x022f 699#define regDMCUB_SCRATCH20_BASE_IDX 2 700#define regDMCUB_SCRATCH21 0x0230 701#define regDMCUB_SCRATCH21_BASE_IDX 2 702#define regDMCUB_SCRATCH22 0x0231 703#define regDMCUB_SCRATCH22_BASE_IDX 2 704#define regDMCUB_SCRATCH23 0x0232 705#define regDMCUB_SCRATCH23_BASE_IDX 2 706 707 708// addressBlock: dcn_dc_wb0_dispdec_dwb_top_dispdec 709// base address: 0x0 710#define regDWB_ENABLE_CLK_CTRL 0x3228 711#define regDWB_ENABLE_CLK_CTRL_BASE_IDX 2 712#define regDWB_MEM_PWR_CTRL 0x3229 713#define regDWB_MEM_PWR_CTRL_BASE_IDX 2 714#define regFC_MODE_CTRL 0x322a 715#define regFC_MODE_CTRL_BASE_IDX 2 716#define regFC_FLOW_CTRL 0x322b 717#define regFC_FLOW_CTRL_BASE_IDX 2 718#define regFC_WINDOW_START 0x322c 719#define regFC_WINDOW_START_BASE_IDX 2 720#define regFC_WINDOW_SIZE 0x322d 721#define regFC_WINDOW_SIZE_BASE_IDX 2 722#define regFC_SOURCE_SIZE 0x322e 723#define regFC_SOURCE_SIZE_BASE_IDX 2 724#define regDWB_UPDATE_CTRL 0x322f 725#define regDWB_UPDATE_CTRL_BASE_IDX 2 726#define regDWB_CRC_CTRL 0x3230 727#define regDWB_CRC_CTRL_BASE_IDX 2 728#define regDWB_CRC_MASK_R_G 0x3231 729#define regDWB_CRC_MASK_R_G_BASE_IDX 2 730#define regDWB_CRC_MASK_B_A 0x3232 731#define regDWB_CRC_MASK_B_A_BASE_IDX 2 732#define regDWB_CRC_VAL_R_G 0x3233 733#define regDWB_CRC_VAL_R_G_BASE_IDX 2 734#define regDWB_CRC_VAL_B_A 0x3234 735#define regDWB_CRC_VAL_B_A_BASE_IDX 2 736#define regDWB_OUT_CTRL 0x3235 737#define regDWB_OUT_CTRL_BASE_IDX 2 738#define regDWB_MMHUBBUB_BACKPRESSURE_CNT_EN 0x3236 739#define regDWB_MMHUBBUB_BACKPRESSURE_CNT_EN_BASE_IDX 2 740#define regDWB_MMHUBBUB_BACKPRESSURE_CNT 0x3237 741#define regDWB_MMHUBBUB_BACKPRESSURE_CNT_BASE_IDX 2 742#define regDWB_HOST_READ_CONTROL 0x3238 743#define regDWB_HOST_READ_CONTROL_BASE_IDX 2 744#define regDWB_OVERFLOW_STATUS 0x3239 745#define regDWB_OVERFLOW_STATUS_BASE_IDX 2 746#define regDWB_OVERFLOW_COUNTER 0x323a 747#define regDWB_OVERFLOW_COUNTER_BASE_IDX 2 748#define regDWB_SOFT_RESET 0x323b 749#define regDWB_SOFT_RESET_BASE_IDX 2 750 751 752// addressBlock: dcn_dc_wb0_dispdec_dwbcp_dispdec 753// base address: 0x0 754#define regDWB_HDR_MULT_COEF 0x3294 755#define regDWB_HDR_MULT_COEF_BASE_IDX 2 756#define regDWB_GAMUT_REMAP_MODE 0x3295 757#define regDWB_GAMUT_REMAP_MODE_BASE_IDX 2 758#define regDWB_GAMUT_REMAP_COEF_FORMAT 0x3296 759#define regDWB_GAMUT_REMAP_COEF_FORMAT_BASE_IDX 2 760#define regDWB_GAMUT_REMAPA_C11_C12 0x3297 761#define regDWB_GAMUT_REMAPA_C11_C12_BASE_IDX 2 762#define regDWB_GAMUT_REMAPA_C13_C14 0x3298 763#define regDWB_GAMUT_REMAPA_C13_C14_BASE_IDX 2 764#define regDWB_GAMUT_REMAPA_C21_C22 0x3299 765#define regDWB_GAMUT_REMAPA_C21_C22_BASE_IDX 2 766#define regDWB_GAMUT_REMAPA_C23_C24 0x329a 767#define regDWB_GAMUT_REMAPA_C23_C24_BASE_IDX 2 768#define regDWB_GAMUT_REMAPA_C31_C32 0x329b 769#define regDWB_GAMUT_REMAPA_C31_C32_BASE_IDX 2 770#define regDWB_GAMUT_REMAPA_C33_C34 0x329c 771#define regDWB_GAMUT_REMAPA_C33_C34_BASE_IDX 2 772#define regDWB_GAMUT_REMAPB_C11_C12 0x329d 773#define regDWB_GAMUT_REMAPB_C11_C12_BASE_IDX 2 774#define regDWB_GAMUT_REMAPB_C13_C14 0x329e 775#define regDWB_GAMUT_REMAPB_C13_C14_BASE_IDX 2 776#define regDWB_GAMUT_REMAPB_C21_C22 0x329f 777#define regDWB_GAMUT_REMAPB_C21_C22_BASE_IDX 2 778#define regDWB_GAMUT_REMAPB_C23_C24 0x32a0 779#define regDWB_GAMUT_REMAPB_C23_C24_BASE_IDX 2 780#define regDWB_GAMUT_REMAPB_C31_C32 0x32a1 781#define regDWB_GAMUT_REMAPB_C31_C32_BASE_IDX 2 782#define regDWB_GAMUT_REMAPB_C33_C34 0x32a2 783#define regDWB_GAMUT_REMAPB_C33_C34_BASE_IDX 2 784#define regDWB_OGAM_CONTROL 0x32a3 785#define regDWB_OGAM_CONTROL_BASE_IDX 2 786#define regDWB_OGAM_LUT_INDEX 0x32a4 787#define regDWB_OGAM_LUT_INDEX_BASE_IDX 2 788#define regDWB_OGAM_LUT_DATA 0x32a5 789#define regDWB_OGAM_LUT_DATA_BASE_IDX 2 790#define regDWB_OGAM_LUT_CONTROL 0x32a6 791#define regDWB_OGAM_LUT_CONTROL_BASE_IDX 2 792#define regDWB_OGAM_RAMA_START_CNTL_B 0x32a7 793#define regDWB_OGAM_RAMA_START_CNTL_B_BASE_IDX 2 794#define regDWB_OGAM_RAMA_START_CNTL_G 0x32a8 795#define regDWB_OGAM_RAMA_START_CNTL_G_BASE_IDX 2 796#define regDWB_OGAM_RAMA_START_CNTL_R 0x32a9 797#define regDWB_OGAM_RAMA_START_CNTL_R_BASE_IDX 2 798#define regDWB_OGAM_RAMA_START_BASE_CNTL_B 0x32aa 799#define regDWB_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX 2 800#define regDWB_OGAM_RAMA_START_SLOPE_CNTL_B 0x32ab 801#define regDWB_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX 2 802#define regDWB_OGAM_RAMA_START_BASE_CNTL_G 0x32ac 803#define regDWB_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX 2 804#define regDWB_OGAM_RAMA_START_SLOPE_CNTL_G 0x32ad 805#define regDWB_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2 806#define regDWB_OGAM_RAMA_START_BASE_CNTL_R 0x32ae 807#define regDWB_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX 2 808#define regDWB_OGAM_RAMA_START_SLOPE_CNTL_R 0x32af 809#define regDWB_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX 2 810#define regDWB_OGAM_RAMA_END_CNTL1_B 0x32b0 811#define regDWB_OGAM_RAMA_END_CNTL1_B_BASE_IDX 2 812#define regDWB_OGAM_RAMA_END_CNTL2_B 0x32b1 813#define regDWB_OGAM_RAMA_END_CNTL2_B_BASE_IDX 2 814#define regDWB_OGAM_RAMA_END_CNTL1_G 0x32b2 815#define regDWB_OGAM_RAMA_END_CNTL1_G_BASE_IDX 2 816#define regDWB_OGAM_RAMA_END_CNTL2_G 0x32b3 817#define regDWB_OGAM_RAMA_END_CNTL2_G_BASE_IDX 2 818#define regDWB_OGAM_RAMA_END_CNTL1_R 0x32b4 819#define regDWB_OGAM_RAMA_END_CNTL1_R_BASE_IDX 2 820#define regDWB_OGAM_RAMA_END_CNTL2_R 0x32b5 821#define regDWB_OGAM_RAMA_END_CNTL2_R_BASE_IDX 2 822#define regDWB_OGAM_RAMA_OFFSET_B 0x32b6 823#define regDWB_OGAM_RAMA_OFFSET_B_BASE_IDX 2 824#define regDWB_OGAM_RAMA_OFFSET_G 0x32b7 825#define regDWB_OGAM_RAMA_OFFSET_G_BASE_IDX 2 826#define regDWB_OGAM_RAMA_OFFSET_R 0x32b8 827#define regDWB_OGAM_RAMA_OFFSET_R_BASE_IDX 2 828#define regDWB_OGAM_RAMA_REGION_0_1 0x32b9 829#define regDWB_OGAM_RAMA_REGION_0_1_BASE_IDX 2 830#define regDWB_OGAM_RAMA_REGION_2_3 0x32ba 831#define regDWB_OGAM_RAMA_REGION_2_3_BASE_IDX 2 832#define regDWB_OGAM_RAMA_REGION_4_5 0x32bb 833#define regDWB_OGAM_RAMA_REGION_4_5_BASE_IDX 2 834#define regDWB_OGAM_RAMA_REGION_6_7 0x32bc 835#define regDWB_OGAM_RAMA_REGION_6_7_BASE_IDX 2 836#define regDWB_OGAM_RAMA_REGION_8_9 0x32bd 837#define regDWB_OGAM_RAMA_REGION_8_9_BASE_IDX 2 838#define regDWB_OGAM_RAMA_REGION_10_11 0x32be 839#define regDWB_OGAM_RAMA_REGION_10_11_BASE_IDX 2 840#define regDWB_OGAM_RAMA_REGION_12_13 0x32bf 841#define regDWB_OGAM_RAMA_REGION_12_13_BASE_IDX 2 842#define regDWB_OGAM_RAMA_REGION_14_15 0x32c0 843#define regDWB_OGAM_RAMA_REGION_14_15_BASE_IDX 2 844#define regDWB_OGAM_RAMA_REGION_16_17 0x32c1 845#define regDWB_OGAM_RAMA_REGION_16_17_BASE_IDX 2 846#define regDWB_OGAM_RAMA_REGION_18_19 0x32c2 847#define regDWB_OGAM_RAMA_REGION_18_19_BASE_IDX 2 848#define regDWB_OGAM_RAMA_REGION_20_21 0x32c3 849#define regDWB_OGAM_RAMA_REGION_20_21_BASE_IDX 2 850#define regDWB_OGAM_RAMA_REGION_22_23 0x32c4 851#define regDWB_OGAM_RAMA_REGION_22_23_BASE_IDX 2 852#define regDWB_OGAM_RAMA_REGION_24_25 0x32c5 853#define regDWB_OGAM_RAMA_REGION_24_25_BASE_IDX 2 854#define regDWB_OGAM_RAMA_REGION_26_27 0x32c6 855#define regDWB_OGAM_RAMA_REGION_26_27_BASE_IDX 2 856#define regDWB_OGAM_RAMA_REGION_28_29 0x32c7 857#define regDWB_OGAM_RAMA_REGION_28_29_BASE_IDX 2 858#define regDWB_OGAM_RAMA_REGION_30_31 0x32c8 859#define regDWB_OGAM_RAMA_REGION_30_31_BASE_IDX 2 860#define regDWB_OGAM_RAMA_REGION_32_33 0x32c9 861#define regDWB_OGAM_RAMA_REGION_32_33_BASE_IDX 2 862#define regDWB_OGAM_RAMB_START_CNTL_B 0x32ca 863#define regDWB_OGAM_RAMB_START_CNTL_B_BASE_IDX 2 864#define regDWB_OGAM_RAMB_START_CNTL_G 0x32cb 865#define regDWB_OGAM_RAMB_START_CNTL_G_BASE_IDX 2 866#define regDWB_OGAM_RAMB_START_CNTL_R 0x32cc 867#define regDWB_OGAM_RAMB_START_CNTL_R_BASE_IDX 2 868#define regDWB_OGAM_RAMB_START_BASE_CNTL_B 0x32cd 869#define regDWB_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX 2 870#define regDWB_OGAM_RAMB_START_SLOPE_CNTL_B 0x32ce 871#define regDWB_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX 2 872#define regDWB_OGAM_RAMB_START_BASE_CNTL_G 0x32cf 873#define regDWB_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX 2 874#define regDWB_OGAM_RAMB_START_SLOPE_CNTL_G 0x32d0 875#define regDWB_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX 2 876#define regDWB_OGAM_RAMB_START_BASE_CNTL_R 0x32d1 877#define regDWB_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX 2 878#define regDWB_OGAM_RAMB_START_SLOPE_CNTL_R 0x32d2 879#define regDWB_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX 2 880#define regDWB_OGAM_RAMB_END_CNTL1_B 0x32d3 881#define regDWB_OGAM_RAMB_END_CNTL1_B_BASE_IDX 2 882#define regDWB_OGAM_RAMB_END_CNTL2_B 0x32d4 883#define regDWB_OGAM_RAMB_END_CNTL2_B_BASE_IDX 2 884#define regDWB_OGAM_RAMB_END_CNTL1_G 0x32d5 885#define regDWB_OGAM_RAMB_END_CNTL1_G_BASE_IDX 2 886#define regDWB_OGAM_RAMB_END_CNTL2_G 0x32d6 887#define regDWB_OGAM_RAMB_END_CNTL2_G_BASE_IDX 2 888#define regDWB_OGAM_RAMB_END_CNTL1_R 0x32d7 889#define regDWB_OGAM_RAMB_END_CNTL1_R_BASE_IDX 2 890#define regDWB_OGAM_RAMB_END_CNTL2_R 0x32d8 891#define regDWB_OGAM_RAMB_END_CNTL2_R_BASE_IDX 2 892#define regDWB_OGAM_RAMB_OFFSET_B 0x32d9 893#define regDWB_OGAM_RAMB_OFFSET_B_BASE_IDX 2 894#define regDWB_OGAM_RAMB_OFFSET_G 0x32da 895#define regDWB_OGAM_RAMB_OFFSET_G_BASE_IDX 2 896#define regDWB_OGAM_RAMB_OFFSET_R 0x32db 897#define regDWB_OGAM_RAMB_OFFSET_R_BASE_IDX 2 898#define regDWB_OGAM_RAMB_REGION_0_1 0x32dc 899#define regDWB_OGAM_RAMB_REGION_0_1_BASE_IDX 2 900#define regDWB_OGAM_RAMB_REGION_2_3 0x32dd 901#define regDWB_OGAM_RAMB_REGION_2_3_BASE_IDX 2 902#define regDWB_OGAM_RAMB_REGION_4_5 0x32de 903#define regDWB_OGAM_RAMB_REGION_4_5_BASE_IDX 2 904#define regDWB_OGAM_RAMB_REGION_6_7 0x32df 905#define regDWB_OGAM_RAMB_REGION_6_7_BASE_IDX 2 906#define regDWB_OGAM_RAMB_REGION_8_9 0x32e0 907#define regDWB_OGAM_RAMB_REGION_8_9_BASE_IDX 2 908#define regDWB_OGAM_RAMB_REGION_10_11 0x32e1 909#define regDWB_OGAM_RAMB_REGION_10_11_BASE_IDX 2 910#define regDWB_OGAM_RAMB_REGION_12_13 0x32e2 911#define regDWB_OGAM_RAMB_REGION_12_13_BASE_IDX 2 912#define regDWB_OGAM_RAMB_REGION_14_15 0x32e3 913#define regDWB_OGAM_RAMB_REGION_14_15_BASE_IDX 2 914#define regDWB_OGAM_RAMB_REGION_16_17 0x32e4 915#define regDWB_OGAM_RAMB_REGION_16_17_BASE_IDX 2 916#define regDWB_OGAM_RAMB_REGION_18_19 0x32e5 917#define regDWB_OGAM_RAMB_REGION_18_19_BASE_IDX 2 918#define regDWB_OGAM_RAMB_REGION_20_21 0x32e6 919#define regDWB_OGAM_RAMB_REGION_20_21_BASE_IDX 2 920#define regDWB_OGAM_RAMB_REGION_22_23 0x32e7 921#define regDWB_OGAM_RAMB_REGION_22_23_BASE_IDX 2 922#define regDWB_OGAM_RAMB_REGION_24_25 0x32e8 923#define regDWB_OGAM_RAMB_REGION_24_25_BASE_IDX 2 924#define regDWB_OGAM_RAMB_REGION_26_27 0x32e9 925#define regDWB_OGAM_RAMB_REGION_26_27_BASE_IDX 2 926#define regDWB_OGAM_RAMB_REGION_28_29 0x32ea 927#define regDWB_OGAM_RAMB_REGION_28_29_BASE_IDX 2 928#define regDWB_OGAM_RAMB_REGION_30_31 0x32eb 929#define regDWB_OGAM_RAMB_REGION_30_31_BASE_IDX 2 930#define regDWB_OGAM_RAMB_REGION_32_33 0x32ec 931#define regDWB_OGAM_RAMB_REGION_32_33_BASE_IDX 2 932 933 934// addressBlock: dcn_dc_mmhubbub_vga_dispdec 935// base address: 0x0 936#define regVGA_MEM_WRITE_PAGE_ADDR 0x0000 937#define regVGA_MEM_WRITE_PAGE_ADDR_BASE_IDX 0 938#define regVGA_MEM_READ_PAGE_ADDR 0x0001 939#define regVGA_MEM_READ_PAGE_ADDR_BASE_IDX 0 940#define regVGA_RENDER_CONTROL 0x0000 941#define regVGA_RENDER_CONTROL_BASE_IDX 1 942#define regVGA_SEQUENCER_RESET_CONTROL 0x0001 943#define regVGA_SEQUENCER_RESET_CONTROL_BASE_IDX 1 944#define regVGA_MODE_CONTROL 0x0002 945#define regVGA_MODE_CONTROL_BASE_IDX 1 946#define regVGA_SURFACE_PITCH_SELECT 0x0003 947#define regVGA_SURFACE_PITCH_SELECT_BASE_IDX 1 948#define regVGA_MEMORY_BASE_ADDRESS 0x0004 949#define regVGA_MEMORY_BASE_ADDRESS_BASE_IDX 1 950#define regVGA_DISPBUF1_SURFACE_ADDR 0x0006 951#define regVGA_DISPBUF1_SURFACE_ADDR_BASE_IDX 1 952#define regVGA_DISPBUF2_SURFACE_ADDR 0x0008 953#define regVGA_DISPBUF2_SURFACE_ADDR_BASE_IDX 1 954#define regVGA_MEMORY_BASE_ADDRESS_HIGH 0x0009 955#define regVGA_MEMORY_BASE_ADDRESS_HIGH_BASE_IDX 1 956#define regVGA_HDP_CONTROL 0x000a 957#define regVGA_HDP_CONTROL_BASE_IDX 1 958#define regVGA_CACHE_CONTROL 0x000b 959#define regVGA_CACHE_CONTROL_BASE_IDX 1 960#define regD1VGA_CONTROL 0x000c 961#define regD1VGA_CONTROL_BASE_IDX 1 962#define regD2VGA_CONTROL 0x000e 963#define regD2VGA_CONTROL_BASE_IDX 1 964#define regVGA_STATUS 0x0010 965#define regVGA_STATUS_BASE_IDX 1 966#define regVGA_INTERRUPT_CONTROL 0x0011 967#define regVGA_INTERRUPT_CONTROL_BASE_IDX 1 968#define regVGA_STATUS_CLEAR 0x0012 969#define regVGA_STATUS_CLEAR_BASE_IDX 1 970#define regVGA_INTERRUPT_STATUS 0x0013 971#define regVGA_INTERRUPT_STATUS_BASE_IDX 1 972#define regVGA_MAIN_CONTROL 0x0014 973#define regVGA_MAIN_CONTROL_BASE_IDX 1 974#define regVGA_TEST_CONTROL 0x0015 975#define regVGA_TEST_CONTROL_BASE_IDX 1 976#define regVGA_QOS_CTRL 0x0018 977#define regVGA_QOS_CTRL_BASE_IDX 1 978#define regCRTC8_IDX 0x002d 979#define regCRTC8_IDX_BASE_IDX 1 980#define regCRTC8_DATA 0x002d 981#define regCRTC8_DATA_BASE_IDX 1 982#define regGENFC_WT 0x002e 983#define regGENFC_WT_BASE_IDX 1 984#define regGENS1 0x002e 985#define regGENS1_BASE_IDX 1 986#define regATTRDW 0x0030 987#define regATTRDW_BASE_IDX 1 988#define regATTRX 0x0030 989#define regATTRX_BASE_IDX 1 990#define regATTRDR 0x0030 991#define regATTRDR_BASE_IDX 1 992#define regGENMO_WT 0x0030 993#define regGENMO_WT_BASE_IDX 1 994#define regGENS0 0x0030 995#define regGENS0_BASE_IDX 1 996#define regGENENB 0x0030 997#define regGENENB_BASE_IDX 1 998#define regSEQ8_IDX 0x0031 999#define regSEQ8_IDX_BASE_IDX 1 1000#define regSEQ8_DATA 0x0031 1001#define regSEQ8_DATA_BASE_IDX 1 1002#define regDAC_MASK 0x0031 1003#define regDAC_MASK_BASE_IDX 1 1004#define regDAC_R_INDEX 0x0031 1005#define regDAC_R_INDEX_BASE_IDX 1 1006#define regDAC_W_INDEX 0x0032 1007#define regDAC_W_INDEX_BASE_IDX 1 1008#define regDAC_DATA 0x0032 1009#define regDAC_DATA_BASE_IDX 1 1010#define regGENFC_RD 0x0032 1011#define regGENFC_RD_BASE_IDX 1 1012#define regGENMO_RD 0x0033 1013#define regGENMO_RD_BASE_IDX 1 1014#define regGRPH8_IDX 0x0033 1015#define regGRPH8_IDX_BASE_IDX 1 1016#define regGRPH8_DATA 0x0033 1017#define regGRPH8_DATA_BASE_IDX 1 1018#define regCRTC8_IDX_1 0x0035 1019#define regCRTC8_IDX_1_BASE_IDX 1 1020#define regCRTC8_DATA_1 0x0035 1021#define regCRTC8_DATA_1_BASE_IDX 1 1022#define regGENFC_WT_1 0x0036 1023#define regGENFC_WT_1_BASE_IDX 1 1024#define regGENS1_1 0x0036 1025#define regGENS1_1_BASE_IDX 1 1026#define regD3VGA_CONTROL 0x0038 1027#define regD3VGA_CONTROL_BASE_IDX 1 1028#define regD4VGA_CONTROL 0x0039 1029#define regD4VGA_CONTROL_BASE_IDX 1 1030#define regD5VGA_CONTROL 0x003a 1031#define regD5VGA_CONTROL_BASE_IDX 1 1032#define regD6VGA_CONTROL 0x003b 1033#define regD6VGA_CONTROL_BASE_IDX 1 1034#define regVGA_SOURCE_SELECT 0x003c 1035#define regVGA_SOURCE_SELECT_BASE_IDX 1 1036 1037 1038// addressBlock: dcn_dc_mmhubbub_vgaif_dispdec 1039// base address: 0x0 1040#define regMCIF_CONTROL 0x034a 1041#define regMCIF_CONTROL_BASE_IDX 2 1042#define regMCIF_WRITE_COMBINE_CONTROL 0x034b 1043#define regMCIF_WRITE_COMBINE_CONTROL_BASE_IDX 2 1044#define regMCIF_PHASE0_OUTSTANDING_COUNTER 0x034e 1045#define regMCIF_PHASE0_OUTSTANDING_COUNTER_BASE_IDX 2 1046#define regMCIF_PHASE1_OUTSTANDING_COUNTER 0x034f 1047#define regMCIF_PHASE1_OUTSTANDING_COUNTER_BASE_IDX 2 1048#define regMCIF_PHASE2_OUTSTANDING_COUNTER 0x0350 1049#define regMCIF_PHASE2_OUTSTANDING_COUNTER_BASE_IDX 2 1050 1051 1052// addressBlock: dcn_dc_mmhubbub_mcif_wb0_dispdec 1053// base address: 0x0 1054#define regMCIF_WB_BUFMGR_SW_CONTROL 0x0272 1055#define regMCIF_WB_BUFMGR_SW_CONTROL_BASE_IDX 2 1056#define regMCIF_WB_BUFMGR_STATUS 0x0274 1057#define regMCIF_WB_BUFMGR_STATUS_BASE_IDX 2 1058#define regMCIF_WB_BUF_PITCH 0x0275 1059#define regMCIF_WB_BUF_PITCH_BASE_IDX 2 1060#define regMCIF_WB_BUF_1_STATUS 0x0276 1061#define regMCIF_WB_BUF_1_STATUS_BASE_IDX 2 1062#define regMCIF_WB_BUF_1_STATUS2 0x0277 1063#define regMCIF_WB_BUF_1_STATUS2_BASE_IDX 2 1064#define regMCIF_WB_BUF_2_STATUS 0x0278 1065#define regMCIF_WB_BUF_2_STATUS_BASE_IDX 2 1066#define regMCIF_WB_BUF_2_STATUS2 0x0279 1067#define regMCIF_WB_BUF_2_STATUS2_BASE_IDX 2 1068#define regMCIF_WB_BUF_3_STATUS 0x027a 1069#define regMCIF_WB_BUF_3_STATUS_BASE_IDX 2 1070#define regMCIF_WB_BUF_3_STATUS2 0x027b 1071#define regMCIF_WB_BUF_3_STATUS2_BASE_IDX 2 1072#define regMCIF_WB_BUF_4_STATUS 0x027c 1073#define regMCIF_WB_BUF_4_STATUS_BASE_IDX 2 1074#define regMCIF_WB_BUF_4_STATUS2 0x027d 1075#define regMCIF_WB_BUF_4_STATUS2_BASE_IDX 2 1076#define regMCIF_WB_ARBITRATION_CONTROL 0x027e 1077#define regMCIF_WB_ARBITRATION_CONTROL_BASE_IDX 2 1078#define regMCIF_WB_SCLK_CHANGE 0x027f 1079#define regMCIF_WB_SCLK_CHANGE_BASE_IDX 2 1080#define regMCIF_WB_TEST_DEBUG_INDEX 0x0280 1081#define regMCIF_WB_TEST_DEBUG_INDEX_BASE_IDX 2 1082#define regMCIF_WB_TEST_DEBUG_DATA 0x0281 1083#define regMCIF_WB_TEST_DEBUG_DATA_BASE_IDX 2 1084#define regMCIF_WB_BUF_1_ADDR_Y 0x0282 1085#define regMCIF_WB_BUF_1_ADDR_Y_BASE_IDX 2 1086#define regMCIF_WB_BUF_1_ADDR_C 0x0284 1087#define regMCIF_WB_BUF_1_ADDR_C_BASE_IDX 2 1088#define regMCIF_WB_BUF_2_ADDR_Y 0x0286 1089#define regMCIF_WB_BUF_2_ADDR_Y_BASE_IDX 2 1090#define regMCIF_WB_BUF_2_ADDR_C 0x0288 1091#define regMCIF_WB_BUF_2_ADDR_C_BASE_IDX 2 1092#define regMCIF_WB_BUF_3_ADDR_Y 0x028a 1093#define regMCIF_WB_BUF_3_ADDR_Y_BASE_IDX 2 1094#define regMCIF_WB_BUF_3_ADDR_C 0x028c 1095#define regMCIF_WB_BUF_3_ADDR_C_BASE_IDX 2 1096#define regMCIF_WB_BUF_4_ADDR_Y 0x028e 1097#define regMCIF_WB_BUF_4_ADDR_Y_BASE_IDX 2 1098#define regMCIF_WB_BUF_4_ADDR_C 0x0290 1099#define regMCIF_WB_BUF_4_ADDR_C_BASE_IDX 2 1100#define regMCIF_WB_BUFMGR_VCE_CONTROL 0x0292 1101#define regMCIF_WB_BUFMGR_VCE_CONTROL_BASE_IDX 2 1102#define regMCIF_WB_NB_PSTATE_CONTROL 0x0293 1103#define regMCIF_WB_NB_PSTATE_CONTROL_BASE_IDX 2 1104#define regMCIF_WB_CLOCK_GATER_CONTROL 0x0294 1105#define regMCIF_WB_CLOCK_GATER_CONTROL_BASE_IDX 2 1106#define regMCIF_WB_SELF_REFRESH_CONTROL 0x0296 1107#define regMCIF_WB_SELF_REFRESH_CONTROL_BASE_IDX 2 1108#define regMULTI_LEVEL_QOS_CTRL 0x0297 1109#define regMULTI_LEVEL_QOS_CTRL_BASE_IDX 2 1110#define regMCIF_WB_SECURITY_LEVEL 0x0298 1111#define regMCIF_WB_SECURITY_LEVEL_BASE_IDX 2 1112#define regMCIF_WB_BUF_LUMA_SIZE 0x0299 1113#define regMCIF_WB_BUF_LUMA_SIZE_BASE_IDX 2 1114#define regMCIF_WB_BUF_CHROMA_SIZE 0x029a 1115#define regMCIF_WB_BUF_CHROMA_SIZE_BASE_IDX 2 1116#define regMCIF_WB_BUF_1_ADDR_Y_HIGH 0x029b 1117#define regMCIF_WB_BUF_1_ADDR_Y_HIGH_BASE_IDX 2 1118#define regMCIF_WB_BUF_1_ADDR_C_HIGH 0x029c 1119#define regMCIF_WB_BUF_1_ADDR_C_HIGH_BASE_IDX 2 1120#define regMCIF_WB_BUF_2_ADDR_Y_HIGH 0x029d 1121#define regMCIF_WB_BUF_2_ADDR_Y_HIGH_BASE_IDX 2 1122#define regMCIF_WB_BUF_2_ADDR_C_HIGH 0x029e 1123#define regMCIF_WB_BUF_2_ADDR_C_HIGH_BASE_IDX 2 1124#define regMCIF_WB_BUF_3_ADDR_Y_HIGH 0x029f 1125#define regMCIF_WB_BUF_3_ADDR_Y_HIGH_BASE_IDX 2 1126#define regMCIF_WB_BUF_3_ADDR_C_HIGH 0x02a0 1127#define regMCIF_WB_BUF_3_ADDR_C_HIGH_BASE_IDX 2 1128#define regMCIF_WB_BUF_4_ADDR_Y_HIGH 0x02a1 1129#define regMCIF_WB_BUF_4_ADDR_Y_HIGH_BASE_IDX 2 1130#define regMCIF_WB_BUF_4_ADDR_C_HIGH 0x02a2 1131#define regMCIF_WB_BUF_4_ADDR_C_HIGH_BASE_IDX 2 1132#define regMCIF_WB_BUF_1_RESOLUTION 0x02a3 1133#define regMCIF_WB_BUF_1_RESOLUTION_BASE_IDX 2 1134#define regMCIF_WB_BUF_2_RESOLUTION 0x02a4 1135#define regMCIF_WB_BUF_2_RESOLUTION_BASE_IDX 2 1136#define regMCIF_WB_BUF_3_RESOLUTION 0x02a5 1137#define regMCIF_WB_BUF_3_RESOLUTION_BASE_IDX 2 1138#define regMCIF_WB_BUF_4_RESOLUTION 0x02a6 1139#define regMCIF_WB_BUF_4_RESOLUTION_BASE_IDX 2 1140#define regMCIF_WB_PSTATE_CHANGE_DURATION_VBI 0x02a7 1141#define regMCIF_WB_PSTATE_CHANGE_DURATION_VBI_BASE_IDX 2 1142#define regMCIF_WB_VMID_CONTROL 0x02a8 1143#define regMCIF_WB_VMID_CONTROL_BASE_IDX 2 1144#define regMCIF_WB_MIN_TTO 0x02a9 1145#define regMCIF_WB_MIN_TTO_BASE_IDX 2 1146 1147 1148// addressBlock: dcn_dc_mmhubbub_mmhubbub_dispdec 1149// base address: 0x0 1150#define regMCIF_WB_NB_PSTATE_LATENCY_WATERMARK 0x02aa 1151#define regMCIF_WB_NB_PSTATE_LATENCY_WATERMARK_BASE_IDX 2 1152#define regMCIF_WB_WATERMARK 0x02ab 1153#define regMCIF_WB_WATERMARK_BASE_IDX 2 1154#define regMMHUBBUB_WARMUP_CONFIG 0x02ac 1155#define regMMHUBBUB_WARMUP_CONFIG_BASE_IDX 2 1156#define regMMHUBBUB_WARMUP_CONTROL_STATUS 0x02ad 1157#define regMMHUBBUB_WARMUP_CONTROL_STATUS_BASE_IDX 2 1158#define regMMHUBBUB_WARMUP_BASE_ADDR_LOW 0x02ae 1159#define regMMHUBBUB_WARMUP_BASE_ADDR_LOW_BASE_IDX 2 1160#define regMMHUBBUB_WARMUP_BASE_ADDR_HIGH 0x02af 1161#define regMMHUBBUB_WARMUP_BASE_ADDR_HIGH_BASE_IDX 2 1162#define regMMHUBBUB_WARMUP_ADDR_REGION 0x02b0 1163#define regMMHUBBUB_WARMUP_ADDR_REGION_BASE_IDX 2 1164#define regMMHUBBUB_MIN_TTO 0x02b1 1165#define regMMHUBBUB_MIN_TTO_BASE_IDX 2 1166#define regMMHUBBUB_CTRL 0x0333 1167#define regMMHUBBUB_CTRL_BASE_IDX 2 1168#define regWBIF_SMU_WM_CONTROL 0x0334 1169#define regWBIF_SMU_WM_CONTROL_BASE_IDX 2 1170#define regWBIF0_MISC_CTRL 0x0335 1171#define regWBIF0_MISC_CTRL_BASE_IDX 2 1172#define regWBIF0_PHASE0_OUTSTANDING_COUNTER 0x0336 1173#define regWBIF0_PHASE0_OUTSTANDING_COUNTER_BASE_IDX 2 1174#define regWBIF0_PHASE1_OUTSTANDING_COUNTER 0x0337 1175#define regWBIF0_PHASE1_OUTSTANDING_COUNTER_BASE_IDX 2 1176#define regVGA_SRC_SPLIT_CNTL 0x033e 1177#define regVGA_SRC_SPLIT_CNTL_BASE_IDX 2 1178#define regMMHUBBUB_MEM_PWR_STATUS 0x033f 1179#define regMMHUBBUB_MEM_PWR_STATUS_BASE_IDX 2 1180#define regMMHUBBUB_MEM_PWR_CNTL 0x0340 1181#define regMMHUBBUB_MEM_PWR_CNTL_BASE_IDX 2 1182#define regMMHUBBUB_CLOCK_CNTL 0x0341 1183#define regMMHUBBUB_CLOCK_CNTL_BASE_IDX 2 1184#define regMMHUBBUB_SOFT_RESET 0x0342 1185#define regMMHUBBUB_SOFT_RESET_BASE_IDX 2 1186#define regDMU_IF_ERR_STATUS 0x0346 1187#define regDMU_IF_ERR_STATUS_BASE_IDX 2 1188#define regMMHUBBUB_CLIENT_UNIT_ID 0x0347 1189#define regMMHUBBUB_CLIENT_UNIT_ID_BASE_IDX 2 1190#define regMMHUBBUB_WARMUP_VMID_CONTROL 0x0349 1191#define regMMHUBBUB_WARMUP_VMID_CONTROL_BASE_IDX 2 1192 1193 1194// addressBlock: dcn_dc_hda_azf0controller_dispdec 1195// base address: 0x0 1196#define regAZALIA_CONTROLLER_CLOCK_GATING 0x03c2 1197#define regAZALIA_CONTROLLER_CLOCK_GATING_BASE_IDX 2 1198#define regAZALIA_AUDIO_DTO 0x03c3 1199#define regAZALIA_AUDIO_DTO_BASE_IDX 2 1200#define regAZALIA_AUDIO_DTO_CONTROL 0x03c4 1201#define regAZALIA_AUDIO_DTO_CONTROL_BASE_IDX 2 1202#define regAZALIA_SOCCLK_CONTROL 0x03c5 1203#define regAZALIA_SOCCLK_CONTROL_BASE_IDX 2 1204#define regAZALIA_UNDERFLOW_FILLER_SAMPLE 0x03c6 1205#define regAZALIA_UNDERFLOW_FILLER_SAMPLE_BASE_IDX 2 1206#define regAZALIA_DATA_DMA_CONTROL 0x03c7 1207#define regAZALIA_DATA_DMA_CONTROL_BASE_IDX 2 1208#define regAZALIA_BDL_DMA_CONTROL 0x03c8 1209#define regAZALIA_BDL_DMA_CONTROL_BASE_IDX 2 1210#define regAZALIA_RIRB_AND_DP_CONTROL 0x03c9 1211#define regAZALIA_RIRB_AND_DP_CONTROL_BASE_IDX 2 1212#define regAZALIA_CORB_DMA_CONTROL 0x03ca 1213#define regAZALIA_CORB_DMA_CONTROL_BASE_IDX 2 1214#define regAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER 0x03d1 1215#define regAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER_BASE_IDX 2 1216#define regAZALIA_CYCLIC_BUFFER_SYNC 0x03d2 1217#define regAZALIA_CYCLIC_BUFFER_SYNC_BASE_IDX 2 1218#define regAZALIA_GLOBAL_CAPABILITIES 0x03d3 1219#define regAZALIA_GLOBAL_CAPABILITIES_BASE_IDX 2 1220#define regAZALIA_OUTPUT_PAYLOAD_CAPABILITY 0x03d4 1221#define regAZALIA_OUTPUT_PAYLOAD_CAPABILITY_BASE_IDX 2 1222#define regAZALIA_OUTPUT_STREAM_ARBITER_CONTROL 0x03d5 1223#define regAZALIA_OUTPUT_STREAM_ARBITER_CONTROL_BASE_IDX 2 1224#define regAZALIA_INPUT_PAYLOAD_CAPABILITY 0x03d6 1225#define regAZALIA_INPUT_PAYLOAD_CAPABILITY_BASE_IDX 2 1226#define regAZALIA_INPUT_CRC0_CONTROL0 0x03d9 1227#define regAZALIA_INPUT_CRC0_CONTROL0_BASE_IDX 2 1228#define regAZALIA_INPUT_CRC0_CONTROL1 0x03da 1229#define regAZALIA_INPUT_CRC0_CONTROL1_BASE_IDX 2 1230#define regAZALIA_INPUT_CRC0_CONTROL2 0x03db 1231#define regAZALIA_INPUT_CRC0_CONTROL2_BASE_IDX 2 1232#define regAZALIA_INPUT_CRC0_CONTROL3 0x03dc 1233#define regAZALIA_INPUT_CRC0_CONTROL3_BASE_IDX 2 1234#define regAZALIA_INPUT_CRC0_RESULT 0x03dd 1235#define regAZALIA_INPUT_CRC0_RESULT_BASE_IDX 2 1236#define regAZALIA_INPUT_CRC1_CONTROL0 0x03de 1237#define regAZALIA_INPUT_CRC1_CONTROL0_BASE_IDX 2 1238#define regAZALIA_INPUT_CRC1_CONTROL1 0x03df 1239#define regAZALIA_INPUT_CRC1_CONTROL1_BASE_IDX 2 1240#define regAZALIA_INPUT_CRC1_CONTROL2 0x03e0 1241#define regAZALIA_INPUT_CRC1_CONTROL2_BASE_IDX 2 1242#define regAZALIA_INPUT_CRC1_CONTROL3 0x03e1 1243#define regAZALIA_INPUT_CRC1_CONTROL3_BASE_IDX 2 1244#define regAZALIA_INPUT_CRC1_RESULT 0x03e2 1245#define regAZALIA_INPUT_CRC1_RESULT_BASE_IDX 2 1246#define regAZALIA_CRC0_CONTROL0 0x03e3 1247#define regAZALIA_CRC0_CONTROL0_BASE_IDX 2 1248#define regAZALIA_CRC0_CONTROL1 0x03e4 1249#define regAZALIA_CRC0_CONTROL1_BASE_IDX 2 1250#define regAZALIA_CRC0_CONTROL2 0x03e5 1251#define regAZALIA_CRC0_CONTROL2_BASE_IDX 2 1252#define regAZALIA_CRC0_CONTROL3 0x03e6 1253#define regAZALIA_CRC0_CONTROL3_BASE_IDX 2 1254#define regAZALIA_CRC0_RESULT 0x03e7 1255#define regAZALIA_CRC0_RESULT_BASE_IDX 2 1256#define regAZALIA_CRC1_CONTROL0 0x03e8 1257#define regAZALIA_CRC1_CONTROL0_BASE_IDX 2 1258#define regAZALIA_CRC1_CONTROL1 0x03e9 1259#define regAZALIA_CRC1_CONTROL1_BASE_IDX 2 1260#define regAZALIA_CRC1_CONTROL2 0x03ea 1261#define regAZALIA_CRC1_CONTROL2_BASE_IDX 2 1262#define regAZALIA_CRC1_CONTROL3 0x03eb 1263#define regAZALIA_CRC1_CONTROL3_BASE_IDX 2 1264#define regAZALIA_CRC1_RESULT 0x03ec 1265#define regAZALIA_CRC1_RESULT_BASE_IDX 2 1266#define regAZALIA_MEM_PWR_CTRL 0x03ee 1267#define regAZALIA_MEM_PWR_CTRL_BASE_IDX 2 1268#define regAZALIA_MEM_PWR_STATUS 0x03ef 1269#define regAZALIA_MEM_PWR_STATUS_BASE_IDX 2 1270 1271 1272// addressBlock: dcn_dc_hda_azf0root_dispdec 1273// base address: 0x0 1274#define regAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID 0x0406 1275#define regAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_BASE_IDX 2 1276#define regAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID 0x0407 1277#define regAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID_BASE_IDX 2 1278#define regAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL 0x0408 1279#define regAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL_BASE_IDX 2 1280#define regAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL 0x0409 1281#define regAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL_BASE_IDX 2 1282#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE 0x040a 1283#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_BASE_IDX 2 1284#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES 0x040b 1285#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES_BASE_IDX 2 1286#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS 0x040c 1287#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_BASE_IDX 2 1288#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES 0x040d 1289#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES_BASE_IDX 2 1290#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE 0x040e 1291#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE_BASE_IDX 2 1292#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET 0x040f 1293#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET_BASE_IDX 2 1294#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID 0x0410 1295#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_BASE_IDX 2 1296#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION 0x0411 1297#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION_BASE_IDX 2 1298#define regCC_RCU_DC_AUDIO_PORT_CONNECTIVITY 0x0412 1299#define regCC_RCU_DC_AUDIO_PORT_CONNECTIVITY_BASE_IDX 2 1300#define regCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY 0x0413 1301#define regCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_BASE_IDX 2 1302#define regAZALIA_F0_GTC_GROUP_OFFSET0 0x0415 1303#define regAZALIA_F0_GTC_GROUP_OFFSET0_BASE_IDX 2 1304#define regAZALIA_F0_GTC_GROUP_OFFSET1 0x0416 1305#define regAZALIA_F0_GTC_GROUP_OFFSET1_BASE_IDX 2 1306#define regAZALIA_F0_GTC_GROUP_OFFSET2 0x0417 1307#define regAZALIA_F0_GTC_GROUP_OFFSET2_BASE_IDX 2 1308#define regAZALIA_F0_GTC_GROUP_OFFSET3 0x0418 1309#define regAZALIA_F0_GTC_GROUP_OFFSET3_BASE_IDX 2 1310#define regAZALIA_F0_GTC_GROUP_OFFSET4 0x0419 1311#define regAZALIA_F0_GTC_GROUP_OFFSET4_BASE_IDX 2 1312#define regAZALIA_F0_GTC_GROUP_OFFSET5 0x041a 1313#define regAZALIA_F0_GTC_GROUP_OFFSET5_BASE_IDX 2 1314#define regAZALIA_F0_GTC_GROUP_OFFSET6 0x041b 1315#define regAZALIA_F0_GTC_GROUP_OFFSET6_BASE_IDX 2 1316#define regREG_DC_AUDIO_PORT_CONNECTIVITY 0x041c 1317#define regREG_DC_AUDIO_PORT_CONNECTIVITY_BASE_IDX 2 1318#define regREG_DC_AUDIO_INPUT_PORT_CONNECTIVITY 0x041d 1319#define regREG_DC_AUDIO_INPUT_PORT_CONNECTIVITY_BASE_IDX 2 1320 1321 1322// addressBlock: dcn_dc_hda_az_misc_dispdec 1323// base address: 0x0 1324#define regAZ_CLOCK_CNTL 0x0372 1325#define regAZ_CLOCK_CNTL_BASE_IDX 2 1326 1327 1328// addressBlock: dcn_dc_hda_azf0stream0_dispdec 1329// base address: 0x0 1330#define regAZF0STREAM0_AZALIA_STREAM_INDEX 0x035e 1331#define regAZF0STREAM0_AZALIA_STREAM_INDEX_BASE_IDX 2 1332#define regAZF0STREAM0_AZALIA_STREAM_DATA 0x035f 1333#define regAZF0STREAM0_AZALIA_STREAM_DATA_BASE_IDX 2 1334 1335 1336// addressBlock: dcn_dc_hda_azf0stream1_dispdec 1337// base address: 0x8 1338#define regAZF0STREAM1_AZALIA_STREAM_INDEX 0x0360 1339#define regAZF0STREAM1_AZALIA_STREAM_INDEX_BASE_IDX 2 1340#define regAZF0STREAM1_AZALIA_STREAM_DATA 0x0361 1341#define regAZF0STREAM1_AZALIA_STREAM_DATA_BASE_IDX 2 1342 1343 1344// addressBlock: dcn_dc_hda_azf0stream2_dispdec 1345// base address: 0x10 1346#define regAZF0STREAM2_AZALIA_STREAM_INDEX 0x0362 1347#define regAZF0STREAM2_AZALIA_STREAM_INDEX_BASE_IDX 2 1348#define regAZF0STREAM2_AZALIA_STREAM_DATA 0x0363 1349#define regAZF0STREAM2_AZALIA_STREAM_DATA_BASE_IDX 2 1350 1351 1352// addressBlock: dcn_dc_hda_azf0stream3_dispdec 1353// base address: 0x18 1354#define regAZF0STREAM3_AZALIA_STREAM_INDEX 0x0364 1355#define regAZF0STREAM3_AZALIA_STREAM_INDEX_BASE_IDX 2 1356#define regAZF0STREAM3_AZALIA_STREAM_DATA 0x0365 1357#define regAZF0STREAM3_AZALIA_STREAM_DATA_BASE_IDX 2 1358 1359 1360// addressBlock: dcn_dc_hda_azf0stream4_dispdec 1361// base address: 0x20 1362#define regAZF0STREAM4_AZALIA_STREAM_INDEX 0x0366 1363#define regAZF0STREAM4_AZALIA_STREAM_INDEX_BASE_IDX 2 1364#define regAZF0STREAM4_AZALIA_STREAM_DATA 0x0367 1365#define regAZF0STREAM4_AZALIA_STREAM_DATA_BASE_IDX 2 1366 1367 1368// addressBlock: dcn_dc_hda_azf0stream5_dispdec 1369// base address: 0x28 1370#define regAZF0STREAM5_AZALIA_STREAM_INDEX 0x0368 1371#define regAZF0STREAM5_AZALIA_STREAM_INDEX_BASE_IDX 2 1372#define regAZF0STREAM5_AZALIA_STREAM_DATA 0x0369 1373#define regAZF0STREAM5_AZALIA_STREAM_DATA_BASE_IDX 2 1374 1375 1376// addressBlock: dcn_dc_hda_azf0stream6_dispdec 1377// base address: 0x30 1378#define regAZF0STREAM6_AZALIA_STREAM_INDEX 0x036a 1379#define regAZF0STREAM6_AZALIA_STREAM_INDEX_BASE_IDX 2 1380#define regAZF0STREAM6_AZALIA_STREAM_DATA 0x036b 1381#define regAZF0STREAM6_AZALIA_STREAM_DATA_BASE_IDX 2 1382 1383 1384// addressBlock: dcn_dc_hda_azf0stream7_dispdec 1385// base address: 0x38 1386#define regAZF0STREAM7_AZALIA_STREAM_INDEX 0x036c 1387#define regAZF0STREAM7_AZALIA_STREAM_INDEX_BASE_IDX 2 1388#define regAZF0STREAM7_AZALIA_STREAM_DATA 0x036d 1389#define regAZF0STREAM7_AZALIA_STREAM_DATA_BASE_IDX 2 1390 1391 1392// addressBlock: dcn_dc_hda_azf0stream8_dispdec 1393// base address: 0x320 1394#define regAZF0STREAM8_AZALIA_STREAM_INDEX 0x0426 1395#define regAZF0STREAM8_AZALIA_STREAM_INDEX_BASE_IDX 2 1396#define regAZF0STREAM8_AZALIA_STREAM_DATA 0x0427 1397#define regAZF0STREAM8_AZALIA_STREAM_DATA_BASE_IDX 2 1398 1399 1400// addressBlock: dcn_dc_hda_azf0stream9_dispdec 1401// base address: 0x328 1402#define regAZF0STREAM9_AZALIA_STREAM_INDEX 0x0428 1403#define regAZF0STREAM9_AZALIA_STREAM_INDEX_BASE_IDX 2 1404#define regAZF0STREAM9_AZALIA_STREAM_DATA 0x0429 1405#define regAZF0STREAM9_AZALIA_STREAM_DATA_BASE_IDX 2 1406 1407 1408// addressBlock: dcn_dc_hda_azf0stream10_dispdec 1409// base address: 0x330 1410#define regAZF0STREAM10_AZALIA_STREAM_INDEX 0x042a 1411#define regAZF0STREAM10_AZALIA_STREAM_INDEX_BASE_IDX 2 1412#define regAZF0STREAM10_AZALIA_STREAM_DATA 0x042b 1413#define regAZF0STREAM10_AZALIA_STREAM_DATA_BASE_IDX 2 1414 1415 1416// addressBlock: dcn_dc_hda_azf0stream11_dispdec 1417// base address: 0x338 1418#define regAZF0STREAM11_AZALIA_STREAM_INDEX 0x042c 1419#define regAZF0STREAM11_AZALIA_STREAM_INDEX_BASE_IDX 2 1420#define regAZF0STREAM11_AZALIA_STREAM_DATA 0x042d 1421#define regAZF0STREAM11_AZALIA_STREAM_DATA_BASE_IDX 2 1422 1423 1424// addressBlock: dcn_dc_hda_azf0stream12_dispdec 1425// base address: 0x340 1426#define regAZF0STREAM12_AZALIA_STREAM_INDEX 0x042e 1427#define regAZF0STREAM12_AZALIA_STREAM_INDEX_BASE_IDX 2 1428#define regAZF0STREAM12_AZALIA_STREAM_DATA 0x042f 1429#define regAZF0STREAM12_AZALIA_STREAM_DATA_BASE_IDX 2 1430 1431 1432// addressBlock: dcn_dc_hda_azf0stream13_dispdec 1433// base address: 0x348 1434#define regAZF0STREAM13_AZALIA_STREAM_INDEX 0x0430 1435#define regAZF0STREAM13_AZALIA_STREAM_INDEX_BASE_IDX 2 1436#define regAZF0STREAM13_AZALIA_STREAM_DATA 0x0431 1437#define regAZF0STREAM13_AZALIA_STREAM_DATA_BASE_IDX 2 1438 1439 1440// addressBlock: dcn_dc_hda_azf0stream14_dispdec 1441// base address: 0x350 1442#define regAZF0STREAM14_AZALIA_STREAM_INDEX 0x0432 1443#define regAZF0STREAM14_AZALIA_STREAM_INDEX_BASE_IDX 2 1444#define regAZF0STREAM14_AZALIA_STREAM_DATA 0x0433 1445#define regAZF0STREAM14_AZALIA_STREAM_DATA_BASE_IDX 2 1446 1447 1448// addressBlock: dcn_dc_hda_azf0stream15_dispdec 1449// base address: 0x358 1450#define regAZF0STREAM15_AZALIA_STREAM_INDEX 0x0434 1451#define regAZF0STREAM15_AZALIA_STREAM_INDEX_BASE_IDX 2 1452#define regAZF0STREAM15_AZALIA_STREAM_DATA 0x0435 1453#define regAZF0STREAM15_AZALIA_STREAM_DATA_BASE_IDX 2 1454 1455 1456// addressBlock: dcn_dc_hda_azf0endpoint0_dispdec 1457// base address: 0x0 1458#define regAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x0386 1459#define regAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 1460#define regAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA 0x0387 1461#define regAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 1462 1463 1464// addressBlock: dcn_dc_hda_azf0endpoint1_dispdec 1465// base address: 0x18 1466#define regAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x038c 1467#define regAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 1468#define regAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA 0x038d 1469#define regAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 1470 1471 1472// addressBlock: dcn_dc_hda_azf0endpoint2_dispdec 1473// base address: 0x30 1474#define regAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x0392 1475#define regAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 1476#define regAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA 0x0393 1477#define regAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 1478 1479 1480// addressBlock: dcn_dc_hda_azf0endpoint3_dispdec 1481// base address: 0x48 1482#define regAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x0398 1483#define regAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 1484#define regAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA 0x0399 1485#define regAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 1486 1487 1488// addressBlock: dcn_dc_hda_azf0endpoint4_dispdec 1489// base address: 0x60 1490#define regAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x039e 1491#define regAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 1492#define regAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA 0x039f 1493#define regAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 1494 1495 1496// addressBlock: dcn_dc_hda_azf0endpoint5_dispdec 1497// base address: 0x78 1498#define regAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x03a4 1499#define regAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 1500#define regAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA 0x03a5 1501#define regAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 1502 1503 1504// addressBlock: dcn_dc_hda_azf0endpoint6_dispdec 1505// base address: 0x90 1506#define regAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x03aa 1507#define regAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 1508#define regAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA 0x03ab 1509#define regAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 1510 1511 1512// addressBlock: dcn_dc_hda_azf0endpoint7_dispdec 1513// base address: 0xa8 1514#define regAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x03b0 1515#define regAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 1516#define regAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA 0x03b1 1517#define regAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 1518 1519 1520// addressBlock: dcn_dc_hda_azf0inputendpoint0_dispdec 1521// base address: 0x0 1522#define regAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x043a 1523#define regAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 1524#define regAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x043b 1525#define regAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 1526 1527 1528// addressBlock: dcn_dc_hda_azf0inputendpoint1_dispdec 1529// base address: 0x10 1530#define regAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x043e 1531#define regAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 1532#define regAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x043f 1533#define regAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 1534 1535 1536// addressBlock: dcn_dc_hda_azf0inputendpoint2_dispdec 1537// base address: 0x20 1538#define regAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0442 1539#define regAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 1540#define regAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0443 1541#define regAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 1542 1543 1544// addressBlock: dcn_dc_hda_azf0inputendpoint3_dispdec 1545// base address: 0x30 1546#define regAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0446 1547#define regAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 1548#define regAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0447 1549#define regAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 1550 1551 1552// addressBlock: dcn_dc_hda_azf0inputendpoint4_dispdec 1553// base address: 0x40 1554#define regAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x044a 1555#define regAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 1556#define regAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x044b 1557#define regAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 1558 1559 1560// addressBlock: dcn_dc_hda_azf0inputendpoint5_dispdec 1561// base address: 0x50 1562#define regAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x044e 1563#define regAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 1564#define regAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x044f 1565#define regAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 1566 1567 1568// addressBlock: dcn_dc_hda_azf0inputendpoint6_dispdec 1569// base address: 0x60 1570#define regAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0452 1571#define regAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 1572#define regAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0453 1573#define regAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 1574 1575 1576// addressBlock: dcn_dc_hda_azf0inputendpoint7_dispdec 1577// base address: 0x70 1578#define regAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0456 1579#define regAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 1580#define regAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0457 1581#define regAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 1582 1583 1584// addressBlock: dcn_dc_dchubbubl_hubbub_dispdec 1585// base address: 0x0 1586#define regDCHUBBUB_ARB_DF_REQ_OUTSTAND 0x04f9 1587#define regDCHUBBUB_ARB_DF_REQ_OUTSTAND_BASE_IDX 2 1588#define regDCHUBBUB_ARB_SAT_LEVEL 0x04fa 1589#define regDCHUBBUB_ARB_SAT_LEVEL_BASE_IDX 2 1590#define regDCHUBBUB_ARB_QOS_FORCE 0x04fb 1591#define regDCHUBBUB_ARB_QOS_FORCE_BASE_IDX 2 1592#define regDCHUBBUB_ARB_DRAM_STATE_CNTL 0x04fc 1593#define regDCHUBBUB_ARB_DRAM_STATE_CNTL_BASE_IDX 2 1594#define regDCHUBBUB_ARB_USR_RETRAINING_CNTL 0x04fd 1595#define regDCHUBBUB_ARB_USR_RETRAINING_CNTL_BASE_IDX 2 1596#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A 0x04fe 1597#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A_BASE_IDX 2 1598#define regDCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A 0x04ff 1599#define regDCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A_BASE_IDX 2 1600#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A 0x0500 1601#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A_BASE_IDX 2 1602#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A 0x0501 1603#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A_BASE_IDX 2 1604#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A 0x0502 1605#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A_BASE_IDX 2 1606#define regDCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A 0x0503 1607#define regDCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A_BASE_IDX 2 1608#define regDCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A 0x0504 1609#define regDCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A_BASE_IDX 2 1610#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_A 0x0505 1611#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_A_BASE_IDX 2 1612#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_A 0x0506 1613#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_A_BASE_IDX 2 1614#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B 0x0507 1615#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B_BASE_IDX 2 1616#define regDCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B 0x0508 1617#define regDCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B_BASE_IDX 2 1618#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B 0x0509 1619#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B_BASE_IDX 2 1620#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B 0x050a 1621#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B_BASE_IDX 2 1622#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B 0x050b 1623#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B_BASE_IDX 2 1624#define regDCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B 0x050c 1625#define regDCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B_BASE_IDX 2 1626#define regDCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B 0x050d 1627#define regDCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B_BASE_IDX 2 1628#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_B 0x050e 1629#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_B_BASE_IDX 2 1630#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_B 0x050f 1631#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_B_BASE_IDX 2 1632#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C 0x0510 1633#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C_BASE_IDX 2 1634#define regDCHUBBUB_ARB_USR_RETRAINING_WATERMARK_C 0x0511 1635#define regDCHUBBUB_ARB_USR_RETRAINING_WATERMARK_C_BASE_IDX 2 1636#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C 0x0512 1637#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C_BASE_IDX 2 1638#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C 0x0513 1639#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C_BASE_IDX 2 1640#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C 0x0514 1641#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C_BASE_IDX 2 1642#define regDCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_C 0x0515 1643#define regDCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_C_BASE_IDX 2 1644#define regDCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_C 0x0516 1645#define regDCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_C_BASE_IDX 2 1646#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_C 0x0517 1647#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_C_BASE_IDX 2 1648#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_C 0x0518 1649#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_C_BASE_IDX 2 1650#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D 0x0519 1651#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D_BASE_IDX 2 1652#define regDCHUBBUB_ARB_USR_RETRAINING_WATERMARK_D 0x051a 1653#define regDCHUBBUB_ARB_USR_RETRAINING_WATERMARK_D_BASE_IDX 2 1654#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D 0x051b 1655#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D_BASE_IDX 2 1656#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D 0x051c 1657#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D_BASE_IDX 2 1658#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D 0x051d 1659#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D_BASE_IDX 2 1660#define regDCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_D 0x051e 1661#define regDCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_D_BASE_IDX 2 1662#define regDCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_D 0x051f 1663#define regDCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_D_BASE_IDX 2 1664#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_D 0x0520 1665#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_D_BASE_IDX 2 1666#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_D 0x0521 1667#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_D_BASE_IDX 2 1668#define regDCHUBBUB_ARB_WATERMARK_CHANGE_CNTL 0x0522 1669#define regDCHUBBUB_ARB_WATERMARK_CHANGE_CNTL_BASE_IDX 2 1670#define regDCHUBBUB_ARB_MALL_CNTL 0x0523 1671#define regDCHUBBUB_ARB_MALL_CNTL_BASE_IDX 2 1672#define regDCHUBBUB_ARB_TIMEOUT_ENABLE 0x0524 1673#define regDCHUBBUB_ARB_TIMEOUT_ENABLE_BASE_IDX 2 1674#define regDCHUBBUB_GLOBAL_TIMER_CNTL 0x0525 1675#define regDCHUBBUB_GLOBAL_TIMER_CNTL_BASE_IDX 2 1676#define regSURFACE_CHECK0_ADDRESS_LSB 0x0526 1677#define regSURFACE_CHECK0_ADDRESS_LSB_BASE_IDX 2 1678#define regSURFACE_CHECK0_ADDRESS_MSB 0x0527 1679#define regSURFACE_CHECK0_ADDRESS_MSB_BASE_IDX 2 1680#define regSURFACE_CHECK1_ADDRESS_LSB 0x0528 1681#define regSURFACE_CHECK1_ADDRESS_LSB_BASE_IDX 2 1682#define regSURFACE_CHECK1_ADDRESS_MSB 0x0529 1683#define regSURFACE_CHECK1_ADDRESS_MSB_BASE_IDX 2 1684#define regSURFACE_CHECK2_ADDRESS_LSB 0x052a 1685#define regSURFACE_CHECK2_ADDRESS_LSB_BASE_IDX 2 1686#define regSURFACE_CHECK2_ADDRESS_MSB 0x052b 1687#define regSURFACE_CHECK2_ADDRESS_MSB_BASE_IDX 2 1688#define regSURFACE_CHECK3_ADDRESS_LSB 0x052c 1689#define regSURFACE_CHECK3_ADDRESS_LSB_BASE_IDX 2 1690#define regSURFACE_CHECK3_ADDRESS_MSB 0x052d 1691#define regSURFACE_CHECK3_ADDRESS_MSB_BASE_IDX 2 1692#define regVTG0_CONTROL 0x052e 1693#define regVTG0_CONTROL_BASE_IDX 2 1694#define regVTG1_CONTROL 0x052f 1695#define regVTG1_CONTROL_BASE_IDX 2 1696#define regVTG2_CONTROL 0x0530 1697#define regVTG2_CONTROL_BASE_IDX 2 1698#define regVTG3_CONTROL 0x0531 1699#define regVTG3_CONTROL_BASE_IDX 2 1700#define regDCHUBBUB_SOFT_RESET 0x0532 1701#define regDCHUBBUB_SOFT_RESET_BASE_IDX 2 1702#define regDCHUBBUB_CLOCK_CNTL 0x0533 1703#define regDCHUBBUB_CLOCK_CNTL_BASE_IDX 2 1704#define regDCFCLK_CNTL 0x0534 1705#define regDCFCLK_CNTL_BASE_IDX 2 1706#define regDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL 0x0535 1707#define regDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL_BASE_IDX 2 1708#define regDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2 0x0536 1709#define regDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2_BASE_IDX 2 1710#define regDCHUBBUB_VLINE_SNAPSHOT 0x0537 1711#define regDCHUBBUB_VLINE_SNAPSHOT_BASE_IDX 2 1712#define regDCHUBBUB_CTRL_STATUS 0x0538 1713#define regDCHUBBUB_CTRL_STATUS_BASE_IDX 2 1714#define regDCHUBBUB_TIMEOUT_DETECTION_CTRL1 0x053e 1715#define regDCHUBBUB_TIMEOUT_DETECTION_CTRL1_BASE_IDX 2 1716#define regDCHUBBUB_TIMEOUT_DETECTION_CTRL2 0x053f 1717#define regDCHUBBUB_TIMEOUT_DETECTION_CTRL2_BASE_IDX 2 1718#define regDCHUBBUB_TIMEOUT_INTERRUPT_STATUS 0x0540 1719#define regDCHUBBUB_TIMEOUT_INTERRUPT_STATUS_BASE_IDX 2 1720#define regFMON_CTRL 0x0541 1721#define regFMON_CTRL_BASE_IDX 2 1722 1723 1724// addressBlock: dcn_dc_dchubbubl_hubbub_sdpif_dispdec 1725// base address: 0x0 1726#define regDCHUBBUB_SDPIF_CFG0 0x046f 1727#define regDCHUBBUB_SDPIF_CFG0_BASE_IDX 2 1728#define regDCHUBBUB_SDPIF_CFG1 0x0470 1729#define regDCHUBBUB_SDPIF_CFG1_BASE_IDX 2 1730#define regDCHUBBUB_SDPIF_CFG2 0x0471 1731#define regDCHUBBUB_SDPIF_CFG2_BASE_IDX 2 1732#define regVM_REQUEST_PHYSICAL 0x0472 1733#define regVM_REQUEST_PHYSICAL_BASE_IDX 2 1734#define regDCHUBBUB_FORCE_IO_STATUS_0 0x0473 1735#define regDCHUBBUB_FORCE_IO_STATUS_0_BASE_IDX 2 1736#define regDCHUBBUB_FORCE_IO_STATUS_1 0x0474 1737#define regDCHUBBUB_FORCE_IO_STATUS_1_BASE_IDX 2 1738#define regDCN_VM_FB_LOCATION_BASE 0x0475 1739#define regDCN_VM_FB_LOCATION_BASE_BASE_IDX 2 1740#define regDCN_VM_FB_LOCATION_TOP 0x0476 1741#define regDCN_VM_FB_LOCATION_TOP_BASE_IDX 2 1742#define regDCN_VM_FB_OFFSET 0x0477 1743#define regDCN_VM_FB_OFFSET_BASE_IDX 2 1744#define regDCN_VM_AGP_BOT 0x0478 1745#define regDCN_VM_AGP_BOT_BASE_IDX 2 1746#define regDCN_VM_AGP_TOP 0x0479 1747#define regDCN_VM_AGP_TOP_BASE_IDX 2 1748#define regDCN_VM_AGP_BASE 0x047a 1749#define regDCN_VM_AGP_BASE_BASE_IDX 2 1750#define regDCN_VM_LOCAL_HBM_ADDRESS_START 0x047b 1751#define regDCN_VM_LOCAL_HBM_ADDRESS_START_BASE_IDX 2 1752#define regDCN_VM_LOCAL_HBM_ADDRESS_END 0x047c 1753#define regDCN_VM_LOCAL_HBM_ADDRESS_END_BASE_IDX 2 1754#define regDCN_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL 0x047d 1755#define regDCN_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL_BASE_IDX 2 1756#define regDCHUBBUB_SDPIF_PIPE_SEC_LVL 0x047e 1757#define regDCHUBBUB_SDPIF_PIPE_SEC_LVL_BASE_IDX 2 1758#define regDCHUBBUB_SDPIF_PIPE_NOALLOC 0x047f 1759#define regDCHUBBUB_SDPIF_PIPE_NOALLOC_BASE_IDX 2 1760#define regDCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL 0x0480 1761#define regDCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL_BASE_IDX 2 1762#define regDCHUBBUB_SDPIF_PIPE_DCCMETA_SEC_LVL 0x0481 1763#define regDCHUBBUB_SDPIF_PIPE_DCCMETA_SEC_LVL_BASE_IDX 2 1764#define regDCHUBBUB_SDPIF_PIPE_CURSOR0_SEC_LVL 0x0482 1765#define regDCHUBBUB_SDPIF_PIPE_CURSOR0_SEC_LVL_BASE_IDX 2 1766#define regDCHUBBUB_SDPIF_PIPE_GPUVM_SEC_LVL 0x0483 1767#define regDCHUBBUB_SDPIF_PIPE_GPUVM_SEC_LVL_BASE_IDX 2 1768#define regSDPIF_REQUEST_RATE_LIMIT 0x0484 1769#define regSDPIF_REQUEST_RATE_LIMIT_BASE_IDX 2 1770#define regDCHUBBUB_SDPIF_MEM_PWR_CTRL 0x0485 1771#define regDCHUBBUB_SDPIF_MEM_PWR_CTRL_BASE_IDX 2 1772#define regDCHUBBUB_SDPIF_MEM_PWR_STATUS 0x0486 1773#define regDCHUBBUB_SDPIF_MEM_PWR_STATUS_BASE_IDX 2 1774 1775 1776// addressBlock: dcn_dc_dchubbubl_hubbub_ret_path_dispdec 1777// base address: 0x0 1778#define regDCHUBBUB_RET_PATH_MEM_PWR_CTRL 0x04af 1779#define regDCHUBBUB_RET_PATH_MEM_PWR_CTRL_BASE_IDX 2 1780#define regDCHUBBUB_RET_PATH_MEM_PWR_STATUS 0x04b0 1781#define regDCHUBBUB_RET_PATH_MEM_PWR_STATUS_BASE_IDX 2 1782#define regDCHUBBUB_CRC_CTRL 0x04b1 1783#define regDCHUBBUB_CRC_CTRL_BASE_IDX 2 1784#define regDCHUBBUB_CRC0_VAL_R_G 0x04b2 1785#define regDCHUBBUB_CRC0_VAL_R_G_BASE_IDX 2 1786#define regDCHUBBUB_CRC0_VAL_B_A 0x04b3 1787#define regDCHUBBUB_CRC0_VAL_B_A_BASE_IDX 2 1788#define regDCHUBBUB_CRC1_VAL_R_G 0x04b4 1789#define regDCHUBBUB_CRC1_VAL_R_G_BASE_IDX 2 1790#define regDCHUBBUB_CRC1_VAL_B_A 0x04b5 1791#define regDCHUBBUB_CRC1_VAL_B_A_BASE_IDX 2 1792#define regDCHUBBUB_DCC_STAT_CNTL 0x04b6 1793#define regDCHUBBUB_DCC_STAT_CNTL_BASE_IDX 2 1794#define regDCHUBBUB_DCC_STAT0 0x04b7 1795#define regDCHUBBUB_DCC_STAT0_BASE_IDX 2 1796#define regDCHUBBUB_DCC_STAT1 0x04b8 1797#define regDCHUBBUB_DCC_STAT1_BASE_IDX 2 1798#define regDCHUBBUB_DCC_STAT2 0x04b9 1799#define regDCHUBBUB_DCC_STAT2_BASE_IDX 2 1800#define regDCHUBBUB_COMPBUF_CTRL 0x04ba 1801#define regDCHUBBUB_COMPBUF_CTRL_BASE_IDX 2 1802#define regDCHUBBUB_DET0_CTRL 0x04bb 1803#define regDCHUBBUB_DET0_CTRL_BASE_IDX 2 1804#define regDCHUBBUB_DET1_CTRL 0x04bc 1805#define regDCHUBBUB_DET1_CTRL_BASE_IDX 2 1806#define regDCHUBBUB_DET2_CTRL 0x04bd 1807#define regDCHUBBUB_DET2_CTRL_BASE_IDX 2 1808#define regDCHUBBUB_DET3_CTRL 0x04be 1809#define regDCHUBBUB_DET3_CTRL_BASE_IDX 2 1810#define regDCHUBBUB_DEBUG_CTRL_0 0x04c5 1811#define regDCHUBBUB_DEBUG_CTRL_0_BASE_IDX 2 1812#define regDCHUBBUB_MEM_PWR_MODE_CTRL 0x04c0 1813#define regDCHUBBUB_MEM_PWR_MODE_CTRL_BASE_IDX 2 1814#define regCOMPBUF_MEM_PWR_CTRL_1 0x04c1 1815#define regCOMPBUF_MEM_PWR_CTRL_1_BASE_IDX 2 1816#define regCOMPBUF_MEM_PWR_CTRL_2 0x04c2 1817#define regCOMPBUF_MEM_PWR_CTRL_2_BASE_IDX 2 1818#define regDCHUBBUB_MEM_PWR_STATUS 0x04c3 1819#define regDCHUBBUB_MEM_PWR_STATUS_BASE_IDX 2 1820#define regCOMPBUF_RESERVED_SPACE 0x04c4 1821#define regCOMPBUF_RESERVED_SPACE_BASE_IDX 2 1822 1823 1824// addressBlock: dcn_dc_dchubbubl_hubbub_vmrq_if_dispdec 1825// base address: 0x0 1826#define regDCN_VM_CONTEXT0_CNTL 0x0559 1827#define regDCN_VM_CONTEXT0_CNTL_BASE_IDX 2 1828#define regDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 0x055a 1829#define regDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 1830#define regDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 0x055b 1831#define regDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 1832#define regDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 0x055c 1833#define regDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 1834#define regDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 0x055d 1835#define regDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 1836#define regDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 0x055e 1837#define regDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 1838#define regDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 0x055f 1839#define regDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 1840#define regDCN_VM_CONTEXT1_CNTL 0x0560 1841#define regDCN_VM_CONTEXT1_CNTL_BASE_IDX 2 1842#define regDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32 0x0561 1843#define regDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 1844#define regDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 0x0562 1845#define regDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 1846#define regDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32 0x0563 1847#define regDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 1848#define regDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32 0x0564 1849#define regDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 1850#define regDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32 0x0565 1851#define regDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 1852#define regDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32 0x0566 1853#define regDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 1854#define regDCN_VM_CONTEXT2_CNTL 0x0567 1855#define regDCN_VM_CONTEXT2_CNTL_BASE_IDX 2 1856#define regDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32 0x0568 1857#define regDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 1858#define regDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32 0x0569 1859#define regDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 1860#define regDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32 0x056a 1861#define regDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 1862#define regDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32 0x056b 1863#define regDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 1864#define regDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32 0x056c 1865#define regDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 1866#define regDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32 0x056d 1867#define regDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 1868#define regDCN_VM_CONTEXT3_CNTL 0x056e 1869#define regDCN_VM_CONTEXT3_CNTL_BASE_IDX 2 1870#define regDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32 0x056f 1871#define regDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 1872#define regDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32 0x0570 1873#define regDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 1874#define regDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32 0x0571 1875#define regDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 1876#define regDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32 0x0572 1877#define regDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 1878#define regDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32 0x0573 1879#define regDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 1880#define regDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32 0x0574 1881#define regDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 1882#define regDCN_VM_CONTEXT4_CNTL 0x0575 1883#define regDCN_VM_CONTEXT4_CNTL_BASE_IDX 2 1884#define regDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32 0x0576 1885#define regDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 1886#define regDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32 0x0577 1887#define regDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 1888#define regDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32 0x0578 1889#define regDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 1890#define regDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32 0x0579 1891#define regDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 1892#define regDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32 0x057a 1893#define regDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 1894#define regDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32 0x057b 1895#define regDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 1896#define regDCN_VM_CONTEXT5_CNTL 0x057c 1897#define regDCN_VM_CONTEXT5_CNTL_BASE_IDX 2 1898#define regDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32 0x057d 1899#define regDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 1900#define regDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32 0x057e 1901#define regDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 1902#define regDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32 0x057f 1903#define regDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 1904#define regDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32 0x0580 1905#define regDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 1906#define regDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32 0x0581 1907#define regDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 1908#define regDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32 0x0582 1909#define regDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 1910#define regDCN_VM_CONTEXT6_CNTL 0x0583 1911#define regDCN_VM_CONTEXT6_CNTL_BASE_IDX 2 1912#define regDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32 0x0584 1913#define regDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 1914#define regDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32 0x0585 1915#define regDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 1916#define regDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32 0x0586 1917#define regDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 1918#define regDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32 0x0587 1919#define regDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 1920#define regDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32 0x0588 1921#define regDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 1922#define regDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32 0x0589 1923#define regDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 1924#define regDCN_VM_CONTEXT7_CNTL 0x058a 1925#define regDCN_VM_CONTEXT7_CNTL_BASE_IDX 2 1926#define regDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32 0x058b 1927#define regDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 1928#define regDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32 0x058c 1929#define regDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 1930#define regDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32 0x058d 1931#define regDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 1932#define regDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32 0x058e 1933#define regDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 1934#define regDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32 0x058f 1935#define regDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 1936#define regDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32 0x0590 1937#define regDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 1938#define regDCN_VM_CONTEXT8_CNTL 0x0591 1939#define regDCN_VM_CONTEXT8_CNTL_BASE_IDX 2 1940#define regDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32 0x0592 1941#define regDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 1942#define regDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32 0x0593 1943#define regDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 1944#define regDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32 0x0594 1945#define regDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 1946#define regDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32 0x0595 1947#define regDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 1948#define regDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32 0x0596 1949#define regDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 1950#define regDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32 0x0597 1951#define regDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 1952#define regDCN_VM_CONTEXT9_CNTL 0x0598 1953#define regDCN_VM_CONTEXT9_CNTL_BASE_IDX 2 1954#define regDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32 0x0599 1955#define regDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 1956#define regDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32 0x059a 1957#define regDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 1958#define regDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32 0x059b 1959#define regDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 1960#define regDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32 0x059c 1961#define regDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 1962#define regDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32 0x059d 1963#define regDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 1964#define regDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32 0x059e 1965#define regDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 1966#define regDCN_VM_CONTEXT10_CNTL 0x059f 1967#define regDCN_VM_CONTEXT10_CNTL_BASE_IDX 2 1968#define regDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32 0x05a0 1969#define regDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 1970#define regDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32 0x05a1 1971#define regDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 1972#define regDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32 0x05a2 1973#define regDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 1974#define regDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32 0x05a3 1975#define regDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 1976#define regDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32 0x05a4 1977#define regDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 1978#define regDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32 0x05a5 1979#define regDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 1980#define regDCN_VM_CONTEXT11_CNTL 0x05a6 1981#define regDCN_VM_CONTEXT11_CNTL_BASE_IDX 2 1982#define regDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32 0x05a7 1983#define regDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 1984#define regDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32 0x05a8 1985#define regDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 1986#define regDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32 0x05a9 1987#define regDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 1988#define regDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32 0x05aa 1989#define regDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 1990#define regDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32 0x05ab 1991#define regDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 1992#define regDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32 0x05ac 1993#define regDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 1994#define regDCN_VM_CONTEXT12_CNTL 0x05ad 1995#define regDCN_VM_CONTEXT12_CNTL_BASE_IDX 2 1996#define regDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32 0x05ae 1997#define regDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 1998#define regDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32 0x05af 1999#define regDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 2000#define regDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32 0x05b0 2001#define regDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 2002#define regDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32 0x05b1 2003#define regDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 2004#define regDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32 0x05b2 2005#define regDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 2006#define regDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32 0x05b3 2007#define regDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 2008#define regDCN_VM_CONTEXT13_CNTL 0x05b4 2009#define regDCN_VM_CONTEXT13_CNTL_BASE_IDX 2 2010#define regDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32 0x05b5 2011#define regDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 2012#define regDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32 0x05b6 2013#define regDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 2014#define regDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32 0x05b7 2015#define regDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 2016#define regDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32 0x05b8 2017#define regDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 2018#define regDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32 0x05b9 2019#define regDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 2020#define regDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32 0x05ba 2021#define regDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 2022#define regDCN_VM_CONTEXT14_CNTL 0x05bb 2023#define regDCN_VM_CONTEXT14_CNTL_BASE_IDX 2 2024#define regDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32 0x05bc 2025#define regDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 2026#define regDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32 0x05bd 2027#define regDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 2028#define regDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32 0x05be 2029#define regDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 2030#define regDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32 0x05bf 2031#define regDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 2032#define regDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32 0x05c0 2033#define regDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 2034#define regDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32 0x05c1 2035#define regDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 2036#define regDCN_VM_CONTEXT15_CNTL 0x05c2 2037#define regDCN_VM_CONTEXT15_CNTL_BASE_IDX 2 2038#define regDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32 0x05c3 2039#define regDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 2040#define regDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32 0x05c4 2041#define regDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 2042#define regDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32 0x05c5 2043#define regDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 2044#define regDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32 0x05c6 2045#define regDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 2046#define regDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32 0x05c7 2047#define regDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 2048#define regDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32 0x05c8 2049#define regDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 2050#define regDCN_VM_DEFAULT_ADDR_MSB 0x05c9 2051#define regDCN_VM_DEFAULT_ADDR_MSB_BASE_IDX 2 2052#define regDCN_VM_DEFAULT_ADDR_LSB 0x05ca 2053#define regDCN_VM_DEFAULT_ADDR_LSB_BASE_IDX 2 2054#define regDCN_VM_FAULT_CNTL 0x05cb 2055#define regDCN_VM_FAULT_CNTL_BASE_IDX 2 2056#define regDCN_VM_FAULT_STATUS 0x05cc 2057#define regDCN_VM_FAULT_STATUS_BASE_IDX 2 2058#define regDCN_VM_FAULT_ADDR_MSB 0x05cd 2059#define regDCN_VM_FAULT_ADDR_MSB_BASE_IDX 2 2060#define regDCN_VM_FAULT_ADDR_LSB 0x05ce 2061#define regDCN_VM_FAULT_ADDR_LSB_BASE_IDX 2 2062 2063 2064// addressBlock: dcn_dc_dcbubp0_dispdec_hubp_dispdec 2065// base address: 0x0 2066#define regHUBP0_DCSURF_SURFACE_CONFIG 0x05e5 2067#define regHUBP0_DCSURF_SURFACE_CONFIG_BASE_IDX 2 2068#define regHUBP0_DCSURF_ADDR_CONFIG 0x05e6 2069#define regHUBP0_DCSURF_ADDR_CONFIG_BASE_IDX 2 2070#define regHUBP0_DCSURF_TILING_CONFIG 0x05e7 2071#define regHUBP0_DCSURF_TILING_CONFIG_BASE_IDX 2 2072#define regHUBP0_DCSURF_PRI_VIEWPORT_START 0x05e9 2073#define regHUBP0_DCSURF_PRI_VIEWPORT_START_BASE_IDX 2 2074#define regHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION 0x05ea 2075#define regHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2 2076#define regHUBP0_DCSURF_PRI_VIEWPORT_START_C 0x05eb 2077#define regHUBP0_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX 2 2078#define regHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C 0x05ec 2079#define regHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX 2 2080#define regHUBP0_DCSURF_SEC_VIEWPORT_START 0x05ed 2081#define regHUBP0_DCSURF_SEC_VIEWPORT_START_BASE_IDX 2 2082#define regHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION 0x05ee 2083#define regHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX 2 2084#define regHUBP0_DCSURF_SEC_VIEWPORT_START_C 0x05ef 2085#define regHUBP0_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX 2 2086#define regHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C 0x05f0 2087#define regHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX 2 2088#define regHUBP0_DCHUBP_REQ_SIZE_CONFIG 0x05f1 2089#define regHUBP0_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX 2 2090#define regHUBP0_DCHUBP_REQ_SIZE_CONFIG_C 0x05f2 2091#define regHUBP0_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX 2 2092#define regHUBP0_DCHUBP_CNTL 0x05f3 2093#define regHUBP0_DCHUBP_CNTL_BASE_IDX 2 2094#define regHUBP0_HUBP_CLK_CNTL 0x05f4 2095#define regHUBP0_HUBP_CLK_CNTL_BASE_IDX 2 2096#define regHUBP0_DCHUBP_VMPG_CONFIG 0x05f5 2097#define regHUBP0_DCHUBP_VMPG_CONFIG_BASE_IDX 2 2098#define regHUBP0_DCHUBP_MALL_CONFIG 0x05f6 2099#define regHUBP0_DCHUBP_MALL_CONFIG_BASE_IDX 2 2100#define regHUBP0_DCHUBP_MALL_SUB_VP 0x05f7 2101#define regHUBP0_DCHUBP_MALL_SUB_VP_BASE_IDX 2 2102#define regHUBP0_HUBPREQ_DEBUG_DB 0x05f8 2103#define regHUBP0_HUBPREQ_DEBUG_DB_BASE_IDX 2 2104#define regHUBP0_HUBPREQ_DEBUG 0x05f9 2105#define regHUBP0_HUBPREQ_DEBUG_BASE_IDX 2 2106#define regHUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK 0x05fd 2107#define regHUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX 2 2108#define regHUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK 0x05fe 2109#define regHUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX 2 2110#define regHUBP0_HUBP_MALL_STATUS 0x05ff 2111#define regHUBP0_HUBP_MALL_STATUS_BASE_IDX 2 2112 2113 2114// addressBlock: dcn_dc_dcbubp0_dispdec_hubpreq_dispdec 2115// base address: 0x0 2116#define regHUBPREQ0_DCSURF_SURFACE_PITCH 0x0607 2117#define regHUBPREQ0_DCSURF_SURFACE_PITCH_BASE_IDX 2 2118#define regHUBPREQ0_DCSURF_SURFACE_PITCH_C 0x0608 2119#define regHUBPREQ0_DCSURF_SURFACE_PITCH_C_BASE_IDX 2 2120#define regHUBPREQ0_VMID_SETTINGS_0 0x0609 2121#define regHUBPREQ0_VMID_SETTINGS_0_BASE_IDX 2 2122#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS 0x060a 2123#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2 2124#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH 0x060b 2125#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 2126#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C 0x060c 2127#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX 2 2128#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x060d 2129#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 2130#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS 0x060e 2131#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2 2132#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH 0x060f 2133#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 2134#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C 0x0610 2135#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX 2 2136#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x0611 2137#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 2138#define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS 0x0612 2139#define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX 2 2140#define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH 0x0613 2141#define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 2142#define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C 0x0614 2143#define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 2144#define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C 0x0615 2145#define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 2146#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS 0x0616 2147#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX 2 2148#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH 0x0617 2149#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 2150#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C 0x0618 2151#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 2152#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C 0x0619 2153#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 2154#define regHUBPREQ0_DCSURF_SURFACE_CONTROL 0x061a 2155#define regHUBPREQ0_DCSURF_SURFACE_CONTROL_BASE_IDX 2 2156#define regHUBPREQ0_DCSURF_FLIP_CONTROL 0x061b 2157#define regHUBPREQ0_DCSURF_FLIP_CONTROL_BASE_IDX 2 2158#define regHUBPREQ0_DCSURF_FLIP_CONTROL2 0x061c 2159#define regHUBPREQ0_DCSURF_FLIP_CONTROL2_BASE_IDX 2 2160#define regHUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT 0x061f 2161#define regHUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX 2 2162#define regHUBPREQ0_DCSURF_SURFACE_INUSE 0x0620 2163#define regHUBPREQ0_DCSURF_SURFACE_INUSE_BASE_IDX 2 2164#define regHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH 0x0621 2165#define regHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX 2 2166#define regHUBPREQ0_DCSURF_SURFACE_INUSE_C 0x0622 2167#define regHUBPREQ0_DCSURF_SURFACE_INUSE_C_BASE_IDX 2 2168#define regHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C 0x0623 2169#define regHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX 2 2170#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE 0x0624 2171#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX 2 2172#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH 0x0625 2173#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX 2 2174#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C 0x0626 2175#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX 2 2176#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C 0x0627 2177#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX 2 2178#define regHUBPREQ0_DCN_EXPANSION_MODE 0x0628 2179#define regHUBPREQ0_DCN_EXPANSION_MODE_BASE_IDX 2 2180#define regHUBPREQ0_DCN_TTU_QOS_WM 0x0629 2181#define regHUBPREQ0_DCN_TTU_QOS_WM_BASE_IDX 2 2182#define regHUBPREQ0_DCN_GLOBAL_TTU_CNTL 0x062a 2183#define regHUBPREQ0_DCN_GLOBAL_TTU_CNTL_BASE_IDX 2 2184#define regHUBPREQ0_DCN_SURF0_TTU_CNTL0 0x062b 2185#define regHUBPREQ0_DCN_SURF0_TTU_CNTL0_BASE_IDX 2 2186#define regHUBPREQ0_DCN_SURF0_TTU_CNTL1 0x062c 2187#define regHUBPREQ0_DCN_SURF0_TTU_CNTL1_BASE_IDX 2 2188#define regHUBPREQ0_DCN_SURF1_TTU_CNTL0 0x062d 2189#define regHUBPREQ0_DCN_SURF1_TTU_CNTL0_BASE_IDX 2 2190#define regHUBPREQ0_DCN_SURF1_TTU_CNTL1 0x062e 2191#define regHUBPREQ0_DCN_SURF1_TTU_CNTL1_BASE_IDX 2 2192#define regHUBPREQ0_DCN_CUR0_TTU_CNTL0 0x062f 2193#define regHUBPREQ0_DCN_CUR0_TTU_CNTL0_BASE_IDX 2 2194#define regHUBPREQ0_DCN_CUR0_TTU_CNTL1 0x0630 2195#define regHUBPREQ0_DCN_CUR0_TTU_CNTL1_BASE_IDX 2 2196#define regHUBPREQ0_DCN_CUR1_TTU_CNTL0 0x0631 2197#define regHUBPREQ0_DCN_CUR1_TTU_CNTL0_BASE_IDX 2 2198#define regHUBPREQ0_DCN_CUR1_TTU_CNTL1 0x0632 2199#define regHUBPREQ0_DCN_CUR1_TTU_CNTL1_BASE_IDX 2 2200#define regHUBPREQ0_DCN_DMDATA_VM_CNTL 0x0633 2201#define regHUBPREQ0_DCN_DMDATA_VM_CNTL_BASE_IDX 2 2202#define regHUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR 0x0634 2203#define regHUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 2 2204#define regHUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR 0x0635 2205#define regHUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 2 2206#define regHUBPREQ0_DCN_VM_MX_L1_TLB_CNTL 0x0642 2207#define regHUBPREQ0_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX 2 2208#define regHUBPREQ0_BLANK_OFFSET_0 0x0643 2209#define regHUBPREQ0_BLANK_OFFSET_0_BASE_IDX 2 2210#define regHUBPREQ0_BLANK_OFFSET_1 0x0644 2211#define regHUBPREQ0_BLANK_OFFSET_1_BASE_IDX 2 2212#define regHUBPREQ0_DST_DIMENSIONS 0x0645 2213#define regHUBPREQ0_DST_DIMENSIONS_BASE_IDX 2 2214#define regHUBPREQ0_DST_AFTER_SCALER 0x0646 2215#define regHUBPREQ0_DST_AFTER_SCALER_BASE_IDX 2 2216#define regHUBPREQ0_PREFETCH_SETTINGS 0x0647 2217#define regHUBPREQ0_PREFETCH_SETTINGS_BASE_IDX 2 2218#define regHUBPREQ0_PREFETCH_SETTINGS_C 0x0648 2219#define regHUBPREQ0_PREFETCH_SETTINGS_C_BASE_IDX 2 2220#define regHUBPREQ0_VBLANK_PARAMETERS_0 0x0649 2221#define regHUBPREQ0_VBLANK_PARAMETERS_0_BASE_IDX 2 2222#define regHUBPREQ0_VBLANK_PARAMETERS_1 0x064a 2223#define regHUBPREQ0_VBLANK_PARAMETERS_1_BASE_IDX 2 2224#define regHUBPREQ0_VBLANK_PARAMETERS_2 0x064b 2225#define regHUBPREQ0_VBLANK_PARAMETERS_2_BASE_IDX 2 2226#define regHUBPREQ0_VBLANK_PARAMETERS_3 0x064c 2227#define regHUBPREQ0_VBLANK_PARAMETERS_3_BASE_IDX 2 2228#define regHUBPREQ0_VBLANK_PARAMETERS_4 0x064d 2229#define regHUBPREQ0_VBLANK_PARAMETERS_4_BASE_IDX 2 2230#define regHUBPREQ0_FLIP_PARAMETERS_0 0x064e 2231#define regHUBPREQ0_FLIP_PARAMETERS_0_BASE_IDX 2 2232#define regHUBPREQ0_FLIP_PARAMETERS_1 0x064f 2233#define regHUBPREQ0_FLIP_PARAMETERS_1_BASE_IDX 2 2234#define regHUBPREQ0_FLIP_PARAMETERS_2 0x0650 2235#define regHUBPREQ0_FLIP_PARAMETERS_2_BASE_IDX 2 2236#define regHUBPREQ0_NOM_PARAMETERS_0 0x0651 2237#define regHUBPREQ0_NOM_PARAMETERS_0_BASE_IDX 2 2238#define regHUBPREQ0_NOM_PARAMETERS_1 0x0652 2239#define regHUBPREQ0_NOM_PARAMETERS_1_BASE_IDX 2 2240#define regHUBPREQ0_NOM_PARAMETERS_2 0x0653 2241#define regHUBPREQ0_NOM_PARAMETERS_2_BASE_IDX 2 2242#define regHUBPREQ0_NOM_PARAMETERS_3 0x0654 2243#define regHUBPREQ0_NOM_PARAMETERS_3_BASE_IDX 2 2244#define regHUBPREQ0_NOM_PARAMETERS_4 0x0655 2245#define regHUBPREQ0_NOM_PARAMETERS_4_BASE_IDX 2 2246#define regHUBPREQ0_NOM_PARAMETERS_5 0x0656 2247#define regHUBPREQ0_NOM_PARAMETERS_5_BASE_IDX 2 2248#define regHUBPREQ0_NOM_PARAMETERS_6 0x0657 2249#define regHUBPREQ0_NOM_PARAMETERS_6_BASE_IDX 2 2250#define regHUBPREQ0_NOM_PARAMETERS_7 0x0658 2251#define regHUBPREQ0_NOM_PARAMETERS_7_BASE_IDX 2 2252#define regHUBPREQ0_PER_LINE_DELIVERY_PRE 0x0659 2253#define regHUBPREQ0_PER_LINE_DELIVERY_PRE_BASE_IDX 2 2254#define regHUBPREQ0_PER_LINE_DELIVERY 0x065a 2255#define regHUBPREQ0_PER_LINE_DELIVERY_BASE_IDX 2 2256#define regHUBPREQ0_CURSOR_SETTINGS 0x065b 2257#define regHUBPREQ0_CURSOR_SETTINGS_BASE_IDX 2 2258#define regHUBPREQ0_REF_FREQ_TO_PIX_FREQ 0x065c 2259#define regHUBPREQ0_REF_FREQ_TO_PIX_FREQ_BASE_IDX 2 2260#define regHUBPREQ0_DST_Y_DELTA_DRQ_LIMIT 0x065d 2261#define regHUBPREQ0_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX 2 2262#define regHUBPREQ0_HUBPREQ_MEM_PWR_CTRL 0x065e 2263#define regHUBPREQ0_HUBPREQ_MEM_PWR_CTRL_BASE_IDX 2 2264#define regHUBPREQ0_HUBPREQ_MEM_PWR_STATUS 0x065f 2265#define regHUBPREQ0_HUBPREQ_MEM_PWR_STATUS_BASE_IDX 2 2266#define regHUBPREQ0_VBLANK_PARAMETERS_5 0x0662 2267#define regHUBPREQ0_VBLANK_PARAMETERS_5_BASE_IDX 2 2268#define regHUBPREQ0_VBLANK_PARAMETERS_6 0x0663 2269#define regHUBPREQ0_VBLANK_PARAMETERS_6_BASE_IDX 2 2270#define regHUBPREQ0_FLIP_PARAMETERS_3 0x0664 2271#define regHUBPREQ0_FLIP_PARAMETERS_3_BASE_IDX 2 2272#define regHUBPREQ0_FLIP_PARAMETERS_4 0x0665 2273#define regHUBPREQ0_FLIP_PARAMETERS_4_BASE_IDX 2 2274#define regHUBPREQ0_FLIP_PARAMETERS_5 0x0666 2275#define regHUBPREQ0_FLIP_PARAMETERS_5_BASE_IDX 2 2276#define regHUBPREQ0_FLIP_PARAMETERS_6 0x0667 2277#define regHUBPREQ0_FLIP_PARAMETERS_6_BASE_IDX 2 2278#define regHUBPREQ0_UCLK_PSTATE_FORCE 0x0668 2279#define regHUBPREQ0_UCLK_PSTATE_FORCE_BASE_IDX 2 2280#define regHUBPREQ0_HUBPREQ_STATUS_REG0 0x0669 2281#define regHUBPREQ0_HUBPREQ_STATUS_REG0_BASE_IDX 2 2282#define regHUBPREQ0_HUBPREQ_STATUS_REG1 0x066a 2283#define regHUBPREQ0_HUBPREQ_STATUS_REG1_BASE_IDX 2 2284#define regHUBPREQ0_HUBPREQ_STATUS_REG2 0x066b 2285#define regHUBPREQ0_HUBPREQ_STATUS_REG2_BASE_IDX 2 2286 2287 2288// addressBlock: dcn_dc_dcbubp0_dispdec_hubpret_dispdec 2289// base address: 0x0 2290#define regHUBPRET0_HUBPRET_CONTROL 0x066c 2291#define regHUBPRET0_HUBPRET_CONTROL_BASE_IDX 2 2292#define regHUBPRET0_HUBPRET_MEM_PWR_CTRL 0x066d 2293#define regHUBPRET0_HUBPRET_MEM_PWR_CTRL_BASE_IDX 2 2294#define regHUBPRET0_HUBPRET_MEM_PWR_STATUS 0x066e 2295#define regHUBPRET0_HUBPRET_MEM_PWR_STATUS_BASE_IDX 2 2296#define regHUBPRET0_HUBPRET_READ_LINE_CTRL0 0x066f 2297#define regHUBPRET0_HUBPRET_READ_LINE_CTRL0_BASE_IDX 2 2298#define regHUBPRET0_HUBPRET_READ_LINE_CTRL1 0x0670 2299#define regHUBPRET0_HUBPRET_READ_LINE_CTRL1_BASE_IDX 2 2300#define regHUBPRET0_HUBPRET_READ_LINE0 0x0671 2301#define regHUBPRET0_HUBPRET_READ_LINE0_BASE_IDX 2 2302#define regHUBPRET0_HUBPRET_READ_LINE1 0x0672 2303#define regHUBPRET0_HUBPRET_READ_LINE1_BASE_IDX 2 2304#define regHUBPRET0_HUBPRET_INTERRUPT 0x0673 2305#define regHUBPRET0_HUBPRET_INTERRUPT_BASE_IDX 2 2306#define regHUBPRET0_HUBPRET_READ_LINE_VALUE 0x0674 2307#define regHUBPRET0_HUBPRET_READ_LINE_VALUE_BASE_IDX 2 2308#define regHUBPRET0_HUBPRET_READ_LINE_STATUS 0x0675 2309#define regHUBPRET0_HUBPRET_READ_LINE_STATUS_BASE_IDX 2 2310 2311 2312// addressBlock: dcn_dc_dcbubp0_dispdec_cursor0_dispdec 2313// base address: 0x0 2314#define regCURSOR0_0_CURSOR_CONTROL 0x0678 2315#define regCURSOR0_0_CURSOR_CONTROL_BASE_IDX 2 2316#define regCURSOR0_0_CURSOR_SURFACE_ADDRESS 0x0679 2317#define regCURSOR0_0_CURSOR_SURFACE_ADDRESS_BASE_IDX 2 2318#define regCURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH 0x067a 2319#define regCURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX 2 2320#define regCURSOR0_0_CURSOR_SIZE 0x067b 2321#define regCURSOR0_0_CURSOR_SIZE_BASE_IDX 2 2322#define regCURSOR0_0_CURSOR_POSITION 0x067c 2323#define regCURSOR0_0_CURSOR_POSITION_BASE_IDX 2 2324#define regCURSOR0_0_CURSOR_HOT_SPOT 0x067d 2325#define regCURSOR0_0_CURSOR_HOT_SPOT_BASE_IDX 2 2326#define regCURSOR0_0_CURSOR_STEREO_CONTROL 0x067e 2327#define regCURSOR0_0_CURSOR_STEREO_CONTROL_BASE_IDX 2 2328#define regCURSOR0_0_CURSOR_DST_OFFSET 0x067f 2329#define regCURSOR0_0_CURSOR_DST_OFFSET_BASE_IDX 2 2330#define regCURSOR0_0_CURSOR_MEM_PWR_CTRL 0x0680 2331#define regCURSOR0_0_CURSOR_MEM_PWR_CTRL_BASE_IDX 2 2332#define regCURSOR0_0_CURSOR_MEM_PWR_STATUS 0x0681 2333#define regCURSOR0_0_CURSOR_MEM_PWR_STATUS_BASE_IDX 2 2334#define regCURSOR0_0_DMDATA_ADDRESS_HIGH 0x0682 2335#define regCURSOR0_0_DMDATA_ADDRESS_HIGH_BASE_IDX 2 2336#define regCURSOR0_0_DMDATA_ADDRESS_LOW 0x0683 2337#define regCURSOR0_0_DMDATA_ADDRESS_LOW_BASE_IDX 2 2338#define regCURSOR0_0_DMDATA_CNTL 0x0684 2339#define regCURSOR0_0_DMDATA_CNTL_BASE_IDX 2 2340#define regCURSOR0_0_DMDATA_QOS_CNTL 0x0685 2341#define regCURSOR0_0_DMDATA_QOS_CNTL_BASE_IDX 2 2342#define regCURSOR0_0_DMDATA_STATUS 0x0686 2343#define regCURSOR0_0_DMDATA_STATUS_BASE_IDX 2 2344#define regCURSOR0_0_DMDATA_SW_CNTL 0x0687 2345#define regCURSOR0_0_DMDATA_SW_CNTL_BASE_IDX 2 2346#define regCURSOR0_0_DMDATA_SW_DATA 0x0688 2347#define regCURSOR0_0_DMDATA_SW_DATA_BASE_IDX 2 2348 2349 2350 2351// addressBlock: dcn_dc_dcbubp1_dispdec_hubp_dispdec 2352// base address: 0x370 2353#define regHUBP1_DCSURF_SURFACE_CONFIG 0x06c1 2354#define regHUBP1_DCSURF_SURFACE_CONFIG_BASE_IDX 2 2355#define regHUBP1_DCSURF_ADDR_CONFIG 0x06c2 2356#define regHUBP1_DCSURF_ADDR_CONFIG_BASE_IDX 2 2357#define regHUBP1_DCSURF_TILING_CONFIG 0x06c3 2358#define regHUBP1_DCSURF_TILING_CONFIG_BASE_IDX 2 2359#define regHUBP1_DCSURF_PRI_VIEWPORT_START 0x06c5 2360#define regHUBP1_DCSURF_PRI_VIEWPORT_START_BASE_IDX 2 2361#define regHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION 0x06c6 2362#define regHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2 2363#define regHUBP1_DCSURF_PRI_VIEWPORT_START_C 0x06c7 2364#define regHUBP1_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX 2 2365#define regHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C 0x06c8 2366#define regHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX 2 2367#define regHUBP1_DCSURF_SEC_VIEWPORT_START 0x06c9 2368#define regHUBP1_DCSURF_SEC_VIEWPORT_START_BASE_IDX 2 2369#define regHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION 0x06ca 2370#define regHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX 2 2371#define regHUBP1_DCSURF_SEC_VIEWPORT_START_C 0x06cb 2372#define regHUBP1_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX 2 2373#define regHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C 0x06cc 2374#define regHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX 2 2375#define regHUBP1_DCHUBP_REQ_SIZE_CONFIG 0x06cd 2376#define regHUBP1_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX 2 2377#define regHUBP1_DCHUBP_REQ_SIZE_CONFIG_C 0x06ce 2378#define regHUBP1_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX 2 2379#define regHUBP1_DCHUBP_CNTL 0x06cf 2380#define regHUBP1_DCHUBP_CNTL_BASE_IDX 2 2381#define regHUBP1_HUBP_CLK_CNTL 0x06d0 2382#define regHUBP1_HUBP_CLK_CNTL_BASE_IDX 2 2383#define regHUBP1_DCHUBP_VMPG_CONFIG 0x06d1 2384#define regHUBP1_DCHUBP_VMPG_CONFIG_BASE_IDX 2 2385#define regHUBP1_DCHUBP_MALL_CONFIG 0x06d2 2386#define regHUBP1_DCHUBP_MALL_CONFIG_BASE_IDX 2 2387#define regHUBP1_DCHUBP_MALL_SUB_VP 0x06d3 2388#define regHUBP1_DCHUBP_MALL_SUB_VP_BASE_IDX 2 2389#define regHUBP1_HUBPREQ_DEBUG_DB 0x06d4 2390#define regHUBP1_HUBPREQ_DEBUG_DB_BASE_IDX 2 2391#define regHUBP1_HUBPREQ_DEBUG 0x06d5 2392#define regHUBP1_HUBPREQ_DEBUG_BASE_IDX 2 2393#define regHUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK 0x06d9 2394#define regHUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX 2 2395#define regHUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK 0x06da 2396#define regHUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX 2 2397#define regHUBP1_HUBP_MALL_STATUS 0x06db 2398#define regHUBP1_HUBP_MALL_STATUS_BASE_IDX 2 2399 2400 2401// addressBlock: dcn_dc_dcbubp1_dispdec_hubpreq_dispdec 2402// base address: 0x370 2403#define regHUBPREQ1_DCSURF_SURFACE_PITCH 0x06e3 2404#define regHUBPREQ1_DCSURF_SURFACE_PITCH_BASE_IDX 2 2405#define regHUBPREQ1_DCSURF_SURFACE_PITCH_C 0x06e4 2406#define regHUBPREQ1_DCSURF_SURFACE_PITCH_C_BASE_IDX 2 2407#define regHUBPREQ1_VMID_SETTINGS_0 0x06e5 2408#define regHUBPREQ1_VMID_SETTINGS_0_BASE_IDX 2 2409#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS 0x06e6 2410#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2 2411#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH 0x06e7 2412#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 2413#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C 0x06e8 2414#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX 2 2415#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x06e9 2416#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 2417#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS 0x06ea 2418#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2 2419#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH 0x06eb 2420#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 2421#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C 0x06ec 2422#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX 2 2423#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x06ed 2424#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 2425#define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS 0x06ee 2426#define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX 2 2427#define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH 0x06ef 2428#define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 2429#define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C 0x06f0 2430#define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 2431#define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C 0x06f1 2432#define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 2433#define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS 0x06f2 2434#define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX 2 2435#define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH 0x06f3 2436#define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 2437#define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C 0x06f4 2438#define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 2439#define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C 0x06f5 2440#define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 2441#define regHUBPREQ1_DCSURF_SURFACE_CONTROL 0x06f6 2442#define regHUBPREQ1_DCSURF_SURFACE_CONTROL_BASE_IDX 2 2443#define regHUBPREQ1_DCSURF_FLIP_CONTROL 0x06f7 2444#define regHUBPREQ1_DCSURF_FLIP_CONTROL_BASE_IDX 2 2445#define regHUBPREQ1_DCSURF_FLIP_CONTROL2 0x06f8 2446#define regHUBPREQ1_DCSURF_FLIP_CONTROL2_BASE_IDX 2 2447#define regHUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT 0x06fb 2448#define regHUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX 2 2449#define regHUBPREQ1_DCSURF_SURFACE_INUSE 0x06fc 2450#define regHUBPREQ1_DCSURF_SURFACE_INUSE_BASE_IDX 2 2451#define regHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH 0x06fd 2452#define regHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX 2 2453#define regHUBPREQ1_DCSURF_SURFACE_INUSE_C 0x06fe 2454#define regHUBPREQ1_DCSURF_SURFACE_INUSE_C_BASE_IDX 2 2455#define regHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C 0x06ff 2456#define regHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX 2 2457#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE 0x0700 2458#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX 2 2459#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH 0x0701 2460#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX 2 2461#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C 0x0702 2462#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX 2 2463#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C 0x0703 2464#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX 2 2465#define regHUBPREQ1_DCN_EXPANSION_MODE 0x0704 2466#define regHUBPREQ1_DCN_EXPANSION_MODE_BASE_IDX 2 2467#define regHUBPREQ1_DCN_TTU_QOS_WM 0x0705 2468#define regHUBPREQ1_DCN_TTU_QOS_WM_BASE_IDX 2 2469#define regHUBPREQ1_DCN_GLOBAL_TTU_CNTL 0x0706 2470#define regHUBPREQ1_DCN_GLOBAL_TTU_CNTL_BASE_IDX 2 2471#define regHUBPREQ1_DCN_SURF0_TTU_CNTL0 0x0707 2472#define regHUBPREQ1_DCN_SURF0_TTU_CNTL0_BASE_IDX 2 2473#define regHUBPREQ1_DCN_SURF0_TTU_CNTL1 0x0708 2474#define regHUBPREQ1_DCN_SURF0_TTU_CNTL1_BASE_IDX 2 2475#define regHUBPREQ1_DCN_SURF1_TTU_CNTL0 0x0709 2476#define regHUBPREQ1_DCN_SURF1_TTU_CNTL0_BASE_IDX 2 2477#define regHUBPREQ1_DCN_SURF1_TTU_CNTL1 0x070a 2478#define regHUBPREQ1_DCN_SURF1_TTU_CNTL1_BASE_IDX 2 2479#define regHUBPREQ1_DCN_CUR0_TTU_CNTL0 0x070b 2480#define regHUBPREQ1_DCN_CUR0_TTU_CNTL0_BASE_IDX 2 2481#define regHUBPREQ1_DCN_CUR0_TTU_CNTL1 0x070c 2482#define regHUBPREQ1_DCN_CUR0_TTU_CNTL1_BASE_IDX 2 2483#define regHUBPREQ1_DCN_CUR1_TTU_CNTL0 0x070d 2484#define regHUBPREQ1_DCN_CUR1_TTU_CNTL0_BASE_IDX 2 2485#define regHUBPREQ1_DCN_CUR1_TTU_CNTL1 0x070e 2486#define regHUBPREQ1_DCN_CUR1_TTU_CNTL1_BASE_IDX 2 2487#define regHUBPREQ1_DCN_DMDATA_VM_CNTL 0x070f 2488#define regHUBPREQ1_DCN_DMDATA_VM_CNTL_BASE_IDX 2 2489#define regHUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR 0x0710 2490#define regHUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 2 2491#define regHUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR 0x0711 2492#define regHUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 2 2493#define regHUBPREQ1_DCN_VM_MX_L1_TLB_CNTL 0x071e 2494#define regHUBPREQ1_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX 2 2495#define regHUBPREQ1_BLANK_OFFSET_0 0x071f 2496#define regHUBPREQ1_BLANK_OFFSET_0_BASE_IDX 2 2497#define regHUBPREQ1_BLANK_OFFSET_1 0x0720 2498#define regHUBPREQ1_BLANK_OFFSET_1_BASE_IDX 2 2499#define regHUBPREQ1_DST_DIMENSIONS 0x0721 2500#define regHUBPREQ1_DST_DIMENSIONS_BASE_IDX 2 2501#define regHUBPREQ1_DST_AFTER_SCALER 0x0722 2502#define regHUBPREQ1_DST_AFTER_SCALER_BASE_IDX 2 2503#define regHUBPREQ1_PREFETCH_SETTINGS 0x0723 2504#define regHUBPREQ1_PREFETCH_SETTINGS_BASE_IDX 2 2505#define regHUBPREQ1_PREFETCH_SETTINGS_C 0x0724 2506#define regHUBPREQ1_PREFETCH_SETTINGS_C_BASE_IDX 2 2507#define regHUBPREQ1_VBLANK_PARAMETERS_0 0x0725 2508#define regHUBPREQ1_VBLANK_PARAMETERS_0_BASE_IDX 2 2509#define regHUBPREQ1_VBLANK_PARAMETERS_1 0x0726 2510#define regHUBPREQ1_VBLANK_PARAMETERS_1_BASE_IDX 2 2511#define regHUBPREQ1_VBLANK_PARAMETERS_2 0x0727 2512#define regHUBPREQ1_VBLANK_PARAMETERS_2_BASE_IDX 2 2513#define regHUBPREQ1_VBLANK_PARAMETERS_3 0x0728 2514#define regHUBPREQ1_VBLANK_PARAMETERS_3_BASE_IDX 2 2515#define regHUBPREQ1_VBLANK_PARAMETERS_4 0x0729 2516#define regHUBPREQ1_VBLANK_PARAMETERS_4_BASE_IDX 2 2517#define regHUBPREQ1_FLIP_PARAMETERS_0 0x072a 2518#define regHUBPREQ1_FLIP_PARAMETERS_0_BASE_IDX 2 2519#define regHUBPREQ1_FLIP_PARAMETERS_1 0x072b 2520#define regHUBPREQ1_FLIP_PARAMETERS_1_BASE_IDX 2 2521#define regHUBPREQ1_FLIP_PARAMETERS_2 0x072c 2522#define regHUBPREQ1_FLIP_PARAMETERS_2_BASE_IDX 2 2523#define regHUBPREQ1_NOM_PARAMETERS_0 0x072d 2524#define regHUBPREQ1_NOM_PARAMETERS_0_BASE_IDX 2 2525#define regHUBPREQ1_NOM_PARAMETERS_1 0x072e 2526#define regHUBPREQ1_NOM_PARAMETERS_1_BASE_IDX 2 2527#define regHUBPREQ1_NOM_PARAMETERS_2 0x072f 2528#define regHUBPREQ1_NOM_PARAMETERS_2_BASE_IDX 2 2529#define regHUBPREQ1_NOM_PARAMETERS_3 0x0730 2530#define regHUBPREQ1_NOM_PARAMETERS_3_BASE_IDX 2 2531#define regHUBPREQ1_NOM_PARAMETERS_4 0x0731 2532#define regHUBPREQ1_NOM_PARAMETERS_4_BASE_IDX 2 2533#define regHUBPREQ1_NOM_PARAMETERS_5 0x0732 2534#define regHUBPREQ1_NOM_PARAMETERS_5_BASE_IDX 2 2535#define regHUBPREQ1_NOM_PARAMETERS_6 0x0733 2536#define regHUBPREQ1_NOM_PARAMETERS_6_BASE_IDX 2 2537#define regHUBPREQ1_NOM_PARAMETERS_7 0x0734 2538#define regHUBPREQ1_NOM_PARAMETERS_7_BASE_IDX 2 2539#define regHUBPREQ1_PER_LINE_DELIVERY_PRE 0x0735 2540#define regHUBPREQ1_PER_LINE_DELIVERY_PRE_BASE_IDX 2 2541#define regHUBPREQ1_PER_LINE_DELIVERY 0x0736 2542#define regHUBPREQ1_PER_LINE_DELIVERY_BASE_IDX 2 2543#define regHUBPREQ1_CURSOR_SETTINGS 0x0737 2544#define regHUBPREQ1_CURSOR_SETTINGS_BASE_IDX 2 2545#define regHUBPREQ1_REF_FREQ_TO_PIX_FREQ 0x0738 2546#define regHUBPREQ1_REF_FREQ_TO_PIX_FREQ_BASE_IDX 2 2547#define regHUBPREQ1_DST_Y_DELTA_DRQ_LIMIT 0x0739 2548#define regHUBPREQ1_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX 2 2549#define regHUBPREQ1_HUBPREQ_MEM_PWR_CTRL 0x073a 2550#define regHUBPREQ1_HUBPREQ_MEM_PWR_CTRL_BASE_IDX 2 2551#define regHUBPREQ1_HUBPREQ_MEM_PWR_STATUS 0x073b 2552#define regHUBPREQ1_HUBPREQ_MEM_PWR_STATUS_BASE_IDX 2 2553#define regHUBPREQ1_VBLANK_PARAMETERS_5 0x073e 2554#define regHUBPREQ1_VBLANK_PARAMETERS_5_BASE_IDX 2 2555#define regHUBPREQ1_VBLANK_PARAMETERS_6 0x073f 2556#define regHUBPREQ1_VBLANK_PARAMETERS_6_BASE_IDX 2 2557#define regHUBPREQ1_FLIP_PARAMETERS_3 0x0740 2558#define regHUBPREQ1_FLIP_PARAMETERS_3_BASE_IDX 2 2559#define regHUBPREQ1_FLIP_PARAMETERS_4 0x0741 2560#define regHUBPREQ1_FLIP_PARAMETERS_4_BASE_IDX 2 2561#define regHUBPREQ1_FLIP_PARAMETERS_5 0x0742 2562#define regHUBPREQ1_FLIP_PARAMETERS_5_BASE_IDX 2 2563#define regHUBPREQ1_FLIP_PARAMETERS_6 0x0743 2564#define regHUBPREQ1_FLIP_PARAMETERS_6_BASE_IDX 2 2565#define regHUBPREQ1_UCLK_PSTATE_FORCE 0x0744 2566#define regHUBPREQ1_UCLK_PSTATE_FORCE_BASE_IDX 2 2567#define regHUBPREQ1_HUBPREQ_STATUS_REG0 0x0745 2568#define regHUBPREQ1_HUBPREQ_STATUS_REG0_BASE_IDX 2 2569#define regHUBPREQ1_HUBPREQ_STATUS_REG1 0x0746 2570#define regHUBPREQ1_HUBPREQ_STATUS_REG1_BASE_IDX 2 2571#define regHUBPREQ1_HUBPREQ_STATUS_REG2 0x0747 2572#define regHUBPREQ1_HUBPREQ_STATUS_REG2_BASE_IDX 2 2573 2574 2575// addressBlock: dcn_dc_dcbubp1_dispdec_hubpret_dispdec 2576// base address: 0x370 2577#define regHUBPRET1_HUBPRET_CONTROL 0x0748 2578#define regHUBPRET1_HUBPRET_CONTROL_BASE_IDX 2 2579#define regHUBPRET1_HUBPRET_MEM_PWR_CTRL 0x0749 2580#define regHUBPRET1_HUBPRET_MEM_PWR_CTRL_BASE_IDX 2 2581#define regHUBPRET1_HUBPRET_MEM_PWR_STATUS 0x074a 2582#define regHUBPRET1_HUBPRET_MEM_PWR_STATUS_BASE_IDX 2 2583#define regHUBPRET1_HUBPRET_READ_LINE_CTRL0 0x074b 2584#define regHUBPRET1_HUBPRET_READ_LINE_CTRL0_BASE_IDX 2 2585#define regHUBPRET1_HUBPRET_READ_LINE_CTRL1 0x074c 2586#define regHUBPRET1_HUBPRET_READ_LINE_CTRL1_BASE_IDX 2 2587#define regHUBPRET1_HUBPRET_READ_LINE0 0x074d 2588#define regHUBPRET1_HUBPRET_READ_LINE0_BASE_IDX 2 2589#define regHUBPRET1_HUBPRET_READ_LINE1 0x074e 2590#define regHUBPRET1_HUBPRET_READ_LINE1_BASE_IDX 2 2591#define regHUBPRET1_HUBPRET_INTERRUPT 0x074f 2592#define regHUBPRET1_HUBPRET_INTERRUPT_BASE_IDX 2 2593#define regHUBPRET1_HUBPRET_READ_LINE_VALUE 0x0750 2594#define regHUBPRET1_HUBPRET_READ_LINE_VALUE_BASE_IDX 2 2595#define regHUBPRET1_HUBPRET_READ_LINE_STATUS 0x0751 2596#define regHUBPRET1_HUBPRET_READ_LINE_STATUS_BASE_IDX 2 2597 2598 2599// addressBlock: dcn_dc_dcbubp1_dispdec_cursor0_dispdec 2600// base address: 0x370 2601#define regCURSOR0_1_CURSOR_CONTROL 0x0754 2602#define regCURSOR0_1_CURSOR_CONTROL_BASE_IDX 2 2603#define regCURSOR0_1_CURSOR_SURFACE_ADDRESS 0x0755 2604#define regCURSOR0_1_CURSOR_SURFACE_ADDRESS_BASE_IDX 2 2605#define regCURSOR0_1_CURSOR_SURFACE_ADDRESS_HIGH 0x0756 2606#define regCURSOR0_1_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX 2 2607#define regCURSOR0_1_CURSOR_SIZE 0x0757 2608#define regCURSOR0_1_CURSOR_SIZE_BASE_IDX 2 2609#define regCURSOR0_1_CURSOR_POSITION 0x0758 2610#define regCURSOR0_1_CURSOR_POSITION_BASE_IDX 2 2611#define regCURSOR0_1_CURSOR_HOT_SPOT 0x0759 2612#define regCURSOR0_1_CURSOR_HOT_SPOT_BASE_IDX 2 2613#define regCURSOR0_1_CURSOR_STEREO_CONTROL 0x075a 2614#define regCURSOR0_1_CURSOR_STEREO_CONTROL_BASE_IDX 2 2615#define regCURSOR0_1_CURSOR_DST_OFFSET 0x075b 2616#define regCURSOR0_1_CURSOR_DST_OFFSET_BASE_IDX 2 2617#define regCURSOR0_1_CURSOR_MEM_PWR_CTRL 0x075c 2618#define regCURSOR0_1_CURSOR_MEM_PWR_CTRL_BASE_IDX 2 2619#define regCURSOR0_1_CURSOR_MEM_PWR_STATUS 0x075d 2620#define regCURSOR0_1_CURSOR_MEM_PWR_STATUS_BASE_IDX 2 2621#define regCURSOR0_1_DMDATA_ADDRESS_HIGH 0x075e 2622#define regCURSOR0_1_DMDATA_ADDRESS_HIGH_BASE_IDX 2 2623#define regCURSOR0_1_DMDATA_ADDRESS_LOW 0x075f 2624#define regCURSOR0_1_DMDATA_ADDRESS_LOW_BASE_IDX 2 2625#define regCURSOR0_1_DMDATA_CNTL 0x0760 2626#define regCURSOR0_1_DMDATA_CNTL_BASE_IDX 2 2627#define regCURSOR0_1_DMDATA_QOS_CNTL 0x0761 2628#define regCURSOR0_1_DMDATA_QOS_CNTL_BASE_IDX 2 2629#define regCURSOR0_1_DMDATA_STATUS 0x0762 2630#define regCURSOR0_1_DMDATA_STATUS_BASE_IDX 2 2631#define regCURSOR0_1_DMDATA_SW_CNTL 0x0763 2632#define regCURSOR0_1_DMDATA_SW_CNTL_BASE_IDX 2 2633#define regCURSOR0_1_DMDATA_SW_DATA 0x0764 2634#define regCURSOR0_1_DMDATA_SW_DATA_BASE_IDX 2 2635 2636 2637// addressBlock: dcn_dc_dcbubp2_dispdec_hubp_dispdec 2638// base address: 0x6e0 2639#define regHUBP2_DCSURF_SURFACE_CONFIG 0x079d 2640#define regHUBP2_DCSURF_SURFACE_CONFIG_BASE_IDX 2 2641#define regHUBP2_DCSURF_ADDR_CONFIG 0x079e 2642#define regHUBP2_DCSURF_ADDR_CONFIG_BASE_IDX 2 2643#define regHUBP2_DCSURF_TILING_CONFIG 0x079f 2644#define regHUBP2_DCSURF_TILING_CONFIG_BASE_IDX 2 2645#define regHUBP2_DCSURF_PRI_VIEWPORT_START 0x07a1 2646#define regHUBP2_DCSURF_PRI_VIEWPORT_START_BASE_IDX 2 2647#define regHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION 0x07a2 2648#define regHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2 2649#define regHUBP2_DCSURF_PRI_VIEWPORT_START_C 0x07a3 2650#define regHUBP2_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX 2 2651#define regHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C 0x07a4 2652#define regHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX 2 2653#define regHUBP2_DCSURF_SEC_VIEWPORT_START 0x07a5 2654#define regHUBP2_DCSURF_SEC_VIEWPORT_START_BASE_IDX 2 2655#define regHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION 0x07a6 2656#define regHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX 2 2657#define regHUBP2_DCSURF_SEC_VIEWPORT_START_C 0x07a7 2658#define regHUBP2_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX 2 2659#define regHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C 0x07a8 2660#define regHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX 2 2661#define regHUBP2_DCHUBP_REQ_SIZE_CONFIG 0x07a9 2662#define regHUBP2_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX 2 2663#define regHUBP2_DCHUBP_REQ_SIZE_CONFIG_C 0x07aa 2664#define regHUBP2_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX 2 2665#define regHUBP2_DCHUBP_CNTL 0x07ab 2666#define regHUBP2_DCHUBP_CNTL_BASE_IDX 2 2667#define regHUBP2_HUBP_CLK_CNTL 0x07ac 2668#define regHUBP2_HUBP_CLK_CNTL_BASE_IDX 2 2669#define regHUBP2_DCHUBP_VMPG_CONFIG 0x07ad 2670#define regHUBP2_DCHUBP_VMPG_CONFIG_BASE_IDX 2 2671#define regHUBP2_DCHUBP_MALL_CONFIG 0x07ae 2672#define regHUBP2_DCHUBP_MALL_CONFIG_BASE_IDX 2 2673#define regHUBP2_DCHUBP_MALL_SUB_VP 0x07af 2674#define regHUBP2_DCHUBP_MALL_SUB_VP_BASE_IDX 2 2675#define regHUBP2_HUBPREQ_DEBUG_DB 0x07b0 2676#define regHUBP2_HUBPREQ_DEBUG_DB_BASE_IDX 2 2677#define regHUBP2_HUBPREQ_DEBUG 0x07b1 2678#define regHUBP2_HUBPREQ_DEBUG_BASE_IDX 2 2679#define regHUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK 0x07b5 2680#define regHUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX 2 2681#define regHUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK 0x07b6 2682#define regHUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX 2 2683#define regHUBP2_HUBP_MALL_STATUS 0x07b7 2684#define regHUBP2_HUBP_MALL_STATUS_BASE_IDX 2 2685 2686 2687// addressBlock: dcn_dc_dcbubp2_dispdec_hubpreq_dispdec 2688// base address: 0x6e0 2689#define regHUBPREQ2_DCSURF_SURFACE_PITCH 0x07bf 2690#define regHUBPREQ2_DCSURF_SURFACE_PITCH_BASE_IDX 2 2691#define regHUBPREQ2_DCSURF_SURFACE_PITCH_C 0x07c0 2692#define regHUBPREQ2_DCSURF_SURFACE_PITCH_C_BASE_IDX 2 2693#define regHUBPREQ2_VMID_SETTINGS_0 0x07c1 2694#define regHUBPREQ2_VMID_SETTINGS_0_BASE_IDX 2 2695#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS 0x07c2 2696#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2 2697#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH 0x07c3 2698#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 2699#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C 0x07c4 2700#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX 2 2701#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x07c5 2702#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 2703#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS 0x07c6 2704#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2 2705#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH 0x07c7 2706#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 2707#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C 0x07c8 2708#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX 2 2709#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x07c9 2710#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 2711#define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS 0x07ca 2712#define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX 2 2713#define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH 0x07cb 2714#define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 2715#define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C 0x07cc 2716#define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 2717#define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C 0x07cd 2718#define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 2719#define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS 0x07ce 2720#define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX 2 2721#define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH 0x07cf 2722#define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 2723#define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C 0x07d0 2724#define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 2725#define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C 0x07d1 2726#define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 2727#define regHUBPREQ2_DCSURF_SURFACE_CONTROL 0x07d2 2728#define regHUBPREQ2_DCSURF_SURFACE_CONTROL_BASE_IDX 2 2729#define regHUBPREQ2_DCSURF_FLIP_CONTROL 0x07d3 2730#define regHUBPREQ2_DCSURF_FLIP_CONTROL_BASE_IDX 2 2731#define regHUBPREQ2_DCSURF_FLIP_CONTROL2 0x07d4 2732#define regHUBPREQ2_DCSURF_FLIP_CONTROL2_BASE_IDX 2 2733#define regHUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT 0x07d7 2734#define regHUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX 2 2735#define regHUBPREQ2_DCSURF_SURFACE_INUSE 0x07d8 2736#define regHUBPREQ2_DCSURF_SURFACE_INUSE_BASE_IDX 2 2737#define regHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH 0x07d9 2738#define regHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX 2 2739#define regHUBPREQ2_DCSURF_SURFACE_INUSE_C 0x07da 2740#define regHUBPREQ2_DCSURF_SURFACE_INUSE_C_BASE_IDX 2 2741#define regHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C 0x07db 2742#define regHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX 2 2743#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE 0x07dc 2744#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX 2 2745#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH 0x07dd 2746#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX 2 2747#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C 0x07de 2748#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX 2 2749#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C 0x07df 2750#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX 2 2751#define regHUBPREQ2_DCN_EXPANSION_MODE 0x07e0 2752#define regHUBPREQ2_DCN_EXPANSION_MODE_BASE_IDX 2 2753#define regHUBPREQ2_DCN_TTU_QOS_WM 0x07e1 2754#define regHUBPREQ2_DCN_TTU_QOS_WM_BASE_IDX 2 2755#define regHUBPREQ2_DCN_GLOBAL_TTU_CNTL 0x07e2 2756#define regHUBPREQ2_DCN_GLOBAL_TTU_CNTL_BASE_IDX 2 2757#define regHUBPREQ2_DCN_SURF0_TTU_CNTL0 0x07e3 2758#define regHUBPREQ2_DCN_SURF0_TTU_CNTL0_BASE_IDX 2 2759#define regHUBPREQ2_DCN_SURF0_TTU_CNTL1 0x07e4 2760#define regHUBPREQ2_DCN_SURF0_TTU_CNTL1_BASE_IDX 2 2761#define regHUBPREQ2_DCN_SURF1_TTU_CNTL0 0x07e5 2762#define regHUBPREQ2_DCN_SURF1_TTU_CNTL0_BASE_IDX 2 2763#define regHUBPREQ2_DCN_SURF1_TTU_CNTL1 0x07e6 2764#define regHUBPREQ2_DCN_SURF1_TTU_CNTL1_BASE_IDX 2 2765#define regHUBPREQ2_DCN_CUR0_TTU_CNTL0 0x07e7 2766#define regHUBPREQ2_DCN_CUR0_TTU_CNTL0_BASE_IDX 2 2767#define regHUBPREQ2_DCN_CUR0_TTU_CNTL1 0x07e8 2768#define regHUBPREQ2_DCN_CUR0_TTU_CNTL1_BASE_IDX 2 2769#define regHUBPREQ2_DCN_CUR1_TTU_CNTL0 0x07e9 2770#define regHUBPREQ2_DCN_CUR1_TTU_CNTL0_BASE_IDX 2 2771#define regHUBPREQ2_DCN_CUR1_TTU_CNTL1 0x07ea 2772#define regHUBPREQ2_DCN_CUR1_TTU_CNTL1_BASE_IDX 2 2773#define regHUBPREQ2_DCN_DMDATA_VM_CNTL 0x07eb 2774#define regHUBPREQ2_DCN_DMDATA_VM_CNTL_BASE_IDX 2 2775#define regHUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR 0x07ec 2776#define regHUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 2 2777#define regHUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR 0x07ed 2778#define regHUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 2 2779#define regHUBPREQ2_DCN_VM_MX_L1_TLB_CNTL 0x07fa 2780#define regHUBPREQ2_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX 2 2781#define regHUBPREQ2_BLANK_OFFSET_0 0x07fb 2782#define regHUBPREQ2_BLANK_OFFSET_0_BASE_IDX 2 2783#define regHUBPREQ2_BLANK_OFFSET_1 0x07fc 2784#define regHUBPREQ2_BLANK_OFFSET_1_BASE_IDX 2 2785#define regHUBPREQ2_DST_DIMENSIONS 0x07fd 2786#define regHUBPREQ2_DST_DIMENSIONS_BASE_IDX 2 2787#define regHUBPREQ2_DST_AFTER_SCALER 0x07fe 2788#define regHUBPREQ2_DST_AFTER_SCALER_BASE_IDX 2 2789#define regHUBPREQ2_PREFETCH_SETTINGS 0x07ff 2790#define regHUBPREQ2_PREFETCH_SETTINGS_BASE_IDX 2 2791#define regHUBPREQ2_PREFETCH_SETTINGS_C 0x0800 2792#define regHUBPREQ2_PREFETCH_SETTINGS_C_BASE_IDX 2 2793#define regHUBPREQ2_VBLANK_PARAMETERS_0 0x0801 2794#define regHUBPREQ2_VBLANK_PARAMETERS_0_BASE_IDX 2 2795#define regHUBPREQ2_VBLANK_PARAMETERS_1 0x0802 2796#define regHUBPREQ2_VBLANK_PARAMETERS_1_BASE_IDX 2 2797#define regHUBPREQ2_VBLANK_PARAMETERS_2 0x0803 2798#define regHUBPREQ2_VBLANK_PARAMETERS_2_BASE_IDX 2 2799#define regHUBPREQ2_VBLANK_PARAMETERS_3 0x0804 2800#define regHUBPREQ2_VBLANK_PARAMETERS_3_BASE_IDX 2 2801#define regHUBPREQ2_VBLANK_PARAMETERS_4 0x0805 2802#define regHUBPREQ2_VBLANK_PARAMETERS_4_BASE_IDX 2 2803#define regHUBPREQ2_FLIP_PARAMETERS_0 0x0806 2804#define regHUBPREQ2_FLIP_PARAMETERS_0_BASE_IDX 2 2805#define regHUBPREQ2_FLIP_PARAMETERS_1 0x0807 2806#define regHUBPREQ2_FLIP_PARAMETERS_1_BASE_IDX 2 2807#define regHUBPREQ2_FLIP_PARAMETERS_2 0x0808 2808#define regHUBPREQ2_FLIP_PARAMETERS_2_BASE_IDX 2 2809#define regHUBPREQ2_NOM_PARAMETERS_0 0x0809 2810#define regHUBPREQ2_NOM_PARAMETERS_0_BASE_IDX 2 2811#define regHUBPREQ2_NOM_PARAMETERS_1 0x080a 2812#define regHUBPREQ2_NOM_PARAMETERS_1_BASE_IDX 2 2813#define regHUBPREQ2_NOM_PARAMETERS_2 0x080b 2814#define regHUBPREQ2_NOM_PARAMETERS_2_BASE_IDX 2 2815#define regHUBPREQ2_NOM_PARAMETERS_3 0x080c 2816#define regHUBPREQ2_NOM_PARAMETERS_3_BASE_IDX 2 2817#define regHUBPREQ2_NOM_PARAMETERS_4 0x080d 2818#define regHUBPREQ2_NOM_PARAMETERS_4_BASE_IDX 2 2819#define regHUBPREQ2_NOM_PARAMETERS_5 0x080e 2820#define regHUBPREQ2_NOM_PARAMETERS_5_BASE_IDX 2 2821#define regHUBPREQ2_NOM_PARAMETERS_6 0x080f 2822#define regHUBPREQ2_NOM_PARAMETERS_6_BASE_IDX 2 2823#define regHUBPREQ2_NOM_PARAMETERS_7 0x0810 2824#define regHUBPREQ2_NOM_PARAMETERS_7_BASE_IDX 2 2825#define regHUBPREQ2_PER_LINE_DELIVERY_PRE 0x0811 2826#define regHUBPREQ2_PER_LINE_DELIVERY_PRE_BASE_IDX 2 2827#define regHUBPREQ2_PER_LINE_DELIVERY 0x0812 2828#define regHUBPREQ2_PER_LINE_DELIVERY_BASE_IDX 2 2829#define regHUBPREQ2_CURSOR_SETTINGS 0x0813 2830#define regHUBPREQ2_CURSOR_SETTINGS_BASE_IDX 2 2831#define regHUBPREQ2_REF_FREQ_TO_PIX_FREQ 0x0814 2832#define regHUBPREQ2_REF_FREQ_TO_PIX_FREQ_BASE_IDX 2 2833#define regHUBPREQ2_DST_Y_DELTA_DRQ_LIMIT 0x0815 2834#define regHUBPREQ2_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX 2 2835#define regHUBPREQ2_HUBPREQ_MEM_PWR_CTRL 0x0816 2836#define regHUBPREQ2_HUBPREQ_MEM_PWR_CTRL_BASE_IDX 2 2837#define regHUBPREQ2_HUBPREQ_MEM_PWR_STATUS 0x0817 2838#define regHUBPREQ2_HUBPREQ_MEM_PWR_STATUS_BASE_IDX 2 2839#define regHUBPREQ2_VBLANK_PARAMETERS_5 0x081a 2840#define regHUBPREQ2_VBLANK_PARAMETERS_5_BASE_IDX 2 2841#define regHUBPREQ2_VBLANK_PARAMETERS_6 0x081b 2842#define regHUBPREQ2_VBLANK_PARAMETERS_6_BASE_IDX 2 2843#define regHUBPREQ2_FLIP_PARAMETERS_3 0x081c 2844#define regHUBPREQ2_FLIP_PARAMETERS_3_BASE_IDX 2 2845#define regHUBPREQ2_FLIP_PARAMETERS_4 0x081d 2846#define regHUBPREQ2_FLIP_PARAMETERS_4_BASE_IDX 2 2847#define regHUBPREQ2_FLIP_PARAMETERS_5 0x081e 2848#define regHUBPREQ2_FLIP_PARAMETERS_5_BASE_IDX 2 2849#define regHUBPREQ2_FLIP_PARAMETERS_6 0x081f 2850#define regHUBPREQ2_FLIP_PARAMETERS_6_BASE_IDX 2 2851#define regHUBPREQ2_UCLK_PSTATE_FORCE 0x0820 2852#define regHUBPREQ2_UCLK_PSTATE_FORCE_BASE_IDX 2 2853#define regHUBPREQ2_HUBPREQ_STATUS_REG0 0x0821 2854#define regHUBPREQ2_HUBPREQ_STATUS_REG0_BASE_IDX 2 2855#define regHUBPREQ2_HUBPREQ_STATUS_REG1 0x0822 2856#define regHUBPREQ2_HUBPREQ_STATUS_REG1_BASE_IDX 2 2857#define regHUBPREQ2_HUBPREQ_STATUS_REG2 0x0823 2858#define regHUBPREQ2_HUBPREQ_STATUS_REG2_BASE_IDX 2 2859 2860 2861// addressBlock: dcn_dc_dcbubp2_dispdec_hubpret_dispdec 2862// base address: 0x6e0 2863#define regHUBPRET2_HUBPRET_CONTROL 0x0824 2864#define regHUBPRET2_HUBPRET_CONTROL_BASE_IDX 2 2865#define regHUBPRET2_HUBPRET_MEM_PWR_CTRL 0x0825 2866#define regHUBPRET2_HUBPRET_MEM_PWR_CTRL_BASE_IDX 2 2867#define regHUBPRET2_HUBPRET_MEM_PWR_STATUS 0x0826 2868#define regHUBPRET2_HUBPRET_MEM_PWR_STATUS_BASE_IDX 2 2869#define regHUBPRET2_HUBPRET_READ_LINE_CTRL0 0x0827 2870#define regHUBPRET2_HUBPRET_READ_LINE_CTRL0_BASE_IDX 2 2871#define regHUBPRET2_HUBPRET_READ_LINE_CTRL1 0x0828 2872#define regHUBPRET2_HUBPRET_READ_LINE_CTRL1_BASE_IDX 2 2873#define regHUBPRET2_HUBPRET_READ_LINE0 0x0829 2874#define regHUBPRET2_HUBPRET_READ_LINE0_BASE_IDX 2 2875#define regHUBPRET2_HUBPRET_READ_LINE1 0x082a 2876#define regHUBPRET2_HUBPRET_READ_LINE1_BASE_IDX 2 2877#define regHUBPRET2_HUBPRET_INTERRUPT 0x082b 2878#define regHUBPRET2_HUBPRET_INTERRUPT_BASE_IDX 2 2879#define regHUBPRET2_HUBPRET_READ_LINE_VALUE 0x082c 2880#define regHUBPRET2_HUBPRET_READ_LINE_VALUE_BASE_IDX 2 2881#define regHUBPRET2_HUBPRET_READ_LINE_STATUS 0x082d 2882#define regHUBPRET2_HUBPRET_READ_LINE_STATUS_BASE_IDX 2 2883 2884 2885// addressBlock: dcn_dc_dcbubp2_dispdec_cursor0_dispdec 2886// base address: 0x6e0 2887#define regCURSOR0_2_CURSOR_CONTROL 0x0830 2888#define regCURSOR0_2_CURSOR_CONTROL_BASE_IDX 2 2889#define regCURSOR0_2_CURSOR_SURFACE_ADDRESS 0x0831 2890#define regCURSOR0_2_CURSOR_SURFACE_ADDRESS_BASE_IDX 2 2891#define regCURSOR0_2_CURSOR_SURFACE_ADDRESS_HIGH 0x0832 2892#define regCURSOR0_2_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX 2 2893#define regCURSOR0_2_CURSOR_SIZE 0x0833 2894#define regCURSOR0_2_CURSOR_SIZE_BASE_IDX 2 2895#define regCURSOR0_2_CURSOR_POSITION 0x0834 2896#define regCURSOR0_2_CURSOR_POSITION_BASE_IDX 2 2897#define regCURSOR0_2_CURSOR_HOT_SPOT 0x0835 2898#define regCURSOR0_2_CURSOR_HOT_SPOT_BASE_IDX 2 2899#define regCURSOR0_2_CURSOR_STEREO_CONTROL 0x0836 2900#define regCURSOR0_2_CURSOR_STEREO_CONTROL_BASE_IDX 2 2901#define regCURSOR0_2_CURSOR_DST_OFFSET 0x0837 2902#define regCURSOR0_2_CURSOR_DST_OFFSET_BASE_IDX 2 2903#define regCURSOR0_2_CURSOR_MEM_PWR_CTRL 0x0838 2904#define regCURSOR0_2_CURSOR_MEM_PWR_CTRL_BASE_IDX 2 2905#define regCURSOR0_2_CURSOR_MEM_PWR_STATUS 0x0839 2906#define regCURSOR0_2_CURSOR_MEM_PWR_STATUS_BASE_IDX 2 2907#define regCURSOR0_2_DMDATA_ADDRESS_HIGH 0x083a 2908#define regCURSOR0_2_DMDATA_ADDRESS_HIGH_BASE_IDX 2 2909#define regCURSOR0_2_DMDATA_ADDRESS_LOW 0x083b 2910#define regCURSOR0_2_DMDATA_ADDRESS_LOW_BASE_IDX 2 2911#define regCURSOR0_2_DMDATA_CNTL 0x083c 2912#define regCURSOR0_2_DMDATA_CNTL_BASE_IDX 2 2913#define regCURSOR0_2_DMDATA_QOS_CNTL 0x083d 2914#define regCURSOR0_2_DMDATA_QOS_CNTL_BASE_IDX 2 2915#define regCURSOR0_2_DMDATA_STATUS 0x083e 2916#define regCURSOR0_2_DMDATA_STATUS_BASE_IDX 2 2917#define regCURSOR0_2_DMDATA_SW_CNTL 0x083f 2918#define regCURSOR0_2_DMDATA_SW_CNTL_BASE_IDX 2 2919#define regCURSOR0_2_DMDATA_SW_DATA 0x0840 2920#define regCURSOR0_2_DMDATA_SW_DATA_BASE_IDX 2 2921 2922 2923// addressBlock: dcn_dc_dcbubp3_dispdec_hubp_dispdec 2924// base address: 0xa50 2925#define regHUBP3_DCSURF_SURFACE_CONFIG 0x0879 2926#define regHUBP3_DCSURF_SURFACE_CONFIG_BASE_IDX 2 2927#define regHUBP3_DCSURF_ADDR_CONFIG 0x087a 2928#define regHUBP3_DCSURF_ADDR_CONFIG_BASE_IDX 2 2929#define regHUBP3_DCSURF_TILING_CONFIG 0x087b 2930#define regHUBP3_DCSURF_TILING_CONFIG_BASE_IDX 2 2931#define regHUBP3_DCSURF_PRI_VIEWPORT_START 0x087d 2932#define regHUBP3_DCSURF_PRI_VIEWPORT_START_BASE_IDX 2 2933#define regHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION 0x087e 2934#define regHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2 2935#define regHUBP3_DCSURF_PRI_VIEWPORT_START_C 0x087f 2936#define regHUBP3_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX 2 2937#define regHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C 0x0880 2938#define regHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX 2 2939#define regHUBP3_DCSURF_SEC_VIEWPORT_START 0x0881 2940#define regHUBP3_DCSURF_SEC_VIEWPORT_START_BASE_IDX 2 2941#define regHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION 0x0882 2942#define regHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX 2 2943#define regHUBP3_DCSURF_SEC_VIEWPORT_START_C 0x0883 2944#define regHUBP3_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX 2 2945#define regHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C 0x0884 2946#define regHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX 2 2947#define regHUBP3_DCHUBP_REQ_SIZE_CONFIG 0x0885 2948#define regHUBP3_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX 2 2949#define regHUBP3_DCHUBP_REQ_SIZE_CONFIG_C 0x0886 2950#define regHUBP3_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX 2 2951#define regHUBP3_DCHUBP_CNTL 0x0887 2952#define regHUBP3_DCHUBP_CNTL_BASE_IDX 2 2953#define regHUBP3_HUBP_CLK_CNTL 0x0888 2954#define regHUBP3_HUBP_CLK_CNTL_BASE_IDX 2 2955#define regHUBP3_DCHUBP_VMPG_CONFIG 0x0889 2956#define regHUBP3_DCHUBP_VMPG_CONFIG_BASE_IDX 2 2957#define regHUBP3_DCHUBP_MALL_CONFIG 0x088a 2958#define regHUBP3_DCHUBP_MALL_CONFIG_BASE_IDX 2 2959#define regHUBP3_DCHUBP_MALL_SUB_VP 0x088b 2960#define regHUBP3_DCHUBP_MALL_SUB_VP_BASE_IDX 2 2961#define regHUBP3_HUBPREQ_DEBUG_DB 0x088c 2962#define regHUBP3_HUBPREQ_DEBUG_DB_BASE_IDX 2 2963#define regHUBP3_HUBPREQ_DEBUG 0x088d 2964#define regHUBP3_HUBPREQ_DEBUG_BASE_IDX 2 2965#define regHUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK 0x0891 2966#define regHUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX 2 2967#define regHUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK 0x0892 2968#define regHUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX 2 2969#define regHUBP3_HUBP_MALL_STATUS 0x0893 2970#define regHUBP3_HUBP_MALL_STATUS_BASE_IDX 2 2971 2972 2973// addressBlock: dcn_dc_dcbubp3_dispdec_hubpreq_dispdec 2974// base address: 0xa50 2975#define regHUBPREQ3_DCSURF_SURFACE_PITCH 0x089b 2976#define regHUBPREQ3_DCSURF_SURFACE_PITCH_BASE_IDX 2 2977#define regHUBPREQ3_DCSURF_SURFACE_PITCH_C 0x089c 2978#define regHUBPREQ3_DCSURF_SURFACE_PITCH_C_BASE_IDX 2 2979#define regHUBPREQ3_VMID_SETTINGS_0 0x089d 2980#define regHUBPREQ3_VMID_SETTINGS_0_BASE_IDX 2 2981#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS 0x089e 2982#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2 2983#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH 0x089f 2984#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 2985#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C 0x08a0 2986#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX 2 2987#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x08a1 2988#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 2989#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS 0x08a2 2990#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2 2991#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH 0x08a3 2992#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 2993#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C 0x08a4 2994#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX 2 2995#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x08a5 2996#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 2997#define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS 0x08a6 2998#define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX 2 2999#define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH 0x08a7 3000#define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 3001#define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C 0x08a8 3002#define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 3003#define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C 0x08a9 3004#define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 3005#define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS 0x08aa 3006#define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX 2 3007#define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH 0x08ab 3008#define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 3009#define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C 0x08ac 3010#define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 3011#define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C 0x08ad 3012#define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 3013#define regHUBPREQ3_DCSURF_SURFACE_CONTROL 0x08ae 3014#define regHUBPREQ3_DCSURF_SURFACE_CONTROL_BASE_IDX 2 3015#define regHUBPREQ3_DCSURF_FLIP_CONTROL 0x08af 3016#define regHUBPREQ3_DCSURF_FLIP_CONTROL_BASE_IDX 2 3017#define regHUBPREQ3_DCSURF_FLIP_CONTROL2 0x08b0 3018#define regHUBPREQ3_DCSURF_FLIP_CONTROL2_BASE_IDX 2 3019#define regHUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT 0x08b3 3020#define regHUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX 2 3021#define regHUBPREQ3_DCSURF_SURFACE_INUSE 0x08b4 3022#define regHUBPREQ3_DCSURF_SURFACE_INUSE_BASE_IDX 2 3023#define regHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH 0x08b5 3024#define regHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX 2 3025#define regHUBPREQ3_DCSURF_SURFACE_INUSE_C 0x08b6 3026#define regHUBPREQ3_DCSURF_SURFACE_INUSE_C_BASE_IDX 2 3027#define regHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C 0x08b7 3028#define regHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX 2 3029#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE 0x08b8 3030#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX 2 3031#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH 0x08b9 3032#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX 2 3033#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C 0x08ba 3034#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX 2 3035#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C 0x08bb 3036#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX 2 3037#define regHUBPREQ3_DCN_EXPANSION_MODE 0x08bc 3038#define regHUBPREQ3_DCN_EXPANSION_MODE_BASE_IDX 2 3039#define regHUBPREQ3_DCN_TTU_QOS_WM 0x08bd 3040#define regHUBPREQ3_DCN_TTU_QOS_WM_BASE_IDX 2 3041#define regHUBPREQ3_DCN_GLOBAL_TTU_CNTL 0x08be 3042#define regHUBPREQ3_DCN_GLOBAL_TTU_CNTL_BASE_IDX 2 3043#define regHUBPREQ3_DCN_SURF0_TTU_CNTL0 0x08bf 3044#define regHUBPREQ3_DCN_SURF0_TTU_CNTL0_BASE_IDX 2 3045#define regHUBPREQ3_DCN_SURF0_TTU_CNTL1 0x08c0 3046#define regHUBPREQ3_DCN_SURF0_TTU_CNTL1_BASE_IDX 2 3047#define regHUBPREQ3_DCN_SURF1_TTU_CNTL0 0x08c1 3048#define regHUBPREQ3_DCN_SURF1_TTU_CNTL0_BASE_IDX 2 3049#define regHUBPREQ3_DCN_SURF1_TTU_CNTL1 0x08c2 3050#define regHUBPREQ3_DCN_SURF1_TTU_CNTL1_BASE_IDX 2 3051#define regHUBPREQ3_DCN_CUR0_TTU_CNTL0 0x08c3 3052#define regHUBPREQ3_DCN_CUR0_TTU_CNTL0_BASE_IDX 2 3053#define regHUBPREQ3_DCN_CUR0_TTU_CNTL1 0x08c4 3054#define regHUBPREQ3_DCN_CUR0_TTU_CNTL1_BASE_IDX 2 3055#define regHUBPREQ3_DCN_CUR1_TTU_CNTL0 0x08c5 3056#define regHUBPREQ3_DCN_CUR1_TTU_CNTL0_BASE_IDX 2 3057#define regHUBPREQ3_DCN_CUR1_TTU_CNTL1 0x08c6 3058#define regHUBPREQ3_DCN_CUR1_TTU_CNTL1_BASE_IDX 2 3059#define regHUBPREQ3_DCN_DMDATA_VM_CNTL 0x08c7 3060#define regHUBPREQ3_DCN_DMDATA_VM_CNTL_BASE_IDX 2 3061#define regHUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR 0x08c8 3062#define regHUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 2 3063#define regHUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR 0x08c9 3064#define regHUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 2 3065#define regHUBPREQ3_DCN_VM_MX_L1_TLB_CNTL 0x08d6 3066#define regHUBPREQ3_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX 2 3067#define regHUBPREQ3_BLANK_OFFSET_0 0x08d7 3068#define regHUBPREQ3_BLANK_OFFSET_0_BASE_IDX 2 3069#define regHUBPREQ3_BLANK_OFFSET_1 0x08d8 3070#define regHUBPREQ3_BLANK_OFFSET_1_BASE_IDX 2 3071#define regHUBPREQ3_DST_DIMENSIONS 0x08d9 3072#define regHUBPREQ3_DST_DIMENSIONS_BASE_IDX 2 3073#define regHUBPREQ3_DST_AFTER_SCALER 0x08da 3074#define regHUBPREQ3_DST_AFTER_SCALER_BASE_IDX 2 3075#define regHUBPREQ3_PREFETCH_SETTINGS 0x08db 3076#define regHUBPREQ3_PREFETCH_SETTINGS_BASE_IDX 2 3077#define regHUBPREQ3_PREFETCH_SETTINGS_C 0x08dc 3078#define regHUBPREQ3_PREFETCH_SETTINGS_C_BASE_IDX 2 3079#define regHUBPREQ3_VBLANK_PARAMETERS_0 0x08dd 3080#define regHUBPREQ3_VBLANK_PARAMETERS_0_BASE_IDX 2 3081#define regHUBPREQ3_VBLANK_PARAMETERS_1 0x08de 3082#define regHUBPREQ3_VBLANK_PARAMETERS_1_BASE_IDX 2 3083#define regHUBPREQ3_VBLANK_PARAMETERS_2 0x08df 3084#define regHUBPREQ3_VBLANK_PARAMETERS_2_BASE_IDX 2 3085#define regHUBPREQ3_VBLANK_PARAMETERS_3 0x08e0 3086#define regHUBPREQ3_VBLANK_PARAMETERS_3_BASE_IDX 2 3087#define regHUBPREQ3_VBLANK_PARAMETERS_4 0x08e1 3088#define regHUBPREQ3_VBLANK_PARAMETERS_4_BASE_IDX 2 3089#define regHUBPREQ3_FLIP_PARAMETERS_0 0x08e2 3090#define regHUBPREQ3_FLIP_PARAMETERS_0_BASE_IDX 2 3091#define regHUBPREQ3_FLIP_PARAMETERS_1 0x08e3 3092#define regHUBPREQ3_FLIP_PARAMETERS_1_BASE_IDX 2 3093#define regHUBPREQ3_FLIP_PARAMETERS_2 0x08e4 3094#define regHUBPREQ3_FLIP_PARAMETERS_2_BASE_IDX 2 3095#define regHUBPREQ3_NOM_PARAMETERS_0 0x08e5 3096#define regHUBPREQ3_NOM_PARAMETERS_0_BASE_IDX 2 3097#define regHUBPREQ3_NOM_PARAMETERS_1 0x08e6 3098#define regHUBPREQ3_NOM_PARAMETERS_1_BASE_IDX 2 3099#define regHUBPREQ3_NOM_PARAMETERS_2 0x08e7 3100#define regHUBPREQ3_NOM_PARAMETERS_2_BASE_IDX 2 3101#define regHUBPREQ3_NOM_PARAMETERS_3 0x08e8 3102#define regHUBPREQ3_NOM_PARAMETERS_3_BASE_IDX 2 3103#define regHUBPREQ3_NOM_PARAMETERS_4 0x08e9 3104#define regHUBPREQ3_NOM_PARAMETERS_4_BASE_IDX 2 3105#define regHUBPREQ3_NOM_PARAMETERS_5 0x08ea 3106#define regHUBPREQ3_NOM_PARAMETERS_5_BASE_IDX 2 3107#define regHUBPREQ3_NOM_PARAMETERS_6 0x08eb 3108#define regHUBPREQ3_NOM_PARAMETERS_6_BASE_IDX 2 3109#define regHUBPREQ3_NOM_PARAMETERS_7 0x08ec 3110#define regHUBPREQ3_NOM_PARAMETERS_7_BASE_IDX 2 3111#define regHUBPREQ3_PER_LINE_DELIVERY_PRE 0x08ed 3112#define regHUBPREQ3_PER_LINE_DELIVERY_PRE_BASE_IDX 2 3113#define regHUBPREQ3_PER_LINE_DELIVERY 0x08ee 3114#define regHUBPREQ3_PER_LINE_DELIVERY_BASE_IDX 2 3115#define regHUBPREQ3_CURSOR_SETTINGS 0x08ef 3116#define regHUBPREQ3_CURSOR_SETTINGS_BASE_IDX 2 3117#define regHUBPREQ3_REF_FREQ_TO_PIX_FREQ 0x08f0 3118#define regHUBPREQ3_REF_FREQ_TO_PIX_FREQ_BASE_IDX 2 3119#define regHUBPREQ3_DST_Y_DELTA_DRQ_LIMIT 0x08f1 3120#define regHUBPREQ3_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX 2 3121#define regHUBPREQ3_HUBPREQ_MEM_PWR_CTRL 0x08f2 3122#define regHUBPREQ3_HUBPREQ_MEM_PWR_CTRL_BASE_IDX 2 3123#define regHUBPREQ3_HUBPREQ_MEM_PWR_STATUS 0x08f3 3124#define regHUBPREQ3_HUBPREQ_MEM_PWR_STATUS_BASE_IDX 2 3125#define regHUBPREQ3_VBLANK_PARAMETERS_5 0x08f6 3126#define regHUBPREQ3_VBLANK_PARAMETERS_5_BASE_IDX 2 3127#define regHUBPREQ3_VBLANK_PARAMETERS_6 0x08f7 3128#define regHUBPREQ3_VBLANK_PARAMETERS_6_BASE_IDX 2 3129#define regHUBPREQ3_FLIP_PARAMETERS_3 0x08f8 3130#define regHUBPREQ3_FLIP_PARAMETERS_3_BASE_IDX 2 3131#define regHUBPREQ3_FLIP_PARAMETERS_4 0x08f9 3132#define regHUBPREQ3_FLIP_PARAMETERS_4_BASE_IDX 2 3133#define regHUBPREQ3_FLIP_PARAMETERS_5 0x08fa 3134#define regHUBPREQ3_FLIP_PARAMETERS_5_BASE_IDX 2 3135#define regHUBPREQ3_FLIP_PARAMETERS_6 0x08fb 3136#define regHUBPREQ3_FLIP_PARAMETERS_6_BASE_IDX 2 3137#define regHUBPREQ3_UCLK_PSTATE_FORCE 0x08fc 3138#define regHUBPREQ3_UCLK_PSTATE_FORCE_BASE_IDX 2 3139#define regHUBPREQ3_HUBPREQ_STATUS_REG0 0x08fd 3140#define regHUBPREQ3_HUBPREQ_STATUS_REG0_BASE_IDX 2 3141#define regHUBPREQ3_HUBPREQ_STATUS_REG1 0x08fe 3142#define regHUBPREQ3_HUBPREQ_STATUS_REG1_BASE_IDX 2 3143#define regHUBPREQ3_HUBPREQ_STATUS_REG2 0x08ff 3144#define regHUBPREQ3_HUBPREQ_STATUS_REG2_BASE_IDX 2 3145 3146 3147// addressBlock: dcn_dc_dcbubp3_dispdec_hubpret_dispdec 3148// base address: 0xa50 3149#define regHUBPRET3_HUBPRET_CONTROL 0x0900 3150#define regHUBPRET3_HUBPRET_CONTROL_BASE_IDX 2 3151#define regHUBPRET3_HUBPRET_MEM_PWR_CTRL 0x0901 3152#define regHUBPRET3_HUBPRET_MEM_PWR_CTRL_BASE_IDX 2 3153#define regHUBPRET3_HUBPRET_MEM_PWR_STATUS 0x0902 3154#define regHUBPRET3_HUBPRET_MEM_PWR_STATUS_BASE_IDX 2 3155#define regHUBPRET3_HUBPRET_READ_LINE_CTRL0 0x0903 3156#define regHUBPRET3_HUBPRET_READ_LINE_CTRL0_BASE_IDX 2 3157#define regHUBPRET3_HUBPRET_READ_LINE_CTRL1 0x0904 3158#define regHUBPRET3_HUBPRET_READ_LINE_CTRL1_BASE_IDX 2 3159#define regHUBPRET3_HUBPRET_READ_LINE0 0x0905 3160#define regHUBPRET3_HUBPRET_READ_LINE0_BASE_IDX 2 3161#define regHUBPRET3_HUBPRET_READ_LINE1 0x0906 3162#define regHUBPRET3_HUBPRET_READ_LINE1_BASE_IDX 2 3163#define regHUBPRET3_HUBPRET_INTERRUPT 0x0907 3164#define regHUBPRET3_HUBPRET_INTERRUPT_BASE_IDX 2 3165#define regHUBPRET3_HUBPRET_READ_LINE_VALUE 0x0908 3166#define regHUBPRET3_HUBPRET_READ_LINE_VALUE_BASE_IDX 2 3167#define regHUBPRET3_HUBPRET_READ_LINE_STATUS 0x0909 3168#define regHUBPRET3_HUBPRET_READ_LINE_STATUS_BASE_IDX 2 3169 3170 3171// addressBlock: dcn_dc_dcbubp3_dispdec_cursor0_dispdec 3172// base address: 0xa50 3173#define regCURSOR0_3_CURSOR_CONTROL 0x090c 3174#define regCURSOR0_3_CURSOR_CONTROL_BASE_IDX 2 3175#define regCURSOR0_3_CURSOR_SURFACE_ADDRESS 0x090d 3176#define regCURSOR0_3_CURSOR_SURFACE_ADDRESS_BASE_IDX 2 3177#define regCURSOR0_3_CURSOR_SURFACE_ADDRESS_HIGH 0x090e 3178#define regCURSOR0_3_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX 2 3179#define regCURSOR0_3_CURSOR_SIZE 0x090f 3180#define regCURSOR0_3_CURSOR_SIZE_BASE_IDX 2 3181#define regCURSOR0_3_CURSOR_POSITION 0x0910 3182#define regCURSOR0_3_CURSOR_POSITION_BASE_IDX 2 3183#define regCURSOR0_3_CURSOR_HOT_SPOT 0x0911 3184#define regCURSOR0_3_CURSOR_HOT_SPOT_BASE_IDX 2 3185#define regCURSOR0_3_CURSOR_STEREO_CONTROL 0x0912 3186#define regCURSOR0_3_CURSOR_STEREO_CONTROL_BASE_IDX 2 3187#define regCURSOR0_3_CURSOR_DST_OFFSET 0x0913 3188#define regCURSOR0_3_CURSOR_DST_OFFSET_BASE_IDX 2 3189#define regCURSOR0_3_CURSOR_MEM_PWR_CTRL 0x0914 3190#define regCURSOR0_3_CURSOR_MEM_PWR_CTRL_BASE_IDX 2 3191#define regCURSOR0_3_CURSOR_MEM_PWR_STATUS 0x0915 3192#define regCURSOR0_3_CURSOR_MEM_PWR_STATUS_BASE_IDX 2 3193#define regCURSOR0_3_DMDATA_ADDRESS_HIGH 0x0916 3194#define regCURSOR0_3_DMDATA_ADDRESS_HIGH_BASE_IDX 2 3195#define regCURSOR0_3_DMDATA_ADDRESS_LOW 0x0917 3196#define regCURSOR0_3_DMDATA_ADDRESS_LOW_BASE_IDX 2 3197#define regCURSOR0_3_DMDATA_CNTL 0x0918 3198#define regCURSOR0_3_DMDATA_CNTL_BASE_IDX 2 3199#define regCURSOR0_3_DMDATA_QOS_CNTL 0x0919 3200#define regCURSOR0_3_DMDATA_QOS_CNTL_BASE_IDX 2 3201#define regCURSOR0_3_DMDATA_STATUS 0x091a 3202#define regCURSOR0_3_DMDATA_STATUS_BASE_IDX 2 3203#define regCURSOR0_3_DMDATA_SW_CNTL 0x091b 3204#define regCURSOR0_3_DMDATA_SW_CNTL_BASE_IDX 2 3205#define regCURSOR0_3_DMDATA_SW_DATA 0x091c 3206#define regCURSOR0_3_DMDATA_SW_DATA_BASE_IDX 2 3207 3208 3209// addressBlock: dcn_dc_dpp0_dispdec_cnvc_cfg_dispdec 3210// base address: 0x0 3211#define regCNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT 0x0ccf 3212#define regCNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX 2 3213#define regCNVC_CFG0_FORMAT_CONTROL 0x0cd0 3214#define regCNVC_CFG0_FORMAT_CONTROL_BASE_IDX 2 3215#define regCNVC_CFG0_FCNV_FP_BIAS_R 0x0cd1 3216#define regCNVC_CFG0_FCNV_FP_BIAS_R_BASE_IDX 2 3217#define regCNVC_CFG0_FCNV_FP_BIAS_G 0x0cd2 3218#define regCNVC_CFG0_FCNV_FP_BIAS_G_BASE_IDX 2 3219#define regCNVC_CFG0_FCNV_FP_BIAS_B 0x0cd3 3220#define regCNVC_CFG0_FCNV_FP_BIAS_B_BASE_IDX 2 3221#define regCNVC_CFG0_FCNV_FP_SCALE_R 0x0cd4 3222#define regCNVC_CFG0_FCNV_FP_SCALE_R_BASE_IDX 2 3223#define regCNVC_CFG0_FCNV_FP_SCALE_G 0x0cd5 3224#define regCNVC_CFG0_FCNV_FP_SCALE_G_BASE_IDX 2 3225#define regCNVC_CFG0_FCNV_FP_SCALE_B 0x0cd6 3226#define regCNVC_CFG0_FCNV_FP_SCALE_B_BASE_IDX 2 3227#define regCNVC_CFG0_COLOR_KEYER_CONTROL 0x0cd7 3228#define regCNVC_CFG0_COLOR_KEYER_CONTROL_BASE_IDX 2 3229#define regCNVC_CFG0_COLOR_KEYER_ALPHA 0x0cd8 3230#define regCNVC_CFG0_COLOR_KEYER_ALPHA_BASE_IDX 2 3231#define regCNVC_CFG0_COLOR_KEYER_RED 0x0cd9 3232#define regCNVC_CFG0_COLOR_KEYER_RED_BASE_IDX 2 3233#define regCNVC_CFG0_COLOR_KEYER_GREEN 0x0cda 3234#define regCNVC_CFG0_COLOR_KEYER_GREEN_BASE_IDX 2 3235#define regCNVC_CFG0_COLOR_KEYER_BLUE 0x0cdb 3236#define regCNVC_CFG0_COLOR_KEYER_BLUE_BASE_IDX 2 3237#define regCNVC_CFG0_ALPHA_2BIT_LUT 0x0cdd 3238#define regCNVC_CFG0_ALPHA_2BIT_LUT_BASE_IDX 2 3239#define regCNVC_CFG0_PRE_DEALPHA 0x0cde 3240#define regCNVC_CFG0_PRE_DEALPHA_BASE_IDX 2 3241#define regCNVC_CFG0_PRE_CSC_MODE 0x0cdf 3242#define regCNVC_CFG0_PRE_CSC_MODE_BASE_IDX 2 3243#define regCNVC_CFG0_PRE_CSC_C11_C12 0x0ce0 3244#define regCNVC_CFG0_PRE_CSC_C11_C12_BASE_IDX 2 3245#define regCNVC_CFG0_PRE_CSC_C13_C14 0x0ce1 3246#define regCNVC_CFG0_PRE_CSC_C13_C14_BASE_IDX 2 3247#define regCNVC_CFG0_PRE_CSC_C21_C22 0x0ce2 3248#define regCNVC_CFG0_PRE_CSC_C21_C22_BASE_IDX 2 3249#define regCNVC_CFG0_PRE_CSC_C23_C24 0x0ce3 3250#define regCNVC_CFG0_PRE_CSC_C23_C24_BASE_IDX 2 3251#define regCNVC_CFG0_PRE_CSC_C31_C32 0x0ce4 3252#define regCNVC_CFG0_PRE_CSC_C31_C32_BASE_IDX 2 3253#define regCNVC_CFG0_PRE_CSC_C33_C34 0x0ce5 3254#define regCNVC_CFG0_PRE_CSC_C33_C34_BASE_IDX 2 3255#define regCNVC_CFG0_PRE_CSC_B_C11_C12 0x0ce6 3256#define regCNVC_CFG0_PRE_CSC_B_C11_C12_BASE_IDX 2 3257#define regCNVC_CFG0_PRE_CSC_B_C13_C14 0x0ce7 3258#define regCNVC_CFG0_PRE_CSC_B_C13_C14_BASE_IDX 2 3259#define regCNVC_CFG0_PRE_CSC_B_C21_C22 0x0ce8 3260#define regCNVC_CFG0_PRE_CSC_B_C21_C22_BASE_IDX 2 3261#define regCNVC_CFG0_PRE_CSC_B_C23_C24 0x0ce9 3262#define regCNVC_CFG0_PRE_CSC_B_C23_C24_BASE_IDX 2 3263#define regCNVC_CFG0_PRE_CSC_B_C31_C32 0x0cea 3264#define regCNVC_CFG0_PRE_CSC_B_C31_C32_BASE_IDX 2 3265#define regCNVC_CFG0_PRE_CSC_B_C33_C34 0x0ceb 3266#define regCNVC_CFG0_PRE_CSC_B_C33_C34_BASE_IDX 2 3267#define regCNVC_CFG0_CNVC_COEF_FORMAT 0x0cec 3268#define regCNVC_CFG0_CNVC_COEF_FORMAT_BASE_IDX 2 3269#define regCNVC_CFG0_PRE_DEGAM 0x0ced 3270#define regCNVC_CFG0_PRE_DEGAM_BASE_IDX 2 3271#define regCNVC_CFG0_PRE_REALPHA 0x0cee 3272#define regCNVC_CFG0_PRE_REALPHA_BASE_IDX 2 3273 3274 3275// addressBlock: dcn_dc_dpp0_dispdec_cnvc_cur_dispdec 3276// base address: 0x0 3277#define regCNVC_CUR0_CURSOR0_CONTROL 0x0cf1 3278#define regCNVC_CUR0_CURSOR0_CONTROL_BASE_IDX 2 3279#define regCNVC_CUR0_CURSOR0_COLOR0 0x0cf2 3280#define regCNVC_CUR0_CURSOR0_COLOR0_BASE_IDX 2 3281#define regCNVC_CUR0_CURSOR0_COLOR1 0x0cf3 3282#define regCNVC_CUR0_CURSOR0_COLOR1_BASE_IDX 2 3283#define regCNVC_CUR0_CURSOR0_FP_SCALE_BIAS 0x0cf4 3284#define regCNVC_CUR0_CURSOR0_FP_SCALE_BIAS_BASE_IDX 2 3285 3286 3287// addressBlock: dcn_dc_dpp0_dispdec_dscl_dispdec 3288// base address: 0x0 3289#define regDSCL0_SCL_COEF_RAM_TAP_SELECT 0x0cf9 3290#define regDSCL0_SCL_COEF_RAM_TAP_SELECT_BASE_IDX 2 3291#define regDSCL0_SCL_COEF_RAM_TAP_DATA 0x0cfa 3292#define regDSCL0_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2 3293#define regDSCL0_SCL_MODE 0x0cfb 3294#define regDSCL0_SCL_MODE_BASE_IDX 2 3295#define regDSCL0_SCL_TAP_CONTROL 0x0cfc 3296#define regDSCL0_SCL_TAP_CONTROL_BASE_IDX 2 3297#define regDSCL0_DSCL_CONTROL 0x0cfd 3298#define regDSCL0_DSCL_CONTROL_BASE_IDX 2 3299#define regDSCL0_DSCL_2TAP_CONTROL 0x0cfe 3300#define regDSCL0_DSCL_2TAP_CONTROL_BASE_IDX 2 3301#define regDSCL0_SCL_MANUAL_REPLICATE_CONTROL 0x0cff 3302#define regDSCL0_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2 3303#define regDSCL0_SCL_HORZ_FILTER_SCALE_RATIO 0x0d00 3304#define regDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2 3305#define regDSCL0_SCL_HORZ_FILTER_INIT 0x0d01 3306#define regDSCL0_SCL_HORZ_FILTER_INIT_BASE_IDX 2 3307#define regDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C 0x0d02 3308#define regDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX 2 3309#define regDSCL0_SCL_HORZ_FILTER_INIT_C 0x0d03 3310#define regDSCL0_SCL_HORZ_FILTER_INIT_C_BASE_IDX 2 3311#define regDSCL0_SCL_VERT_FILTER_SCALE_RATIO 0x0d04 3312#define regDSCL0_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2 3313#define regDSCL0_SCL_VERT_FILTER_INIT 0x0d05 3314#define regDSCL0_SCL_VERT_FILTER_INIT_BASE_IDX 2 3315#define regDSCL0_SCL_VERT_FILTER_INIT_BOT 0x0d06 3316#define regDSCL0_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2 3317#define regDSCL0_SCL_VERT_FILTER_SCALE_RATIO_C 0x0d07 3318#define regDSCL0_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX 2 3319#define regDSCL0_SCL_VERT_FILTER_INIT_C 0x0d08 3320#define regDSCL0_SCL_VERT_FILTER_INIT_C_BASE_IDX 2 3321#define regDSCL0_SCL_VERT_FILTER_INIT_BOT_C 0x0d09 3322#define regDSCL0_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX 2 3323#define regDSCL0_SCL_BLACK_COLOR 0x0d0a 3324#define regDSCL0_SCL_BLACK_COLOR_BASE_IDX 2 3325#define regDSCL0_DSCL_UPDATE 0x0d0b 3326#define regDSCL0_DSCL_UPDATE_BASE_IDX 2 3327#define regDSCL0_DSCL_AUTOCAL 0x0d0c 3328#define regDSCL0_DSCL_AUTOCAL_BASE_IDX 2 3329#define regDSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT 0x0d0d 3330#define regDSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2 3331#define regDSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM 0x0d0e 3332#define regDSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2 3333#define regDSCL0_OTG_H_BLANK 0x0d0f 3334#define regDSCL0_OTG_H_BLANK_BASE_IDX 2 3335#define regDSCL0_OTG_V_BLANK 0x0d10 3336#define regDSCL0_OTG_V_BLANK_BASE_IDX 2 3337#define regDSCL0_RECOUT_START 0x0d11 3338#define regDSCL0_RECOUT_START_BASE_IDX 2 3339#define regDSCL0_RECOUT_SIZE 0x0d12 3340#define regDSCL0_RECOUT_SIZE_BASE_IDX 2 3341#define regDSCL0_MPC_SIZE 0x0d13 3342#define regDSCL0_MPC_SIZE_BASE_IDX 2 3343#define regDSCL0_LB_DATA_FORMAT 0x0d14 3344#define regDSCL0_LB_DATA_FORMAT_BASE_IDX 2 3345#define regDSCL0_LB_MEMORY_CTRL 0x0d15 3346#define regDSCL0_LB_MEMORY_CTRL_BASE_IDX 2 3347#define regDSCL0_LB_V_COUNTER 0x0d16 3348#define regDSCL0_LB_V_COUNTER_BASE_IDX 2 3349#define regDSCL0_DSCL_MEM_PWR_CTRL 0x0d17 3350#define regDSCL0_DSCL_MEM_PWR_CTRL_BASE_IDX 2 3351#define regDSCL0_DSCL_MEM_PWR_STATUS 0x0d18 3352#define regDSCL0_DSCL_MEM_PWR_STATUS_BASE_IDX 2 3353#define regDSCL0_OBUF_CONTROL 0x0d19 3354#define regDSCL0_OBUF_CONTROL_BASE_IDX 2 3355#define regDSCL0_OBUF_MEM_PWR_CTRL 0x0d1a 3356#define regDSCL0_OBUF_MEM_PWR_CTRL_BASE_IDX 2 3357 3358 3359// addressBlock: dcn_dc_dpp0_dispdec_cm_dispdec 3360// base address: 0x0 3361#define regCM0_CM_CONTROL 0x0d20 3362#define regCM0_CM_CONTROL_BASE_IDX 2 3363#define regCM0_CM_POST_CSC_CONTROL 0x0d21 3364#define regCM0_CM_POST_CSC_CONTROL_BASE_IDX 2 3365#define regCM0_CM_POST_CSC_C11_C12 0x0d22 3366#define regCM0_CM_POST_CSC_C11_C12_BASE_IDX 2 3367#define regCM0_CM_POST_CSC_C13_C14 0x0d23 3368#define regCM0_CM_POST_CSC_C13_C14_BASE_IDX 2 3369#define regCM0_CM_POST_CSC_C21_C22 0x0d24 3370#define regCM0_CM_POST_CSC_C21_C22_BASE_IDX 2 3371#define regCM0_CM_POST_CSC_C23_C24 0x0d25 3372#define regCM0_CM_POST_CSC_C23_C24_BASE_IDX 2 3373#define regCM0_CM_POST_CSC_C31_C32 0x0d26 3374#define regCM0_CM_POST_CSC_C31_C32_BASE_IDX 2 3375#define regCM0_CM_POST_CSC_C33_C34 0x0d27 3376#define regCM0_CM_POST_CSC_C33_C34_BASE_IDX 2 3377#define regCM0_CM_POST_CSC_B_C11_C12 0x0d28 3378#define regCM0_CM_POST_CSC_B_C11_C12_BASE_IDX 2 3379#define regCM0_CM_POST_CSC_B_C13_C14 0x0d29 3380#define regCM0_CM_POST_CSC_B_C13_C14_BASE_IDX 2 3381#define regCM0_CM_POST_CSC_B_C21_C22 0x0d2a 3382#define regCM0_CM_POST_CSC_B_C21_C22_BASE_IDX 2 3383#define regCM0_CM_POST_CSC_B_C23_C24 0x0d2b 3384#define regCM0_CM_POST_CSC_B_C23_C24_BASE_IDX 2 3385#define regCM0_CM_POST_CSC_B_C31_C32 0x0d2c 3386#define regCM0_CM_POST_CSC_B_C31_C32_BASE_IDX 2 3387#define regCM0_CM_POST_CSC_B_C33_C34 0x0d2d 3388#define regCM0_CM_POST_CSC_B_C33_C34_BASE_IDX 2 3389#define regCM0_CM_GAMUT_REMAP_CONTROL 0x0d2e 3390#define regCM0_CM_GAMUT_REMAP_CONTROL_BASE_IDX 2 3391#define regCM0_CM_GAMUT_REMAP_C11_C12 0x0d2f 3392#define regCM0_CM_GAMUT_REMAP_C11_C12_BASE_IDX 2 3393#define regCM0_CM_GAMUT_REMAP_C13_C14 0x0d30 3394#define regCM0_CM_GAMUT_REMAP_C13_C14_BASE_IDX 2 3395#define regCM0_CM_GAMUT_REMAP_C21_C22 0x0d31 3396#define regCM0_CM_GAMUT_REMAP_C21_C22_BASE_IDX 2 3397#define regCM0_CM_GAMUT_REMAP_C23_C24 0x0d32 3398#define regCM0_CM_GAMUT_REMAP_C23_C24_BASE_IDX 2 3399#define regCM0_CM_GAMUT_REMAP_C31_C32 0x0d33 3400#define regCM0_CM_GAMUT_REMAP_C31_C32_BASE_IDX 2 3401#define regCM0_CM_GAMUT_REMAP_C33_C34 0x0d34 3402#define regCM0_CM_GAMUT_REMAP_C33_C34_BASE_IDX 2 3403#define regCM0_CM_GAMUT_REMAP_B_C11_C12 0x0d35 3404#define regCM0_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX 2 3405#define regCM0_CM_GAMUT_REMAP_B_C13_C14 0x0d36 3406#define regCM0_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX 2 3407#define regCM0_CM_GAMUT_REMAP_B_C21_C22 0x0d37 3408#define regCM0_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX 2 3409#define regCM0_CM_GAMUT_REMAP_B_C23_C24 0x0d38 3410#define regCM0_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX 2 3411#define regCM0_CM_GAMUT_REMAP_B_C31_C32 0x0d39 3412#define regCM0_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX 2 3413#define regCM0_CM_GAMUT_REMAP_B_C33_C34 0x0d3a 3414#define regCM0_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX 2 3415#define regCM0_CM_BIAS_CR_R 0x0d3b 3416#define regCM0_CM_BIAS_CR_R_BASE_IDX 2 3417#define regCM0_CM_BIAS_Y_G_CB_B 0x0d3c 3418#define regCM0_CM_BIAS_Y_G_CB_B_BASE_IDX 2 3419#define regCM0_CM_GAMCOR_CONTROL 0x0d3d 3420#define regCM0_CM_GAMCOR_CONTROL_BASE_IDX 2 3421#define regCM0_CM_GAMCOR_LUT_INDEX 0x0d3e 3422#define regCM0_CM_GAMCOR_LUT_INDEX_BASE_IDX 2 3423#define regCM0_CM_GAMCOR_LUT_DATA 0x0d3f 3424#define regCM0_CM_GAMCOR_LUT_DATA_BASE_IDX 2 3425#define regCM0_CM_GAMCOR_LUT_CONTROL 0x0d40 3426#define regCM0_CM_GAMCOR_LUT_CONTROL_BASE_IDX 2 3427#define regCM0_CM_GAMCOR_RAMA_START_CNTL_B 0x0d41 3428#define regCM0_CM_GAMCOR_RAMA_START_CNTL_B_BASE_IDX 2 3429#define regCM0_CM_GAMCOR_RAMA_START_CNTL_G 0x0d42 3430#define regCM0_CM_GAMCOR_RAMA_START_CNTL_G_BASE_IDX 2 3431#define regCM0_CM_GAMCOR_RAMA_START_CNTL_R 0x0d43 3432#define regCM0_CM_GAMCOR_RAMA_START_CNTL_R_BASE_IDX 2 3433#define regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B 0x0d44 3434#define regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B_BASE_IDX 2 3435#define regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G 0x0d45 3436#define regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2 3437#define regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R 0x0d46 3438#define regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R_BASE_IDX 2 3439#define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_B 0x0d47 3440#define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_B_BASE_IDX 2 3441#define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_G 0x0d48 3442#define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_G_BASE_IDX 2 3443#define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_R 0x0d49 3444#define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_R_BASE_IDX 2 3445#define regCM0_CM_GAMCOR_RAMA_END_CNTL1_B 0x0d4a 3446#define regCM0_CM_GAMCOR_RAMA_END_CNTL1_B_BASE_IDX 2 3447#define regCM0_CM_GAMCOR_RAMA_END_CNTL2_B 0x0d4b 3448#define regCM0_CM_GAMCOR_RAMA_END_CNTL2_B_BASE_IDX 2 3449#define regCM0_CM_GAMCOR_RAMA_END_CNTL1_G 0x0d4c 3450#define regCM0_CM_GAMCOR_RAMA_END_CNTL1_G_BASE_IDX 2 3451#define regCM0_CM_GAMCOR_RAMA_END_CNTL2_G 0x0d4d 3452#define regCM0_CM_GAMCOR_RAMA_END_CNTL2_G_BASE_IDX 2 3453#define regCM0_CM_GAMCOR_RAMA_END_CNTL1_R 0x0d4e 3454#define regCM0_CM_GAMCOR_RAMA_END_CNTL1_R_BASE_IDX 2 3455#define regCM0_CM_GAMCOR_RAMA_END_CNTL2_R 0x0d4f 3456#define regCM0_CM_GAMCOR_RAMA_END_CNTL2_R_BASE_IDX 2 3457#define regCM0_CM_GAMCOR_RAMA_OFFSET_B 0x0d50 3458#define regCM0_CM_GAMCOR_RAMA_OFFSET_B_BASE_IDX 2 3459#define regCM0_CM_GAMCOR_RAMA_OFFSET_G 0x0d51 3460#define regCM0_CM_GAMCOR_RAMA_OFFSET_G_BASE_IDX 2 3461#define regCM0_CM_GAMCOR_RAMA_OFFSET_R 0x0d52 3462#define regCM0_CM_GAMCOR_RAMA_OFFSET_R_BASE_IDX 2 3463#define regCM0_CM_GAMCOR_RAMA_REGION_0_1 0x0d53 3464#define regCM0_CM_GAMCOR_RAMA_REGION_0_1_BASE_IDX 2 3465#define regCM0_CM_GAMCOR_RAMA_REGION_2_3 0x0d54 3466#define regCM0_CM_GAMCOR_RAMA_REGION_2_3_BASE_IDX 2 3467#define regCM0_CM_GAMCOR_RAMA_REGION_4_5 0x0d55 3468#define regCM0_CM_GAMCOR_RAMA_REGION_4_5_BASE_IDX 2 3469#define regCM0_CM_GAMCOR_RAMA_REGION_6_7 0x0d56 3470#define regCM0_CM_GAMCOR_RAMA_REGION_6_7_BASE_IDX 2 3471#define regCM0_CM_GAMCOR_RAMA_REGION_8_9 0x0d57 3472#define regCM0_CM_GAMCOR_RAMA_REGION_8_9_BASE_IDX 2 3473#define regCM0_CM_GAMCOR_RAMA_REGION_10_11 0x0d58 3474#define regCM0_CM_GAMCOR_RAMA_REGION_10_11_BASE_IDX 2 3475#define regCM0_CM_GAMCOR_RAMA_REGION_12_13 0x0d59 3476#define regCM0_CM_GAMCOR_RAMA_REGION_12_13_BASE_IDX 2 3477#define regCM0_CM_GAMCOR_RAMA_REGION_14_15 0x0d5a 3478#define regCM0_CM_GAMCOR_RAMA_REGION_14_15_BASE_IDX 2 3479#define regCM0_CM_GAMCOR_RAMA_REGION_16_17 0x0d5b 3480#define regCM0_CM_GAMCOR_RAMA_REGION_16_17_BASE_IDX 2 3481#define regCM0_CM_GAMCOR_RAMA_REGION_18_19 0x0d5c 3482#define regCM0_CM_GAMCOR_RAMA_REGION_18_19_BASE_IDX 2 3483#define regCM0_CM_GAMCOR_RAMA_REGION_20_21 0x0d5d 3484#define regCM0_CM_GAMCOR_RAMA_REGION_20_21_BASE_IDX 2 3485#define regCM0_CM_GAMCOR_RAMA_REGION_22_23 0x0d5e 3486#define regCM0_CM_GAMCOR_RAMA_REGION_22_23_BASE_IDX 2 3487#define regCM0_CM_GAMCOR_RAMA_REGION_24_25 0x0d5f 3488#define regCM0_CM_GAMCOR_RAMA_REGION_24_25_BASE_IDX 2 3489#define regCM0_CM_GAMCOR_RAMA_REGION_26_27 0x0d60 3490#define regCM0_CM_GAMCOR_RAMA_REGION_26_27_BASE_IDX 2 3491#define regCM0_CM_GAMCOR_RAMA_REGION_28_29 0x0d61 3492#define regCM0_CM_GAMCOR_RAMA_REGION_28_29_BASE_IDX 2 3493#define regCM0_CM_GAMCOR_RAMA_REGION_30_31 0x0d62 3494#define regCM0_CM_GAMCOR_RAMA_REGION_30_31_BASE_IDX 2 3495#define regCM0_CM_GAMCOR_RAMA_REGION_32_33 0x0d63 3496#define regCM0_CM_GAMCOR_RAMA_REGION_32_33_BASE_IDX 2 3497#define regCM0_CM_GAMCOR_RAMB_START_CNTL_B 0x0d64 3498#define regCM0_CM_GAMCOR_RAMB_START_CNTL_B_BASE_IDX 2 3499#define regCM0_CM_GAMCOR_RAMB_START_CNTL_G 0x0d65 3500#define regCM0_CM_GAMCOR_RAMB_START_CNTL_G_BASE_IDX 2 3501#define regCM0_CM_GAMCOR_RAMB_START_CNTL_R 0x0d66 3502#define regCM0_CM_GAMCOR_RAMB_START_CNTL_R_BASE_IDX 2 3503#define regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B 0x0d67 3504#define regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B_BASE_IDX 2 3505#define regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G 0x0d68 3506#define regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G_BASE_IDX 2 3507#define regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R 0x0d69 3508#define regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R_BASE_IDX 2 3509#define regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_B 0x0d6a 3510#define regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_B_BASE_IDX 2 3511#define regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_G 0x0d6b 3512#define regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_G_BASE_IDX 2 3513#define regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_R 0x0d6c 3514#define regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_R_BASE_IDX 2 3515#define regCM0_CM_GAMCOR_RAMB_END_CNTL1_B 0x0d6d 3516#define regCM0_CM_GAMCOR_RAMB_END_CNTL1_B_BASE_IDX 2 3517#define regCM0_CM_GAMCOR_RAMB_END_CNTL2_B 0x0d6e 3518#define regCM0_CM_GAMCOR_RAMB_END_CNTL2_B_BASE_IDX 2 3519#define regCM0_CM_GAMCOR_RAMB_END_CNTL1_G 0x0d6f 3520#define regCM0_CM_GAMCOR_RAMB_END_CNTL1_G_BASE_IDX 2 3521#define regCM0_CM_GAMCOR_RAMB_END_CNTL2_G 0x0d70 3522#define regCM0_CM_GAMCOR_RAMB_END_CNTL2_G_BASE_IDX 2 3523#define regCM0_CM_GAMCOR_RAMB_END_CNTL1_R 0x0d71 3524#define regCM0_CM_GAMCOR_RAMB_END_CNTL1_R_BASE_IDX 2 3525#define regCM0_CM_GAMCOR_RAMB_END_CNTL2_R 0x0d72 3526#define regCM0_CM_GAMCOR_RAMB_END_CNTL2_R_BASE_IDX 2 3527#define regCM0_CM_GAMCOR_RAMB_OFFSET_B 0x0d73 3528#define regCM0_CM_GAMCOR_RAMB_OFFSET_B_BASE_IDX 2 3529#define regCM0_CM_GAMCOR_RAMB_OFFSET_G 0x0d74 3530#define regCM0_CM_GAMCOR_RAMB_OFFSET_G_BASE_IDX 2 3531#define regCM0_CM_GAMCOR_RAMB_OFFSET_R 0x0d75 3532#define regCM0_CM_GAMCOR_RAMB_OFFSET_R_BASE_IDX 2 3533#define regCM0_CM_GAMCOR_RAMB_REGION_0_1 0x0d76 3534#define regCM0_CM_GAMCOR_RAMB_REGION_0_1_BASE_IDX 2 3535#define regCM0_CM_GAMCOR_RAMB_REGION_2_3 0x0d77 3536#define regCM0_CM_GAMCOR_RAMB_REGION_2_3_BASE_IDX 2 3537#define regCM0_CM_GAMCOR_RAMB_REGION_4_5 0x0d78 3538#define regCM0_CM_GAMCOR_RAMB_REGION_4_5_BASE_IDX 2 3539#define regCM0_CM_GAMCOR_RAMB_REGION_6_7 0x0d79 3540#define regCM0_CM_GAMCOR_RAMB_REGION_6_7_BASE_IDX 2 3541#define regCM0_CM_GAMCOR_RAMB_REGION_8_9 0x0d7a 3542#define regCM0_CM_GAMCOR_RAMB_REGION_8_9_BASE_IDX 2 3543#define regCM0_CM_GAMCOR_RAMB_REGION_10_11 0x0d7b 3544#define regCM0_CM_GAMCOR_RAMB_REGION_10_11_BASE_IDX 2 3545#define regCM0_CM_GAMCOR_RAMB_REGION_12_13 0x0d7c 3546#define regCM0_CM_GAMCOR_RAMB_REGION_12_13_BASE_IDX 2 3547#define regCM0_CM_GAMCOR_RAMB_REGION_14_15 0x0d7d 3548#define regCM0_CM_GAMCOR_RAMB_REGION_14_15_BASE_IDX 2 3549#define regCM0_CM_GAMCOR_RAMB_REGION_16_17 0x0d7e 3550#define regCM0_CM_GAMCOR_RAMB_REGION_16_17_BASE_IDX 2 3551#define regCM0_CM_GAMCOR_RAMB_REGION_18_19 0x0d7f 3552#define regCM0_CM_GAMCOR_RAMB_REGION_18_19_BASE_IDX 2 3553#define regCM0_CM_GAMCOR_RAMB_REGION_20_21 0x0d80 3554#define regCM0_CM_GAMCOR_RAMB_REGION_20_21_BASE_IDX 2 3555#define regCM0_CM_GAMCOR_RAMB_REGION_22_23 0x0d81 3556#define regCM0_CM_GAMCOR_RAMB_REGION_22_23_BASE_IDX 2 3557#define regCM0_CM_GAMCOR_RAMB_REGION_24_25 0x0d82 3558#define regCM0_CM_GAMCOR_RAMB_REGION_24_25_BASE_IDX 2 3559#define regCM0_CM_GAMCOR_RAMB_REGION_26_27 0x0d83 3560#define regCM0_CM_GAMCOR_RAMB_REGION_26_27_BASE_IDX 2 3561#define regCM0_CM_GAMCOR_RAMB_REGION_28_29 0x0d84 3562#define regCM0_CM_GAMCOR_RAMB_REGION_28_29_BASE_IDX 2 3563#define regCM0_CM_GAMCOR_RAMB_REGION_30_31 0x0d85 3564#define regCM0_CM_GAMCOR_RAMB_REGION_30_31_BASE_IDX 2 3565#define regCM0_CM_GAMCOR_RAMB_REGION_32_33 0x0d86 3566#define regCM0_CM_GAMCOR_RAMB_REGION_32_33_BASE_IDX 2 3567#define regCM0_CM_HDR_MULT_COEF 0x0d87 3568#define regCM0_CM_HDR_MULT_COEF_BASE_IDX 2 3569#define regCM0_CM_MEM_PWR_CTRL 0x0d88 3570#define regCM0_CM_MEM_PWR_CTRL_BASE_IDX 2 3571#define regCM0_CM_MEM_PWR_STATUS 0x0d89 3572#define regCM0_CM_MEM_PWR_STATUS_BASE_IDX 2 3573#define regCM0_CM_DEALPHA 0x0d8b 3574#define regCM0_CM_DEALPHA_BASE_IDX 2 3575#define regCM0_CM_COEF_FORMAT 0x0d8c 3576#define regCM0_CM_COEF_FORMAT_BASE_IDX 2 3577 3578 3579// addressBlock: dcn_dc_dpp0_dispdec_dpp_top_dispdec 3580// base address: 0x0 3581#define regDPP_TOP0_DPP_CONTROL 0x0cc5 3582#define regDPP_TOP0_DPP_CONTROL_BASE_IDX 2 3583#define regDPP_TOP0_DPP_SOFT_RESET 0x0cc6 3584#define regDPP_TOP0_DPP_SOFT_RESET_BASE_IDX 2 3585#define regDPP_TOP0_DPP_CRC_VAL_R_G 0x0cc7 3586#define regDPP_TOP0_DPP_CRC_VAL_R_G_BASE_IDX 2 3587#define regDPP_TOP0_DPP_CRC_VAL_B_A 0x0cc8 3588#define regDPP_TOP0_DPP_CRC_VAL_B_A_BASE_IDX 2 3589#define regDPP_TOP0_DPP_CRC_CTRL 0x0cc9 3590#define regDPP_TOP0_DPP_CRC_CTRL_BASE_IDX 2 3591#define regDPP_TOP0_HOST_READ_CONTROL 0x0cca 3592#define regDPP_TOP0_HOST_READ_CONTROL_BASE_IDX 2 3593 3594 3595// addressBlock: dcn_dc_dpp1_dispdec_cnvc_cfg_dispdec 3596// base address: 0x5ac 3597#define regCNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT 0x0e3a 3598#define regCNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX 2 3599#define regCNVC_CFG1_FORMAT_CONTROL 0x0e3b 3600#define regCNVC_CFG1_FORMAT_CONTROL_BASE_IDX 2 3601#define regCNVC_CFG1_FCNV_FP_BIAS_R 0x0e3c 3602#define regCNVC_CFG1_FCNV_FP_BIAS_R_BASE_IDX 2 3603#define regCNVC_CFG1_FCNV_FP_BIAS_G 0x0e3d 3604#define regCNVC_CFG1_FCNV_FP_BIAS_G_BASE_IDX 2 3605#define regCNVC_CFG1_FCNV_FP_BIAS_B 0x0e3e 3606#define regCNVC_CFG1_FCNV_FP_BIAS_B_BASE_IDX 2 3607#define regCNVC_CFG1_FCNV_FP_SCALE_R 0x0e3f 3608#define regCNVC_CFG1_FCNV_FP_SCALE_R_BASE_IDX 2 3609#define regCNVC_CFG1_FCNV_FP_SCALE_G 0x0e40 3610#define regCNVC_CFG1_FCNV_FP_SCALE_G_BASE_IDX 2 3611#define regCNVC_CFG1_FCNV_FP_SCALE_B 0x0e41 3612#define regCNVC_CFG1_FCNV_FP_SCALE_B_BASE_IDX 2 3613#define regCNVC_CFG1_COLOR_KEYER_CONTROL 0x0e42 3614#define regCNVC_CFG1_COLOR_KEYER_CONTROL_BASE_IDX 2 3615#define regCNVC_CFG1_COLOR_KEYER_ALPHA 0x0e43 3616#define regCNVC_CFG1_COLOR_KEYER_ALPHA_BASE_IDX 2 3617#define regCNVC_CFG1_COLOR_KEYER_RED 0x0e44 3618#define regCNVC_CFG1_COLOR_KEYER_RED_BASE_IDX 2 3619#define regCNVC_CFG1_COLOR_KEYER_GREEN 0x0e45 3620#define regCNVC_CFG1_COLOR_KEYER_GREEN_BASE_IDX 2 3621#define regCNVC_CFG1_COLOR_KEYER_BLUE 0x0e46 3622#define regCNVC_CFG1_COLOR_KEYER_BLUE_BASE_IDX 2 3623#define regCNVC_CFG1_ALPHA_2BIT_LUT 0x0e48 3624#define regCNVC_CFG1_ALPHA_2BIT_LUT_BASE_IDX 2 3625#define regCNVC_CFG1_PRE_DEALPHA 0x0e49 3626#define regCNVC_CFG1_PRE_DEALPHA_BASE_IDX 2 3627#define regCNVC_CFG1_PRE_CSC_MODE 0x0e4a 3628#define regCNVC_CFG1_PRE_CSC_MODE_BASE_IDX 2 3629#define regCNVC_CFG1_PRE_CSC_C11_C12 0x0e4b 3630#define regCNVC_CFG1_PRE_CSC_C11_C12_BASE_IDX 2 3631#define regCNVC_CFG1_PRE_CSC_C13_C14 0x0e4c 3632#define regCNVC_CFG1_PRE_CSC_C13_C14_BASE_IDX 2 3633#define regCNVC_CFG1_PRE_CSC_C21_C22 0x0e4d 3634#define regCNVC_CFG1_PRE_CSC_C21_C22_BASE_IDX 2 3635#define regCNVC_CFG1_PRE_CSC_C23_C24 0x0e4e 3636#define regCNVC_CFG1_PRE_CSC_C23_C24_BASE_IDX 2 3637#define regCNVC_CFG1_PRE_CSC_C31_C32 0x0e4f 3638#define regCNVC_CFG1_PRE_CSC_C31_C32_BASE_IDX 2 3639#define regCNVC_CFG1_PRE_CSC_C33_C34 0x0e50 3640#define regCNVC_CFG1_PRE_CSC_C33_C34_BASE_IDX 2 3641#define regCNVC_CFG1_PRE_CSC_B_C11_C12 0x0e51 3642#define regCNVC_CFG1_PRE_CSC_B_C11_C12_BASE_IDX 2 3643#define regCNVC_CFG1_PRE_CSC_B_C13_C14 0x0e52 3644#define regCNVC_CFG1_PRE_CSC_B_C13_C14_BASE_IDX 2 3645#define regCNVC_CFG1_PRE_CSC_B_C21_C22 0x0e53 3646#define regCNVC_CFG1_PRE_CSC_B_C21_C22_BASE_IDX 2 3647#define regCNVC_CFG1_PRE_CSC_B_C23_C24 0x0e54 3648#define regCNVC_CFG1_PRE_CSC_B_C23_C24_BASE_IDX 2 3649#define regCNVC_CFG1_PRE_CSC_B_C31_C32 0x0e55 3650#define regCNVC_CFG1_PRE_CSC_B_C31_C32_BASE_IDX 2 3651#define regCNVC_CFG1_PRE_CSC_B_C33_C34 0x0e56 3652#define regCNVC_CFG1_PRE_CSC_B_C33_C34_BASE_IDX 2 3653#define regCNVC_CFG1_CNVC_COEF_FORMAT 0x0e57 3654#define regCNVC_CFG1_CNVC_COEF_FORMAT_BASE_IDX 2 3655#define regCNVC_CFG1_PRE_DEGAM 0x0e58 3656#define regCNVC_CFG1_PRE_DEGAM_BASE_IDX 2 3657#define regCNVC_CFG1_PRE_REALPHA 0x0e59 3658#define regCNVC_CFG1_PRE_REALPHA_BASE_IDX 2 3659 3660 3661// addressBlock: dcn_dc_dpp1_dispdec_cnvc_cur_dispdec 3662// base address: 0x5ac 3663#define regCNVC_CUR1_CURSOR0_CONTROL 0x0e5c 3664#define regCNVC_CUR1_CURSOR0_CONTROL_BASE_IDX 2 3665#define regCNVC_CUR1_CURSOR0_COLOR0 0x0e5d 3666#define regCNVC_CUR1_CURSOR0_COLOR0_BASE_IDX 2 3667#define regCNVC_CUR1_CURSOR0_COLOR1 0x0e5e 3668#define regCNVC_CUR1_CURSOR0_COLOR1_BASE_IDX 2 3669#define regCNVC_CUR1_CURSOR0_FP_SCALE_BIAS 0x0e5f 3670#define regCNVC_CUR1_CURSOR0_FP_SCALE_BIAS_BASE_IDX 2 3671 3672 3673// addressBlock: dcn_dc_dpp1_dispdec_dscl_dispdec 3674// base address: 0x5ac 3675#define regDSCL1_SCL_COEF_RAM_TAP_SELECT 0x0e64 3676#define regDSCL1_SCL_COEF_RAM_TAP_SELECT_BASE_IDX 2 3677#define regDSCL1_SCL_COEF_RAM_TAP_DATA 0x0e65 3678#define regDSCL1_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2 3679#define regDSCL1_SCL_MODE 0x0e66 3680#define regDSCL1_SCL_MODE_BASE_IDX 2 3681#define regDSCL1_SCL_TAP_CONTROL 0x0e67 3682#define regDSCL1_SCL_TAP_CONTROL_BASE_IDX 2 3683#define regDSCL1_DSCL_CONTROL 0x0e68 3684#define regDSCL1_DSCL_CONTROL_BASE_IDX 2 3685#define regDSCL1_DSCL_2TAP_CONTROL 0x0e69 3686#define regDSCL1_DSCL_2TAP_CONTROL_BASE_IDX 2 3687#define regDSCL1_SCL_MANUAL_REPLICATE_CONTROL 0x0e6a 3688#define regDSCL1_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2 3689#define regDSCL1_SCL_HORZ_FILTER_SCALE_RATIO 0x0e6b 3690#define regDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2 3691#define regDSCL1_SCL_HORZ_FILTER_INIT 0x0e6c 3692#define regDSCL1_SCL_HORZ_FILTER_INIT_BASE_IDX 2 3693#define regDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C 0x0e6d 3694#define regDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX 2 3695#define regDSCL1_SCL_HORZ_FILTER_INIT_C 0x0e6e 3696#define regDSCL1_SCL_HORZ_FILTER_INIT_C_BASE_IDX 2 3697#define regDSCL1_SCL_VERT_FILTER_SCALE_RATIO 0x0e6f 3698#define regDSCL1_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2 3699#define regDSCL1_SCL_VERT_FILTER_INIT 0x0e70 3700#define regDSCL1_SCL_VERT_FILTER_INIT_BASE_IDX 2 3701#define regDSCL1_SCL_VERT_FILTER_INIT_BOT 0x0e71 3702#define regDSCL1_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2 3703#define regDSCL1_SCL_VERT_FILTER_SCALE_RATIO_C 0x0e72 3704#define regDSCL1_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX 2 3705#define regDSCL1_SCL_VERT_FILTER_INIT_C 0x0e73 3706#define regDSCL1_SCL_VERT_FILTER_INIT_C_BASE_IDX 2 3707#define regDSCL1_SCL_VERT_FILTER_INIT_BOT_C 0x0e74 3708#define regDSCL1_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX 2 3709#define regDSCL1_SCL_BLACK_COLOR 0x0e75 3710#define regDSCL1_SCL_BLACK_COLOR_BASE_IDX 2 3711#define regDSCL1_DSCL_UPDATE 0x0e76 3712#define regDSCL1_DSCL_UPDATE_BASE_IDX 2 3713#define regDSCL1_DSCL_AUTOCAL 0x0e77 3714#define regDSCL1_DSCL_AUTOCAL_BASE_IDX 2 3715#define regDSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT 0x0e78 3716#define regDSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2 3717#define regDSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM 0x0e79 3718#define regDSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2 3719#define regDSCL1_OTG_H_BLANK 0x0e7a 3720#define regDSCL1_OTG_H_BLANK_BASE_IDX 2 3721#define regDSCL1_OTG_V_BLANK 0x0e7b 3722#define regDSCL1_OTG_V_BLANK_BASE_IDX 2 3723#define regDSCL1_RECOUT_START 0x0e7c 3724#define regDSCL1_RECOUT_START_BASE_IDX 2 3725#define regDSCL1_RECOUT_SIZE 0x0e7d 3726#define regDSCL1_RECOUT_SIZE_BASE_IDX 2 3727#define regDSCL1_MPC_SIZE 0x0e7e 3728#define regDSCL1_MPC_SIZE_BASE_IDX 2 3729#define regDSCL1_LB_DATA_FORMAT 0x0e7f 3730#define regDSCL1_LB_DATA_FORMAT_BASE_IDX 2 3731#define regDSCL1_LB_MEMORY_CTRL 0x0e80 3732#define regDSCL1_LB_MEMORY_CTRL_BASE_IDX 2 3733#define regDSCL1_LB_V_COUNTER 0x0e81 3734#define regDSCL1_LB_V_COUNTER_BASE_IDX 2 3735#define regDSCL1_DSCL_MEM_PWR_CTRL 0x0e82 3736#define regDSCL1_DSCL_MEM_PWR_CTRL_BASE_IDX 2 3737#define regDSCL1_DSCL_MEM_PWR_STATUS 0x0e83 3738#define regDSCL1_DSCL_MEM_PWR_STATUS_BASE_IDX 2 3739#define regDSCL1_OBUF_CONTROL 0x0e84 3740#define regDSCL1_OBUF_CONTROL_BASE_IDX 2 3741#define regDSCL1_OBUF_MEM_PWR_CTRL 0x0e85 3742#define regDSCL1_OBUF_MEM_PWR_CTRL_BASE_IDX 2 3743 3744 3745// addressBlock: dcn_dc_dpp1_dispdec_cm_dispdec 3746// base address: 0x5ac 3747#define regCM1_CM_CONTROL 0x0e8b 3748#define regCM1_CM_CONTROL_BASE_IDX 2 3749#define regCM1_CM_POST_CSC_CONTROL 0x0e8c 3750#define regCM1_CM_POST_CSC_CONTROL_BASE_IDX 2 3751#define regCM1_CM_POST_CSC_C11_C12 0x0e8d 3752#define regCM1_CM_POST_CSC_C11_C12_BASE_IDX 2 3753#define regCM1_CM_POST_CSC_C13_C14 0x0e8e 3754#define regCM1_CM_POST_CSC_C13_C14_BASE_IDX 2 3755#define regCM1_CM_POST_CSC_C21_C22 0x0e8f 3756#define regCM1_CM_POST_CSC_C21_C22_BASE_IDX 2 3757#define regCM1_CM_POST_CSC_C23_C24 0x0e90 3758#define regCM1_CM_POST_CSC_C23_C24_BASE_IDX 2 3759#define regCM1_CM_POST_CSC_C31_C32 0x0e91 3760#define regCM1_CM_POST_CSC_C31_C32_BASE_IDX 2 3761#define regCM1_CM_POST_CSC_C33_C34 0x0e92 3762#define regCM1_CM_POST_CSC_C33_C34_BASE_IDX 2 3763#define regCM1_CM_POST_CSC_B_C11_C12 0x0e93 3764#define regCM1_CM_POST_CSC_B_C11_C12_BASE_IDX 2 3765#define regCM1_CM_POST_CSC_B_C13_C14 0x0e94 3766#define regCM1_CM_POST_CSC_B_C13_C14_BASE_IDX 2 3767#define regCM1_CM_POST_CSC_B_C21_C22 0x0e95 3768#define regCM1_CM_POST_CSC_B_C21_C22_BASE_IDX 2 3769#define regCM1_CM_POST_CSC_B_C23_C24 0x0e96 3770#define regCM1_CM_POST_CSC_B_C23_C24_BASE_IDX 2 3771#define regCM1_CM_POST_CSC_B_C31_C32 0x0e97 3772#define regCM1_CM_POST_CSC_B_C31_C32_BASE_IDX 2 3773#define regCM1_CM_POST_CSC_B_C33_C34 0x0e98 3774#define regCM1_CM_POST_CSC_B_C33_C34_BASE_IDX 2 3775#define regCM1_CM_GAMUT_REMAP_CONTROL 0x0e99 3776#define regCM1_CM_GAMUT_REMAP_CONTROL_BASE_IDX 2 3777#define regCM1_CM_GAMUT_REMAP_C11_C12 0x0e9a 3778#define regCM1_CM_GAMUT_REMAP_C11_C12_BASE_IDX 2 3779#define regCM1_CM_GAMUT_REMAP_C13_C14 0x0e9b 3780#define regCM1_CM_GAMUT_REMAP_C13_C14_BASE_IDX 2 3781#define regCM1_CM_GAMUT_REMAP_C21_C22 0x0e9c 3782#define regCM1_CM_GAMUT_REMAP_C21_C22_BASE_IDX 2 3783#define regCM1_CM_GAMUT_REMAP_C23_C24 0x0e9d 3784#define regCM1_CM_GAMUT_REMAP_C23_C24_BASE_IDX 2 3785#define regCM1_CM_GAMUT_REMAP_C31_C32 0x0e9e 3786#define regCM1_CM_GAMUT_REMAP_C31_C32_BASE_IDX 2 3787#define regCM1_CM_GAMUT_REMAP_C33_C34 0x0e9f 3788#define regCM1_CM_GAMUT_REMAP_C33_C34_BASE_IDX 2 3789#define regCM1_CM_GAMUT_REMAP_B_C11_C12 0x0ea0 3790#define regCM1_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX 2 3791#define regCM1_CM_GAMUT_REMAP_B_C13_C14 0x0ea1 3792#define regCM1_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX 2 3793#define regCM1_CM_GAMUT_REMAP_B_C21_C22 0x0ea2 3794#define regCM1_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX 2 3795#define regCM1_CM_GAMUT_REMAP_B_C23_C24 0x0ea3 3796#define regCM1_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX 2 3797#define regCM1_CM_GAMUT_REMAP_B_C31_C32 0x0ea4 3798#define regCM1_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX 2 3799#define regCM1_CM_GAMUT_REMAP_B_C33_C34 0x0ea5 3800#define regCM1_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX 2 3801#define regCM1_CM_BIAS_CR_R 0x0ea6 3802#define regCM1_CM_BIAS_CR_R_BASE_IDX 2 3803#define regCM1_CM_BIAS_Y_G_CB_B 0x0ea7 3804#define regCM1_CM_BIAS_Y_G_CB_B_BASE_IDX 2 3805#define regCM1_CM_GAMCOR_CONTROL 0x0ea8 3806#define regCM1_CM_GAMCOR_CONTROL_BASE_IDX 2 3807#define regCM1_CM_GAMCOR_LUT_INDEX 0x0ea9 3808#define regCM1_CM_GAMCOR_LUT_INDEX_BASE_IDX 2 3809#define regCM1_CM_GAMCOR_LUT_DATA 0x0eaa 3810#define regCM1_CM_GAMCOR_LUT_DATA_BASE_IDX 2 3811#define regCM1_CM_GAMCOR_LUT_CONTROL 0x0eab 3812#define regCM1_CM_GAMCOR_LUT_CONTROL_BASE_IDX 2 3813#define regCM1_CM_GAMCOR_RAMA_START_CNTL_B 0x0eac 3814#define regCM1_CM_GAMCOR_RAMA_START_CNTL_B_BASE_IDX 2 3815#define regCM1_CM_GAMCOR_RAMA_START_CNTL_G 0x0ead 3816#define regCM1_CM_GAMCOR_RAMA_START_CNTL_G_BASE_IDX 2 3817#define regCM1_CM_GAMCOR_RAMA_START_CNTL_R 0x0eae 3818#define regCM1_CM_GAMCOR_RAMA_START_CNTL_R_BASE_IDX 2 3819#define regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B 0x0eaf 3820#define regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B_BASE_IDX 2 3821#define regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G 0x0eb0 3822#define regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2 3823#define regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R 0x0eb1 3824#define regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R_BASE_IDX 2 3825#define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_B 0x0eb2 3826#define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_B_BASE_IDX 2 3827#define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_G 0x0eb3 3828#define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_G_BASE_IDX 2 3829#define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_R 0x0eb4 3830#define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_R_BASE_IDX 2 3831#define regCM1_CM_GAMCOR_RAMA_END_CNTL1_B 0x0eb5 3832#define regCM1_CM_GAMCOR_RAMA_END_CNTL1_B_BASE_IDX 2 3833#define regCM1_CM_GAMCOR_RAMA_END_CNTL2_B 0x0eb6 3834#define regCM1_CM_GAMCOR_RAMA_END_CNTL2_B_BASE_IDX 2 3835#define regCM1_CM_GAMCOR_RAMA_END_CNTL1_G 0x0eb7 3836#define regCM1_CM_GAMCOR_RAMA_END_CNTL1_G_BASE_IDX 2 3837#define regCM1_CM_GAMCOR_RAMA_END_CNTL2_G 0x0eb8 3838#define regCM1_CM_GAMCOR_RAMA_END_CNTL2_G_BASE_IDX 2 3839#define regCM1_CM_GAMCOR_RAMA_END_CNTL1_R 0x0eb9 3840#define regCM1_CM_GAMCOR_RAMA_END_CNTL1_R_BASE_IDX 2 3841#define regCM1_CM_GAMCOR_RAMA_END_CNTL2_R 0x0eba 3842#define regCM1_CM_GAMCOR_RAMA_END_CNTL2_R_BASE_IDX 2 3843#define regCM1_CM_GAMCOR_RAMA_OFFSET_B 0x0ebb 3844#define regCM1_CM_GAMCOR_RAMA_OFFSET_B_BASE_IDX 2 3845#define regCM1_CM_GAMCOR_RAMA_OFFSET_G 0x0ebc 3846#define regCM1_CM_GAMCOR_RAMA_OFFSET_G_BASE_IDX 2 3847#define regCM1_CM_GAMCOR_RAMA_OFFSET_R 0x0ebd 3848#define regCM1_CM_GAMCOR_RAMA_OFFSET_R_BASE_IDX 2 3849#define regCM1_CM_GAMCOR_RAMA_REGION_0_1 0x0ebe 3850#define regCM1_CM_GAMCOR_RAMA_REGION_0_1_BASE_IDX 2 3851#define regCM1_CM_GAMCOR_RAMA_REGION_2_3 0x0ebf 3852#define regCM1_CM_GAMCOR_RAMA_REGION_2_3_BASE_IDX 2 3853#define regCM1_CM_GAMCOR_RAMA_REGION_4_5 0x0ec0 3854#define regCM1_CM_GAMCOR_RAMA_REGION_4_5_BASE_IDX 2 3855#define regCM1_CM_GAMCOR_RAMA_REGION_6_7 0x0ec1 3856#define regCM1_CM_GAMCOR_RAMA_REGION_6_7_BASE_IDX 2 3857#define regCM1_CM_GAMCOR_RAMA_REGION_8_9 0x0ec2 3858#define regCM1_CM_GAMCOR_RAMA_REGION_8_9_BASE_IDX 2 3859#define regCM1_CM_GAMCOR_RAMA_REGION_10_11 0x0ec3 3860#define regCM1_CM_GAMCOR_RAMA_REGION_10_11_BASE_IDX 2 3861#define regCM1_CM_GAMCOR_RAMA_REGION_12_13 0x0ec4 3862#define regCM1_CM_GAMCOR_RAMA_REGION_12_13_BASE_IDX 2 3863#define regCM1_CM_GAMCOR_RAMA_REGION_14_15 0x0ec5 3864#define regCM1_CM_GAMCOR_RAMA_REGION_14_15_BASE_IDX 2 3865#define regCM1_CM_GAMCOR_RAMA_REGION_16_17 0x0ec6 3866#define regCM1_CM_GAMCOR_RAMA_REGION_16_17_BASE_IDX 2 3867#define regCM1_CM_GAMCOR_RAMA_REGION_18_19 0x0ec7 3868#define regCM1_CM_GAMCOR_RAMA_REGION_18_19_BASE_IDX 2 3869#define regCM1_CM_GAMCOR_RAMA_REGION_20_21 0x0ec8 3870#define regCM1_CM_GAMCOR_RAMA_REGION_20_21_BASE_IDX 2 3871#define regCM1_CM_GAMCOR_RAMA_REGION_22_23 0x0ec9 3872#define regCM1_CM_GAMCOR_RAMA_REGION_22_23_BASE_IDX 2 3873#define regCM1_CM_GAMCOR_RAMA_REGION_24_25 0x0eca 3874#define regCM1_CM_GAMCOR_RAMA_REGION_24_25_BASE_IDX 2 3875#define regCM1_CM_GAMCOR_RAMA_REGION_26_27 0x0ecb 3876#define regCM1_CM_GAMCOR_RAMA_REGION_26_27_BASE_IDX 2 3877#define regCM1_CM_GAMCOR_RAMA_REGION_28_29 0x0ecc 3878#define regCM1_CM_GAMCOR_RAMA_REGION_28_29_BASE_IDX 2 3879#define regCM1_CM_GAMCOR_RAMA_REGION_30_31 0x0ecd 3880#define regCM1_CM_GAMCOR_RAMA_REGION_30_31_BASE_IDX 2 3881#define regCM1_CM_GAMCOR_RAMA_REGION_32_33 0x0ece 3882#define regCM1_CM_GAMCOR_RAMA_REGION_32_33_BASE_IDX 2 3883#define regCM1_CM_GAMCOR_RAMB_START_CNTL_B 0x0ecf 3884#define regCM1_CM_GAMCOR_RAMB_START_CNTL_B_BASE_IDX 2 3885#define regCM1_CM_GAMCOR_RAMB_START_CNTL_G 0x0ed0 3886#define regCM1_CM_GAMCOR_RAMB_START_CNTL_G_BASE_IDX 2 3887#define regCM1_CM_GAMCOR_RAMB_START_CNTL_R 0x0ed1 3888#define regCM1_CM_GAMCOR_RAMB_START_CNTL_R_BASE_IDX 2 3889#define regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B 0x0ed2 3890#define regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B_BASE_IDX 2 3891#define regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G 0x0ed3 3892#define regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G_BASE_IDX 2 3893#define regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R 0x0ed4 3894#define regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R_BASE_IDX 2 3895#define regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_B 0x0ed5 3896#define regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_B_BASE_IDX 2 3897#define regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_G 0x0ed6 3898#define regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_G_BASE_IDX 2 3899#define regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_R 0x0ed7 3900#define regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_R_BASE_IDX 2 3901#define regCM1_CM_GAMCOR_RAMB_END_CNTL1_B 0x0ed8 3902#define regCM1_CM_GAMCOR_RAMB_END_CNTL1_B_BASE_IDX 2 3903#define regCM1_CM_GAMCOR_RAMB_END_CNTL2_B 0x0ed9 3904#define regCM1_CM_GAMCOR_RAMB_END_CNTL2_B_BASE_IDX 2 3905#define regCM1_CM_GAMCOR_RAMB_END_CNTL1_G 0x0eda 3906#define regCM1_CM_GAMCOR_RAMB_END_CNTL1_G_BASE_IDX 2 3907#define regCM1_CM_GAMCOR_RAMB_END_CNTL2_G 0x0edb 3908#define regCM1_CM_GAMCOR_RAMB_END_CNTL2_G_BASE_IDX 2 3909#define regCM1_CM_GAMCOR_RAMB_END_CNTL1_R 0x0edc 3910#define regCM1_CM_GAMCOR_RAMB_END_CNTL1_R_BASE_IDX 2 3911#define regCM1_CM_GAMCOR_RAMB_END_CNTL2_R 0x0edd 3912#define regCM1_CM_GAMCOR_RAMB_END_CNTL2_R_BASE_IDX 2 3913#define regCM1_CM_GAMCOR_RAMB_OFFSET_B 0x0ede 3914#define regCM1_CM_GAMCOR_RAMB_OFFSET_B_BASE_IDX 2 3915#define regCM1_CM_GAMCOR_RAMB_OFFSET_G 0x0edf 3916#define regCM1_CM_GAMCOR_RAMB_OFFSET_G_BASE_IDX 2 3917#define regCM1_CM_GAMCOR_RAMB_OFFSET_R 0x0ee0 3918#define regCM1_CM_GAMCOR_RAMB_OFFSET_R_BASE_IDX 2 3919#define regCM1_CM_GAMCOR_RAMB_REGION_0_1 0x0ee1 3920#define regCM1_CM_GAMCOR_RAMB_REGION_0_1_BASE_IDX 2 3921#define regCM1_CM_GAMCOR_RAMB_REGION_2_3 0x0ee2 3922#define regCM1_CM_GAMCOR_RAMB_REGION_2_3_BASE_IDX 2 3923#define regCM1_CM_GAMCOR_RAMB_REGION_4_5 0x0ee3 3924#define regCM1_CM_GAMCOR_RAMB_REGION_4_5_BASE_IDX 2 3925#define regCM1_CM_GAMCOR_RAMB_REGION_6_7 0x0ee4 3926#define regCM1_CM_GAMCOR_RAMB_REGION_6_7_BASE_IDX 2 3927#define regCM1_CM_GAMCOR_RAMB_REGION_8_9 0x0ee5 3928#define regCM1_CM_GAMCOR_RAMB_REGION_8_9_BASE_IDX 2 3929#define regCM1_CM_GAMCOR_RAMB_REGION_10_11 0x0ee6 3930#define regCM1_CM_GAMCOR_RAMB_REGION_10_11_BASE_IDX 2 3931#define regCM1_CM_GAMCOR_RAMB_REGION_12_13 0x0ee7 3932#define regCM1_CM_GAMCOR_RAMB_REGION_12_13_BASE_IDX 2 3933#define regCM1_CM_GAMCOR_RAMB_REGION_14_15 0x0ee8 3934#define regCM1_CM_GAMCOR_RAMB_REGION_14_15_BASE_IDX 2 3935#define regCM1_CM_GAMCOR_RAMB_REGION_16_17 0x0ee9 3936#define regCM1_CM_GAMCOR_RAMB_REGION_16_17_BASE_IDX 2 3937#define regCM1_CM_GAMCOR_RAMB_REGION_18_19 0x0eea 3938#define regCM1_CM_GAMCOR_RAMB_REGION_18_19_BASE_IDX 2 3939#define regCM1_CM_GAMCOR_RAMB_REGION_20_21 0x0eeb 3940#define regCM1_CM_GAMCOR_RAMB_REGION_20_21_BASE_IDX 2 3941#define regCM1_CM_GAMCOR_RAMB_REGION_22_23 0x0eec 3942#define regCM1_CM_GAMCOR_RAMB_REGION_22_23_BASE_IDX 2 3943#define regCM1_CM_GAMCOR_RAMB_REGION_24_25 0x0eed 3944#define regCM1_CM_GAMCOR_RAMB_REGION_24_25_BASE_IDX 2 3945#define regCM1_CM_GAMCOR_RAMB_REGION_26_27 0x0eee 3946#define regCM1_CM_GAMCOR_RAMB_REGION_26_27_BASE_IDX 2 3947#define regCM1_CM_GAMCOR_RAMB_REGION_28_29 0x0eef 3948#define regCM1_CM_GAMCOR_RAMB_REGION_28_29_BASE_IDX 2 3949#define regCM1_CM_GAMCOR_RAMB_REGION_30_31 0x0ef0 3950#define regCM1_CM_GAMCOR_RAMB_REGION_30_31_BASE_IDX 2 3951#define regCM1_CM_GAMCOR_RAMB_REGION_32_33 0x0ef1 3952#define regCM1_CM_GAMCOR_RAMB_REGION_32_33_BASE_IDX 2 3953#define regCM1_CM_HDR_MULT_COEF 0x0ef2 3954#define regCM1_CM_HDR_MULT_COEF_BASE_IDX 2 3955#define regCM1_CM_MEM_PWR_CTRL 0x0ef3 3956#define regCM1_CM_MEM_PWR_CTRL_BASE_IDX 2 3957#define regCM1_CM_MEM_PWR_STATUS 0x0ef4 3958#define regCM1_CM_MEM_PWR_STATUS_BASE_IDX 2 3959#define regCM1_CM_DEALPHA 0x0ef6 3960#define regCM1_CM_DEALPHA_BASE_IDX 2 3961#define regCM1_CM_COEF_FORMAT 0x0ef7 3962#define regCM1_CM_COEF_FORMAT_BASE_IDX 2 3963 3964 3965// addressBlock: dcn_dc_dpp1_dispdec_dpp_top_dispdec 3966// base address: 0x5ac 3967#define regDPP_TOP1_DPP_CONTROL 0x0e30 3968#define regDPP_TOP1_DPP_CONTROL_BASE_IDX 2 3969#define regDPP_TOP1_DPP_SOFT_RESET 0x0e31 3970#define regDPP_TOP1_DPP_SOFT_RESET_BASE_IDX 2 3971#define regDPP_TOP1_DPP_CRC_VAL_R_G 0x0e32 3972#define regDPP_TOP1_DPP_CRC_VAL_R_G_BASE_IDX 2 3973#define regDPP_TOP1_DPP_CRC_VAL_B_A 0x0e33 3974#define regDPP_TOP1_DPP_CRC_VAL_B_A_BASE_IDX 2 3975#define regDPP_TOP1_DPP_CRC_CTRL 0x0e34 3976#define regDPP_TOP1_DPP_CRC_CTRL_BASE_IDX 2 3977#define regDPP_TOP1_HOST_READ_CONTROL 0x0e35 3978#define regDPP_TOP1_HOST_READ_CONTROL_BASE_IDX 2 3979 3980 3981// addressBlock: dcn_dc_dpp2_dispdec_cnvc_cfg_dispdec 3982// base address: 0xb58 3983#define regCNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT 0x0fa5 3984#define regCNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX 2 3985#define regCNVC_CFG2_FORMAT_CONTROL 0x0fa6 3986#define regCNVC_CFG2_FORMAT_CONTROL_BASE_IDX 2 3987#define regCNVC_CFG2_FCNV_FP_BIAS_R 0x0fa7 3988#define regCNVC_CFG2_FCNV_FP_BIAS_R_BASE_IDX 2 3989#define regCNVC_CFG2_FCNV_FP_BIAS_G 0x0fa8 3990#define regCNVC_CFG2_FCNV_FP_BIAS_G_BASE_IDX 2 3991#define regCNVC_CFG2_FCNV_FP_BIAS_B 0x0fa9 3992#define regCNVC_CFG2_FCNV_FP_BIAS_B_BASE_IDX 2 3993#define regCNVC_CFG2_FCNV_FP_SCALE_R 0x0faa 3994#define regCNVC_CFG2_FCNV_FP_SCALE_R_BASE_IDX 2 3995#define regCNVC_CFG2_FCNV_FP_SCALE_G 0x0fab 3996#define regCNVC_CFG2_FCNV_FP_SCALE_G_BASE_IDX 2 3997#define regCNVC_CFG2_FCNV_FP_SCALE_B 0x0fac 3998#define regCNVC_CFG2_FCNV_FP_SCALE_B_BASE_IDX 2 3999#define regCNVC_CFG2_COLOR_KEYER_CONTROL 0x0fad 4000#define regCNVC_CFG2_COLOR_KEYER_CONTROL_BASE_IDX 2 4001#define regCNVC_CFG2_COLOR_KEYER_ALPHA 0x0fae 4002#define regCNVC_CFG2_COLOR_KEYER_ALPHA_BASE_IDX 2 4003#define regCNVC_CFG2_COLOR_KEYER_RED 0x0faf 4004#define regCNVC_CFG2_COLOR_KEYER_RED_BASE_IDX 2 4005#define regCNVC_CFG2_COLOR_KEYER_GREEN 0x0fb0 4006#define regCNVC_CFG2_COLOR_KEYER_GREEN_BASE_IDX 2 4007#define regCNVC_CFG2_COLOR_KEYER_BLUE 0x0fb1 4008#define regCNVC_CFG2_COLOR_KEYER_BLUE_BASE_IDX 2 4009#define regCNVC_CFG2_ALPHA_2BIT_LUT 0x0fb3 4010#define regCNVC_CFG2_ALPHA_2BIT_LUT_BASE_IDX 2 4011#define regCNVC_CFG2_PRE_DEALPHA 0x0fb4 4012#define regCNVC_CFG2_PRE_DEALPHA_BASE_IDX 2 4013#define regCNVC_CFG2_PRE_CSC_MODE 0x0fb5 4014#define regCNVC_CFG2_PRE_CSC_MODE_BASE_IDX 2 4015#define regCNVC_CFG2_PRE_CSC_C11_C12 0x0fb6 4016#define regCNVC_CFG2_PRE_CSC_C11_C12_BASE_IDX 2 4017#define regCNVC_CFG2_PRE_CSC_C13_C14 0x0fb7 4018#define regCNVC_CFG2_PRE_CSC_C13_C14_BASE_IDX 2 4019#define regCNVC_CFG2_PRE_CSC_C21_C22 0x0fb8 4020#define regCNVC_CFG2_PRE_CSC_C21_C22_BASE_IDX 2 4021#define regCNVC_CFG2_PRE_CSC_C23_C24 0x0fb9 4022#define regCNVC_CFG2_PRE_CSC_C23_C24_BASE_IDX 2 4023#define regCNVC_CFG2_PRE_CSC_C31_C32 0x0fba 4024#define regCNVC_CFG2_PRE_CSC_C31_C32_BASE_IDX 2 4025#define regCNVC_CFG2_PRE_CSC_C33_C34 0x0fbb 4026#define regCNVC_CFG2_PRE_CSC_C33_C34_BASE_IDX 2 4027#define regCNVC_CFG2_PRE_CSC_B_C11_C12 0x0fbc 4028#define regCNVC_CFG2_PRE_CSC_B_C11_C12_BASE_IDX 2 4029#define regCNVC_CFG2_PRE_CSC_B_C13_C14 0x0fbd 4030#define regCNVC_CFG2_PRE_CSC_B_C13_C14_BASE_IDX 2 4031#define regCNVC_CFG2_PRE_CSC_B_C21_C22 0x0fbe 4032#define regCNVC_CFG2_PRE_CSC_B_C21_C22_BASE_IDX 2 4033#define regCNVC_CFG2_PRE_CSC_B_C23_C24 0x0fbf 4034#define regCNVC_CFG2_PRE_CSC_B_C23_C24_BASE_IDX 2 4035#define regCNVC_CFG2_PRE_CSC_B_C31_C32 0x0fc0 4036#define regCNVC_CFG2_PRE_CSC_B_C31_C32_BASE_IDX 2 4037#define regCNVC_CFG2_PRE_CSC_B_C33_C34 0x0fc1 4038#define regCNVC_CFG2_PRE_CSC_B_C33_C34_BASE_IDX 2 4039#define regCNVC_CFG2_CNVC_COEF_FORMAT 0x0fc2 4040#define regCNVC_CFG2_CNVC_COEF_FORMAT_BASE_IDX 2 4041#define regCNVC_CFG2_PRE_DEGAM 0x0fc3 4042#define regCNVC_CFG2_PRE_DEGAM_BASE_IDX 2 4043#define regCNVC_CFG2_PRE_REALPHA 0x0fc4 4044#define regCNVC_CFG2_PRE_REALPHA_BASE_IDX 2 4045 4046 4047// addressBlock: dcn_dc_dpp2_dispdec_cnvc_cur_dispdec 4048// base address: 0xb58 4049#define regCNVC_CUR2_CURSOR0_CONTROL 0x0fc7 4050#define regCNVC_CUR2_CURSOR0_CONTROL_BASE_IDX 2 4051#define regCNVC_CUR2_CURSOR0_COLOR0 0x0fc8 4052#define regCNVC_CUR2_CURSOR0_COLOR0_BASE_IDX 2 4053#define regCNVC_CUR2_CURSOR0_COLOR1 0x0fc9 4054#define regCNVC_CUR2_CURSOR0_COLOR1_BASE_IDX 2 4055#define regCNVC_CUR2_CURSOR0_FP_SCALE_BIAS 0x0fca 4056#define regCNVC_CUR2_CURSOR0_FP_SCALE_BIAS_BASE_IDX 2 4057 4058 4059// addressBlock: dcn_dc_dpp2_dispdec_dscl_dispdec 4060// base address: 0xb58 4061#define regDSCL2_SCL_COEF_RAM_TAP_SELECT 0x0fcf 4062#define regDSCL2_SCL_COEF_RAM_TAP_SELECT_BASE_IDX 2 4063#define regDSCL2_SCL_COEF_RAM_TAP_DATA 0x0fd0 4064#define regDSCL2_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2 4065#define regDSCL2_SCL_MODE 0x0fd1 4066#define regDSCL2_SCL_MODE_BASE_IDX 2 4067#define regDSCL2_SCL_TAP_CONTROL 0x0fd2 4068#define regDSCL2_SCL_TAP_CONTROL_BASE_IDX 2 4069#define regDSCL2_DSCL_CONTROL 0x0fd3 4070#define regDSCL2_DSCL_CONTROL_BASE_IDX 2 4071#define regDSCL2_DSCL_2TAP_CONTROL 0x0fd4 4072#define regDSCL2_DSCL_2TAP_CONTROL_BASE_IDX 2 4073#define regDSCL2_SCL_MANUAL_REPLICATE_CONTROL 0x0fd5 4074#define regDSCL2_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2 4075#define regDSCL2_SCL_HORZ_FILTER_SCALE_RATIO 0x0fd6 4076#define regDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2 4077#define regDSCL2_SCL_HORZ_FILTER_INIT 0x0fd7 4078#define regDSCL2_SCL_HORZ_FILTER_INIT_BASE_IDX 2 4079#define regDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C 0x0fd8 4080#define regDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX 2 4081#define regDSCL2_SCL_HORZ_FILTER_INIT_C 0x0fd9 4082#define regDSCL2_SCL_HORZ_FILTER_INIT_C_BASE_IDX 2 4083#define regDSCL2_SCL_VERT_FILTER_SCALE_RATIO 0x0fda 4084#define regDSCL2_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2 4085#define regDSCL2_SCL_VERT_FILTER_INIT 0x0fdb 4086#define regDSCL2_SCL_VERT_FILTER_INIT_BASE_IDX 2 4087#define regDSCL2_SCL_VERT_FILTER_INIT_BOT 0x0fdc 4088#define regDSCL2_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2 4089#define regDSCL2_SCL_VERT_FILTER_SCALE_RATIO_C 0x0fdd 4090#define regDSCL2_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX 2 4091#define regDSCL2_SCL_VERT_FILTER_INIT_C 0x0fde 4092#define regDSCL2_SCL_VERT_FILTER_INIT_C_BASE_IDX 2 4093#define regDSCL2_SCL_VERT_FILTER_INIT_BOT_C 0x0fdf 4094#define regDSCL2_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX 2 4095#define regDSCL2_SCL_BLACK_COLOR 0x0fe0 4096#define regDSCL2_SCL_BLACK_COLOR_BASE_IDX 2 4097#define regDSCL2_DSCL_UPDATE 0x0fe1 4098#define regDSCL2_DSCL_UPDATE_BASE_IDX 2 4099#define regDSCL2_DSCL_AUTOCAL 0x0fe2 4100#define regDSCL2_DSCL_AUTOCAL_BASE_IDX 2 4101#define regDSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT 0x0fe3 4102#define regDSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2 4103#define regDSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM 0x0fe4 4104#define regDSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2 4105#define regDSCL2_OTG_H_BLANK 0x0fe5 4106#define regDSCL2_OTG_H_BLANK_BASE_IDX 2 4107#define regDSCL2_OTG_V_BLANK 0x0fe6 4108#define regDSCL2_OTG_V_BLANK_BASE_IDX 2 4109#define regDSCL2_RECOUT_START 0x0fe7 4110#define regDSCL2_RECOUT_START_BASE_IDX 2 4111#define regDSCL2_RECOUT_SIZE 0x0fe8 4112#define regDSCL2_RECOUT_SIZE_BASE_IDX 2 4113#define regDSCL2_MPC_SIZE 0x0fe9 4114#define regDSCL2_MPC_SIZE_BASE_IDX 2 4115#define regDSCL2_LB_DATA_FORMAT 0x0fea 4116#define regDSCL2_LB_DATA_FORMAT_BASE_IDX 2 4117#define regDSCL2_LB_MEMORY_CTRL 0x0feb 4118#define regDSCL2_LB_MEMORY_CTRL_BASE_IDX 2 4119#define regDSCL2_LB_V_COUNTER 0x0fec 4120#define regDSCL2_LB_V_COUNTER_BASE_IDX 2 4121#define regDSCL2_DSCL_MEM_PWR_CTRL 0x0fed 4122#define regDSCL2_DSCL_MEM_PWR_CTRL_BASE_IDX 2 4123#define regDSCL2_DSCL_MEM_PWR_STATUS 0x0fee 4124#define regDSCL2_DSCL_MEM_PWR_STATUS_BASE_IDX 2 4125#define regDSCL2_OBUF_CONTROL 0x0fef 4126#define regDSCL2_OBUF_CONTROL_BASE_IDX 2 4127#define regDSCL2_OBUF_MEM_PWR_CTRL 0x0ff0 4128#define regDSCL2_OBUF_MEM_PWR_CTRL_BASE_IDX 2 4129 4130 4131// addressBlock: dcn_dc_dpp2_dispdec_cm_dispdec 4132// base address: 0xb58 4133#define regCM2_CM_CONTROL 0x0ff6 4134#define regCM2_CM_CONTROL_BASE_IDX 2 4135#define regCM2_CM_POST_CSC_CONTROL 0x0ff7 4136#define regCM2_CM_POST_CSC_CONTROL_BASE_IDX 2 4137#define regCM2_CM_POST_CSC_C11_C12 0x0ff8 4138#define regCM2_CM_POST_CSC_C11_C12_BASE_IDX 2 4139#define regCM2_CM_POST_CSC_C13_C14 0x0ff9 4140#define regCM2_CM_POST_CSC_C13_C14_BASE_IDX 2 4141#define regCM2_CM_POST_CSC_C21_C22 0x0ffa 4142#define regCM2_CM_POST_CSC_C21_C22_BASE_IDX 2 4143#define regCM2_CM_POST_CSC_C23_C24 0x0ffb 4144#define regCM2_CM_POST_CSC_C23_C24_BASE_IDX 2 4145#define regCM2_CM_POST_CSC_C31_C32 0x0ffc 4146#define regCM2_CM_POST_CSC_C31_C32_BASE_IDX 2 4147#define regCM2_CM_POST_CSC_C33_C34 0x0ffd 4148#define regCM2_CM_POST_CSC_C33_C34_BASE_IDX 2 4149#define regCM2_CM_POST_CSC_B_C11_C12 0x0ffe 4150#define regCM2_CM_POST_CSC_B_C11_C12_BASE_IDX 2 4151#define regCM2_CM_POST_CSC_B_C13_C14 0x0fff 4152#define regCM2_CM_POST_CSC_B_C13_C14_BASE_IDX 2 4153#define regCM2_CM_POST_CSC_B_C21_C22 0x1000 4154#define regCM2_CM_POST_CSC_B_C21_C22_BASE_IDX 2 4155#define regCM2_CM_POST_CSC_B_C23_C24 0x1001 4156#define regCM2_CM_POST_CSC_B_C23_C24_BASE_IDX 2 4157#define regCM2_CM_POST_CSC_B_C31_C32 0x1002 4158#define regCM2_CM_POST_CSC_B_C31_C32_BASE_IDX 2 4159#define regCM2_CM_POST_CSC_B_C33_C34 0x1003 4160#define regCM2_CM_POST_CSC_B_C33_C34_BASE_IDX 2 4161#define regCM2_CM_GAMUT_REMAP_CONTROL 0x1004 4162#define regCM2_CM_GAMUT_REMAP_CONTROL_BASE_IDX 2 4163#define regCM2_CM_GAMUT_REMAP_C11_C12 0x1005 4164#define regCM2_CM_GAMUT_REMAP_C11_C12_BASE_IDX 2 4165#define regCM2_CM_GAMUT_REMAP_C13_C14 0x1006 4166#define regCM2_CM_GAMUT_REMAP_C13_C14_BASE_IDX 2 4167#define regCM2_CM_GAMUT_REMAP_C21_C22 0x1007 4168#define regCM2_CM_GAMUT_REMAP_C21_C22_BASE_IDX 2 4169#define regCM2_CM_GAMUT_REMAP_C23_C24 0x1008 4170#define regCM2_CM_GAMUT_REMAP_C23_C24_BASE_IDX 2 4171#define regCM2_CM_GAMUT_REMAP_C31_C32 0x1009 4172#define regCM2_CM_GAMUT_REMAP_C31_C32_BASE_IDX 2 4173#define regCM2_CM_GAMUT_REMAP_C33_C34 0x100a 4174#define regCM2_CM_GAMUT_REMAP_C33_C34_BASE_IDX 2 4175#define regCM2_CM_GAMUT_REMAP_B_C11_C12 0x100b 4176#define regCM2_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX 2 4177#define regCM2_CM_GAMUT_REMAP_B_C13_C14 0x100c 4178#define regCM2_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX 2 4179#define regCM2_CM_GAMUT_REMAP_B_C21_C22 0x100d 4180#define regCM2_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX 2 4181#define regCM2_CM_GAMUT_REMAP_B_C23_C24 0x100e 4182#define regCM2_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX 2 4183#define regCM2_CM_GAMUT_REMAP_B_C31_C32 0x100f 4184#define regCM2_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX 2 4185#define regCM2_CM_GAMUT_REMAP_B_C33_C34 0x1010 4186#define regCM2_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX 2 4187#define regCM2_CM_BIAS_CR_R 0x1011 4188#define regCM2_CM_BIAS_CR_R_BASE_IDX 2 4189#define regCM2_CM_BIAS_Y_G_CB_B 0x1012 4190#define regCM2_CM_BIAS_Y_G_CB_B_BASE_IDX 2 4191#define regCM2_CM_GAMCOR_CONTROL 0x1013 4192#define regCM2_CM_GAMCOR_CONTROL_BASE_IDX 2 4193#define regCM2_CM_GAMCOR_LUT_INDEX 0x1014 4194#define regCM2_CM_GAMCOR_LUT_INDEX_BASE_IDX 2 4195#define regCM2_CM_GAMCOR_LUT_DATA 0x1015 4196#define regCM2_CM_GAMCOR_LUT_DATA_BASE_IDX 2 4197#define regCM2_CM_GAMCOR_LUT_CONTROL 0x1016 4198#define regCM2_CM_GAMCOR_LUT_CONTROL_BASE_IDX 2 4199#define regCM2_CM_GAMCOR_RAMA_START_CNTL_B 0x1017 4200#define regCM2_CM_GAMCOR_RAMA_START_CNTL_B_BASE_IDX 2 4201#define regCM2_CM_GAMCOR_RAMA_START_CNTL_G 0x1018 4202#define regCM2_CM_GAMCOR_RAMA_START_CNTL_G_BASE_IDX 2 4203#define regCM2_CM_GAMCOR_RAMA_START_CNTL_R 0x1019 4204#define regCM2_CM_GAMCOR_RAMA_START_CNTL_R_BASE_IDX 2 4205#define regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B 0x101a 4206#define regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B_BASE_IDX 2 4207#define regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G 0x101b 4208#define regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2 4209#define regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R 0x101c 4210#define regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R_BASE_IDX 2 4211#define regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_B 0x101d 4212#define regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_B_BASE_IDX 2 4213#define regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_G 0x101e 4214#define regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_G_BASE_IDX 2 4215#define regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_R 0x101f 4216#define regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_R_BASE_IDX 2 4217#define regCM2_CM_GAMCOR_RAMA_END_CNTL1_B 0x1020 4218#define regCM2_CM_GAMCOR_RAMA_END_CNTL1_B_BASE_IDX 2 4219#define regCM2_CM_GAMCOR_RAMA_END_CNTL2_B 0x1021 4220#define regCM2_CM_GAMCOR_RAMA_END_CNTL2_B_BASE_IDX 2 4221#define regCM2_CM_GAMCOR_RAMA_END_CNTL1_G 0x1022 4222#define regCM2_CM_GAMCOR_RAMA_END_CNTL1_G_BASE_IDX 2 4223#define regCM2_CM_GAMCOR_RAMA_END_CNTL2_G 0x1023 4224#define regCM2_CM_GAMCOR_RAMA_END_CNTL2_G_BASE_IDX 2 4225#define regCM2_CM_GAMCOR_RAMA_END_CNTL1_R 0x1024 4226#define regCM2_CM_GAMCOR_RAMA_END_CNTL1_R_BASE_IDX 2 4227#define regCM2_CM_GAMCOR_RAMA_END_CNTL2_R 0x1025 4228#define regCM2_CM_GAMCOR_RAMA_END_CNTL2_R_BASE_IDX 2 4229#define regCM2_CM_GAMCOR_RAMA_OFFSET_B 0x1026 4230#define regCM2_CM_GAMCOR_RAMA_OFFSET_B_BASE_IDX 2 4231#define regCM2_CM_GAMCOR_RAMA_OFFSET_G 0x1027 4232#define regCM2_CM_GAMCOR_RAMA_OFFSET_G_BASE_IDX 2 4233#define regCM2_CM_GAMCOR_RAMA_OFFSET_R 0x1028 4234#define regCM2_CM_GAMCOR_RAMA_OFFSET_R_BASE_IDX 2 4235#define regCM2_CM_GAMCOR_RAMA_REGION_0_1 0x1029 4236#define regCM2_CM_GAMCOR_RAMA_REGION_0_1_BASE_IDX 2 4237#define regCM2_CM_GAMCOR_RAMA_REGION_2_3 0x102a 4238#define regCM2_CM_GAMCOR_RAMA_REGION_2_3_BASE_IDX 2 4239#define regCM2_CM_GAMCOR_RAMA_REGION_4_5 0x102b 4240#define regCM2_CM_GAMCOR_RAMA_REGION_4_5_BASE_IDX 2 4241#define regCM2_CM_GAMCOR_RAMA_REGION_6_7 0x102c 4242#define regCM2_CM_GAMCOR_RAMA_REGION_6_7_BASE_IDX 2 4243#define regCM2_CM_GAMCOR_RAMA_REGION_8_9 0x102d 4244#define regCM2_CM_GAMCOR_RAMA_REGION_8_9_BASE_IDX 2 4245#define regCM2_CM_GAMCOR_RAMA_REGION_10_11 0x102e 4246#define regCM2_CM_GAMCOR_RAMA_REGION_10_11_BASE_IDX 2 4247#define regCM2_CM_GAMCOR_RAMA_REGION_12_13 0x102f 4248#define regCM2_CM_GAMCOR_RAMA_REGION_12_13_BASE_IDX 2 4249#define regCM2_CM_GAMCOR_RAMA_REGION_14_15 0x1030 4250#define regCM2_CM_GAMCOR_RAMA_REGION_14_15_BASE_IDX 2 4251#define regCM2_CM_GAMCOR_RAMA_REGION_16_17 0x1031 4252#define regCM2_CM_GAMCOR_RAMA_REGION_16_17_BASE_IDX 2 4253#define regCM2_CM_GAMCOR_RAMA_REGION_18_19 0x1032 4254#define regCM2_CM_GAMCOR_RAMA_REGION_18_19_BASE_IDX 2 4255#define regCM2_CM_GAMCOR_RAMA_REGION_20_21 0x1033 4256#define regCM2_CM_GAMCOR_RAMA_REGION_20_21_BASE_IDX 2 4257#define regCM2_CM_GAMCOR_RAMA_REGION_22_23 0x1034 4258#define regCM2_CM_GAMCOR_RAMA_REGION_22_23_BASE_IDX 2 4259#define regCM2_CM_GAMCOR_RAMA_REGION_24_25 0x1035 4260#define regCM2_CM_GAMCOR_RAMA_REGION_24_25_BASE_IDX 2 4261#define regCM2_CM_GAMCOR_RAMA_REGION_26_27 0x1036 4262#define regCM2_CM_GAMCOR_RAMA_REGION_26_27_BASE_IDX 2 4263#define regCM2_CM_GAMCOR_RAMA_REGION_28_29 0x1037 4264#define regCM2_CM_GAMCOR_RAMA_REGION_28_29_BASE_IDX 2 4265#define regCM2_CM_GAMCOR_RAMA_REGION_30_31 0x1038 4266#define regCM2_CM_GAMCOR_RAMA_REGION_30_31_BASE_IDX 2 4267#define regCM2_CM_GAMCOR_RAMA_REGION_32_33 0x1039 4268#define regCM2_CM_GAMCOR_RAMA_REGION_32_33_BASE_IDX 2 4269#define regCM2_CM_GAMCOR_RAMB_START_CNTL_B 0x103a 4270#define regCM2_CM_GAMCOR_RAMB_START_CNTL_B_BASE_IDX 2 4271#define regCM2_CM_GAMCOR_RAMB_START_CNTL_G 0x103b 4272#define regCM2_CM_GAMCOR_RAMB_START_CNTL_G_BASE_IDX 2 4273#define regCM2_CM_GAMCOR_RAMB_START_CNTL_R 0x103c 4274#define regCM2_CM_GAMCOR_RAMB_START_CNTL_R_BASE_IDX 2 4275#define regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B 0x103d 4276#define regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B_BASE_IDX 2 4277#define regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G 0x103e 4278#define regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G_BASE_IDX 2 4279#define regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R 0x103f 4280#define regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R_BASE_IDX 2 4281#define regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_B 0x1040 4282#define regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_B_BASE_IDX 2 4283#define regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_G 0x1041 4284#define regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_G_BASE_IDX 2 4285#define regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_R 0x1042 4286#define regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_R_BASE_IDX 2 4287#define regCM2_CM_GAMCOR_RAMB_END_CNTL1_B 0x1043 4288#define regCM2_CM_GAMCOR_RAMB_END_CNTL1_B_BASE_IDX 2 4289#define regCM2_CM_GAMCOR_RAMB_END_CNTL2_B 0x1044 4290#define regCM2_CM_GAMCOR_RAMB_END_CNTL2_B_BASE_IDX 2 4291#define regCM2_CM_GAMCOR_RAMB_END_CNTL1_G 0x1045 4292#define regCM2_CM_GAMCOR_RAMB_END_CNTL1_G_BASE_IDX 2 4293#define regCM2_CM_GAMCOR_RAMB_END_CNTL2_G 0x1046 4294#define regCM2_CM_GAMCOR_RAMB_END_CNTL2_G_BASE_IDX 2 4295#define regCM2_CM_GAMCOR_RAMB_END_CNTL1_R 0x1047 4296#define regCM2_CM_GAMCOR_RAMB_END_CNTL1_R_BASE_IDX 2 4297#define regCM2_CM_GAMCOR_RAMB_END_CNTL2_R 0x1048 4298#define regCM2_CM_GAMCOR_RAMB_END_CNTL2_R_BASE_IDX 2 4299#define regCM2_CM_GAMCOR_RAMB_OFFSET_B 0x1049 4300#define regCM2_CM_GAMCOR_RAMB_OFFSET_B_BASE_IDX 2 4301#define regCM2_CM_GAMCOR_RAMB_OFFSET_G 0x104a 4302#define regCM2_CM_GAMCOR_RAMB_OFFSET_G_BASE_IDX 2 4303#define regCM2_CM_GAMCOR_RAMB_OFFSET_R 0x104b 4304#define regCM2_CM_GAMCOR_RAMB_OFFSET_R_BASE_IDX 2 4305#define regCM2_CM_GAMCOR_RAMB_REGION_0_1 0x104c 4306#define regCM2_CM_GAMCOR_RAMB_REGION_0_1_BASE_IDX 2 4307#define regCM2_CM_GAMCOR_RAMB_REGION_2_3 0x104d 4308#define regCM2_CM_GAMCOR_RAMB_REGION_2_3_BASE_IDX 2 4309#define regCM2_CM_GAMCOR_RAMB_REGION_4_5 0x104e 4310#define regCM2_CM_GAMCOR_RAMB_REGION_4_5_BASE_IDX 2 4311#define regCM2_CM_GAMCOR_RAMB_REGION_6_7 0x104f 4312#define regCM2_CM_GAMCOR_RAMB_REGION_6_7_BASE_IDX 2 4313#define regCM2_CM_GAMCOR_RAMB_REGION_8_9 0x1050 4314#define regCM2_CM_GAMCOR_RAMB_REGION_8_9_BASE_IDX 2 4315#define regCM2_CM_GAMCOR_RAMB_REGION_10_11 0x1051 4316#define regCM2_CM_GAMCOR_RAMB_REGION_10_11_BASE_IDX 2 4317#define regCM2_CM_GAMCOR_RAMB_REGION_12_13 0x1052 4318#define regCM2_CM_GAMCOR_RAMB_REGION_12_13_BASE_IDX 2 4319#define regCM2_CM_GAMCOR_RAMB_REGION_14_15 0x1053 4320#define regCM2_CM_GAMCOR_RAMB_REGION_14_15_BASE_IDX 2 4321#define regCM2_CM_GAMCOR_RAMB_REGION_16_17 0x1054 4322#define regCM2_CM_GAMCOR_RAMB_REGION_16_17_BASE_IDX 2 4323#define regCM2_CM_GAMCOR_RAMB_REGION_18_19 0x1055 4324#define regCM2_CM_GAMCOR_RAMB_REGION_18_19_BASE_IDX 2 4325#define regCM2_CM_GAMCOR_RAMB_REGION_20_21 0x1056 4326#define regCM2_CM_GAMCOR_RAMB_REGION_20_21_BASE_IDX 2 4327#define regCM2_CM_GAMCOR_RAMB_REGION_22_23 0x1057 4328#define regCM2_CM_GAMCOR_RAMB_REGION_22_23_BASE_IDX 2 4329#define regCM2_CM_GAMCOR_RAMB_REGION_24_25 0x1058 4330#define regCM2_CM_GAMCOR_RAMB_REGION_24_25_BASE_IDX 2 4331#define regCM2_CM_GAMCOR_RAMB_REGION_26_27 0x1059 4332#define regCM2_CM_GAMCOR_RAMB_REGION_26_27_BASE_IDX 2 4333#define regCM2_CM_GAMCOR_RAMB_REGION_28_29 0x105a 4334#define regCM2_CM_GAMCOR_RAMB_REGION_28_29_BASE_IDX 2 4335#define regCM2_CM_GAMCOR_RAMB_REGION_30_31 0x105b 4336#define regCM2_CM_GAMCOR_RAMB_REGION_30_31_BASE_IDX 2 4337#define regCM2_CM_GAMCOR_RAMB_REGION_32_33 0x105c 4338#define regCM2_CM_GAMCOR_RAMB_REGION_32_33_BASE_IDX 2 4339#define regCM2_CM_HDR_MULT_COEF 0x105d 4340#define regCM2_CM_HDR_MULT_COEF_BASE_IDX 2 4341#define regCM2_CM_MEM_PWR_CTRL 0x105e 4342#define regCM2_CM_MEM_PWR_CTRL_BASE_IDX 2 4343#define regCM2_CM_MEM_PWR_STATUS 0x105f 4344#define regCM2_CM_MEM_PWR_STATUS_BASE_IDX 2 4345#define regCM2_CM_DEALPHA 0x1061 4346#define regCM2_CM_DEALPHA_BASE_IDX 2 4347#define regCM2_CM_COEF_FORMAT 0x1062 4348#define regCM2_CM_COEF_FORMAT_BASE_IDX 2 4349 4350 4351// addressBlock: dcn_dc_dpp2_dispdec_dpp_top_dispdec 4352// base address: 0xb58 4353#define regDPP_TOP2_DPP_CONTROL 0x0f9b 4354#define regDPP_TOP2_DPP_CONTROL_BASE_IDX 2 4355#define regDPP_TOP2_DPP_SOFT_RESET 0x0f9c 4356#define regDPP_TOP2_DPP_SOFT_RESET_BASE_IDX 2 4357#define regDPP_TOP2_DPP_CRC_VAL_R_G 0x0f9d 4358#define regDPP_TOP2_DPP_CRC_VAL_R_G_BASE_IDX 2 4359#define regDPP_TOP2_DPP_CRC_VAL_B_A 0x0f9e 4360#define regDPP_TOP2_DPP_CRC_VAL_B_A_BASE_IDX 2 4361#define regDPP_TOP2_DPP_CRC_CTRL 0x0f9f 4362#define regDPP_TOP2_DPP_CRC_CTRL_BASE_IDX 2 4363#define regDPP_TOP2_HOST_READ_CONTROL 0x0fa0 4364#define regDPP_TOP2_HOST_READ_CONTROL_BASE_IDX 2 4365 4366 4367// addressBlock: dcn_dc_dpp3_dispdec_cnvc_cfg_dispdec 4368// base address: 0x1104 4369#define regCNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT 0x1110 4370#define regCNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX 2 4371#define regCNVC_CFG3_FORMAT_CONTROL 0x1111 4372#define regCNVC_CFG3_FORMAT_CONTROL_BASE_IDX 2 4373#define regCNVC_CFG3_FCNV_FP_BIAS_R 0x1112 4374#define regCNVC_CFG3_FCNV_FP_BIAS_R_BASE_IDX 2 4375#define regCNVC_CFG3_FCNV_FP_BIAS_G 0x1113 4376#define regCNVC_CFG3_FCNV_FP_BIAS_G_BASE_IDX 2 4377#define regCNVC_CFG3_FCNV_FP_BIAS_B 0x1114 4378#define regCNVC_CFG3_FCNV_FP_BIAS_B_BASE_IDX 2 4379#define regCNVC_CFG3_FCNV_FP_SCALE_R 0x1115 4380#define regCNVC_CFG3_FCNV_FP_SCALE_R_BASE_IDX 2 4381#define regCNVC_CFG3_FCNV_FP_SCALE_G 0x1116 4382#define regCNVC_CFG3_FCNV_FP_SCALE_G_BASE_IDX 2 4383#define regCNVC_CFG3_FCNV_FP_SCALE_B 0x1117 4384#define regCNVC_CFG3_FCNV_FP_SCALE_B_BASE_IDX 2 4385#define regCNVC_CFG3_COLOR_KEYER_CONTROL 0x1118 4386#define regCNVC_CFG3_COLOR_KEYER_CONTROL_BASE_IDX 2 4387#define regCNVC_CFG3_COLOR_KEYER_ALPHA 0x1119 4388#define regCNVC_CFG3_COLOR_KEYER_ALPHA_BASE_IDX 2 4389#define regCNVC_CFG3_COLOR_KEYER_RED 0x111a 4390#define regCNVC_CFG3_COLOR_KEYER_RED_BASE_IDX 2 4391#define regCNVC_CFG3_COLOR_KEYER_GREEN 0x111b 4392#define regCNVC_CFG3_COLOR_KEYER_GREEN_BASE_IDX 2 4393#define regCNVC_CFG3_COLOR_KEYER_BLUE 0x111c 4394#define regCNVC_CFG3_COLOR_KEYER_BLUE_BASE_IDX 2 4395#define regCNVC_CFG3_ALPHA_2BIT_LUT 0x111e 4396#define regCNVC_CFG3_ALPHA_2BIT_LUT_BASE_IDX 2 4397#define regCNVC_CFG3_PRE_DEALPHA 0x111f 4398#define regCNVC_CFG3_PRE_DEALPHA_BASE_IDX 2 4399#define regCNVC_CFG3_PRE_CSC_MODE 0x1120 4400#define regCNVC_CFG3_PRE_CSC_MODE_BASE_IDX 2 4401#define regCNVC_CFG3_PRE_CSC_C11_C12 0x1121 4402#define regCNVC_CFG3_PRE_CSC_C11_C12_BASE_IDX 2 4403#define regCNVC_CFG3_PRE_CSC_C13_C14 0x1122 4404#define regCNVC_CFG3_PRE_CSC_C13_C14_BASE_IDX 2 4405#define regCNVC_CFG3_PRE_CSC_C21_C22 0x1123 4406#define regCNVC_CFG3_PRE_CSC_C21_C22_BASE_IDX 2 4407#define regCNVC_CFG3_PRE_CSC_C23_C24 0x1124 4408#define regCNVC_CFG3_PRE_CSC_C23_C24_BASE_IDX 2 4409#define regCNVC_CFG3_PRE_CSC_C31_C32 0x1125 4410#define regCNVC_CFG3_PRE_CSC_C31_C32_BASE_IDX 2 4411#define regCNVC_CFG3_PRE_CSC_C33_C34 0x1126 4412#define regCNVC_CFG3_PRE_CSC_C33_C34_BASE_IDX 2 4413#define regCNVC_CFG3_PRE_CSC_B_C11_C12 0x1127 4414#define regCNVC_CFG3_PRE_CSC_B_C11_C12_BASE_IDX 2 4415#define regCNVC_CFG3_PRE_CSC_B_C13_C14 0x1128 4416#define regCNVC_CFG3_PRE_CSC_B_C13_C14_BASE_IDX 2 4417#define regCNVC_CFG3_PRE_CSC_B_C21_C22 0x1129 4418#define regCNVC_CFG3_PRE_CSC_B_C21_C22_BASE_IDX 2 4419#define regCNVC_CFG3_PRE_CSC_B_C23_C24 0x112a 4420#define regCNVC_CFG3_PRE_CSC_B_C23_C24_BASE_IDX 2 4421#define regCNVC_CFG3_PRE_CSC_B_C31_C32 0x112b 4422#define regCNVC_CFG3_PRE_CSC_B_C31_C32_BASE_IDX 2 4423#define regCNVC_CFG3_PRE_CSC_B_C33_C34 0x112c 4424#define regCNVC_CFG3_PRE_CSC_B_C33_C34_BASE_IDX 2 4425#define regCNVC_CFG3_CNVC_COEF_FORMAT 0x112d 4426#define regCNVC_CFG3_CNVC_COEF_FORMAT_BASE_IDX 2 4427#define regCNVC_CFG3_PRE_DEGAM 0x112e 4428#define regCNVC_CFG3_PRE_DEGAM_BASE_IDX 2 4429#define regCNVC_CFG3_PRE_REALPHA 0x112f 4430#define regCNVC_CFG3_PRE_REALPHA_BASE_IDX 2 4431 4432 4433// addressBlock: dcn_dc_dpp3_dispdec_cnvc_cur_dispdec 4434// base address: 0x1104 4435#define regCNVC_CUR3_CURSOR0_CONTROL 0x1132 4436#define regCNVC_CUR3_CURSOR0_CONTROL_BASE_IDX 2 4437#define regCNVC_CUR3_CURSOR0_COLOR0 0x1133 4438#define regCNVC_CUR3_CURSOR0_COLOR0_BASE_IDX 2 4439#define regCNVC_CUR3_CURSOR0_COLOR1 0x1134 4440#define regCNVC_CUR3_CURSOR0_COLOR1_BASE_IDX 2 4441#define regCNVC_CUR3_CURSOR0_FP_SCALE_BIAS 0x1135 4442#define regCNVC_CUR3_CURSOR0_FP_SCALE_BIAS_BASE_IDX 2 4443 4444 4445// addressBlock: dcn_dc_dpp3_dispdec_dscl_dispdec 4446// base address: 0x1104 4447#define regDSCL3_SCL_COEF_RAM_TAP_SELECT 0x113a 4448#define regDSCL3_SCL_COEF_RAM_TAP_SELECT_BASE_IDX 2 4449#define regDSCL3_SCL_COEF_RAM_TAP_DATA 0x113b 4450#define regDSCL3_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2 4451#define regDSCL3_SCL_MODE 0x113c 4452#define regDSCL3_SCL_MODE_BASE_IDX 2 4453#define regDSCL3_SCL_TAP_CONTROL 0x113d 4454#define regDSCL3_SCL_TAP_CONTROL_BASE_IDX 2 4455#define regDSCL3_DSCL_CONTROL 0x113e 4456#define regDSCL3_DSCL_CONTROL_BASE_IDX 2 4457#define regDSCL3_DSCL_2TAP_CONTROL 0x113f 4458#define regDSCL3_DSCL_2TAP_CONTROL_BASE_IDX 2 4459#define regDSCL3_SCL_MANUAL_REPLICATE_CONTROL 0x1140 4460#define regDSCL3_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2 4461#define regDSCL3_SCL_HORZ_FILTER_SCALE_RATIO 0x1141 4462#define regDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2 4463#define regDSCL3_SCL_HORZ_FILTER_INIT 0x1142 4464#define regDSCL3_SCL_HORZ_FILTER_INIT_BASE_IDX 2 4465#define regDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C 0x1143 4466#define regDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX 2 4467#define regDSCL3_SCL_HORZ_FILTER_INIT_C 0x1144 4468#define regDSCL3_SCL_HORZ_FILTER_INIT_C_BASE_IDX 2 4469#define regDSCL3_SCL_VERT_FILTER_SCALE_RATIO 0x1145 4470#define regDSCL3_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2 4471#define regDSCL3_SCL_VERT_FILTER_INIT 0x1146 4472#define regDSCL3_SCL_VERT_FILTER_INIT_BASE_IDX 2 4473#define regDSCL3_SCL_VERT_FILTER_INIT_BOT 0x1147 4474#define regDSCL3_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2 4475#define regDSCL3_SCL_VERT_FILTER_SCALE_RATIO_C 0x1148 4476#define regDSCL3_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX 2 4477#define regDSCL3_SCL_VERT_FILTER_INIT_C 0x1149 4478#define regDSCL3_SCL_VERT_FILTER_INIT_C_BASE_IDX 2 4479#define regDSCL3_SCL_VERT_FILTER_INIT_BOT_C 0x114a 4480#define regDSCL3_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX 2 4481#define regDSCL3_SCL_BLACK_COLOR 0x114b 4482#define regDSCL3_SCL_BLACK_COLOR_BASE_IDX 2 4483#define regDSCL3_DSCL_UPDATE 0x114c 4484#define regDSCL3_DSCL_UPDATE_BASE_IDX 2 4485#define regDSCL3_DSCL_AUTOCAL 0x114d 4486#define regDSCL3_DSCL_AUTOCAL_BASE_IDX 2 4487#define regDSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT 0x114e 4488#define regDSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2 4489#define regDSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM 0x114f 4490#define regDSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2 4491#define regDSCL3_OTG_H_BLANK 0x1150 4492#define regDSCL3_OTG_H_BLANK_BASE_IDX 2 4493#define regDSCL3_OTG_V_BLANK 0x1151 4494#define regDSCL3_OTG_V_BLANK_BASE_IDX 2 4495#define regDSCL3_RECOUT_START 0x1152 4496#define regDSCL3_RECOUT_START_BASE_IDX 2 4497#define regDSCL3_RECOUT_SIZE 0x1153 4498#define regDSCL3_RECOUT_SIZE_BASE_IDX 2 4499#define regDSCL3_MPC_SIZE 0x1154 4500#define regDSCL3_MPC_SIZE_BASE_IDX 2 4501#define regDSCL3_LB_DATA_FORMAT 0x1155 4502#define regDSCL3_LB_DATA_FORMAT_BASE_IDX 2 4503#define regDSCL3_LB_MEMORY_CTRL 0x1156 4504#define regDSCL3_LB_MEMORY_CTRL_BASE_IDX 2 4505#define regDSCL3_LB_V_COUNTER 0x1157 4506#define regDSCL3_LB_V_COUNTER_BASE_IDX 2 4507#define regDSCL3_DSCL_MEM_PWR_CTRL 0x1158 4508#define regDSCL3_DSCL_MEM_PWR_CTRL_BASE_IDX 2 4509#define regDSCL3_DSCL_MEM_PWR_STATUS 0x1159 4510#define regDSCL3_DSCL_MEM_PWR_STATUS_BASE_IDX 2 4511#define regDSCL3_OBUF_CONTROL 0x115a 4512#define regDSCL3_OBUF_CONTROL_BASE_IDX 2 4513#define regDSCL3_OBUF_MEM_PWR_CTRL 0x115b 4514#define regDSCL3_OBUF_MEM_PWR_CTRL_BASE_IDX 2 4515 4516 4517// addressBlock: dcn_dc_dpp3_dispdec_cm_dispdec 4518// base address: 0x1104 4519#define regCM3_CM_CONTROL 0x1161 4520#define regCM3_CM_CONTROL_BASE_IDX 2 4521#define regCM3_CM_POST_CSC_CONTROL 0x1162 4522#define regCM3_CM_POST_CSC_CONTROL_BASE_IDX 2 4523#define regCM3_CM_POST_CSC_C11_C12 0x1163 4524#define regCM3_CM_POST_CSC_C11_C12_BASE_IDX 2 4525#define regCM3_CM_POST_CSC_C13_C14 0x1164 4526#define regCM3_CM_POST_CSC_C13_C14_BASE_IDX 2 4527#define regCM3_CM_POST_CSC_C21_C22 0x1165 4528#define regCM3_CM_POST_CSC_C21_C22_BASE_IDX 2 4529#define regCM3_CM_POST_CSC_C23_C24 0x1166 4530#define regCM3_CM_POST_CSC_C23_C24_BASE_IDX 2 4531#define regCM3_CM_POST_CSC_C31_C32 0x1167 4532#define regCM3_CM_POST_CSC_C31_C32_BASE_IDX 2 4533#define regCM3_CM_POST_CSC_C33_C34 0x1168 4534#define regCM3_CM_POST_CSC_C33_C34_BASE_IDX 2 4535#define regCM3_CM_POST_CSC_B_C11_C12 0x1169 4536#define regCM3_CM_POST_CSC_B_C11_C12_BASE_IDX 2 4537#define regCM3_CM_POST_CSC_B_C13_C14 0x116a 4538#define regCM3_CM_POST_CSC_B_C13_C14_BASE_IDX 2 4539#define regCM3_CM_POST_CSC_B_C21_C22 0x116b 4540#define regCM3_CM_POST_CSC_B_C21_C22_BASE_IDX 2 4541#define regCM3_CM_POST_CSC_B_C23_C24 0x116c 4542#define regCM3_CM_POST_CSC_B_C23_C24_BASE_IDX 2 4543#define regCM3_CM_POST_CSC_B_C31_C32 0x116d 4544#define regCM3_CM_POST_CSC_B_C31_C32_BASE_IDX 2 4545#define regCM3_CM_POST_CSC_B_C33_C34 0x116e 4546#define regCM3_CM_POST_CSC_B_C33_C34_BASE_IDX 2 4547#define regCM3_CM_GAMUT_REMAP_CONTROL 0x116f 4548#define regCM3_CM_GAMUT_REMAP_CONTROL_BASE_IDX 2 4549#define regCM3_CM_GAMUT_REMAP_C11_C12 0x1170 4550#define regCM3_CM_GAMUT_REMAP_C11_C12_BASE_IDX 2 4551#define regCM3_CM_GAMUT_REMAP_C13_C14 0x1171 4552#define regCM3_CM_GAMUT_REMAP_C13_C14_BASE_IDX 2 4553#define regCM3_CM_GAMUT_REMAP_C21_C22 0x1172 4554#define regCM3_CM_GAMUT_REMAP_C21_C22_BASE_IDX 2 4555#define regCM3_CM_GAMUT_REMAP_C23_C24 0x1173 4556#define regCM3_CM_GAMUT_REMAP_C23_C24_BASE_IDX 2 4557#define regCM3_CM_GAMUT_REMAP_C31_C32 0x1174 4558#define regCM3_CM_GAMUT_REMAP_C31_C32_BASE_IDX 2 4559#define regCM3_CM_GAMUT_REMAP_C33_C34 0x1175 4560#define regCM3_CM_GAMUT_REMAP_C33_C34_BASE_IDX 2 4561#define regCM3_CM_GAMUT_REMAP_B_C11_C12 0x1176 4562#define regCM3_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX 2 4563#define regCM3_CM_GAMUT_REMAP_B_C13_C14 0x1177 4564#define regCM3_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX 2 4565#define regCM3_CM_GAMUT_REMAP_B_C21_C22 0x1178 4566#define regCM3_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX 2 4567#define regCM3_CM_GAMUT_REMAP_B_C23_C24 0x1179 4568#define regCM3_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX 2 4569#define regCM3_CM_GAMUT_REMAP_B_C31_C32 0x117a 4570#define regCM3_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX 2 4571#define regCM3_CM_GAMUT_REMAP_B_C33_C34 0x117b 4572#define regCM3_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX 2 4573#define regCM3_CM_BIAS_CR_R 0x117c 4574#define regCM3_CM_BIAS_CR_R_BASE_IDX 2 4575#define regCM3_CM_BIAS_Y_G_CB_B 0x117d 4576#define regCM3_CM_BIAS_Y_G_CB_B_BASE_IDX 2 4577#define regCM3_CM_GAMCOR_CONTROL 0x117e 4578#define regCM3_CM_GAMCOR_CONTROL_BASE_IDX 2 4579#define regCM3_CM_GAMCOR_LUT_INDEX 0x117f 4580#define regCM3_CM_GAMCOR_LUT_INDEX_BASE_IDX 2 4581#define regCM3_CM_GAMCOR_LUT_DATA 0x1180 4582#define regCM3_CM_GAMCOR_LUT_DATA_BASE_IDX 2 4583#define regCM3_CM_GAMCOR_LUT_CONTROL 0x1181 4584#define regCM3_CM_GAMCOR_LUT_CONTROL_BASE_IDX 2 4585#define regCM3_CM_GAMCOR_RAMA_START_CNTL_B 0x1182 4586#define regCM3_CM_GAMCOR_RAMA_START_CNTL_B_BASE_IDX 2 4587#define regCM3_CM_GAMCOR_RAMA_START_CNTL_G 0x1183 4588#define regCM3_CM_GAMCOR_RAMA_START_CNTL_G_BASE_IDX 2 4589#define regCM3_CM_GAMCOR_RAMA_START_CNTL_R 0x1184 4590#define regCM3_CM_GAMCOR_RAMA_START_CNTL_R_BASE_IDX 2 4591#define regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B 0x1185 4592#define regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B_BASE_IDX 2 4593#define regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G 0x1186 4594#define regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2 4595#define regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R 0x1187 4596#define regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R_BASE_IDX 2 4597#define regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_B 0x1188 4598#define regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_B_BASE_IDX 2 4599#define regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_G 0x1189 4600#define regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_G_BASE_IDX 2 4601#define regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_R 0x118a 4602#define regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_R_BASE_IDX 2 4603#define regCM3_CM_GAMCOR_RAMA_END_CNTL1_B 0x118b 4604#define regCM3_CM_GAMCOR_RAMA_END_CNTL1_B_BASE_IDX 2 4605#define regCM3_CM_GAMCOR_RAMA_END_CNTL2_B 0x118c 4606#define regCM3_CM_GAMCOR_RAMA_END_CNTL2_B_BASE_IDX 2 4607#define regCM3_CM_GAMCOR_RAMA_END_CNTL1_G 0x118d 4608#define regCM3_CM_GAMCOR_RAMA_END_CNTL1_G_BASE_IDX 2 4609#define regCM3_CM_GAMCOR_RAMA_END_CNTL2_G 0x118e 4610#define regCM3_CM_GAMCOR_RAMA_END_CNTL2_G_BASE_IDX 2 4611#define regCM3_CM_GAMCOR_RAMA_END_CNTL1_R 0x118f 4612#define regCM3_CM_GAMCOR_RAMA_END_CNTL1_R_BASE_IDX 2 4613#define regCM3_CM_GAMCOR_RAMA_END_CNTL2_R 0x1190 4614#define regCM3_CM_GAMCOR_RAMA_END_CNTL2_R_BASE_IDX 2 4615#define regCM3_CM_GAMCOR_RAMA_OFFSET_B 0x1191 4616#define regCM3_CM_GAMCOR_RAMA_OFFSET_B_BASE_IDX 2 4617#define regCM3_CM_GAMCOR_RAMA_OFFSET_G 0x1192 4618#define regCM3_CM_GAMCOR_RAMA_OFFSET_G_BASE_IDX 2 4619#define regCM3_CM_GAMCOR_RAMA_OFFSET_R 0x1193 4620#define regCM3_CM_GAMCOR_RAMA_OFFSET_R_BASE_IDX 2 4621#define regCM3_CM_GAMCOR_RAMA_REGION_0_1 0x1194 4622#define regCM3_CM_GAMCOR_RAMA_REGION_0_1_BASE_IDX 2 4623#define regCM3_CM_GAMCOR_RAMA_REGION_2_3 0x1195 4624#define regCM3_CM_GAMCOR_RAMA_REGION_2_3_BASE_IDX 2 4625#define regCM3_CM_GAMCOR_RAMA_REGION_4_5 0x1196 4626#define regCM3_CM_GAMCOR_RAMA_REGION_4_5_BASE_IDX 2 4627#define regCM3_CM_GAMCOR_RAMA_REGION_6_7 0x1197 4628#define regCM3_CM_GAMCOR_RAMA_REGION_6_7_BASE_IDX 2 4629#define regCM3_CM_GAMCOR_RAMA_REGION_8_9 0x1198 4630#define regCM3_CM_GAMCOR_RAMA_REGION_8_9_BASE_IDX 2 4631#define regCM3_CM_GAMCOR_RAMA_REGION_10_11 0x1199 4632#define regCM3_CM_GAMCOR_RAMA_REGION_10_11_BASE_IDX 2 4633#define regCM3_CM_GAMCOR_RAMA_REGION_12_13 0x119a 4634#define regCM3_CM_GAMCOR_RAMA_REGION_12_13_BASE_IDX 2 4635#define regCM3_CM_GAMCOR_RAMA_REGION_14_15 0x119b 4636#define regCM3_CM_GAMCOR_RAMA_REGION_14_15_BASE_IDX 2 4637#define regCM3_CM_GAMCOR_RAMA_REGION_16_17 0x119c 4638#define regCM3_CM_GAMCOR_RAMA_REGION_16_17_BASE_IDX 2 4639#define regCM3_CM_GAMCOR_RAMA_REGION_18_19 0x119d 4640#define regCM3_CM_GAMCOR_RAMA_REGION_18_19_BASE_IDX 2 4641#define regCM3_CM_GAMCOR_RAMA_REGION_20_21 0x119e 4642#define regCM3_CM_GAMCOR_RAMA_REGION_20_21_BASE_IDX 2 4643#define regCM3_CM_GAMCOR_RAMA_REGION_22_23 0x119f 4644#define regCM3_CM_GAMCOR_RAMA_REGION_22_23_BASE_IDX 2 4645#define regCM3_CM_GAMCOR_RAMA_REGION_24_25 0x11a0 4646#define regCM3_CM_GAMCOR_RAMA_REGION_24_25_BASE_IDX 2 4647#define regCM3_CM_GAMCOR_RAMA_REGION_26_27 0x11a1 4648#define regCM3_CM_GAMCOR_RAMA_REGION_26_27_BASE_IDX 2 4649#define regCM3_CM_GAMCOR_RAMA_REGION_28_29 0x11a2 4650#define regCM3_CM_GAMCOR_RAMA_REGION_28_29_BASE_IDX 2 4651#define regCM3_CM_GAMCOR_RAMA_REGION_30_31 0x11a3 4652#define regCM3_CM_GAMCOR_RAMA_REGION_30_31_BASE_IDX 2 4653#define regCM3_CM_GAMCOR_RAMA_REGION_32_33 0x11a4 4654#define regCM3_CM_GAMCOR_RAMA_REGION_32_33_BASE_IDX 2 4655#define regCM3_CM_GAMCOR_RAMB_START_CNTL_B 0x11a5 4656#define regCM3_CM_GAMCOR_RAMB_START_CNTL_B_BASE_IDX 2 4657#define regCM3_CM_GAMCOR_RAMB_START_CNTL_G 0x11a6 4658#define regCM3_CM_GAMCOR_RAMB_START_CNTL_G_BASE_IDX 2 4659#define regCM3_CM_GAMCOR_RAMB_START_CNTL_R 0x11a7 4660#define regCM3_CM_GAMCOR_RAMB_START_CNTL_R_BASE_IDX 2 4661#define regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B 0x11a8 4662#define regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B_BASE_IDX 2 4663#define regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G 0x11a9 4664#define regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G_BASE_IDX 2 4665#define regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R 0x11aa 4666#define regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R_BASE_IDX 2 4667#define regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_B 0x11ab 4668#define regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_B_BASE_IDX 2 4669#define regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_G 0x11ac 4670#define regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_G_BASE_IDX 2 4671#define regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_R 0x11ad 4672#define regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_R_BASE_IDX 2 4673#define regCM3_CM_GAMCOR_RAMB_END_CNTL1_B 0x11ae 4674#define regCM3_CM_GAMCOR_RAMB_END_CNTL1_B_BASE_IDX 2 4675#define regCM3_CM_GAMCOR_RAMB_END_CNTL2_B 0x11af 4676#define regCM3_CM_GAMCOR_RAMB_END_CNTL2_B_BASE_IDX 2 4677#define regCM3_CM_GAMCOR_RAMB_END_CNTL1_G 0x11b0 4678#define regCM3_CM_GAMCOR_RAMB_END_CNTL1_G_BASE_IDX 2 4679#define regCM3_CM_GAMCOR_RAMB_END_CNTL2_G 0x11b1 4680#define regCM3_CM_GAMCOR_RAMB_END_CNTL2_G_BASE_IDX 2 4681#define regCM3_CM_GAMCOR_RAMB_END_CNTL1_R 0x11b2 4682#define regCM3_CM_GAMCOR_RAMB_END_CNTL1_R_BASE_IDX 2 4683#define regCM3_CM_GAMCOR_RAMB_END_CNTL2_R 0x11b3 4684#define regCM3_CM_GAMCOR_RAMB_END_CNTL2_R_BASE_IDX 2 4685#define regCM3_CM_GAMCOR_RAMB_OFFSET_B 0x11b4 4686#define regCM3_CM_GAMCOR_RAMB_OFFSET_B_BASE_IDX 2 4687#define regCM3_CM_GAMCOR_RAMB_OFFSET_G 0x11b5 4688#define regCM3_CM_GAMCOR_RAMB_OFFSET_G_BASE_IDX 2 4689#define regCM3_CM_GAMCOR_RAMB_OFFSET_R 0x11b6 4690#define regCM3_CM_GAMCOR_RAMB_OFFSET_R_BASE_IDX 2 4691#define regCM3_CM_GAMCOR_RAMB_REGION_0_1 0x11b7 4692#define regCM3_CM_GAMCOR_RAMB_REGION_0_1_BASE_IDX 2 4693#define regCM3_CM_GAMCOR_RAMB_REGION_2_3 0x11b8 4694#define regCM3_CM_GAMCOR_RAMB_REGION_2_3_BASE_IDX 2 4695#define regCM3_CM_GAMCOR_RAMB_REGION_4_5 0x11b9 4696#define regCM3_CM_GAMCOR_RAMB_REGION_4_5_BASE_IDX 2 4697#define regCM3_CM_GAMCOR_RAMB_REGION_6_7 0x11ba 4698#define regCM3_CM_GAMCOR_RAMB_REGION_6_7_BASE_IDX 2 4699#define regCM3_CM_GAMCOR_RAMB_REGION_8_9 0x11bb 4700#define regCM3_CM_GAMCOR_RAMB_REGION_8_9_BASE_IDX 2 4701#define regCM3_CM_GAMCOR_RAMB_REGION_10_11 0x11bc 4702#define regCM3_CM_GAMCOR_RAMB_REGION_10_11_BASE_IDX 2 4703#define regCM3_CM_GAMCOR_RAMB_REGION_12_13 0x11bd 4704#define regCM3_CM_GAMCOR_RAMB_REGION_12_13_BASE_IDX 2 4705#define regCM3_CM_GAMCOR_RAMB_REGION_14_15 0x11be 4706#define regCM3_CM_GAMCOR_RAMB_REGION_14_15_BASE_IDX 2 4707#define regCM3_CM_GAMCOR_RAMB_REGION_16_17 0x11bf 4708#define regCM3_CM_GAMCOR_RAMB_REGION_16_17_BASE_IDX 2 4709#define regCM3_CM_GAMCOR_RAMB_REGION_18_19 0x11c0 4710#define regCM3_CM_GAMCOR_RAMB_REGION_18_19_BASE_IDX 2 4711#define regCM3_CM_GAMCOR_RAMB_REGION_20_21 0x11c1 4712#define regCM3_CM_GAMCOR_RAMB_REGION_20_21_BASE_IDX 2 4713#define regCM3_CM_GAMCOR_RAMB_REGION_22_23 0x11c2 4714#define regCM3_CM_GAMCOR_RAMB_REGION_22_23_BASE_IDX 2 4715#define regCM3_CM_GAMCOR_RAMB_REGION_24_25 0x11c3 4716#define regCM3_CM_GAMCOR_RAMB_REGION_24_25_BASE_IDX 2 4717#define regCM3_CM_GAMCOR_RAMB_REGION_26_27 0x11c4 4718#define regCM3_CM_GAMCOR_RAMB_REGION_26_27_BASE_IDX 2 4719#define regCM3_CM_GAMCOR_RAMB_REGION_28_29 0x11c5 4720#define regCM3_CM_GAMCOR_RAMB_REGION_28_29_BASE_IDX 2 4721#define regCM3_CM_GAMCOR_RAMB_REGION_30_31 0x11c6 4722#define regCM3_CM_GAMCOR_RAMB_REGION_30_31_BASE_IDX 2 4723#define regCM3_CM_GAMCOR_RAMB_REGION_32_33 0x11c7 4724#define regCM3_CM_GAMCOR_RAMB_REGION_32_33_BASE_IDX 2 4725#define regCM3_CM_HDR_MULT_COEF 0x11c8 4726#define regCM3_CM_HDR_MULT_COEF_BASE_IDX 2 4727#define regCM3_CM_MEM_PWR_CTRL 0x11c9 4728#define regCM3_CM_MEM_PWR_CTRL_BASE_IDX 2 4729#define regCM3_CM_MEM_PWR_STATUS 0x11ca 4730#define regCM3_CM_MEM_PWR_STATUS_BASE_IDX 2 4731#define regCM3_CM_DEALPHA 0x11cc 4732#define regCM3_CM_DEALPHA_BASE_IDX 2 4733#define regCM3_CM_COEF_FORMAT 0x11cd 4734#define regCM3_CM_COEF_FORMAT_BASE_IDX 2 4735 4736 4737// addressBlock: dcn_dc_dpp3_dispdec_dpp_top_dispdec 4738// base address: 0x1104 4739#define regDPP_TOP3_DPP_CONTROL 0x1106 4740#define regDPP_TOP3_DPP_CONTROL_BASE_IDX 2 4741#define regDPP_TOP3_DPP_SOFT_RESET 0x1107 4742#define regDPP_TOP3_DPP_SOFT_RESET_BASE_IDX 2 4743#define regDPP_TOP3_DPP_CRC_VAL_R_G 0x1108 4744#define regDPP_TOP3_DPP_CRC_VAL_R_G_BASE_IDX 2 4745#define regDPP_TOP3_DPP_CRC_VAL_B_A 0x1109 4746#define regDPP_TOP3_DPP_CRC_VAL_B_A_BASE_IDX 2 4747#define regDPP_TOP3_DPP_CRC_CTRL 0x110a 4748#define regDPP_TOP3_DPP_CRC_CTRL_BASE_IDX 2 4749#define regDPP_TOP3_HOST_READ_CONTROL 0x110b 4750#define regDPP_TOP3_HOST_READ_CONTROL_BASE_IDX 2 4751 4752 4753// addressBlock: dcn_dc_mpc_mpcc0_dispdec 4754// base address: 0x0 4755#define regMPCC0_MPCC_TOP_SEL 0x0000 4756#define regMPCC0_MPCC_TOP_SEL_BASE_IDX 3 4757#define regMPCC0_MPCC_BOT_SEL 0x0001 4758#define regMPCC0_MPCC_BOT_SEL_BASE_IDX 3 4759#define regMPCC0_MPCC_OPP_ID 0x0002 4760#define regMPCC0_MPCC_OPP_ID_BASE_IDX 3 4761#define regMPCC0_MPCC_CONTROL 0x0003 4762#define regMPCC0_MPCC_CONTROL_BASE_IDX 3 4763#define regMPCC0_MPCC_SM_CONTROL 0x0004 4764#define regMPCC0_MPCC_SM_CONTROL_BASE_IDX 3 4765#define regMPCC0_MPCC_UPDATE_LOCK_SEL 0x0005 4766#define regMPCC0_MPCC_UPDATE_LOCK_SEL_BASE_IDX 3 4767#define regMPCC0_MPCC_TOP_GAIN 0x0006 4768#define regMPCC0_MPCC_TOP_GAIN_BASE_IDX 3 4769#define regMPCC0_MPCC_BOT_GAIN_INSIDE 0x0007 4770#define regMPCC0_MPCC_BOT_GAIN_INSIDE_BASE_IDX 3 4771#define regMPCC0_MPCC_BOT_GAIN_OUTSIDE 0x0008 4772#define regMPCC0_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX 3 4773#define regMPCC0_MPCC_MOVABLE_CM_LOCATION_CONTROL 0x0009 4774#define regMPCC0_MPCC_MOVABLE_CM_LOCATION_CONTROL_BASE_IDX 3 4775#define regMPCC0_MPCC_BG_R_CR 0x000a 4776#define regMPCC0_MPCC_BG_R_CR_BASE_IDX 3 4777#define regMPCC0_MPCC_BG_G_Y 0x000b 4778#define regMPCC0_MPCC_BG_G_Y_BASE_IDX 3 4779#define regMPCC0_MPCC_BG_B_CB 0x000c 4780#define regMPCC0_MPCC_BG_B_CB_BASE_IDX 3 4781#define regMPCC0_MPCC_MEM_PWR_CTRL 0x000d 4782#define regMPCC0_MPCC_MEM_PWR_CTRL_BASE_IDX 3 4783#define regMPCC0_MPCC_STATUS 0x000e 4784#define regMPCC0_MPCC_STATUS_BASE_IDX 3 4785 4786 4787// addressBlock: dcn_dc_mpc_mpcc1_dispdec 4788// base address: 0x54 4789#define regMPCC1_MPCC_TOP_SEL 0x0015 4790#define regMPCC1_MPCC_TOP_SEL_BASE_IDX 3 4791#define regMPCC1_MPCC_BOT_SEL 0x0016 4792#define regMPCC1_MPCC_BOT_SEL_BASE_IDX 3 4793#define regMPCC1_MPCC_OPP_ID 0x0017 4794#define regMPCC1_MPCC_OPP_ID_BASE_IDX 3 4795#define regMPCC1_MPCC_CONTROL 0x0018 4796#define regMPCC1_MPCC_CONTROL_BASE_IDX 3 4797#define regMPCC1_MPCC_SM_CONTROL 0x0019 4798#define regMPCC1_MPCC_SM_CONTROL_BASE_IDX 3 4799#define regMPCC1_MPCC_UPDATE_LOCK_SEL 0x001a 4800#define regMPCC1_MPCC_UPDATE_LOCK_SEL_BASE_IDX 3 4801#define regMPCC1_MPCC_TOP_GAIN 0x001b 4802#define regMPCC1_MPCC_TOP_GAIN_BASE_IDX 3 4803#define regMPCC1_MPCC_BOT_GAIN_INSIDE 0x001c 4804#define regMPCC1_MPCC_BOT_GAIN_INSIDE_BASE_IDX 3 4805#define regMPCC1_MPCC_BOT_GAIN_OUTSIDE 0x001d 4806#define regMPCC1_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX 3 4807#define regMPCC1_MPCC_MOVABLE_CM_LOCATION_CONTROL 0x001e 4808#define regMPCC1_MPCC_MOVABLE_CM_LOCATION_CONTROL_BASE_IDX 3 4809#define regMPCC1_MPCC_BG_R_CR 0x001f 4810#define regMPCC1_MPCC_BG_R_CR_BASE_IDX 3 4811#define regMPCC1_MPCC_BG_G_Y 0x0020 4812#define regMPCC1_MPCC_BG_G_Y_BASE_IDX 3 4813#define regMPCC1_MPCC_BG_B_CB 0x0021 4814#define regMPCC1_MPCC_BG_B_CB_BASE_IDX 3 4815#define regMPCC1_MPCC_MEM_PWR_CTRL 0x0022 4816#define regMPCC1_MPCC_MEM_PWR_CTRL_BASE_IDX 3 4817#define regMPCC1_MPCC_STATUS 0x0023 4818#define regMPCC1_MPCC_STATUS_BASE_IDX 3 4819 4820 4821// addressBlock: dcn_dc_mpc_mpcc2_dispdec 4822// base address: 0xa8 4823#define regMPCC2_MPCC_TOP_SEL 0x002a 4824#define regMPCC2_MPCC_TOP_SEL_BASE_IDX 3 4825#define regMPCC2_MPCC_BOT_SEL 0x002b 4826#define regMPCC2_MPCC_BOT_SEL_BASE_IDX 3 4827#define regMPCC2_MPCC_OPP_ID 0x002c 4828#define regMPCC2_MPCC_OPP_ID_BASE_IDX 3 4829#define regMPCC2_MPCC_CONTROL 0x002d 4830#define regMPCC2_MPCC_CONTROL_BASE_IDX 3 4831#define regMPCC2_MPCC_SM_CONTROL 0x002e 4832#define regMPCC2_MPCC_SM_CONTROL_BASE_IDX 3 4833#define regMPCC2_MPCC_UPDATE_LOCK_SEL 0x002f 4834#define regMPCC2_MPCC_UPDATE_LOCK_SEL_BASE_IDX 3 4835#define regMPCC2_MPCC_TOP_GAIN 0x0030 4836#define regMPCC2_MPCC_TOP_GAIN_BASE_IDX 3 4837#define regMPCC2_MPCC_BOT_GAIN_INSIDE 0x0031 4838#define regMPCC2_MPCC_BOT_GAIN_INSIDE_BASE_IDX 3 4839#define regMPCC2_MPCC_BOT_GAIN_OUTSIDE 0x0032 4840#define regMPCC2_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX 3 4841#define regMPCC2_MPCC_MOVABLE_CM_LOCATION_CONTROL 0x0033 4842#define regMPCC2_MPCC_MOVABLE_CM_LOCATION_CONTROL_BASE_IDX 3 4843#define regMPCC2_MPCC_BG_R_CR 0x0034 4844#define regMPCC2_MPCC_BG_R_CR_BASE_IDX 3 4845#define regMPCC2_MPCC_BG_G_Y 0x0035 4846#define regMPCC2_MPCC_BG_G_Y_BASE_IDX 3 4847#define regMPCC2_MPCC_BG_B_CB 0x0036 4848#define regMPCC2_MPCC_BG_B_CB_BASE_IDX 3 4849#define regMPCC2_MPCC_MEM_PWR_CTRL 0x0037 4850#define regMPCC2_MPCC_MEM_PWR_CTRL_BASE_IDX 3 4851#define regMPCC2_MPCC_STATUS 0x0038 4852#define regMPCC2_MPCC_STATUS_BASE_IDX 3 4853 4854 4855// addressBlock: dcn_dc_mpc_mpcc3_dispdec 4856// base address: 0xfc 4857#define regMPCC3_MPCC_TOP_SEL 0x003f 4858#define regMPCC3_MPCC_TOP_SEL_BASE_IDX 3 4859#define regMPCC3_MPCC_BOT_SEL 0x0040 4860#define regMPCC3_MPCC_BOT_SEL_BASE_IDX 3 4861#define regMPCC3_MPCC_OPP_ID 0x0041 4862#define regMPCC3_MPCC_OPP_ID_BASE_IDX 3 4863#define regMPCC3_MPCC_CONTROL 0x0042 4864#define regMPCC3_MPCC_CONTROL_BASE_IDX 3 4865#define regMPCC3_MPCC_SM_CONTROL 0x0043 4866#define regMPCC3_MPCC_SM_CONTROL_BASE_IDX 3 4867#define regMPCC3_MPCC_UPDATE_LOCK_SEL 0x0044 4868#define regMPCC3_MPCC_UPDATE_LOCK_SEL_BASE_IDX 3 4869#define regMPCC3_MPCC_TOP_GAIN 0x0045 4870#define regMPCC3_MPCC_TOP_GAIN_BASE_IDX 3 4871#define regMPCC3_MPCC_BOT_GAIN_INSIDE 0x0046 4872#define regMPCC3_MPCC_BOT_GAIN_INSIDE_BASE_IDX 3 4873#define regMPCC3_MPCC_BOT_GAIN_OUTSIDE 0x0047 4874#define regMPCC3_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX 3 4875#define regMPCC3_MPCC_MOVABLE_CM_LOCATION_CONTROL 0x0048 4876#define regMPCC3_MPCC_MOVABLE_CM_LOCATION_CONTROL_BASE_IDX 3 4877#define regMPCC3_MPCC_BG_R_CR 0x0049 4878#define regMPCC3_MPCC_BG_R_CR_BASE_IDX 3 4879#define regMPCC3_MPCC_BG_G_Y 0x004a 4880#define regMPCC3_MPCC_BG_G_Y_BASE_IDX 3 4881#define regMPCC3_MPCC_BG_B_CB 0x004b 4882#define regMPCC3_MPCC_BG_B_CB_BASE_IDX 3 4883#define regMPCC3_MPCC_MEM_PWR_CTRL 0x004c 4884#define regMPCC3_MPCC_MEM_PWR_CTRL_BASE_IDX 3 4885#define regMPCC3_MPCC_STATUS 0x004d 4886#define regMPCC3_MPCC_STATUS_BASE_IDX 3 4887 4888 4889// addressBlock: dcn_dc_mpc_mpc_cfg_dispdec 4890// base address: 0x0 4891#define regMPC_CLOCK_CONTROL 0x0398 4892#define regMPC_CLOCK_CONTROL_BASE_IDX 3 4893#define regMPC_SOFT_RESET 0x0399 4894#define regMPC_SOFT_RESET_BASE_IDX 3 4895#define regMPC_CRC_CTRL 0x039a 4896#define regMPC_CRC_CTRL_BASE_IDX 3 4897#define regMPC_CRC_SEL_CONTROL 0x039b 4898#define regMPC_CRC_SEL_CONTROL_BASE_IDX 3 4899#define regMPC_CRC_RESULT_AR 0x039c 4900#define regMPC_CRC_RESULT_AR_BASE_IDX 3 4901#define regMPC_CRC_RESULT_GB 0x039d 4902#define regMPC_CRC_RESULT_GB_BASE_IDX 3 4903#define regMPC_CRC_RESULT_C 0x039e 4904#define regMPC_CRC_RESULT_C_BASE_IDX 3 4905#define regMPC_BYPASS_BG_AR 0x03a2 4906#define regMPC_BYPASS_BG_AR_BASE_IDX 3 4907#define regMPC_BYPASS_BG_GB 0x03a3 4908#define regMPC_BYPASS_BG_GB_BASE_IDX 3 4909#define regMPC_HOST_READ_CONTROL 0x03a4 4910#define regMPC_HOST_READ_CONTROL_BASE_IDX 3 4911#define regMPC_DPP_PENDING_STATUS 0x03a5 4912#define regMPC_DPP_PENDING_STATUS_BASE_IDX 3 4913#define regMPC_PENDING_STATUS_MISC 0x03a6 4914#define regMPC_PENDING_STATUS_MISC_BASE_IDX 3 4915#define regADR_CFG_CUR_VUPDATE_LOCK_SET0 0x03a7 4916#define regADR_CFG_CUR_VUPDATE_LOCK_SET0_BASE_IDX 3 4917#define regADR_CFG_VUPDATE_LOCK_SET0 0x03a8 4918#define regADR_CFG_VUPDATE_LOCK_SET0_BASE_IDX 3 4919#define regADR_VUPDATE_LOCK_SET0 0x03a9 4920#define regADR_VUPDATE_LOCK_SET0_BASE_IDX 3 4921#define regCFG_VUPDATE_LOCK_SET0 0x03aa 4922#define regCFG_VUPDATE_LOCK_SET0_BASE_IDX 3 4923#define regCUR_VUPDATE_LOCK_SET0 0x03ab 4924#define regCUR_VUPDATE_LOCK_SET0_BASE_IDX 3 4925#define regADR_CFG_CUR_VUPDATE_LOCK_SET1 0x03ac 4926#define regADR_CFG_CUR_VUPDATE_LOCK_SET1_BASE_IDX 3 4927#define regADR_CFG_VUPDATE_LOCK_SET1 0x03ad 4928#define regADR_CFG_VUPDATE_LOCK_SET1_BASE_IDX 3 4929#define regADR_VUPDATE_LOCK_SET1 0x03ae 4930#define regADR_VUPDATE_LOCK_SET1_BASE_IDX 3 4931#define regCFG_VUPDATE_LOCK_SET1 0x03af 4932#define regCFG_VUPDATE_LOCK_SET1_BASE_IDX 3 4933#define regCUR_VUPDATE_LOCK_SET1 0x03b0 4934#define regCUR_VUPDATE_LOCK_SET1_BASE_IDX 3 4935#define regADR_CFG_CUR_VUPDATE_LOCK_SET2 0x03b1 4936#define regADR_CFG_CUR_VUPDATE_LOCK_SET2_BASE_IDX 3 4937#define regADR_CFG_VUPDATE_LOCK_SET2 0x03b2 4938#define regADR_CFG_VUPDATE_LOCK_SET2_BASE_IDX 3 4939#define regADR_VUPDATE_LOCK_SET2 0x03b3 4940#define regADR_VUPDATE_LOCK_SET2_BASE_IDX 3 4941#define regCFG_VUPDATE_LOCK_SET2 0x03b4 4942#define regCFG_VUPDATE_LOCK_SET2_BASE_IDX 3 4943#define regCUR_VUPDATE_LOCK_SET2 0x03b5 4944#define regCUR_VUPDATE_LOCK_SET2_BASE_IDX 3 4945#define regADR_CFG_CUR_VUPDATE_LOCK_SET3 0x03b6 4946#define regADR_CFG_CUR_VUPDATE_LOCK_SET3_BASE_IDX 3 4947#define regADR_CFG_VUPDATE_LOCK_SET3 0x03b7 4948#define regADR_CFG_VUPDATE_LOCK_SET3_BASE_IDX 3 4949#define regADR_VUPDATE_LOCK_SET3 0x03b8 4950#define regADR_VUPDATE_LOCK_SET3_BASE_IDX 3 4951#define regCFG_VUPDATE_LOCK_SET3 0x03b9 4952#define regCFG_VUPDATE_LOCK_SET3_BASE_IDX 3 4953#define regCUR_VUPDATE_LOCK_SET3 0x03ba 4954#define regCUR_VUPDATE_LOCK_SET3_BASE_IDX 3 4955#define regMPC_DWB0_MUX 0x03c6 4956#define regMPC_DWB0_MUX_BASE_IDX 3 4957 4958 4959// addressBlock: dcn_dc_mpc_mpcc_ogam0_dispdec 4960// base address: 0x0 4961#define regMPCC_OGAM0_MPCC_OGAM_CONTROL 0x00a8 4962#define regMPCC_OGAM0_MPCC_OGAM_CONTROL_BASE_IDX 3 4963#define regMPCC_OGAM0_MPCC_OGAM_LUT_INDEX 0x00a9 4964#define regMPCC_OGAM0_MPCC_OGAM_LUT_INDEX_BASE_IDX 3 4965#define regMPCC_OGAM0_MPCC_OGAM_LUT_DATA 0x00aa 4966#define regMPCC_OGAM0_MPCC_OGAM_LUT_DATA_BASE_IDX 3 4967#define regMPCC_OGAM0_MPCC_OGAM_LUT_CONTROL 0x00ab 4968#define regMPCC_OGAM0_MPCC_OGAM_LUT_CONTROL_BASE_IDX 3 4969#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B 0x00ac 4970#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX 3 4971#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G 0x00ad 4972#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX 3 4973#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R 0x00ae 4974#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX 3 4975#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B 0x00af 4976#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX 3 4977#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G 0x00b0 4978#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 3 4979#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R 0x00b1 4980#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX 3 4981#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_B 0x00b2 4982#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX 3 4983#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_G 0x00b3 4984#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX 3 4985#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_R 0x00b4 4986#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX 3 4987#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B 0x00b5 4988#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX 3 4989#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B 0x00b6 4990#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX 3 4991#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_G 0x00b7 4992#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX 3 4993#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G 0x00b8 4994#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX 3 4995#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_R 0x00b9 4996#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX 3 4997#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R 0x00ba 4998#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX 3 4999#define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_B 0x00bb 5000#define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_B_BASE_IDX 3 5001#define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_G 0x00bc 5002#define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX 3 5003#define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_R 0x00bd 5004#define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_R_BASE_IDX 3 5005#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1 0x00be 5006#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX 3 5007#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3 0x00bf 5008#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX 3 5009#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5 0x00c0 5010#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX 3 5011#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7 0x00c1 5012#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX 3 5013#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9 0x00c2 5014#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX 3 5015#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11 0x00c3 5016#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX 3 5017#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13 0x00c4 5018#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX 3 5019#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15 0x00c5 5020#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX 3 5021#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17 0x00c6 5022#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX 3 5023#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19 0x00c7 5024#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX 3 5025#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21 0x00c8 5026#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX 3 5027#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23 0x00c9 5028#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX 3 5029#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25 0x00ca 5030#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX 3 5031#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27 0x00cb 5032#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX 3 5033#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29 0x00cc 5034#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX 3 5035#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31 0x00cd 5036#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX 3 5037#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33 0x00ce 5038#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX 3 5039#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B 0x00cf 5040#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX 3 5041#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G 0x00d0 5042#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX 3 5043#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R 0x00d1 5044#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX 3 5045#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B 0x00d2 5046#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX 3 5047#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G 0x00d3 5048#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX 3 5049#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R 0x00d4 5050#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX 3 5051#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_B 0x00d5 5052#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX 3 5053#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_G 0x00d6 5054#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX 3 5055#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_R 0x00d7 5056#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX 3 5057#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_B 0x00d8 5058#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX 3 5059#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B 0x00d9 5060#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX 3 5061#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_G 0x00da 5062#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX 3 5063#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G 0x00db 5064#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX 3 5065#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_R 0x00dc 5066#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX 3 5067#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R 0x00dd 5068#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX 3 5069#define regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_B 0x00de 5070#define regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_B_BASE_IDX 3 5071#define regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_G 0x00df 5072#define regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_G_BASE_IDX 3 5073#define regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_R 0x00e0 5074#define regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_R_BASE_IDX 3 5075#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1 0x00e1 5076#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX 3 5077#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3 0x00e2 5078#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX 3 5079#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5 0x00e3 5080#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX 3 5081#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7 0x00e4 5082#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX 3 5083#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9 0x00e5 5084#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX 3 5085#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11 0x00e6 5086#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX 3 5087#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13 0x00e7 5088#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX 3 5089#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15 0x00e8 5090#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX 3 5091#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17 0x00e9 5092#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX 3 5093#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19 0x00ea 5094#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX 3 5095#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21 0x00eb 5096#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX 3 5097#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23 0x00ec 5098#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX 3 5099#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25 0x00ed 5100#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX 3 5101#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27 0x00ee 5102#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX 3 5103#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29 0x00ef 5104#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX 3 5105#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31 0x00f0 5106#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX 3 5107#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33 0x00f1 5108#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX 3 5109#define regMPCC_OGAM0_MPCC_GAMUT_REMAP_COEF_FORMAT 0x00f2 5110#define regMPCC_OGAM0_MPCC_GAMUT_REMAP_COEF_FORMAT_BASE_IDX 3 5111#define regMPCC_OGAM0_MPCC_GAMUT_REMAP_MODE 0x00f3 5112#define regMPCC_OGAM0_MPCC_GAMUT_REMAP_MODE_BASE_IDX 3 5113#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A 0x00f4 5114#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A_BASE_IDX 3 5115#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_A 0x00f5 5116#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_A_BASE_IDX 3 5117#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_A 0x00f6 5118#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_A_BASE_IDX 3 5119#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_A 0x00f7 5120#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_A_BASE_IDX 3 5121#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_A 0x00f8 5122#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_A_BASE_IDX 3 5123#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_A 0x00f9 5124#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_A_BASE_IDX 3 5125#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_B 0x00fa 5126#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_B_BASE_IDX 3 5127#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_B 0x00fb 5128#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_B_BASE_IDX 3 5129#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_B 0x00fc 5130#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_B_BASE_IDX 3 5131#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_B 0x00fd 5132#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_B_BASE_IDX 3 5133#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_B 0x00fe 5134#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_B_BASE_IDX 3 5135#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_B 0x00ff 5136#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_B_BASE_IDX 3 5137 5138 5139// addressBlock: dcn_dc_mpc_mpcc_ogam1_dispdec 5140// base address: 0x178 5141#define regMPCC_OGAM1_MPCC_OGAM_CONTROL 0x0106 5142#define regMPCC_OGAM1_MPCC_OGAM_CONTROL_BASE_IDX 3 5143#define regMPCC_OGAM1_MPCC_OGAM_LUT_INDEX 0x0107 5144#define regMPCC_OGAM1_MPCC_OGAM_LUT_INDEX_BASE_IDX 3 5145#define regMPCC_OGAM1_MPCC_OGAM_LUT_DATA 0x0108 5146#define regMPCC_OGAM1_MPCC_OGAM_LUT_DATA_BASE_IDX 3 5147#define regMPCC_OGAM1_MPCC_OGAM_LUT_CONTROL 0x0109 5148#define regMPCC_OGAM1_MPCC_OGAM_LUT_CONTROL_BASE_IDX 3 5149#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B 0x010a 5150#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX 3 5151#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G 0x010b 5152#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX 3 5153#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R 0x010c 5154#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX 3 5155#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B 0x010d 5156#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX 3 5157#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G 0x010e 5158#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 3 5159#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R 0x010f 5160#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX 3 5161#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_B 0x0110 5162#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX 3 5163#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_G 0x0111 5164#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX 3 5165#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_R 0x0112 5166#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX 3 5167#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_B 0x0113 5168#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX 3 5169#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B 0x0114 5170#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX 3 5171#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_G 0x0115 5172#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX 3 5173#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G 0x0116 5174#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX 3 5175#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_R 0x0117 5176#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX 3 5177#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R 0x0118 5178#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX 3 5179#define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_B 0x0119 5180#define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_B_BASE_IDX 3 5181#define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_G 0x011a 5182#define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX 3 5183#define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_R 0x011b 5184#define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_R_BASE_IDX 3 5185#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1 0x011c 5186#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX 3 5187#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3 0x011d 5188#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX 3 5189#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5 0x011e 5190#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX 3 5191#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7 0x011f 5192#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX 3 5193#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9 0x0120 5194#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX 3 5195#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11 0x0121 5196#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX 3 5197#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13 0x0122 5198#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX 3 5199#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15 0x0123 5200#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX 3 5201#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17 0x0124 5202#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX 3 5203#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19 0x0125 5204#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX 3 5205#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21 0x0126 5206#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX 3 5207#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23 0x0127 5208#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX 3 5209#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25 0x0128 5210#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX 3 5211#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27 0x0129 5212#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX 3 5213#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29 0x012a 5214#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX 3 5215#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31 0x012b 5216#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX 3 5217#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33 0x012c 5218#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX 3 5219#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B 0x012d 5220#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX 3 5221#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G 0x012e 5222#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX 3 5223#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R 0x012f 5224#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX 3 5225#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B 0x0130 5226#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX 3 5227#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G 0x0131 5228#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX 3 5229#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R 0x0132 5230#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX 3 5231#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_B 0x0133 5232#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX 3 5233#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_G 0x0134 5234#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX 3 5235#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_R 0x0135 5236#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX 3 5237#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_B 0x0136 5238#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX 3 5239#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B 0x0137 5240#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX 3 5241#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_G 0x0138 5242#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX 3 5243#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G 0x0139 5244#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX 3 5245#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_R 0x013a 5246#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX 3 5247#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R 0x013b 5248#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX 3 5249#define regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_B 0x013c 5250#define regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_B_BASE_IDX 3 5251#define regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_G 0x013d 5252#define regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_G_BASE_IDX 3 5253#define regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_R 0x013e 5254#define regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_R_BASE_IDX 3 5255#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1 0x013f 5256#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX 3 5257#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3 0x0140 5258#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX 3 5259#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5 0x0141 5260#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX 3 5261#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7 0x0142 5262#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX 3 5263#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9 0x0143 5264#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX 3 5265#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11 0x0144 5266#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX 3 5267#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13 0x0145 5268#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX 3 5269#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15 0x0146 5270#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX 3 5271#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17 0x0147 5272#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX 3 5273#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19 0x0148 5274#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX 3 5275#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21 0x0149 5276#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX 3 5277#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23 0x014a 5278#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX 3 5279#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25 0x014b 5280#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX 3 5281#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27 0x014c 5282#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX 3 5283#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29 0x014d 5284#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX 3 5285#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31 0x014e 5286#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX 3 5287#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33 0x014f 5288#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX 3 5289#define regMPCC_OGAM1_MPCC_GAMUT_REMAP_COEF_FORMAT 0x0150 5290#define regMPCC_OGAM1_MPCC_GAMUT_REMAP_COEF_FORMAT_BASE_IDX 3 5291#define regMPCC_OGAM1_MPCC_GAMUT_REMAP_MODE 0x0151 5292#define regMPCC_OGAM1_MPCC_GAMUT_REMAP_MODE_BASE_IDX 3 5293#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_A 0x0152 5294#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_A_BASE_IDX 3 5295#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_A 0x0153 5296#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_A_BASE_IDX 3 5297#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_A 0x0154 5298#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_A_BASE_IDX 3 5299#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_A 0x0155 5300#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_A_BASE_IDX 3 5301#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_A 0x0156 5302#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_A_BASE_IDX 3 5303#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_A 0x0157 5304#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_A_BASE_IDX 3 5305#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_B 0x0158 5306#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_B_BASE_IDX 3 5307#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_B 0x0159 5308#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_B_BASE_IDX 3 5309#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_B 0x015a 5310#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_B_BASE_IDX 3 5311#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_B 0x015b 5312#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_B_BASE_IDX 3 5313#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_B 0x015c 5314#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_B_BASE_IDX 3 5315#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_B 0x015d 5316#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_B_BASE_IDX 3 5317 5318 5319// addressBlock: dcn_dc_mpc_mpcc_ogam2_dispdec 5320// base address: 0x2f0 5321#define regMPCC_OGAM2_MPCC_OGAM_CONTROL 0x0164 5322#define regMPCC_OGAM2_MPCC_OGAM_CONTROL_BASE_IDX 3 5323#define regMPCC_OGAM2_MPCC_OGAM_LUT_INDEX 0x0165 5324#define regMPCC_OGAM2_MPCC_OGAM_LUT_INDEX_BASE_IDX 3 5325#define regMPCC_OGAM2_MPCC_OGAM_LUT_DATA 0x0166 5326#define regMPCC_OGAM2_MPCC_OGAM_LUT_DATA_BASE_IDX 3 5327#define regMPCC_OGAM2_MPCC_OGAM_LUT_CONTROL 0x0167 5328#define regMPCC_OGAM2_MPCC_OGAM_LUT_CONTROL_BASE_IDX 3 5329#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B 0x0168 5330#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX 3 5331#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G 0x0169 5332#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX 3 5333#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R 0x016a 5334#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX 3 5335#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B 0x016b 5336#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX 3 5337#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G 0x016c 5338#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 3 5339#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R 0x016d 5340#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX 3 5341#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_B 0x016e 5342#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX 3 5343#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_G 0x016f 5344#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX 3 5345#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_R 0x0170 5346#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX 3 5347#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_B 0x0171 5348#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX 3 5349#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B 0x0172 5350#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX 3 5351#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_G 0x0173 5352#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX 3 5353#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G 0x0174 5354#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX 3 5355#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_R 0x0175 5356#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX 3 5357#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R 0x0176 5358#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX 3 5359#define regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_B 0x0177 5360#define regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_B_BASE_IDX 3 5361#define regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_G 0x0178 5362#define regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX 3 5363#define regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_R 0x0179 5364#define regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_R_BASE_IDX 3 5365#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1 0x017a 5366#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX 3 5367#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3 0x017b 5368#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX 3 5369#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5 0x017c 5370#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX 3 5371#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7 0x017d 5372#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX 3 5373#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9 0x017e 5374#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX 3 5375#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11 0x017f 5376#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX 3 5377#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13 0x0180 5378#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX 3 5379#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15 0x0181 5380#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX 3 5381#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17 0x0182 5382#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX 3 5383#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19 0x0183 5384#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX 3 5385#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21 0x0184 5386#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX 3 5387#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23 0x0185 5388#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX 3 5389#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25 0x0186 5390#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX 3 5391#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27 0x0187 5392#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX 3 5393#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29 0x0188 5394#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX 3 5395#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31 0x0189 5396#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX 3 5397#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33 0x018a 5398#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX 3 5399#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B 0x018b 5400#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX 3 5401#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G 0x018c 5402#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX 3 5403#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R 0x018d 5404#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX 3 5405#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B 0x018e 5406#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX 3 5407#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G 0x018f 5408#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX 3 5409#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R 0x0190 5410#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX 3 5411#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_B 0x0191 5412#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX 3 5413#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_G 0x0192 5414#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX 3 5415#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_R 0x0193 5416#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX 3 5417#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_B 0x0194 5418#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX 3 5419#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B 0x0195 5420#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX 3 5421#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_G 0x0196 5422#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX 3 5423#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G 0x0197 5424#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX 3 5425#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_R 0x0198 5426#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX 3 5427#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R 0x0199 5428#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX 3 5429#define regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_B 0x019a 5430#define regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_B_BASE_IDX 3 5431#define regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_G 0x019b 5432#define regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_G_BASE_IDX 3 5433#define regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_R 0x019c 5434#define regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_R_BASE_IDX 3 5435#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1 0x019d 5436#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX 3 5437#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3 0x019e 5438#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX 3 5439#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5 0x019f 5440#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX 3 5441#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7 0x01a0 5442#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX 3 5443#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9 0x01a1 5444#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX 3 5445#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11 0x01a2 5446#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX 3 5447#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13 0x01a3 5448#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX 3 5449#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15 0x01a4 5450#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX 3 5451#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17 0x01a5 5452#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX 3 5453#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19 0x01a6 5454#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX 3 5455#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21 0x01a7 5456#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX 3 5457#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23 0x01a8 5458#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX 3 5459#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25 0x01a9 5460#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX 3 5461#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27 0x01aa 5462#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX 3 5463#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29 0x01ab 5464#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX 3 5465#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31 0x01ac 5466#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX 3 5467#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33 0x01ad 5468#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX 3 5469#define regMPCC_OGAM2_MPCC_GAMUT_REMAP_COEF_FORMAT 0x01ae 5470#define regMPCC_OGAM2_MPCC_GAMUT_REMAP_COEF_FORMAT_BASE_IDX 3 5471#define regMPCC_OGAM2_MPCC_GAMUT_REMAP_MODE 0x01af 5472#define regMPCC_OGAM2_MPCC_GAMUT_REMAP_MODE_BASE_IDX 3 5473#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_A 0x01b0 5474#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_A_BASE_IDX 3 5475#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_A 0x01b1 5476#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_A_BASE_IDX 3 5477#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_A 0x01b2 5478#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_A_BASE_IDX 3 5479#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_A 0x01b3 5480#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_A_BASE_IDX 3 5481#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_A 0x01b4 5482#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_A_BASE_IDX 3 5483#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_A 0x01b5 5484#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_A_BASE_IDX 3 5485#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_B 0x01b6 5486#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_B_BASE_IDX 3 5487#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_B 0x01b7 5488#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_B_BASE_IDX 3 5489#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_B 0x01b8 5490#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_B_BASE_IDX 3 5491#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_B 0x01b9 5492#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_B_BASE_IDX 3 5493#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_B 0x01ba 5494#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_B_BASE_IDX 3 5495#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_B 0x01bb 5496#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_B_BASE_IDX 3 5497 5498 5499// addressBlock: dcn_dc_mpc_mpcc_ogam3_dispdec 5500// base address: 0x468 5501#define regMPCC_OGAM3_MPCC_OGAM_CONTROL 0x01c2 5502#define regMPCC_OGAM3_MPCC_OGAM_CONTROL_BASE_IDX 3 5503#define regMPCC_OGAM3_MPCC_OGAM_LUT_INDEX 0x01c3 5504#define regMPCC_OGAM3_MPCC_OGAM_LUT_INDEX_BASE_IDX 3 5505#define regMPCC_OGAM3_MPCC_OGAM_LUT_DATA 0x01c4 5506#define regMPCC_OGAM3_MPCC_OGAM_LUT_DATA_BASE_IDX 3 5507#define regMPCC_OGAM3_MPCC_OGAM_LUT_CONTROL 0x01c5 5508#define regMPCC_OGAM3_MPCC_OGAM_LUT_CONTROL_BASE_IDX 3 5509#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B 0x01c6 5510#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX 3 5511#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G 0x01c7 5512#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX 3 5513#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R 0x01c8 5514#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX 3 5515#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B 0x01c9 5516#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX 3 5517#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G 0x01ca 5518#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 3 5519#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R 0x01cb 5520#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX 3 5521#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_B 0x01cc 5522#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX 3 5523#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_G 0x01cd 5524#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX 3 5525#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_R 0x01ce 5526#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX 3 5527#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_B 0x01cf 5528#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX 3 5529#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B 0x01d0 5530#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX 3 5531#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_G 0x01d1 5532#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX 3 5533#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G 0x01d2 5534#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX 3 5535#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_R 0x01d3 5536#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX 3 5537#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R 0x01d4 5538#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX 3 5539#define regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_B 0x01d5 5540#define regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_B_BASE_IDX 3 5541#define regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_G 0x01d6 5542#define regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX 3 5543#define regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_R 0x01d7 5544#define regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_R_BASE_IDX 3 5545#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1 0x01d8 5546#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX 3 5547#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3 0x01d9 5548#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX 3 5549#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5 0x01da 5550#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX 3 5551#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7 0x01db 5552#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX 3 5553#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9 0x01dc 5554#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX 3 5555#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11 0x01dd 5556#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX 3 5557#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13 0x01de 5558#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX 3 5559#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15 0x01df 5560#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX 3 5561#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17 0x01e0 5562#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX 3 5563#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19 0x01e1 5564#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX 3 5565#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21 0x01e2 5566#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX 3 5567#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23 0x01e3 5568#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX 3 5569#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25 0x01e4 5570#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX 3 5571#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27 0x01e5 5572#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX 3 5573#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29 0x01e6 5574#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX 3 5575#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31 0x01e7 5576#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX 3 5577#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33 0x01e8 5578#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX 3 5579#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B 0x01e9 5580#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX 3 5581#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G 0x01ea 5582#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX 3 5583#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R 0x01eb 5584#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX 3 5585#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B 0x01ec 5586#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX 3 5587#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G 0x01ed 5588#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX 3 5589#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R 0x01ee 5590#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX 3 5591#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_B 0x01ef 5592#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX 3 5593#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_G 0x01f0 5594#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX 3 5595#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_R 0x01f1 5596#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX 3 5597#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_B 0x01f2 5598#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX 3 5599#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B 0x01f3 5600#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX 3 5601#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_G 0x01f4 5602#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX 3 5603#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G 0x01f5 5604#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX 3 5605#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_R 0x01f6 5606#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX 3 5607#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R 0x01f7 5608#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX 3 5609#define regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_B 0x01f8 5610#define regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_B_BASE_IDX 3 5611#define regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_G 0x01f9 5612#define regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_G_BASE_IDX 3 5613#define regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_R 0x01fa 5614#define regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_R_BASE_IDX 3 5615#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1 0x01fb 5616#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX 3 5617#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3 0x01fc 5618#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX 3 5619#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5 0x01fd 5620#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX 3 5621#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7 0x01fe 5622#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX 3 5623#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9 0x01ff 5624#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX 3 5625#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11 0x0200 5626#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX 3 5627#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13 0x0201 5628#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX 3 5629#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15 0x0202 5630#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX 3 5631#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17 0x0203 5632#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX 3 5633#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19 0x0204 5634#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX 3 5635#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21 0x0205 5636#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX 3 5637#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23 0x0206 5638#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX 3 5639#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25 0x0207 5640#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX 3 5641#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27 0x0208 5642#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX 3 5643#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29 0x0209 5644#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX 3 5645#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31 0x020a 5646#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX 3 5647#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33 0x020b 5648#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX 3 5649#define regMPCC_OGAM3_MPCC_GAMUT_REMAP_COEF_FORMAT 0x020c 5650#define regMPCC_OGAM3_MPCC_GAMUT_REMAP_COEF_FORMAT_BASE_IDX 3 5651#define regMPCC_OGAM3_MPCC_GAMUT_REMAP_MODE 0x020d 5652#define regMPCC_OGAM3_MPCC_GAMUT_REMAP_MODE_BASE_IDX 3 5653#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_A 0x020e 5654#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_A_BASE_IDX 3 5655#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_A 0x020f 5656#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_A_BASE_IDX 3 5657#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_A 0x0210 5658#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_A_BASE_IDX 3 5659#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_A 0x0211 5660#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_A_BASE_IDX 3 5661#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_A 0x0212 5662#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_A_BASE_IDX 3 5663#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_A 0x0213 5664#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_A_BASE_IDX 3 5665#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_B 0x0214 5666#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_B_BASE_IDX 3 5667#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_B 0x0215 5668#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_B_BASE_IDX 3 5669#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_B 0x0216 5670#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_B_BASE_IDX 3 5671#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_B 0x0217 5672#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_B_BASE_IDX 3 5673#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_B 0x0218 5674#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_B_BASE_IDX 3 5675#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_B 0x0219 5676#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_B_BASE_IDX 3 5677 5678 5679// addressBlock: dcn_dc_mpc_mpcc_mcm0_dispdec 5680// base address: 0x0 5681#define regMPCC_MCM0_MPCC_MCM_SHAPER_CONTROL 0x0453 5682#define regMPCC_MCM0_MPCC_MCM_SHAPER_CONTROL_BASE_IDX 3 5683#define regMPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_R 0x0454 5684#define regMPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_R_BASE_IDX 3 5685#define regMPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_G 0x0455 5686#define regMPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_G_BASE_IDX 3 5687#define regMPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_B 0x0456 5688#define regMPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_B_BASE_IDX 3 5689#define regMPCC_MCM0_MPCC_MCM_SHAPER_SCALE_R 0x0457 5690#define regMPCC_MCM0_MPCC_MCM_SHAPER_SCALE_R_BASE_IDX 3 5691#define regMPCC_MCM0_MPCC_MCM_SHAPER_SCALE_G_B 0x0458 5692#define regMPCC_MCM0_MPCC_MCM_SHAPER_SCALE_G_B_BASE_IDX 3 5693#define regMPCC_MCM0_MPCC_MCM_SHAPER_LUT_INDEX 0x0459 5694#define regMPCC_MCM0_MPCC_MCM_SHAPER_LUT_INDEX_BASE_IDX 3 5695#define regMPCC_MCM0_MPCC_MCM_SHAPER_LUT_DATA 0x045a 5696#define regMPCC_MCM0_MPCC_MCM_SHAPER_LUT_DATA_BASE_IDX 3 5697#define regMPCC_MCM0_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK 0x045b 5698#define regMPCC_MCM0_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX 3 5699#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_B 0x045c 5700#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_B_BASE_IDX 3 5701#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_G 0x045d 5702#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_G_BASE_IDX 3 5703#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_R 0x045e 5704#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_R_BASE_IDX 3 5705#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_B 0x045f 5706#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_B_BASE_IDX 3 5707#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_G 0x0460 5708#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_G_BASE_IDX 3 5709#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_R 0x0461 5710#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_R_BASE_IDX 3 5711#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_0_1 0x0462 5712#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_0_1_BASE_IDX 3 5713#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_2_3 0x0463 5714#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_2_3_BASE_IDX 3 5715#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_4_5 0x0464 5716#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_4_5_BASE_IDX 3 5717#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_6_7 0x0465 5718#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_6_7_BASE_IDX 3 5719#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_8_9 0x0466 5720#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_8_9_BASE_IDX 3 5721#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_10_11 0x0467 5722#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_10_11_BASE_IDX 3 5723#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_12_13 0x0468 5724#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_12_13_BASE_IDX 3 5725#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_14_15 0x0469 5726#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_14_15_BASE_IDX 3 5727#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_16_17 0x046a 5728#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_16_17_BASE_IDX 3 5729#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_18_19 0x046b 5730#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_18_19_BASE_IDX 3 5731#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_20_21 0x046c 5732#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_20_21_BASE_IDX 3 5733#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_22_23 0x046d 5734#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_22_23_BASE_IDX 3 5735#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_24_25 0x046e 5736#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_24_25_BASE_IDX 3 5737#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_26_27 0x046f 5738#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_26_27_BASE_IDX 3 5739#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_28_29 0x0470 5740#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_28_29_BASE_IDX 3 5741#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_30_31 0x0471 5742#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_30_31_BASE_IDX 3 5743#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_32_33 0x0472 5744#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_32_33_BASE_IDX 3 5745#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_B 0x0473 5746#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_B_BASE_IDX 3 5747#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_G 0x0474 5748#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_G_BASE_IDX 3 5749#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_R 0x0475 5750#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_R_BASE_IDX 3 5751#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_B 0x0476 5752#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_B_BASE_IDX 3 5753#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_G 0x0477 5754#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_G_BASE_IDX 3 5755#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_R 0x0478 5756#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_R_BASE_IDX 3 5757#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_0_1 0x0479 5758#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_0_1_BASE_IDX 3 5759#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_2_3 0x047a 5760#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_2_3_BASE_IDX 3 5761#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_4_5 0x047b 5762#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_4_5_BASE_IDX 3 5763#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_6_7 0x047c 5764#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_6_7_BASE_IDX 3 5765#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_8_9 0x047d 5766#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_8_9_BASE_IDX 3 5767#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_10_11 0x047e 5768#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_10_11_BASE_IDX 3 5769#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_12_13 0x047f 5770#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_12_13_BASE_IDX 3 5771#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_14_15 0x0480 5772#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_14_15_BASE_IDX 3 5773#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_16_17 0x0481 5774#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_16_17_BASE_IDX 3 5775#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_18_19 0x0482 5776#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_18_19_BASE_IDX 3 5777#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_20_21 0x0483 5778#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_20_21_BASE_IDX 3 5779#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_22_23 0x0484 5780#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_22_23_BASE_IDX 3 5781#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_24_25 0x0485 5782#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_24_25_BASE_IDX 3 5783#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_26_27 0x0486 5784#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_26_27_BASE_IDX 3 5785#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_28_29 0x0487 5786#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_28_29_BASE_IDX 3 5787#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_30_31 0x0488 5788#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_30_31_BASE_IDX 3 5789#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_32_33 0x0489 5790#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_32_33_BASE_IDX 3 5791#define regMPCC_MCM0_MPCC_MCM_3DLUT_MODE 0x048a 5792#define regMPCC_MCM0_MPCC_MCM_3DLUT_MODE_BASE_IDX 3 5793#define regMPCC_MCM0_MPCC_MCM_3DLUT_INDEX 0x048b 5794#define regMPCC_MCM0_MPCC_MCM_3DLUT_INDEX_BASE_IDX 3 5795#define regMPCC_MCM0_MPCC_MCM_3DLUT_DATA 0x048c 5796#define regMPCC_MCM0_MPCC_MCM_3DLUT_DATA_BASE_IDX 3 5797#define regMPCC_MCM0_MPCC_MCM_3DLUT_DATA_30BIT 0x048d 5798#define regMPCC_MCM0_MPCC_MCM_3DLUT_DATA_30BIT_BASE_IDX 3 5799#define regMPCC_MCM0_MPCC_MCM_3DLUT_READ_WRITE_CONTROL 0x048e 5800#define regMPCC_MCM0_MPCC_MCM_3DLUT_READ_WRITE_CONTROL_BASE_IDX 3 5801#define regMPCC_MCM0_MPCC_MCM_3DLUT_OUT_NORM_FACTOR 0x048f 5802#define regMPCC_MCM0_MPCC_MCM_3DLUT_OUT_NORM_FACTOR_BASE_IDX 3 5803#define regMPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_R 0x0490 5804#define regMPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_R_BASE_IDX 3 5805#define regMPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_G 0x0491 5806#define regMPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_G_BASE_IDX 3 5807#define regMPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_B 0x0492 5808#define regMPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_B_BASE_IDX 3 5809#define regMPCC_MCM0_MPCC_MCM_1DLUT_CONTROL 0x0493 5810#define regMPCC_MCM0_MPCC_MCM_1DLUT_CONTROL_BASE_IDX 3 5811#define regMPCC_MCM0_MPCC_MCM_1DLUT_LUT_INDEX 0x0494 5812#define regMPCC_MCM0_MPCC_MCM_1DLUT_LUT_INDEX_BASE_IDX 3 5813#define regMPCC_MCM0_MPCC_MCM_1DLUT_LUT_DATA 0x0495 5814#define regMPCC_MCM0_MPCC_MCM_1DLUT_LUT_DATA_BASE_IDX 3 5815#define regMPCC_MCM0_MPCC_MCM_1DLUT_LUT_CONTROL 0x0496 5816#define regMPCC_MCM0_MPCC_MCM_1DLUT_LUT_CONTROL_BASE_IDX 3 5817#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_B 0x0497 5818#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_B_BASE_IDX 3 5819#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_G 0x0498 5820#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_G_BASE_IDX 3 5821#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_R 0x0499 5822#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_R_BASE_IDX 3 5823#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B 0x049a 5824#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B_BASE_IDX 3 5825#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G 0x049b 5826#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G_BASE_IDX 3 5827#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R 0x049c 5828#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R_BASE_IDX 3 5829#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B 0x049d 5830#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B_BASE_IDX 3 5831#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G 0x049e 5832#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G_BASE_IDX 3 5833#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R 0x049f 5834#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R_BASE_IDX 3 5835#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B 0x04a0 5836#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B_BASE_IDX 3 5837#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B 0x04a1 5838#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B_BASE_IDX 3 5839#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G 0x04a2 5840#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G_BASE_IDX 3 5841#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G 0x04a3 5842#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G_BASE_IDX 3 5843#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R 0x04a4 5844#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R_BASE_IDX 3 5845#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R 0x04a5 5846#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R_BASE_IDX 3 5847#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_B 0x04a6 5848#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_B_BASE_IDX 3 5849#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_G 0x04a7 5850#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_G_BASE_IDX 3 5851#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_R 0x04a8 5852#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_R_BASE_IDX 3 5853#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_0_1 0x04a9 5854#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_0_1_BASE_IDX 3 5855#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_2_3 0x04aa 5856#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_2_3_BASE_IDX 3 5857#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_4_5 0x04ab 5858#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_4_5_BASE_IDX 3 5859#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_6_7 0x04ac 5860#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_6_7_BASE_IDX 3 5861#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_8_9 0x04ad 5862#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_8_9_BASE_IDX 3 5863#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_10_11 0x04ae 5864#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_10_11_BASE_IDX 3 5865#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_12_13 0x04af 5866#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_12_13_BASE_IDX 3 5867#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_14_15 0x04b0 5868#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_14_15_BASE_IDX 3 5869#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_16_17 0x04b1 5870#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_16_17_BASE_IDX 3 5871#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_18_19 0x04b2 5872#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_18_19_BASE_IDX 3 5873#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_20_21 0x04b3 5874#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_20_21_BASE_IDX 3 5875#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_22_23 0x04b4 5876#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_22_23_BASE_IDX 3 5877#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_24_25 0x04b5 5878#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_24_25_BASE_IDX 3 5879#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_26_27 0x04b6 5880#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_26_27_BASE_IDX 3 5881#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_28_29 0x04b7 5882#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_28_29_BASE_IDX 3 5883#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_30_31 0x04b8 5884#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_30_31_BASE_IDX 3 5885#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_32_33 0x04b9 5886#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_32_33_BASE_IDX 3 5887#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_B 0x04ba 5888#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_B_BASE_IDX 3 5889#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_G 0x04bb 5890#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_G_BASE_IDX 3 5891#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_R 0x04bc 5892#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_R_BASE_IDX 3 5893#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B 0x04bd 5894#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B_BASE_IDX 3 5895#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G 0x04be 5896#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G_BASE_IDX 3 5897#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R 0x04bf 5898#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R_BASE_IDX 3 5899#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B 0x04c0 5900#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B_BASE_IDX 3 5901#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G 0x04c1 5902#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G_BASE_IDX 3 5903#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R 0x04c2 5904#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R_BASE_IDX 3 5905#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B 0x04c3 5906#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B_BASE_IDX 3 5907#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B 0x04c4 5908#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B_BASE_IDX 3 5909#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G 0x04c5 5910#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G_BASE_IDX 3 5911#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G 0x04c6 5912#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G_BASE_IDX 3 5913#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R 0x04c7 5914#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R_BASE_IDX 3 5915#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R 0x04c8 5916#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R_BASE_IDX 3 5917#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_B 0x04c9 5918#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_B_BASE_IDX 3 5919#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_G 0x04ca 5920#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_G_BASE_IDX 3 5921#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_R 0x04cb 5922#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_R_BASE_IDX 3 5923#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_0_1 0x04cc 5924#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_0_1_BASE_IDX 3 5925#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_2_3 0x04cd 5926#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_2_3_BASE_IDX 3 5927#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_4_5 0x04ce 5928#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_4_5_BASE_IDX 3 5929#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_6_7 0x04cf 5930#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_6_7_BASE_IDX 3 5931#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_8_9 0x04d0 5932#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_8_9_BASE_IDX 3 5933#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_10_11 0x04d1 5934#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_10_11_BASE_IDX 3 5935#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_12_13 0x04d2 5936#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_12_13_BASE_IDX 3 5937#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_14_15 0x04d3 5938#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_14_15_BASE_IDX 3 5939#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_16_17 0x04d4 5940#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_16_17_BASE_IDX 3 5941#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_18_19 0x04d5 5942#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_18_19_BASE_IDX 3 5943#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_20_21 0x04d6 5944#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_20_21_BASE_IDX 3 5945#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_22_23 0x04d7 5946#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_22_23_BASE_IDX 3 5947#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_24_25 0x04d8 5948#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_24_25_BASE_IDX 3 5949#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_26_27 0x04d9 5950#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_26_27_BASE_IDX 3 5951#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_28_29 0x04da 5952#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_28_29_BASE_IDX 3 5953#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_30_31 0x04db 5954#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_30_31_BASE_IDX 3 5955#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_32_33 0x04dc 5956#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_32_33_BASE_IDX 3 5957#define regMPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL 0x04dd 5958#define regMPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL_BASE_IDX 3 5959 5960 5961// addressBlock: dcn_dc_mpc_mpcc_mcm1_dispdec 5962// base address: 0x240 5963#define regMPCC_MCM1_MPCC_MCM_SHAPER_CONTROL 0x04e3 5964#define regMPCC_MCM1_MPCC_MCM_SHAPER_CONTROL_BASE_IDX 3 5965#define regMPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_R 0x04e4 5966#define regMPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_R_BASE_IDX 3 5967#define regMPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_G 0x04e5 5968#define regMPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_G_BASE_IDX 3 5969#define regMPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_B 0x04e6 5970#define regMPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_B_BASE_IDX 3 5971#define regMPCC_MCM1_MPCC_MCM_SHAPER_SCALE_R 0x04e7 5972#define regMPCC_MCM1_MPCC_MCM_SHAPER_SCALE_R_BASE_IDX 3 5973#define regMPCC_MCM1_MPCC_MCM_SHAPER_SCALE_G_B 0x04e8 5974#define regMPCC_MCM1_MPCC_MCM_SHAPER_SCALE_G_B_BASE_IDX 3 5975#define regMPCC_MCM1_MPCC_MCM_SHAPER_LUT_INDEX 0x04e9 5976#define regMPCC_MCM1_MPCC_MCM_SHAPER_LUT_INDEX_BASE_IDX 3 5977#define regMPCC_MCM1_MPCC_MCM_SHAPER_LUT_DATA 0x04ea 5978#define regMPCC_MCM1_MPCC_MCM_SHAPER_LUT_DATA_BASE_IDX 3 5979#define regMPCC_MCM1_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK 0x04eb 5980#define regMPCC_MCM1_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX 3 5981#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_B 0x04ec 5982#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_B_BASE_IDX 3 5983#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_G 0x04ed 5984#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_G_BASE_IDX 3 5985#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_R 0x04ee 5986#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_R_BASE_IDX 3 5987#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_B 0x04ef 5988#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_B_BASE_IDX 3 5989#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_G 0x04f0 5990#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_G_BASE_IDX 3 5991#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_R 0x04f1 5992#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_R_BASE_IDX 3 5993#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_0_1 0x04f2 5994#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_0_1_BASE_IDX 3 5995#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_2_3 0x04f3 5996#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_2_3_BASE_IDX 3 5997#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_4_5 0x04f4 5998#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_4_5_BASE_IDX 3 5999#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_6_7 0x04f5 6000#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_6_7_BASE_IDX 3 6001#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_8_9 0x04f6 6002#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_8_9_BASE_IDX 3 6003#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_10_11 0x04f7 6004#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_10_11_BASE_IDX 3 6005#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_12_13 0x04f8 6006#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_12_13_BASE_IDX 3 6007#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_14_15 0x04f9 6008#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_14_15_BASE_IDX 3 6009#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_16_17 0x04fa 6010#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_16_17_BASE_IDX 3 6011#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_18_19 0x04fb 6012#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_18_19_BASE_IDX 3 6013#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_20_21 0x04fc 6014#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_20_21_BASE_IDX 3 6015#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_22_23 0x04fd 6016#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_22_23_BASE_IDX 3 6017#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_24_25 0x04fe 6018#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_24_25_BASE_IDX 3 6019#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_26_27 0x04ff 6020#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_26_27_BASE_IDX 3 6021#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_28_29 0x0500 6022#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_28_29_BASE_IDX 3 6023#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_30_31 0x0501 6024#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_30_31_BASE_IDX 3 6025#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_32_33 0x0502 6026#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_32_33_BASE_IDX 3 6027#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_B 0x0503 6028#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_B_BASE_IDX 3 6029#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_G 0x0504 6030#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_G_BASE_IDX 3 6031#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_R 0x0505 6032#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_R_BASE_IDX 3 6033#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_B 0x0506 6034#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_B_BASE_IDX 3 6035#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_G 0x0507 6036#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_G_BASE_IDX 3 6037#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_R 0x0508 6038#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_R_BASE_IDX 3 6039#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_0_1 0x0509 6040#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_0_1_BASE_IDX 3 6041#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_2_3 0x050a 6042#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_2_3_BASE_IDX 3 6043#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_4_5 0x050b 6044#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_4_5_BASE_IDX 3 6045#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_6_7 0x050c 6046#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_6_7_BASE_IDX 3 6047#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_8_9 0x050d 6048#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_8_9_BASE_IDX 3 6049#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_10_11 0x050e 6050#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_10_11_BASE_IDX 3 6051#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_12_13 0x050f 6052#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_12_13_BASE_IDX 3 6053#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_14_15 0x0510 6054#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_14_15_BASE_IDX 3 6055#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_16_17 0x0511 6056#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_16_17_BASE_IDX 3 6057#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_18_19 0x0512 6058#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_18_19_BASE_IDX 3 6059#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_20_21 0x0513 6060#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_20_21_BASE_IDX 3 6061#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_22_23 0x0514 6062#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_22_23_BASE_IDX 3 6063#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_24_25 0x0515 6064#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_24_25_BASE_IDX 3 6065#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_26_27 0x0516 6066#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_26_27_BASE_IDX 3 6067#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_28_29 0x0517 6068#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_28_29_BASE_IDX 3 6069#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_30_31 0x0518 6070#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_30_31_BASE_IDX 3 6071#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_32_33 0x0519 6072#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_32_33_BASE_IDX 3 6073#define regMPCC_MCM1_MPCC_MCM_3DLUT_MODE 0x051a 6074#define regMPCC_MCM1_MPCC_MCM_3DLUT_MODE_BASE_IDX 3 6075#define regMPCC_MCM1_MPCC_MCM_3DLUT_INDEX 0x051b 6076#define regMPCC_MCM1_MPCC_MCM_3DLUT_INDEX_BASE_IDX 3 6077#define regMPCC_MCM1_MPCC_MCM_3DLUT_DATA 0x051c 6078#define regMPCC_MCM1_MPCC_MCM_3DLUT_DATA_BASE_IDX 3 6079#define regMPCC_MCM1_MPCC_MCM_3DLUT_DATA_30BIT 0x051d 6080#define regMPCC_MCM1_MPCC_MCM_3DLUT_DATA_30BIT_BASE_IDX 3 6081#define regMPCC_MCM1_MPCC_MCM_3DLUT_READ_WRITE_CONTROL 0x051e 6082#define regMPCC_MCM1_MPCC_MCM_3DLUT_READ_WRITE_CONTROL_BASE_IDX 3 6083#define regMPCC_MCM1_MPCC_MCM_3DLUT_OUT_NORM_FACTOR 0x051f 6084#define regMPCC_MCM1_MPCC_MCM_3DLUT_OUT_NORM_FACTOR_BASE_IDX 3 6085#define regMPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_R 0x0520 6086#define regMPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_R_BASE_IDX 3 6087#define regMPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_G 0x0521 6088#define regMPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_G_BASE_IDX 3 6089#define regMPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_B 0x0522 6090#define regMPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_B_BASE_IDX 3 6091#define regMPCC_MCM1_MPCC_MCM_1DLUT_CONTROL 0x0523 6092#define regMPCC_MCM1_MPCC_MCM_1DLUT_CONTROL_BASE_IDX 3 6093#define regMPCC_MCM1_MPCC_MCM_1DLUT_LUT_INDEX 0x0524 6094#define regMPCC_MCM1_MPCC_MCM_1DLUT_LUT_INDEX_BASE_IDX 3 6095#define regMPCC_MCM1_MPCC_MCM_1DLUT_LUT_DATA 0x0525 6096#define regMPCC_MCM1_MPCC_MCM_1DLUT_LUT_DATA_BASE_IDX 3 6097#define regMPCC_MCM1_MPCC_MCM_1DLUT_LUT_CONTROL 0x0526 6098#define regMPCC_MCM1_MPCC_MCM_1DLUT_LUT_CONTROL_BASE_IDX 3 6099#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_B 0x0527 6100#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_B_BASE_IDX 3 6101#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_G 0x0528 6102#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_G_BASE_IDX 3 6103#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_R 0x0529 6104#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_R_BASE_IDX 3 6105#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B 0x052a 6106#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B_BASE_IDX 3 6107#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G 0x052b 6108#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G_BASE_IDX 3 6109#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R 0x052c 6110#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R_BASE_IDX 3 6111#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B 0x052d 6112#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B_BASE_IDX 3 6113#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G 0x052e 6114#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G_BASE_IDX 3 6115#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R 0x052f 6116#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R_BASE_IDX 3 6117#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B 0x0530 6118#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B_BASE_IDX 3 6119#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B 0x0531 6120#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B_BASE_IDX 3 6121#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G 0x0532 6122#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G_BASE_IDX 3 6123#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G 0x0533 6124#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G_BASE_IDX 3 6125#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R 0x0534 6126#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R_BASE_IDX 3 6127#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R 0x0535 6128#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R_BASE_IDX 3 6129#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_B 0x0536 6130#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_B_BASE_IDX 3 6131#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_G 0x0537 6132#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_G_BASE_IDX 3 6133#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_R 0x0538 6134#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_R_BASE_IDX 3 6135#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_0_1 0x0539 6136#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_0_1_BASE_IDX 3 6137#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_2_3 0x053a 6138#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_2_3_BASE_IDX 3 6139#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_4_5 0x053b 6140#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_4_5_BASE_IDX 3 6141#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_6_7 0x053c 6142#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_6_7_BASE_IDX 3 6143#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_8_9 0x053d 6144#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_8_9_BASE_IDX 3 6145#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_10_11 0x053e 6146#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_10_11_BASE_IDX 3 6147#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_12_13 0x053f 6148#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_12_13_BASE_IDX 3 6149#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_14_15 0x0540 6150#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_14_15_BASE_IDX 3 6151#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_16_17 0x0541 6152#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_16_17_BASE_IDX 3 6153#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_18_19 0x0542 6154#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_18_19_BASE_IDX 3 6155#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_20_21 0x0543 6156#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_20_21_BASE_IDX 3 6157#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_22_23 0x0544 6158#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_22_23_BASE_IDX 3 6159#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_24_25 0x0545 6160#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_24_25_BASE_IDX 3 6161#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_26_27 0x0546 6162#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_26_27_BASE_IDX 3 6163#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_28_29 0x0547 6164#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_28_29_BASE_IDX 3 6165#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_30_31 0x0548 6166#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_30_31_BASE_IDX 3 6167#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_32_33 0x0549 6168#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_32_33_BASE_IDX 3 6169#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_B 0x054a 6170#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_B_BASE_IDX 3 6171#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_G 0x054b 6172#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_G_BASE_IDX 3 6173#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_R 0x054c 6174#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_R_BASE_IDX 3 6175#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B 0x054d 6176#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B_BASE_IDX 3 6177#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G 0x054e 6178#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G_BASE_IDX 3 6179#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R 0x054f 6180#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R_BASE_IDX 3 6181#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B 0x0550 6182#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B_BASE_IDX 3 6183#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G 0x0551 6184#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G_BASE_IDX 3 6185#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R 0x0552 6186#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R_BASE_IDX 3 6187#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B 0x0553 6188#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B_BASE_IDX 3 6189#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B 0x0554 6190#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B_BASE_IDX 3 6191#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G 0x0555 6192#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G_BASE_IDX 3 6193#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G 0x0556 6194#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G_BASE_IDX 3 6195#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R 0x0557 6196#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R_BASE_IDX 3 6197#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R 0x0558 6198#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R_BASE_IDX 3 6199#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_B 0x0559 6200#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_B_BASE_IDX 3 6201#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_G 0x055a 6202#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_G_BASE_IDX 3 6203#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_R 0x055b 6204#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_R_BASE_IDX 3 6205#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_0_1 0x055c 6206#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_0_1_BASE_IDX 3 6207#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_2_3 0x055d 6208#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_2_3_BASE_IDX 3 6209#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_4_5 0x055e 6210#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_4_5_BASE_IDX 3 6211#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_6_7 0x055f 6212#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_6_7_BASE_IDX 3 6213#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_8_9 0x0560 6214#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_8_9_BASE_IDX 3 6215#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_10_11 0x0561 6216#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_10_11_BASE_IDX 3 6217#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_12_13 0x0562 6218#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_12_13_BASE_IDX 3 6219#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_14_15 0x0563 6220#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_14_15_BASE_IDX 3 6221#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_16_17 0x0564 6222#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_16_17_BASE_IDX 3 6223#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_18_19 0x0565 6224#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_18_19_BASE_IDX 3 6225#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_20_21 0x0566 6226#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_20_21_BASE_IDX 3 6227#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_22_23 0x0567 6228#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_22_23_BASE_IDX 3 6229#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_24_25 0x0568 6230#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_24_25_BASE_IDX 3 6231#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_26_27 0x0569 6232#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_26_27_BASE_IDX 3 6233#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_28_29 0x056a 6234#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_28_29_BASE_IDX 3 6235#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_30_31 0x056b 6236#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_30_31_BASE_IDX 3 6237#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_32_33 0x056c 6238#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_32_33_BASE_IDX 3 6239#define regMPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL 0x056d 6240#define regMPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL_BASE_IDX 3 6241 6242 6243// addressBlock: dcn_dc_mpc_mpcc_mcm2_dispdec 6244// base address: 0x480 6245#define regMPCC_MCM2_MPCC_MCM_SHAPER_CONTROL 0x0573 6246#define regMPCC_MCM2_MPCC_MCM_SHAPER_CONTROL_BASE_IDX 3 6247#define regMPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_R 0x0574 6248#define regMPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_R_BASE_IDX 3 6249#define regMPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_G 0x0575 6250#define regMPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_G_BASE_IDX 3 6251#define regMPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_B 0x0576 6252#define regMPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_B_BASE_IDX 3 6253#define regMPCC_MCM2_MPCC_MCM_SHAPER_SCALE_R 0x0577 6254#define regMPCC_MCM2_MPCC_MCM_SHAPER_SCALE_R_BASE_IDX 3 6255#define regMPCC_MCM2_MPCC_MCM_SHAPER_SCALE_G_B 0x0578 6256#define regMPCC_MCM2_MPCC_MCM_SHAPER_SCALE_G_B_BASE_IDX 3 6257#define regMPCC_MCM2_MPCC_MCM_SHAPER_LUT_INDEX 0x0579 6258#define regMPCC_MCM2_MPCC_MCM_SHAPER_LUT_INDEX_BASE_IDX 3 6259#define regMPCC_MCM2_MPCC_MCM_SHAPER_LUT_DATA 0x057a 6260#define regMPCC_MCM2_MPCC_MCM_SHAPER_LUT_DATA_BASE_IDX 3 6261#define regMPCC_MCM2_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK 0x057b 6262#define regMPCC_MCM2_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX 3 6263#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_B 0x057c 6264#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_B_BASE_IDX 3 6265#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_G 0x057d 6266#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_G_BASE_IDX 3 6267#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_R 0x057e 6268#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_R_BASE_IDX 3 6269#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_B 0x057f 6270#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_B_BASE_IDX 3 6271#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_G 0x0580 6272#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_G_BASE_IDX 3 6273#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_R 0x0581 6274#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_R_BASE_IDX 3 6275#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_0_1 0x0582 6276#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_0_1_BASE_IDX 3 6277#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_2_3 0x0583 6278#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_2_3_BASE_IDX 3 6279#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_4_5 0x0584 6280#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_4_5_BASE_IDX 3 6281#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_6_7 0x0585 6282#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_6_7_BASE_IDX 3 6283#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_8_9 0x0586 6284#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_8_9_BASE_IDX 3 6285#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_10_11 0x0587 6286#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_10_11_BASE_IDX 3 6287#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_12_13 0x0588 6288#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_12_13_BASE_IDX 3 6289#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_14_15 0x0589 6290#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_14_15_BASE_IDX 3 6291#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_16_17 0x058a 6292#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_16_17_BASE_IDX 3 6293#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_18_19 0x058b 6294#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_18_19_BASE_IDX 3 6295#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_20_21 0x058c 6296#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_20_21_BASE_IDX 3 6297#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_22_23 0x058d 6298#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_22_23_BASE_IDX 3 6299#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_24_25 0x058e 6300#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_24_25_BASE_IDX 3 6301#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_26_27 0x058f 6302#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_26_27_BASE_IDX 3 6303#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_28_29 0x0590 6304#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_28_29_BASE_IDX 3 6305#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_30_31 0x0591 6306#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_30_31_BASE_IDX 3 6307#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_32_33 0x0592 6308#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_32_33_BASE_IDX 3 6309#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_B 0x0593 6310#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_B_BASE_IDX 3 6311#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_G 0x0594 6312#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_G_BASE_IDX 3 6313#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_R 0x0595 6314#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_R_BASE_IDX 3 6315#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_B 0x0596 6316#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_B_BASE_IDX 3 6317#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_G 0x0597 6318#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_G_BASE_IDX 3 6319#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_R 0x0598 6320#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_R_BASE_IDX 3 6321#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_0_1 0x0599 6322#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_0_1_BASE_IDX 3 6323#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_2_3 0x059a 6324#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_2_3_BASE_IDX 3 6325#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_4_5 0x059b 6326#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_4_5_BASE_IDX 3 6327#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_6_7 0x059c 6328#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_6_7_BASE_IDX 3 6329#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_8_9 0x059d 6330#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_8_9_BASE_IDX 3 6331#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_10_11 0x059e 6332#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_10_11_BASE_IDX 3 6333#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_12_13 0x059f 6334#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_12_13_BASE_IDX 3 6335#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_14_15 0x05a0 6336#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_14_15_BASE_IDX 3 6337#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_16_17 0x05a1 6338#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_16_17_BASE_IDX 3 6339#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_18_19 0x05a2 6340#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_18_19_BASE_IDX 3 6341#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_20_21 0x05a3 6342#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_20_21_BASE_IDX 3 6343#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_22_23 0x05a4 6344#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_22_23_BASE_IDX 3 6345#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_24_25 0x05a5 6346#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_24_25_BASE_IDX 3 6347#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_26_27 0x05a6 6348#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_26_27_BASE_IDX 3 6349#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_28_29 0x05a7 6350#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_28_29_BASE_IDX 3 6351#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_30_31 0x05a8 6352#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_30_31_BASE_IDX 3 6353#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_32_33 0x05a9 6354#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_32_33_BASE_IDX 3 6355#define regMPCC_MCM2_MPCC_MCM_3DLUT_MODE 0x05aa 6356#define regMPCC_MCM2_MPCC_MCM_3DLUT_MODE_BASE_IDX 3 6357#define regMPCC_MCM2_MPCC_MCM_3DLUT_INDEX 0x05ab 6358#define regMPCC_MCM2_MPCC_MCM_3DLUT_INDEX_BASE_IDX 3 6359#define regMPCC_MCM2_MPCC_MCM_3DLUT_DATA 0x05ac 6360#define regMPCC_MCM2_MPCC_MCM_3DLUT_DATA_BASE_IDX 3 6361#define regMPCC_MCM2_MPCC_MCM_3DLUT_DATA_30BIT 0x05ad 6362#define regMPCC_MCM2_MPCC_MCM_3DLUT_DATA_30BIT_BASE_IDX 3 6363#define regMPCC_MCM2_MPCC_MCM_3DLUT_READ_WRITE_CONTROL 0x05ae 6364#define regMPCC_MCM2_MPCC_MCM_3DLUT_READ_WRITE_CONTROL_BASE_IDX 3 6365#define regMPCC_MCM2_MPCC_MCM_3DLUT_OUT_NORM_FACTOR 0x05af 6366#define regMPCC_MCM2_MPCC_MCM_3DLUT_OUT_NORM_FACTOR_BASE_IDX 3 6367#define regMPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_R 0x05b0 6368#define regMPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_R_BASE_IDX 3 6369#define regMPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_G 0x05b1 6370#define regMPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_G_BASE_IDX 3 6371#define regMPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_B 0x05b2 6372#define regMPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_B_BASE_IDX 3 6373#define regMPCC_MCM2_MPCC_MCM_1DLUT_CONTROL 0x05b3 6374#define regMPCC_MCM2_MPCC_MCM_1DLUT_CONTROL_BASE_IDX 3 6375#define regMPCC_MCM2_MPCC_MCM_1DLUT_LUT_INDEX 0x05b4 6376#define regMPCC_MCM2_MPCC_MCM_1DLUT_LUT_INDEX_BASE_IDX 3 6377#define regMPCC_MCM2_MPCC_MCM_1DLUT_LUT_DATA 0x05b5 6378#define regMPCC_MCM2_MPCC_MCM_1DLUT_LUT_DATA_BASE_IDX 3 6379#define regMPCC_MCM2_MPCC_MCM_1DLUT_LUT_CONTROL 0x05b6 6380#define regMPCC_MCM2_MPCC_MCM_1DLUT_LUT_CONTROL_BASE_IDX 3 6381#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_B 0x05b7 6382#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_B_BASE_IDX 3 6383#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_G 0x05b8 6384#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_G_BASE_IDX 3 6385#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_R 0x05b9 6386#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_R_BASE_IDX 3 6387#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B 0x05ba 6388#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B_BASE_IDX 3 6389#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G 0x05bb 6390#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G_BASE_IDX 3 6391#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R 0x05bc 6392#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R_BASE_IDX 3 6393#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B 0x05bd 6394#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B_BASE_IDX 3 6395#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G 0x05be 6396#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G_BASE_IDX 3 6397#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R 0x05bf 6398#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R_BASE_IDX 3 6399#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B 0x05c0 6400#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B_BASE_IDX 3 6401#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B 0x05c1 6402#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B_BASE_IDX 3 6403#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G 0x05c2 6404#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G_BASE_IDX 3 6405#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G 0x05c3 6406#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G_BASE_IDX 3 6407#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R 0x05c4 6408#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R_BASE_IDX 3 6409#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R 0x05c5 6410#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R_BASE_IDX 3 6411#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_B 0x05c6 6412#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_B_BASE_IDX 3 6413#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_G 0x05c7 6414#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_G_BASE_IDX 3 6415#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_R 0x05c8 6416#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_R_BASE_IDX 3 6417#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_0_1 0x05c9 6418#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_0_1_BASE_IDX 3 6419#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_2_3 0x05ca 6420#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_2_3_BASE_IDX 3 6421#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_4_5 0x05cb 6422#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_4_5_BASE_IDX 3 6423#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_6_7 0x05cc 6424#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_6_7_BASE_IDX 3 6425#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_8_9 0x05cd 6426#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_8_9_BASE_IDX 3 6427#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_10_11 0x05ce 6428#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_10_11_BASE_IDX 3 6429#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_12_13 0x05cf 6430#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_12_13_BASE_IDX 3 6431#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_14_15 0x05d0 6432#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_14_15_BASE_IDX 3 6433#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_16_17 0x05d1 6434#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_16_17_BASE_IDX 3 6435#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_18_19 0x05d2 6436#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_18_19_BASE_IDX 3 6437#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_20_21 0x05d3 6438#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_20_21_BASE_IDX 3 6439#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_22_23 0x05d4 6440#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_22_23_BASE_IDX 3 6441#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_24_25 0x05d5 6442#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_24_25_BASE_IDX 3 6443#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_26_27 0x05d6 6444#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_26_27_BASE_IDX 3 6445#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_28_29 0x05d7 6446#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_28_29_BASE_IDX 3 6447#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_30_31 0x05d8 6448#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_30_31_BASE_IDX 3 6449#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_32_33 0x05d9 6450#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_32_33_BASE_IDX 3 6451#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_B 0x05da 6452#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_B_BASE_IDX 3 6453#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_G 0x05db 6454#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_G_BASE_IDX 3 6455#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_R 0x05dc 6456#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_R_BASE_IDX 3 6457#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B 0x05dd 6458#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B_BASE_IDX 3 6459#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G 0x05de 6460#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G_BASE_IDX 3 6461#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R 0x05df 6462#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R_BASE_IDX 3 6463#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B 0x05e0 6464#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B_BASE_IDX 3 6465#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G 0x05e1 6466#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G_BASE_IDX 3 6467#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R 0x05e2 6468#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R_BASE_IDX 3 6469#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B 0x05e3 6470#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B_BASE_IDX 3 6471#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B 0x05e4 6472#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B_BASE_IDX 3 6473#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G 0x05e5 6474#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G_BASE_IDX 3 6475#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G 0x05e6 6476#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G_BASE_IDX 3 6477#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R 0x05e7 6478#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R_BASE_IDX 3 6479#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R 0x05e8 6480#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R_BASE_IDX 3 6481#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_B 0x05e9 6482#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_B_BASE_IDX 3 6483#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_G 0x05ea 6484#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_G_BASE_IDX 3 6485#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_R 0x05eb 6486#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_R_BASE_IDX 3 6487#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_0_1 0x05ec 6488#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_0_1_BASE_IDX 3 6489#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_2_3 0x05ed 6490#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_2_3_BASE_IDX 3 6491#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_4_5 0x05ee 6492#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_4_5_BASE_IDX 3 6493#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_6_7 0x05ef 6494#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_6_7_BASE_IDX 3 6495#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_8_9 0x05f0 6496#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_8_9_BASE_IDX 3 6497#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_10_11 0x05f1 6498#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_10_11_BASE_IDX 3 6499#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_12_13 0x05f2 6500#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_12_13_BASE_IDX 3 6501#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_14_15 0x05f3 6502#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_14_15_BASE_IDX 3 6503#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_16_17 0x05f4 6504#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_16_17_BASE_IDX 3 6505#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_18_19 0x05f5 6506#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_18_19_BASE_IDX 3 6507#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_20_21 0x05f6 6508#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_20_21_BASE_IDX 3 6509#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_22_23 0x05f7 6510#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_22_23_BASE_IDX 3 6511#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_24_25 0x05f8 6512#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_24_25_BASE_IDX 3 6513#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_26_27 0x05f9 6514#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_26_27_BASE_IDX 3 6515#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_28_29 0x05fa 6516#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_28_29_BASE_IDX 3 6517#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_30_31 0x05fb 6518#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_30_31_BASE_IDX 3 6519#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_32_33 0x05fc 6520#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_32_33_BASE_IDX 3 6521#define regMPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL 0x05fd 6522#define regMPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL_BASE_IDX 3 6523 6524 6525// addressBlock: dcn_dc_mpc_mpcc_mcm3_dispdec 6526// base address: 0x6c0 6527#define regMPCC_MCM3_MPCC_MCM_SHAPER_CONTROL 0x0603 6528#define regMPCC_MCM3_MPCC_MCM_SHAPER_CONTROL_BASE_IDX 3 6529#define regMPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_R 0x0604 6530#define regMPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_R_BASE_IDX 3 6531#define regMPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_G 0x0605 6532#define regMPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_G_BASE_IDX 3 6533#define regMPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_B 0x0606 6534#define regMPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_B_BASE_IDX 3 6535#define regMPCC_MCM3_MPCC_MCM_SHAPER_SCALE_R 0x0607 6536#define regMPCC_MCM3_MPCC_MCM_SHAPER_SCALE_R_BASE_IDX 3 6537#define regMPCC_MCM3_MPCC_MCM_SHAPER_SCALE_G_B 0x0608 6538#define regMPCC_MCM3_MPCC_MCM_SHAPER_SCALE_G_B_BASE_IDX 3 6539#define regMPCC_MCM3_MPCC_MCM_SHAPER_LUT_INDEX 0x0609 6540#define regMPCC_MCM3_MPCC_MCM_SHAPER_LUT_INDEX_BASE_IDX 3 6541#define regMPCC_MCM3_MPCC_MCM_SHAPER_LUT_DATA 0x060a 6542#define regMPCC_MCM3_MPCC_MCM_SHAPER_LUT_DATA_BASE_IDX 3 6543#define regMPCC_MCM3_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK 0x060b 6544#define regMPCC_MCM3_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX 3 6545#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_B 0x060c 6546#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_B_BASE_IDX 3 6547#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_G 0x060d 6548#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_G_BASE_IDX 3 6549#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_R 0x060e 6550#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_R_BASE_IDX 3 6551#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_B 0x060f 6552#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_B_BASE_IDX 3 6553#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_G 0x0610 6554#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_G_BASE_IDX 3 6555#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_R 0x0611 6556#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_R_BASE_IDX 3 6557#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_0_1 0x0612 6558#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_0_1_BASE_IDX 3 6559#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_2_3 0x0613 6560#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_2_3_BASE_IDX 3 6561#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_4_5 0x0614 6562#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_4_5_BASE_IDX 3 6563#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_6_7 0x0615 6564#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_6_7_BASE_IDX 3 6565#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_8_9 0x0616 6566#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_8_9_BASE_IDX 3 6567#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_10_11 0x0617 6568#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_10_11_BASE_IDX 3 6569#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_12_13 0x0618 6570#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_12_13_BASE_IDX 3 6571#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_14_15 0x0619 6572#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_14_15_BASE_IDX 3 6573#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_16_17 0x061a 6574#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_16_17_BASE_IDX 3 6575#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_18_19 0x061b 6576#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_18_19_BASE_IDX 3 6577#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_20_21 0x061c 6578#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_20_21_BASE_IDX 3 6579#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_22_23 0x061d 6580#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_22_23_BASE_IDX 3 6581#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_24_25 0x061e 6582#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_24_25_BASE_IDX 3 6583#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_26_27 0x061f 6584#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_26_27_BASE_IDX 3 6585#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_28_29 0x0620 6586#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_28_29_BASE_IDX 3 6587#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_30_31 0x0621 6588#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_30_31_BASE_IDX 3 6589#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_32_33 0x0622 6590#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_32_33_BASE_IDX 3 6591#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_B 0x0623 6592#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_B_BASE_IDX 3 6593#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_G 0x0624 6594#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_G_BASE_IDX 3 6595#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_R 0x0625 6596#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_R_BASE_IDX 3 6597#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_B 0x0626 6598#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_B_BASE_IDX 3 6599#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_G 0x0627 6600#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_G_BASE_IDX 3 6601#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_R 0x0628 6602#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_R_BASE_IDX 3 6603#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_0_1 0x0629 6604#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_0_1_BASE_IDX 3 6605#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_2_3 0x062a 6606#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_2_3_BASE_IDX 3 6607#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_4_5 0x062b 6608#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_4_5_BASE_IDX 3 6609#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_6_7 0x062c 6610#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_6_7_BASE_IDX 3 6611#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_8_9 0x062d 6612#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_8_9_BASE_IDX 3 6613#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_10_11 0x062e 6614#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_10_11_BASE_IDX 3 6615#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_12_13 0x062f 6616#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_12_13_BASE_IDX 3 6617#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_14_15 0x0630 6618#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_14_15_BASE_IDX 3 6619#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_16_17 0x0631 6620#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_16_17_BASE_IDX 3 6621#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_18_19 0x0632 6622#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_18_19_BASE_IDX 3 6623#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_20_21 0x0633 6624#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_20_21_BASE_IDX 3 6625#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_22_23 0x0634 6626#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_22_23_BASE_IDX 3 6627#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_24_25 0x0635 6628#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_24_25_BASE_IDX 3 6629#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_26_27 0x0636 6630#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_26_27_BASE_IDX 3 6631#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_28_29 0x0637 6632#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_28_29_BASE_IDX 3 6633#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_30_31 0x0638 6634#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_30_31_BASE_IDX 3 6635#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_32_33 0x0639 6636#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_32_33_BASE_IDX 3 6637#define regMPCC_MCM3_MPCC_MCM_3DLUT_MODE 0x063a 6638#define regMPCC_MCM3_MPCC_MCM_3DLUT_MODE_BASE_IDX 3 6639#define regMPCC_MCM3_MPCC_MCM_3DLUT_INDEX 0x063b 6640#define regMPCC_MCM3_MPCC_MCM_3DLUT_INDEX_BASE_IDX 3 6641#define regMPCC_MCM3_MPCC_MCM_3DLUT_DATA 0x063c 6642#define regMPCC_MCM3_MPCC_MCM_3DLUT_DATA_BASE_IDX 3 6643#define regMPCC_MCM3_MPCC_MCM_3DLUT_DATA_30BIT 0x063d 6644#define regMPCC_MCM3_MPCC_MCM_3DLUT_DATA_30BIT_BASE_IDX 3 6645#define regMPCC_MCM3_MPCC_MCM_3DLUT_READ_WRITE_CONTROL 0x063e 6646#define regMPCC_MCM3_MPCC_MCM_3DLUT_READ_WRITE_CONTROL_BASE_IDX 3 6647#define regMPCC_MCM3_MPCC_MCM_3DLUT_OUT_NORM_FACTOR 0x063f 6648#define regMPCC_MCM3_MPCC_MCM_3DLUT_OUT_NORM_FACTOR_BASE_IDX 3 6649#define regMPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_R 0x0640 6650#define regMPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_R_BASE_IDX 3 6651#define regMPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_G 0x0641 6652#define regMPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_G_BASE_IDX 3 6653#define regMPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_B 0x0642 6654#define regMPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_B_BASE_IDX 3 6655#define regMPCC_MCM3_MPCC_MCM_1DLUT_CONTROL 0x0643 6656#define regMPCC_MCM3_MPCC_MCM_1DLUT_CONTROL_BASE_IDX 3 6657#define regMPCC_MCM3_MPCC_MCM_1DLUT_LUT_INDEX 0x0644 6658#define regMPCC_MCM3_MPCC_MCM_1DLUT_LUT_INDEX_BASE_IDX 3 6659#define regMPCC_MCM3_MPCC_MCM_1DLUT_LUT_DATA 0x0645 6660#define regMPCC_MCM3_MPCC_MCM_1DLUT_LUT_DATA_BASE_IDX 3 6661#define regMPCC_MCM3_MPCC_MCM_1DLUT_LUT_CONTROL 0x0646 6662#define regMPCC_MCM3_MPCC_MCM_1DLUT_LUT_CONTROL_BASE_IDX 3 6663#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_B 0x0647 6664#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_B_BASE_IDX 3 6665#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_G 0x0648 6666#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_G_BASE_IDX 3 6667#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_R 0x0649 6668#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_R_BASE_IDX 3 6669#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B 0x064a 6670#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B_BASE_IDX 3 6671#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G 0x064b 6672#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G_BASE_IDX 3 6673#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R 0x064c 6674#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R_BASE_IDX 3 6675#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B 0x064d 6676#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B_BASE_IDX 3 6677#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G 0x064e 6678#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G_BASE_IDX 3 6679#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R 0x064f 6680#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R_BASE_IDX 3 6681#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B 0x0650 6682#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B_BASE_IDX 3 6683#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B 0x0651 6684#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B_BASE_IDX 3 6685#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G 0x0652 6686#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G_BASE_IDX 3 6687#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G 0x0653 6688#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G_BASE_IDX 3 6689#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R 0x0654 6690#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R_BASE_IDX 3 6691#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R 0x0655 6692#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R_BASE_IDX 3 6693#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_B 0x0656 6694#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_B_BASE_IDX 3 6695#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_G 0x0657 6696#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_G_BASE_IDX 3 6697#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_R 0x0658 6698#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_R_BASE_IDX 3 6699#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_0_1 0x0659 6700#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_0_1_BASE_IDX 3 6701#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_2_3 0x065a 6702#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_2_3_BASE_IDX 3 6703#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_4_5 0x065b 6704#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_4_5_BASE_IDX 3 6705#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_6_7 0x065c 6706#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_6_7_BASE_IDX 3 6707#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_8_9 0x065d 6708#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_8_9_BASE_IDX 3 6709#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_10_11 0x065e 6710#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_10_11_BASE_IDX 3 6711#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_12_13 0x065f 6712#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_12_13_BASE_IDX 3 6713#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_14_15 0x0660 6714#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_14_15_BASE_IDX 3 6715#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_16_17 0x0661 6716#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_16_17_BASE_IDX 3 6717#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_18_19 0x0662 6718#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_18_19_BASE_IDX 3 6719#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_20_21 0x0663 6720#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_20_21_BASE_IDX 3 6721#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_22_23 0x0664 6722#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_22_23_BASE_IDX 3 6723#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_24_25 0x0665 6724#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_24_25_BASE_IDX 3 6725#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_26_27 0x0666 6726#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_26_27_BASE_IDX 3 6727#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_28_29 0x0667 6728#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_28_29_BASE_IDX 3 6729#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_30_31 0x0668 6730#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_30_31_BASE_IDX 3 6731#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_32_33 0x0669 6732#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_32_33_BASE_IDX 3 6733#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_B 0x066a 6734#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_B_BASE_IDX 3 6735#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_G 0x066b 6736#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_G_BASE_IDX 3 6737#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_R 0x066c 6738#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_R_BASE_IDX 3 6739#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B 0x066d 6740#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B_BASE_IDX 3 6741#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G 0x066e 6742#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G_BASE_IDX 3 6743#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R 0x066f 6744#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R_BASE_IDX 3 6745#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B 0x0670 6746#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B_BASE_IDX 3 6747#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G 0x0671 6748#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G_BASE_IDX 3 6749#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R 0x0672 6750#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R_BASE_IDX 3 6751#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B 0x0673 6752#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B_BASE_IDX 3 6753#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B 0x0674 6754#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B_BASE_IDX 3 6755#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G 0x0675 6756#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G_BASE_IDX 3 6757#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G 0x0676 6758#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G_BASE_IDX 3 6759#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R 0x0677 6760#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R_BASE_IDX 3 6761#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R 0x0678 6762#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R_BASE_IDX 3 6763#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_B 0x0679 6764#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_B_BASE_IDX 3 6765#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_G 0x067a 6766#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_G_BASE_IDX 3 6767#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_R 0x067b 6768#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_R_BASE_IDX 3 6769#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_0_1 0x067c 6770#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_0_1_BASE_IDX 3 6771#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_2_3 0x067d 6772#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_2_3_BASE_IDX 3 6773#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_4_5 0x067e 6774#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_4_5_BASE_IDX 3 6775#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_6_7 0x067f 6776#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_6_7_BASE_IDX 3 6777#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_8_9 0x0680 6778#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_8_9_BASE_IDX 3 6779#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_10_11 0x0681 6780#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_10_11_BASE_IDX 3 6781#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_12_13 0x0682 6782#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_12_13_BASE_IDX 3 6783#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_14_15 0x0683 6784#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_14_15_BASE_IDX 3 6785#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_16_17 0x0684 6786#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_16_17_BASE_IDX 3 6787#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_18_19 0x0685 6788#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_18_19_BASE_IDX 3 6789#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_20_21 0x0686 6790#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_20_21_BASE_IDX 3 6791#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_22_23 0x0687 6792#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_22_23_BASE_IDX 3 6793#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_24_25 0x0688 6794#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_24_25_BASE_IDX 3 6795#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_26_27 0x0689 6796#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_26_27_BASE_IDX 3 6797#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_28_29 0x068a 6798#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_28_29_BASE_IDX 3 6799#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_30_31 0x068b 6800#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_30_31_BASE_IDX 3 6801#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_32_33 0x068c 6802#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_32_33_BASE_IDX 3 6803#define regMPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL 0x068d 6804#define regMPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL_BASE_IDX 3 6805 6806 6807// addressBlock: dcn_dc_mpc_mpc_ocsc_dispdec 6808// base address: 0x0 6809#define regMPC_OUT0_MUX 0x03d8 6810#define regMPC_OUT0_MUX_BASE_IDX 3 6811#define regMPC_OUT0_DENORM_CONTROL 0x03d9 6812#define regMPC_OUT0_DENORM_CONTROL_BASE_IDX 3 6813#define regMPC_OUT0_DENORM_CLAMP_G_Y 0x03da 6814#define regMPC_OUT0_DENORM_CLAMP_G_Y_BASE_IDX 3 6815#define regMPC_OUT0_DENORM_CLAMP_B_CB 0x03db 6816#define regMPC_OUT0_DENORM_CLAMP_B_CB_BASE_IDX 3 6817#define regMPC_OUT1_MUX 0x03dc 6818#define regMPC_OUT1_MUX_BASE_IDX 3 6819#define regMPC_OUT1_DENORM_CONTROL 0x03dd 6820#define regMPC_OUT1_DENORM_CONTROL_BASE_IDX 3 6821#define regMPC_OUT1_DENORM_CLAMP_G_Y 0x03de 6822#define regMPC_OUT1_DENORM_CLAMP_G_Y_BASE_IDX 3 6823#define regMPC_OUT1_DENORM_CLAMP_B_CB 0x03df 6824#define regMPC_OUT1_DENORM_CLAMP_B_CB_BASE_IDX 3 6825#define regMPC_OUT2_MUX 0x03e0 6826#define regMPC_OUT2_MUX_BASE_IDX 3 6827#define regMPC_OUT2_DENORM_CONTROL 0x03e1 6828#define regMPC_OUT2_DENORM_CONTROL_BASE_IDX 3 6829#define regMPC_OUT2_DENORM_CLAMP_G_Y 0x03e2 6830#define regMPC_OUT2_DENORM_CLAMP_G_Y_BASE_IDX 3 6831#define regMPC_OUT2_DENORM_CLAMP_B_CB 0x03e3 6832#define regMPC_OUT2_DENORM_CLAMP_B_CB_BASE_IDX 3 6833#define regMPC_OUT3_MUX 0x03e4 6834#define regMPC_OUT3_MUX_BASE_IDX 3 6835#define regMPC_OUT3_DENORM_CONTROL 0x03e5 6836#define regMPC_OUT3_DENORM_CONTROL_BASE_IDX 3 6837#define regMPC_OUT3_DENORM_CLAMP_G_Y 0x03e6 6838#define regMPC_OUT3_DENORM_CLAMP_G_Y_BASE_IDX 3 6839#define regMPC_OUT3_DENORM_CLAMP_B_CB 0x03e7 6840#define regMPC_OUT3_DENORM_CLAMP_B_CB_BASE_IDX 3 6841#define regMPC_OUT_CSC_COEF_FORMAT 0x03f0 6842#define regMPC_OUT_CSC_COEF_FORMAT_BASE_IDX 3 6843#define regMPC_OUT0_CSC_MODE 0x03f1 6844#define regMPC_OUT0_CSC_MODE_BASE_IDX 3 6845#define regMPC_OUT0_CSC_C11_C12_A 0x03f2 6846#define regMPC_OUT0_CSC_C11_C12_A_BASE_IDX 3 6847#define regMPC_OUT0_CSC_C13_C14_A 0x03f3 6848#define regMPC_OUT0_CSC_C13_C14_A_BASE_IDX 3 6849#define regMPC_OUT0_CSC_C21_C22_A 0x03f4 6850#define regMPC_OUT0_CSC_C21_C22_A_BASE_IDX 3 6851#define regMPC_OUT0_CSC_C23_C24_A 0x03f5 6852#define regMPC_OUT0_CSC_C23_C24_A_BASE_IDX 3 6853#define regMPC_OUT0_CSC_C31_C32_A 0x03f6 6854#define regMPC_OUT0_CSC_C31_C32_A_BASE_IDX 3 6855#define regMPC_OUT0_CSC_C33_C34_A 0x03f7 6856#define regMPC_OUT0_CSC_C33_C34_A_BASE_IDX 3 6857#define regMPC_OUT0_CSC_C11_C12_B 0x03f8 6858#define regMPC_OUT0_CSC_C11_C12_B_BASE_IDX 3 6859#define regMPC_OUT0_CSC_C13_C14_B 0x03f9 6860#define regMPC_OUT0_CSC_C13_C14_B_BASE_IDX 3 6861#define regMPC_OUT0_CSC_C21_C22_B 0x03fa 6862#define regMPC_OUT0_CSC_C21_C22_B_BASE_IDX 3 6863#define regMPC_OUT0_CSC_C23_C24_B 0x03fb 6864#define regMPC_OUT0_CSC_C23_C24_B_BASE_IDX 3 6865#define regMPC_OUT0_CSC_C31_C32_B 0x03fc 6866#define regMPC_OUT0_CSC_C31_C32_B_BASE_IDX 3 6867#define regMPC_OUT0_CSC_C33_C34_B 0x03fd 6868#define regMPC_OUT0_CSC_C33_C34_B_BASE_IDX 3 6869#define regMPC_OUT1_CSC_MODE 0x03fe 6870#define regMPC_OUT1_CSC_MODE_BASE_IDX 3 6871#define regMPC_OUT1_CSC_C11_C12_A 0x03ff 6872#define regMPC_OUT1_CSC_C11_C12_A_BASE_IDX 3 6873#define regMPC_OUT1_CSC_C13_C14_A 0x0400 6874#define regMPC_OUT1_CSC_C13_C14_A_BASE_IDX 3 6875#define regMPC_OUT1_CSC_C21_C22_A 0x0401 6876#define regMPC_OUT1_CSC_C21_C22_A_BASE_IDX 3 6877#define regMPC_OUT1_CSC_C23_C24_A 0x0402 6878#define regMPC_OUT1_CSC_C23_C24_A_BASE_IDX 3 6879#define regMPC_OUT1_CSC_C31_C32_A 0x0403 6880#define regMPC_OUT1_CSC_C31_C32_A_BASE_IDX 3 6881#define regMPC_OUT1_CSC_C33_C34_A 0x0404 6882#define regMPC_OUT1_CSC_C33_C34_A_BASE_IDX 3 6883#define regMPC_OUT1_CSC_C11_C12_B 0x0405 6884#define regMPC_OUT1_CSC_C11_C12_B_BASE_IDX 3 6885#define regMPC_OUT1_CSC_C13_C14_B 0x0406 6886#define regMPC_OUT1_CSC_C13_C14_B_BASE_IDX 3 6887#define regMPC_OUT1_CSC_C21_C22_B 0x0407 6888#define regMPC_OUT1_CSC_C21_C22_B_BASE_IDX 3 6889#define regMPC_OUT1_CSC_C23_C24_B 0x0408 6890#define regMPC_OUT1_CSC_C23_C24_B_BASE_IDX 3 6891#define regMPC_OUT1_CSC_C31_C32_B 0x0409 6892#define regMPC_OUT1_CSC_C31_C32_B_BASE_IDX 3 6893#define regMPC_OUT1_CSC_C33_C34_B 0x040a 6894#define regMPC_OUT1_CSC_C33_C34_B_BASE_IDX 3 6895#define regMPC_OUT2_CSC_MODE 0x040b 6896#define regMPC_OUT2_CSC_MODE_BASE_IDX 3 6897#define regMPC_OUT2_CSC_C11_C12_A 0x040c 6898#define regMPC_OUT2_CSC_C11_C12_A_BASE_IDX 3 6899#define regMPC_OUT2_CSC_C13_C14_A 0x040d 6900#define regMPC_OUT2_CSC_C13_C14_A_BASE_IDX 3 6901#define regMPC_OUT2_CSC_C21_C22_A 0x040e 6902#define regMPC_OUT2_CSC_C21_C22_A_BASE_IDX 3 6903#define regMPC_OUT2_CSC_C23_C24_A 0x040f 6904#define regMPC_OUT2_CSC_C23_C24_A_BASE_IDX 3 6905#define regMPC_OUT2_CSC_C31_C32_A 0x0410 6906#define regMPC_OUT2_CSC_C31_C32_A_BASE_IDX 3 6907#define regMPC_OUT2_CSC_C33_C34_A 0x0411 6908#define regMPC_OUT2_CSC_C33_C34_A_BASE_IDX 3 6909#define regMPC_OUT2_CSC_C11_C12_B 0x0412 6910#define regMPC_OUT2_CSC_C11_C12_B_BASE_IDX 3 6911#define regMPC_OUT2_CSC_C13_C14_B 0x0413 6912#define regMPC_OUT2_CSC_C13_C14_B_BASE_IDX 3 6913#define regMPC_OUT2_CSC_C21_C22_B 0x0414 6914#define regMPC_OUT2_CSC_C21_C22_B_BASE_IDX 3 6915#define regMPC_OUT2_CSC_C23_C24_B 0x0415 6916#define regMPC_OUT2_CSC_C23_C24_B_BASE_IDX 3 6917#define regMPC_OUT2_CSC_C31_C32_B 0x0416 6918#define regMPC_OUT2_CSC_C31_C32_B_BASE_IDX 3 6919#define regMPC_OUT2_CSC_C33_C34_B 0x0417 6920#define regMPC_OUT2_CSC_C33_C34_B_BASE_IDX 3 6921#define regMPC_OUT3_CSC_MODE 0x0418 6922#define regMPC_OUT3_CSC_MODE_BASE_IDX 3 6923#define regMPC_OUT3_CSC_C11_C12_A 0x0419 6924#define regMPC_OUT3_CSC_C11_C12_A_BASE_IDX 3 6925#define regMPC_OUT3_CSC_C13_C14_A 0x041a 6926#define regMPC_OUT3_CSC_C13_C14_A_BASE_IDX 3 6927#define regMPC_OUT3_CSC_C21_C22_A 0x041b 6928#define regMPC_OUT3_CSC_C21_C22_A_BASE_IDX 3 6929#define regMPC_OUT3_CSC_C23_C24_A 0x041c 6930#define regMPC_OUT3_CSC_C23_C24_A_BASE_IDX 3 6931#define regMPC_OUT3_CSC_C31_C32_A 0x041d 6932#define regMPC_OUT3_CSC_C31_C32_A_BASE_IDX 3 6933#define regMPC_OUT3_CSC_C33_C34_A 0x041e 6934#define regMPC_OUT3_CSC_C33_C34_A_BASE_IDX 3 6935#define regMPC_OUT3_CSC_C11_C12_B 0x041f 6936#define regMPC_OUT3_CSC_C11_C12_B_BASE_IDX 3 6937#define regMPC_OUT3_CSC_C13_C14_B 0x0420 6938#define regMPC_OUT3_CSC_C13_C14_B_BASE_IDX 3 6939#define regMPC_OUT3_CSC_C21_C22_B 0x0421 6940#define regMPC_OUT3_CSC_C21_C22_B_BASE_IDX 3 6941#define regMPC_OUT3_CSC_C23_C24_B 0x0422 6942#define regMPC_OUT3_CSC_C23_C24_B_BASE_IDX 3 6943#define regMPC_OUT3_CSC_C31_C32_B 0x0423 6944#define regMPC_OUT3_CSC_C31_C32_B_BASE_IDX 3 6945#define regMPC_OUT3_CSC_C33_C34_B 0x0424 6946#define regMPC_OUT3_CSC_C33_C34_B_BASE_IDX 3 6947 6948 6949// addressBlock: dcn_dc_opp_abm0_dispdec 6950// base address: 0x0 6951#define regABM0_BL1_PWM_AMBIENT_LIGHT_LEVEL 0x0e7a 6952#define regABM0_BL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX 3 6953#define regABM0_BL1_PWM_USER_LEVEL 0x0e7b 6954#define regABM0_BL1_PWM_USER_LEVEL_BASE_IDX 3 6955#define regABM0_BL1_PWM_TARGET_ABM_LEVEL 0x0e7c 6956#define regABM0_BL1_PWM_TARGET_ABM_LEVEL_BASE_IDX 3 6957#define regABM0_BL1_PWM_CURRENT_ABM_LEVEL 0x0e7d 6958#define regABM0_BL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX 3 6959#define regABM0_BL1_PWM_FINAL_DUTY_CYCLE 0x0e7e 6960#define regABM0_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX 3 6961#define regABM0_BL1_PWM_MINIMUM_DUTY_CYCLE 0x0e7f 6962#define regABM0_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX 3 6963#define regABM0_BL1_PWM_ABM_CNTL 0x0e80 6964#define regABM0_BL1_PWM_ABM_CNTL_BASE_IDX 3 6965#define regABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE 0x0e81 6966#define regABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX 3 6967#define regABM0_BL1_PWM_GRP2_REG_LOCK 0x0e82 6968#define regABM0_BL1_PWM_GRP2_REG_LOCK_BASE_IDX 3 6969#define regABM0_DC_ABM1_CNTL 0x0e83 6970#define regABM0_DC_ABM1_CNTL_BASE_IDX 3 6971#define regABM0_DC_ABM1_IPCSC_COEFF_SEL 0x0e84 6972#define regABM0_DC_ABM1_IPCSC_COEFF_SEL_BASE_IDX 3 6973#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_0 0x0e85 6974#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_0_BASE_IDX 3 6975#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_1 0x0e86 6976#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_1_BASE_IDX 3 6977#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_2 0x0e87 6978#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_2_BASE_IDX 3 6979#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_3 0x0e88 6980#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_3_BASE_IDX 3 6981#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_4 0x0e89 6982#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_4_BASE_IDX 3 6983#define regABM0_DC_ABM1_ACE_THRES_12 0x0e8a 6984#define regABM0_DC_ABM1_ACE_THRES_12_BASE_IDX 3 6985#define regABM0_DC_ABM1_ACE_THRES_34 0x0e8b 6986#define regABM0_DC_ABM1_ACE_THRES_34_BASE_IDX 3 6987#define regABM0_DC_ABM1_ACE_CNTL_MISC 0x0e8c 6988#define regABM0_DC_ABM1_ACE_CNTL_MISC_BASE_IDX 3 6989#define regABM0_DC_ABM1_HGLS_REG_READ_PROGRESS 0x0e8e 6990#define regABM0_DC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX 3 6991#define regABM0_DC_ABM1_HG_MISC_CTRL 0x0e8f 6992#define regABM0_DC_ABM1_HG_MISC_CTRL_BASE_IDX 3 6993#define regABM0_DC_ABM1_LS_SUM_OF_LUMA 0x0e90 6994#define regABM0_DC_ABM1_LS_SUM_OF_LUMA_BASE_IDX 3 6995#define regABM0_DC_ABM1_LS_MIN_MAX_LUMA 0x0e91 6996#define regABM0_DC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX 3 6997#define regABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA 0x0e92 6998#define regABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX 3 6999#define regABM0_DC_ABM1_LS_PIXEL_COUNT 0x0e93 7000#define regABM0_DC_ABM1_LS_PIXEL_COUNT_BASE_IDX 3 7001#define regABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES 0x0e94 7002#define regABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX 3 7003#define regABM0_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT 0x0e95 7004#define regABM0_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX 3 7005#define regABM0_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT 0x0e96 7006#define regABM0_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX 3 7007#define regABM0_DC_ABM1_HG_SAMPLE_RATE 0x0e97 7008#define regABM0_DC_ABM1_HG_SAMPLE_RATE_BASE_IDX 3 7009#define regABM0_DC_ABM1_LS_SAMPLE_RATE 0x0e98 7010#define regABM0_DC_ABM1_LS_SAMPLE_RATE_BASE_IDX 3 7011#define regABM0_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG 0x0e99 7012#define regABM0_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX 3 7013#define regABM0_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX 0x0e9a 7014#define regABM0_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX 3 7015#define regABM0_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX 0x0e9b 7016#define regABM0_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX 3 7017#define regABM0_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX 0x0e9c 7018#define regABM0_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX 3 7019#define regABM0_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX 0x0e9d 7020#define regABM0_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX 3 7021#define regABM0_DC_ABM1_HG_RESULT_1 0x0e9e 7022#define regABM0_DC_ABM1_HG_RESULT_1_BASE_IDX 3 7023#define regABM0_DC_ABM1_HG_RESULT_2 0x0e9f 7024#define regABM0_DC_ABM1_HG_RESULT_2_BASE_IDX 3 7025#define regABM0_DC_ABM1_HG_RESULT_3 0x0ea0 7026#define regABM0_DC_ABM1_HG_RESULT_3_BASE_IDX 3 7027#define regABM0_DC_ABM1_HG_RESULT_4 0x0ea1 7028#define regABM0_DC_ABM1_HG_RESULT_4_BASE_IDX 3 7029#define regABM0_DC_ABM1_HG_RESULT_5 0x0ea2 7030#define regABM0_DC_ABM1_HG_RESULT_5_BASE_IDX 3 7031#define regABM0_DC_ABM1_HG_RESULT_6 0x0ea3 7032#define regABM0_DC_ABM1_HG_RESULT_6_BASE_IDX 3 7033#define regABM0_DC_ABM1_HG_RESULT_7 0x0ea4 7034#define regABM0_DC_ABM1_HG_RESULT_7_BASE_IDX 3 7035#define regABM0_DC_ABM1_HG_RESULT_8 0x0ea5 7036#define regABM0_DC_ABM1_HG_RESULT_8_BASE_IDX 3 7037#define regABM0_DC_ABM1_HG_RESULT_9 0x0ea6 7038#define regABM0_DC_ABM1_HG_RESULT_9_BASE_IDX 3 7039#define regABM0_DC_ABM1_HG_RESULT_10 0x0ea7 7040#define regABM0_DC_ABM1_HG_RESULT_10_BASE_IDX 3 7041#define regABM0_DC_ABM1_HG_RESULT_11 0x0ea8 7042#define regABM0_DC_ABM1_HG_RESULT_11_BASE_IDX 3 7043#define regABM0_DC_ABM1_HG_RESULT_12 0x0ea9 7044#define regABM0_DC_ABM1_HG_RESULT_12_BASE_IDX 3 7045#define regABM0_DC_ABM1_HG_RESULT_13 0x0eaa 7046#define regABM0_DC_ABM1_HG_RESULT_13_BASE_IDX 3 7047#define regABM0_DC_ABM1_HG_RESULT_14 0x0eab 7048#define regABM0_DC_ABM1_HG_RESULT_14_BASE_IDX 3 7049#define regABM0_DC_ABM1_HG_RESULT_15 0x0eac 7050#define regABM0_DC_ABM1_HG_RESULT_15_BASE_IDX 3 7051#define regABM0_DC_ABM1_HG_RESULT_16 0x0ead 7052#define regABM0_DC_ABM1_HG_RESULT_16_BASE_IDX 3 7053#define regABM0_DC_ABM1_HG_RESULT_17 0x0eae 7054#define regABM0_DC_ABM1_HG_RESULT_17_BASE_IDX 3 7055#define regABM0_DC_ABM1_HG_RESULT_18 0x0eaf 7056#define regABM0_DC_ABM1_HG_RESULT_18_BASE_IDX 3 7057#define regABM0_DC_ABM1_HG_RESULT_19 0x0eb0 7058#define regABM0_DC_ABM1_HG_RESULT_19_BASE_IDX 3 7059#define regABM0_DC_ABM1_HG_RESULT_20 0x0eb1 7060#define regABM0_DC_ABM1_HG_RESULT_20_BASE_IDX 3 7061#define regABM0_DC_ABM1_HG_RESULT_21 0x0eb2 7062#define regABM0_DC_ABM1_HG_RESULT_21_BASE_IDX 3 7063#define regABM0_DC_ABM1_HG_RESULT_22 0x0eb3 7064#define regABM0_DC_ABM1_HG_RESULT_22_BASE_IDX 3 7065#define regABM0_DC_ABM1_HG_RESULT_23 0x0eb4 7066#define regABM0_DC_ABM1_HG_RESULT_23_BASE_IDX 3 7067#define regABM0_DC_ABM1_HG_RESULT_24 0x0eb5 7068#define regABM0_DC_ABM1_HG_RESULT_24_BASE_IDX 3 7069#define regABM0_DC_ABM1_BL_MASTER_LOCK 0x0eb6 7070#define regABM0_DC_ABM1_BL_MASTER_LOCK_BASE_IDX 3 7071 7072 7073// addressBlock: dcn_dc_opp_abm1_dispdec 7074// base address: 0x104 7075#define regABM1_BL1_PWM_AMBIENT_LIGHT_LEVEL 0x0ebb 7076#define regABM1_BL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX 3 7077#define regABM1_BL1_PWM_USER_LEVEL 0x0ebc 7078#define regABM1_BL1_PWM_USER_LEVEL_BASE_IDX 3 7079#define regABM1_BL1_PWM_TARGET_ABM_LEVEL 0x0ebd 7080#define regABM1_BL1_PWM_TARGET_ABM_LEVEL_BASE_IDX 3 7081#define regABM1_BL1_PWM_CURRENT_ABM_LEVEL 0x0ebe 7082#define regABM1_BL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX 3 7083#define regABM1_BL1_PWM_FINAL_DUTY_CYCLE 0x0ebf 7084#define regABM1_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX 3 7085#define regABM1_BL1_PWM_MINIMUM_DUTY_CYCLE 0x0ec0 7086#define regABM1_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX 3 7087#define regABM1_BL1_PWM_ABM_CNTL 0x0ec1 7088#define regABM1_BL1_PWM_ABM_CNTL_BASE_IDX 3 7089#define regABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE 0x0ec2 7090#define regABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX 3 7091#define regABM1_BL1_PWM_GRP2_REG_LOCK 0x0ec3 7092#define regABM1_BL1_PWM_GRP2_REG_LOCK_BASE_IDX 3 7093#define regABM1_DC_ABM1_CNTL 0x0ec4 7094#define regABM1_DC_ABM1_CNTL_BASE_IDX 3 7095#define regABM1_DC_ABM1_IPCSC_COEFF_SEL 0x0ec5 7096#define regABM1_DC_ABM1_IPCSC_COEFF_SEL_BASE_IDX 3 7097#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_0 0x0ec6 7098#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_0_BASE_IDX 3 7099#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_1 0x0ec7 7100#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_1_BASE_IDX 3 7101#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_2 0x0ec8 7102#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_2_BASE_IDX 3 7103#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_3 0x0ec9 7104#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_3_BASE_IDX 3 7105#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_4 0x0eca 7106#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_4_BASE_IDX 3 7107#define regABM1_DC_ABM1_ACE_THRES_12 0x0ecb 7108#define regABM1_DC_ABM1_ACE_THRES_12_BASE_IDX 3 7109#define regABM1_DC_ABM1_ACE_THRES_34 0x0ecc 7110#define regABM1_DC_ABM1_ACE_THRES_34_BASE_IDX 3 7111#define regABM1_DC_ABM1_ACE_CNTL_MISC 0x0ecd 7112#define regABM1_DC_ABM1_ACE_CNTL_MISC_BASE_IDX 3 7113#define regABM1_DC_ABM1_HGLS_REG_READ_PROGRESS 0x0ecf 7114#define regABM1_DC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX 3 7115#define regABM1_DC_ABM1_HG_MISC_CTRL 0x0ed0 7116#define regABM1_DC_ABM1_HG_MISC_CTRL_BASE_IDX 3 7117#define regABM1_DC_ABM1_LS_SUM_OF_LUMA 0x0ed1 7118#define regABM1_DC_ABM1_LS_SUM_OF_LUMA_BASE_IDX 3 7119#define regABM1_DC_ABM1_LS_MIN_MAX_LUMA 0x0ed2 7120#define regABM1_DC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX 3 7121#define regABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA 0x0ed3 7122#define regABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX 3 7123#define regABM1_DC_ABM1_LS_PIXEL_COUNT 0x0ed4 7124#define regABM1_DC_ABM1_LS_PIXEL_COUNT_BASE_IDX 3 7125#define regABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES 0x0ed5 7126#define regABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX 3 7127#define regABM1_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT 0x0ed6 7128#define regABM1_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX 3 7129#define regABM1_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT 0x0ed7 7130#define regABM1_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX 3 7131#define regABM1_DC_ABM1_HG_SAMPLE_RATE 0x0ed8 7132#define regABM1_DC_ABM1_HG_SAMPLE_RATE_BASE_IDX 3 7133#define regABM1_DC_ABM1_LS_SAMPLE_RATE 0x0ed9 7134#define regABM1_DC_ABM1_LS_SAMPLE_RATE_BASE_IDX 3 7135#define regABM1_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG 0x0eda 7136#define regABM1_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX 3 7137#define regABM1_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX 0x0edb 7138#define regABM1_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX 3 7139#define regABM1_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX 0x0edc 7140#define regABM1_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX 3 7141#define regABM1_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX 0x0edd 7142#define regABM1_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX 3 7143#define regABM1_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX 0x0ede 7144#define regABM1_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX 3 7145#define regABM1_DC_ABM1_HG_RESULT_1 0x0edf 7146#define regABM1_DC_ABM1_HG_RESULT_1_BASE_IDX 3 7147#define regABM1_DC_ABM1_HG_RESULT_2 0x0ee0 7148#define regABM1_DC_ABM1_HG_RESULT_2_BASE_IDX 3 7149#define regABM1_DC_ABM1_HG_RESULT_3 0x0ee1 7150#define regABM1_DC_ABM1_HG_RESULT_3_BASE_IDX 3 7151#define regABM1_DC_ABM1_HG_RESULT_4 0x0ee2 7152#define regABM1_DC_ABM1_HG_RESULT_4_BASE_IDX 3 7153#define regABM1_DC_ABM1_HG_RESULT_5 0x0ee3 7154#define regABM1_DC_ABM1_HG_RESULT_5_BASE_IDX 3 7155#define regABM1_DC_ABM1_HG_RESULT_6 0x0ee4 7156#define regABM1_DC_ABM1_HG_RESULT_6_BASE_IDX 3 7157#define regABM1_DC_ABM1_HG_RESULT_7 0x0ee5 7158#define regABM1_DC_ABM1_HG_RESULT_7_BASE_IDX 3 7159#define regABM1_DC_ABM1_HG_RESULT_8 0x0ee6 7160#define regABM1_DC_ABM1_HG_RESULT_8_BASE_IDX 3 7161#define regABM1_DC_ABM1_HG_RESULT_9 0x0ee7 7162#define regABM1_DC_ABM1_HG_RESULT_9_BASE_IDX 3 7163#define regABM1_DC_ABM1_HG_RESULT_10 0x0ee8 7164#define regABM1_DC_ABM1_HG_RESULT_10_BASE_IDX 3 7165#define regABM1_DC_ABM1_HG_RESULT_11 0x0ee9 7166#define regABM1_DC_ABM1_HG_RESULT_11_BASE_IDX 3 7167#define regABM1_DC_ABM1_HG_RESULT_12 0x0eea 7168#define regABM1_DC_ABM1_HG_RESULT_12_BASE_IDX 3 7169#define regABM1_DC_ABM1_HG_RESULT_13 0x0eeb 7170#define regABM1_DC_ABM1_HG_RESULT_13_BASE_IDX 3 7171#define regABM1_DC_ABM1_HG_RESULT_14 0x0eec 7172#define regABM1_DC_ABM1_HG_RESULT_14_BASE_IDX 3 7173#define regABM1_DC_ABM1_HG_RESULT_15 0x0eed 7174#define regABM1_DC_ABM1_HG_RESULT_15_BASE_IDX 3 7175#define regABM1_DC_ABM1_HG_RESULT_16 0x0eee 7176#define regABM1_DC_ABM1_HG_RESULT_16_BASE_IDX 3 7177#define regABM1_DC_ABM1_HG_RESULT_17 0x0eef 7178#define regABM1_DC_ABM1_HG_RESULT_17_BASE_IDX 3 7179#define regABM1_DC_ABM1_HG_RESULT_18 0x0ef0 7180#define regABM1_DC_ABM1_HG_RESULT_18_BASE_IDX 3 7181#define regABM1_DC_ABM1_HG_RESULT_19 0x0ef1 7182#define regABM1_DC_ABM1_HG_RESULT_19_BASE_IDX 3 7183#define regABM1_DC_ABM1_HG_RESULT_20 0x0ef2 7184#define regABM1_DC_ABM1_HG_RESULT_20_BASE_IDX 3 7185#define regABM1_DC_ABM1_HG_RESULT_21 0x0ef3 7186#define regABM1_DC_ABM1_HG_RESULT_21_BASE_IDX 3 7187#define regABM1_DC_ABM1_HG_RESULT_22 0x0ef4 7188#define regABM1_DC_ABM1_HG_RESULT_22_BASE_IDX 3 7189#define regABM1_DC_ABM1_HG_RESULT_23 0x0ef5 7190#define regABM1_DC_ABM1_HG_RESULT_23_BASE_IDX 3 7191#define regABM1_DC_ABM1_HG_RESULT_24 0x0ef6 7192#define regABM1_DC_ABM1_HG_RESULT_24_BASE_IDX 3 7193#define regABM1_DC_ABM1_BL_MASTER_LOCK 0x0ef7 7194#define regABM1_DC_ABM1_BL_MASTER_LOCK_BASE_IDX 3 7195 7196 7197// addressBlock: dcn_dc_opp_abm2_dispdec 7198// base address: 0x208 7199#define regABM2_BL1_PWM_AMBIENT_LIGHT_LEVEL 0x0efc 7200#define regABM2_BL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX 3 7201#define regABM2_BL1_PWM_USER_LEVEL 0x0efd 7202#define regABM2_BL1_PWM_USER_LEVEL_BASE_IDX 3 7203#define regABM2_BL1_PWM_TARGET_ABM_LEVEL 0x0efe 7204#define regABM2_BL1_PWM_TARGET_ABM_LEVEL_BASE_IDX 3 7205#define regABM2_BL1_PWM_CURRENT_ABM_LEVEL 0x0eff 7206#define regABM2_BL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX 3 7207#define regABM2_BL1_PWM_FINAL_DUTY_CYCLE 0x0f00 7208#define regABM2_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX 3 7209#define regABM2_BL1_PWM_MINIMUM_DUTY_CYCLE 0x0f01 7210#define regABM2_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX 3 7211#define regABM2_BL1_PWM_ABM_CNTL 0x0f02 7212#define regABM2_BL1_PWM_ABM_CNTL_BASE_IDX 3 7213#define regABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE 0x0f03 7214#define regABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX 3 7215#define regABM2_BL1_PWM_GRP2_REG_LOCK 0x0f04 7216#define regABM2_BL1_PWM_GRP2_REG_LOCK_BASE_IDX 3 7217#define regABM2_DC_ABM1_CNTL 0x0f05 7218#define regABM2_DC_ABM1_CNTL_BASE_IDX 3 7219#define regABM2_DC_ABM1_IPCSC_COEFF_SEL 0x0f06 7220#define regABM2_DC_ABM1_IPCSC_COEFF_SEL_BASE_IDX 3 7221#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_0 0x0f07 7222#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_0_BASE_IDX 3 7223#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_1 0x0f08 7224#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_1_BASE_IDX 3 7225#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_2 0x0f09 7226#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_2_BASE_IDX 3 7227#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_3 0x0f0a 7228#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_3_BASE_IDX 3 7229#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_4 0x0f0b 7230#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_4_BASE_IDX 3 7231#define regABM2_DC_ABM1_ACE_THRES_12 0x0f0c 7232#define regABM2_DC_ABM1_ACE_THRES_12_BASE_IDX 3 7233#define regABM2_DC_ABM1_ACE_THRES_34 0x0f0d 7234#define regABM2_DC_ABM1_ACE_THRES_34_BASE_IDX 3 7235#define regABM2_DC_ABM1_ACE_CNTL_MISC 0x0f0e 7236#define regABM2_DC_ABM1_ACE_CNTL_MISC_BASE_IDX 3 7237#define regABM2_DC_ABM1_HGLS_REG_READ_PROGRESS 0x0f10 7238#define regABM2_DC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX 3 7239#define regABM2_DC_ABM1_HG_MISC_CTRL 0x0f11 7240#define regABM2_DC_ABM1_HG_MISC_CTRL_BASE_IDX 3 7241#define regABM2_DC_ABM1_LS_SUM_OF_LUMA 0x0f12 7242#define regABM2_DC_ABM1_LS_SUM_OF_LUMA_BASE_IDX 3 7243#define regABM2_DC_ABM1_LS_MIN_MAX_LUMA 0x0f13 7244#define regABM2_DC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX 3 7245#define regABM2_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA 0x0f14 7246#define regABM2_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX 3 7247#define regABM2_DC_ABM1_LS_PIXEL_COUNT 0x0f15 7248#define regABM2_DC_ABM1_LS_PIXEL_COUNT_BASE_IDX 3 7249#define regABM2_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES 0x0f16 7250#define regABM2_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX 3 7251#define regABM2_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT 0x0f17 7252#define regABM2_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX 3 7253#define regABM2_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT 0x0f18 7254#define regABM2_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX 3 7255#define regABM2_DC_ABM1_HG_SAMPLE_RATE 0x0f19 7256#define regABM2_DC_ABM1_HG_SAMPLE_RATE_BASE_IDX 3 7257#define regABM2_DC_ABM1_LS_SAMPLE_RATE 0x0f1a 7258#define regABM2_DC_ABM1_LS_SAMPLE_RATE_BASE_IDX 3 7259#define regABM2_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG 0x0f1b 7260#define regABM2_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX 3 7261#define regABM2_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX 0x0f1c 7262#define regABM2_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX 3 7263#define regABM2_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX 0x0f1d 7264#define regABM2_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX 3 7265#define regABM2_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX 0x0f1e 7266#define regABM2_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX 3 7267#define regABM2_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX 0x0f1f 7268#define regABM2_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX 3 7269#define regABM2_DC_ABM1_HG_RESULT_1 0x0f20 7270#define regABM2_DC_ABM1_HG_RESULT_1_BASE_IDX 3 7271#define regABM2_DC_ABM1_HG_RESULT_2 0x0f21 7272#define regABM2_DC_ABM1_HG_RESULT_2_BASE_IDX 3 7273#define regABM2_DC_ABM1_HG_RESULT_3 0x0f22 7274#define regABM2_DC_ABM1_HG_RESULT_3_BASE_IDX 3 7275#define regABM2_DC_ABM1_HG_RESULT_4 0x0f23 7276#define regABM2_DC_ABM1_HG_RESULT_4_BASE_IDX 3 7277#define regABM2_DC_ABM1_HG_RESULT_5 0x0f24 7278#define regABM2_DC_ABM1_HG_RESULT_5_BASE_IDX 3 7279#define regABM2_DC_ABM1_HG_RESULT_6 0x0f25 7280#define regABM2_DC_ABM1_HG_RESULT_6_BASE_IDX 3 7281#define regABM2_DC_ABM1_HG_RESULT_7 0x0f26 7282#define regABM2_DC_ABM1_HG_RESULT_7_BASE_IDX 3 7283#define regABM2_DC_ABM1_HG_RESULT_8 0x0f27 7284#define regABM2_DC_ABM1_HG_RESULT_8_BASE_IDX 3 7285#define regABM2_DC_ABM1_HG_RESULT_9 0x0f28 7286#define regABM2_DC_ABM1_HG_RESULT_9_BASE_IDX 3 7287#define regABM2_DC_ABM1_HG_RESULT_10 0x0f29 7288#define regABM2_DC_ABM1_HG_RESULT_10_BASE_IDX 3 7289#define regABM2_DC_ABM1_HG_RESULT_11 0x0f2a 7290#define regABM2_DC_ABM1_HG_RESULT_11_BASE_IDX 3 7291#define regABM2_DC_ABM1_HG_RESULT_12 0x0f2b 7292#define regABM2_DC_ABM1_HG_RESULT_12_BASE_IDX 3 7293#define regABM2_DC_ABM1_HG_RESULT_13 0x0f2c 7294#define regABM2_DC_ABM1_HG_RESULT_13_BASE_IDX 3 7295#define regABM2_DC_ABM1_HG_RESULT_14 0x0f2d 7296#define regABM2_DC_ABM1_HG_RESULT_14_BASE_IDX 3 7297#define regABM2_DC_ABM1_HG_RESULT_15 0x0f2e 7298#define regABM2_DC_ABM1_HG_RESULT_15_BASE_IDX 3 7299#define regABM2_DC_ABM1_HG_RESULT_16 0x0f2f 7300#define regABM2_DC_ABM1_HG_RESULT_16_BASE_IDX 3 7301#define regABM2_DC_ABM1_HG_RESULT_17 0x0f30 7302#define regABM2_DC_ABM1_HG_RESULT_17_BASE_IDX 3 7303#define regABM2_DC_ABM1_HG_RESULT_18 0x0f31 7304#define regABM2_DC_ABM1_HG_RESULT_18_BASE_IDX 3 7305#define regABM2_DC_ABM1_HG_RESULT_19 0x0f32 7306#define regABM2_DC_ABM1_HG_RESULT_19_BASE_IDX 3 7307#define regABM2_DC_ABM1_HG_RESULT_20 0x0f33 7308#define regABM2_DC_ABM1_HG_RESULT_20_BASE_IDX 3 7309#define regABM2_DC_ABM1_HG_RESULT_21 0x0f34 7310#define regABM2_DC_ABM1_HG_RESULT_21_BASE_IDX 3 7311#define regABM2_DC_ABM1_HG_RESULT_22 0x0f35 7312#define regABM2_DC_ABM1_HG_RESULT_22_BASE_IDX 3 7313#define regABM2_DC_ABM1_HG_RESULT_23 0x0f36 7314#define regABM2_DC_ABM1_HG_RESULT_23_BASE_IDX 3 7315#define regABM2_DC_ABM1_HG_RESULT_24 0x0f37 7316#define regABM2_DC_ABM1_HG_RESULT_24_BASE_IDX 3 7317#define regABM2_DC_ABM1_BL_MASTER_LOCK 0x0f38 7318#define regABM2_DC_ABM1_BL_MASTER_LOCK_BASE_IDX 3 7319 7320 7321// addressBlock: dcn_dc_opp_abm3_dispdec 7322// base address: 0x30c 7323#define regABM3_BL1_PWM_AMBIENT_LIGHT_LEVEL 0x0f3d 7324#define regABM3_BL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX 3 7325#define regABM3_BL1_PWM_USER_LEVEL 0x0f3e 7326#define regABM3_BL1_PWM_USER_LEVEL_BASE_IDX 3 7327#define regABM3_BL1_PWM_TARGET_ABM_LEVEL 0x0f3f 7328#define regABM3_BL1_PWM_TARGET_ABM_LEVEL_BASE_IDX 3 7329#define regABM3_BL1_PWM_CURRENT_ABM_LEVEL 0x0f40 7330#define regABM3_BL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX 3 7331#define regABM3_BL1_PWM_FINAL_DUTY_CYCLE 0x0f41 7332#define regABM3_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX 3 7333#define regABM3_BL1_PWM_MINIMUM_DUTY_CYCLE 0x0f42 7334#define regABM3_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX 3 7335#define regABM3_BL1_PWM_ABM_CNTL 0x0f43 7336#define regABM3_BL1_PWM_ABM_CNTL_BASE_IDX 3 7337#define regABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE 0x0f44 7338#define regABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX 3 7339#define regABM3_BL1_PWM_GRP2_REG_LOCK 0x0f45 7340#define regABM3_BL1_PWM_GRP2_REG_LOCK_BASE_IDX 3 7341#define regABM3_DC_ABM1_CNTL 0x0f46 7342#define regABM3_DC_ABM1_CNTL_BASE_IDX 3 7343#define regABM3_DC_ABM1_IPCSC_COEFF_SEL 0x0f47 7344#define regABM3_DC_ABM1_IPCSC_COEFF_SEL_BASE_IDX 3 7345#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_0 0x0f48 7346#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_0_BASE_IDX 3 7347#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_1 0x0f49 7348#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_1_BASE_IDX 3 7349#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_2 0x0f4a 7350#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_2_BASE_IDX 3 7351#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_3 0x0f4b 7352#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_3_BASE_IDX 3 7353#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_4 0x0f4c 7354#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_4_BASE_IDX 3 7355#define regABM3_DC_ABM1_ACE_THRES_12 0x0f4d 7356#define regABM3_DC_ABM1_ACE_THRES_12_BASE_IDX 3 7357#define regABM3_DC_ABM1_ACE_THRES_34 0x0f4e 7358#define regABM3_DC_ABM1_ACE_THRES_34_BASE_IDX 3 7359#define regABM3_DC_ABM1_ACE_CNTL_MISC 0x0f4f 7360#define regABM3_DC_ABM1_ACE_CNTL_MISC_BASE_IDX 3 7361#define regABM3_DC_ABM1_HGLS_REG_READ_PROGRESS 0x0f51 7362#define regABM3_DC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX 3 7363#define regABM3_DC_ABM1_HG_MISC_CTRL 0x0f52 7364#define regABM3_DC_ABM1_HG_MISC_CTRL_BASE_IDX 3 7365#define regABM3_DC_ABM1_LS_SUM_OF_LUMA 0x0f53 7366#define regABM3_DC_ABM1_LS_SUM_OF_LUMA_BASE_IDX 3 7367#define regABM3_DC_ABM1_LS_MIN_MAX_LUMA 0x0f54 7368#define regABM3_DC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX 3 7369#define regABM3_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA 0x0f55 7370#define regABM3_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX 3 7371#define regABM3_DC_ABM1_LS_PIXEL_COUNT 0x0f56 7372#define regABM3_DC_ABM1_LS_PIXEL_COUNT_BASE_IDX 3 7373#define regABM3_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES 0x0f57 7374#define regABM3_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX 3 7375#define regABM3_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT 0x0f58 7376#define regABM3_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX 3 7377#define regABM3_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT 0x0f59 7378#define regABM3_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX 3 7379#define regABM3_DC_ABM1_HG_SAMPLE_RATE 0x0f5a 7380#define regABM3_DC_ABM1_HG_SAMPLE_RATE_BASE_IDX 3 7381#define regABM3_DC_ABM1_LS_SAMPLE_RATE 0x0f5b 7382#define regABM3_DC_ABM1_LS_SAMPLE_RATE_BASE_IDX 3 7383#define regABM3_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG 0x0f5c 7384#define regABM3_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX 3 7385#define regABM3_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX 0x0f5d 7386#define regABM3_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX 3 7387#define regABM3_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX 0x0f5e 7388#define regABM3_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX 3 7389#define regABM3_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX 0x0f5f 7390#define regABM3_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX 3 7391#define regABM3_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX 0x0f60 7392#define regABM3_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX 3 7393#define regABM3_DC_ABM1_HG_RESULT_1 0x0f61 7394#define regABM3_DC_ABM1_HG_RESULT_1_BASE_IDX 3 7395#define regABM3_DC_ABM1_HG_RESULT_2 0x0f62 7396#define regABM3_DC_ABM1_HG_RESULT_2_BASE_IDX 3 7397#define regABM3_DC_ABM1_HG_RESULT_3 0x0f63 7398#define regABM3_DC_ABM1_HG_RESULT_3_BASE_IDX 3 7399#define regABM3_DC_ABM1_HG_RESULT_4 0x0f64 7400#define regABM3_DC_ABM1_HG_RESULT_4_BASE_IDX 3 7401#define regABM3_DC_ABM1_HG_RESULT_5 0x0f65 7402#define regABM3_DC_ABM1_HG_RESULT_5_BASE_IDX 3 7403#define regABM3_DC_ABM1_HG_RESULT_6 0x0f66 7404#define regABM3_DC_ABM1_HG_RESULT_6_BASE_IDX 3 7405#define regABM3_DC_ABM1_HG_RESULT_7 0x0f67 7406#define regABM3_DC_ABM1_HG_RESULT_7_BASE_IDX 3 7407#define regABM3_DC_ABM1_HG_RESULT_8 0x0f68 7408#define regABM3_DC_ABM1_HG_RESULT_8_BASE_IDX 3 7409#define regABM3_DC_ABM1_HG_RESULT_9 0x0f69 7410#define regABM3_DC_ABM1_HG_RESULT_9_BASE_IDX 3 7411#define regABM3_DC_ABM1_HG_RESULT_10 0x0f6a 7412#define regABM3_DC_ABM1_HG_RESULT_10_BASE_IDX 3 7413#define regABM3_DC_ABM1_HG_RESULT_11 0x0f6b 7414#define regABM3_DC_ABM1_HG_RESULT_11_BASE_IDX 3 7415#define regABM3_DC_ABM1_HG_RESULT_12 0x0f6c 7416#define regABM3_DC_ABM1_HG_RESULT_12_BASE_IDX 3 7417#define regABM3_DC_ABM1_HG_RESULT_13 0x0f6d 7418#define regABM3_DC_ABM1_HG_RESULT_13_BASE_IDX 3 7419#define regABM3_DC_ABM1_HG_RESULT_14 0x0f6e 7420#define regABM3_DC_ABM1_HG_RESULT_14_BASE_IDX 3 7421#define regABM3_DC_ABM1_HG_RESULT_15 0x0f6f 7422#define regABM3_DC_ABM1_HG_RESULT_15_BASE_IDX 3 7423#define regABM3_DC_ABM1_HG_RESULT_16 0x0f70 7424#define regABM3_DC_ABM1_HG_RESULT_16_BASE_IDX 3 7425#define regABM3_DC_ABM1_HG_RESULT_17 0x0f71 7426#define regABM3_DC_ABM1_HG_RESULT_17_BASE_IDX 3 7427#define regABM3_DC_ABM1_HG_RESULT_18 0x0f72 7428#define regABM3_DC_ABM1_HG_RESULT_18_BASE_IDX 3 7429#define regABM3_DC_ABM1_HG_RESULT_19 0x0f73 7430#define regABM3_DC_ABM1_HG_RESULT_19_BASE_IDX 3 7431#define regABM3_DC_ABM1_HG_RESULT_20 0x0f74 7432#define regABM3_DC_ABM1_HG_RESULT_20_BASE_IDX 3 7433#define regABM3_DC_ABM1_HG_RESULT_21 0x0f75 7434#define regABM3_DC_ABM1_HG_RESULT_21_BASE_IDX 3 7435#define regABM3_DC_ABM1_HG_RESULT_22 0x0f76 7436#define regABM3_DC_ABM1_HG_RESULT_22_BASE_IDX 3 7437#define regABM3_DC_ABM1_HG_RESULT_23 0x0f77 7438#define regABM3_DC_ABM1_HG_RESULT_23_BASE_IDX 3 7439#define regABM3_DC_ABM1_HG_RESULT_24 0x0f78 7440#define regABM3_DC_ABM1_HG_RESULT_24_BASE_IDX 3 7441#define regABM3_DC_ABM1_BL_MASTER_LOCK 0x0f79 7442#define regABM3_DC_ABM1_BL_MASTER_LOCK_BASE_IDX 3 7443 7444 7445// addressBlock: dcn_dc_opp_dpg0_dispdec 7446// base address: 0x0 7447#define regDPG0_DPG_CONTROL 0x1854 7448#define regDPG0_DPG_CONTROL_BASE_IDX 2 7449#define regDPG0_DPG_RAMP_CONTROL 0x1855 7450#define regDPG0_DPG_RAMP_CONTROL_BASE_IDX 2 7451#define regDPG0_DPG_DIMENSIONS 0x1856 7452#define regDPG0_DPG_DIMENSIONS_BASE_IDX 2 7453#define regDPG0_DPG_COLOUR_R_CR 0x1857 7454#define regDPG0_DPG_COLOUR_R_CR_BASE_IDX 2 7455#define regDPG0_DPG_COLOUR_G_Y 0x1858 7456#define regDPG0_DPG_COLOUR_G_Y_BASE_IDX 2 7457#define regDPG0_DPG_COLOUR_B_CB 0x1859 7458#define regDPG0_DPG_COLOUR_B_CB_BASE_IDX 2 7459#define regDPG0_DPG_OFFSET_SEGMENT 0x185a 7460#define regDPG0_DPG_OFFSET_SEGMENT_BASE_IDX 2 7461#define regDPG0_DPG_STATUS 0x185b 7462#define regDPG0_DPG_STATUS_BASE_IDX 2 7463 7464 7465// addressBlock: dcn_dc_opp_fmt0_dispdec 7466// base address: 0x0 7467#define regFMT0_FMT_CLAMP_COMPONENT_R 0x183c 7468#define regFMT0_FMT_CLAMP_COMPONENT_R_BASE_IDX 2 7469#define regFMT0_FMT_CLAMP_COMPONENT_G 0x183d 7470#define regFMT0_FMT_CLAMP_COMPONENT_G_BASE_IDX 2 7471#define regFMT0_FMT_CLAMP_COMPONENT_B 0x183e 7472#define regFMT0_FMT_CLAMP_COMPONENT_B_BASE_IDX 2 7473#define regFMT0_FMT_DYNAMIC_EXP_CNTL 0x183f 7474#define regFMT0_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2 7475#define regFMT0_FMT_CONTROL 0x1840 7476#define regFMT0_FMT_CONTROL_BASE_IDX 2 7477#define regFMT0_FMT_BIT_DEPTH_CONTROL 0x1841 7478#define regFMT0_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2 7479#define regFMT0_FMT_DITHER_RAND_R_SEED 0x1842 7480#define regFMT0_FMT_DITHER_RAND_R_SEED_BASE_IDX 2 7481#define regFMT0_FMT_DITHER_RAND_G_SEED 0x1843 7482#define regFMT0_FMT_DITHER_RAND_G_SEED_BASE_IDX 2 7483#define regFMT0_FMT_DITHER_RAND_B_SEED 0x1844 7484#define regFMT0_FMT_DITHER_RAND_B_SEED_BASE_IDX 2 7485#define regFMT0_FMT_CLAMP_CNTL 0x1845 7486#define regFMT0_FMT_CLAMP_CNTL_BASE_IDX 2 7487#define regFMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x1846 7488#define regFMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2 7489#define regFMT0_FMT_MAP420_MEMORY_CONTROL 0x1847 7490#define regFMT0_FMT_MAP420_MEMORY_CONTROL_BASE_IDX 2 7491#define regFMT0_FMT_422_CONTROL 0x1849 7492#define regFMT0_FMT_422_CONTROL_BASE_IDX 2 7493 7494 7495// addressBlock: dcn_dc_opp_oppbuf0_dispdec 7496// base address: 0x0 7497#define regOPPBUF0_OPPBUF_CONTROL 0x1884 7498#define regOPPBUF0_OPPBUF_CONTROL_BASE_IDX 2 7499#define regOPPBUF0_OPPBUF_3D_PARAMETERS_0 0x1885 7500#define regOPPBUF0_OPPBUF_3D_PARAMETERS_0_BASE_IDX 2 7501#define regOPPBUF0_OPPBUF_3D_PARAMETERS_1 0x1886 7502#define regOPPBUF0_OPPBUF_3D_PARAMETERS_1_BASE_IDX 2 7503#define regOPPBUF0_OPPBUF_CONTROL1 0x1889 7504#define regOPPBUF0_OPPBUF_CONTROL1_BASE_IDX 2 7505 7506 7507// addressBlock: dcn_dc_opp_opp_pipe0_dispdec 7508// base address: 0x0 7509#define regOPP_PIPE0_OPP_PIPE_CONTROL 0x188c 7510#define regOPP_PIPE0_OPP_PIPE_CONTROL_BASE_IDX 2 7511 7512 7513// addressBlock: dcn_dc_opp_opp_pipe_crc0_dispdec 7514// base address: 0x0 7515#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL 0x1891 7516#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL_BASE_IDX 2 7517#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_MASK 0x1892 7518#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_MASK_BASE_IDX 2 7519#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0 0x1893 7520#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0_BASE_IDX 2 7521#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1 0x1894 7522#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1_BASE_IDX 2 7523#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2 0x1895 7524#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2_BASE_IDX 2 7525 7526 7527// addressBlock: dcn_dc_opp_dpg1_dispdec 7528// base address: 0x168 7529#define regDPG1_DPG_CONTROL 0x18ae 7530#define regDPG1_DPG_CONTROL_BASE_IDX 2 7531#define regDPG1_DPG_RAMP_CONTROL 0x18af 7532#define regDPG1_DPG_RAMP_CONTROL_BASE_IDX 2 7533#define regDPG1_DPG_DIMENSIONS 0x18b0 7534#define regDPG1_DPG_DIMENSIONS_BASE_IDX 2 7535#define regDPG1_DPG_COLOUR_R_CR 0x18b1 7536#define regDPG1_DPG_COLOUR_R_CR_BASE_IDX 2 7537#define regDPG1_DPG_COLOUR_G_Y 0x18b2 7538#define regDPG1_DPG_COLOUR_G_Y_BASE_IDX 2 7539#define regDPG1_DPG_COLOUR_B_CB 0x18b3 7540#define regDPG1_DPG_COLOUR_B_CB_BASE_IDX 2 7541#define regDPG1_DPG_OFFSET_SEGMENT 0x18b4 7542#define regDPG1_DPG_OFFSET_SEGMENT_BASE_IDX 2 7543#define regDPG1_DPG_STATUS 0x18b5 7544#define regDPG1_DPG_STATUS_BASE_IDX 2 7545 7546 7547// addressBlock: dcn_dc_opp_fmt1_dispdec 7548// base address: 0x168 7549#define regFMT1_FMT_CLAMP_COMPONENT_R 0x1896 7550#define regFMT1_FMT_CLAMP_COMPONENT_R_BASE_IDX 2 7551#define regFMT1_FMT_CLAMP_COMPONENT_G 0x1897 7552#define regFMT1_FMT_CLAMP_COMPONENT_G_BASE_IDX 2 7553#define regFMT1_FMT_CLAMP_COMPONENT_B 0x1898 7554#define regFMT1_FMT_CLAMP_COMPONENT_B_BASE_IDX 2 7555#define regFMT1_FMT_DYNAMIC_EXP_CNTL 0x1899 7556#define regFMT1_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2 7557#define regFMT1_FMT_CONTROL 0x189a 7558#define regFMT1_FMT_CONTROL_BASE_IDX 2 7559#define regFMT1_FMT_BIT_DEPTH_CONTROL 0x189b 7560#define regFMT1_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2 7561#define regFMT1_FMT_DITHER_RAND_R_SEED 0x189c 7562#define regFMT1_FMT_DITHER_RAND_R_SEED_BASE_IDX 2 7563#define regFMT1_FMT_DITHER_RAND_G_SEED 0x189d 7564#define regFMT1_FMT_DITHER_RAND_G_SEED_BASE_IDX 2 7565#define regFMT1_FMT_DITHER_RAND_B_SEED 0x189e 7566#define regFMT1_FMT_DITHER_RAND_B_SEED_BASE_IDX 2 7567#define regFMT1_FMT_CLAMP_CNTL 0x189f 7568#define regFMT1_FMT_CLAMP_CNTL_BASE_IDX 2 7569#define regFMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x18a0 7570#define regFMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2 7571#define regFMT1_FMT_MAP420_MEMORY_CONTROL 0x18a1 7572#define regFMT1_FMT_MAP420_MEMORY_CONTROL_BASE_IDX 2 7573#define regFMT1_FMT_422_CONTROL 0x18a3 7574#define regFMT1_FMT_422_CONTROL_BASE_IDX 2 7575 7576 7577// addressBlock: dcn_dc_opp_oppbuf1_dispdec 7578// base address: 0x168 7579#define regOPPBUF1_OPPBUF_CONTROL 0x18de 7580#define regOPPBUF1_OPPBUF_CONTROL_BASE_IDX 2 7581#define regOPPBUF1_OPPBUF_3D_PARAMETERS_0 0x18df 7582#define regOPPBUF1_OPPBUF_3D_PARAMETERS_0_BASE_IDX 2 7583#define regOPPBUF1_OPPBUF_3D_PARAMETERS_1 0x18e0 7584#define regOPPBUF1_OPPBUF_3D_PARAMETERS_1_BASE_IDX 2 7585#define regOPPBUF1_OPPBUF_CONTROL1 0x18e3 7586#define regOPPBUF1_OPPBUF_CONTROL1_BASE_IDX 2 7587 7588 7589// addressBlock: dcn_dc_opp_opp_pipe1_dispdec 7590// base address: 0x168 7591#define regOPP_PIPE1_OPP_PIPE_CONTROL 0x18e6 7592#define regOPP_PIPE1_OPP_PIPE_CONTROL_BASE_IDX 2 7593 7594 7595// addressBlock: dcn_dc_opp_opp_pipe_crc1_dispdec 7596// base address: 0x168 7597#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL 0x18eb 7598#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL_BASE_IDX 2 7599#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_MASK 0x18ec 7600#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_MASK_BASE_IDX 2 7601#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0 0x18ed 7602#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0_BASE_IDX 2 7603#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1 0x18ee 7604#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1_BASE_IDX 2 7605#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2 0x18ef 7606#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2_BASE_IDX 2 7607 7608 7609// addressBlock: dcn_dc_opp_dpg2_dispdec 7610// base address: 0x2d0 7611#define regDPG2_DPG_CONTROL 0x1908 7612#define regDPG2_DPG_CONTROL_BASE_IDX 2 7613#define regDPG2_DPG_RAMP_CONTROL 0x1909 7614#define regDPG2_DPG_RAMP_CONTROL_BASE_IDX 2 7615#define regDPG2_DPG_DIMENSIONS 0x190a 7616#define regDPG2_DPG_DIMENSIONS_BASE_IDX 2 7617#define regDPG2_DPG_COLOUR_R_CR 0x190b 7618#define regDPG2_DPG_COLOUR_R_CR_BASE_IDX 2 7619#define regDPG2_DPG_COLOUR_G_Y 0x190c 7620#define regDPG2_DPG_COLOUR_G_Y_BASE_IDX 2 7621#define regDPG2_DPG_COLOUR_B_CB 0x190d 7622#define regDPG2_DPG_COLOUR_B_CB_BASE_IDX 2 7623#define regDPG2_DPG_OFFSET_SEGMENT 0x190e 7624#define regDPG2_DPG_OFFSET_SEGMENT_BASE_IDX 2 7625#define regDPG2_DPG_STATUS 0x190f 7626#define regDPG2_DPG_STATUS_BASE_IDX 2 7627 7628 7629// addressBlock: dcn_dc_opp_fmt2_dispdec 7630// base address: 0x2d0 7631#define regFMT2_FMT_CLAMP_COMPONENT_R 0x18f0 7632#define regFMT2_FMT_CLAMP_COMPONENT_R_BASE_IDX 2 7633#define regFMT2_FMT_CLAMP_COMPONENT_G 0x18f1 7634#define regFMT2_FMT_CLAMP_COMPONENT_G_BASE_IDX 2 7635#define regFMT2_FMT_CLAMP_COMPONENT_B 0x18f2 7636#define regFMT2_FMT_CLAMP_COMPONENT_B_BASE_IDX 2 7637#define regFMT2_FMT_DYNAMIC_EXP_CNTL 0x18f3 7638#define regFMT2_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2 7639#define regFMT2_FMT_CONTROL 0x18f4 7640#define regFMT2_FMT_CONTROL_BASE_IDX 2 7641#define regFMT2_FMT_BIT_DEPTH_CONTROL 0x18f5 7642#define regFMT2_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2 7643#define regFMT2_FMT_DITHER_RAND_R_SEED 0x18f6 7644#define regFMT2_FMT_DITHER_RAND_R_SEED_BASE_IDX 2 7645#define regFMT2_FMT_DITHER_RAND_G_SEED 0x18f7 7646#define regFMT2_FMT_DITHER_RAND_G_SEED_BASE_IDX 2 7647#define regFMT2_FMT_DITHER_RAND_B_SEED 0x18f8 7648#define regFMT2_FMT_DITHER_RAND_B_SEED_BASE_IDX 2 7649#define regFMT2_FMT_CLAMP_CNTL 0x18f9 7650#define regFMT2_FMT_CLAMP_CNTL_BASE_IDX 2 7651#define regFMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x18fa 7652#define regFMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2 7653#define regFMT2_FMT_MAP420_MEMORY_CONTROL 0x18fb 7654#define regFMT2_FMT_MAP420_MEMORY_CONTROL_BASE_IDX 2 7655#define regFMT2_FMT_422_CONTROL 0x18fd 7656#define regFMT2_FMT_422_CONTROL_BASE_IDX 2 7657 7658 7659// addressBlock: dcn_dc_opp_oppbuf2_dispdec 7660// base address: 0x2d0 7661#define regOPPBUF2_OPPBUF_CONTROL 0x1938 7662#define regOPPBUF2_OPPBUF_CONTROL_BASE_IDX 2 7663#define regOPPBUF2_OPPBUF_3D_PARAMETERS_0 0x1939 7664#define regOPPBUF2_OPPBUF_3D_PARAMETERS_0_BASE_IDX 2 7665#define regOPPBUF2_OPPBUF_3D_PARAMETERS_1 0x193a 7666#define regOPPBUF2_OPPBUF_3D_PARAMETERS_1_BASE_IDX 2 7667#define regOPPBUF2_OPPBUF_CONTROL1 0x193d 7668#define regOPPBUF2_OPPBUF_CONTROL1_BASE_IDX 2 7669 7670 7671// addressBlock: dcn_dc_opp_opp_pipe2_dispdec 7672// base address: 0x2d0 7673#define regOPP_PIPE2_OPP_PIPE_CONTROL 0x1940 7674#define regOPP_PIPE2_OPP_PIPE_CONTROL_BASE_IDX 2 7675 7676 7677// addressBlock: dcn_dc_opp_opp_pipe_crc2_dispdec 7678// base address: 0x2d0 7679#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL 0x1945 7680#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL_BASE_IDX 2 7681#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_MASK 0x1946 7682#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_MASK_BASE_IDX 2 7683#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0 0x1947 7684#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0_BASE_IDX 2 7685#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1 0x1948 7686#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1_BASE_IDX 2 7687#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT2 0x1949 7688#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT2_BASE_IDX 2 7689 7690 7691// addressBlock: dcn_dc_opp_dpg3_dispdec 7692// base address: 0x438 7693#define regDPG3_DPG_CONTROL 0x1962 7694#define regDPG3_DPG_CONTROL_BASE_IDX 2 7695#define regDPG3_DPG_RAMP_CONTROL 0x1963 7696#define regDPG3_DPG_RAMP_CONTROL_BASE_IDX 2 7697#define regDPG3_DPG_DIMENSIONS 0x1964 7698#define regDPG3_DPG_DIMENSIONS_BASE_IDX 2 7699#define regDPG3_DPG_COLOUR_R_CR 0x1965 7700#define regDPG3_DPG_COLOUR_R_CR_BASE_IDX 2 7701#define regDPG3_DPG_COLOUR_G_Y 0x1966 7702#define regDPG3_DPG_COLOUR_G_Y_BASE_IDX 2 7703#define regDPG3_DPG_COLOUR_B_CB 0x1967 7704#define regDPG3_DPG_COLOUR_B_CB_BASE_IDX 2 7705#define regDPG3_DPG_OFFSET_SEGMENT 0x1968 7706#define regDPG3_DPG_OFFSET_SEGMENT_BASE_IDX 2 7707#define regDPG3_DPG_STATUS 0x1969 7708#define regDPG3_DPG_STATUS_BASE_IDX 2 7709 7710 7711// addressBlock: dcn_dc_opp_fmt3_dispdec 7712// base address: 0x438 7713#define regFMT3_FMT_CLAMP_COMPONENT_R 0x194a 7714#define regFMT3_FMT_CLAMP_COMPONENT_R_BASE_IDX 2 7715#define regFMT3_FMT_CLAMP_COMPONENT_G 0x194b 7716#define regFMT3_FMT_CLAMP_COMPONENT_G_BASE_IDX 2 7717#define regFMT3_FMT_CLAMP_COMPONENT_B 0x194c 7718#define regFMT3_FMT_CLAMP_COMPONENT_B_BASE_IDX 2 7719#define regFMT3_FMT_DYNAMIC_EXP_CNTL 0x194d 7720#define regFMT3_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2 7721#define regFMT3_FMT_CONTROL 0x194e 7722#define regFMT3_FMT_CONTROL_BASE_IDX 2 7723#define regFMT3_FMT_BIT_DEPTH_CONTROL 0x194f 7724#define regFMT3_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2 7725#define regFMT3_FMT_DITHER_RAND_R_SEED 0x1950 7726#define regFMT3_FMT_DITHER_RAND_R_SEED_BASE_IDX 2 7727#define regFMT3_FMT_DITHER_RAND_G_SEED 0x1951 7728#define regFMT3_FMT_DITHER_RAND_G_SEED_BASE_IDX 2 7729#define regFMT3_FMT_DITHER_RAND_B_SEED 0x1952 7730#define regFMT3_FMT_DITHER_RAND_B_SEED_BASE_IDX 2 7731#define regFMT3_FMT_CLAMP_CNTL 0x1953 7732#define regFMT3_FMT_CLAMP_CNTL_BASE_IDX 2 7733#define regFMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x1954 7734#define regFMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2 7735#define regFMT3_FMT_MAP420_MEMORY_CONTROL 0x1955 7736#define regFMT3_FMT_MAP420_MEMORY_CONTROL_BASE_IDX 2 7737#define regFMT3_FMT_422_CONTROL 0x1957 7738#define regFMT3_FMT_422_CONTROL_BASE_IDX 2 7739 7740 7741// addressBlock: dcn_dc_opp_oppbuf3_dispdec 7742// base address: 0x438 7743#define regOPPBUF3_OPPBUF_CONTROL 0x1992 7744#define regOPPBUF3_OPPBUF_CONTROL_BASE_IDX 2 7745#define regOPPBUF3_OPPBUF_3D_PARAMETERS_0 0x1993 7746#define regOPPBUF3_OPPBUF_3D_PARAMETERS_0_BASE_IDX 2 7747#define regOPPBUF3_OPPBUF_3D_PARAMETERS_1 0x1994 7748#define regOPPBUF3_OPPBUF_3D_PARAMETERS_1_BASE_IDX 2 7749#define regOPPBUF3_OPPBUF_CONTROL1 0x1997 7750#define regOPPBUF3_OPPBUF_CONTROL1_BASE_IDX 2 7751 7752 7753// addressBlock: dcn_dc_opp_opp_pipe3_dispdec 7754// base address: 0x438 7755#define regOPP_PIPE3_OPP_PIPE_CONTROL 0x199a 7756#define regOPP_PIPE3_OPP_PIPE_CONTROL_BASE_IDX 2 7757 7758 7759// addressBlock: dcn_dc_opp_opp_pipe_crc3_dispdec 7760// base address: 0x438 7761#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL 0x199f 7762#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL_BASE_IDX 2 7763#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_MASK 0x19a0 7764#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_MASK_BASE_IDX 2 7765#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0 0x19a1 7766#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0_BASE_IDX 2 7767#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1 0x19a2 7768#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1_BASE_IDX 2 7769#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT2 0x19a3 7770#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT2_BASE_IDX 2 7771 7772 7773// addressBlock: dcn_dc_opp_dscrm0_dispdec 7774// base address: 0x0 7775#define regDSCRM0_DSCRM_DSC_FORWARD_CONFIG 0x1a64 7776#define regDSCRM0_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX 2 7777 7778 7779// addressBlock: dcn_dc_opp_dscrm1_dispdec 7780// base address: 0x4 7781#define regDSCRM1_DSCRM_DSC_FORWARD_CONFIG 0x1a65 7782#define regDSCRM1_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX 2 7783 7784 7785// addressBlock: dcn_dc_opp_dscrm2_dispdec 7786// base address: 0x8 7787#define regDSCRM2_DSCRM_DSC_FORWARD_CONFIG 0x1a66 7788#define regDSCRM2_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX 2 7789 7790 7791// addressBlock: dcn_dc_opp_dscrm3_dispdec 7792// base address: 0xc 7793#define regDSCRM3_DSCRM_DSC_FORWARD_CONFIG 0x1a67 7794#define regDSCRM3_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX 2 7795 7796 7797// addressBlock: dcn_dc_opp_opp_top_dispdec 7798// base address: 0x0 7799#define regOPP_TOP_CLK_CONTROL 0x1a5e 7800#define regOPP_TOP_CLK_CONTROL_BASE_IDX 2 7801#define regOPP_ABM_CONTROL 0x1a60 7802#define regOPP_ABM_CONTROL_BASE_IDX 2 7803 7804 7805// addressBlock: dcn_dc_optc_odm0_dispdec 7806// base address: 0x0 7807#define regODM0_OPTC_INPUT_GLOBAL_CONTROL 0x1aca 7808#define regODM0_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX 2 7809#define regODM0_OPTC_DATA_SOURCE_SELECT 0x1acb 7810#define regODM0_OPTC_DATA_SOURCE_SELECT_BASE_IDX 2 7811#define regODM0_OPTC_DATA_FORMAT_CONTROL 0x1acc 7812#define regODM0_OPTC_DATA_FORMAT_CONTROL_BASE_IDX 2 7813#define regODM0_OPTC_BYTES_PER_PIXEL 0x1acd 7814#define regODM0_OPTC_BYTES_PER_PIXEL_BASE_IDX 2 7815#define regODM0_OPTC_WIDTH_CONTROL 0x1ace 7816#define regODM0_OPTC_WIDTH_CONTROL_BASE_IDX 2 7817#define regODM0_OPTC_INPUT_CLOCK_CONTROL 0x1acf 7818#define regODM0_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX 2 7819#define regODM0_OPTC_MEMORY_CONFIG 0x1ad0 7820#define regODM0_OPTC_MEMORY_CONFIG_BASE_IDX 2 7821#define regODM0_OPTC_INPUT_SPARE_REGISTER 0x1ad1 7822#define regODM0_OPTC_INPUT_SPARE_REGISTER_BASE_IDX 2 7823 7824 7825// addressBlock: dcn_dc_optc_odm1_dispdec 7826// base address: 0x40 7827#define regODM1_OPTC_INPUT_GLOBAL_CONTROL 0x1ada 7828#define regODM1_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX 2 7829#define regODM1_OPTC_DATA_SOURCE_SELECT 0x1adb 7830#define regODM1_OPTC_DATA_SOURCE_SELECT_BASE_IDX 2 7831#define regODM1_OPTC_DATA_FORMAT_CONTROL 0x1adc 7832#define regODM1_OPTC_DATA_FORMAT_CONTROL_BASE_IDX 2 7833#define regODM1_OPTC_BYTES_PER_PIXEL 0x1add 7834#define regODM1_OPTC_BYTES_PER_PIXEL_BASE_IDX 2 7835#define regODM1_OPTC_WIDTH_CONTROL 0x1ade 7836#define regODM1_OPTC_WIDTH_CONTROL_BASE_IDX 2 7837#define regODM1_OPTC_INPUT_CLOCK_CONTROL 0x1adf 7838#define regODM1_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX 2 7839#define regODM1_OPTC_MEMORY_CONFIG 0x1ae0 7840#define regODM1_OPTC_MEMORY_CONFIG_BASE_IDX 2 7841#define regODM1_OPTC_INPUT_SPARE_REGISTER 0x1ae1 7842#define regODM1_OPTC_INPUT_SPARE_REGISTER_BASE_IDX 2 7843 7844 7845// addressBlock: dcn_dc_optc_odm2_dispdec 7846// base address: 0x80 7847#define regODM2_OPTC_INPUT_GLOBAL_CONTROL 0x1aea 7848#define regODM2_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX 2 7849#define regODM2_OPTC_DATA_SOURCE_SELECT 0x1aeb 7850#define regODM2_OPTC_DATA_SOURCE_SELECT_BASE_IDX 2 7851#define regODM2_OPTC_DATA_FORMAT_CONTROL 0x1aec 7852#define regODM2_OPTC_DATA_FORMAT_CONTROL_BASE_IDX 2 7853#define regODM2_OPTC_BYTES_PER_PIXEL 0x1aed 7854#define regODM2_OPTC_BYTES_PER_PIXEL_BASE_IDX 2 7855#define regODM2_OPTC_WIDTH_CONTROL 0x1aee 7856#define regODM2_OPTC_WIDTH_CONTROL_BASE_IDX 2 7857#define regODM2_OPTC_INPUT_CLOCK_CONTROL 0x1aef 7858#define regODM2_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX 2 7859#define regODM2_OPTC_MEMORY_CONFIG 0x1af0 7860#define regODM2_OPTC_MEMORY_CONFIG_BASE_IDX 2 7861#define regODM2_OPTC_INPUT_SPARE_REGISTER 0x1af1 7862#define regODM2_OPTC_INPUT_SPARE_REGISTER_BASE_IDX 2 7863 7864 7865// addressBlock: dcn_dc_optc_odm3_dispdec 7866// base address: 0xc0 7867#define regODM3_OPTC_INPUT_GLOBAL_CONTROL 0x1afa 7868#define regODM3_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX 2 7869#define regODM3_OPTC_DATA_SOURCE_SELECT 0x1afb 7870#define regODM3_OPTC_DATA_SOURCE_SELECT_BASE_IDX 2 7871#define regODM3_OPTC_DATA_FORMAT_CONTROL 0x1afc 7872#define regODM3_OPTC_DATA_FORMAT_CONTROL_BASE_IDX 2 7873#define regODM3_OPTC_BYTES_PER_PIXEL 0x1afd 7874#define regODM3_OPTC_BYTES_PER_PIXEL_BASE_IDX 2 7875#define regODM3_OPTC_WIDTH_CONTROL 0x1afe 7876#define regODM3_OPTC_WIDTH_CONTROL_BASE_IDX 2 7877#define regODM3_OPTC_INPUT_CLOCK_CONTROL 0x1aff 7878#define regODM3_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX 2 7879#define regODM3_OPTC_MEMORY_CONFIG 0x1b00 7880#define regODM3_OPTC_MEMORY_CONFIG_BASE_IDX 2 7881#define regODM3_OPTC_INPUT_SPARE_REGISTER 0x1b01 7882#define regODM3_OPTC_INPUT_SPARE_REGISTER_BASE_IDX 2 7883 7884 7885// addressBlock: dcn_dc_optc_otg0_dispdec 7886// base address: 0x0 7887#define regOTG0_OTG_H_TOTAL 0x1b2a 7888#define regOTG0_OTG_H_TOTAL_BASE_IDX 2 7889#define regOTG0_OTG_H_BLANK_START_END 0x1b2b 7890#define regOTG0_OTG_H_BLANK_START_END_BASE_IDX 2 7891#define regOTG0_OTG_H_SYNC_A 0x1b2c 7892#define regOTG0_OTG_H_SYNC_A_BASE_IDX 2 7893#define regOTG0_OTG_H_SYNC_A_CNTL 0x1b2d 7894#define regOTG0_OTG_H_SYNC_A_CNTL_BASE_IDX 2 7895#define regOTG0_OTG_H_TIMING_CNTL 0x1b2e 7896#define regOTG0_OTG_H_TIMING_CNTL_BASE_IDX 2 7897#define regOTG0_OTG_V_TOTAL 0x1b2f 7898#define regOTG0_OTG_V_TOTAL_BASE_IDX 2 7899#define regOTG0_OTG_V_TOTAL_MIN 0x1b30 7900#define regOTG0_OTG_V_TOTAL_MIN_BASE_IDX 2 7901#define regOTG0_OTG_V_TOTAL_MAX 0x1b31 7902#define regOTG0_OTG_V_TOTAL_MAX_BASE_IDX 2 7903#define regOTG0_OTG_V_TOTAL_MID 0x1b32 7904#define regOTG0_OTG_V_TOTAL_MID_BASE_IDX 2 7905#define regOTG0_OTG_V_TOTAL_CONTROL 0x1b33 7906#define regOTG0_OTG_V_TOTAL_CONTROL_BASE_IDX 2 7907#define regOTG0_OTG_V_TOTAL_INT_STATUS 0x1b34 7908#define regOTG0_OTG_V_TOTAL_INT_STATUS_BASE_IDX 2 7909#define regOTG0_OTG_VSYNC_NOM_INT_STATUS 0x1b35 7910#define regOTG0_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX 2 7911#define regOTG0_OTG_V_BLANK_START_END 0x1b36 7912#define regOTG0_OTG_V_BLANK_START_END_BASE_IDX 2 7913#define regOTG0_OTG_V_SYNC_A 0x1b37 7914#define regOTG0_OTG_V_SYNC_A_BASE_IDX 2 7915#define regOTG0_OTG_V_SYNC_A_CNTL 0x1b38 7916#define regOTG0_OTG_V_SYNC_A_CNTL_BASE_IDX 2 7917#define regOTG0_OTG_TRIGA_CNTL 0x1b39 7918#define regOTG0_OTG_TRIGA_CNTL_BASE_IDX 2 7919#define regOTG0_OTG_TRIGA_MANUAL_TRIG 0x1b3a 7920#define regOTG0_OTG_TRIGA_MANUAL_TRIG_BASE_IDX 2 7921#define regOTG0_OTG_TRIGB_CNTL 0x1b3b 7922#define regOTG0_OTG_TRIGB_CNTL_BASE_IDX 2 7923#define regOTG0_OTG_TRIGB_MANUAL_TRIG 0x1b3c 7924#define regOTG0_OTG_TRIGB_MANUAL_TRIG_BASE_IDX 2 7925#define regOTG0_OTG_FORCE_COUNT_NOW_CNTL 0x1b3d 7926#define regOTG0_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX 2 7927#define regOTG0_OTG_FLOW_CONTROL 0x1b3e 7928#define regOTG0_OTG_FLOW_CONTROL_BASE_IDX 2 7929#define regOTG0_OTG_STEREO_FORCE_NEXT_EYE 0x1b3f 7930#define regOTG0_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX 2 7931#define regOTG0_OTG_CONTROL 0x1b41 7932#define regOTG0_OTG_CONTROL_BASE_IDX 2 7933#define regOTG0_OTG_INTERLACE_CONTROL 0x1b44 7934#define regOTG0_OTG_INTERLACE_CONTROL_BASE_IDX 2 7935#define regOTG0_OTG_INTERLACE_STATUS 0x1b45 7936#define regOTG0_OTG_INTERLACE_STATUS_BASE_IDX 2 7937#define regOTG0_OTG_PIXEL_DATA_READBACK0 0x1b47 7938#define regOTG0_OTG_PIXEL_DATA_READBACK0_BASE_IDX 2 7939#define regOTG0_OTG_PIXEL_DATA_READBACK1 0x1b48 7940#define regOTG0_OTG_PIXEL_DATA_READBACK1_BASE_IDX 2 7941#define regOTG0_OTG_STATUS 0x1b49 7942#define regOTG0_OTG_STATUS_BASE_IDX 2 7943#define regOTG0_OTG_STATUS_POSITION 0x1b4a 7944#define regOTG0_OTG_STATUS_POSITION_BASE_IDX 2 7945#define regOTG0_OTG_NOM_VERT_POSITION 0x1b4b 7946#define regOTG0_OTG_NOM_VERT_POSITION_BASE_IDX 2 7947#define regOTG0_OTG_STATUS_FRAME_COUNT 0x1b4c 7948#define regOTG0_OTG_STATUS_FRAME_COUNT_BASE_IDX 2 7949#define regOTG0_OTG_STATUS_VF_COUNT 0x1b4d 7950#define regOTG0_OTG_STATUS_VF_COUNT_BASE_IDX 2 7951#define regOTG0_OTG_STATUS_HV_COUNT 0x1b4e 7952#define regOTG0_OTG_STATUS_HV_COUNT_BASE_IDX 2 7953#define regOTG0_OTG_COUNT_CONTROL 0x1b4f 7954#define regOTG0_OTG_COUNT_CONTROL_BASE_IDX 2 7955#define regOTG0_OTG_COUNT_RESET 0x1b50 7956#define regOTG0_OTG_COUNT_RESET_BASE_IDX 2 7957#define regOTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1b51 7958#define regOTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2 7959#define regOTG0_OTG_VERT_SYNC_CONTROL 0x1b52 7960#define regOTG0_OTG_VERT_SYNC_CONTROL_BASE_IDX 2 7961#define regOTG0_OTG_STEREO_STATUS 0x1b53 7962#define regOTG0_OTG_STEREO_STATUS_BASE_IDX 2 7963#define regOTG0_OTG_STEREO_CONTROL 0x1b54 7964#define regOTG0_OTG_STEREO_CONTROL_BASE_IDX 2 7965#define regOTG0_OTG_SNAPSHOT_STATUS 0x1b55 7966#define regOTG0_OTG_SNAPSHOT_STATUS_BASE_IDX 2 7967#define regOTG0_OTG_SNAPSHOT_CONTROL 0x1b56 7968#define regOTG0_OTG_SNAPSHOT_CONTROL_BASE_IDX 2 7969#define regOTG0_OTG_SNAPSHOT_POSITION 0x1b57 7970#define regOTG0_OTG_SNAPSHOT_POSITION_BASE_IDX 2 7971#define regOTG0_OTG_SNAPSHOT_FRAME 0x1b58 7972#define regOTG0_OTG_SNAPSHOT_FRAME_BASE_IDX 2 7973#define regOTG0_OTG_INTERRUPT_CONTROL 0x1b59 7974#define regOTG0_OTG_INTERRUPT_CONTROL_BASE_IDX 2 7975#define regOTG0_OTG_UPDATE_LOCK 0x1b5a 7976#define regOTG0_OTG_UPDATE_LOCK_BASE_IDX 2 7977#define regOTG0_OTG_DOUBLE_BUFFER_CONTROL 0x1b5b 7978#define regOTG0_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 7979#define regOTG0_OTG_MASTER_EN 0x1b5c 7980#define regOTG0_OTG_MASTER_EN_BASE_IDX 2 7981#define regOTG0_OTG_VERTICAL_INTERRUPT0_POSITION 0x1b62 7982#define regOTG0_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2 7983#define regOTG0_OTG_VERTICAL_INTERRUPT0_CONTROL 0x1b63 7984#define regOTG0_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2 7985#define regOTG0_OTG_VERTICAL_INTERRUPT1_POSITION 0x1b64 7986#define regOTG0_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2 7987#define regOTG0_OTG_VERTICAL_INTERRUPT1_CONTROL 0x1b65 7988#define regOTG0_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2 7989#define regOTG0_OTG_VERTICAL_INTERRUPT2_POSITION 0x1b66 7990#define regOTG0_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2 7991#define regOTG0_OTG_VERTICAL_INTERRUPT2_CONTROL 0x1b67 7992#define regOTG0_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2 7993#define regOTG0_OTG_CRC_CNTL 0x1b68 7994#define regOTG0_OTG_CRC_CNTL_BASE_IDX 2 7995#define regOTG0_OTG_CRC0_WINDOWA_X_CONTROL 0x1b69 7996#define regOTG0_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2 7997#define regOTG0_OTG_CRC0_WINDOWA_Y_CONTROL 0x1b6a 7998#define regOTG0_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2 7999#define regOTG0_OTG_CRC0_WINDOWB_X_CONTROL 0x1b6b 8000#define regOTG0_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2 8001#define regOTG0_OTG_CRC0_WINDOWB_Y_CONTROL 0x1b6c 8002#define regOTG0_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2 8003#define regOTG0_OTG_CRC0_DATA_RG 0x1b6d 8004#define regOTG0_OTG_CRC0_DATA_RG_BASE_IDX 2 8005#define regOTG0_OTG_CRC0_DATA_B 0x1b6e 8006#define regOTG0_OTG_CRC0_DATA_B_BASE_IDX 2 8007#define regOTG0_OTG_CRC1_WINDOWA_X_CONTROL 0x1b6f 8008#define regOTG0_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2 8009#define regOTG0_OTG_CRC1_WINDOWA_Y_CONTROL 0x1b70 8010#define regOTG0_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2 8011#define regOTG0_OTG_CRC1_WINDOWB_X_CONTROL 0x1b71 8012#define regOTG0_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2 8013#define regOTG0_OTG_CRC1_WINDOWB_Y_CONTROL 0x1b72 8014#define regOTG0_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2 8015#define regOTG0_OTG_CRC1_DATA_RG 0x1b73 8016#define regOTG0_OTG_CRC1_DATA_RG_BASE_IDX 2 8017#define regOTG0_OTG_CRC1_DATA_B 0x1b74 8018#define regOTG0_OTG_CRC1_DATA_B_BASE_IDX 2 8019#define regOTG0_OTG_CRC2_DATA_RG 0x1b75 8020#define regOTG0_OTG_CRC2_DATA_RG_BASE_IDX 2 8021#define regOTG0_OTG_CRC2_DATA_B 0x1b76 8022#define regOTG0_OTG_CRC2_DATA_B_BASE_IDX 2 8023#define regOTG0_OTG_CRC3_DATA_RG 0x1b77 8024#define regOTG0_OTG_CRC3_DATA_RG_BASE_IDX 2 8025#define regOTG0_OTG_CRC3_DATA_B 0x1b78 8026#define regOTG0_OTG_CRC3_DATA_B_BASE_IDX 2 8027#define regOTG0_OTG_CRC_SIG_RED_GREEN_MASK 0x1b79 8028#define regOTG0_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2 8029#define regOTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK 0x1b7a 8030#define regOTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2 8031#define regOTG0_OTG_STATIC_SCREEN_CONTROL 0x1b81 8032#define regOTG0_OTG_STATIC_SCREEN_CONTROL_BASE_IDX 2 8033#define regOTG0_OTG_3D_STRUCTURE_CONTROL 0x1b82 8034#define regOTG0_OTG_3D_STRUCTURE_CONTROL_BASE_IDX 2 8035#define regOTG0_OTG_GSL_VSYNC_GAP 0x1b83 8036#define regOTG0_OTG_GSL_VSYNC_GAP_BASE_IDX 2 8037#define regOTG0_OTG_MASTER_UPDATE_MODE 0x1b84 8038#define regOTG0_OTG_MASTER_UPDATE_MODE_BASE_IDX 2 8039#define regOTG0_OTG_CLOCK_CONTROL 0x1b85 8040#define regOTG0_OTG_CLOCK_CONTROL_BASE_IDX 2 8041#define regOTG0_OTG_VSTARTUP_PARAM 0x1b86 8042#define regOTG0_OTG_VSTARTUP_PARAM_BASE_IDX 2 8043#define regOTG0_OTG_VUPDATE_PARAM 0x1b87 8044#define regOTG0_OTG_VUPDATE_PARAM_BASE_IDX 2 8045#define regOTG0_OTG_VREADY_PARAM 0x1b88 8046#define regOTG0_OTG_VREADY_PARAM_BASE_IDX 2 8047#define regOTG0_OTG_GLOBAL_SYNC_STATUS 0x1b89 8048#define regOTG0_OTG_GLOBAL_SYNC_STATUS_BASE_IDX 2 8049#define regOTG0_OTG_MASTER_UPDATE_LOCK 0x1b8a 8050#define regOTG0_OTG_MASTER_UPDATE_LOCK_BASE_IDX 2 8051#define regOTG0_OTG_GSL_CONTROL 0x1b8b 8052#define regOTG0_OTG_GSL_CONTROL_BASE_IDX 2 8053#define regOTG0_OTG_GSL_WINDOW_X 0x1b8c 8054#define regOTG0_OTG_GSL_WINDOW_X_BASE_IDX 2 8055#define regOTG0_OTG_GSL_WINDOW_Y 0x1b8d 8056#define regOTG0_OTG_GSL_WINDOW_Y_BASE_IDX 2 8057#define regOTG0_OTG_VUPDATE_KEEPOUT 0x1b8e 8058#define regOTG0_OTG_VUPDATE_KEEPOUT_BASE_IDX 2 8059#define regOTG0_OTG_GLOBAL_CONTROL0 0x1b8f 8060#define regOTG0_OTG_GLOBAL_CONTROL0_BASE_IDX 2 8061#define regOTG0_OTG_GLOBAL_CONTROL1 0x1b90 8062#define regOTG0_OTG_GLOBAL_CONTROL1_BASE_IDX 2 8063#define regOTG0_OTG_GLOBAL_CONTROL2 0x1b91 8064#define regOTG0_OTG_GLOBAL_CONTROL2_BASE_IDX 2 8065#define regOTG0_OTG_GLOBAL_CONTROL3 0x1b92 8066#define regOTG0_OTG_GLOBAL_CONTROL3_BASE_IDX 2 8067#define regOTG0_OTG_GLOBAL_CONTROL4 0x1b93 8068#define regOTG0_OTG_GLOBAL_CONTROL4_BASE_IDX 2 8069#define regOTG0_OTG_TRIG_MANUAL_CONTROL 0x1b94 8070#define regOTG0_OTG_TRIG_MANUAL_CONTROL_BASE_IDX 2 8071#define regOTG0_OTG_MANUAL_FLOW_CONTROL 0x1b95 8072#define regOTG0_OTG_MANUAL_FLOW_CONTROL_BASE_IDX 2 8073#define regOTG0_OTG_DRR_TIMING_INT_STATUS 0x1b96 8074#define regOTG0_OTG_DRR_TIMING_INT_STATUS_BASE_IDX 2 8075#define regOTG0_OTG_DRR_V_TOTAL_REACH_RANGE 0x1b97 8076#define regOTG0_OTG_DRR_V_TOTAL_REACH_RANGE_BASE_IDX 2 8077#define regOTG0_OTG_DRR_V_TOTAL_CHANGE 0x1b98 8078#define regOTG0_OTG_DRR_V_TOTAL_CHANGE_BASE_IDX 2 8079#define regOTG0_OTG_DRR_TRIGGER_WINDOW 0x1b99 8080#define regOTG0_OTG_DRR_TRIGGER_WINDOW_BASE_IDX 2 8081#define regOTG0_OTG_DRR_CONTROL 0x1b9a 8082#define regOTG0_OTG_DRR_CONTROL_BASE_IDX 2 8083#define regOTG0_OTG_M_CONST_DTO0 0x1b9b 8084#define regOTG0_OTG_M_CONST_DTO0_BASE_IDX 2 8085#define regOTG0_OTG_M_CONST_DTO1 0x1b9c 8086#define regOTG0_OTG_M_CONST_DTO1_BASE_IDX 2 8087#define regOTG0_OTG_REQUEST_CONTROL 0x1b9d 8088#define regOTG0_OTG_REQUEST_CONTROL_BASE_IDX 2 8089#define regOTG0_OTG_DSC_START_POSITION 0x1b9e 8090#define regOTG0_OTG_DSC_START_POSITION_BASE_IDX 2 8091#define regOTG0_OTG_PIPE_UPDATE_STATUS 0x1b9f 8092#define regOTG0_OTG_PIPE_UPDATE_STATUS_BASE_IDX 2 8093#define regOTG0_OTG_SPARE_REGISTER 0x1ba1 8094#define regOTG0_OTG_SPARE_REGISTER_BASE_IDX 2 8095 8096 8097// addressBlock: dcn_dc_optc_otg1_dispdec 8098// base address: 0x200 8099#define regOTG1_OTG_H_TOTAL 0x1baa 8100#define regOTG1_OTG_H_TOTAL_BASE_IDX 2 8101#define regOTG1_OTG_H_BLANK_START_END 0x1bab 8102#define regOTG1_OTG_H_BLANK_START_END_BASE_IDX 2 8103#define regOTG1_OTG_H_SYNC_A 0x1bac 8104#define regOTG1_OTG_H_SYNC_A_BASE_IDX 2 8105#define regOTG1_OTG_H_SYNC_A_CNTL 0x1bad 8106#define regOTG1_OTG_H_SYNC_A_CNTL_BASE_IDX 2 8107#define regOTG1_OTG_H_TIMING_CNTL 0x1bae 8108#define regOTG1_OTG_H_TIMING_CNTL_BASE_IDX 2 8109#define regOTG1_OTG_V_TOTAL 0x1baf 8110#define regOTG1_OTG_V_TOTAL_BASE_IDX 2 8111#define regOTG1_OTG_V_TOTAL_MIN 0x1bb0 8112#define regOTG1_OTG_V_TOTAL_MIN_BASE_IDX 2 8113#define regOTG1_OTG_V_TOTAL_MAX 0x1bb1 8114#define regOTG1_OTG_V_TOTAL_MAX_BASE_IDX 2 8115#define regOTG1_OTG_V_TOTAL_MID 0x1bb2 8116#define regOTG1_OTG_V_TOTAL_MID_BASE_IDX 2 8117#define regOTG1_OTG_V_TOTAL_CONTROL 0x1bb3 8118#define regOTG1_OTG_V_TOTAL_CONTROL_BASE_IDX 2 8119#define regOTG1_OTG_V_TOTAL_INT_STATUS 0x1bb4 8120#define regOTG1_OTG_V_TOTAL_INT_STATUS_BASE_IDX 2 8121#define regOTG1_OTG_VSYNC_NOM_INT_STATUS 0x1bb5 8122#define regOTG1_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX 2 8123#define regOTG1_OTG_V_BLANK_START_END 0x1bb6 8124#define regOTG1_OTG_V_BLANK_START_END_BASE_IDX 2 8125#define regOTG1_OTG_V_SYNC_A 0x1bb7 8126#define regOTG1_OTG_V_SYNC_A_BASE_IDX 2 8127#define regOTG1_OTG_V_SYNC_A_CNTL 0x1bb8 8128#define regOTG1_OTG_V_SYNC_A_CNTL_BASE_IDX 2 8129#define regOTG1_OTG_TRIGA_CNTL 0x1bb9 8130#define regOTG1_OTG_TRIGA_CNTL_BASE_IDX 2 8131#define regOTG1_OTG_TRIGA_MANUAL_TRIG 0x1bba 8132#define regOTG1_OTG_TRIGA_MANUAL_TRIG_BASE_IDX 2 8133#define regOTG1_OTG_TRIGB_CNTL 0x1bbb 8134#define regOTG1_OTG_TRIGB_CNTL_BASE_IDX 2 8135#define regOTG1_OTG_TRIGB_MANUAL_TRIG 0x1bbc 8136#define regOTG1_OTG_TRIGB_MANUAL_TRIG_BASE_IDX 2 8137#define regOTG1_OTG_FORCE_COUNT_NOW_CNTL 0x1bbd 8138#define regOTG1_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX 2 8139#define regOTG1_OTG_FLOW_CONTROL 0x1bbe 8140#define regOTG1_OTG_FLOW_CONTROL_BASE_IDX 2 8141#define regOTG1_OTG_STEREO_FORCE_NEXT_EYE 0x1bbf 8142#define regOTG1_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX 2 8143#define regOTG1_OTG_CONTROL 0x1bc1 8144#define regOTG1_OTG_CONTROL_BASE_IDX 2 8145#define regOTG1_OTG_INTERLACE_CONTROL 0x1bc4 8146#define regOTG1_OTG_INTERLACE_CONTROL_BASE_IDX 2 8147#define regOTG1_OTG_INTERLACE_STATUS 0x1bc5 8148#define regOTG1_OTG_INTERLACE_STATUS_BASE_IDX 2 8149#define regOTG1_OTG_PIXEL_DATA_READBACK0 0x1bc7 8150#define regOTG1_OTG_PIXEL_DATA_READBACK0_BASE_IDX 2 8151#define regOTG1_OTG_PIXEL_DATA_READBACK1 0x1bc8 8152#define regOTG1_OTG_PIXEL_DATA_READBACK1_BASE_IDX 2 8153#define regOTG1_OTG_STATUS 0x1bc9 8154#define regOTG1_OTG_STATUS_BASE_IDX 2 8155#define regOTG1_OTG_STATUS_POSITION 0x1bca 8156#define regOTG1_OTG_STATUS_POSITION_BASE_IDX 2 8157#define regOTG1_OTG_NOM_VERT_POSITION 0x1bcb 8158#define regOTG1_OTG_NOM_VERT_POSITION_BASE_IDX 2 8159#define regOTG1_OTG_STATUS_FRAME_COUNT 0x1bcc 8160#define regOTG1_OTG_STATUS_FRAME_COUNT_BASE_IDX 2 8161#define regOTG1_OTG_STATUS_VF_COUNT 0x1bcd 8162#define regOTG1_OTG_STATUS_VF_COUNT_BASE_IDX 2 8163#define regOTG1_OTG_STATUS_HV_COUNT 0x1bce 8164#define regOTG1_OTG_STATUS_HV_COUNT_BASE_IDX 2 8165#define regOTG1_OTG_COUNT_CONTROL 0x1bcf 8166#define regOTG1_OTG_COUNT_CONTROL_BASE_IDX 2 8167#define regOTG1_OTG_COUNT_RESET 0x1bd0 8168#define regOTG1_OTG_COUNT_RESET_BASE_IDX 2 8169#define regOTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1bd1 8170#define regOTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2 8171#define regOTG1_OTG_VERT_SYNC_CONTROL 0x1bd2 8172#define regOTG1_OTG_VERT_SYNC_CONTROL_BASE_IDX 2 8173#define regOTG1_OTG_STEREO_STATUS 0x1bd3 8174#define regOTG1_OTG_STEREO_STATUS_BASE_IDX 2 8175#define regOTG1_OTG_STEREO_CONTROL 0x1bd4 8176#define regOTG1_OTG_STEREO_CONTROL_BASE_IDX 2 8177#define regOTG1_OTG_SNAPSHOT_STATUS 0x1bd5 8178#define regOTG1_OTG_SNAPSHOT_STATUS_BASE_IDX 2 8179#define regOTG1_OTG_SNAPSHOT_CONTROL 0x1bd6 8180#define regOTG1_OTG_SNAPSHOT_CONTROL_BASE_IDX 2 8181#define regOTG1_OTG_SNAPSHOT_POSITION 0x1bd7 8182#define regOTG1_OTG_SNAPSHOT_POSITION_BASE_IDX 2 8183#define regOTG1_OTG_SNAPSHOT_FRAME 0x1bd8 8184#define regOTG1_OTG_SNAPSHOT_FRAME_BASE_IDX 2 8185#define regOTG1_OTG_INTERRUPT_CONTROL 0x1bd9 8186#define regOTG1_OTG_INTERRUPT_CONTROL_BASE_IDX 2 8187#define regOTG1_OTG_UPDATE_LOCK 0x1bda 8188#define regOTG1_OTG_UPDATE_LOCK_BASE_IDX 2 8189#define regOTG1_OTG_DOUBLE_BUFFER_CONTROL 0x1bdb 8190#define regOTG1_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 8191#define regOTG1_OTG_MASTER_EN 0x1bdc 8192#define regOTG1_OTG_MASTER_EN_BASE_IDX 2 8193#define regOTG1_OTG_VERTICAL_INTERRUPT0_POSITION 0x1be2 8194#define regOTG1_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2 8195#define regOTG1_OTG_VERTICAL_INTERRUPT0_CONTROL 0x1be3 8196#define regOTG1_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2 8197#define regOTG1_OTG_VERTICAL_INTERRUPT1_POSITION 0x1be4 8198#define regOTG1_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2 8199#define regOTG1_OTG_VERTICAL_INTERRUPT1_CONTROL 0x1be5 8200#define regOTG1_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2 8201#define regOTG1_OTG_VERTICAL_INTERRUPT2_POSITION 0x1be6 8202#define regOTG1_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2 8203#define regOTG1_OTG_VERTICAL_INTERRUPT2_CONTROL 0x1be7 8204#define regOTG1_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2 8205#define regOTG1_OTG_CRC_CNTL 0x1be8 8206#define regOTG1_OTG_CRC_CNTL_BASE_IDX 2 8207#define regOTG1_OTG_CRC0_WINDOWA_X_CONTROL 0x1be9 8208#define regOTG1_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2 8209#define regOTG1_OTG_CRC0_WINDOWA_Y_CONTROL 0x1bea 8210#define regOTG1_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2 8211#define regOTG1_OTG_CRC0_WINDOWB_X_CONTROL 0x1beb 8212#define regOTG1_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2 8213#define regOTG1_OTG_CRC0_WINDOWB_Y_CONTROL 0x1bec 8214#define regOTG1_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2 8215#define regOTG1_OTG_CRC0_DATA_RG 0x1bed 8216#define regOTG1_OTG_CRC0_DATA_RG_BASE_IDX 2 8217#define regOTG1_OTG_CRC0_DATA_B 0x1bee 8218#define regOTG1_OTG_CRC0_DATA_B_BASE_IDX 2 8219#define regOTG1_OTG_CRC1_WINDOWA_X_CONTROL 0x1bef 8220#define regOTG1_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2 8221#define regOTG1_OTG_CRC1_WINDOWA_Y_CONTROL 0x1bf0 8222#define regOTG1_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2 8223#define regOTG1_OTG_CRC1_WINDOWB_X_CONTROL 0x1bf1 8224#define regOTG1_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2 8225#define regOTG1_OTG_CRC1_WINDOWB_Y_CONTROL 0x1bf2 8226#define regOTG1_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2 8227#define regOTG1_OTG_CRC1_DATA_RG 0x1bf3 8228#define regOTG1_OTG_CRC1_DATA_RG_BASE_IDX 2 8229#define regOTG1_OTG_CRC1_DATA_B 0x1bf4 8230#define regOTG1_OTG_CRC1_DATA_B_BASE_IDX 2 8231#define regOTG1_OTG_CRC2_DATA_RG 0x1bf5 8232#define regOTG1_OTG_CRC2_DATA_RG_BASE_IDX 2 8233#define regOTG1_OTG_CRC2_DATA_B 0x1bf6 8234#define regOTG1_OTG_CRC2_DATA_B_BASE_IDX 2 8235#define regOTG1_OTG_CRC3_DATA_RG 0x1bf7 8236#define regOTG1_OTG_CRC3_DATA_RG_BASE_IDX 2 8237#define regOTG1_OTG_CRC3_DATA_B 0x1bf8 8238#define regOTG1_OTG_CRC3_DATA_B_BASE_IDX 2 8239#define regOTG1_OTG_CRC_SIG_RED_GREEN_MASK 0x1bf9 8240#define regOTG1_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2 8241#define regOTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK 0x1bfa 8242#define regOTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2 8243#define regOTG1_OTG_STATIC_SCREEN_CONTROL 0x1c01 8244#define regOTG1_OTG_STATIC_SCREEN_CONTROL_BASE_IDX 2 8245#define regOTG1_OTG_3D_STRUCTURE_CONTROL 0x1c02 8246#define regOTG1_OTG_3D_STRUCTURE_CONTROL_BASE_IDX 2 8247#define regOTG1_OTG_GSL_VSYNC_GAP 0x1c03 8248#define regOTG1_OTG_GSL_VSYNC_GAP_BASE_IDX 2 8249#define regOTG1_OTG_MASTER_UPDATE_MODE 0x1c04 8250#define regOTG1_OTG_MASTER_UPDATE_MODE_BASE_IDX 2 8251#define regOTG1_OTG_CLOCK_CONTROL 0x1c05 8252#define regOTG1_OTG_CLOCK_CONTROL_BASE_IDX 2 8253#define regOTG1_OTG_VSTARTUP_PARAM 0x1c06 8254#define regOTG1_OTG_VSTARTUP_PARAM_BASE_IDX 2 8255#define regOTG1_OTG_VUPDATE_PARAM 0x1c07 8256#define regOTG1_OTG_VUPDATE_PARAM_BASE_IDX 2 8257#define regOTG1_OTG_VREADY_PARAM 0x1c08 8258#define regOTG1_OTG_VREADY_PARAM_BASE_IDX 2 8259#define regOTG1_OTG_GLOBAL_SYNC_STATUS 0x1c09 8260#define regOTG1_OTG_GLOBAL_SYNC_STATUS_BASE_IDX 2 8261#define regOTG1_OTG_MASTER_UPDATE_LOCK 0x1c0a 8262#define regOTG1_OTG_MASTER_UPDATE_LOCK_BASE_IDX 2 8263#define regOTG1_OTG_GSL_CONTROL 0x1c0b 8264#define regOTG1_OTG_GSL_CONTROL_BASE_IDX 2 8265#define regOTG1_OTG_GSL_WINDOW_X 0x1c0c 8266#define regOTG1_OTG_GSL_WINDOW_X_BASE_IDX 2 8267#define regOTG1_OTG_GSL_WINDOW_Y 0x1c0d 8268#define regOTG1_OTG_GSL_WINDOW_Y_BASE_IDX 2 8269#define regOTG1_OTG_VUPDATE_KEEPOUT 0x1c0e 8270#define regOTG1_OTG_VUPDATE_KEEPOUT_BASE_IDX 2 8271#define regOTG1_OTG_GLOBAL_CONTROL0 0x1c0f 8272#define regOTG1_OTG_GLOBAL_CONTROL0_BASE_IDX 2 8273#define regOTG1_OTG_GLOBAL_CONTROL1 0x1c10 8274#define regOTG1_OTG_GLOBAL_CONTROL1_BASE_IDX 2 8275#define regOTG1_OTG_GLOBAL_CONTROL2 0x1c11 8276#define regOTG1_OTG_GLOBAL_CONTROL2_BASE_IDX 2 8277#define regOTG1_OTG_GLOBAL_CONTROL3 0x1c12 8278#define regOTG1_OTG_GLOBAL_CONTROL3_BASE_IDX 2 8279#define regOTG1_OTG_GLOBAL_CONTROL4 0x1c13 8280#define regOTG1_OTG_GLOBAL_CONTROL4_BASE_IDX 2 8281#define regOTG1_OTG_TRIG_MANUAL_CONTROL 0x1c14 8282#define regOTG1_OTG_TRIG_MANUAL_CONTROL_BASE_IDX 2 8283#define regOTG1_OTG_MANUAL_FLOW_CONTROL 0x1c15 8284#define regOTG1_OTG_MANUAL_FLOW_CONTROL_BASE_IDX 2 8285#define regOTG1_OTG_DRR_TIMING_INT_STATUS 0x1c16 8286#define regOTG1_OTG_DRR_TIMING_INT_STATUS_BASE_IDX 2 8287#define regOTG1_OTG_DRR_V_TOTAL_REACH_RANGE 0x1c17 8288#define regOTG1_OTG_DRR_V_TOTAL_REACH_RANGE_BASE_IDX 2 8289#define regOTG1_OTG_DRR_V_TOTAL_CHANGE 0x1c18 8290#define regOTG1_OTG_DRR_V_TOTAL_CHANGE_BASE_IDX 2 8291#define regOTG1_OTG_DRR_TRIGGER_WINDOW 0x1c19 8292#define regOTG1_OTG_DRR_TRIGGER_WINDOW_BASE_IDX 2 8293#define regOTG1_OTG_DRR_CONTROL 0x1c1a 8294#define regOTG1_OTG_DRR_CONTROL_BASE_IDX 2 8295#define regOTG1_OTG_M_CONST_DTO0 0x1c1b 8296#define regOTG1_OTG_M_CONST_DTO0_BASE_IDX 2 8297#define regOTG1_OTG_M_CONST_DTO1 0x1c1c 8298#define regOTG1_OTG_M_CONST_DTO1_BASE_IDX 2 8299#define regOTG1_OTG_REQUEST_CONTROL 0x1c1d 8300#define regOTG1_OTG_REQUEST_CONTROL_BASE_IDX 2 8301#define regOTG1_OTG_DSC_START_POSITION 0x1c1e 8302#define regOTG1_OTG_DSC_START_POSITION_BASE_IDX 2 8303#define regOTG1_OTG_PIPE_UPDATE_STATUS 0x1c1f 8304#define regOTG1_OTG_PIPE_UPDATE_STATUS_BASE_IDX 2 8305#define regOTG1_OTG_SPARE_REGISTER 0x1c21 8306#define regOTG1_OTG_SPARE_REGISTER_BASE_IDX 2 8307 8308 8309// addressBlock: dcn_dc_optc_otg2_dispdec 8310// base address: 0x400 8311#define regOTG2_OTG_H_TOTAL 0x1c2a 8312#define regOTG2_OTG_H_TOTAL_BASE_IDX 2 8313#define regOTG2_OTG_H_BLANK_START_END 0x1c2b 8314#define regOTG2_OTG_H_BLANK_START_END_BASE_IDX 2 8315#define regOTG2_OTG_H_SYNC_A 0x1c2c 8316#define regOTG2_OTG_H_SYNC_A_BASE_IDX 2 8317#define regOTG2_OTG_H_SYNC_A_CNTL 0x1c2d 8318#define regOTG2_OTG_H_SYNC_A_CNTL_BASE_IDX 2 8319#define regOTG2_OTG_H_TIMING_CNTL 0x1c2e 8320#define regOTG2_OTG_H_TIMING_CNTL_BASE_IDX 2 8321#define regOTG2_OTG_V_TOTAL 0x1c2f 8322#define regOTG2_OTG_V_TOTAL_BASE_IDX 2 8323#define regOTG2_OTG_V_TOTAL_MIN 0x1c30 8324#define regOTG2_OTG_V_TOTAL_MIN_BASE_IDX 2 8325#define regOTG2_OTG_V_TOTAL_MAX 0x1c31 8326#define regOTG2_OTG_V_TOTAL_MAX_BASE_IDX 2 8327#define regOTG2_OTG_V_TOTAL_MID 0x1c32 8328#define regOTG2_OTG_V_TOTAL_MID_BASE_IDX 2 8329#define regOTG2_OTG_V_TOTAL_CONTROL 0x1c33 8330#define regOTG2_OTG_V_TOTAL_CONTROL_BASE_IDX 2 8331#define regOTG2_OTG_V_TOTAL_INT_STATUS 0x1c34 8332#define regOTG2_OTG_V_TOTAL_INT_STATUS_BASE_IDX 2 8333#define regOTG2_OTG_VSYNC_NOM_INT_STATUS 0x1c35 8334#define regOTG2_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX 2 8335#define regOTG2_OTG_V_BLANK_START_END 0x1c36 8336#define regOTG2_OTG_V_BLANK_START_END_BASE_IDX 2 8337#define regOTG2_OTG_V_SYNC_A 0x1c37 8338#define regOTG2_OTG_V_SYNC_A_BASE_IDX 2 8339#define regOTG2_OTG_V_SYNC_A_CNTL 0x1c38 8340#define regOTG2_OTG_V_SYNC_A_CNTL_BASE_IDX 2 8341#define regOTG2_OTG_TRIGA_CNTL 0x1c39 8342#define regOTG2_OTG_TRIGA_CNTL_BASE_IDX 2 8343#define regOTG2_OTG_TRIGA_MANUAL_TRIG 0x1c3a 8344#define regOTG2_OTG_TRIGA_MANUAL_TRIG_BASE_IDX 2 8345#define regOTG2_OTG_TRIGB_CNTL 0x1c3b 8346#define regOTG2_OTG_TRIGB_CNTL_BASE_IDX 2 8347#define regOTG2_OTG_TRIGB_MANUAL_TRIG 0x1c3c 8348#define regOTG2_OTG_TRIGB_MANUAL_TRIG_BASE_IDX 2 8349#define regOTG2_OTG_FORCE_COUNT_NOW_CNTL 0x1c3d 8350#define regOTG2_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX 2 8351#define regOTG2_OTG_FLOW_CONTROL 0x1c3e 8352#define regOTG2_OTG_FLOW_CONTROL_BASE_IDX 2 8353#define regOTG2_OTG_STEREO_FORCE_NEXT_EYE 0x1c3f 8354#define regOTG2_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX 2 8355#define regOTG2_OTG_CONTROL 0x1c41 8356#define regOTG2_OTG_CONTROL_BASE_IDX 2 8357#define regOTG2_OTG_INTERLACE_CONTROL 0x1c44 8358#define regOTG2_OTG_INTERLACE_CONTROL_BASE_IDX 2 8359#define regOTG2_OTG_INTERLACE_STATUS 0x1c45 8360#define regOTG2_OTG_INTERLACE_STATUS_BASE_IDX 2 8361#define regOTG2_OTG_PIXEL_DATA_READBACK0 0x1c47 8362#define regOTG2_OTG_PIXEL_DATA_READBACK0_BASE_IDX 2 8363#define regOTG2_OTG_PIXEL_DATA_READBACK1 0x1c48 8364#define regOTG2_OTG_PIXEL_DATA_READBACK1_BASE_IDX 2 8365#define regOTG2_OTG_STATUS 0x1c49 8366#define regOTG2_OTG_STATUS_BASE_IDX 2 8367#define regOTG2_OTG_STATUS_POSITION 0x1c4a 8368#define regOTG2_OTG_STATUS_POSITION_BASE_IDX 2 8369#define regOTG2_OTG_NOM_VERT_POSITION 0x1c4b 8370#define regOTG2_OTG_NOM_VERT_POSITION_BASE_IDX 2 8371#define regOTG2_OTG_STATUS_FRAME_COUNT 0x1c4c 8372#define regOTG2_OTG_STATUS_FRAME_COUNT_BASE_IDX 2 8373#define regOTG2_OTG_STATUS_VF_COUNT 0x1c4d 8374#define regOTG2_OTG_STATUS_VF_COUNT_BASE_IDX 2 8375#define regOTG2_OTG_STATUS_HV_COUNT 0x1c4e 8376#define regOTG2_OTG_STATUS_HV_COUNT_BASE_IDX 2 8377#define regOTG2_OTG_COUNT_CONTROL 0x1c4f 8378#define regOTG2_OTG_COUNT_CONTROL_BASE_IDX 2 8379#define regOTG2_OTG_COUNT_RESET 0x1c50 8380#define regOTG2_OTG_COUNT_RESET_BASE_IDX 2 8381#define regOTG2_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1c51 8382#define regOTG2_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2 8383#define regOTG2_OTG_VERT_SYNC_CONTROL 0x1c52 8384#define regOTG2_OTG_VERT_SYNC_CONTROL_BASE_IDX 2 8385#define regOTG2_OTG_STEREO_STATUS 0x1c53 8386#define regOTG2_OTG_STEREO_STATUS_BASE_IDX 2 8387#define regOTG2_OTG_STEREO_CONTROL 0x1c54 8388#define regOTG2_OTG_STEREO_CONTROL_BASE_IDX 2 8389#define regOTG2_OTG_SNAPSHOT_STATUS 0x1c55 8390#define regOTG2_OTG_SNAPSHOT_STATUS_BASE_IDX 2 8391#define regOTG2_OTG_SNAPSHOT_CONTROL 0x1c56 8392#define regOTG2_OTG_SNAPSHOT_CONTROL_BASE_IDX 2 8393#define regOTG2_OTG_SNAPSHOT_POSITION 0x1c57 8394#define regOTG2_OTG_SNAPSHOT_POSITION_BASE_IDX 2 8395#define regOTG2_OTG_SNAPSHOT_FRAME 0x1c58 8396#define regOTG2_OTG_SNAPSHOT_FRAME_BASE_IDX 2 8397#define regOTG2_OTG_INTERRUPT_CONTROL 0x1c59 8398#define regOTG2_OTG_INTERRUPT_CONTROL_BASE_IDX 2 8399#define regOTG2_OTG_UPDATE_LOCK 0x1c5a 8400#define regOTG2_OTG_UPDATE_LOCK_BASE_IDX 2 8401#define regOTG2_OTG_DOUBLE_BUFFER_CONTROL 0x1c5b 8402#define regOTG2_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 8403#define regOTG2_OTG_MASTER_EN 0x1c5c 8404#define regOTG2_OTG_MASTER_EN_BASE_IDX 2 8405#define regOTG2_OTG_VERTICAL_INTERRUPT0_POSITION 0x1c62 8406#define regOTG2_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2 8407#define regOTG2_OTG_VERTICAL_INTERRUPT0_CONTROL 0x1c63 8408#define regOTG2_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2 8409#define regOTG2_OTG_VERTICAL_INTERRUPT1_POSITION 0x1c64 8410#define regOTG2_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2 8411#define regOTG2_OTG_VERTICAL_INTERRUPT1_CONTROL 0x1c65 8412#define regOTG2_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2 8413#define regOTG2_OTG_VERTICAL_INTERRUPT2_POSITION 0x1c66 8414#define regOTG2_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2 8415#define regOTG2_OTG_VERTICAL_INTERRUPT2_CONTROL 0x1c67 8416#define regOTG2_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2 8417#define regOTG2_OTG_CRC_CNTL 0x1c68 8418#define regOTG2_OTG_CRC_CNTL_BASE_IDX 2 8419#define regOTG2_OTG_CRC0_WINDOWA_X_CONTROL 0x1c69 8420#define regOTG2_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2 8421#define regOTG2_OTG_CRC0_WINDOWA_Y_CONTROL 0x1c6a 8422#define regOTG2_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2 8423#define regOTG2_OTG_CRC0_WINDOWB_X_CONTROL 0x1c6b 8424#define regOTG2_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2 8425#define regOTG2_OTG_CRC0_WINDOWB_Y_CONTROL 0x1c6c 8426#define regOTG2_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2 8427#define regOTG2_OTG_CRC0_DATA_RG 0x1c6d 8428#define regOTG2_OTG_CRC0_DATA_RG_BASE_IDX 2 8429#define regOTG2_OTG_CRC0_DATA_B 0x1c6e 8430#define regOTG2_OTG_CRC0_DATA_B_BASE_IDX 2 8431#define regOTG2_OTG_CRC1_WINDOWA_X_CONTROL 0x1c6f 8432#define regOTG2_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2 8433#define regOTG2_OTG_CRC1_WINDOWA_Y_CONTROL 0x1c70 8434#define regOTG2_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2 8435#define regOTG2_OTG_CRC1_WINDOWB_X_CONTROL 0x1c71 8436#define regOTG2_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2 8437#define regOTG2_OTG_CRC1_WINDOWB_Y_CONTROL 0x1c72 8438#define regOTG2_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2 8439#define regOTG2_OTG_CRC1_DATA_RG 0x1c73 8440#define regOTG2_OTG_CRC1_DATA_RG_BASE_IDX 2 8441#define regOTG2_OTG_CRC1_DATA_B 0x1c74 8442#define regOTG2_OTG_CRC1_DATA_B_BASE_IDX 2 8443#define regOTG2_OTG_CRC2_DATA_RG 0x1c75 8444#define regOTG2_OTG_CRC2_DATA_RG_BASE_IDX 2 8445#define regOTG2_OTG_CRC2_DATA_B 0x1c76 8446#define regOTG2_OTG_CRC2_DATA_B_BASE_IDX 2 8447#define regOTG2_OTG_CRC3_DATA_RG 0x1c77 8448#define regOTG2_OTG_CRC3_DATA_RG_BASE_IDX 2 8449#define regOTG2_OTG_CRC3_DATA_B 0x1c78 8450#define regOTG2_OTG_CRC3_DATA_B_BASE_IDX 2 8451#define regOTG2_OTG_CRC_SIG_RED_GREEN_MASK 0x1c79 8452#define regOTG2_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2 8453#define regOTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK 0x1c7a 8454#define regOTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2 8455#define regOTG2_OTG_STATIC_SCREEN_CONTROL 0x1c81 8456#define regOTG2_OTG_STATIC_SCREEN_CONTROL_BASE_IDX 2 8457#define regOTG2_OTG_3D_STRUCTURE_CONTROL 0x1c82 8458#define regOTG2_OTG_3D_STRUCTURE_CONTROL_BASE_IDX 2 8459#define regOTG2_OTG_GSL_VSYNC_GAP 0x1c83 8460#define regOTG2_OTG_GSL_VSYNC_GAP_BASE_IDX 2 8461#define regOTG2_OTG_MASTER_UPDATE_MODE 0x1c84 8462#define regOTG2_OTG_MASTER_UPDATE_MODE_BASE_IDX 2 8463#define regOTG2_OTG_CLOCK_CONTROL 0x1c85 8464#define regOTG2_OTG_CLOCK_CONTROL_BASE_IDX 2 8465#define regOTG2_OTG_VSTARTUP_PARAM 0x1c86 8466#define regOTG2_OTG_VSTARTUP_PARAM_BASE_IDX 2 8467#define regOTG2_OTG_VUPDATE_PARAM 0x1c87 8468#define regOTG2_OTG_VUPDATE_PARAM_BASE_IDX 2 8469#define regOTG2_OTG_VREADY_PARAM 0x1c88 8470#define regOTG2_OTG_VREADY_PARAM_BASE_IDX 2 8471#define regOTG2_OTG_GLOBAL_SYNC_STATUS 0x1c89 8472#define regOTG2_OTG_GLOBAL_SYNC_STATUS_BASE_IDX 2 8473#define regOTG2_OTG_MASTER_UPDATE_LOCK 0x1c8a 8474#define regOTG2_OTG_MASTER_UPDATE_LOCK_BASE_IDX 2 8475#define regOTG2_OTG_GSL_CONTROL 0x1c8b 8476#define regOTG2_OTG_GSL_CONTROL_BASE_IDX 2 8477#define regOTG2_OTG_GSL_WINDOW_X 0x1c8c 8478#define regOTG2_OTG_GSL_WINDOW_X_BASE_IDX 2 8479#define regOTG2_OTG_GSL_WINDOW_Y 0x1c8d 8480#define regOTG2_OTG_GSL_WINDOW_Y_BASE_IDX 2 8481#define regOTG2_OTG_VUPDATE_KEEPOUT 0x1c8e 8482#define regOTG2_OTG_VUPDATE_KEEPOUT_BASE_IDX 2 8483#define regOTG2_OTG_GLOBAL_CONTROL0 0x1c8f 8484#define regOTG2_OTG_GLOBAL_CONTROL0_BASE_IDX 2 8485#define regOTG2_OTG_GLOBAL_CONTROL1 0x1c90 8486#define regOTG2_OTG_GLOBAL_CONTROL1_BASE_IDX 2 8487#define regOTG2_OTG_GLOBAL_CONTROL2 0x1c91 8488#define regOTG2_OTG_GLOBAL_CONTROL2_BASE_IDX 2 8489#define regOTG2_OTG_GLOBAL_CONTROL3 0x1c92 8490#define regOTG2_OTG_GLOBAL_CONTROL3_BASE_IDX 2 8491#define regOTG2_OTG_GLOBAL_CONTROL4 0x1c93 8492#define regOTG2_OTG_GLOBAL_CONTROL4_BASE_IDX 2 8493#define regOTG2_OTG_TRIG_MANUAL_CONTROL 0x1c94 8494#define regOTG2_OTG_TRIG_MANUAL_CONTROL_BASE_IDX 2 8495#define regOTG2_OTG_MANUAL_FLOW_CONTROL 0x1c95 8496#define regOTG2_OTG_MANUAL_FLOW_CONTROL_BASE_IDX 2 8497#define regOTG2_OTG_DRR_TIMING_INT_STATUS 0x1c96 8498#define regOTG2_OTG_DRR_TIMING_INT_STATUS_BASE_IDX 2 8499#define regOTG2_OTG_DRR_V_TOTAL_REACH_RANGE 0x1c97 8500#define regOTG2_OTG_DRR_V_TOTAL_REACH_RANGE_BASE_IDX 2 8501#define regOTG2_OTG_DRR_V_TOTAL_CHANGE 0x1c98 8502#define regOTG2_OTG_DRR_V_TOTAL_CHANGE_BASE_IDX 2 8503#define regOTG2_OTG_DRR_TRIGGER_WINDOW 0x1c99 8504#define regOTG2_OTG_DRR_TRIGGER_WINDOW_BASE_IDX 2 8505#define regOTG2_OTG_DRR_CONTROL 0x1c9a 8506#define regOTG2_OTG_DRR_CONTROL_BASE_IDX 2 8507#define regOTG2_OTG_M_CONST_DTO0 0x1c9b 8508#define regOTG2_OTG_M_CONST_DTO0_BASE_IDX 2 8509#define regOTG2_OTG_M_CONST_DTO1 0x1c9c 8510#define regOTG2_OTG_M_CONST_DTO1_BASE_IDX 2 8511#define regOTG2_OTG_REQUEST_CONTROL 0x1c9d 8512#define regOTG2_OTG_REQUEST_CONTROL_BASE_IDX 2 8513#define regOTG2_OTG_DSC_START_POSITION 0x1c9e 8514#define regOTG2_OTG_DSC_START_POSITION_BASE_IDX 2 8515#define regOTG2_OTG_PIPE_UPDATE_STATUS 0x1c9f 8516#define regOTG2_OTG_PIPE_UPDATE_STATUS_BASE_IDX 2 8517#define regOTG2_OTG_SPARE_REGISTER 0x1ca1 8518#define regOTG2_OTG_SPARE_REGISTER_BASE_IDX 2 8519 8520 8521// addressBlock: dcn_dc_optc_otg3_dispdec 8522// base address: 0x600 8523#define regOTG3_OTG_H_TOTAL 0x1caa 8524#define regOTG3_OTG_H_TOTAL_BASE_IDX 2 8525#define regOTG3_OTG_H_BLANK_START_END 0x1cab 8526#define regOTG3_OTG_H_BLANK_START_END_BASE_IDX 2 8527#define regOTG3_OTG_H_SYNC_A 0x1cac 8528#define regOTG3_OTG_H_SYNC_A_BASE_IDX 2 8529#define regOTG3_OTG_H_SYNC_A_CNTL 0x1cad 8530#define regOTG3_OTG_H_SYNC_A_CNTL_BASE_IDX 2 8531#define regOTG3_OTG_H_TIMING_CNTL 0x1cae 8532#define regOTG3_OTG_H_TIMING_CNTL_BASE_IDX 2 8533#define regOTG3_OTG_V_TOTAL 0x1caf 8534#define regOTG3_OTG_V_TOTAL_BASE_IDX 2 8535#define regOTG3_OTG_V_TOTAL_MIN 0x1cb0 8536#define regOTG3_OTG_V_TOTAL_MIN_BASE_IDX 2 8537#define regOTG3_OTG_V_TOTAL_MAX 0x1cb1 8538#define regOTG3_OTG_V_TOTAL_MAX_BASE_IDX 2 8539#define regOTG3_OTG_V_TOTAL_MID 0x1cb2 8540#define regOTG3_OTG_V_TOTAL_MID_BASE_IDX 2 8541#define regOTG3_OTG_V_TOTAL_CONTROL 0x1cb3 8542#define regOTG3_OTG_V_TOTAL_CONTROL_BASE_IDX 2 8543#define regOTG3_OTG_V_TOTAL_INT_STATUS 0x1cb4 8544#define regOTG3_OTG_V_TOTAL_INT_STATUS_BASE_IDX 2 8545#define regOTG3_OTG_VSYNC_NOM_INT_STATUS 0x1cb5 8546#define regOTG3_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX 2 8547#define regOTG3_OTG_V_BLANK_START_END 0x1cb6 8548#define regOTG3_OTG_V_BLANK_START_END_BASE_IDX 2 8549#define regOTG3_OTG_V_SYNC_A 0x1cb7 8550#define regOTG3_OTG_V_SYNC_A_BASE_IDX 2 8551#define regOTG3_OTG_V_SYNC_A_CNTL 0x1cb8 8552#define regOTG3_OTG_V_SYNC_A_CNTL_BASE_IDX 2 8553#define regOTG3_OTG_TRIGA_CNTL 0x1cb9 8554#define regOTG3_OTG_TRIGA_CNTL_BASE_IDX 2 8555#define regOTG3_OTG_TRIGA_MANUAL_TRIG 0x1cba 8556#define regOTG3_OTG_TRIGA_MANUAL_TRIG_BASE_IDX 2 8557#define regOTG3_OTG_TRIGB_CNTL 0x1cbb 8558#define regOTG3_OTG_TRIGB_CNTL_BASE_IDX 2 8559#define regOTG3_OTG_TRIGB_MANUAL_TRIG 0x1cbc 8560#define regOTG3_OTG_TRIGB_MANUAL_TRIG_BASE_IDX 2 8561#define regOTG3_OTG_FORCE_COUNT_NOW_CNTL 0x1cbd 8562#define regOTG3_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX 2 8563#define regOTG3_OTG_FLOW_CONTROL 0x1cbe 8564#define regOTG3_OTG_FLOW_CONTROL_BASE_IDX 2 8565#define regOTG3_OTG_STEREO_FORCE_NEXT_EYE 0x1cbf 8566#define regOTG3_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX 2 8567#define regOTG3_OTG_CONTROL 0x1cc1 8568#define regOTG3_OTG_CONTROL_BASE_IDX 2 8569#define regOTG3_OTG_INTERLACE_CONTROL 0x1cc4 8570#define regOTG3_OTG_INTERLACE_CONTROL_BASE_IDX 2 8571#define regOTG3_OTG_INTERLACE_STATUS 0x1cc5 8572#define regOTG3_OTG_INTERLACE_STATUS_BASE_IDX 2 8573#define regOTG3_OTG_PIXEL_DATA_READBACK0 0x1cc7 8574#define regOTG3_OTG_PIXEL_DATA_READBACK0_BASE_IDX 2 8575#define regOTG3_OTG_PIXEL_DATA_READBACK1 0x1cc8 8576#define regOTG3_OTG_PIXEL_DATA_READBACK1_BASE_IDX 2 8577#define regOTG3_OTG_STATUS 0x1cc9 8578#define regOTG3_OTG_STATUS_BASE_IDX 2 8579#define regOTG3_OTG_STATUS_POSITION 0x1cca 8580#define regOTG3_OTG_STATUS_POSITION_BASE_IDX 2 8581#define regOTG3_OTG_NOM_VERT_POSITION 0x1ccb 8582#define regOTG3_OTG_NOM_VERT_POSITION_BASE_IDX 2 8583#define regOTG3_OTG_STATUS_FRAME_COUNT 0x1ccc 8584#define regOTG3_OTG_STATUS_FRAME_COUNT_BASE_IDX 2 8585#define regOTG3_OTG_STATUS_VF_COUNT 0x1ccd 8586#define regOTG3_OTG_STATUS_VF_COUNT_BASE_IDX 2 8587#define regOTG3_OTG_STATUS_HV_COUNT 0x1cce 8588#define regOTG3_OTG_STATUS_HV_COUNT_BASE_IDX 2 8589#define regOTG3_OTG_COUNT_CONTROL 0x1ccf 8590#define regOTG3_OTG_COUNT_CONTROL_BASE_IDX 2 8591#define regOTG3_OTG_COUNT_RESET 0x1cd0 8592#define regOTG3_OTG_COUNT_RESET_BASE_IDX 2 8593#define regOTG3_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1cd1 8594#define regOTG3_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2 8595#define regOTG3_OTG_VERT_SYNC_CONTROL 0x1cd2 8596#define regOTG3_OTG_VERT_SYNC_CONTROL_BASE_IDX 2 8597#define regOTG3_OTG_STEREO_STATUS 0x1cd3 8598#define regOTG3_OTG_STEREO_STATUS_BASE_IDX 2 8599#define regOTG3_OTG_STEREO_CONTROL 0x1cd4 8600#define regOTG3_OTG_STEREO_CONTROL_BASE_IDX 2 8601#define regOTG3_OTG_SNAPSHOT_STATUS 0x1cd5 8602#define regOTG3_OTG_SNAPSHOT_STATUS_BASE_IDX 2 8603#define regOTG3_OTG_SNAPSHOT_CONTROL 0x1cd6 8604#define regOTG3_OTG_SNAPSHOT_CONTROL_BASE_IDX 2 8605#define regOTG3_OTG_SNAPSHOT_POSITION 0x1cd7 8606#define regOTG3_OTG_SNAPSHOT_POSITION_BASE_IDX 2 8607#define regOTG3_OTG_SNAPSHOT_FRAME 0x1cd8 8608#define regOTG3_OTG_SNAPSHOT_FRAME_BASE_IDX 2 8609#define regOTG3_OTG_INTERRUPT_CONTROL 0x1cd9 8610#define regOTG3_OTG_INTERRUPT_CONTROL_BASE_IDX 2 8611#define regOTG3_OTG_UPDATE_LOCK 0x1cda 8612#define regOTG3_OTG_UPDATE_LOCK_BASE_IDX 2 8613#define regOTG3_OTG_DOUBLE_BUFFER_CONTROL 0x1cdb 8614#define regOTG3_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 8615#define regOTG3_OTG_MASTER_EN 0x1cdc 8616#define regOTG3_OTG_MASTER_EN_BASE_IDX 2 8617#define regOTG3_OTG_VERTICAL_INTERRUPT0_POSITION 0x1ce2 8618#define regOTG3_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2 8619#define regOTG3_OTG_VERTICAL_INTERRUPT0_CONTROL 0x1ce3 8620#define regOTG3_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2 8621#define regOTG3_OTG_VERTICAL_INTERRUPT1_POSITION 0x1ce4 8622#define regOTG3_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2 8623#define regOTG3_OTG_VERTICAL_INTERRUPT1_CONTROL 0x1ce5 8624#define regOTG3_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2 8625#define regOTG3_OTG_VERTICAL_INTERRUPT2_POSITION 0x1ce6 8626#define regOTG3_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2 8627#define regOTG3_OTG_VERTICAL_INTERRUPT2_CONTROL 0x1ce7 8628#define regOTG3_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2 8629#define regOTG3_OTG_CRC_CNTL 0x1ce8 8630#define regOTG3_OTG_CRC_CNTL_BASE_IDX 2 8631#define regOTG3_OTG_CRC0_WINDOWA_X_CONTROL 0x1ce9 8632#define regOTG3_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2 8633#define regOTG3_OTG_CRC0_WINDOWA_Y_CONTROL 0x1cea 8634#define regOTG3_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2 8635#define regOTG3_OTG_CRC0_WINDOWB_X_CONTROL 0x1ceb 8636#define regOTG3_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2 8637#define regOTG3_OTG_CRC0_WINDOWB_Y_CONTROL 0x1cec 8638#define regOTG3_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2 8639#define regOTG3_OTG_CRC0_DATA_RG 0x1ced 8640#define regOTG3_OTG_CRC0_DATA_RG_BASE_IDX 2 8641#define regOTG3_OTG_CRC0_DATA_B 0x1cee 8642#define regOTG3_OTG_CRC0_DATA_B_BASE_IDX 2 8643#define regOTG3_OTG_CRC1_WINDOWA_X_CONTROL 0x1cef 8644#define regOTG3_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2 8645#define regOTG3_OTG_CRC1_WINDOWA_Y_CONTROL 0x1cf0 8646#define regOTG3_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2 8647#define regOTG3_OTG_CRC1_WINDOWB_X_CONTROL 0x1cf1 8648#define regOTG3_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2 8649#define regOTG3_OTG_CRC1_WINDOWB_Y_CONTROL 0x1cf2 8650#define regOTG3_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2 8651#define regOTG3_OTG_CRC1_DATA_RG 0x1cf3 8652#define regOTG3_OTG_CRC1_DATA_RG_BASE_IDX 2 8653#define regOTG3_OTG_CRC1_DATA_B 0x1cf4 8654#define regOTG3_OTG_CRC1_DATA_B_BASE_IDX 2 8655#define regOTG3_OTG_CRC2_DATA_RG 0x1cf5 8656#define regOTG3_OTG_CRC2_DATA_RG_BASE_IDX 2 8657#define regOTG3_OTG_CRC2_DATA_B 0x1cf6 8658#define regOTG3_OTG_CRC2_DATA_B_BASE_IDX 2 8659#define regOTG3_OTG_CRC3_DATA_RG 0x1cf7 8660#define regOTG3_OTG_CRC3_DATA_RG_BASE_IDX 2 8661#define regOTG3_OTG_CRC3_DATA_B 0x1cf8 8662#define regOTG3_OTG_CRC3_DATA_B_BASE_IDX 2 8663#define regOTG3_OTG_CRC_SIG_RED_GREEN_MASK 0x1cf9 8664#define regOTG3_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2 8665#define regOTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK 0x1cfa 8666#define regOTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2 8667#define regOTG3_OTG_STATIC_SCREEN_CONTROL 0x1d01 8668#define regOTG3_OTG_STATIC_SCREEN_CONTROL_BASE_IDX 2 8669#define regOTG3_OTG_3D_STRUCTURE_CONTROL 0x1d02 8670#define regOTG3_OTG_3D_STRUCTURE_CONTROL_BASE_IDX 2 8671#define regOTG3_OTG_GSL_VSYNC_GAP 0x1d03 8672#define regOTG3_OTG_GSL_VSYNC_GAP_BASE_IDX 2 8673#define regOTG3_OTG_MASTER_UPDATE_MODE 0x1d04 8674#define regOTG3_OTG_MASTER_UPDATE_MODE_BASE_IDX 2 8675#define regOTG3_OTG_CLOCK_CONTROL 0x1d05 8676#define regOTG3_OTG_CLOCK_CONTROL_BASE_IDX 2 8677#define regOTG3_OTG_VSTARTUP_PARAM 0x1d06 8678#define regOTG3_OTG_VSTARTUP_PARAM_BASE_IDX 2 8679#define regOTG3_OTG_VUPDATE_PARAM 0x1d07 8680#define regOTG3_OTG_VUPDATE_PARAM_BASE_IDX 2 8681#define regOTG3_OTG_VREADY_PARAM 0x1d08 8682#define regOTG3_OTG_VREADY_PARAM_BASE_IDX 2 8683#define regOTG3_OTG_GLOBAL_SYNC_STATUS 0x1d09 8684#define regOTG3_OTG_GLOBAL_SYNC_STATUS_BASE_IDX 2 8685#define regOTG3_OTG_MASTER_UPDATE_LOCK 0x1d0a 8686#define regOTG3_OTG_MASTER_UPDATE_LOCK_BASE_IDX 2 8687#define regOTG3_OTG_GSL_CONTROL 0x1d0b 8688#define regOTG3_OTG_GSL_CONTROL_BASE_IDX 2 8689#define regOTG3_OTG_GSL_WINDOW_X 0x1d0c 8690#define regOTG3_OTG_GSL_WINDOW_X_BASE_IDX 2 8691#define regOTG3_OTG_GSL_WINDOW_Y 0x1d0d 8692#define regOTG3_OTG_GSL_WINDOW_Y_BASE_IDX 2 8693#define regOTG3_OTG_VUPDATE_KEEPOUT 0x1d0e 8694#define regOTG3_OTG_VUPDATE_KEEPOUT_BASE_IDX 2 8695#define regOTG3_OTG_GLOBAL_CONTROL0 0x1d0f 8696#define regOTG3_OTG_GLOBAL_CONTROL0_BASE_IDX 2 8697#define regOTG3_OTG_GLOBAL_CONTROL1 0x1d10 8698#define regOTG3_OTG_GLOBAL_CONTROL1_BASE_IDX 2 8699#define regOTG3_OTG_GLOBAL_CONTROL2 0x1d11 8700#define regOTG3_OTG_GLOBAL_CONTROL2_BASE_IDX 2 8701#define regOTG3_OTG_GLOBAL_CONTROL3 0x1d12 8702#define regOTG3_OTG_GLOBAL_CONTROL3_BASE_IDX 2 8703#define regOTG3_OTG_GLOBAL_CONTROL4 0x1d13 8704#define regOTG3_OTG_GLOBAL_CONTROL4_BASE_IDX 2 8705#define regOTG3_OTG_TRIG_MANUAL_CONTROL 0x1d14 8706#define regOTG3_OTG_TRIG_MANUAL_CONTROL_BASE_IDX 2 8707#define regOTG3_OTG_MANUAL_FLOW_CONTROL 0x1d15 8708#define regOTG3_OTG_MANUAL_FLOW_CONTROL_BASE_IDX 2 8709#define regOTG3_OTG_DRR_TIMING_INT_STATUS 0x1d16 8710#define regOTG3_OTG_DRR_TIMING_INT_STATUS_BASE_IDX 2 8711#define regOTG3_OTG_DRR_V_TOTAL_REACH_RANGE 0x1d17 8712#define regOTG3_OTG_DRR_V_TOTAL_REACH_RANGE_BASE_IDX 2 8713#define regOTG3_OTG_DRR_V_TOTAL_CHANGE 0x1d18 8714#define regOTG3_OTG_DRR_V_TOTAL_CHANGE_BASE_IDX 2 8715#define regOTG3_OTG_DRR_TRIGGER_WINDOW 0x1d19 8716#define regOTG3_OTG_DRR_TRIGGER_WINDOW_BASE_IDX 2 8717#define regOTG3_OTG_DRR_CONTROL 0x1d1a 8718#define regOTG3_OTG_DRR_CONTROL_BASE_IDX 2 8719#define regOTG3_OTG_M_CONST_DTO0 0x1d1b 8720#define regOTG3_OTG_M_CONST_DTO0_BASE_IDX 2 8721#define regOTG3_OTG_M_CONST_DTO1 0x1d1c 8722#define regOTG3_OTG_M_CONST_DTO1_BASE_IDX 2 8723#define regOTG3_OTG_REQUEST_CONTROL 0x1d1d 8724#define regOTG3_OTG_REQUEST_CONTROL_BASE_IDX 2 8725#define regOTG3_OTG_DSC_START_POSITION 0x1d1e 8726#define regOTG3_OTG_DSC_START_POSITION_BASE_IDX 2 8727#define regOTG3_OTG_PIPE_UPDATE_STATUS 0x1d1f 8728#define regOTG3_OTG_PIPE_UPDATE_STATUS_BASE_IDX 2 8729#define regOTG3_OTG_SPARE_REGISTER 0x1d21 8730#define regOTG3_OTG_SPARE_REGISTER_BASE_IDX 2 8731 8732 8733// addressBlock: dcn_dc_optc_optc_misc_dispdec 8734// base address: 0x0 8735#define regGSL_SOURCE_SELECT 0x1e2b 8736#define regGSL_SOURCE_SELECT_BASE_IDX 2 8737#define regOPTC_CLOCK_CONTROL 0x1e2c 8738#define regOPTC_CLOCK_CONTROL_BASE_IDX 2 8739#define regODM_MEM_PWR_CTRL 0x1e2d 8740#define regODM_MEM_PWR_CTRL_BASE_IDX 2 8741#define regODM_MEM_PWR_CTRL3 0x1e2f 8742#define regODM_MEM_PWR_CTRL3_BASE_IDX 2 8743#define regODM_MEM_PWR_STATUS 0x1e30 8744#define regODM_MEM_PWR_STATUS_BASE_IDX 2 8745#define regOPTC_MISC_SPARE_REGISTER 0x1e31 8746#define regOPTC_MISC_SPARE_REGISTER_BASE_IDX 2 8747 8748 8749// addressBlock: dcn_dc_dio_hpd0_dispdec 8750// base address: 0x0 8751#define regHPD0_DC_HPD_INT_STATUS 0x1f14 8752#define regHPD0_DC_HPD_INT_STATUS_BASE_IDX 2 8753#define regHPD0_DC_HPD_INT_CONTROL 0x1f15 8754#define regHPD0_DC_HPD_INT_CONTROL_BASE_IDX 2 8755#define regHPD0_DC_HPD_CONTROL 0x1f16 8756#define regHPD0_DC_HPD_CONTROL_BASE_IDX 2 8757#define regHPD0_DC_HPD_FAST_TRAIN_CNTL 0x1f17 8758#define regHPD0_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2 8759#define regHPD0_DC_HPD_TOGGLE_FILT_CNTL 0x1f18 8760#define regHPD0_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2 8761 8762 8763// addressBlock: dcn_dc_dio_hpd1_dispdec 8764// base address: 0x20 8765#define regHPD1_DC_HPD_INT_STATUS 0x1f1c 8766#define regHPD1_DC_HPD_INT_STATUS_BASE_IDX 2 8767#define regHPD1_DC_HPD_INT_CONTROL 0x1f1d 8768#define regHPD1_DC_HPD_INT_CONTROL_BASE_IDX 2 8769#define regHPD1_DC_HPD_CONTROL 0x1f1e 8770#define regHPD1_DC_HPD_CONTROL_BASE_IDX 2 8771#define regHPD1_DC_HPD_FAST_TRAIN_CNTL 0x1f1f 8772#define regHPD1_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2 8773#define regHPD1_DC_HPD_TOGGLE_FILT_CNTL 0x1f20 8774#define regHPD1_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2 8775 8776 8777// addressBlock: dcn_dc_dio_hpd2_dispdec 8778// base address: 0x40 8779#define regHPD2_DC_HPD_INT_STATUS 0x1f24 8780#define regHPD2_DC_HPD_INT_STATUS_BASE_IDX 2 8781#define regHPD2_DC_HPD_INT_CONTROL 0x1f25 8782#define regHPD2_DC_HPD_INT_CONTROL_BASE_IDX 2 8783#define regHPD2_DC_HPD_CONTROL 0x1f26 8784#define regHPD2_DC_HPD_CONTROL_BASE_IDX 2 8785#define regHPD2_DC_HPD_FAST_TRAIN_CNTL 0x1f27 8786#define regHPD2_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2 8787#define regHPD2_DC_HPD_TOGGLE_FILT_CNTL 0x1f28 8788#define regHPD2_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2 8789 8790 8791// addressBlock: dcn_dc_dio_hpd3_dispdec 8792// base address: 0x60 8793#define regHPD3_DC_HPD_INT_STATUS 0x1f2c 8794#define regHPD3_DC_HPD_INT_STATUS_BASE_IDX 2 8795#define regHPD3_DC_HPD_INT_CONTROL 0x1f2d 8796#define regHPD3_DC_HPD_INT_CONTROL_BASE_IDX 2 8797#define regHPD3_DC_HPD_CONTROL 0x1f2e 8798#define regHPD3_DC_HPD_CONTROL_BASE_IDX 2 8799#define regHPD3_DC_HPD_FAST_TRAIN_CNTL 0x1f2f 8800#define regHPD3_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2 8801#define regHPD3_DC_HPD_TOGGLE_FILT_CNTL 0x1f30 8802#define regHPD3_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2 8803 8804 8805// addressBlock: dcn_dc_dio_hpd4_dispdec 8806// base address: 0x80 8807#define regHPD4_DC_HPD_INT_STATUS 0x1f34 8808#define regHPD4_DC_HPD_INT_STATUS_BASE_IDX 2 8809#define regHPD4_DC_HPD_INT_CONTROL 0x1f35 8810#define regHPD4_DC_HPD_INT_CONTROL_BASE_IDX 2 8811#define regHPD4_DC_HPD_CONTROL 0x1f36 8812#define regHPD4_DC_HPD_CONTROL_BASE_IDX 2 8813#define regHPD4_DC_HPD_FAST_TRAIN_CNTL 0x1f37 8814#define regHPD4_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2 8815#define regHPD4_DC_HPD_TOGGLE_FILT_CNTL 0x1f38 8816#define regHPD4_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2 8817 8818 8819// addressBlock: dcn_dc_dio_dp0_dispdec 8820// base address: 0x0 8821#define regDP0_DP_LINK_CNTL 0x2108 8822#define regDP0_DP_LINK_CNTL_BASE_IDX 2 8823#define regDP0_DP_PIXEL_FORMAT 0x2109 8824#define regDP0_DP_PIXEL_FORMAT_BASE_IDX 2 8825#define regDP0_DP_MSA_COLORIMETRY 0x210a 8826#define regDP0_DP_MSA_COLORIMETRY_BASE_IDX 2 8827#define regDP0_DP_CONFIG 0x210b 8828#define regDP0_DP_CONFIG_BASE_IDX 2 8829#define regDP0_DP_VID_STREAM_CNTL 0x210c 8830#define regDP0_DP_VID_STREAM_CNTL_BASE_IDX 2 8831#define regDP0_DP_STEER_FIFO 0x210d 8832#define regDP0_DP_STEER_FIFO_BASE_IDX 2 8833#define regDP0_DP_MSA_MISC 0x210e 8834#define regDP0_DP_MSA_MISC_BASE_IDX 2 8835#define regDP0_DP_DPHY_INTERNAL_CTRL 0x210f 8836#define regDP0_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 8837#define regDP0_DP_VID_TIMING 0x2110 8838#define regDP0_DP_VID_TIMING_BASE_IDX 2 8839#define regDP0_DP_VID_N 0x2111 8840#define regDP0_DP_VID_N_BASE_IDX 2 8841#define regDP0_DP_VID_M 0x2112 8842#define regDP0_DP_VID_M_BASE_IDX 2 8843#define regDP0_DP_LINK_FRAMING_CNTL 0x2113 8844#define regDP0_DP_LINK_FRAMING_CNTL_BASE_IDX 2 8845#define regDP0_DP_HBR2_EYE_PATTERN 0x2114 8846#define regDP0_DP_HBR2_EYE_PATTERN_BASE_IDX 2 8847#define regDP0_DP_VID_MSA_VBID 0x2115 8848#define regDP0_DP_VID_MSA_VBID_BASE_IDX 2 8849#define regDP0_DP_VID_INTERRUPT_CNTL 0x2116 8850#define regDP0_DP_VID_INTERRUPT_CNTL_BASE_IDX 2 8851#define regDP0_DP_DPHY_CNTL 0x2117 8852#define regDP0_DP_DPHY_CNTL_BASE_IDX 2 8853#define regDP0_DP_DPHY_TRAINING_PATTERN_SEL 0x2118 8854#define regDP0_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2 8855#define regDP0_DP_DPHY_SYM0 0x2119 8856#define regDP0_DP_DPHY_SYM0_BASE_IDX 2 8857#define regDP0_DP_DPHY_SYM1 0x211a 8858#define regDP0_DP_DPHY_SYM1_BASE_IDX 2 8859#define regDP0_DP_DPHY_SYM2 0x211b 8860#define regDP0_DP_DPHY_SYM2_BASE_IDX 2 8861#define regDP0_DP_DPHY_8B10B_CNTL 0x211c 8862#define regDP0_DP_DPHY_8B10B_CNTL_BASE_IDX 2 8863#define regDP0_DP_DPHY_PRBS_CNTL 0x211d 8864#define regDP0_DP_DPHY_PRBS_CNTL_BASE_IDX 2 8865#define regDP0_DP_DPHY_SCRAM_CNTL 0x211e 8866#define regDP0_DP_DPHY_SCRAM_CNTL_BASE_IDX 2 8867#define regDP0_DP_DPHY_CRC_EN 0x211f 8868#define regDP0_DP_DPHY_CRC_EN_BASE_IDX 2 8869#define regDP0_DP_DPHY_CRC_CNTL 0x2120 8870#define regDP0_DP_DPHY_CRC_CNTL_BASE_IDX 2 8871#define regDP0_DP_DPHY_CRC_RESULT 0x2121 8872#define regDP0_DP_DPHY_CRC_RESULT_BASE_IDX 2 8873#define regDP0_DP_DPHY_CRC_MST_CNTL 0x2122 8874#define regDP0_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2 8875#define regDP0_DP_DPHY_CRC_MST_STATUS 0x2123 8876#define regDP0_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2 8877#define regDP0_DP_DPHY_FAST_TRAINING 0x2124 8878#define regDP0_DP_DPHY_FAST_TRAINING_BASE_IDX 2 8879#define regDP0_DP_DPHY_FAST_TRAINING_STATUS 0x2125 8880#define regDP0_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2 8881#define regDP0_DP_SEC_CNTL 0x212b 8882#define regDP0_DP_SEC_CNTL_BASE_IDX 2 8883#define regDP0_DP_SEC_CNTL1 0x212c 8884#define regDP0_DP_SEC_CNTL1_BASE_IDX 2 8885#define regDP0_DP_SEC_FRAMING1 0x212d 8886#define regDP0_DP_SEC_FRAMING1_BASE_IDX 2 8887#define regDP0_DP_SEC_FRAMING2 0x212e 8888#define regDP0_DP_SEC_FRAMING2_BASE_IDX 2 8889#define regDP0_DP_SEC_FRAMING3 0x212f 8890#define regDP0_DP_SEC_FRAMING3_BASE_IDX 2 8891#define regDP0_DP_SEC_FRAMING4 0x2130 8892#define regDP0_DP_SEC_FRAMING4_BASE_IDX 2 8893#define regDP0_DP_SEC_AUD_N 0x2131 8894#define regDP0_DP_SEC_AUD_N_BASE_IDX 2 8895#define regDP0_DP_SEC_AUD_N_READBACK 0x2132 8896#define regDP0_DP_SEC_AUD_N_READBACK_BASE_IDX 2 8897#define regDP0_DP_SEC_AUD_M 0x2133 8898#define regDP0_DP_SEC_AUD_M_BASE_IDX 2 8899#define regDP0_DP_SEC_AUD_M_READBACK 0x2134 8900#define regDP0_DP_SEC_AUD_M_READBACK_BASE_IDX 2 8901#define regDP0_DP_SEC_TIMESTAMP 0x2135 8902#define regDP0_DP_SEC_TIMESTAMP_BASE_IDX 2 8903#define regDP0_DP_SEC_PACKET_CNTL 0x2136 8904#define regDP0_DP_SEC_PACKET_CNTL_BASE_IDX 2 8905#define regDP0_DP_MSE_RATE_CNTL 0x2137 8906#define regDP0_DP_MSE_RATE_CNTL_BASE_IDX 2 8907#define regDP0_DP_MSE_RATE_UPDATE 0x2139 8908#define regDP0_DP_MSE_RATE_UPDATE_BASE_IDX 2 8909#define regDP0_DP_MSE_SAT0 0x213a 8910#define regDP0_DP_MSE_SAT0_BASE_IDX 2 8911#define regDP0_DP_MSE_SAT1 0x213b 8912#define regDP0_DP_MSE_SAT1_BASE_IDX 2 8913#define regDP0_DP_MSE_SAT2 0x213c 8914#define regDP0_DP_MSE_SAT2_BASE_IDX 2 8915#define regDP0_DP_MSE_SAT_UPDATE 0x213d 8916#define regDP0_DP_MSE_SAT_UPDATE_BASE_IDX 2 8917#define regDP0_DP_MSE_LINK_TIMING 0x213e 8918#define regDP0_DP_MSE_LINK_TIMING_BASE_IDX 2 8919#define regDP0_DP_MSE_MISC_CNTL 0x213f 8920#define regDP0_DP_MSE_MISC_CNTL_BASE_IDX 2 8921#define regDP0_DP_DPHY_BS_SR_SWAP_CNTL 0x2144 8922#define regDP0_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2 8923#define regDP0_DP_DPHY_HBR2_PATTERN_CONTROL 0x2145 8924#define regDP0_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2 8925#define regDP0_DP_MSE_SAT0_STATUS 0x2147 8926#define regDP0_DP_MSE_SAT0_STATUS_BASE_IDX 2 8927#define regDP0_DP_MSE_SAT1_STATUS 0x2148 8928#define regDP0_DP_MSE_SAT1_STATUS_BASE_IDX 2 8929#define regDP0_DP_MSE_SAT2_STATUS 0x2149 8930#define regDP0_DP_MSE_SAT2_STATUS_BASE_IDX 2 8931#define regDP0_DP_DPIA_SPARE 0x214a 8932#define regDP0_DP_DPIA_SPARE_BASE_IDX 2 8933#define regDP0_DP_MSA_TIMING_PARAM1 0x214c 8934#define regDP0_DP_MSA_TIMING_PARAM1_BASE_IDX 2 8935#define regDP0_DP_MSA_TIMING_PARAM2 0x214d 8936#define regDP0_DP_MSA_TIMING_PARAM2_BASE_IDX 2 8937#define regDP0_DP_MSA_TIMING_PARAM3 0x214e 8938#define regDP0_DP_MSA_TIMING_PARAM3_BASE_IDX 2 8939#define regDP0_DP_MSA_TIMING_PARAM4 0x214f 8940#define regDP0_DP_MSA_TIMING_PARAM4_BASE_IDX 2 8941#define regDP0_DP_MSO_CNTL 0x2150 8942#define regDP0_DP_MSO_CNTL_BASE_IDX 2 8943#define regDP0_DP_MSO_CNTL1 0x2151 8944#define regDP0_DP_MSO_CNTL1_BASE_IDX 2 8945#define regDP0_DP_DSC_CNTL 0x2152 8946#define regDP0_DP_DSC_CNTL_BASE_IDX 2 8947#define regDP0_DP_SEC_CNTL2 0x2153 8948#define regDP0_DP_SEC_CNTL2_BASE_IDX 2 8949#define regDP0_DP_SEC_CNTL3 0x2154 8950#define regDP0_DP_SEC_CNTL3_BASE_IDX 2 8951#define regDP0_DP_SEC_CNTL4 0x2155 8952#define regDP0_DP_SEC_CNTL4_BASE_IDX 2 8953#define regDP0_DP_SEC_CNTL5 0x2156 8954#define regDP0_DP_SEC_CNTL5_BASE_IDX 2 8955#define regDP0_DP_SEC_CNTL6 0x2157 8956#define regDP0_DP_SEC_CNTL6_BASE_IDX 2 8957#define regDP0_DP_SEC_CNTL7 0x2158 8958#define regDP0_DP_SEC_CNTL7_BASE_IDX 2 8959#define regDP0_DP_DB_CNTL 0x2159 8960#define regDP0_DP_DB_CNTL_BASE_IDX 2 8961#define regDP0_DP_MSA_VBID_MISC 0x215a 8962#define regDP0_DP_MSA_VBID_MISC_BASE_IDX 2 8963#define regDP0_DP_SEC_METADATA_TRANSMISSION 0x215b 8964#define regDP0_DP_SEC_METADATA_TRANSMISSION_BASE_IDX 2 8965#define regDP0_DP_ALPM_CNTL 0x215d 8966#define regDP0_DP_ALPM_CNTL_BASE_IDX 2 8967#define regDP0_DP_GSP8_CNTL 0x215e 8968#define regDP0_DP_GSP8_CNTL_BASE_IDX 2 8969#define regDP0_DP_GSP9_CNTL 0x215f 8970#define regDP0_DP_GSP9_CNTL_BASE_IDX 2 8971#define regDP0_DP_GSP10_CNTL 0x2160 8972#define regDP0_DP_GSP10_CNTL_BASE_IDX 2 8973#define regDP0_DP_GSP11_CNTL 0x2161 8974#define regDP0_DP_GSP11_CNTL_BASE_IDX 2 8975#define regDP0_DP_GSP_EN_DB_STATUS 0x2162 8976#define regDP0_DP_GSP_EN_DB_STATUS_BASE_IDX 2 8977#define regDP0_DP_AUXLESS_ALPM_CNTL1 0x2163 8978#define regDP0_DP_AUXLESS_ALPM_CNTL1_BASE_IDX 2 8979#define regDP0_DP_AUXLESS_ALPM_CNTL2 0x2164 8980#define regDP0_DP_AUXLESS_ALPM_CNTL2_BASE_IDX 2 8981#define regDP0_DP_AUXLESS_ALPM_CNTL3 0x2165 8982#define regDP0_DP_AUXLESS_ALPM_CNTL3_BASE_IDX 2 8983#define regDP0_DP_AUXLESS_ALPM_CNTL4 0x2166 8984#define regDP0_DP_AUXLESS_ALPM_CNTL4_BASE_IDX 2 8985#define regDP0_DP_AUXLESS_ALPM_CNTL5 0x2167 8986#define regDP0_DP_AUXLESS_ALPM_CNTL5_BASE_IDX 2 8987 8988 8989// addressBlock: dcn_dc_dio_dig0_dispdec 8990// base address: 0x0 8991#define regDIG0_DIG_FE_CNTL 0x208b 8992#define regDIG0_DIG_FE_CNTL_BASE_IDX 2 8993#define regDIG0_DIG_OUTPUT_CRC_CNTL 0x208c 8994#define regDIG0_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2 8995#define regDIG0_DIG_OUTPUT_CRC_RESULT 0x208d 8996#define regDIG0_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2 8997#define regDIG0_DIG_CLOCK_PATTERN 0x208e 8998#define regDIG0_DIG_CLOCK_PATTERN_BASE_IDX 2 8999#define regDIG0_DIG_TEST_PATTERN 0x208f 9000#define regDIG0_DIG_TEST_PATTERN_BASE_IDX 2 9001#define regDIG0_DIG_RANDOM_PATTERN_SEED 0x2090 9002#define regDIG0_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2 9003#define regDIG0_DIG_FIFO_CTRL0 0x2091 9004#define regDIG0_DIG_FIFO_CTRL0_BASE_IDX 2 9005#define regDIG0_DIG_FIFO_CTRL1 0x2092 9006#define regDIG0_DIG_FIFO_CTRL1_BASE_IDX 2 9007#define regDIG0_HDMI_METADATA_PACKET_CONTROL 0x2093 9008#define regDIG0_HDMI_METADATA_PACKET_CONTROL_BASE_IDX 2 9009#define regDIG0_HDMI_CONTROL 0x2094 9010#define regDIG0_HDMI_CONTROL_BASE_IDX 2 9011#define regDIG0_HDMI_STATUS 0x2095 9012#define regDIG0_HDMI_STATUS_BASE_IDX 2 9013#define regDIG0_HDMI_AUDIO_PACKET_CONTROL 0x2096 9014#define regDIG0_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2 9015#define regDIG0_HDMI_ACR_PACKET_CONTROL 0x2097 9016#define regDIG0_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2 9017#define regDIG0_HDMI_VBI_PACKET_CONTROL 0x2098 9018#define regDIG0_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2 9019#define regDIG0_HDMI_INFOFRAME_CONTROL0 0x2099 9020#define regDIG0_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2 9021#define regDIG0_HDMI_INFOFRAME_CONTROL1 0x209a 9022#define regDIG0_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2 9023#define regDIG0_HDMI_GENERIC_PACKET_CONTROL0 0x209b 9024#define regDIG0_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2 9025#define regDIG0_HDMI_GENERIC_PACKET_CONTROL6 0x209c 9026#define regDIG0_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX 2 9027#define regDIG0_HDMI_GENERIC_PACKET_CONTROL5 0x209d 9028#define regDIG0_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX 2 9029#define regDIG0_HDMI_GC 0x209e 9030#define regDIG0_HDMI_GC_BASE_IDX 2 9031#define regDIG0_HDMI_GENERIC_PACKET_CONTROL1 0x209f 9032#define regDIG0_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2 9033#define regDIG0_HDMI_GENERIC_PACKET_CONTROL2 0x20a0 9034#define regDIG0_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2 9035#define regDIG0_HDMI_GENERIC_PACKET_CONTROL3 0x20a1 9036#define regDIG0_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2 9037#define regDIG0_HDMI_GENERIC_PACKET_CONTROL4 0x20a2 9038#define regDIG0_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX 2 9039#define regDIG0_HDMI_GENERIC_PACKET_CONTROL7 0x20a3 9040#define regDIG0_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX 2 9041#define regDIG0_HDMI_GENERIC_PACKET_CONTROL8 0x20a4 9042#define regDIG0_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX 2 9043#define regDIG0_HDMI_GENERIC_PACKET_CONTROL9 0x20a5 9044#define regDIG0_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX 2 9045#define regDIG0_HDMI_GENERIC_PACKET_CONTROL10 0x20a6 9046#define regDIG0_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX 2 9047#define regDIG0_HDMI_DB_CONTROL 0x20a7 9048#define regDIG0_HDMI_DB_CONTROL_BASE_IDX 2 9049#define regDIG0_HDMI_ACR_32_0 0x20a8 9050#define regDIG0_HDMI_ACR_32_0_BASE_IDX 2 9051#define regDIG0_HDMI_ACR_32_1 0x20a9 9052#define regDIG0_HDMI_ACR_32_1_BASE_IDX 2 9053#define regDIG0_HDMI_ACR_44_0 0x20aa 9054#define regDIG0_HDMI_ACR_44_0_BASE_IDX 2 9055#define regDIG0_HDMI_ACR_44_1 0x20ab 9056#define regDIG0_HDMI_ACR_44_1_BASE_IDX 2 9057#define regDIG0_HDMI_ACR_48_0 0x20ac 9058#define regDIG0_HDMI_ACR_48_0_BASE_IDX 2 9059#define regDIG0_HDMI_ACR_48_1 0x20ad 9060#define regDIG0_HDMI_ACR_48_1_BASE_IDX 2 9061#define regDIG0_HDMI_ACR_STATUS_0 0x20ae 9062#define regDIG0_HDMI_ACR_STATUS_0_BASE_IDX 2 9063#define regDIG0_HDMI_ACR_STATUS_1 0x20af 9064#define regDIG0_HDMI_ACR_STATUS_1_BASE_IDX 2 9065#define regDIG0_AFMT_CNTL 0x20b0 9066#define regDIG0_AFMT_CNTL_BASE_IDX 2 9067#define regDIG0_DIG_BE_CNTL 0x20b1 9068#define regDIG0_DIG_BE_CNTL_BASE_IDX 2 9069#define regDIG0_DIG_BE_EN_CNTL 0x20b2 9070#define regDIG0_DIG_BE_EN_CNTL_BASE_IDX 2 9071#define regDIG0_TMDS_CNTL 0x20d8 9072#define regDIG0_TMDS_CNTL_BASE_IDX 2 9073#define regDIG0_TMDS_CONTROL_CHAR 0x20d9 9074#define regDIG0_TMDS_CONTROL_CHAR_BASE_IDX 2 9075#define regDIG0_TMDS_CONTROL0_FEEDBACK 0x20da 9076#define regDIG0_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2 9077#define regDIG0_TMDS_STEREOSYNC_CTL_SEL 0x20db 9078#define regDIG0_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2 9079#define regDIG0_TMDS_SYNC_CHAR_PATTERN_0_1 0x20dc 9080#define regDIG0_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2 9081#define regDIG0_TMDS_SYNC_CHAR_PATTERN_2_3 0x20dd 9082#define regDIG0_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2 9083#define regDIG0_TMDS_CTL_BITS 0x20df 9084#define regDIG0_TMDS_CTL_BITS_BASE_IDX 2 9085#define regDIG0_TMDS_DCBALANCER_CONTROL 0x20e0 9086#define regDIG0_TMDS_DCBALANCER_CONTROL_BASE_IDX 2 9087#define regDIG0_TMDS_SYNC_DCBALANCE_CHAR 0x20e1 9088#define regDIG0_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX 2 9089#define regDIG0_TMDS_CTL0_1_GEN_CNTL 0x20e2 9090#define regDIG0_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2 9091#define regDIG0_TMDS_CTL2_3_GEN_CNTL 0x20e3 9092#define regDIG0_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2 9093#define regDIG0_DIG_VERSION 0x20e5 9094#define regDIG0_DIG_VERSION_BASE_IDX 2 9095#define regDIG0_FORCE_DIG_DISABLE 0x20e6 9096#define regDIG0_FORCE_DIG_DISABLE_BASE_IDX 2 9097 9098 9099// addressBlock: dcn_dc_dio_dp1_dispdec 9100// base address: 0x400 9101#define regDP1_DP_LINK_CNTL 0x2208 9102#define regDP1_DP_LINK_CNTL_BASE_IDX 2 9103#define regDP1_DP_PIXEL_FORMAT 0x2209 9104#define regDP1_DP_PIXEL_FORMAT_BASE_IDX 2 9105#define regDP1_DP_MSA_COLORIMETRY 0x220a 9106#define regDP1_DP_MSA_COLORIMETRY_BASE_IDX 2 9107#define regDP1_DP_CONFIG 0x220b 9108#define regDP1_DP_CONFIG_BASE_IDX 2 9109#define regDP1_DP_VID_STREAM_CNTL 0x220c 9110#define regDP1_DP_VID_STREAM_CNTL_BASE_IDX 2 9111#define regDP1_DP_STEER_FIFO 0x220d 9112#define regDP1_DP_STEER_FIFO_BASE_IDX 2 9113#define regDP1_DP_MSA_MISC 0x220e 9114#define regDP1_DP_MSA_MISC_BASE_IDX 2 9115#define regDP1_DP_DPHY_INTERNAL_CTRL 0x220f 9116#define regDP1_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 9117#define regDP1_DP_VID_TIMING 0x2210 9118#define regDP1_DP_VID_TIMING_BASE_IDX 2 9119#define regDP1_DP_VID_N 0x2211 9120#define regDP1_DP_VID_N_BASE_IDX 2 9121#define regDP1_DP_VID_M 0x2212 9122#define regDP1_DP_VID_M_BASE_IDX 2 9123#define regDP1_DP_LINK_FRAMING_CNTL 0x2213 9124#define regDP1_DP_LINK_FRAMING_CNTL_BASE_IDX 2 9125#define regDP1_DP_HBR2_EYE_PATTERN 0x2214 9126#define regDP1_DP_HBR2_EYE_PATTERN_BASE_IDX 2 9127#define regDP1_DP_VID_MSA_VBID 0x2215 9128#define regDP1_DP_VID_MSA_VBID_BASE_IDX 2 9129#define regDP1_DP_VID_INTERRUPT_CNTL 0x2216 9130#define regDP1_DP_VID_INTERRUPT_CNTL_BASE_IDX 2 9131#define regDP1_DP_DPHY_CNTL 0x2217 9132#define regDP1_DP_DPHY_CNTL_BASE_IDX 2 9133#define regDP1_DP_DPHY_TRAINING_PATTERN_SEL 0x2218 9134#define regDP1_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2 9135#define regDP1_DP_DPHY_SYM0 0x2219 9136#define regDP1_DP_DPHY_SYM0_BASE_IDX 2 9137#define regDP1_DP_DPHY_SYM1 0x221a 9138#define regDP1_DP_DPHY_SYM1_BASE_IDX 2 9139#define regDP1_DP_DPHY_SYM2 0x221b 9140#define regDP1_DP_DPHY_SYM2_BASE_IDX 2 9141#define regDP1_DP_DPHY_8B10B_CNTL 0x221c 9142#define regDP1_DP_DPHY_8B10B_CNTL_BASE_IDX 2 9143#define regDP1_DP_DPHY_PRBS_CNTL 0x221d 9144#define regDP1_DP_DPHY_PRBS_CNTL_BASE_IDX 2 9145#define regDP1_DP_DPHY_SCRAM_CNTL 0x221e 9146#define regDP1_DP_DPHY_SCRAM_CNTL_BASE_IDX 2 9147#define regDP1_DP_DPHY_CRC_EN 0x221f 9148#define regDP1_DP_DPHY_CRC_EN_BASE_IDX 2 9149#define regDP1_DP_DPHY_CRC_CNTL 0x2220 9150#define regDP1_DP_DPHY_CRC_CNTL_BASE_IDX 2 9151#define regDP1_DP_DPHY_CRC_RESULT 0x2221 9152#define regDP1_DP_DPHY_CRC_RESULT_BASE_IDX 2 9153#define regDP1_DP_DPHY_CRC_MST_CNTL 0x2222 9154#define regDP1_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2 9155#define regDP1_DP_DPHY_CRC_MST_STATUS 0x2223 9156#define regDP1_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2 9157#define regDP1_DP_DPHY_FAST_TRAINING 0x2224 9158#define regDP1_DP_DPHY_FAST_TRAINING_BASE_IDX 2 9159#define regDP1_DP_DPHY_FAST_TRAINING_STATUS 0x2225 9160#define regDP1_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2 9161#define regDP1_DP_SEC_CNTL 0x222b 9162#define regDP1_DP_SEC_CNTL_BASE_IDX 2 9163#define regDP1_DP_SEC_CNTL1 0x222c 9164#define regDP1_DP_SEC_CNTL1_BASE_IDX 2 9165#define regDP1_DP_SEC_FRAMING1 0x222d 9166#define regDP1_DP_SEC_FRAMING1_BASE_IDX 2 9167#define regDP1_DP_SEC_FRAMING2 0x222e 9168#define regDP1_DP_SEC_FRAMING2_BASE_IDX 2 9169#define regDP1_DP_SEC_FRAMING3 0x222f 9170#define regDP1_DP_SEC_FRAMING3_BASE_IDX 2 9171#define regDP1_DP_SEC_FRAMING4 0x2230 9172#define regDP1_DP_SEC_FRAMING4_BASE_IDX 2 9173#define regDP1_DP_SEC_AUD_N 0x2231 9174#define regDP1_DP_SEC_AUD_N_BASE_IDX 2 9175#define regDP1_DP_SEC_AUD_N_READBACK 0x2232 9176#define regDP1_DP_SEC_AUD_N_READBACK_BASE_IDX 2 9177#define regDP1_DP_SEC_AUD_M 0x2233 9178#define regDP1_DP_SEC_AUD_M_BASE_IDX 2 9179#define regDP1_DP_SEC_AUD_M_READBACK 0x2234 9180#define regDP1_DP_SEC_AUD_M_READBACK_BASE_IDX 2 9181#define regDP1_DP_SEC_TIMESTAMP 0x2235 9182#define regDP1_DP_SEC_TIMESTAMP_BASE_IDX 2 9183#define regDP1_DP_SEC_PACKET_CNTL 0x2236 9184#define regDP1_DP_SEC_PACKET_CNTL_BASE_IDX 2 9185#define regDP1_DP_MSE_RATE_CNTL 0x2237 9186#define regDP1_DP_MSE_RATE_CNTL_BASE_IDX 2 9187#define regDP1_DP_MSE_RATE_UPDATE 0x2239 9188#define regDP1_DP_MSE_RATE_UPDATE_BASE_IDX 2 9189#define regDP1_DP_MSE_SAT0 0x223a 9190#define regDP1_DP_MSE_SAT0_BASE_IDX 2 9191#define regDP1_DP_MSE_SAT1 0x223b 9192#define regDP1_DP_MSE_SAT1_BASE_IDX 2 9193#define regDP1_DP_MSE_SAT2 0x223c 9194#define regDP1_DP_MSE_SAT2_BASE_IDX 2 9195#define regDP1_DP_MSE_SAT_UPDATE 0x223d 9196#define regDP1_DP_MSE_SAT_UPDATE_BASE_IDX 2 9197#define regDP1_DP_MSE_LINK_TIMING 0x223e 9198#define regDP1_DP_MSE_LINK_TIMING_BASE_IDX 2 9199#define regDP1_DP_MSE_MISC_CNTL 0x223f 9200#define regDP1_DP_MSE_MISC_CNTL_BASE_IDX 2 9201#define regDP1_DP_DPHY_BS_SR_SWAP_CNTL 0x2244 9202#define regDP1_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2 9203#define regDP1_DP_DPHY_HBR2_PATTERN_CONTROL 0x2245 9204#define regDP1_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2 9205#define regDP1_DP_MSE_SAT0_STATUS 0x2247 9206#define regDP1_DP_MSE_SAT0_STATUS_BASE_IDX 2 9207#define regDP1_DP_MSE_SAT1_STATUS 0x2248 9208#define regDP1_DP_MSE_SAT1_STATUS_BASE_IDX 2 9209#define regDP1_DP_MSE_SAT2_STATUS 0x2249 9210#define regDP1_DP_MSE_SAT2_STATUS_BASE_IDX 2 9211#define regDP1_DP_DPIA_SPARE 0x224a 9212#define regDP1_DP_DPIA_SPARE_BASE_IDX 2 9213#define regDP1_DP_MSA_TIMING_PARAM1 0x224c 9214#define regDP1_DP_MSA_TIMING_PARAM1_BASE_IDX 2 9215#define regDP1_DP_MSA_TIMING_PARAM2 0x224d 9216#define regDP1_DP_MSA_TIMING_PARAM2_BASE_IDX 2 9217#define regDP1_DP_MSA_TIMING_PARAM3 0x224e 9218#define regDP1_DP_MSA_TIMING_PARAM3_BASE_IDX 2 9219#define regDP1_DP_MSA_TIMING_PARAM4 0x224f 9220#define regDP1_DP_MSA_TIMING_PARAM4_BASE_IDX 2 9221#define regDP1_DP_MSO_CNTL 0x2250 9222#define regDP1_DP_MSO_CNTL_BASE_IDX 2 9223#define regDP1_DP_MSO_CNTL1 0x2251 9224#define regDP1_DP_MSO_CNTL1_BASE_IDX 2 9225#define regDP1_DP_DSC_CNTL 0x2252 9226#define regDP1_DP_DSC_CNTL_BASE_IDX 2 9227#define regDP1_DP_SEC_CNTL2 0x2253 9228#define regDP1_DP_SEC_CNTL2_BASE_IDX 2 9229#define regDP1_DP_SEC_CNTL3 0x2254 9230#define regDP1_DP_SEC_CNTL3_BASE_IDX 2 9231#define regDP1_DP_SEC_CNTL4 0x2255 9232#define regDP1_DP_SEC_CNTL4_BASE_IDX 2 9233#define regDP1_DP_SEC_CNTL5 0x2256 9234#define regDP1_DP_SEC_CNTL5_BASE_IDX 2 9235#define regDP1_DP_SEC_CNTL6 0x2257 9236#define regDP1_DP_SEC_CNTL6_BASE_IDX 2 9237#define regDP1_DP_SEC_CNTL7 0x2258 9238#define regDP1_DP_SEC_CNTL7_BASE_IDX 2 9239#define regDP1_DP_DB_CNTL 0x2259 9240#define regDP1_DP_DB_CNTL_BASE_IDX 2 9241#define regDP1_DP_MSA_VBID_MISC 0x225a 9242#define regDP1_DP_MSA_VBID_MISC_BASE_IDX 2 9243#define regDP1_DP_SEC_METADATA_TRANSMISSION 0x225b 9244#define regDP1_DP_SEC_METADATA_TRANSMISSION_BASE_IDX 2 9245#define regDP1_DP_ALPM_CNTL 0x225d 9246#define regDP1_DP_ALPM_CNTL_BASE_IDX 2 9247#define regDP1_DP_GSP8_CNTL 0x225e 9248#define regDP1_DP_GSP8_CNTL_BASE_IDX 2 9249#define regDP1_DP_GSP9_CNTL 0x225f 9250#define regDP1_DP_GSP9_CNTL_BASE_IDX 2 9251#define regDP1_DP_GSP10_CNTL 0x2260 9252#define regDP1_DP_GSP10_CNTL_BASE_IDX 2 9253#define regDP1_DP_GSP11_CNTL 0x2261 9254#define regDP1_DP_GSP11_CNTL_BASE_IDX 2 9255#define regDP1_DP_GSP_EN_DB_STATUS 0x2262 9256#define regDP1_DP_GSP_EN_DB_STATUS_BASE_IDX 2 9257#define regDP1_DP_AUXLESS_ALPM_CNTL1 0x2263 9258#define regDP1_DP_AUXLESS_ALPM_CNTL1_BASE_IDX 2 9259#define regDP1_DP_AUXLESS_ALPM_CNTL2 0x2264 9260#define regDP1_DP_AUXLESS_ALPM_CNTL2_BASE_IDX 2 9261#define regDP1_DP_AUXLESS_ALPM_CNTL3 0x2265 9262#define regDP1_DP_AUXLESS_ALPM_CNTL3_BASE_IDX 2 9263#define regDP1_DP_AUXLESS_ALPM_CNTL4 0x2266 9264#define regDP1_DP_AUXLESS_ALPM_CNTL4_BASE_IDX 2 9265#define regDP1_DP_AUXLESS_ALPM_CNTL5 0x2267 9266#define regDP1_DP_AUXLESS_ALPM_CNTL5_BASE_IDX 2 9267 9268 9269// addressBlock: dcn_dc_dio_dig1_dispdec 9270// base address: 0x400 9271#define regDIG1_DIG_FE_CNTL 0x218b 9272#define regDIG1_DIG_FE_CNTL_BASE_IDX 2 9273#define regDIG1_DIG_OUTPUT_CRC_CNTL 0x218c 9274#define regDIG1_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2 9275#define regDIG1_DIG_OUTPUT_CRC_RESULT 0x218d 9276#define regDIG1_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2 9277#define regDIG1_DIG_CLOCK_PATTERN 0x218e 9278#define regDIG1_DIG_CLOCK_PATTERN_BASE_IDX 2 9279#define regDIG1_DIG_TEST_PATTERN 0x218f 9280#define regDIG1_DIG_TEST_PATTERN_BASE_IDX 2 9281#define regDIG1_DIG_RANDOM_PATTERN_SEED 0x2190 9282#define regDIG1_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2 9283#define regDIG1_DIG_FIFO_CTRL0 0x2191 9284#define regDIG1_DIG_FIFO_CTRL0_BASE_IDX 2 9285#define regDIG1_DIG_FIFO_CTRL1 0x2192 9286#define regDIG1_DIG_FIFO_CTRL1_BASE_IDX 2 9287#define regDIG1_HDMI_METADATA_PACKET_CONTROL 0x2193 9288#define regDIG1_HDMI_METADATA_PACKET_CONTROL_BASE_IDX 2 9289#define regDIG1_HDMI_CONTROL 0x2194 9290#define regDIG1_HDMI_CONTROL_BASE_IDX 2 9291#define regDIG1_HDMI_STATUS 0x2195 9292#define regDIG1_HDMI_STATUS_BASE_IDX 2 9293#define regDIG1_HDMI_AUDIO_PACKET_CONTROL 0x2196 9294#define regDIG1_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2 9295#define regDIG1_HDMI_ACR_PACKET_CONTROL 0x2197 9296#define regDIG1_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2 9297#define regDIG1_HDMI_VBI_PACKET_CONTROL 0x2198 9298#define regDIG1_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2 9299#define regDIG1_HDMI_INFOFRAME_CONTROL0 0x2199 9300#define regDIG1_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2 9301#define regDIG1_HDMI_INFOFRAME_CONTROL1 0x219a 9302#define regDIG1_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2 9303#define regDIG1_HDMI_GENERIC_PACKET_CONTROL0 0x219b 9304#define regDIG1_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2 9305#define regDIG1_HDMI_GENERIC_PACKET_CONTROL6 0x219c 9306#define regDIG1_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX 2 9307#define regDIG1_HDMI_GENERIC_PACKET_CONTROL5 0x219d 9308#define regDIG1_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX 2 9309#define regDIG1_HDMI_GC 0x219e 9310#define regDIG1_HDMI_GC_BASE_IDX 2 9311#define regDIG1_HDMI_GENERIC_PACKET_CONTROL1 0x219f 9312#define regDIG1_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2 9313#define regDIG1_HDMI_GENERIC_PACKET_CONTROL2 0x21a0 9314#define regDIG1_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2 9315#define regDIG1_HDMI_GENERIC_PACKET_CONTROL3 0x21a1 9316#define regDIG1_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2 9317#define regDIG1_HDMI_GENERIC_PACKET_CONTROL4 0x21a2 9318#define regDIG1_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX 2 9319#define regDIG1_HDMI_GENERIC_PACKET_CONTROL7 0x21a3 9320#define regDIG1_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX 2 9321#define regDIG1_HDMI_GENERIC_PACKET_CONTROL8 0x21a4 9322#define regDIG1_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX 2 9323#define regDIG1_HDMI_GENERIC_PACKET_CONTROL9 0x21a5 9324#define regDIG1_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX 2 9325#define regDIG1_HDMI_GENERIC_PACKET_CONTROL10 0x21a6 9326#define regDIG1_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX 2 9327#define regDIG1_HDMI_DB_CONTROL 0x21a7 9328#define regDIG1_HDMI_DB_CONTROL_BASE_IDX 2 9329#define regDIG1_HDMI_ACR_32_0 0x21a8 9330#define regDIG1_HDMI_ACR_32_0_BASE_IDX 2 9331#define regDIG1_HDMI_ACR_32_1 0x21a9 9332#define regDIG1_HDMI_ACR_32_1_BASE_IDX 2 9333#define regDIG1_HDMI_ACR_44_0 0x21aa 9334#define regDIG1_HDMI_ACR_44_0_BASE_IDX 2 9335#define regDIG1_HDMI_ACR_44_1 0x21ab 9336#define regDIG1_HDMI_ACR_44_1_BASE_IDX 2 9337#define regDIG1_HDMI_ACR_48_0 0x21ac 9338#define regDIG1_HDMI_ACR_48_0_BASE_IDX 2 9339#define regDIG1_HDMI_ACR_48_1 0x21ad 9340#define regDIG1_HDMI_ACR_48_1_BASE_IDX 2 9341#define regDIG1_HDMI_ACR_STATUS_0 0x21ae 9342#define regDIG1_HDMI_ACR_STATUS_0_BASE_IDX 2 9343#define regDIG1_HDMI_ACR_STATUS_1 0x21af 9344#define regDIG1_HDMI_ACR_STATUS_1_BASE_IDX 2 9345#define regDIG1_AFMT_CNTL 0x21b0 9346#define regDIG1_AFMT_CNTL_BASE_IDX 2 9347#define regDIG1_DIG_BE_CNTL 0x21b1 9348#define regDIG1_DIG_BE_CNTL_BASE_IDX 2 9349#define regDIG1_DIG_BE_EN_CNTL 0x21b2 9350#define regDIG1_DIG_BE_EN_CNTL_BASE_IDX 2 9351#define regDIG1_TMDS_CNTL 0x21d8 9352#define regDIG1_TMDS_CNTL_BASE_IDX 2 9353#define regDIG1_TMDS_CONTROL_CHAR 0x21d9 9354#define regDIG1_TMDS_CONTROL_CHAR_BASE_IDX 2 9355#define regDIG1_TMDS_CONTROL0_FEEDBACK 0x21da 9356#define regDIG1_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2 9357#define regDIG1_TMDS_STEREOSYNC_CTL_SEL 0x21db 9358#define regDIG1_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2 9359#define regDIG1_TMDS_SYNC_CHAR_PATTERN_0_1 0x21dc 9360#define regDIG1_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2 9361#define regDIG1_TMDS_SYNC_CHAR_PATTERN_2_3 0x21dd 9362#define regDIG1_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2 9363#define regDIG1_TMDS_CTL_BITS 0x21df 9364#define regDIG1_TMDS_CTL_BITS_BASE_IDX 2 9365#define regDIG1_TMDS_DCBALANCER_CONTROL 0x21e0 9366#define regDIG1_TMDS_DCBALANCER_CONTROL_BASE_IDX 2 9367#define regDIG1_TMDS_SYNC_DCBALANCE_CHAR 0x21e1 9368#define regDIG1_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX 2 9369#define regDIG1_TMDS_CTL0_1_GEN_CNTL 0x21e2 9370#define regDIG1_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2 9371#define regDIG1_TMDS_CTL2_3_GEN_CNTL 0x21e3 9372#define regDIG1_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2 9373#define regDIG1_DIG_VERSION 0x21e5 9374#define regDIG1_DIG_VERSION_BASE_IDX 2 9375#define regDIG1_FORCE_DIG_DISABLE 0x21e6 9376#define regDIG1_FORCE_DIG_DISABLE_BASE_IDX 2 9377 9378 9379// addressBlock: dcn_dc_dio_dp2_dispdec 9380// base address: 0x800 9381#define regDP2_DP_LINK_CNTL 0x2308 9382#define regDP2_DP_LINK_CNTL_BASE_IDX 2 9383#define regDP2_DP_PIXEL_FORMAT 0x2309 9384#define regDP2_DP_PIXEL_FORMAT_BASE_IDX 2 9385#define regDP2_DP_MSA_COLORIMETRY 0x230a 9386#define regDP2_DP_MSA_COLORIMETRY_BASE_IDX 2 9387#define regDP2_DP_CONFIG 0x230b 9388#define regDP2_DP_CONFIG_BASE_IDX 2 9389#define regDP2_DP_VID_STREAM_CNTL 0x230c 9390#define regDP2_DP_VID_STREAM_CNTL_BASE_IDX 2 9391#define regDP2_DP_STEER_FIFO 0x230d 9392#define regDP2_DP_STEER_FIFO_BASE_IDX 2 9393#define regDP2_DP_MSA_MISC 0x230e 9394#define regDP2_DP_MSA_MISC_BASE_IDX 2 9395#define regDP2_DP_DPHY_INTERNAL_CTRL 0x230f 9396#define regDP2_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 9397#define regDP2_DP_VID_TIMING 0x2310 9398#define regDP2_DP_VID_TIMING_BASE_IDX 2 9399#define regDP2_DP_VID_N 0x2311 9400#define regDP2_DP_VID_N_BASE_IDX 2 9401#define regDP2_DP_VID_M 0x2312 9402#define regDP2_DP_VID_M_BASE_IDX 2 9403#define regDP2_DP_LINK_FRAMING_CNTL 0x2313 9404#define regDP2_DP_LINK_FRAMING_CNTL_BASE_IDX 2 9405#define regDP2_DP_HBR2_EYE_PATTERN 0x2314 9406#define regDP2_DP_HBR2_EYE_PATTERN_BASE_IDX 2 9407#define regDP2_DP_VID_MSA_VBID 0x2315 9408#define regDP2_DP_VID_MSA_VBID_BASE_IDX 2 9409#define regDP2_DP_VID_INTERRUPT_CNTL 0x2316 9410#define regDP2_DP_VID_INTERRUPT_CNTL_BASE_IDX 2 9411#define regDP2_DP_DPHY_CNTL 0x2317 9412#define regDP2_DP_DPHY_CNTL_BASE_IDX 2 9413#define regDP2_DP_DPHY_TRAINING_PATTERN_SEL 0x2318 9414#define regDP2_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2 9415#define regDP2_DP_DPHY_SYM0 0x2319 9416#define regDP2_DP_DPHY_SYM0_BASE_IDX 2 9417#define regDP2_DP_DPHY_SYM1 0x231a 9418#define regDP2_DP_DPHY_SYM1_BASE_IDX 2 9419#define regDP2_DP_DPHY_SYM2 0x231b 9420#define regDP2_DP_DPHY_SYM2_BASE_IDX 2 9421#define regDP2_DP_DPHY_8B10B_CNTL 0x231c 9422#define regDP2_DP_DPHY_8B10B_CNTL_BASE_IDX 2 9423#define regDP2_DP_DPHY_PRBS_CNTL 0x231d 9424#define regDP2_DP_DPHY_PRBS_CNTL_BASE_IDX 2 9425#define regDP2_DP_DPHY_SCRAM_CNTL 0x231e 9426#define regDP2_DP_DPHY_SCRAM_CNTL_BASE_IDX 2 9427#define regDP2_DP_DPHY_CRC_EN 0x231f 9428#define regDP2_DP_DPHY_CRC_EN_BASE_IDX 2 9429#define regDP2_DP_DPHY_CRC_CNTL 0x2320 9430#define regDP2_DP_DPHY_CRC_CNTL_BASE_IDX 2 9431#define regDP2_DP_DPHY_CRC_RESULT 0x2321 9432#define regDP2_DP_DPHY_CRC_RESULT_BASE_IDX 2 9433#define regDP2_DP_DPHY_CRC_MST_CNTL 0x2322 9434#define regDP2_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2 9435#define regDP2_DP_DPHY_CRC_MST_STATUS 0x2323 9436#define regDP2_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2 9437#define regDP2_DP_DPHY_FAST_TRAINING 0x2324 9438#define regDP2_DP_DPHY_FAST_TRAINING_BASE_IDX 2 9439#define regDP2_DP_DPHY_FAST_TRAINING_STATUS 0x2325 9440#define regDP2_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2 9441#define regDP2_DP_SEC_CNTL 0x232b 9442#define regDP2_DP_SEC_CNTL_BASE_IDX 2 9443#define regDP2_DP_SEC_CNTL1 0x232c 9444#define regDP2_DP_SEC_CNTL1_BASE_IDX 2 9445#define regDP2_DP_SEC_FRAMING1 0x232d 9446#define regDP2_DP_SEC_FRAMING1_BASE_IDX 2 9447#define regDP2_DP_SEC_FRAMING2 0x232e 9448#define regDP2_DP_SEC_FRAMING2_BASE_IDX 2 9449#define regDP2_DP_SEC_FRAMING3 0x232f 9450#define regDP2_DP_SEC_FRAMING3_BASE_IDX 2 9451#define regDP2_DP_SEC_FRAMING4 0x2330 9452#define regDP2_DP_SEC_FRAMING4_BASE_IDX 2 9453#define regDP2_DP_SEC_AUD_N 0x2331 9454#define regDP2_DP_SEC_AUD_N_BASE_IDX 2 9455#define regDP2_DP_SEC_AUD_N_READBACK 0x2332 9456#define regDP2_DP_SEC_AUD_N_READBACK_BASE_IDX 2 9457#define regDP2_DP_SEC_AUD_M 0x2333 9458#define regDP2_DP_SEC_AUD_M_BASE_IDX 2 9459#define regDP2_DP_SEC_AUD_M_READBACK 0x2334 9460#define regDP2_DP_SEC_AUD_M_READBACK_BASE_IDX 2 9461#define regDP2_DP_SEC_TIMESTAMP 0x2335 9462#define regDP2_DP_SEC_TIMESTAMP_BASE_IDX 2 9463#define regDP2_DP_SEC_PACKET_CNTL 0x2336 9464#define regDP2_DP_SEC_PACKET_CNTL_BASE_IDX 2 9465#define regDP2_DP_MSE_RATE_CNTL 0x2337 9466#define regDP2_DP_MSE_RATE_CNTL_BASE_IDX 2 9467#define regDP2_DP_MSE_RATE_UPDATE 0x2339 9468#define regDP2_DP_MSE_RATE_UPDATE_BASE_IDX 2 9469#define regDP2_DP_MSE_SAT0 0x233a 9470#define regDP2_DP_MSE_SAT0_BASE_IDX 2 9471#define regDP2_DP_MSE_SAT1 0x233b 9472#define regDP2_DP_MSE_SAT1_BASE_IDX 2 9473#define regDP2_DP_MSE_SAT2 0x233c 9474#define regDP2_DP_MSE_SAT2_BASE_IDX 2 9475#define regDP2_DP_MSE_SAT_UPDATE 0x233d 9476#define regDP2_DP_MSE_SAT_UPDATE_BASE_IDX 2 9477#define regDP2_DP_MSE_LINK_TIMING 0x233e 9478#define regDP2_DP_MSE_LINK_TIMING_BASE_IDX 2 9479#define regDP2_DP_MSE_MISC_CNTL 0x233f 9480#define regDP2_DP_MSE_MISC_CNTL_BASE_IDX 2 9481#define regDP2_DP_DPHY_BS_SR_SWAP_CNTL 0x2344 9482#define regDP2_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2 9483#define regDP2_DP_DPHY_HBR2_PATTERN_CONTROL 0x2345 9484#define regDP2_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2 9485#define regDP2_DP_MSE_SAT0_STATUS 0x2347 9486#define regDP2_DP_MSE_SAT0_STATUS_BASE_IDX 2 9487#define regDP2_DP_MSE_SAT1_STATUS 0x2348 9488#define regDP2_DP_MSE_SAT1_STATUS_BASE_IDX 2 9489#define regDP2_DP_MSE_SAT2_STATUS 0x2349 9490#define regDP2_DP_MSE_SAT2_STATUS_BASE_IDX 2 9491#define regDP2_DP_DPIA_SPARE 0x234a 9492#define regDP2_DP_DPIA_SPARE_BASE_IDX 2 9493#define regDP2_DP_MSA_TIMING_PARAM1 0x234c 9494#define regDP2_DP_MSA_TIMING_PARAM1_BASE_IDX 2 9495#define regDP2_DP_MSA_TIMING_PARAM2 0x234d 9496#define regDP2_DP_MSA_TIMING_PARAM2_BASE_IDX 2 9497#define regDP2_DP_MSA_TIMING_PARAM3 0x234e 9498#define regDP2_DP_MSA_TIMING_PARAM3_BASE_IDX 2 9499#define regDP2_DP_MSA_TIMING_PARAM4 0x234f 9500#define regDP2_DP_MSA_TIMING_PARAM4_BASE_IDX 2 9501#define regDP2_DP_MSO_CNTL 0x2350 9502#define regDP2_DP_MSO_CNTL_BASE_IDX 2 9503#define regDP2_DP_MSO_CNTL1 0x2351 9504#define regDP2_DP_MSO_CNTL1_BASE_IDX 2 9505#define regDP2_DP_DSC_CNTL 0x2352 9506#define regDP2_DP_DSC_CNTL_BASE_IDX 2 9507#define regDP2_DP_SEC_CNTL2 0x2353 9508#define regDP2_DP_SEC_CNTL2_BASE_IDX 2 9509#define regDP2_DP_SEC_CNTL3 0x2354 9510#define regDP2_DP_SEC_CNTL3_BASE_IDX 2 9511#define regDP2_DP_SEC_CNTL4 0x2355 9512#define regDP2_DP_SEC_CNTL4_BASE_IDX 2 9513#define regDP2_DP_SEC_CNTL5 0x2356 9514#define regDP2_DP_SEC_CNTL5_BASE_IDX 2 9515#define regDP2_DP_SEC_CNTL6 0x2357 9516#define regDP2_DP_SEC_CNTL6_BASE_IDX 2 9517#define regDP2_DP_SEC_CNTL7 0x2358 9518#define regDP2_DP_SEC_CNTL7_BASE_IDX 2 9519#define regDP2_DP_DB_CNTL 0x2359 9520#define regDP2_DP_DB_CNTL_BASE_IDX 2 9521#define regDP2_DP_MSA_VBID_MISC 0x235a 9522#define regDP2_DP_MSA_VBID_MISC_BASE_IDX 2 9523#define regDP2_DP_SEC_METADATA_TRANSMISSION 0x235b 9524#define regDP2_DP_SEC_METADATA_TRANSMISSION_BASE_IDX 2 9525#define regDP2_DP_ALPM_CNTL 0x235d 9526#define regDP2_DP_ALPM_CNTL_BASE_IDX 2 9527#define regDP2_DP_GSP8_CNTL 0x235e 9528#define regDP2_DP_GSP8_CNTL_BASE_IDX 2 9529#define regDP2_DP_GSP9_CNTL 0x235f 9530#define regDP2_DP_GSP9_CNTL_BASE_IDX 2 9531#define regDP2_DP_GSP10_CNTL 0x2360 9532#define regDP2_DP_GSP10_CNTL_BASE_IDX 2 9533#define regDP2_DP_GSP11_CNTL 0x2361 9534#define regDP2_DP_GSP11_CNTL_BASE_IDX 2 9535#define regDP2_DP_GSP_EN_DB_STATUS 0x2362 9536#define regDP2_DP_GSP_EN_DB_STATUS_BASE_IDX 2 9537#define regDP2_DP_AUXLESS_ALPM_CNTL1 0x2363 9538#define regDP2_DP_AUXLESS_ALPM_CNTL1_BASE_IDX 2 9539#define regDP2_DP_AUXLESS_ALPM_CNTL2 0x2364 9540#define regDP2_DP_AUXLESS_ALPM_CNTL2_BASE_IDX 2 9541#define regDP2_DP_AUXLESS_ALPM_CNTL3 0x2365 9542#define regDP2_DP_AUXLESS_ALPM_CNTL3_BASE_IDX 2 9543#define regDP2_DP_AUXLESS_ALPM_CNTL4 0x2366 9544#define regDP2_DP_AUXLESS_ALPM_CNTL4_BASE_IDX 2 9545#define regDP2_DP_AUXLESS_ALPM_CNTL5 0x2367 9546#define regDP2_DP_AUXLESS_ALPM_CNTL5_BASE_IDX 2 9547 9548 9549// addressBlock: dcn_dc_dio_dig2_dispdec 9550// base address: 0x800 9551#define regDIG2_DIG_FE_CNTL 0x228b 9552#define regDIG2_DIG_FE_CNTL_BASE_IDX 2 9553#define regDIG2_DIG_OUTPUT_CRC_CNTL 0x228c 9554#define regDIG2_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2 9555#define regDIG2_DIG_OUTPUT_CRC_RESULT 0x228d 9556#define regDIG2_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2 9557#define regDIG2_DIG_CLOCK_PATTERN 0x228e 9558#define regDIG2_DIG_CLOCK_PATTERN_BASE_IDX 2 9559#define regDIG2_DIG_TEST_PATTERN 0x228f 9560#define regDIG2_DIG_TEST_PATTERN_BASE_IDX 2 9561#define regDIG2_DIG_RANDOM_PATTERN_SEED 0x2290 9562#define regDIG2_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2 9563#define regDIG2_DIG_FIFO_CTRL0 0x2291 9564#define regDIG2_DIG_FIFO_CTRL0_BASE_IDX 2 9565#define regDIG2_DIG_FIFO_CTRL1 0x2292 9566#define regDIG2_DIG_FIFO_CTRL1_BASE_IDX 2 9567#define regDIG2_HDMI_METADATA_PACKET_CONTROL 0x2293 9568#define regDIG2_HDMI_METADATA_PACKET_CONTROL_BASE_IDX 2 9569#define regDIG2_HDMI_CONTROL 0x2294 9570#define regDIG2_HDMI_CONTROL_BASE_IDX 2 9571#define regDIG2_HDMI_STATUS 0x2295 9572#define regDIG2_HDMI_STATUS_BASE_IDX 2 9573#define regDIG2_HDMI_AUDIO_PACKET_CONTROL 0x2296 9574#define regDIG2_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2 9575#define regDIG2_HDMI_ACR_PACKET_CONTROL 0x2297 9576#define regDIG2_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2 9577#define regDIG2_HDMI_VBI_PACKET_CONTROL 0x2298 9578#define regDIG2_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2 9579#define regDIG2_HDMI_INFOFRAME_CONTROL0 0x2299 9580#define regDIG2_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2 9581#define regDIG2_HDMI_INFOFRAME_CONTROL1 0x229a 9582#define regDIG2_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2 9583#define regDIG2_HDMI_GENERIC_PACKET_CONTROL0 0x229b 9584#define regDIG2_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2 9585#define regDIG2_HDMI_GENERIC_PACKET_CONTROL6 0x229c 9586#define regDIG2_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX 2 9587#define regDIG2_HDMI_GENERIC_PACKET_CONTROL5 0x229d 9588#define regDIG2_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX 2 9589#define regDIG2_HDMI_GC 0x229e 9590#define regDIG2_HDMI_GC_BASE_IDX 2 9591#define regDIG2_HDMI_GENERIC_PACKET_CONTROL1 0x229f 9592#define regDIG2_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2 9593#define regDIG2_HDMI_GENERIC_PACKET_CONTROL2 0x22a0 9594#define regDIG2_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2 9595#define regDIG2_HDMI_GENERIC_PACKET_CONTROL3 0x22a1 9596#define regDIG2_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2 9597#define regDIG2_HDMI_GENERIC_PACKET_CONTROL4 0x22a2 9598#define regDIG2_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX 2 9599#define regDIG2_HDMI_GENERIC_PACKET_CONTROL7 0x22a3 9600#define regDIG2_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX 2 9601#define regDIG2_HDMI_GENERIC_PACKET_CONTROL8 0x22a4 9602#define regDIG2_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX 2 9603#define regDIG2_HDMI_GENERIC_PACKET_CONTROL9 0x22a5 9604#define regDIG2_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX 2 9605#define regDIG2_HDMI_GENERIC_PACKET_CONTROL10 0x22a6 9606#define regDIG2_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX 2 9607#define regDIG2_HDMI_DB_CONTROL 0x22a7 9608#define regDIG2_HDMI_DB_CONTROL_BASE_IDX 2 9609#define regDIG2_HDMI_ACR_32_0 0x22a8 9610#define regDIG2_HDMI_ACR_32_0_BASE_IDX 2 9611#define regDIG2_HDMI_ACR_32_1 0x22a9 9612#define regDIG2_HDMI_ACR_32_1_BASE_IDX 2 9613#define regDIG2_HDMI_ACR_44_0 0x22aa 9614#define regDIG2_HDMI_ACR_44_0_BASE_IDX 2 9615#define regDIG2_HDMI_ACR_44_1 0x22ab 9616#define regDIG2_HDMI_ACR_44_1_BASE_IDX 2 9617#define regDIG2_HDMI_ACR_48_0 0x22ac 9618#define regDIG2_HDMI_ACR_48_0_BASE_IDX 2 9619#define regDIG2_HDMI_ACR_48_1 0x22ad 9620#define regDIG2_HDMI_ACR_48_1_BASE_IDX 2 9621#define regDIG2_HDMI_ACR_STATUS_0 0x22ae 9622#define regDIG2_HDMI_ACR_STATUS_0_BASE_IDX 2 9623#define regDIG2_HDMI_ACR_STATUS_1 0x22af 9624#define regDIG2_HDMI_ACR_STATUS_1_BASE_IDX 2 9625#define regDIG2_AFMT_CNTL 0x22b0 9626#define regDIG2_AFMT_CNTL_BASE_IDX 2 9627#define regDIG2_DIG_BE_CNTL 0x22b1 9628#define regDIG2_DIG_BE_CNTL_BASE_IDX 2 9629#define regDIG2_DIG_BE_EN_CNTL 0x22b2 9630#define regDIG2_DIG_BE_EN_CNTL_BASE_IDX 2 9631#define regDIG2_TMDS_CNTL 0x22d8 9632#define regDIG2_TMDS_CNTL_BASE_IDX 2 9633#define regDIG2_TMDS_CONTROL_CHAR 0x22d9 9634#define regDIG2_TMDS_CONTROL_CHAR_BASE_IDX 2 9635#define regDIG2_TMDS_CONTROL0_FEEDBACK 0x22da 9636#define regDIG2_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2 9637#define regDIG2_TMDS_STEREOSYNC_CTL_SEL 0x22db 9638#define regDIG2_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2 9639#define regDIG2_TMDS_SYNC_CHAR_PATTERN_0_1 0x22dc 9640#define regDIG2_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2 9641#define regDIG2_TMDS_SYNC_CHAR_PATTERN_2_3 0x22dd 9642#define regDIG2_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2 9643#define regDIG2_TMDS_CTL_BITS 0x22df 9644#define regDIG2_TMDS_CTL_BITS_BASE_IDX 2 9645#define regDIG2_TMDS_DCBALANCER_CONTROL 0x22e0 9646#define regDIG2_TMDS_DCBALANCER_CONTROL_BASE_IDX 2 9647#define regDIG2_TMDS_SYNC_DCBALANCE_CHAR 0x22e1 9648#define regDIG2_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX 2 9649#define regDIG2_TMDS_CTL0_1_GEN_CNTL 0x22e2 9650#define regDIG2_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2 9651#define regDIG2_TMDS_CTL2_3_GEN_CNTL 0x22e3 9652#define regDIG2_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2 9653#define regDIG2_DIG_VERSION 0x22e5 9654#define regDIG2_DIG_VERSION_BASE_IDX 2 9655#define regDIG2_FORCE_DIG_DISABLE 0x22e6 9656#define regDIG2_FORCE_DIG_DISABLE_BASE_IDX 2 9657 9658 9659// addressBlock: dcn_dc_dio_dp3_dispdec 9660// base address: 0xc00 9661#define regDP3_DP_LINK_CNTL 0x2408 9662#define regDP3_DP_LINK_CNTL_BASE_IDX 2 9663#define regDP3_DP_PIXEL_FORMAT 0x2409 9664#define regDP3_DP_PIXEL_FORMAT_BASE_IDX 2 9665#define regDP3_DP_MSA_COLORIMETRY 0x240a 9666#define regDP3_DP_MSA_COLORIMETRY_BASE_IDX 2 9667#define regDP3_DP_CONFIG 0x240b 9668#define regDP3_DP_CONFIG_BASE_IDX 2 9669#define regDP3_DP_VID_STREAM_CNTL 0x240c 9670#define regDP3_DP_VID_STREAM_CNTL_BASE_IDX 2 9671#define regDP3_DP_STEER_FIFO 0x240d 9672#define regDP3_DP_STEER_FIFO_BASE_IDX 2 9673#define regDP3_DP_MSA_MISC 0x240e 9674#define regDP3_DP_MSA_MISC_BASE_IDX 2 9675#define regDP3_DP_DPHY_INTERNAL_CTRL 0x240f 9676#define regDP3_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 9677#define regDP3_DP_VID_TIMING 0x2410 9678#define regDP3_DP_VID_TIMING_BASE_IDX 2 9679#define regDP3_DP_VID_N 0x2411 9680#define regDP3_DP_VID_N_BASE_IDX 2 9681#define regDP3_DP_VID_M 0x2412 9682#define regDP3_DP_VID_M_BASE_IDX 2 9683#define regDP3_DP_LINK_FRAMING_CNTL 0x2413 9684#define regDP3_DP_LINK_FRAMING_CNTL_BASE_IDX 2 9685#define regDP3_DP_HBR2_EYE_PATTERN 0x2414 9686#define regDP3_DP_HBR2_EYE_PATTERN_BASE_IDX 2 9687#define regDP3_DP_VID_MSA_VBID 0x2415 9688#define regDP3_DP_VID_MSA_VBID_BASE_IDX 2 9689#define regDP3_DP_VID_INTERRUPT_CNTL 0x2416 9690#define regDP3_DP_VID_INTERRUPT_CNTL_BASE_IDX 2 9691#define regDP3_DP_DPHY_CNTL 0x2417 9692#define regDP3_DP_DPHY_CNTL_BASE_IDX 2 9693#define regDP3_DP_DPHY_TRAINING_PATTERN_SEL 0x2418 9694#define regDP3_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2 9695#define regDP3_DP_DPHY_SYM0 0x2419 9696#define regDP3_DP_DPHY_SYM0_BASE_IDX 2 9697#define regDP3_DP_DPHY_SYM1 0x241a 9698#define regDP3_DP_DPHY_SYM1_BASE_IDX 2 9699#define regDP3_DP_DPHY_SYM2 0x241b 9700#define regDP3_DP_DPHY_SYM2_BASE_IDX 2 9701#define regDP3_DP_DPHY_8B10B_CNTL 0x241c 9702#define regDP3_DP_DPHY_8B10B_CNTL_BASE_IDX 2 9703#define regDP3_DP_DPHY_PRBS_CNTL 0x241d 9704#define regDP3_DP_DPHY_PRBS_CNTL_BASE_IDX 2 9705#define regDP3_DP_DPHY_SCRAM_CNTL 0x241e 9706#define regDP3_DP_DPHY_SCRAM_CNTL_BASE_IDX 2 9707#define regDP3_DP_DPHY_CRC_EN 0x241f 9708#define regDP3_DP_DPHY_CRC_EN_BASE_IDX 2 9709#define regDP3_DP_DPHY_CRC_CNTL 0x2420 9710#define regDP3_DP_DPHY_CRC_CNTL_BASE_IDX 2 9711#define regDP3_DP_DPHY_CRC_RESULT 0x2421 9712#define regDP3_DP_DPHY_CRC_RESULT_BASE_IDX 2 9713#define regDP3_DP_DPHY_CRC_MST_CNTL 0x2422 9714#define regDP3_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2 9715#define regDP3_DP_DPHY_CRC_MST_STATUS 0x2423 9716#define regDP3_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2 9717#define regDP3_DP_DPHY_FAST_TRAINING 0x2424 9718#define regDP3_DP_DPHY_FAST_TRAINING_BASE_IDX 2 9719#define regDP3_DP_DPHY_FAST_TRAINING_STATUS 0x2425 9720#define regDP3_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2 9721#define regDP3_DP_SEC_CNTL 0x242b 9722#define regDP3_DP_SEC_CNTL_BASE_IDX 2 9723#define regDP3_DP_SEC_CNTL1 0x242c 9724#define regDP3_DP_SEC_CNTL1_BASE_IDX 2 9725#define regDP3_DP_SEC_FRAMING1 0x242d 9726#define regDP3_DP_SEC_FRAMING1_BASE_IDX 2 9727#define regDP3_DP_SEC_FRAMING2 0x242e 9728#define regDP3_DP_SEC_FRAMING2_BASE_IDX 2 9729#define regDP3_DP_SEC_FRAMING3 0x242f 9730#define regDP3_DP_SEC_FRAMING3_BASE_IDX 2 9731#define regDP3_DP_SEC_FRAMING4 0x2430 9732#define regDP3_DP_SEC_FRAMING4_BASE_IDX 2 9733#define regDP3_DP_SEC_AUD_N 0x2431 9734#define regDP3_DP_SEC_AUD_N_BASE_IDX 2 9735#define regDP3_DP_SEC_AUD_N_READBACK 0x2432 9736#define regDP3_DP_SEC_AUD_N_READBACK_BASE_IDX 2 9737#define regDP3_DP_SEC_AUD_M 0x2433 9738#define regDP3_DP_SEC_AUD_M_BASE_IDX 2 9739#define regDP3_DP_SEC_AUD_M_READBACK 0x2434 9740#define regDP3_DP_SEC_AUD_M_READBACK_BASE_IDX 2 9741#define regDP3_DP_SEC_TIMESTAMP 0x2435 9742#define regDP3_DP_SEC_TIMESTAMP_BASE_IDX 2 9743#define regDP3_DP_SEC_PACKET_CNTL 0x2436 9744#define regDP3_DP_SEC_PACKET_CNTL_BASE_IDX 2 9745#define regDP3_DP_MSE_RATE_CNTL 0x2437 9746#define regDP3_DP_MSE_RATE_CNTL_BASE_IDX 2 9747#define regDP3_DP_MSE_RATE_UPDATE 0x2439 9748#define regDP3_DP_MSE_RATE_UPDATE_BASE_IDX 2 9749#define regDP3_DP_MSE_SAT0 0x243a 9750#define regDP3_DP_MSE_SAT0_BASE_IDX 2 9751#define regDP3_DP_MSE_SAT1 0x243b 9752#define regDP3_DP_MSE_SAT1_BASE_IDX 2 9753#define regDP3_DP_MSE_SAT2 0x243c 9754#define regDP3_DP_MSE_SAT2_BASE_IDX 2 9755#define regDP3_DP_MSE_SAT_UPDATE 0x243d 9756#define regDP3_DP_MSE_SAT_UPDATE_BASE_IDX 2 9757#define regDP3_DP_MSE_LINK_TIMING 0x243e 9758#define regDP3_DP_MSE_LINK_TIMING_BASE_IDX 2 9759#define regDP3_DP_MSE_MISC_CNTL 0x243f 9760#define regDP3_DP_MSE_MISC_CNTL_BASE_IDX 2 9761#define regDP3_DP_DPHY_BS_SR_SWAP_CNTL 0x2444 9762#define regDP3_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2 9763#define regDP3_DP_DPHY_HBR2_PATTERN_CONTROL 0x2445 9764#define regDP3_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2 9765#define regDP3_DP_MSE_SAT0_STATUS 0x2447 9766#define regDP3_DP_MSE_SAT0_STATUS_BASE_IDX 2 9767#define regDP3_DP_MSE_SAT1_STATUS 0x2448 9768#define regDP3_DP_MSE_SAT1_STATUS_BASE_IDX 2 9769#define regDP3_DP_MSE_SAT2_STATUS 0x2449 9770#define regDP3_DP_MSE_SAT2_STATUS_BASE_IDX 2 9771#define regDP3_DP_DPIA_SPARE 0x244a 9772#define regDP3_DP_DPIA_SPARE_BASE_IDX 2 9773#define regDP3_DP_MSA_TIMING_PARAM1 0x244c 9774#define regDP3_DP_MSA_TIMING_PARAM1_BASE_IDX 2 9775#define regDP3_DP_MSA_TIMING_PARAM2 0x244d 9776#define regDP3_DP_MSA_TIMING_PARAM2_BASE_IDX 2 9777#define regDP3_DP_MSA_TIMING_PARAM3 0x244e 9778#define regDP3_DP_MSA_TIMING_PARAM3_BASE_IDX 2 9779#define regDP3_DP_MSA_TIMING_PARAM4 0x244f 9780#define regDP3_DP_MSA_TIMING_PARAM4_BASE_IDX 2 9781#define regDP3_DP_MSO_CNTL 0x2450 9782#define regDP3_DP_MSO_CNTL_BASE_IDX 2 9783#define regDP3_DP_MSO_CNTL1 0x2451 9784#define regDP3_DP_MSO_CNTL1_BASE_IDX 2 9785#define regDP3_DP_DSC_CNTL 0x2452 9786#define regDP3_DP_DSC_CNTL_BASE_IDX 2 9787#define regDP3_DP_SEC_CNTL2 0x2453 9788#define regDP3_DP_SEC_CNTL2_BASE_IDX 2 9789#define regDP3_DP_SEC_CNTL3 0x2454 9790#define regDP3_DP_SEC_CNTL3_BASE_IDX 2 9791#define regDP3_DP_SEC_CNTL4 0x2455 9792#define regDP3_DP_SEC_CNTL4_BASE_IDX 2 9793#define regDP3_DP_SEC_CNTL5 0x2456 9794#define regDP3_DP_SEC_CNTL5_BASE_IDX 2 9795#define regDP3_DP_SEC_CNTL6 0x2457 9796#define regDP3_DP_SEC_CNTL6_BASE_IDX 2 9797#define regDP3_DP_SEC_CNTL7 0x2458 9798#define regDP3_DP_SEC_CNTL7_BASE_IDX 2 9799#define regDP3_DP_DB_CNTL 0x2459 9800#define regDP3_DP_DB_CNTL_BASE_IDX 2 9801#define regDP3_DP_MSA_VBID_MISC 0x245a 9802#define regDP3_DP_MSA_VBID_MISC_BASE_IDX 2 9803#define regDP3_DP_SEC_METADATA_TRANSMISSION 0x245b 9804#define regDP3_DP_SEC_METADATA_TRANSMISSION_BASE_IDX 2 9805#define regDP3_DP_ALPM_CNTL 0x245d 9806#define regDP3_DP_ALPM_CNTL_BASE_IDX 2 9807#define regDP3_DP_GSP8_CNTL 0x245e 9808#define regDP3_DP_GSP8_CNTL_BASE_IDX 2 9809#define regDP3_DP_GSP9_CNTL 0x245f 9810#define regDP3_DP_GSP9_CNTL_BASE_IDX 2 9811#define regDP3_DP_GSP10_CNTL 0x2460 9812#define regDP3_DP_GSP10_CNTL_BASE_IDX 2 9813#define regDP3_DP_GSP11_CNTL 0x2461 9814#define regDP3_DP_GSP11_CNTL_BASE_IDX 2 9815#define regDP3_DP_GSP_EN_DB_STATUS 0x2462 9816#define regDP3_DP_GSP_EN_DB_STATUS_BASE_IDX 2 9817#define regDP3_DP_AUXLESS_ALPM_CNTL1 0x2463 9818#define regDP3_DP_AUXLESS_ALPM_CNTL1_BASE_IDX 2 9819#define regDP3_DP_AUXLESS_ALPM_CNTL2 0x2464 9820#define regDP3_DP_AUXLESS_ALPM_CNTL2_BASE_IDX 2 9821#define regDP3_DP_AUXLESS_ALPM_CNTL3 0x2465 9822#define regDP3_DP_AUXLESS_ALPM_CNTL3_BASE_IDX 2 9823#define regDP3_DP_AUXLESS_ALPM_CNTL4 0x2466 9824#define regDP3_DP_AUXLESS_ALPM_CNTL4_BASE_IDX 2 9825#define regDP3_DP_AUXLESS_ALPM_CNTL5 0x2467 9826#define regDP3_DP_AUXLESS_ALPM_CNTL5_BASE_IDX 2 9827 9828 9829// addressBlock: dcn_dc_dio_dig3_dispdec 9830// base address: 0xc00 9831#define regDIG3_DIG_FE_CNTL 0x238b 9832#define regDIG3_DIG_FE_CNTL_BASE_IDX 2 9833#define regDIG3_DIG_OUTPUT_CRC_CNTL 0x238c 9834#define regDIG3_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2 9835#define regDIG3_DIG_OUTPUT_CRC_RESULT 0x238d 9836#define regDIG3_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2 9837#define regDIG3_DIG_CLOCK_PATTERN 0x238e 9838#define regDIG3_DIG_CLOCK_PATTERN_BASE_IDX 2 9839#define regDIG3_DIG_TEST_PATTERN 0x238f 9840#define regDIG3_DIG_TEST_PATTERN_BASE_IDX 2 9841#define regDIG3_DIG_RANDOM_PATTERN_SEED 0x2390 9842#define regDIG3_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2 9843#define regDIG3_DIG_FIFO_CTRL0 0x2391 9844#define regDIG3_DIG_FIFO_CTRL0_BASE_IDX 2 9845#define regDIG3_DIG_FIFO_CTRL1 0x2392 9846#define regDIG3_DIG_FIFO_CTRL1_BASE_IDX 2 9847#define regDIG3_HDMI_METADATA_PACKET_CONTROL 0x2393 9848#define regDIG3_HDMI_METADATA_PACKET_CONTROL_BASE_IDX 2 9849#define regDIG3_HDMI_CONTROL 0x2394 9850#define regDIG3_HDMI_CONTROL_BASE_IDX 2 9851#define regDIG3_HDMI_STATUS 0x2395 9852#define regDIG3_HDMI_STATUS_BASE_IDX 2 9853#define regDIG3_HDMI_AUDIO_PACKET_CONTROL 0x2396 9854#define regDIG3_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2 9855#define regDIG3_HDMI_ACR_PACKET_CONTROL 0x2397 9856#define regDIG3_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2 9857#define regDIG3_HDMI_VBI_PACKET_CONTROL 0x2398 9858#define regDIG3_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2 9859#define regDIG3_HDMI_INFOFRAME_CONTROL0 0x2399 9860#define regDIG3_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2 9861#define regDIG3_HDMI_INFOFRAME_CONTROL1 0x239a 9862#define regDIG3_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2 9863#define regDIG3_HDMI_GENERIC_PACKET_CONTROL0 0x239b 9864#define regDIG3_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2 9865#define regDIG3_HDMI_GENERIC_PACKET_CONTROL6 0x239c 9866#define regDIG3_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX 2 9867#define regDIG3_HDMI_GENERIC_PACKET_CONTROL5 0x239d 9868#define regDIG3_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX 2 9869#define regDIG3_HDMI_GC 0x239e 9870#define regDIG3_HDMI_GC_BASE_IDX 2 9871#define regDIG3_HDMI_GENERIC_PACKET_CONTROL1 0x239f 9872#define regDIG3_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2 9873#define regDIG3_HDMI_GENERIC_PACKET_CONTROL2 0x23a0 9874#define regDIG3_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2 9875#define regDIG3_HDMI_GENERIC_PACKET_CONTROL3 0x23a1 9876#define regDIG3_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2 9877#define regDIG3_HDMI_GENERIC_PACKET_CONTROL4 0x23a2 9878#define regDIG3_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX 2 9879#define regDIG3_HDMI_GENERIC_PACKET_CONTROL7 0x23a3 9880#define regDIG3_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX 2 9881#define regDIG3_HDMI_GENERIC_PACKET_CONTROL8 0x23a4 9882#define regDIG3_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX 2 9883#define regDIG3_HDMI_GENERIC_PACKET_CONTROL9 0x23a5 9884#define regDIG3_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX 2 9885#define regDIG3_HDMI_GENERIC_PACKET_CONTROL10 0x23a6 9886#define regDIG3_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX 2 9887#define regDIG3_HDMI_DB_CONTROL 0x23a7 9888#define regDIG3_HDMI_DB_CONTROL_BASE_IDX 2 9889#define regDIG3_HDMI_ACR_32_0 0x23a8 9890#define regDIG3_HDMI_ACR_32_0_BASE_IDX 2 9891#define regDIG3_HDMI_ACR_32_1 0x23a9 9892#define regDIG3_HDMI_ACR_32_1_BASE_IDX 2 9893#define regDIG3_HDMI_ACR_44_0 0x23aa 9894#define regDIG3_HDMI_ACR_44_0_BASE_IDX 2 9895#define regDIG3_HDMI_ACR_44_1 0x23ab 9896#define regDIG3_HDMI_ACR_44_1_BASE_IDX 2 9897#define regDIG3_HDMI_ACR_48_0 0x23ac 9898#define regDIG3_HDMI_ACR_48_0_BASE_IDX 2 9899#define regDIG3_HDMI_ACR_48_1 0x23ad 9900#define regDIG3_HDMI_ACR_48_1_BASE_IDX 2 9901#define regDIG3_HDMI_ACR_STATUS_0 0x23ae 9902#define regDIG3_HDMI_ACR_STATUS_0_BASE_IDX 2 9903#define regDIG3_HDMI_ACR_STATUS_1 0x23af 9904#define regDIG3_HDMI_ACR_STATUS_1_BASE_IDX 2 9905#define regDIG3_AFMT_CNTL 0x23b0 9906#define regDIG3_AFMT_CNTL_BASE_IDX 2 9907#define regDIG3_DIG_BE_CNTL 0x23b1 9908#define regDIG3_DIG_BE_CNTL_BASE_IDX 2 9909#define regDIG3_DIG_BE_EN_CNTL 0x23b2 9910#define regDIG3_DIG_BE_EN_CNTL_BASE_IDX 2 9911#define regDIG3_TMDS_CNTL 0x23d8 9912#define regDIG3_TMDS_CNTL_BASE_IDX 2 9913#define regDIG3_TMDS_CONTROL_CHAR 0x23d9 9914#define regDIG3_TMDS_CONTROL_CHAR_BASE_IDX 2 9915#define regDIG3_TMDS_CONTROL0_FEEDBACK 0x23da 9916#define regDIG3_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2 9917#define regDIG3_TMDS_STEREOSYNC_CTL_SEL 0x23db 9918#define regDIG3_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2 9919#define regDIG3_TMDS_SYNC_CHAR_PATTERN_0_1 0x23dc 9920#define regDIG3_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2 9921#define regDIG3_TMDS_SYNC_CHAR_PATTERN_2_3 0x23dd 9922#define regDIG3_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2 9923#define regDIG3_TMDS_CTL_BITS 0x23df 9924#define regDIG3_TMDS_CTL_BITS_BASE_IDX 2 9925#define regDIG3_TMDS_DCBALANCER_CONTROL 0x23e0 9926#define regDIG3_TMDS_DCBALANCER_CONTROL_BASE_IDX 2 9927#define regDIG3_TMDS_SYNC_DCBALANCE_CHAR 0x23e1 9928#define regDIG3_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX 2 9929#define regDIG3_TMDS_CTL0_1_GEN_CNTL 0x23e2 9930#define regDIG3_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2 9931#define regDIG3_TMDS_CTL2_3_GEN_CNTL 0x23e3 9932#define regDIG3_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2 9933#define regDIG3_DIG_VERSION 0x23e5 9934#define regDIG3_DIG_VERSION_BASE_IDX 2 9935#define regDIG3_FORCE_DIG_DISABLE 0x23e6 9936#define regDIG3_FORCE_DIG_DISABLE_BASE_IDX 2 9937 9938 9939// addressBlock: dcn_dc_dio_dp4_dispdec 9940// base address: 0x1000 9941#define regDP4_DP_LINK_CNTL 0x2508 9942#define regDP4_DP_LINK_CNTL_BASE_IDX 2 9943#define regDP4_DP_PIXEL_FORMAT 0x2509 9944#define regDP4_DP_PIXEL_FORMAT_BASE_IDX 2 9945#define regDP4_DP_MSA_COLORIMETRY 0x250a 9946#define regDP4_DP_MSA_COLORIMETRY_BASE_IDX 2 9947#define regDP4_DP_CONFIG 0x250b 9948#define regDP4_DP_CONFIG_BASE_IDX 2 9949#define regDP4_DP_VID_STREAM_CNTL 0x250c 9950#define regDP4_DP_VID_STREAM_CNTL_BASE_IDX 2 9951#define regDP4_DP_STEER_FIFO 0x250d 9952#define regDP4_DP_STEER_FIFO_BASE_IDX 2 9953#define regDP4_DP_MSA_MISC 0x250e 9954#define regDP4_DP_MSA_MISC_BASE_IDX 2 9955#define regDP4_DP_DPHY_INTERNAL_CTRL 0x250f 9956#define regDP4_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 9957#define regDP4_DP_VID_TIMING 0x2510 9958#define regDP4_DP_VID_TIMING_BASE_IDX 2 9959#define regDP4_DP_VID_N 0x2511 9960#define regDP4_DP_VID_N_BASE_IDX 2 9961#define regDP4_DP_VID_M 0x2512 9962#define regDP4_DP_VID_M_BASE_IDX 2 9963#define regDP4_DP_LINK_FRAMING_CNTL 0x2513 9964#define regDP4_DP_LINK_FRAMING_CNTL_BASE_IDX 2 9965#define regDP4_DP_HBR2_EYE_PATTERN 0x2514 9966#define regDP4_DP_HBR2_EYE_PATTERN_BASE_IDX 2 9967#define regDP4_DP_VID_MSA_VBID 0x2515 9968#define regDP4_DP_VID_MSA_VBID_BASE_IDX 2 9969#define regDP4_DP_VID_INTERRUPT_CNTL 0x2516 9970#define regDP4_DP_VID_INTERRUPT_CNTL_BASE_IDX 2 9971#define regDP4_DP_DPHY_CNTL 0x2517 9972#define regDP4_DP_DPHY_CNTL_BASE_IDX 2 9973#define regDP4_DP_DPHY_TRAINING_PATTERN_SEL 0x2518 9974#define regDP4_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2 9975#define regDP4_DP_DPHY_SYM0 0x2519 9976#define regDP4_DP_DPHY_SYM0_BASE_IDX 2 9977#define regDP4_DP_DPHY_SYM1 0x251a 9978#define regDP4_DP_DPHY_SYM1_BASE_IDX 2 9979#define regDP4_DP_DPHY_SYM2 0x251b 9980#define regDP4_DP_DPHY_SYM2_BASE_IDX 2 9981#define regDP4_DP_DPHY_8B10B_CNTL 0x251c 9982#define regDP4_DP_DPHY_8B10B_CNTL_BASE_IDX 2 9983#define regDP4_DP_DPHY_PRBS_CNTL 0x251d 9984#define regDP4_DP_DPHY_PRBS_CNTL_BASE_IDX 2 9985#define regDP4_DP_DPHY_SCRAM_CNTL 0x251e 9986#define regDP4_DP_DPHY_SCRAM_CNTL_BASE_IDX 2 9987#define regDP4_DP_DPHY_CRC_EN 0x251f 9988#define regDP4_DP_DPHY_CRC_EN_BASE_IDX 2 9989#define regDP4_DP_DPHY_CRC_CNTL 0x2520 9990#define regDP4_DP_DPHY_CRC_CNTL_BASE_IDX 2 9991#define regDP4_DP_DPHY_CRC_RESULT 0x2521 9992#define regDP4_DP_DPHY_CRC_RESULT_BASE_IDX 2 9993#define regDP4_DP_DPHY_CRC_MST_CNTL 0x2522 9994#define regDP4_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2 9995#define regDP4_DP_DPHY_CRC_MST_STATUS 0x2523 9996#define regDP4_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2 9997#define regDP4_DP_DPHY_FAST_TRAINING 0x2524 9998#define regDP4_DP_DPHY_FAST_TRAINING_BASE_IDX 2 9999#define regDP4_DP_DPHY_FAST_TRAINING_STATUS 0x2525 10000#define regDP4_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2 10001#define regDP4_DP_SEC_CNTL 0x252b 10002#define regDP4_DP_SEC_CNTL_BASE_IDX 2 10003#define regDP4_DP_SEC_CNTL1 0x252c 10004#define regDP4_DP_SEC_CNTL1_BASE_IDX 2 10005#define regDP4_DP_SEC_FRAMING1 0x252d 10006#define regDP4_DP_SEC_FRAMING1_BASE_IDX 2 10007#define regDP4_DP_SEC_FRAMING2 0x252e 10008#define regDP4_DP_SEC_FRAMING2_BASE_IDX 2 10009#define regDP4_DP_SEC_FRAMING3 0x252f 10010#define regDP4_DP_SEC_FRAMING3_BASE_IDX 2 10011#define regDP4_DP_SEC_FRAMING4 0x2530 10012#define regDP4_DP_SEC_FRAMING4_BASE_IDX 2 10013#define regDP4_DP_SEC_AUD_N 0x2531 10014#define regDP4_DP_SEC_AUD_N_BASE_IDX 2 10015#define regDP4_DP_SEC_AUD_N_READBACK 0x2532 10016#define regDP4_DP_SEC_AUD_N_READBACK_BASE_IDX 2 10017#define regDP4_DP_SEC_AUD_M 0x2533 10018#define regDP4_DP_SEC_AUD_M_BASE_IDX 2 10019#define regDP4_DP_SEC_AUD_M_READBACK 0x2534 10020#define regDP4_DP_SEC_AUD_M_READBACK_BASE_IDX 2 10021#define regDP4_DP_SEC_TIMESTAMP 0x2535 10022#define regDP4_DP_SEC_TIMESTAMP_BASE_IDX 2 10023#define regDP4_DP_SEC_PACKET_CNTL 0x2536 10024#define regDP4_DP_SEC_PACKET_CNTL_BASE_IDX 2 10025#define regDP4_DP_MSE_RATE_CNTL 0x2537 10026#define regDP4_DP_MSE_RATE_CNTL_BASE_IDX 2 10027#define regDP4_DP_MSE_RATE_UPDATE 0x2539 10028#define regDP4_DP_MSE_RATE_UPDATE_BASE_IDX 2 10029#define regDP4_DP_MSE_SAT0 0x253a 10030#define regDP4_DP_MSE_SAT0_BASE_IDX 2 10031#define regDP4_DP_MSE_SAT1 0x253b 10032#define regDP4_DP_MSE_SAT1_BASE_IDX 2 10033#define regDP4_DP_MSE_SAT2 0x253c 10034#define regDP4_DP_MSE_SAT2_BASE_IDX 2 10035#define regDP4_DP_MSE_SAT_UPDATE 0x253d 10036#define regDP4_DP_MSE_SAT_UPDATE_BASE_IDX 2 10037#define regDP4_DP_MSE_LINK_TIMING 0x253e 10038#define regDP4_DP_MSE_LINK_TIMING_BASE_IDX 2 10039#define regDP4_DP_MSE_MISC_CNTL 0x253f 10040#define regDP4_DP_MSE_MISC_CNTL_BASE_IDX 2 10041#define regDP4_DP_DPHY_BS_SR_SWAP_CNTL 0x2544 10042#define regDP4_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2 10043#define regDP4_DP_DPHY_HBR2_PATTERN_CONTROL 0x2545 10044#define regDP4_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2 10045#define regDP4_DP_MSE_SAT0_STATUS 0x2547 10046#define regDP4_DP_MSE_SAT0_STATUS_BASE_IDX 2 10047#define regDP4_DP_MSE_SAT1_STATUS 0x2548 10048#define regDP4_DP_MSE_SAT1_STATUS_BASE_IDX 2 10049#define regDP4_DP_MSE_SAT2_STATUS 0x2549 10050#define regDP4_DP_MSE_SAT2_STATUS_BASE_IDX 2 10051#define regDP4_DP_DPIA_SPARE 0x254a 10052#define regDP4_DP_DPIA_SPARE_BASE_IDX 2 10053#define regDP4_DP_MSA_TIMING_PARAM1 0x254c 10054#define regDP4_DP_MSA_TIMING_PARAM1_BASE_IDX 2 10055#define regDP4_DP_MSA_TIMING_PARAM2 0x254d 10056#define regDP4_DP_MSA_TIMING_PARAM2_BASE_IDX 2 10057#define regDP4_DP_MSA_TIMING_PARAM3 0x254e 10058#define regDP4_DP_MSA_TIMING_PARAM3_BASE_IDX 2 10059#define regDP4_DP_MSA_TIMING_PARAM4 0x254f 10060#define regDP4_DP_MSA_TIMING_PARAM4_BASE_IDX 2 10061#define regDP4_DP_MSO_CNTL 0x2550 10062#define regDP4_DP_MSO_CNTL_BASE_IDX 2 10063#define regDP4_DP_MSO_CNTL1 0x2551 10064#define regDP4_DP_MSO_CNTL1_BASE_IDX 2 10065#define regDP4_DP_DSC_CNTL 0x2552 10066#define regDP4_DP_DSC_CNTL_BASE_IDX 2 10067#define regDP4_DP_SEC_CNTL2 0x2553 10068#define regDP4_DP_SEC_CNTL2_BASE_IDX 2 10069#define regDP4_DP_SEC_CNTL3 0x2554 10070#define regDP4_DP_SEC_CNTL3_BASE_IDX 2 10071#define regDP4_DP_SEC_CNTL4 0x2555 10072#define regDP4_DP_SEC_CNTL4_BASE_IDX 2 10073#define regDP4_DP_SEC_CNTL5 0x2556 10074#define regDP4_DP_SEC_CNTL5_BASE_IDX 2 10075#define regDP4_DP_SEC_CNTL6 0x2557 10076#define regDP4_DP_SEC_CNTL6_BASE_IDX 2 10077#define regDP4_DP_SEC_CNTL7 0x2558 10078#define regDP4_DP_SEC_CNTL7_BASE_IDX 2 10079#define regDP4_DP_DB_CNTL 0x2559 10080#define regDP4_DP_DB_CNTL_BASE_IDX 2 10081#define regDP4_DP_MSA_VBID_MISC 0x255a 10082#define regDP4_DP_MSA_VBID_MISC_BASE_IDX 2 10083#define regDP4_DP_SEC_METADATA_TRANSMISSION 0x255b 10084#define regDP4_DP_SEC_METADATA_TRANSMISSION_BASE_IDX 2 10085#define regDP4_DP_ALPM_CNTL 0x255d 10086#define regDP4_DP_ALPM_CNTL_BASE_IDX 2 10087#define regDP4_DP_GSP8_CNTL 0x255e 10088#define regDP4_DP_GSP8_CNTL_BASE_IDX 2 10089#define regDP4_DP_GSP9_CNTL 0x255f 10090#define regDP4_DP_GSP9_CNTL_BASE_IDX 2 10091#define regDP4_DP_GSP10_CNTL 0x2560 10092#define regDP4_DP_GSP10_CNTL_BASE_IDX 2 10093#define regDP4_DP_GSP11_CNTL 0x2561 10094#define regDP4_DP_GSP11_CNTL_BASE_IDX 2 10095#define regDP4_DP_GSP_EN_DB_STATUS 0x2562 10096#define regDP4_DP_GSP_EN_DB_STATUS_BASE_IDX 2 10097#define regDP4_DP_AUXLESS_ALPM_CNTL1 0x2563 10098#define regDP4_DP_AUXLESS_ALPM_CNTL1_BASE_IDX 2 10099#define regDP4_DP_AUXLESS_ALPM_CNTL2 0x2564 10100#define regDP4_DP_AUXLESS_ALPM_CNTL2_BASE_IDX 2 10101#define regDP4_DP_AUXLESS_ALPM_CNTL3 0x2565 10102#define regDP4_DP_AUXLESS_ALPM_CNTL3_BASE_IDX 2 10103#define regDP4_DP_AUXLESS_ALPM_CNTL4 0x2566 10104#define regDP4_DP_AUXLESS_ALPM_CNTL4_BASE_IDX 2 10105#define regDP4_DP_AUXLESS_ALPM_CNTL5 0x2567 10106#define regDP4_DP_AUXLESS_ALPM_CNTL5_BASE_IDX 2 10107 10108 10109// addressBlock: dcn_dc_dio_dig4_dispdec 10110// base address: 0x1000 10111#define regDIG4_DIG_FE_CNTL 0x248b 10112#define regDIG4_DIG_FE_CNTL_BASE_IDX 2 10113#define regDIG4_DIG_OUTPUT_CRC_CNTL 0x248c 10114#define regDIG4_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2 10115#define regDIG4_DIG_OUTPUT_CRC_RESULT 0x248d 10116#define regDIG4_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2 10117#define regDIG4_DIG_CLOCK_PATTERN 0x248e 10118#define regDIG4_DIG_CLOCK_PATTERN_BASE_IDX 2 10119#define regDIG4_DIG_TEST_PATTERN 0x248f 10120#define regDIG4_DIG_TEST_PATTERN_BASE_IDX 2 10121#define regDIG4_DIG_RANDOM_PATTERN_SEED 0x2490 10122#define regDIG4_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2 10123#define regDIG4_DIG_FIFO_CTRL0 0x2491 10124#define regDIG4_DIG_FIFO_CTRL0_BASE_IDX 2 10125#define regDIG4_DIG_FIFO_CTRL1 0x2492 10126#define regDIG4_DIG_FIFO_CTRL1_BASE_IDX 2 10127#define regDIG4_HDMI_METADATA_PACKET_CONTROL 0x2493 10128#define regDIG4_HDMI_METADATA_PACKET_CONTROL_BASE_IDX 2 10129#define regDIG4_HDMI_CONTROL 0x2494 10130#define regDIG4_HDMI_CONTROL_BASE_IDX 2 10131#define regDIG4_HDMI_STATUS 0x2495 10132#define regDIG4_HDMI_STATUS_BASE_IDX 2 10133#define regDIG4_HDMI_AUDIO_PACKET_CONTROL 0x2496 10134#define regDIG4_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2 10135#define regDIG4_HDMI_ACR_PACKET_CONTROL 0x2497 10136#define regDIG4_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2 10137#define regDIG4_HDMI_VBI_PACKET_CONTROL 0x2498 10138#define regDIG4_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2 10139#define regDIG4_HDMI_INFOFRAME_CONTROL0 0x2499 10140#define regDIG4_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2 10141#define regDIG4_HDMI_INFOFRAME_CONTROL1 0x249a 10142#define regDIG4_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2 10143#define regDIG4_HDMI_GENERIC_PACKET_CONTROL0 0x249b 10144#define regDIG4_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2 10145#define regDIG4_HDMI_GENERIC_PACKET_CONTROL6 0x249c 10146#define regDIG4_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX 2 10147#define regDIG4_HDMI_GENERIC_PACKET_CONTROL5 0x249d 10148#define regDIG4_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX 2 10149#define regDIG4_HDMI_GC 0x249e 10150#define regDIG4_HDMI_GC_BASE_IDX 2 10151#define regDIG4_HDMI_GENERIC_PACKET_CONTROL1 0x249f 10152#define regDIG4_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2 10153#define regDIG4_HDMI_GENERIC_PACKET_CONTROL2 0x24a0 10154#define regDIG4_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2 10155#define regDIG4_HDMI_GENERIC_PACKET_CONTROL3 0x24a1 10156#define regDIG4_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2 10157#define regDIG4_HDMI_GENERIC_PACKET_CONTROL4 0x24a2 10158#define regDIG4_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX 2 10159#define regDIG4_HDMI_GENERIC_PACKET_CONTROL7 0x24a3 10160#define regDIG4_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX 2 10161#define regDIG4_HDMI_GENERIC_PACKET_CONTROL8 0x24a4 10162#define regDIG4_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX 2 10163#define regDIG4_HDMI_GENERIC_PACKET_CONTROL9 0x24a5 10164#define regDIG4_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX 2 10165#define regDIG4_HDMI_GENERIC_PACKET_CONTROL10 0x24a6 10166#define regDIG4_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX 2 10167#define regDIG4_HDMI_DB_CONTROL 0x24a7 10168#define regDIG4_HDMI_DB_CONTROL_BASE_IDX 2 10169#define regDIG4_HDMI_ACR_32_0 0x24a8 10170#define regDIG4_HDMI_ACR_32_0_BASE_IDX 2 10171#define regDIG4_HDMI_ACR_32_1 0x24a9 10172#define regDIG4_HDMI_ACR_32_1_BASE_IDX 2 10173#define regDIG4_HDMI_ACR_44_0 0x24aa 10174#define regDIG4_HDMI_ACR_44_0_BASE_IDX 2 10175#define regDIG4_HDMI_ACR_44_1 0x24ab 10176#define regDIG4_HDMI_ACR_44_1_BASE_IDX 2 10177#define regDIG4_HDMI_ACR_48_0 0x24ac 10178#define regDIG4_HDMI_ACR_48_0_BASE_IDX 2 10179#define regDIG4_HDMI_ACR_48_1 0x24ad 10180#define regDIG4_HDMI_ACR_48_1_BASE_IDX 2 10181#define regDIG4_HDMI_ACR_STATUS_0 0x24ae 10182#define regDIG4_HDMI_ACR_STATUS_0_BASE_IDX 2 10183#define regDIG4_HDMI_ACR_STATUS_1 0x24af 10184#define regDIG4_HDMI_ACR_STATUS_1_BASE_IDX 2 10185#define regDIG4_AFMT_CNTL 0x24b0 10186#define regDIG4_AFMT_CNTL_BASE_IDX 2 10187#define regDIG4_DIG_BE_CNTL 0x24b1 10188#define regDIG4_DIG_BE_CNTL_BASE_IDX 2 10189#define regDIG4_DIG_BE_EN_CNTL 0x24b2 10190#define regDIG4_DIG_BE_EN_CNTL_BASE_IDX 2 10191#define regDIG4_TMDS_CNTL 0x24d8 10192#define regDIG4_TMDS_CNTL_BASE_IDX 2 10193#define regDIG4_TMDS_CONTROL_CHAR 0x24d9 10194#define regDIG4_TMDS_CONTROL_CHAR_BASE_IDX 2 10195#define regDIG4_TMDS_CONTROL0_FEEDBACK 0x24da 10196#define regDIG4_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2 10197#define regDIG4_TMDS_STEREOSYNC_CTL_SEL 0x24db 10198#define regDIG4_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2 10199#define regDIG4_TMDS_SYNC_CHAR_PATTERN_0_1 0x24dc 10200#define regDIG4_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2 10201#define regDIG4_TMDS_SYNC_CHAR_PATTERN_2_3 0x24dd 10202#define regDIG4_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2 10203#define regDIG4_TMDS_CTL_BITS 0x24df 10204#define regDIG4_TMDS_CTL_BITS_BASE_IDX 2 10205#define regDIG4_TMDS_DCBALANCER_CONTROL 0x24e0 10206#define regDIG4_TMDS_DCBALANCER_CONTROL_BASE_IDX 2 10207#define regDIG4_TMDS_SYNC_DCBALANCE_CHAR 0x24e1 10208#define regDIG4_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX 2 10209#define regDIG4_TMDS_CTL0_1_GEN_CNTL 0x24e2 10210#define regDIG4_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2 10211#define regDIG4_TMDS_CTL2_3_GEN_CNTL 0x24e3 10212#define regDIG4_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2 10213#define regDIG4_DIG_VERSION 0x24e5 10214#define regDIG4_DIG_VERSION_BASE_IDX 2 10215#define regDIG4_FORCE_DIG_DISABLE 0x24e6 10216#define regDIG4_FORCE_DIG_DISABLE_BASE_IDX 2 10217 10218 10219// addressBlock: dcn_dc_dio_dig0_afmt_afmt_dispdec 10220// base address: 0x154cc 10221#define regAFMT0_AFMT_VBI_PACKET_CONTROL 0x2074 10222#define regAFMT0_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2 10223#define regAFMT0_AFMT_AUDIO_PACKET_CONTROL2 0x2075 10224#define regAFMT0_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2 10225#define regAFMT0_AFMT_AUDIO_INFO0 0x2076 10226#define regAFMT0_AFMT_AUDIO_INFO0_BASE_IDX 2 10227#define regAFMT0_AFMT_AUDIO_INFO1 0x2077 10228#define regAFMT0_AFMT_AUDIO_INFO1_BASE_IDX 2 10229#define regAFMT0_AFMT_60958_0 0x2078 10230#define regAFMT0_AFMT_60958_0_BASE_IDX 2 10231#define regAFMT0_AFMT_60958_1 0x2079 10232#define regAFMT0_AFMT_60958_1_BASE_IDX 2 10233#define regAFMT0_AFMT_AUDIO_CRC_CONTROL 0x207a 10234#define regAFMT0_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2 10235#define regAFMT0_AFMT_RAMP_CONTROL0 0x207b 10236#define regAFMT0_AFMT_RAMP_CONTROL0_BASE_IDX 2 10237#define regAFMT0_AFMT_RAMP_CONTROL1 0x207c 10238#define regAFMT0_AFMT_RAMP_CONTROL1_BASE_IDX 2 10239#define regAFMT0_AFMT_RAMP_CONTROL2 0x207d 10240#define regAFMT0_AFMT_RAMP_CONTROL2_BASE_IDX 2 10241#define regAFMT0_AFMT_RAMP_CONTROL3 0x207e 10242#define regAFMT0_AFMT_RAMP_CONTROL3_BASE_IDX 2 10243#define regAFMT0_AFMT_60958_2 0x207f 10244#define regAFMT0_AFMT_60958_2_BASE_IDX 2 10245#define regAFMT0_AFMT_AUDIO_CRC_RESULT 0x2080 10246#define regAFMT0_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2 10247#define regAFMT0_AFMT_STATUS 0x2081 10248#define regAFMT0_AFMT_STATUS_BASE_IDX 2 10249#define regAFMT0_AFMT_AUDIO_PACKET_CONTROL 0x2082 10250#define regAFMT0_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2 10251#define regAFMT0_AFMT_INFOFRAME_CONTROL0 0x2083 10252#define regAFMT0_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2 10253#define regAFMT0_AFMT_INTERRUPT_STATUS 0x2084 10254#define regAFMT0_AFMT_INTERRUPT_STATUS_BASE_IDX 2 10255#define regAFMT0_AFMT_AUDIO_SRC_CONTROL 0x2085 10256#define regAFMT0_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2 10257#define regAFMT0_AFMT_MEM_PWR 0x2087 10258#define regAFMT0_AFMT_MEM_PWR_BASE_IDX 2 10259 10260 10261// addressBlock: dcn_dc_dio_dig1_afmt_afmt_dispdec 10262// base address: 0x158cc 10263#define regAFMT1_AFMT_VBI_PACKET_CONTROL 0x2174 10264#define regAFMT1_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2 10265#define regAFMT1_AFMT_AUDIO_PACKET_CONTROL2 0x2175 10266#define regAFMT1_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2 10267#define regAFMT1_AFMT_AUDIO_INFO0 0x2176 10268#define regAFMT1_AFMT_AUDIO_INFO0_BASE_IDX 2 10269#define regAFMT1_AFMT_AUDIO_INFO1 0x2177 10270#define regAFMT1_AFMT_AUDIO_INFO1_BASE_IDX 2 10271#define regAFMT1_AFMT_60958_0 0x2178 10272#define regAFMT1_AFMT_60958_0_BASE_IDX 2 10273#define regAFMT1_AFMT_60958_1 0x2179 10274#define regAFMT1_AFMT_60958_1_BASE_IDX 2 10275#define regAFMT1_AFMT_AUDIO_CRC_CONTROL 0x217a 10276#define regAFMT1_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2 10277#define regAFMT1_AFMT_RAMP_CONTROL0 0x217b 10278#define regAFMT1_AFMT_RAMP_CONTROL0_BASE_IDX 2 10279#define regAFMT1_AFMT_RAMP_CONTROL1 0x217c 10280#define regAFMT1_AFMT_RAMP_CONTROL1_BASE_IDX 2 10281#define regAFMT1_AFMT_RAMP_CONTROL2 0x217d 10282#define regAFMT1_AFMT_RAMP_CONTROL2_BASE_IDX 2 10283#define regAFMT1_AFMT_RAMP_CONTROL3 0x217e 10284#define regAFMT1_AFMT_RAMP_CONTROL3_BASE_IDX 2 10285#define regAFMT1_AFMT_60958_2 0x217f 10286#define regAFMT1_AFMT_60958_2_BASE_IDX 2 10287#define regAFMT1_AFMT_AUDIO_CRC_RESULT 0x2180 10288#define regAFMT1_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2 10289#define regAFMT1_AFMT_STATUS 0x2181 10290#define regAFMT1_AFMT_STATUS_BASE_IDX 2 10291#define regAFMT1_AFMT_AUDIO_PACKET_CONTROL 0x2182 10292#define regAFMT1_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2 10293#define regAFMT1_AFMT_INFOFRAME_CONTROL0 0x2183 10294#define regAFMT1_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2 10295#define regAFMT1_AFMT_INTERRUPT_STATUS 0x2184 10296#define regAFMT1_AFMT_INTERRUPT_STATUS_BASE_IDX 2 10297#define regAFMT1_AFMT_AUDIO_SRC_CONTROL 0x2185 10298#define regAFMT1_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2 10299#define regAFMT1_AFMT_MEM_PWR 0x2187 10300#define regAFMT1_AFMT_MEM_PWR_BASE_IDX 2 10301 10302 10303// addressBlock: dcn_dc_dio_dig2_afmt_afmt_dispdec 10304// base address: 0x15ccc 10305#define regAFMT2_AFMT_VBI_PACKET_CONTROL 0x2274 10306#define regAFMT2_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2 10307#define regAFMT2_AFMT_AUDIO_PACKET_CONTROL2 0x2275 10308#define regAFMT2_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2 10309#define regAFMT2_AFMT_AUDIO_INFO0 0x2276 10310#define regAFMT2_AFMT_AUDIO_INFO0_BASE_IDX 2 10311#define regAFMT2_AFMT_AUDIO_INFO1 0x2277 10312#define regAFMT2_AFMT_AUDIO_INFO1_BASE_IDX 2 10313#define regAFMT2_AFMT_60958_0 0x2278 10314#define regAFMT2_AFMT_60958_0_BASE_IDX 2 10315#define regAFMT2_AFMT_60958_1 0x2279 10316#define regAFMT2_AFMT_60958_1_BASE_IDX 2 10317#define regAFMT2_AFMT_AUDIO_CRC_CONTROL 0x227a 10318#define regAFMT2_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2 10319#define regAFMT2_AFMT_RAMP_CONTROL0 0x227b 10320#define regAFMT2_AFMT_RAMP_CONTROL0_BASE_IDX 2 10321#define regAFMT2_AFMT_RAMP_CONTROL1 0x227c 10322#define regAFMT2_AFMT_RAMP_CONTROL1_BASE_IDX 2 10323#define regAFMT2_AFMT_RAMP_CONTROL2 0x227d 10324#define regAFMT2_AFMT_RAMP_CONTROL2_BASE_IDX 2 10325#define regAFMT2_AFMT_RAMP_CONTROL3 0x227e 10326#define regAFMT2_AFMT_RAMP_CONTROL3_BASE_IDX 2 10327#define regAFMT2_AFMT_60958_2 0x227f 10328#define regAFMT2_AFMT_60958_2_BASE_IDX 2 10329#define regAFMT2_AFMT_AUDIO_CRC_RESULT 0x2280 10330#define regAFMT2_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2 10331#define regAFMT2_AFMT_STATUS 0x2281 10332#define regAFMT2_AFMT_STATUS_BASE_IDX 2 10333#define regAFMT2_AFMT_AUDIO_PACKET_CONTROL 0x2282 10334#define regAFMT2_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2 10335#define regAFMT2_AFMT_INFOFRAME_CONTROL0 0x2283 10336#define regAFMT2_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2 10337#define regAFMT2_AFMT_INTERRUPT_STATUS 0x2284 10338#define regAFMT2_AFMT_INTERRUPT_STATUS_BASE_IDX 2 10339#define regAFMT2_AFMT_AUDIO_SRC_CONTROL 0x2285 10340#define regAFMT2_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2 10341#define regAFMT2_AFMT_MEM_PWR 0x2287 10342#define regAFMT2_AFMT_MEM_PWR_BASE_IDX 2 10343 10344 10345// addressBlock: dcn_dc_dio_dig3_afmt_afmt_dispdec 10346// base address: 0x160cc 10347#define regAFMT3_AFMT_VBI_PACKET_CONTROL 0x2374 10348#define regAFMT3_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2 10349#define regAFMT3_AFMT_AUDIO_PACKET_CONTROL2 0x2375 10350#define regAFMT3_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2 10351#define regAFMT3_AFMT_AUDIO_INFO0 0x2376 10352#define regAFMT3_AFMT_AUDIO_INFO0_BASE_IDX 2 10353#define regAFMT3_AFMT_AUDIO_INFO1 0x2377 10354#define regAFMT3_AFMT_AUDIO_INFO1_BASE_IDX 2 10355#define regAFMT3_AFMT_60958_0 0x2378 10356#define regAFMT3_AFMT_60958_0_BASE_IDX 2 10357#define regAFMT3_AFMT_60958_1 0x2379 10358#define regAFMT3_AFMT_60958_1_BASE_IDX 2 10359#define regAFMT3_AFMT_AUDIO_CRC_CONTROL 0x237a 10360#define regAFMT3_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2 10361#define regAFMT3_AFMT_RAMP_CONTROL0 0x237b 10362#define regAFMT3_AFMT_RAMP_CONTROL0_BASE_IDX 2 10363#define regAFMT3_AFMT_RAMP_CONTROL1 0x237c 10364#define regAFMT3_AFMT_RAMP_CONTROL1_BASE_IDX 2 10365#define regAFMT3_AFMT_RAMP_CONTROL2 0x237d 10366#define regAFMT3_AFMT_RAMP_CONTROL2_BASE_IDX 2 10367#define regAFMT3_AFMT_RAMP_CONTROL3 0x237e 10368#define regAFMT3_AFMT_RAMP_CONTROL3_BASE_IDX 2 10369#define regAFMT3_AFMT_60958_2 0x237f 10370#define regAFMT3_AFMT_60958_2_BASE_IDX 2 10371#define regAFMT3_AFMT_AUDIO_CRC_RESULT 0x2380 10372#define regAFMT3_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2 10373#define regAFMT3_AFMT_STATUS 0x2381 10374#define regAFMT3_AFMT_STATUS_BASE_IDX 2 10375#define regAFMT3_AFMT_AUDIO_PACKET_CONTROL 0x2382 10376#define regAFMT3_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2 10377#define regAFMT3_AFMT_INFOFRAME_CONTROL0 0x2383 10378#define regAFMT3_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2 10379#define regAFMT3_AFMT_INTERRUPT_STATUS 0x2384 10380#define regAFMT3_AFMT_INTERRUPT_STATUS_BASE_IDX 2 10381#define regAFMT3_AFMT_AUDIO_SRC_CONTROL 0x2385 10382#define regAFMT3_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2 10383#define regAFMT3_AFMT_MEM_PWR 0x2387 10384#define regAFMT3_AFMT_MEM_PWR_BASE_IDX 2 10385 10386 10387// addressBlock: dcn_dc_dio_dig4_afmt_afmt_dispdec 10388// base address: 0x164cc 10389#define regAFMT4_AFMT_VBI_PACKET_CONTROL 0x2474 10390#define regAFMT4_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2 10391#define regAFMT4_AFMT_AUDIO_PACKET_CONTROL2 0x2475 10392#define regAFMT4_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2 10393#define regAFMT4_AFMT_AUDIO_INFO0 0x2476 10394#define regAFMT4_AFMT_AUDIO_INFO0_BASE_IDX 2 10395#define regAFMT4_AFMT_AUDIO_INFO1 0x2477 10396#define regAFMT4_AFMT_AUDIO_INFO1_BASE_IDX 2 10397#define regAFMT4_AFMT_60958_0 0x2478 10398#define regAFMT4_AFMT_60958_0_BASE_IDX 2 10399#define regAFMT4_AFMT_60958_1 0x2479 10400#define regAFMT4_AFMT_60958_1_BASE_IDX 2 10401#define regAFMT4_AFMT_AUDIO_CRC_CONTROL 0x247a 10402#define regAFMT4_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2 10403#define regAFMT4_AFMT_RAMP_CONTROL0 0x247b 10404#define regAFMT4_AFMT_RAMP_CONTROL0_BASE_IDX 2 10405#define regAFMT4_AFMT_RAMP_CONTROL1 0x247c 10406#define regAFMT4_AFMT_RAMP_CONTROL1_BASE_IDX 2 10407#define regAFMT4_AFMT_RAMP_CONTROL2 0x247d 10408#define regAFMT4_AFMT_RAMP_CONTROL2_BASE_IDX 2 10409#define regAFMT4_AFMT_RAMP_CONTROL3 0x247e 10410#define regAFMT4_AFMT_RAMP_CONTROL3_BASE_IDX 2 10411#define regAFMT4_AFMT_60958_2 0x247f 10412#define regAFMT4_AFMT_60958_2_BASE_IDX 2 10413#define regAFMT4_AFMT_AUDIO_CRC_RESULT 0x2480 10414#define regAFMT4_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2 10415#define regAFMT4_AFMT_STATUS 0x2481 10416#define regAFMT4_AFMT_STATUS_BASE_IDX 2 10417#define regAFMT4_AFMT_AUDIO_PACKET_CONTROL 0x2482 10418#define regAFMT4_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2 10419#define regAFMT4_AFMT_INFOFRAME_CONTROL0 0x2483 10420#define regAFMT4_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2 10421#define regAFMT4_AFMT_INTERRUPT_STATUS 0x2484 10422#define regAFMT4_AFMT_INTERRUPT_STATUS_BASE_IDX 2 10423#define regAFMT4_AFMT_AUDIO_SRC_CONTROL 0x2485 10424#define regAFMT4_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2 10425#define regAFMT4_AFMT_MEM_PWR 0x2487 10426#define regAFMT4_AFMT_MEM_PWR_BASE_IDX 2 10427 10428 10429// addressBlock: dcn_dc_dio_dig0_dme_dme_dispdec 10430// base address: 0x15524 10431#define regDME0_DME_CONTROL 0x2089 10432#define regDME0_DME_CONTROL_BASE_IDX 2 10433#define regDME0_DME_MEMORY_CONTROL 0x208a 10434#define regDME0_DME_MEMORY_CONTROL_BASE_IDX 2 10435 10436 10437// addressBlock: dcn_dc_dio_dig0_vpg_vpg_dispdec 10438// base address: 0x154a0 10439#define regVPG0_VPG_GENERIC_PACKET_ACCESS_CTRL 0x2068 10440#define regVPG0_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2 10441#define regVPG0_VPG_GENERIC_PACKET_DATA 0x2069 10442#define regVPG0_VPG_GENERIC_PACKET_DATA_BASE_IDX 2 10443#define regVPG0_VPG_GSP_FRAME_UPDATE_CTRL 0x206a 10444#define regVPG0_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2 10445#define regVPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x206b 10446#define regVPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2 10447#define regVPG0_VPG_GENERIC_STATUS 0x206c 10448#define regVPG0_VPG_GENERIC_STATUS_BASE_IDX 2 10449#define regVPG0_VPG_MEM_PWR 0x206d 10450#define regVPG0_VPG_MEM_PWR_BASE_IDX 2 10451#define regVPG0_VPG_ISRC1_2_ACCESS_CTRL 0x206e 10452#define regVPG0_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2 10453#define regVPG0_VPG_ISRC1_2_DATA 0x206f 10454#define regVPG0_VPG_ISRC1_2_DATA_BASE_IDX 2 10455#define regVPG0_VPG_MPEG_INFO0 0x2070 10456#define regVPG0_VPG_MPEG_INFO0_BASE_IDX 2 10457#define regVPG0_VPG_MPEG_INFO1 0x2071 10458#define regVPG0_VPG_MPEG_INFO1_BASE_IDX 2 10459 10460 10461// addressBlock: dcn_dc_dio_dig1_dme_dme_dispdec 10462// base address: 0x15924 10463#define regDME1_DME_CONTROL 0x2189 10464#define regDME1_DME_CONTROL_BASE_IDX 2 10465#define regDME1_DME_MEMORY_CONTROL 0x218a 10466#define regDME1_DME_MEMORY_CONTROL_BASE_IDX 2 10467 10468 10469// addressBlock: dcn_dc_dio_dig1_vpg_vpg_dispdec 10470// base address: 0x158a0 10471#define regVPG1_VPG_GENERIC_PACKET_ACCESS_CTRL 0x2168 10472#define regVPG1_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2 10473#define regVPG1_VPG_GENERIC_PACKET_DATA 0x2169 10474#define regVPG1_VPG_GENERIC_PACKET_DATA_BASE_IDX 2 10475#define regVPG1_VPG_GSP_FRAME_UPDATE_CTRL 0x216a 10476#define regVPG1_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2 10477#define regVPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x216b 10478#define regVPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2 10479#define regVPG1_VPG_GENERIC_STATUS 0x216c 10480#define regVPG1_VPG_GENERIC_STATUS_BASE_IDX 2 10481#define regVPG1_VPG_MEM_PWR 0x216d 10482#define regVPG1_VPG_MEM_PWR_BASE_IDX 2 10483#define regVPG1_VPG_ISRC1_2_ACCESS_CTRL 0x216e 10484#define regVPG1_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2 10485#define regVPG1_VPG_ISRC1_2_DATA 0x216f 10486#define regVPG1_VPG_ISRC1_2_DATA_BASE_IDX 2 10487#define regVPG1_VPG_MPEG_INFO0 0x2170 10488#define regVPG1_VPG_MPEG_INFO0_BASE_IDX 2 10489#define regVPG1_VPG_MPEG_INFO1 0x2171 10490#define regVPG1_VPG_MPEG_INFO1_BASE_IDX 2 10491 10492 10493// addressBlock: dcn_dc_dio_dig2_dme_dme_dispdec 10494// base address: 0x15d24 10495#define regDME2_DME_CONTROL 0x2289 10496#define regDME2_DME_CONTROL_BASE_IDX 2 10497#define regDME2_DME_MEMORY_CONTROL 0x228a 10498#define regDME2_DME_MEMORY_CONTROL_BASE_IDX 2 10499 10500 10501// addressBlock: dcn_dc_dio_dig2_vpg_vpg_dispdec 10502// base address: 0x15ca0 10503#define regVPG2_VPG_GENERIC_PACKET_ACCESS_CTRL 0x2268 10504#define regVPG2_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2 10505#define regVPG2_VPG_GENERIC_PACKET_DATA 0x2269 10506#define regVPG2_VPG_GENERIC_PACKET_DATA_BASE_IDX 2 10507#define regVPG2_VPG_GSP_FRAME_UPDATE_CTRL 0x226a 10508#define regVPG2_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2 10509#define regVPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x226b 10510#define regVPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2 10511#define regVPG2_VPG_GENERIC_STATUS 0x226c 10512#define regVPG2_VPG_GENERIC_STATUS_BASE_IDX 2 10513#define regVPG2_VPG_MEM_PWR 0x226d 10514#define regVPG2_VPG_MEM_PWR_BASE_IDX 2 10515#define regVPG2_VPG_ISRC1_2_ACCESS_CTRL 0x226e 10516#define regVPG2_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2 10517#define regVPG2_VPG_ISRC1_2_DATA 0x226f 10518#define regVPG2_VPG_ISRC1_2_DATA_BASE_IDX 2 10519#define regVPG2_VPG_MPEG_INFO0 0x2270 10520#define regVPG2_VPG_MPEG_INFO0_BASE_IDX 2 10521#define regVPG2_VPG_MPEG_INFO1 0x2271 10522#define regVPG2_VPG_MPEG_INFO1_BASE_IDX 2 10523 10524 10525// addressBlock: dcn_dc_dio_dig3_dme_dme_dispdec 10526// base address: 0x16124 10527#define regDME3_DME_CONTROL 0x2389 10528#define regDME3_DME_CONTROL_BASE_IDX 2 10529#define regDME3_DME_MEMORY_CONTROL 0x238a 10530#define regDME3_DME_MEMORY_CONTROL_BASE_IDX 2 10531 10532 10533// addressBlock: dcn_dc_dio_dig3_vpg_vpg_dispdec 10534// base address: 0x160a0 10535#define regVPG3_VPG_GENERIC_PACKET_ACCESS_CTRL 0x2368 10536#define regVPG3_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2 10537#define regVPG3_VPG_GENERIC_PACKET_DATA 0x2369 10538#define regVPG3_VPG_GENERIC_PACKET_DATA_BASE_IDX 2 10539#define regVPG3_VPG_GSP_FRAME_UPDATE_CTRL 0x236a 10540#define regVPG3_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2 10541#define regVPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x236b 10542#define regVPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2 10543#define regVPG3_VPG_GENERIC_STATUS 0x236c 10544#define regVPG3_VPG_GENERIC_STATUS_BASE_IDX 2 10545#define regVPG3_VPG_MEM_PWR 0x236d 10546#define regVPG3_VPG_MEM_PWR_BASE_IDX 2 10547#define regVPG3_VPG_ISRC1_2_ACCESS_CTRL 0x236e 10548#define regVPG3_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2 10549#define regVPG3_VPG_ISRC1_2_DATA 0x236f 10550#define regVPG3_VPG_ISRC1_2_DATA_BASE_IDX 2 10551#define regVPG3_VPG_MPEG_INFO0 0x2370 10552#define regVPG3_VPG_MPEG_INFO0_BASE_IDX 2 10553#define regVPG3_VPG_MPEG_INFO1 0x2371 10554#define regVPG3_VPG_MPEG_INFO1_BASE_IDX 2 10555 10556 10557// addressBlock: dcn_dc_dio_dig4_dme_dme_dispdec 10558// base address: 0x16524 10559#define regDME4_DME_CONTROL 0x2489 10560#define regDME4_DME_CONTROL_BASE_IDX 2 10561#define regDME4_DME_MEMORY_CONTROL 0x248a 10562#define regDME4_DME_MEMORY_CONTROL_BASE_IDX 2 10563 10564 10565// addressBlock: dcn_dc_dio_dig4_vpg_vpg_dispdec 10566// base address: 0x164a0 10567#define regVPG4_VPG_GENERIC_PACKET_ACCESS_CTRL 0x2468 10568#define regVPG4_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2 10569#define regVPG4_VPG_GENERIC_PACKET_DATA 0x2469 10570#define regVPG4_VPG_GENERIC_PACKET_DATA_BASE_IDX 2 10571#define regVPG4_VPG_GSP_FRAME_UPDATE_CTRL 0x246a 10572#define regVPG4_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2 10573#define regVPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x246b 10574#define regVPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2 10575#define regVPG4_VPG_GENERIC_STATUS 0x246c 10576#define regVPG4_VPG_GENERIC_STATUS_BASE_IDX 2 10577#define regVPG4_VPG_MEM_PWR 0x246d 10578#define regVPG4_VPG_MEM_PWR_BASE_IDX 2 10579#define regVPG4_VPG_ISRC1_2_ACCESS_CTRL 0x246e 10580#define regVPG4_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2 10581#define regVPG4_VPG_ISRC1_2_DATA 0x246f 10582#define regVPG4_VPG_ISRC1_2_DATA_BASE_IDX 2 10583#define regVPG4_VPG_MPEG_INFO0 0x2470 10584#define regVPG4_VPG_MPEG_INFO0_BASE_IDX 2 10585#define regVPG4_VPG_MPEG_INFO1 0x2471 10586#define regVPG4_VPG_MPEG_INFO1_BASE_IDX 2 10587 10588 10589// addressBlock: dcn_dc_dio_dp_aux0_dispdec 10590// base address: 0x0 10591#define regDP_AUX0_AUX_CONTROL 0x1f50 10592#define regDP_AUX0_AUX_CONTROL_BASE_IDX 2 10593#define regDP_AUX0_AUX_SW_CONTROL 0x1f51 10594#define regDP_AUX0_AUX_SW_CONTROL_BASE_IDX 2 10595#define regDP_AUX0_AUX_ARB_CONTROL 0x1f52 10596#define regDP_AUX0_AUX_ARB_CONTROL_BASE_IDX 2 10597#define regDP_AUX0_AUX_INTERRUPT_CONTROL 0x1f53 10598#define regDP_AUX0_AUX_INTERRUPT_CONTROL_BASE_IDX 2 10599#define regDP_AUX0_AUX_SW_STATUS 0x1f54 10600#define regDP_AUX0_AUX_SW_STATUS_BASE_IDX 2 10601#define regDP_AUX0_AUX_LS_STATUS 0x1f55 10602#define regDP_AUX0_AUX_LS_STATUS_BASE_IDX 2 10603#define regDP_AUX0_AUX_SW_DATA 0x1f56 10604#define regDP_AUX0_AUX_SW_DATA_BASE_IDX 2 10605#define regDP_AUX0_AUX_LS_DATA 0x1f57 10606#define regDP_AUX0_AUX_LS_DATA_BASE_IDX 2 10607#define regDP_AUX0_AUX_DPHY_TX_REF_CONTROL 0x1f58 10608#define regDP_AUX0_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2 10609#define regDP_AUX0_AUX_DPHY_TX_CONTROL 0x1f59 10610#define regDP_AUX0_AUX_DPHY_TX_CONTROL_BASE_IDX 2 10611#define regDP_AUX0_AUX_DPHY_RX_CONTROL0 0x1f5a 10612#define regDP_AUX0_AUX_DPHY_RX_CONTROL0_BASE_IDX 2 10613#define regDP_AUX0_AUX_DPHY_RX_CONTROL1 0x1f5b 10614#define regDP_AUX0_AUX_DPHY_RX_CONTROL1_BASE_IDX 2 10615#define regDP_AUX0_AUX_DPHY_TX_STATUS 0x1f5c 10616#define regDP_AUX0_AUX_DPHY_TX_STATUS_BASE_IDX 2 10617#define regDP_AUX0_AUX_DPHY_RX_STATUS 0x1f5d 10618#define regDP_AUX0_AUX_DPHY_RX_STATUS_BASE_IDX 2 10619#define regDP_AUX0_AUX_GTC_SYNC_CONTROL 0x1f5e 10620#define regDP_AUX0_AUX_GTC_SYNC_CONTROL_BASE_IDX 2 10621#define regDP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL 0x1f5f 10622#define regDP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2 10623#define regDP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1f60 10624#define regDP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2 10625#define regDP_AUX0_AUX_GTC_SYNC_STATUS 0x1f61 10626#define regDP_AUX0_AUX_GTC_SYNC_STATUS_BASE_IDX 2 10627#define regDP_AUX0_AUX_PHY_WAKE_CNTL 0x1f66 10628#define regDP_AUX0_AUX_PHY_WAKE_CNTL_BASE_IDX 2 10629 10630 10631// addressBlock: dcn_dc_dio_dp_aux1_dispdec 10632// base address: 0x70 10633#define regDP_AUX1_AUX_CONTROL 0x1f6c 10634#define regDP_AUX1_AUX_CONTROL_BASE_IDX 2 10635#define regDP_AUX1_AUX_SW_CONTROL 0x1f6d 10636#define regDP_AUX1_AUX_SW_CONTROL_BASE_IDX 2 10637#define regDP_AUX1_AUX_ARB_CONTROL 0x1f6e 10638#define regDP_AUX1_AUX_ARB_CONTROL_BASE_IDX 2 10639#define regDP_AUX1_AUX_INTERRUPT_CONTROL 0x1f6f 10640#define regDP_AUX1_AUX_INTERRUPT_CONTROL_BASE_IDX 2 10641#define regDP_AUX1_AUX_SW_STATUS 0x1f70 10642#define regDP_AUX1_AUX_SW_STATUS_BASE_IDX 2 10643#define regDP_AUX1_AUX_LS_STATUS 0x1f71 10644#define regDP_AUX1_AUX_LS_STATUS_BASE_IDX 2 10645#define regDP_AUX1_AUX_SW_DATA 0x1f72 10646#define regDP_AUX1_AUX_SW_DATA_BASE_IDX 2 10647#define regDP_AUX1_AUX_LS_DATA 0x1f73 10648#define regDP_AUX1_AUX_LS_DATA_BASE_IDX 2 10649#define regDP_AUX1_AUX_DPHY_TX_REF_CONTROL 0x1f74 10650#define regDP_AUX1_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2 10651#define regDP_AUX1_AUX_DPHY_TX_CONTROL 0x1f75 10652#define regDP_AUX1_AUX_DPHY_TX_CONTROL_BASE_IDX 2 10653#define regDP_AUX1_AUX_DPHY_RX_CONTROL0 0x1f76 10654#define regDP_AUX1_AUX_DPHY_RX_CONTROL0_BASE_IDX 2 10655#define regDP_AUX1_AUX_DPHY_RX_CONTROL1 0x1f77 10656#define regDP_AUX1_AUX_DPHY_RX_CONTROL1_BASE_IDX 2 10657#define regDP_AUX1_AUX_DPHY_TX_STATUS 0x1f78 10658#define regDP_AUX1_AUX_DPHY_TX_STATUS_BASE_IDX 2 10659#define regDP_AUX1_AUX_DPHY_RX_STATUS 0x1f79 10660#define regDP_AUX1_AUX_DPHY_RX_STATUS_BASE_IDX 2 10661#define regDP_AUX1_AUX_GTC_SYNC_CONTROL 0x1f7a 10662#define regDP_AUX1_AUX_GTC_SYNC_CONTROL_BASE_IDX 2 10663#define regDP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL 0x1f7b 10664#define regDP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2 10665#define regDP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1f7c 10666#define regDP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2 10667#define regDP_AUX1_AUX_GTC_SYNC_STATUS 0x1f7d 10668#define regDP_AUX1_AUX_GTC_SYNC_STATUS_BASE_IDX 2 10669#define regDP_AUX1_AUX_PHY_WAKE_CNTL 0x1f82 10670#define regDP_AUX1_AUX_PHY_WAKE_CNTL_BASE_IDX 2 10671 10672 10673// addressBlock: dcn_dc_dio_dp_aux2_dispdec 10674// base address: 0xe0 10675#define regDP_AUX2_AUX_CONTROL 0x1f88 10676#define regDP_AUX2_AUX_CONTROL_BASE_IDX 2 10677#define regDP_AUX2_AUX_SW_CONTROL 0x1f89 10678#define regDP_AUX2_AUX_SW_CONTROL_BASE_IDX 2 10679#define regDP_AUX2_AUX_ARB_CONTROL 0x1f8a 10680#define regDP_AUX2_AUX_ARB_CONTROL_BASE_IDX 2 10681#define regDP_AUX2_AUX_INTERRUPT_CONTROL 0x1f8b 10682#define regDP_AUX2_AUX_INTERRUPT_CONTROL_BASE_IDX 2 10683#define regDP_AUX2_AUX_SW_STATUS 0x1f8c 10684#define regDP_AUX2_AUX_SW_STATUS_BASE_IDX 2 10685#define regDP_AUX2_AUX_LS_STATUS 0x1f8d 10686#define regDP_AUX2_AUX_LS_STATUS_BASE_IDX 2 10687#define regDP_AUX2_AUX_SW_DATA 0x1f8e 10688#define regDP_AUX2_AUX_SW_DATA_BASE_IDX 2 10689#define regDP_AUX2_AUX_LS_DATA 0x1f8f 10690#define regDP_AUX2_AUX_LS_DATA_BASE_IDX 2 10691#define regDP_AUX2_AUX_DPHY_TX_REF_CONTROL 0x1f90 10692#define regDP_AUX2_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2 10693#define regDP_AUX2_AUX_DPHY_TX_CONTROL 0x1f91 10694#define regDP_AUX2_AUX_DPHY_TX_CONTROL_BASE_IDX 2 10695#define regDP_AUX2_AUX_DPHY_RX_CONTROL0 0x1f92 10696#define regDP_AUX2_AUX_DPHY_RX_CONTROL0_BASE_IDX 2 10697#define regDP_AUX2_AUX_DPHY_RX_CONTROL1 0x1f93 10698#define regDP_AUX2_AUX_DPHY_RX_CONTROL1_BASE_IDX 2 10699#define regDP_AUX2_AUX_DPHY_TX_STATUS 0x1f94 10700#define regDP_AUX2_AUX_DPHY_TX_STATUS_BASE_IDX 2 10701#define regDP_AUX2_AUX_DPHY_RX_STATUS 0x1f95 10702#define regDP_AUX2_AUX_DPHY_RX_STATUS_BASE_IDX 2 10703#define regDP_AUX2_AUX_GTC_SYNC_CONTROL 0x1f96 10704#define regDP_AUX2_AUX_GTC_SYNC_CONTROL_BASE_IDX 2 10705#define regDP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL 0x1f97 10706#define regDP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2 10707#define regDP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1f98 10708#define regDP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2 10709#define regDP_AUX2_AUX_GTC_SYNC_STATUS 0x1f99 10710#define regDP_AUX2_AUX_GTC_SYNC_STATUS_BASE_IDX 2 10711#define regDP_AUX2_AUX_PHY_WAKE_CNTL 0x1f9e 10712#define regDP_AUX2_AUX_PHY_WAKE_CNTL_BASE_IDX 2 10713 10714 10715// addressBlock: dcn_dc_dio_dp_aux3_dispdec 10716// base address: 0x150 10717#define regDP_AUX3_AUX_CONTROL 0x1fa4 10718#define regDP_AUX3_AUX_CONTROL_BASE_IDX 2 10719#define regDP_AUX3_AUX_SW_CONTROL 0x1fa5 10720#define regDP_AUX3_AUX_SW_CONTROL_BASE_IDX 2 10721#define regDP_AUX3_AUX_ARB_CONTROL 0x1fa6 10722#define regDP_AUX3_AUX_ARB_CONTROL_BASE_IDX 2 10723#define regDP_AUX3_AUX_INTERRUPT_CONTROL 0x1fa7 10724#define regDP_AUX3_AUX_INTERRUPT_CONTROL_BASE_IDX 2 10725#define regDP_AUX3_AUX_SW_STATUS 0x1fa8 10726#define regDP_AUX3_AUX_SW_STATUS_BASE_IDX 2 10727#define regDP_AUX3_AUX_LS_STATUS 0x1fa9 10728#define regDP_AUX3_AUX_LS_STATUS_BASE_IDX 2 10729#define regDP_AUX3_AUX_SW_DATA 0x1faa 10730#define regDP_AUX3_AUX_SW_DATA_BASE_IDX 2 10731#define regDP_AUX3_AUX_LS_DATA 0x1fab 10732#define regDP_AUX3_AUX_LS_DATA_BASE_IDX 2 10733#define regDP_AUX3_AUX_DPHY_TX_REF_CONTROL 0x1fac 10734#define regDP_AUX3_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2 10735#define regDP_AUX3_AUX_DPHY_TX_CONTROL 0x1fad 10736#define regDP_AUX3_AUX_DPHY_TX_CONTROL_BASE_IDX 2 10737#define regDP_AUX3_AUX_DPHY_RX_CONTROL0 0x1fae 10738#define regDP_AUX3_AUX_DPHY_RX_CONTROL0_BASE_IDX 2 10739#define regDP_AUX3_AUX_DPHY_RX_CONTROL1 0x1faf 10740#define regDP_AUX3_AUX_DPHY_RX_CONTROL1_BASE_IDX 2 10741#define regDP_AUX3_AUX_DPHY_TX_STATUS 0x1fb0 10742#define regDP_AUX3_AUX_DPHY_TX_STATUS_BASE_IDX 2 10743#define regDP_AUX3_AUX_DPHY_RX_STATUS 0x1fb1 10744#define regDP_AUX3_AUX_DPHY_RX_STATUS_BASE_IDX 2 10745#define regDP_AUX3_AUX_GTC_SYNC_CONTROL 0x1fb2 10746#define regDP_AUX3_AUX_GTC_SYNC_CONTROL_BASE_IDX 2 10747#define regDP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL 0x1fb3 10748#define regDP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2 10749#define regDP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1fb4 10750#define regDP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2 10751#define regDP_AUX3_AUX_GTC_SYNC_STATUS 0x1fb5 10752#define regDP_AUX3_AUX_GTC_SYNC_STATUS_BASE_IDX 2 10753#define regDP_AUX3_AUX_PHY_WAKE_CNTL 0x1fba 10754#define regDP_AUX3_AUX_PHY_WAKE_CNTL_BASE_IDX 2 10755 10756 10757// addressBlock: dcn_dc_dio_dp_aux4_dispdec 10758// base address: 0x1c0 10759#define regDP_AUX4_AUX_CONTROL 0x1fc0 10760#define regDP_AUX4_AUX_CONTROL_BASE_IDX 2 10761#define regDP_AUX4_AUX_SW_CONTROL 0x1fc1 10762#define regDP_AUX4_AUX_SW_CONTROL_BASE_IDX 2 10763#define regDP_AUX4_AUX_ARB_CONTROL 0x1fc2 10764#define regDP_AUX4_AUX_ARB_CONTROL_BASE_IDX 2 10765#define regDP_AUX4_AUX_INTERRUPT_CONTROL 0x1fc3 10766#define regDP_AUX4_AUX_INTERRUPT_CONTROL_BASE_IDX 2 10767#define regDP_AUX4_AUX_SW_STATUS 0x1fc4 10768#define regDP_AUX4_AUX_SW_STATUS_BASE_IDX 2 10769#define regDP_AUX4_AUX_LS_STATUS 0x1fc5 10770#define regDP_AUX4_AUX_LS_STATUS_BASE_IDX 2 10771#define regDP_AUX4_AUX_SW_DATA 0x1fc6 10772#define regDP_AUX4_AUX_SW_DATA_BASE_IDX 2 10773#define regDP_AUX4_AUX_LS_DATA 0x1fc7 10774#define regDP_AUX4_AUX_LS_DATA_BASE_IDX 2 10775#define regDP_AUX4_AUX_DPHY_TX_REF_CONTROL 0x1fc8 10776#define regDP_AUX4_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2 10777#define regDP_AUX4_AUX_DPHY_TX_CONTROL 0x1fc9 10778#define regDP_AUX4_AUX_DPHY_TX_CONTROL_BASE_IDX 2 10779#define regDP_AUX4_AUX_DPHY_RX_CONTROL0 0x1fca 10780#define regDP_AUX4_AUX_DPHY_RX_CONTROL0_BASE_IDX 2 10781#define regDP_AUX4_AUX_DPHY_RX_CONTROL1 0x1fcb 10782#define regDP_AUX4_AUX_DPHY_RX_CONTROL1_BASE_IDX 2 10783#define regDP_AUX4_AUX_DPHY_TX_STATUS 0x1fcc 10784#define regDP_AUX4_AUX_DPHY_TX_STATUS_BASE_IDX 2 10785#define regDP_AUX4_AUX_DPHY_RX_STATUS 0x1fcd 10786#define regDP_AUX4_AUX_DPHY_RX_STATUS_BASE_IDX 2 10787#define regDP_AUX4_AUX_GTC_SYNC_CONTROL 0x1fce 10788#define regDP_AUX4_AUX_GTC_SYNC_CONTROL_BASE_IDX 2 10789#define regDP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL 0x1fcf 10790#define regDP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2 10791#define regDP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1fd0 10792#define regDP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2 10793#define regDP_AUX4_AUX_GTC_SYNC_STATUS 0x1fd1 10794#define regDP_AUX4_AUX_GTC_SYNC_STATUS_BASE_IDX 2 10795#define regDP_AUX4_AUX_PHY_WAKE_CNTL 0x1fd6 10796#define regDP_AUX4_AUX_PHY_WAKE_CNTL_BASE_IDX 2 10797 10798 10799// addressBlock: dcn_dc_dio_dout_i2c_dispdec 10800// base address: 0x0 10801#define regDC_I2C_CONTROL 0x1e98 10802#define regDC_I2C_CONTROL_BASE_IDX 2 10803#define regDC_I2C_ARBITRATION 0x1e99 10804#define regDC_I2C_ARBITRATION_BASE_IDX 2 10805#define regDC_I2C_INTERRUPT_CONTROL 0x1e9a 10806#define regDC_I2C_INTERRUPT_CONTROL_BASE_IDX 2 10807#define regDC_I2C_SW_STATUS 0x1e9b 10808#define regDC_I2C_SW_STATUS_BASE_IDX 2 10809#define regDC_I2C_DDC1_HW_STATUS 0x1e9c 10810#define regDC_I2C_DDC1_HW_STATUS_BASE_IDX 2 10811#define regDC_I2C_DDC2_HW_STATUS 0x1e9d 10812#define regDC_I2C_DDC2_HW_STATUS_BASE_IDX 2 10813#define regDC_I2C_DDC3_HW_STATUS 0x1e9e 10814#define regDC_I2C_DDC3_HW_STATUS_BASE_IDX 2 10815#define regDC_I2C_DDC4_HW_STATUS 0x1e9f 10816#define regDC_I2C_DDC4_HW_STATUS_BASE_IDX 2 10817#define regDC_I2C_DDC5_HW_STATUS 0x1ea0 10818#define regDC_I2C_DDC5_HW_STATUS_BASE_IDX 2 10819#define regDC_I2C_DDC1_SPEED 0x1ea2 10820#define regDC_I2C_DDC1_SPEED_BASE_IDX 2 10821#define regDC_I2C_DDC1_SETUP 0x1ea3 10822#define regDC_I2C_DDC1_SETUP_BASE_IDX 2 10823#define regDC_I2C_DDC2_SPEED 0x1ea4 10824#define regDC_I2C_DDC2_SPEED_BASE_IDX 2 10825#define regDC_I2C_DDC2_SETUP 0x1ea5 10826#define regDC_I2C_DDC2_SETUP_BASE_IDX 2 10827#define regDC_I2C_DDC3_SPEED 0x1ea6 10828#define regDC_I2C_DDC3_SPEED_BASE_IDX 2 10829#define regDC_I2C_DDC3_SETUP 0x1ea7 10830#define regDC_I2C_DDC3_SETUP_BASE_IDX 2 10831#define regDC_I2C_DDC4_SPEED 0x1ea8 10832#define regDC_I2C_DDC4_SPEED_BASE_IDX 2 10833#define regDC_I2C_DDC4_SETUP 0x1ea9 10834#define regDC_I2C_DDC4_SETUP_BASE_IDX 2 10835#define regDC_I2C_DDC5_SPEED 0x1eaa 10836#define regDC_I2C_DDC5_SPEED_BASE_IDX 2 10837#define regDC_I2C_DDC5_SETUP 0x1eab 10838#define regDC_I2C_DDC5_SETUP_BASE_IDX 2 10839#define regDC_I2C_TRANSACTION0 0x1eae 10840#define regDC_I2C_TRANSACTION0_BASE_IDX 2 10841#define regDC_I2C_TRANSACTION1 0x1eaf 10842#define regDC_I2C_TRANSACTION1_BASE_IDX 2 10843#define regDC_I2C_TRANSACTION2 0x1eb0 10844#define regDC_I2C_TRANSACTION2_BASE_IDX 2 10845#define regDC_I2C_TRANSACTION3 0x1eb1 10846#define regDC_I2C_TRANSACTION3_BASE_IDX 2 10847#define regDC_I2C_DATA 0x1eb2 10848#define regDC_I2C_DATA_BASE_IDX 2 10849#define regDC_I2C_EDID_DETECT_CTRL 0x1eb6 10850#define regDC_I2C_EDID_DETECT_CTRL_BASE_IDX 2 10851#define regDC_I2C_READ_REQUEST_INTERRUPT 0x1eb7 10852#define regDC_I2C_READ_REQUEST_INTERRUPT_BASE_IDX 2 10853 10854 10855// addressBlock: dcn_dc_dio_dio_misc_dispdec 10856// base address: 0x0 10857#define regDIO_SCRATCH0 0x1eca 10858#define regDIO_SCRATCH0_BASE_IDX 2 10859#define regDIO_SCRATCH1 0x1ecb 10860#define regDIO_SCRATCH1_BASE_IDX 2 10861#define regDIO_SCRATCH2 0x1ecc 10862#define regDIO_SCRATCH2_BASE_IDX 2 10863#define regDIO_SCRATCH3 0x1ecd 10864#define regDIO_SCRATCH3_BASE_IDX 2 10865#define regDIO_SCRATCH4 0x1ece 10866#define regDIO_SCRATCH4_BASE_IDX 2 10867#define regDIO_SCRATCH5 0x1ecf 10868#define regDIO_SCRATCH5_BASE_IDX 2 10869#define regDIO_SCRATCH6 0x1ed0 10870#define regDIO_SCRATCH6_BASE_IDX 2 10871#define regDIO_SCRATCH7 0x1ed1 10872#define regDIO_SCRATCH7_BASE_IDX 2 10873#define regDIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS 0x1ed3 10874#define regDIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS_BASE_IDX 2 10875#define regDIO_MEM_PWR_STATUS 0x1edd 10876#define regDIO_MEM_PWR_STATUS_BASE_IDX 2 10877#define regDIO_MEM_PWR_CTRL 0x1ede 10878#define regDIO_MEM_PWR_CTRL_BASE_IDX 2 10879#define regDIO_MEM_PWR_CTRL2 0x1edf 10880#define regDIO_MEM_PWR_CTRL2_BASE_IDX 2 10881#define regDIO_CLK_CNTL 0x1ee0 10882#define regDIO_CLK_CNTL_BASE_IDX 2 10883#define regDIO_POWER_MANAGEMENT_CNTL 0x1ee4 10884#define regDIO_POWER_MANAGEMENT_CNTL_BASE_IDX 2 10885#define regDIG_SOFT_RESET 0x1eee 10886#define regDIG_SOFT_RESET_BASE_IDX 2 10887#define regDIO_CLK_CNTL2 0x1ef2 10888#define regDIO_CLK_CNTL2_BASE_IDX 2 10889#define regDIO_CLK_CNTL3 0x1ef3 10890#define regDIO_CLK_CNTL3_BASE_IDX 2 10891#define regDIO_HDMI_RXSTATUS_TIMER_CONTROL 0x1eff 10892#define regDIO_HDMI_RXSTATUS_TIMER_CONTROL_BASE_IDX 2 10893#define regDIO_LINKA_CNTL 0x1f04 10894#define regDIO_LINKA_CNTL_BASE_IDX 2 10895#define regDIO_LINKB_CNTL 0x1f05 10896#define regDIO_LINKB_CNTL_BASE_IDX 2 10897#define regDIO_LINKC_CNTL 0x1f06 10898#define regDIO_LINKC_CNTL_BASE_IDX 2 10899#define regDIO_LINKD_CNTL 0x1f07 10900#define regDIO_LINKD_CNTL_BASE_IDX 2 10901#define regDIO_LINKE_CNTL 0x1f08 10902#define regDIO_LINKE_CNTL_BASE_IDX 2 10903#define regDIO_LINKF_CNTL 0x1f09 10904#define regDIO_LINKF_CNTL_BASE_IDX 2 10905 10906 10907// addressBlock: dcn_dc_dcio_dcio_dispdec 10908// base address: 0x0 10909#define regDC_GENERICA 0x2868 10910#define regDC_GENERICA_BASE_IDX 2 10911#define regDC_GENERICB 0x2869 10912#define regDC_GENERICB_BASE_IDX 2 10913#define regDCIO_CLOCK_CNTL 0x286a 10914#define regDCIO_CLOCK_CNTL_BASE_IDX 2 10915#define regDC_REF_CLK_CNTL 0x286b 10916#define regDC_REF_CLK_CNTL_BASE_IDX 2 10917#define regUNIPHYA_CHANNEL_XBAR_CNTL 0x286e 10918#define regUNIPHYA_CHANNEL_XBAR_CNTL_BASE_IDX 2 10919#define regUNIPHYB_CHANNEL_XBAR_CNTL 0x2870 10920#define regUNIPHYB_CHANNEL_XBAR_CNTL_BASE_IDX 2 10921#define regUNIPHYC_CHANNEL_XBAR_CNTL 0x2872 10922#define regUNIPHYC_CHANNEL_XBAR_CNTL_BASE_IDX 2 10923#define regUNIPHYD_CHANNEL_XBAR_CNTL 0x2874 10924#define regUNIPHYD_CHANNEL_XBAR_CNTL_BASE_IDX 2 10925#define regUNIPHYE_CHANNEL_XBAR_CNTL 0x2876 10926#define regUNIPHYE_CHANNEL_XBAR_CNTL_BASE_IDX 2 10927#define regDCIO_WRCMD_DELAY 0x287e 10928#define regDCIO_WRCMD_DELAY_BASE_IDX 2 10929#define regDC_PINSTRAPS 0x2880 10930#define regDC_PINSTRAPS_BASE_IDX 2 10931#define regDCIO_SPARE 0x2882 10932#define regDCIO_SPARE_BASE_IDX 2 10933#define regINTERCEPT_STATE 0x2884 10934#define regINTERCEPT_STATE_BASE_IDX 2 10935#define regDCIO_PATTERN_GEN_PAT 0x2886 10936#define regDCIO_PATTERN_GEN_PAT_BASE_IDX 2 10937#define regDCIO_PATTERN_GEN_EN 0x2887 10938#define regDCIO_PATTERN_GEN_EN_BASE_IDX 2 10939#define regDCIO_BL_PWM_FRAME_START_DISP_SEL 0x288b 10940#define regDCIO_BL_PWM_FRAME_START_DISP_SEL_BASE_IDX 2 10941#define regDCIO_GSL_GENLK_PAD_CNTL 0x288c 10942#define regDCIO_GSL_GENLK_PAD_CNTL_BASE_IDX 2 10943#define regDCIO_GSL_SWAPLOCK_PAD_CNTL 0x288d 10944#define regDCIO_GSL_SWAPLOCK_PAD_CNTL_BASE_IDX 2 10945#define regDCIO_SOFT_RESET 0x289e 10946#define regDCIO_SOFT_RESET_BASE_IDX 2 10947 10948 10949// addressBlock: dcn_dc_dcio_dcio_chip_dispdec 10950// base address: 0x0 10951#define regDC_GPIO_GENERIC_MASK 0x28c8 10952#define regDC_GPIO_GENERIC_MASK_BASE_IDX 2 10953#define regDC_GPIO_GENERIC_A 0x28c9 10954#define regDC_GPIO_GENERIC_A_BASE_IDX 2 10955#define regDC_GPIO_GENERIC_EN 0x28ca 10956#define regDC_GPIO_GENERIC_EN_BASE_IDX 2 10957#define regDC_GPIO_GENERIC_Y 0x28cb 10958#define regDC_GPIO_GENERIC_Y_BASE_IDX 2 10959#define regDC_GPIO_DDC1_MASK 0x28d0 10960#define regDC_GPIO_DDC1_MASK_BASE_IDX 2 10961#define regDC_GPIO_DDC1_A 0x28d1 10962#define regDC_GPIO_DDC1_A_BASE_IDX 2 10963#define regDC_GPIO_DDC1_EN 0x28d2 10964#define regDC_GPIO_DDC1_EN_BASE_IDX 2 10965#define regDC_GPIO_DDC1_Y 0x28d3 10966#define regDC_GPIO_DDC1_Y_BASE_IDX 2 10967#define regDC_GPIO_DDC2_MASK 0x28d4 10968#define regDC_GPIO_DDC2_MASK_BASE_IDX 2 10969#define regDC_GPIO_DDC2_A 0x28d5 10970#define regDC_GPIO_DDC2_A_BASE_IDX 2 10971#define regDC_GPIO_DDC2_EN 0x28d6 10972#define regDC_GPIO_DDC2_EN_BASE_IDX 2 10973#define regDC_GPIO_DDC2_Y 0x28d7 10974#define regDC_GPIO_DDC2_Y_BASE_IDX 2 10975#define regDC_GPIO_DDC3_MASK 0x28d8 10976#define regDC_GPIO_DDC3_MASK_BASE_IDX 2 10977#define regDC_GPIO_DDC3_A 0x28d9 10978#define regDC_GPIO_DDC3_A_BASE_IDX 2 10979#define regDC_GPIO_DDC3_EN 0x28da 10980#define regDC_GPIO_DDC3_EN_BASE_IDX 2 10981#define regDC_GPIO_DDC3_Y 0x28db 10982#define regDC_GPIO_DDC3_Y_BASE_IDX 2 10983#define regDC_GPIO_DDC4_MASK 0x28dc 10984#define regDC_GPIO_DDC4_MASK_BASE_IDX 2 10985#define regDC_GPIO_DDC4_A 0x28dd 10986#define regDC_GPIO_DDC4_A_BASE_IDX 2 10987#define regDC_GPIO_DDC4_EN 0x28de 10988#define regDC_GPIO_DDC4_EN_BASE_IDX 2 10989#define regDC_GPIO_DDC4_Y 0x28df 10990#define regDC_GPIO_DDC4_Y_BASE_IDX 2 10991#define regDC_GPIO_DDC5_MASK 0x28e0 10992#define regDC_GPIO_DDC5_MASK_BASE_IDX 2 10993#define regDC_GPIO_DDC5_A 0x28e1 10994#define regDC_GPIO_DDC5_A_BASE_IDX 2 10995#define regDC_GPIO_DDC5_EN 0x28e2 10996#define regDC_GPIO_DDC5_EN_BASE_IDX 2 10997#define regDC_GPIO_DDC5_Y 0x28e3 10998#define regDC_GPIO_DDC5_Y_BASE_IDX 2 10999#define regDC_GPIO_DDCVGA_MASK 0x28e8 11000#define regDC_GPIO_DDCVGA_MASK_BASE_IDX 2 11001#define regDC_GPIO_DDCVGA_A 0x28e9 11002#define regDC_GPIO_DDCVGA_A_BASE_IDX 2 11003#define regDC_GPIO_DDCVGA_EN 0x28ea 11004#define regDC_GPIO_DDCVGA_EN_BASE_IDX 2 11005#define regDC_GPIO_DDCVGA_Y 0x28eb 11006#define regDC_GPIO_DDCVGA_Y_BASE_IDX 2 11007#define regDC_GPIO_GENLK_MASK 0x28f0 11008#define regDC_GPIO_GENLK_MASK_BASE_IDX 2 11009#define regDC_GPIO_GENLK_A 0x28f1 11010#define regDC_GPIO_GENLK_A_BASE_IDX 2 11011#define regDC_GPIO_GENLK_EN 0x28f2 11012#define regDC_GPIO_GENLK_EN_BASE_IDX 2 11013#define regDC_GPIO_GENLK_Y 0x28f3 11014#define regDC_GPIO_GENLK_Y_BASE_IDX 2 11015#define regDC_GPIO_HPD_MASK 0x28f4 11016#define regDC_GPIO_HPD_MASK_BASE_IDX 2 11017#define regDC_GPIO_HPD_A 0x28f5 11018#define regDC_GPIO_HPD_A_BASE_IDX 2 11019#define regDC_GPIO_HPD_EN 0x28f6 11020#define regDC_GPIO_HPD_EN_BASE_IDX 2 11021#define regDC_GPIO_HPD_Y 0x28f7 11022#define regDC_GPIO_HPD_Y_BASE_IDX 2 11023#define regDC_GPIO_DRIVE_STRENGTH_S0 0x28f8 11024#define regDC_GPIO_DRIVE_STRENGTH_S0_BASE_IDX 2 11025#define regDC_GPIO_DRIVE_STRENGTH_S1 0x28f9 11026#define regDC_GPIO_DRIVE_STRENGTH_S1_BASE_IDX 2 11027#define regDC_GPIO_PWRSEQ0_EN 0x28fa 11028#define regDC_GPIO_PWRSEQ0_EN_BASE_IDX 2 11029#define regDC_GPIO_PAD_STRENGTH_1 0x28fc 11030#define regDC_GPIO_PAD_STRENGTH_1_BASE_IDX 2 11031#define regDC_GPIO_PAD_STRENGTH_2 0x28fd 11032#define regDC_GPIO_PAD_STRENGTH_2_BASE_IDX 2 11033#define regPHY_AUX_CNTL 0x28ff 11034#define regPHY_AUX_CNTL_BASE_IDX 2 11035#define regDC_GPIO_DRIVE_TXIMPSEL 0x2900 11036#define regDC_GPIO_DRIVE_TXIMPSEL_BASE_IDX 2 11037#define regDC_GPIO_TX12_EN 0x2915 11038#define regDC_GPIO_TX12_EN_BASE_IDX 2 11039#define regDC_GPIO_AUX_CTRL_0 0x2916 11040#define regDC_GPIO_AUX_CTRL_0_BASE_IDX 2 11041#define regDC_GPIO_AUX_CTRL_1 0x2917 11042#define regDC_GPIO_AUX_CTRL_1_BASE_IDX 2 11043#define regDC_GPIO_AUX_CTRL_2 0x2918 11044#define regDC_GPIO_AUX_CTRL_2_BASE_IDX 2 11045#define regDC_GPIO_RXEN 0x2919 11046#define regDC_GPIO_RXEN_BASE_IDX 2 11047#define regDC_GPIO_PULLUPEN 0x291a 11048#define regDC_GPIO_PULLUPEN_BASE_IDX 2 11049#define regDC_GPIO_AUX_CTRL_3 0x291b 11050#define regDC_GPIO_AUX_CTRL_3_BASE_IDX 2 11051#define regDC_GPIO_AUX_CTRL_4 0x291c 11052#define regDC_GPIO_AUX_CTRL_4_BASE_IDX 2 11053#define regDC_GPIO_AUX_CTRL_5 0x291d 11054#define regDC_GPIO_AUX_CTRL_5_BASE_IDX 2 11055#define regAUXI2C_PAD_ALL_PWR_OK 0x291e 11056#define regAUXI2C_PAD_ALL_PWR_OK_BASE_IDX 2 11057 11058 11059// addressBlock: dcn_dc_dcio_dcio_uniphy0_dispdec 11060// base address: 0x0 11061#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED0 0x2928 11062#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2 11063#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED1 0x2929 11064#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2 11065#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED2 0x292a 11066#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2 11067#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED3 0x292b 11068#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2 11069#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED4 0x292c 11070#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2 11071#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED5 0x292d 11072#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2 11073#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED6 0x292e 11074#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2 11075#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED7 0x292f 11076#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2 11077#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED8 0x2930 11078#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2 11079#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED9 0x2931 11080#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2 11081#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED10 0x2932 11082#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2 11083#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED11 0x2933 11084#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2 11085#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED12 0x2934 11086#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2 11087#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED13 0x2935 11088#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2 11089#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED14 0x2936 11090#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2 11091#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED15 0x2937 11092#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2 11093#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED16 0x2938 11094#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2 11095#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED17 0x2939 11096#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2 11097#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED18 0x293a 11098#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2 11099#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED19 0x293b 11100#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2 11101#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED20 0x293c 11102#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2 11103#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED21 0x293d 11104#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2 11105#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED22 0x293e 11106#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2 11107#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED23 0x293f 11108#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2 11109#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED24 0x2940 11110#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2 11111#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED25 0x2941 11112#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2 11113#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED26 0x2942 11114#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2 11115#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED27 0x2943 11116#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2 11117#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED28 0x2944 11118#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2 11119#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED29 0x2945 11120#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2 11121#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED30 0x2946 11122#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2 11123#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED31 0x2947 11124#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2 11125#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED32 0x2948 11126#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2 11127#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED33 0x2949 11128#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2 11129#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED34 0x294a 11130#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2 11131#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED35 0x294b 11132#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2 11133#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED36 0x294c 11134#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2 11135#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED37 0x294d 11136#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2 11137#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED38 0x294e 11138#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2 11139#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED39 0x294f 11140#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2 11141#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED40 0x2950 11142#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2 11143#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED41 0x2951 11144#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2 11145#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED42 0x2952 11146#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2 11147#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED43 0x2953 11148#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2 11149#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED44 0x2954 11150#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2 11151#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED45 0x2955 11152#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2 11153#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED46 0x2956 11154#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2 11155#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED47 0x2957 11156#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2 11157#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED48 0x2958 11158#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX 2 11159#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED49 0x2959 11160#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX 2 11161#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED50 0x295a 11162#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX 2 11163#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED51 0x295b 11164#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX 2 11165#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED52 0x295c 11166#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX 2 11167#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED53 0x295d 11168#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX 2 11169#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED54 0x295e 11170#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX 2 11171#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED55 0x295f 11172#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX 2 11173#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED56 0x2960 11174#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX 2 11175#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED57 0x2961 11176#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX 2 11177 11178 11179// addressBlock: dcn_dc_dcio_dcio_uniphy1_dispdec 11180// base address: 0x360 11181#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0 0x2a00 11182#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2 11183#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1 0x2a01 11184#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2 11185#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2 0x2a02 11186#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2 11187#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3 0x2a03 11188#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2 11189#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4 0x2a04 11190#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2 11191#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5 0x2a05 11192#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2 11193#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6 0x2a06 11194#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2 11195#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7 0x2a07 11196#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2 11197#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8 0x2a08 11198#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2 11199#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9 0x2a09 11200#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2 11201#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10 0x2a0a 11202#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2 11203#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11 0x2a0b 11204#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2 11205#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12 0x2a0c 11206#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2 11207#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13 0x2a0d 11208#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2 11209#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14 0x2a0e 11210#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2 11211#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15 0x2a0f 11212#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2 11213#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16 0x2a10 11214#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2 11215#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17 0x2a11 11216#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2 11217#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18 0x2a12 11218#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2 11219#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19 0x2a13 11220#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2 11221#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20 0x2a14 11222#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2 11223#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21 0x2a15 11224#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2 11225#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22 0x2a16 11226#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2 11227#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23 0x2a17 11228#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2 11229#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24 0x2a18 11230#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2 11231#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25 0x2a19 11232#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2 11233#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26 0x2a1a 11234#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2 11235#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27 0x2a1b 11236#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2 11237#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28 0x2a1c 11238#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2 11239#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29 0x2a1d 11240#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2 11241#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30 0x2a1e 11242#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2 11243#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31 0x2a1f 11244#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2 11245#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32 0x2a20 11246#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2 11247#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33 0x2a21 11248#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2 11249#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34 0x2a22 11250#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2 11251#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35 0x2a23 11252#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2 11253#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36 0x2a24 11254#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2 11255#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37 0x2a25 11256#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2 11257#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38 0x2a26 11258#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2 11259#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39 0x2a27 11260#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2 11261#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40 0x2a28 11262#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2 11263#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41 0x2a29 11264#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2 11265#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42 0x2a2a 11266#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2 11267#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43 0x2a2b 11268#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2 11269#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44 0x2a2c 11270#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2 11271#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45 0x2a2d 11272#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2 11273#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46 0x2a2e 11274#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2 11275#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47 0x2a2f 11276#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2 11277#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48 0x2a30 11278#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX 2 11279#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49 0x2a31 11280#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX 2 11281#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50 0x2a32 11282#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX 2 11283#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51 0x2a33 11284#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX 2 11285#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52 0x2a34 11286#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX 2 11287#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53 0x2a35 11288#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX 2 11289#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54 0x2a36 11290#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX 2 11291#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55 0x2a37 11292#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX 2 11293#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56 0x2a38 11294#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX 2 11295#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57 0x2a39 11296#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX 2 11297 11298 11299// addressBlock: dcn_dc_dcio_dcio_uniphy2_dispdec 11300// base address: 0x6c0 11301#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0 0x2ad8 11302#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2 11303#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1 0x2ad9 11304#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2 11305#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2 0x2ada 11306#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2 11307#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3 0x2adb 11308#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2 11309#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4 0x2adc 11310#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2 11311#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5 0x2add 11312#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2 11313#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6 0x2ade 11314#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2 11315#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7 0x2adf 11316#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2 11317#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8 0x2ae0 11318#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2 11319#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9 0x2ae1 11320#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2 11321#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10 0x2ae2 11322#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2 11323#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11 0x2ae3 11324#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2 11325#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12 0x2ae4 11326#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2 11327#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13 0x2ae5 11328#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2 11329#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14 0x2ae6 11330#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2 11331#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15 0x2ae7 11332#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2 11333#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16 0x2ae8 11334#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2 11335#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17 0x2ae9 11336#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2 11337#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18 0x2aea 11338#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2 11339#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19 0x2aeb 11340#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2 11341#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20 0x2aec 11342#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2 11343#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21 0x2aed 11344#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2 11345#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22 0x2aee 11346#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2 11347#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23 0x2aef 11348#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2 11349#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24 0x2af0 11350#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2 11351#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25 0x2af1 11352#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2 11353#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26 0x2af2 11354#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2 11355#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27 0x2af3 11356#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2 11357#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28 0x2af4 11358#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2 11359#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29 0x2af5 11360#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2 11361#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30 0x2af6 11362#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2 11363#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31 0x2af7 11364#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2 11365#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32 0x2af8 11366#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2 11367#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33 0x2af9 11368#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2 11369#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34 0x2afa 11370#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2 11371#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35 0x2afb 11372#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2 11373#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36 0x2afc 11374#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2 11375#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37 0x2afd 11376#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2 11377#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38 0x2afe 11378#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2 11379#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39 0x2aff 11380#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2 11381#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40 0x2b00 11382#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2 11383#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41 0x2b01 11384#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2 11385#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42 0x2b02 11386#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2 11387#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43 0x2b03 11388#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2 11389#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44 0x2b04 11390#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2 11391#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45 0x2b05 11392#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2 11393#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46 0x2b06 11394#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2 11395#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47 0x2b07 11396#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2 11397#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48 0x2b08 11398#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX 2 11399#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49 0x2b09 11400#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX 2 11401#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50 0x2b0a 11402#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX 2 11403#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51 0x2b0b 11404#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX 2 11405#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52 0x2b0c 11406#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX 2 11407#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53 0x2b0d 11408#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX 2 11409#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54 0x2b0e 11410#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX 2 11411#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55 0x2b0f 11412#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX 2 11413#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56 0x2b10 11414#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX 2 11415#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57 0x2b11 11416#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX 2 11417 11418 11419// addressBlock: dcn_dc_dcio_dcio_uniphy3_dispdec 11420// base address: 0xa20 11421#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0 0x2bb0 11422#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2 11423#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1 0x2bb1 11424#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2 11425#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2 0x2bb2 11426#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2 11427#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3 0x2bb3 11428#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2 11429#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4 0x2bb4 11430#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2 11431#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5 0x2bb5 11432#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2 11433#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6 0x2bb6 11434#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2 11435#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7 0x2bb7 11436#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2 11437#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8 0x2bb8 11438#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2 11439#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9 0x2bb9 11440#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2 11441#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10 0x2bba 11442#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2 11443#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11 0x2bbb 11444#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2 11445#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12 0x2bbc 11446#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2 11447#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13 0x2bbd 11448#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2 11449#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14 0x2bbe 11450#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2 11451#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15 0x2bbf 11452#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2 11453#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16 0x2bc0 11454#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2 11455#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17 0x2bc1 11456#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2 11457#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18 0x2bc2 11458#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2 11459#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19 0x2bc3 11460#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2 11461#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20 0x2bc4 11462#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2 11463#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21 0x2bc5 11464#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2 11465#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22 0x2bc6 11466#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2 11467#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23 0x2bc7 11468#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2 11469#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24 0x2bc8 11470#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2 11471#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25 0x2bc9 11472#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2 11473#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26 0x2bca 11474#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2 11475#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27 0x2bcb 11476#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2 11477#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28 0x2bcc 11478#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2 11479#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29 0x2bcd 11480#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2 11481#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30 0x2bce 11482#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2 11483#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31 0x2bcf 11484#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2 11485#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32 0x2bd0 11486#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2 11487#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33 0x2bd1 11488#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2 11489#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34 0x2bd2 11490#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2 11491#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35 0x2bd3 11492#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2 11493#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36 0x2bd4 11494#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2 11495#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37 0x2bd5 11496#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2 11497#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38 0x2bd6 11498#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2 11499#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39 0x2bd7 11500#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2 11501#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40 0x2bd8 11502#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2 11503#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41 0x2bd9 11504#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2 11505#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42 0x2bda 11506#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2 11507#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43 0x2bdb 11508#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2 11509#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44 0x2bdc 11510#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2 11511#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45 0x2bdd 11512#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2 11513#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46 0x2bde 11514#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2 11515#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47 0x2bdf 11516#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2 11517#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48 0x2be0 11518#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX 2 11519#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49 0x2be1 11520#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX 2 11521#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50 0x2be2 11522#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX 2 11523#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51 0x2be3 11524#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX 2 11525#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52 0x2be4 11526#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX 2 11527#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53 0x2be5 11528#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX 2 11529#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54 0x2be6 11530#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX 2 11531#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55 0x2be7 11532#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX 2 11533#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56 0x2be8 11534#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX 2 11535#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57 0x2be9 11536#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX 2 11537 11538 11539// addressBlock: dcn_dc_dcio_dcio_uniphy4_dispdec 11540// base address: 0xd80 11541#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED0 0x2c88 11542#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2 11543#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED1 0x2c89 11544#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2 11545#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED2 0x2c8a 11546#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2 11547#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED3 0x2c8b 11548#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2 11549#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED4 0x2c8c 11550#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2 11551#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED5 0x2c8d 11552#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2 11553#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED6 0x2c8e 11554#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2 11555#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED7 0x2c8f 11556#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2 11557#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED8 0x2c90 11558#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2 11559#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED9 0x2c91 11560#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2 11561#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED10 0x2c92 11562#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2 11563#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED11 0x2c93 11564#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2 11565#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED12 0x2c94 11566#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2 11567#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED13 0x2c95 11568#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2 11569#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14 0x2c96 11570#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2 11571#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15 0x2c97 11572#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2 11573#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16 0x2c98 11574#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2 11575#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17 0x2c99 11576#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2 11577#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18 0x2c9a 11578#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2 11579#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19 0x2c9b 11580#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2 11581#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED20 0x2c9c 11582#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2 11583#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED21 0x2c9d 11584#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2 11585#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED22 0x2c9e 11586#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2 11587#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23 0x2c9f 11588#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2 11589#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24 0x2ca0 11590#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2 11591#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25 0x2ca1 11592#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2 11593#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26 0x2ca2 11594#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2 11595#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27 0x2ca3 11596#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2 11597#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28 0x2ca4 11598#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2 11599#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29 0x2ca5 11600#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2 11601#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30 0x2ca6 11602#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2 11603#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31 0x2ca7 11604#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2 11605#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED32 0x2ca8 11606#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2 11607#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED33 0x2ca9 11608#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2 11609#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED34 0x2caa 11610#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2 11611#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED35 0x2cab 11612#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2 11613#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED36 0x2cac 11614#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2 11615#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED37 0x2cad 11616#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2 11617#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED38 0x2cae 11618#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2 11619#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED39 0x2caf 11620#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2 11621#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED40 0x2cb0 11622#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2 11623#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED41 0x2cb1 11624#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2 11625#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED42 0x2cb2 11626#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2 11627#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED43 0x2cb3 11628#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2 11629#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED44 0x2cb4 11630#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2 11631#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED45 0x2cb5 11632#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2 11633#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED46 0x2cb6 11634#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2 11635#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED47 0x2cb7 11636#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2 11637#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED48 0x2cb8 11638#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX 2 11639#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED49 0x2cb9 11640#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX 2 11641#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED50 0x2cba 11642#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX 2 11643#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED51 0x2cbb 11644#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX 2 11645#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED52 0x2cbc 11646#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX 2 11647#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED53 0x2cbd 11648#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX 2 11649#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED54 0x2cbe 11650#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX 2 11651#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED55 0x2cbf 11652#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX 2 11653#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED56 0x2cc0 11654#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX 2 11655#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED57 0x2cc1 11656#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX 2 11657 11658 11659// addressBlock: dcn_dc_pwrseq0_dispdec_pwrseq_dispdec 11660// base address: 0x0 11661#define regDC_GPIO_PWRSEQ_EN 0x2f10 11662#define regDC_GPIO_PWRSEQ_EN_BASE_IDX 2 11663#define regDC_GPIO_PWRSEQ_CTRL 0x2f11 11664#define regDC_GPIO_PWRSEQ_CTRL_BASE_IDX 2 11665#define regDC_GPIO_PWRSEQ_MASK 0x2f12 11666#define regDC_GPIO_PWRSEQ_MASK_BASE_IDX 2 11667#define regDC_GPIO_PWRSEQ_A_Y 0x2f13 11668#define regDC_GPIO_PWRSEQ_A_Y_BASE_IDX 2 11669#define regPANEL_PWRSEQ_CNTL 0x2f14 11670#define regPANEL_PWRSEQ_CNTL_BASE_IDX 2 11671#define regPANEL_PWRSEQ_STATE 0x2f15 11672#define regPANEL_PWRSEQ_STATE_BASE_IDX 2 11673#define regPANEL_PWRSEQ_DELAY1 0x2f16 11674#define regPANEL_PWRSEQ_DELAY1_BASE_IDX 2 11675#define regPANEL_PWRSEQ_DELAY2 0x2f17 11676#define regPANEL_PWRSEQ_DELAY2_BASE_IDX 2 11677#define regPANEL_PWRSEQ_REF_DIV1 0x2f18 11678#define regPANEL_PWRSEQ_REF_DIV1_BASE_IDX 2 11679#define regBL_PWM_CNTL 0x2f19 11680#define regBL_PWM_CNTL_BASE_IDX 2 11681#define regBL_PWM_CNTL2 0x2f1a 11682#define regBL_PWM_CNTL2_BASE_IDX 2 11683#define regBL_PWM_PERIOD_CNTL 0x2f1b 11684#define regBL_PWM_PERIOD_CNTL_BASE_IDX 2 11685#define regBL_PWM_GRP1_REG_LOCK 0x2f1c 11686#define regBL_PWM_GRP1_REG_LOCK_BASE_IDX 2 11687#define regPANEL_PWRSEQ_REF_DIV2 0x2f1d 11688#define regPANEL_PWRSEQ_REF_DIV2_BASE_IDX 2 11689#define regPWRSEQ_SPARE 0x2f21 11690#define regPWRSEQ_SPARE_BASE_IDX 2 11691 11692 11693// addressBlock: dcn_dc_dsc0_dispdec_dscc_dispdec 11694// base address: 0x0 11695#define regDSCC0_DSCC_CONFIG0 0x300a 11696#define regDSCC0_DSCC_CONFIG0_BASE_IDX 2 11697#define regDSCC0_DSCC_CONFIG1 0x300b 11698#define regDSCC0_DSCC_CONFIG1_BASE_IDX 2 11699#define regDSCC0_DSCC_STATUS 0x300c 11700#define regDSCC0_DSCC_STATUS_BASE_IDX 2 11701#define regDSCC0_DSCC_INTERRUPT_CONTROL_STATUS 0x300d 11702#define regDSCC0_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX 2 11703#define regDSCC0_DSCC_PPS_CONFIG0 0x300e 11704#define regDSCC0_DSCC_PPS_CONFIG0_BASE_IDX 2 11705#define regDSCC0_DSCC_PPS_CONFIG1 0x300f 11706#define regDSCC0_DSCC_PPS_CONFIG1_BASE_IDX 2 11707#define regDSCC0_DSCC_PPS_CONFIG2 0x3010 11708#define regDSCC0_DSCC_PPS_CONFIG2_BASE_IDX 2 11709#define regDSCC0_DSCC_PPS_CONFIG3 0x3011 11710#define regDSCC0_DSCC_PPS_CONFIG3_BASE_IDX 2 11711#define regDSCC0_DSCC_PPS_CONFIG4 0x3012 11712#define regDSCC0_DSCC_PPS_CONFIG4_BASE_IDX 2 11713#define regDSCC0_DSCC_PPS_CONFIG5 0x3013 11714#define regDSCC0_DSCC_PPS_CONFIG5_BASE_IDX 2 11715#define regDSCC0_DSCC_PPS_CONFIG6 0x3014 11716#define regDSCC0_DSCC_PPS_CONFIG6_BASE_IDX 2 11717#define regDSCC0_DSCC_PPS_CONFIG7 0x3015 11718#define regDSCC0_DSCC_PPS_CONFIG7_BASE_IDX 2 11719#define regDSCC0_DSCC_PPS_CONFIG8 0x3016 11720#define regDSCC0_DSCC_PPS_CONFIG8_BASE_IDX 2 11721#define regDSCC0_DSCC_PPS_CONFIG9 0x3017 11722#define regDSCC0_DSCC_PPS_CONFIG9_BASE_IDX 2 11723#define regDSCC0_DSCC_PPS_CONFIG10 0x3018 11724#define regDSCC0_DSCC_PPS_CONFIG10_BASE_IDX 2 11725#define regDSCC0_DSCC_PPS_CONFIG11 0x3019 11726#define regDSCC0_DSCC_PPS_CONFIG11_BASE_IDX 2 11727#define regDSCC0_DSCC_PPS_CONFIG12 0x301a 11728#define regDSCC0_DSCC_PPS_CONFIG12_BASE_IDX 2 11729#define regDSCC0_DSCC_PPS_CONFIG13 0x301b 11730#define regDSCC0_DSCC_PPS_CONFIG13_BASE_IDX 2 11731#define regDSCC0_DSCC_PPS_CONFIG14 0x301c 11732#define regDSCC0_DSCC_PPS_CONFIG14_BASE_IDX 2 11733#define regDSCC0_DSCC_PPS_CONFIG15 0x301d 11734#define regDSCC0_DSCC_PPS_CONFIG15_BASE_IDX 2 11735#define regDSCC0_DSCC_PPS_CONFIG16 0x301e 11736#define regDSCC0_DSCC_PPS_CONFIG16_BASE_IDX 2 11737#define regDSCC0_DSCC_PPS_CONFIG17 0x301f 11738#define regDSCC0_DSCC_PPS_CONFIG17_BASE_IDX 2 11739#define regDSCC0_DSCC_PPS_CONFIG18 0x3020 11740#define regDSCC0_DSCC_PPS_CONFIG18_BASE_IDX 2 11741#define regDSCC0_DSCC_PPS_CONFIG19 0x3021 11742#define regDSCC0_DSCC_PPS_CONFIG19_BASE_IDX 2 11743#define regDSCC0_DSCC_PPS_CONFIG20 0x3022 11744#define regDSCC0_DSCC_PPS_CONFIG20_BASE_IDX 2 11745#define regDSCC0_DSCC_PPS_CONFIG21 0x3023 11746#define regDSCC0_DSCC_PPS_CONFIG21_BASE_IDX 2 11747#define regDSCC0_DSCC_PPS_CONFIG22 0x3024 11748#define regDSCC0_DSCC_PPS_CONFIG22_BASE_IDX 2 11749#define regDSCC0_DSCC_MEM_POWER_CONTROL 0x3025 11750#define regDSCC0_DSCC_MEM_POWER_CONTROL_BASE_IDX 2 11751#define regDSCC0_DSCC_R_Y_SQUARED_ERROR_LOWER 0x3026 11752#define regDSCC0_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX 2 11753#define regDSCC0_DSCC_R_Y_SQUARED_ERROR_UPPER 0x3027 11754#define regDSCC0_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX 2 11755#define regDSCC0_DSCC_G_CB_SQUARED_ERROR_LOWER 0x3028 11756#define regDSCC0_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX 2 11757#define regDSCC0_DSCC_G_CB_SQUARED_ERROR_UPPER 0x3029 11758#define regDSCC0_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX 2 11759#define regDSCC0_DSCC_B_CR_SQUARED_ERROR_LOWER 0x302a 11760#define regDSCC0_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX 2 11761#define regDSCC0_DSCC_B_CR_SQUARED_ERROR_UPPER 0x302b 11762#define regDSCC0_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX 2 11763#define regDSCC0_DSCC_MAX_ABS_ERROR0 0x302c 11764#define regDSCC0_DSCC_MAX_ABS_ERROR0_BASE_IDX 2 11765#define regDSCC0_DSCC_MAX_ABS_ERROR1 0x302d 11766#define regDSCC0_DSCC_MAX_ABS_ERROR1_BASE_IDX 2 11767#define regDSCC0_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL 0x302e 11768#define regDSCC0_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2 11769#define regDSCC0_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL 0x302f 11770#define regDSCC0_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2 11771#define regDSCC0_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL 0x3030 11772#define regDSCC0_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2 11773#define regDSCC0_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL 0x3031 11774#define regDSCC0_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2 11775#define regDSCC0_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL 0x3032 11776#define regDSCC0_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2 11777#define regDSCC0_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL 0x3033 11778#define regDSCC0_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2 11779#define regDSCC0_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL 0x3034 11780#define regDSCC0_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2 11781#define regDSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL 0x3035 11782#define regDSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2 11783 11784 11785// addressBlock: dcn_dc_dsc0_dispdec_dsccif_dispdec 11786// base address: 0x0 11787#define regDSCCIF0_DSCCIF_CONFIG0 0x3005 11788#define regDSCCIF0_DSCCIF_CONFIG0_BASE_IDX 2 11789#define regDSCCIF0_DSCCIF_CONFIG1 0x3006 11790#define regDSCCIF0_DSCCIF_CONFIG1_BASE_IDX 2 11791 11792 11793// addressBlock: dcn_dc_dsc0_dispdec_dsc_top_dispdec 11794// base address: 0x0 11795#define regDSC_TOP0_DSC_TOP_CONTROL 0x3000 11796#define regDSC_TOP0_DSC_TOP_CONTROL_BASE_IDX 2 11797#define regDSC_TOP0_DSC_DEBUG_CONTROL 0x3001 11798#define regDSC_TOP0_DSC_DEBUG_CONTROL_BASE_IDX 2 11799 11800 11801// addressBlock: dcn_dc_dsc1_dispdec_dscc_dispdec 11802// base address: 0x170 11803#define regDSCC1_DSCC_CONFIG0 0x3066 11804#define regDSCC1_DSCC_CONFIG0_BASE_IDX 2 11805#define regDSCC1_DSCC_CONFIG1 0x3067 11806#define regDSCC1_DSCC_CONFIG1_BASE_IDX 2 11807#define regDSCC1_DSCC_STATUS 0x3068 11808#define regDSCC1_DSCC_STATUS_BASE_IDX 2 11809#define regDSCC1_DSCC_INTERRUPT_CONTROL_STATUS 0x3069 11810#define regDSCC1_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX 2 11811#define regDSCC1_DSCC_PPS_CONFIG0 0x306a 11812#define regDSCC1_DSCC_PPS_CONFIG0_BASE_IDX 2 11813#define regDSCC1_DSCC_PPS_CONFIG1 0x306b 11814#define regDSCC1_DSCC_PPS_CONFIG1_BASE_IDX 2 11815#define regDSCC1_DSCC_PPS_CONFIG2 0x306c 11816#define regDSCC1_DSCC_PPS_CONFIG2_BASE_IDX 2 11817#define regDSCC1_DSCC_PPS_CONFIG3 0x306d 11818#define regDSCC1_DSCC_PPS_CONFIG3_BASE_IDX 2 11819#define regDSCC1_DSCC_PPS_CONFIG4 0x306e 11820#define regDSCC1_DSCC_PPS_CONFIG4_BASE_IDX 2 11821#define regDSCC1_DSCC_PPS_CONFIG5 0x306f 11822#define regDSCC1_DSCC_PPS_CONFIG5_BASE_IDX 2 11823#define regDSCC1_DSCC_PPS_CONFIG6 0x3070 11824#define regDSCC1_DSCC_PPS_CONFIG6_BASE_IDX 2 11825#define regDSCC1_DSCC_PPS_CONFIG7 0x3071 11826#define regDSCC1_DSCC_PPS_CONFIG7_BASE_IDX 2 11827#define regDSCC1_DSCC_PPS_CONFIG8 0x3072 11828#define regDSCC1_DSCC_PPS_CONFIG8_BASE_IDX 2 11829#define regDSCC1_DSCC_PPS_CONFIG9 0x3073 11830#define regDSCC1_DSCC_PPS_CONFIG9_BASE_IDX 2 11831#define regDSCC1_DSCC_PPS_CONFIG10 0x3074 11832#define regDSCC1_DSCC_PPS_CONFIG10_BASE_IDX 2 11833#define regDSCC1_DSCC_PPS_CONFIG11 0x3075 11834#define regDSCC1_DSCC_PPS_CONFIG11_BASE_IDX 2 11835#define regDSCC1_DSCC_PPS_CONFIG12 0x3076 11836#define regDSCC1_DSCC_PPS_CONFIG12_BASE_IDX 2 11837#define regDSCC1_DSCC_PPS_CONFIG13 0x3077 11838#define regDSCC1_DSCC_PPS_CONFIG13_BASE_IDX 2 11839#define regDSCC1_DSCC_PPS_CONFIG14 0x3078 11840#define regDSCC1_DSCC_PPS_CONFIG14_BASE_IDX 2 11841#define regDSCC1_DSCC_PPS_CONFIG15 0x3079 11842#define regDSCC1_DSCC_PPS_CONFIG15_BASE_IDX 2 11843#define regDSCC1_DSCC_PPS_CONFIG16 0x307a 11844#define regDSCC1_DSCC_PPS_CONFIG16_BASE_IDX 2 11845#define regDSCC1_DSCC_PPS_CONFIG17 0x307b 11846#define regDSCC1_DSCC_PPS_CONFIG17_BASE_IDX 2 11847#define regDSCC1_DSCC_PPS_CONFIG18 0x307c 11848#define regDSCC1_DSCC_PPS_CONFIG18_BASE_IDX 2 11849#define regDSCC1_DSCC_PPS_CONFIG19 0x307d 11850#define regDSCC1_DSCC_PPS_CONFIG19_BASE_IDX 2 11851#define regDSCC1_DSCC_PPS_CONFIG20 0x307e 11852#define regDSCC1_DSCC_PPS_CONFIG20_BASE_IDX 2 11853#define regDSCC1_DSCC_PPS_CONFIG21 0x307f 11854#define regDSCC1_DSCC_PPS_CONFIG21_BASE_IDX 2 11855#define regDSCC1_DSCC_PPS_CONFIG22 0x3080 11856#define regDSCC1_DSCC_PPS_CONFIG22_BASE_IDX 2 11857#define regDSCC1_DSCC_MEM_POWER_CONTROL 0x3081 11858#define regDSCC1_DSCC_MEM_POWER_CONTROL_BASE_IDX 2 11859#define regDSCC1_DSCC_R_Y_SQUARED_ERROR_LOWER 0x3082 11860#define regDSCC1_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX 2 11861#define regDSCC1_DSCC_R_Y_SQUARED_ERROR_UPPER 0x3083 11862#define regDSCC1_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX 2 11863#define regDSCC1_DSCC_G_CB_SQUARED_ERROR_LOWER 0x3084 11864#define regDSCC1_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX 2 11865#define regDSCC1_DSCC_G_CB_SQUARED_ERROR_UPPER 0x3085 11866#define regDSCC1_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX 2 11867#define regDSCC1_DSCC_B_CR_SQUARED_ERROR_LOWER 0x3086 11868#define regDSCC1_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX 2 11869#define regDSCC1_DSCC_B_CR_SQUARED_ERROR_UPPER 0x3087 11870#define regDSCC1_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX 2 11871#define regDSCC1_DSCC_MAX_ABS_ERROR0 0x3088 11872#define regDSCC1_DSCC_MAX_ABS_ERROR0_BASE_IDX 2 11873#define regDSCC1_DSCC_MAX_ABS_ERROR1 0x3089 11874#define regDSCC1_DSCC_MAX_ABS_ERROR1_BASE_IDX 2 11875#define regDSCC1_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL 0x308a 11876#define regDSCC1_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2 11877#define regDSCC1_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL 0x308b 11878#define regDSCC1_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2 11879#define regDSCC1_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL 0x308c 11880#define regDSCC1_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2 11881#define regDSCC1_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL 0x308d 11882#define regDSCC1_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2 11883#define regDSCC1_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL 0x308e 11884#define regDSCC1_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2 11885#define regDSCC1_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL 0x308f 11886#define regDSCC1_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2 11887#define regDSCC1_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL 0x3090 11888#define regDSCC1_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2 11889#define regDSCC1_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL 0x3091 11890#define regDSCC1_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2 11891 11892 11893// addressBlock: dcn_dc_dsc1_dispdec_dsccif_dispdec 11894// base address: 0x170 11895#define regDSCCIF1_DSCCIF_CONFIG0 0x3061 11896#define regDSCCIF1_DSCCIF_CONFIG0_BASE_IDX 2 11897#define regDSCCIF1_DSCCIF_CONFIG1 0x3062 11898#define regDSCCIF1_DSCCIF_CONFIG1_BASE_IDX 2 11899 11900 11901// addressBlock: dcn_dc_dsc1_dispdec_dsc_top_dispdec 11902// base address: 0x170 11903#define regDSC_TOP1_DSC_TOP_CONTROL 0x305c 11904#define regDSC_TOP1_DSC_TOP_CONTROL_BASE_IDX 2 11905#define regDSC_TOP1_DSC_DEBUG_CONTROL 0x305d 11906#define regDSC_TOP1_DSC_DEBUG_CONTROL_BASE_IDX 2 11907 11908 11909// addressBlock: dcn_dc_dsc2_dispdec_dscc_dispdec 11910// base address: 0x2e0 11911#define regDSCC2_DSCC_CONFIG0 0x30c2 11912#define regDSCC2_DSCC_CONFIG0_BASE_IDX 2 11913#define regDSCC2_DSCC_CONFIG1 0x30c3 11914#define regDSCC2_DSCC_CONFIG1_BASE_IDX 2 11915#define regDSCC2_DSCC_STATUS 0x30c4 11916#define regDSCC2_DSCC_STATUS_BASE_IDX 2 11917#define regDSCC2_DSCC_INTERRUPT_CONTROL_STATUS 0x30c5 11918#define regDSCC2_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX 2 11919#define regDSCC2_DSCC_PPS_CONFIG0 0x30c6 11920#define regDSCC2_DSCC_PPS_CONFIG0_BASE_IDX 2 11921#define regDSCC2_DSCC_PPS_CONFIG1 0x30c7 11922#define regDSCC2_DSCC_PPS_CONFIG1_BASE_IDX 2 11923#define regDSCC2_DSCC_PPS_CONFIG2 0x30c8 11924#define regDSCC2_DSCC_PPS_CONFIG2_BASE_IDX 2 11925#define regDSCC2_DSCC_PPS_CONFIG3 0x30c9 11926#define regDSCC2_DSCC_PPS_CONFIG3_BASE_IDX 2 11927#define regDSCC2_DSCC_PPS_CONFIG4 0x30ca 11928#define regDSCC2_DSCC_PPS_CONFIG4_BASE_IDX 2 11929#define regDSCC2_DSCC_PPS_CONFIG5 0x30cb 11930#define regDSCC2_DSCC_PPS_CONFIG5_BASE_IDX 2 11931#define regDSCC2_DSCC_PPS_CONFIG6 0x30cc 11932#define regDSCC2_DSCC_PPS_CONFIG6_BASE_IDX 2 11933#define regDSCC2_DSCC_PPS_CONFIG7 0x30cd 11934#define regDSCC2_DSCC_PPS_CONFIG7_BASE_IDX 2 11935#define regDSCC2_DSCC_PPS_CONFIG8 0x30ce 11936#define regDSCC2_DSCC_PPS_CONFIG8_BASE_IDX 2 11937#define regDSCC2_DSCC_PPS_CONFIG9 0x30cf 11938#define regDSCC2_DSCC_PPS_CONFIG9_BASE_IDX 2 11939#define regDSCC2_DSCC_PPS_CONFIG10 0x30d0 11940#define regDSCC2_DSCC_PPS_CONFIG10_BASE_IDX 2 11941#define regDSCC2_DSCC_PPS_CONFIG11 0x30d1 11942#define regDSCC2_DSCC_PPS_CONFIG11_BASE_IDX 2 11943#define regDSCC2_DSCC_PPS_CONFIG12 0x30d2 11944#define regDSCC2_DSCC_PPS_CONFIG12_BASE_IDX 2 11945#define regDSCC2_DSCC_PPS_CONFIG13 0x30d3 11946#define regDSCC2_DSCC_PPS_CONFIG13_BASE_IDX 2 11947#define regDSCC2_DSCC_PPS_CONFIG14 0x30d4 11948#define regDSCC2_DSCC_PPS_CONFIG14_BASE_IDX 2 11949#define regDSCC2_DSCC_PPS_CONFIG15 0x30d5 11950#define regDSCC2_DSCC_PPS_CONFIG15_BASE_IDX 2 11951#define regDSCC2_DSCC_PPS_CONFIG16 0x30d6 11952#define regDSCC2_DSCC_PPS_CONFIG16_BASE_IDX 2 11953#define regDSCC2_DSCC_PPS_CONFIG17 0x30d7 11954#define regDSCC2_DSCC_PPS_CONFIG17_BASE_IDX 2 11955#define regDSCC2_DSCC_PPS_CONFIG18 0x30d8 11956#define regDSCC2_DSCC_PPS_CONFIG18_BASE_IDX 2 11957#define regDSCC2_DSCC_PPS_CONFIG19 0x30d9 11958#define regDSCC2_DSCC_PPS_CONFIG19_BASE_IDX 2 11959#define regDSCC2_DSCC_PPS_CONFIG20 0x30da 11960#define regDSCC2_DSCC_PPS_CONFIG20_BASE_IDX 2 11961#define regDSCC2_DSCC_PPS_CONFIG21 0x30db 11962#define regDSCC2_DSCC_PPS_CONFIG21_BASE_IDX 2 11963#define regDSCC2_DSCC_PPS_CONFIG22 0x30dc 11964#define regDSCC2_DSCC_PPS_CONFIG22_BASE_IDX 2 11965#define regDSCC2_DSCC_MEM_POWER_CONTROL 0x30dd 11966#define regDSCC2_DSCC_MEM_POWER_CONTROL_BASE_IDX 2 11967#define regDSCC2_DSCC_R_Y_SQUARED_ERROR_LOWER 0x30de 11968#define regDSCC2_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX 2 11969#define regDSCC2_DSCC_R_Y_SQUARED_ERROR_UPPER 0x30df 11970#define regDSCC2_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX 2 11971#define regDSCC2_DSCC_G_CB_SQUARED_ERROR_LOWER 0x30e0 11972#define regDSCC2_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX 2 11973#define regDSCC2_DSCC_G_CB_SQUARED_ERROR_UPPER 0x30e1 11974#define regDSCC2_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX 2 11975#define regDSCC2_DSCC_B_CR_SQUARED_ERROR_LOWER 0x30e2 11976#define regDSCC2_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX 2 11977#define regDSCC2_DSCC_B_CR_SQUARED_ERROR_UPPER 0x30e3 11978#define regDSCC2_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX 2 11979#define regDSCC2_DSCC_MAX_ABS_ERROR0 0x30e4 11980#define regDSCC2_DSCC_MAX_ABS_ERROR0_BASE_IDX 2 11981#define regDSCC2_DSCC_MAX_ABS_ERROR1 0x30e5 11982#define regDSCC2_DSCC_MAX_ABS_ERROR1_BASE_IDX 2 11983#define regDSCC2_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL 0x30e6 11984#define regDSCC2_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2 11985#define regDSCC2_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL 0x30e7 11986#define regDSCC2_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2 11987#define regDSCC2_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL 0x30e8 11988#define regDSCC2_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2 11989#define regDSCC2_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL 0x30e9 11990#define regDSCC2_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2 11991#define regDSCC2_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL 0x30ea 11992#define regDSCC2_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2 11993#define regDSCC2_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL 0x30eb 11994#define regDSCC2_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2 11995#define regDSCC2_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL 0x30ec 11996#define regDSCC2_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2 11997#define regDSCC2_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL 0x30ed 11998#define regDSCC2_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2 11999 12000 12001// addressBlock: dcn_dc_dsc2_dispdec_dsccif_dispdec 12002// base address: 0x2e0 12003#define regDSCCIF2_DSCCIF_CONFIG0 0x30bd 12004#define regDSCCIF2_DSCCIF_CONFIG0_BASE_IDX 2 12005#define regDSCCIF2_DSCCIF_CONFIG1 0x30be 12006#define regDSCCIF2_DSCCIF_CONFIG1_BASE_IDX 2 12007 12008 12009// addressBlock: dcn_dc_dsc2_dispdec_dsc_top_dispdec 12010// base address: 0x2e0 12011#define regDSC_TOP2_DSC_TOP_CONTROL 0x30b8 12012#define regDSC_TOP2_DSC_TOP_CONTROL_BASE_IDX 2 12013#define regDSC_TOP2_DSC_DEBUG_CONTROL 0x30b9 12014#define regDSC_TOP2_DSC_DEBUG_CONTROL_BASE_IDX 2 12015 12016 12017// addressBlock: dcn_dc_dsc3_dispdec_dscc_dispdec 12018// base address: 0x450 12019#define regDSCC3_DSCC_CONFIG0 0x311e 12020#define regDSCC3_DSCC_CONFIG0_BASE_IDX 2 12021#define regDSCC3_DSCC_CONFIG1 0x311f 12022#define regDSCC3_DSCC_CONFIG1_BASE_IDX 2 12023#define regDSCC3_DSCC_STATUS 0x3120 12024#define regDSCC3_DSCC_STATUS_BASE_IDX 2 12025#define regDSCC3_DSCC_INTERRUPT_CONTROL_STATUS 0x3121 12026#define regDSCC3_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX 2 12027#define regDSCC3_DSCC_PPS_CONFIG0 0x3122 12028#define regDSCC3_DSCC_PPS_CONFIG0_BASE_IDX 2 12029#define regDSCC3_DSCC_PPS_CONFIG1 0x3123 12030#define regDSCC3_DSCC_PPS_CONFIG1_BASE_IDX 2 12031#define regDSCC3_DSCC_PPS_CONFIG2 0x3124 12032#define regDSCC3_DSCC_PPS_CONFIG2_BASE_IDX 2 12033#define regDSCC3_DSCC_PPS_CONFIG3 0x3125 12034#define regDSCC3_DSCC_PPS_CONFIG3_BASE_IDX 2 12035#define regDSCC3_DSCC_PPS_CONFIG4 0x3126 12036#define regDSCC3_DSCC_PPS_CONFIG4_BASE_IDX 2 12037#define regDSCC3_DSCC_PPS_CONFIG5 0x3127 12038#define regDSCC3_DSCC_PPS_CONFIG5_BASE_IDX 2 12039#define regDSCC3_DSCC_PPS_CONFIG6 0x3128 12040#define regDSCC3_DSCC_PPS_CONFIG6_BASE_IDX 2 12041#define regDSCC3_DSCC_PPS_CONFIG7 0x3129 12042#define regDSCC3_DSCC_PPS_CONFIG7_BASE_IDX 2 12043#define regDSCC3_DSCC_PPS_CONFIG8 0x312a 12044#define regDSCC3_DSCC_PPS_CONFIG8_BASE_IDX 2 12045#define regDSCC3_DSCC_PPS_CONFIG9 0x312b 12046#define regDSCC3_DSCC_PPS_CONFIG9_BASE_IDX 2 12047#define regDSCC3_DSCC_PPS_CONFIG10 0x312c 12048#define regDSCC3_DSCC_PPS_CONFIG10_BASE_IDX 2 12049#define regDSCC3_DSCC_PPS_CONFIG11 0x312d 12050#define regDSCC3_DSCC_PPS_CONFIG11_BASE_IDX 2 12051#define regDSCC3_DSCC_PPS_CONFIG12 0x312e 12052#define regDSCC3_DSCC_PPS_CONFIG12_BASE_IDX 2 12053#define regDSCC3_DSCC_PPS_CONFIG13 0x312f 12054#define regDSCC3_DSCC_PPS_CONFIG13_BASE_IDX 2 12055#define regDSCC3_DSCC_PPS_CONFIG14 0x3130 12056#define regDSCC3_DSCC_PPS_CONFIG14_BASE_IDX 2 12057#define regDSCC3_DSCC_PPS_CONFIG15 0x3131 12058#define regDSCC3_DSCC_PPS_CONFIG15_BASE_IDX 2 12059#define regDSCC3_DSCC_PPS_CONFIG16 0x3132 12060#define regDSCC3_DSCC_PPS_CONFIG16_BASE_IDX 2 12061#define regDSCC3_DSCC_PPS_CONFIG17 0x3133 12062#define regDSCC3_DSCC_PPS_CONFIG17_BASE_IDX 2 12063#define regDSCC3_DSCC_PPS_CONFIG18 0x3134 12064#define regDSCC3_DSCC_PPS_CONFIG18_BASE_IDX 2 12065#define regDSCC3_DSCC_PPS_CONFIG19 0x3135 12066#define regDSCC3_DSCC_PPS_CONFIG19_BASE_IDX 2 12067#define regDSCC3_DSCC_PPS_CONFIG20 0x3136 12068#define regDSCC3_DSCC_PPS_CONFIG20_BASE_IDX 2 12069#define regDSCC3_DSCC_PPS_CONFIG21 0x3137 12070#define regDSCC3_DSCC_PPS_CONFIG21_BASE_IDX 2 12071#define regDSCC3_DSCC_PPS_CONFIG22 0x3138 12072#define regDSCC3_DSCC_PPS_CONFIG22_BASE_IDX 2 12073#define regDSCC3_DSCC_MEM_POWER_CONTROL 0x3139 12074#define regDSCC3_DSCC_MEM_POWER_CONTROL_BASE_IDX 2 12075#define regDSCC3_DSCC_R_Y_SQUARED_ERROR_LOWER 0x313a 12076#define regDSCC3_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX 2 12077#define regDSCC3_DSCC_R_Y_SQUARED_ERROR_UPPER 0x313b 12078#define regDSCC3_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX 2 12079#define regDSCC3_DSCC_G_CB_SQUARED_ERROR_LOWER 0x313c 12080#define regDSCC3_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX 2 12081#define regDSCC3_DSCC_G_CB_SQUARED_ERROR_UPPER 0x313d 12082#define regDSCC3_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX 2 12083#define regDSCC3_DSCC_B_CR_SQUARED_ERROR_LOWER 0x313e 12084#define regDSCC3_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX 2 12085#define regDSCC3_DSCC_B_CR_SQUARED_ERROR_UPPER 0x313f 12086#define regDSCC3_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX 2 12087#define regDSCC3_DSCC_MAX_ABS_ERROR0 0x3140 12088#define regDSCC3_DSCC_MAX_ABS_ERROR0_BASE_IDX 2 12089#define regDSCC3_DSCC_MAX_ABS_ERROR1 0x3141 12090#define regDSCC3_DSCC_MAX_ABS_ERROR1_BASE_IDX 2 12091#define regDSCC3_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL 0x3142 12092#define regDSCC3_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2 12093#define regDSCC3_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL 0x3143 12094#define regDSCC3_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2 12095#define regDSCC3_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL 0x3144 12096#define regDSCC3_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2 12097#define regDSCC3_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL 0x3145 12098#define regDSCC3_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2 12099#define regDSCC3_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL 0x3146 12100#define regDSCC3_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2 12101#define regDSCC3_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL 0x3147 12102#define regDSCC3_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2 12103#define regDSCC3_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL 0x3148 12104#define regDSCC3_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2 12105#define regDSCC3_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL 0x3149 12106#define regDSCC3_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2 12107 12108 12109// addressBlock: dcn_dc_dsc3_dispdec_dsccif_dispdec 12110// base address: 0x450 12111#define regDSCCIF3_DSCCIF_CONFIG0 0x3119 12112#define regDSCCIF3_DSCCIF_CONFIG0_BASE_IDX 2 12113#define regDSCCIF3_DSCCIF_CONFIG1 0x311a 12114#define regDSCCIF3_DSCCIF_CONFIG1_BASE_IDX 2 12115 12116 12117// addressBlock: dcn_dc_dsc3_dispdec_dsc_top_dispdec 12118// base address: 0x450 12119#define regDSC_TOP3_DSC_TOP_CONTROL 0x3114 12120#define regDSC_TOP3_DSC_TOP_CONTROL_BASE_IDX 2 12121#define regDSC_TOP3_DSC_DEBUG_CONTROL 0x3115 12122#define regDSC_TOP3_DSC_DEBUG_CONTROL_BASE_IDX 2 12123 12124 12125// addressBlock: dcn_dc_hpo_hpo_top_dispdec 12126// base address: 0x2790c 12127#define regHPO_TOP_CLOCK_CONTROL 0x0e43 12128#define regHPO_TOP_CLOCK_CONTROL_BASE_IDX 3 12129#define regHPO_TOP_HW_CONTROL 0x0e4a 12130#define regHPO_TOP_HW_CONTROL_BASE_IDX 3 12131 12132 12133// addressBlock: dcn_dc_hpo_dp_stream_mapper_dispdec 12134// base address: 0x27958 12135#define regDP_STREAM_MAPPER_CONTROL0 0x0e56 12136#define regDP_STREAM_MAPPER_CONTROL0_BASE_IDX 3 12137#define regDP_STREAM_MAPPER_CONTROL1 0x0e57 12138#define regDP_STREAM_MAPPER_CONTROL1_BASE_IDX 3 12139#define regDP_STREAM_MAPPER_CONTROL2 0x0e58 12140#define regDP_STREAM_MAPPER_CONTROL2_BASE_IDX 3 12141#define regDP_STREAM_MAPPER_CONTROL3 0x0e59 12142#define regDP_STREAM_MAPPER_CONTROL3_BASE_IDX 3 12143 12144 12145// addressBlock: dcn_dc_hpo_hdmi_stream_enc0_afmt_afmt_dispdec 12146// base address: 0x2646c 12147#define regAFMT5_AFMT_VBI_PACKET_CONTROL 0x091c 12148#define regAFMT5_AFMT_VBI_PACKET_CONTROL_BASE_IDX 3 12149#define regAFMT5_AFMT_AUDIO_PACKET_CONTROL2 0x091d 12150#define regAFMT5_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 3 12151#define regAFMT5_AFMT_AUDIO_INFO0 0x091e 12152#define regAFMT5_AFMT_AUDIO_INFO0_BASE_IDX 3 12153#define regAFMT5_AFMT_AUDIO_INFO1 0x091f 12154#define regAFMT5_AFMT_AUDIO_INFO1_BASE_IDX 3 12155#define regAFMT5_AFMT_60958_0 0x0920 12156#define regAFMT5_AFMT_60958_0_BASE_IDX 3 12157#define regAFMT5_AFMT_60958_1 0x0921 12158#define regAFMT5_AFMT_60958_1_BASE_IDX 3 12159#define regAFMT5_AFMT_AUDIO_CRC_CONTROL 0x0922 12160#define regAFMT5_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 3 12161#define regAFMT5_AFMT_RAMP_CONTROL0 0x0923 12162#define regAFMT5_AFMT_RAMP_CONTROL0_BASE_IDX 3 12163#define regAFMT5_AFMT_RAMP_CONTROL1 0x0924 12164#define regAFMT5_AFMT_RAMP_CONTROL1_BASE_IDX 3 12165#define regAFMT5_AFMT_RAMP_CONTROL2 0x0925 12166#define regAFMT5_AFMT_RAMP_CONTROL2_BASE_IDX 3 12167#define regAFMT5_AFMT_RAMP_CONTROL3 0x0926 12168#define regAFMT5_AFMT_RAMP_CONTROL3_BASE_IDX 3 12169#define regAFMT5_AFMT_60958_2 0x0927 12170#define regAFMT5_AFMT_60958_2_BASE_IDX 3 12171#define regAFMT5_AFMT_AUDIO_CRC_RESULT 0x0928 12172#define regAFMT5_AFMT_AUDIO_CRC_RESULT_BASE_IDX 3 12173#define regAFMT5_AFMT_STATUS 0x0929 12174#define regAFMT5_AFMT_STATUS_BASE_IDX 3 12175#define regAFMT5_AFMT_AUDIO_PACKET_CONTROL 0x092a 12176#define regAFMT5_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 3 12177#define regAFMT5_AFMT_INFOFRAME_CONTROL0 0x092b 12178#define regAFMT5_AFMT_INFOFRAME_CONTROL0_BASE_IDX 3 12179#define regAFMT5_AFMT_INTERRUPT_STATUS 0x092c 12180#define regAFMT5_AFMT_INTERRUPT_STATUS_BASE_IDX 3 12181#define regAFMT5_AFMT_AUDIO_SRC_CONTROL 0x092d 12182#define regAFMT5_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 3 12183#define regAFMT5_AFMT_MEM_PWR 0x092f 12184#define regAFMT5_AFMT_MEM_PWR_BASE_IDX 3 12185 12186 12187// addressBlock: dcn_dc_hpo_hdmi_stream_enc0_dme_dme_dispdec 12188// base address: 0x264f0 12189#define regDME5_DME_CONTROL 0x093c 12190#define regDME5_DME_CONTROL_BASE_IDX 3 12191#define regDME5_DME_MEMORY_CONTROL 0x093d 12192#define regDME5_DME_MEMORY_CONTROL_BASE_IDX 3 12193 12194 12195// addressBlock: dcn_dc_hpo_hdmi_stream_enc0_vpg_vpg_dispdec 12196// base address: 0x264c4 12197#define regVPG5_VPG_GENERIC_PACKET_ACCESS_CTRL 0x0931 12198#define regVPG5_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 3 12199#define regVPG5_VPG_GENERIC_PACKET_DATA 0x0932 12200#define regVPG5_VPG_GENERIC_PACKET_DATA_BASE_IDX 3 12201#define regVPG5_VPG_GSP_FRAME_UPDATE_CTRL 0x0933 12202#define regVPG5_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 3 12203#define regVPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x0934 12204#define regVPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 3 12205#define regVPG5_VPG_GENERIC_STATUS 0x0935 12206#define regVPG5_VPG_GENERIC_STATUS_BASE_IDX 3 12207#define regVPG5_VPG_MEM_PWR 0x0936 12208#define regVPG5_VPG_MEM_PWR_BASE_IDX 3 12209#define regVPG5_VPG_ISRC1_2_ACCESS_CTRL 0x0937 12210#define regVPG5_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 3 12211#define regVPG5_VPG_ISRC1_2_DATA 0x0938 12212#define regVPG5_VPG_ISRC1_2_DATA_BASE_IDX 3 12213#define regVPG5_VPG_MPEG_INFO0 0x0939 12214#define regVPG5_VPG_MPEG_INFO0_BASE_IDX 3 12215#define regVPG5_VPG_MPEG_INFO1 0x093a 12216#define regVPG5_VPG_MPEG_INFO1_BASE_IDX 3 12217 12218 12219// addressBlock: dcn_dc_hpo_dp_stream_enc0_dispdec 12220// base address: 0x1ab8c 12221#define regDP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL 0x3623 12222#define regDP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL_BASE_IDX 2 12223#define regDP_STREAM_ENC0_DP_STREAM_ENC_INPUT_MUX_CONTROL 0x3624 12224#define regDP_STREAM_ENC0_DP_STREAM_ENC_INPUT_MUX_CONTROL_BASE_IDX 2 12225#define regDP_STREAM_ENC0_DP_STREAM_ENC_AUDIO_CONTROL 0x3625 12226#define regDP_STREAM_ENC0_DP_STREAM_ENC_AUDIO_CONTROL_BASE_IDX 2 12227#define regDP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0 0x3626 12228#define regDP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0_BASE_IDX 2 12229#define regDP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1 0x3627 12230#define regDP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1_BASE_IDX 2 12231#define regDP_STREAM_ENC0_DP_STREAM_ENC_SPARE 0x3628 12232#define regDP_STREAM_ENC0_DP_STREAM_ENC_SPARE_BASE_IDX 2 12233 12234 12235// addressBlock: dcn_dc_hpo_dp_stream_enc0_apg_apg_dispdec 12236// base address: 0x1abc0 12237#define regAPG0_APG_CONTROL 0x3630 12238#define regAPG0_APG_CONTROL_BASE_IDX 2 12239#define regAPG0_APG_CONTROL2 0x3631 12240#define regAPG0_APG_CONTROL2_BASE_IDX 2 12241#define regAPG0_APG_DBG_GEN_CONTROL 0x3632 12242#define regAPG0_APG_DBG_GEN_CONTROL_BASE_IDX 2 12243#define regAPG0_APG_PACKET_CONTROL 0x3633 12244#define regAPG0_APG_PACKET_CONTROL_BASE_IDX 2 12245#define regAPG0_APG_AUDIO_CRC_CONTROL 0x363a 12246#define regAPG0_APG_AUDIO_CRC_CONTROL_BASE_IDX 2 12247#define regAPG0_APG_AUDIO_CRC_CONTROL2 0x363b 12248#define regAPG0_APG_AUDIO_CRC_CONTROL2_BASE_IDX 2 12249#define regAPG0_APG_AUDIO_CRC_RESULT 0x363c 12250#define regAPG0_APG_AUDIO_CRC_RESULT_BASE_IDX 2 12251#define regAPG0_APG_STATUS 0x3641 12252#define regAPG0_APG_STATUS_BASE_IDX 2 12253#define regAPG0_APG_STATUS2 0x3642 12254#define regAPG0_APG_STATUS2_BASE_IDX 2 12255#define regAPG0_APG_MEM_PWR 0x3644 12256#define regAPG0_APG_MEM_PWR_BASE_IDX 2 12257#define regAPG0_APG_SPARE 0x3646 12258#define regAPG0_APG_SPARE_BASE_IDX 2 12259 12260 12261// addressBlock: dcn_dc_hpo_dp_stream_enc0_dme_dme_dispdec 12262// base address: 0x1ac38 12263#define regDME6_DME_CONTROL 0x364e 12264#define regDME6_DME_CONTROL_BASE_IDX 2 12265#define regDME6_DME_MEMORY_CONTROL 0x364f 12266#define regDME6_DME_MEMORY_CONTROL_BASE_IDX 2 12267 12268 12269// addressBlock: dcn_dc_hpo_dp_stream_enc0_vpg_vpg_dispdec 12270// base address: 0x1ac44 12271#define regVPG6_VPG_GENERIC_PACKET_ACCESS_CTRL 0x3651 12272#define regVPG6_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2 12273#define regVPG6_VPG_GENERIC_PACKET_DATA 0x3652 12274#define regVPG6_VPG_GENERIC_PACKET_DATA_BASE_IDX 2 12275#define regVPG6_VPG_GSP_FRAME_UPDATE_CTRL 0x3653 12276#define regVPG6_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2 12277#define regVPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x3654 12278#define regVPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2 12279#define regVPG6_VPG_GENERIC_STATUS 0x3655 12280#define regVPG6_VPG_GENERIC_STATUS_BASE_IDX 2 12281#define regVPG6_VPG_MEM_PWR 0x3656 12282#define regVPG6_VPG_MEM_PWR_BASE_IDX 2 12283#define regVPG6_VPG_ISRC1_2_ACCESS_CTRL 0x3657 12284#define regVPG6_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2 12285#define regVPG6_VPG_ISRC1_2_DATA 0x3658 12286#define regVPG6_VPG_ISRC1_2_DATA_BASE_IDX 2 12287#define regVPG6_VPG_MPEG_INFO0 0x3659 12288#define regVPG6_VPG_MPEG_INFO0_BASE_IDX 2 12289#define regVPG6_VPG_MPEG_INFO1 0x365a 12290#define regVPG6_VPG_MPEG_INFO1_BASE_IDX 2 12291 12292 12293// addressBlock: dcn_dc_hpo_dp_sym32_enc0_dispdec 12294// base address: 0x1ac74 12295#define regDP_SYM32_ENC0_DP_SYM32_ENC_CONTROL 0x365d 12296#define regDP_SYM32_ENC0_DP_SYM32_ENC_CONTROL_BASE_IDX 2 12297#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL 0x365e 12298#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL_BASE_IDX 2 12299#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL 0x365f 12300#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 12301#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL 0x3660 12302#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 12303#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT 0x3661 12304#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT_BASE_IDX 2 12305#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA0 0x3662 12306#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA0_BASE_IDX 2 12307#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA1 0x3663 12308#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA1_BASE_IDX 2 12309#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA2 0x3664 12310#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA2_BASE_IDX 2 12311#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA3 0x3665 12312#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA3_BASE_IDX 2 12313#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA4 0x3666 12314#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA4_BASE_IDX 2 12315#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA5 0x3667 12316#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA5_BASE_IDX 2 12317#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA6 0x3668 12318#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA6_BASE_IDX 2 12319#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA7 0x3669 12320#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA7_BASE_IDX 2 12321#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA8 0x366a 12322#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA8_BASE_IDX 2 12323#define regDP_SYM32_ENC0_DP_SYM32_ENC_HBLANK_CONTROL 0x366b 12324#define regDP_SYM32_ENC0_DP_SYM32_ENC_HBLANK_CONTROL_BASE_IDX 2 12325#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0 0x366c 12326#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0_BASE_IDX 2 12327#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1 0x366d 12328#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1_BASE_IDX 2 12329#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2 0x366e 12330#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2_BASE_IDX 2 12331#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3 0x366f 12332#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3_BASE_IDX 2 12333#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4 0x3670 12334#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4_BASE_IDX 2 12335#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5 0x3671 12336#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5_BASE_IDX 2 12337#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6 0x3672 12338#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6_BASE_IDX 2 12339#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7 0x3673 12340#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7_BASE_IDX 2 12341#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8 0x3674 12342#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8_BASE_IDX 2 12343#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9 0x3675 12344#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9_BASE_IDX 2 12345#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10 0x3676 12346#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10_BASE_IDX 2 12347#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11 0x3677 12348#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11_BASE_IDX 2 12349#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12 0x3678 12350#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12_BASE_IDX 2 12351#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13 0x3679 12352#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13_BASE_IDX 2 12353#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14 0x367a 12354#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14_BASE_IDX 2 12355#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_CONTROL 0x367b 12356#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_CONTROL_BASE_IDX 2 12357#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0 0x367c 12358#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0_BASE_IDX 2 12359#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL1 0x367d 12360#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL1_BASE_IDX 2 12361#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL 0x367e 12362#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL_BASE_IDX 2 12363#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_CONTROL 0x3683 12364#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_CONTROL_BASE_IDX 2 12365#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_VBID_CONTROL 0x3684 12366#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_VBID_CONTROL_BASE_IDX 2 12367#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_STREAM_CONTROL 0x3685 12368#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_STREAM_CONTROL_BASE_IDX 2 12369#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL 0x3686 12370#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL_BASE_IDX 2 12371#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_CONTROL 0x3687 12372#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_CONTROL_BASE_IDX 2 12373#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT0 0x3688 12374#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT0_BASE_IDX 2 12375#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT1 0x3689 12376#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT1_BASE_IDX 2 12377#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_STATUS 0x368a 12378#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_STATUS_BASE_IDX 2 12379#define regDP_SYM32_ENC0_DP_SYM32_ENC_MEM_POWER_CONTROL 0x368b 12380#define regDP_SYM32_ENC0_DP_SYM32_ENC_MEM_POWER_CONTROL_BASE_IDX 2 12381#define regDP_SYM32_ENC0_DP_SYM32_ENC_SPARE 0x368c 12382#define regDP_SYM32_ENC0_DP_SYM32_ENC_SPARE_BASE_IDX 2 12383 12384 12385// addressBlock: dcn_dc_hpo_dp_stream_enc1_dispdec 12386// base address: 0x1aedc 12387#define regDP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL 0x36f7 12388#define regDP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL_BASE_IDX 2 12389#define regDP_STREAM_ENC1_DP_STREAM_ENC_INPUT_MUX_CONTROL 0x36f8 12390#define regDP_STREAM_ENC1_DP_STREAM_ENC_INPUT_MUX_CONTROL_BASE_IDX 2 12391#define regDP_STREAM_ENC1_DP_STREAM_ENC_AUDIO_CONTROL 0x36f9 12392#define regDP_STREAM_ENC1_DP_STREAM_ENC_AUDIO_CONTROL_BASE_IDX 2 12393#define regDP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0 0x36fa 12394#define regDP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0_BASE_IDX 2 12395#define regDP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1 0x36fb 12396#define regDP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1_BASE_IDX 2 12397#define regDP_STREAM_ENC1_DP_STREAM_ENC_SPARE 0x36fc 12398#define regDP_STREAM_ENC1_DP_STREAM_ENC_SPARE_BASE_IDX 2 12399 12400 12401// addressBlock: dcn_dc_hpo_dp_stream_enc1_apg_apg_dispdec 12402// base address: 0x1af10 12403#define regAPG1_APG_CONTROL 0x3704 12404#define regAPG1_APG_CONTROL_BASE_IDX 2 12405#define regAPG1_APG_CONTROL2 0x3705 12406#define regAPG1_APG_CONTROL2_BASE_IDX 2 12407#define regAPG1_APG_DBG_GEN_CONTROL 0x3706 12408#define regAPG1_APG_DBG_GEN_CONTROL_BASE_IDX 2 12409#define regAPG1_APG_PACKET_CONTROL 0x3707 12410#define regAPG1_APG_PACKET_CONTROL_BASE_IDX 2 12411#define regAPG1_APG_AUDIO_CRC_CONTROL 0x370e 12412#define regAPG1_APG_AUDIO_CRC_CONTROL_BASE_IDX 2 12413#define regAPG1_APG_AUDIO_CRC_CONTROL2 0x370f 12414#define regAPG1_APG_AUDIO_CRC_CONTROL2_BASE_IDX 2 12415#define regAPG1_APG_AUDIO_CRC_RESULT 0x3710 12416#define regAPG1_APG_AUDIO_CRC_RESULT_BASE_IDX 2 12417#define regAPG1_APG_STATUS 0x3715 12418#define regAPG1_APG_STATUS_BASE_IDX 2 12419#define regAPG1_APG_STATUS2 0x3716 12420#define regAPG1_APG_STATUS2_BASE_IDX 2 12421#define regAPG1_APG_MEM_PWR 0x3718 12422#define regAPG1_APG_MEM_PWR_BASE_IDX 2 12423#define regAPG1_APG_SPARE 0x371a 12424#define regAPG1_APG_SPARE_BASE_IDX 2 12425 12426 12427// addressBlock: dcn_dc_hpo_dp_stream_enc1_dme_dme_dispdec 12428// base address: 0x1af88 12429#define regDME7_DME_CONTROL 0x3722 12430#define regDME7_DME_CONTROL_BASE_IDX 2 12431#define regDME7_DME_MEMORY_CONTROL 0x3723 12432#define regDME7_DME_MEMORY_CONTROL_BASE_IDX 2 12433 12434 12435// addressBlock: dcn_dc_hpo_dp_stream_enc1_vpg_vpg_dispdec 12436// base address: 0x1af94 12437#define regVPG7_VPG_GENERIC_PACKET_ACCESS_CTRL 0x3725 12438#define regVPG7_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2 12439#define regVPG7_VPG_GENERIC_PACKET_DATA 0x3726 12440#define regVPG7_VPG_GENERIC_PACKET_DATA_BASE_IDX 2 12441#define regVPG7_VPG_GSP_FRAME_UPDATE_CTRL 0x3727 12442#define regVPG7_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2 12443#define regVPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x3728 12444#define regVPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2 12445#define regVPG7_VPG_GENERIC_STATUS 0x3729 12446#define regVPG7_VPG_GENERIC_STATUS_BASE_IDX 2 12447#define regVPG7_VPG_MEM_PWR 0x372a 12448#define regVPG7_VPG_MEM_PWR_BASE_IDX 2 12449#define regVPG7_VPG_ISRC1_2_ACCESS_CTRL 0x372b 12450#define regVPG7_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2 12451#define regVPG7_VPG_ISRC1_2_DATA 0x372c 12452#define regVPG7_VPG_ISRC1_2_DATA_BASE_IDX 2 12453#define regVPG7_VPG_MPEG_INFO0 0x372d 12454#define regVPG7_VPG_MPEG_INFO0_BASE_IDX 2 12455#define regVPG7_VPG_MPEG_INFO1 0x372e 12456#define regVPG7_VPG_MPEG_INFO1_BASE_IDX 2 12457 12458 12459// addressBlock: dcn_dc_hpo_dp_sym32_enc1_dispdec 12460// base address: 0x1afc4 12461#define regDP_SYM32_ENC1_DP_SYM32_ENC_CONTROL 0x3731 12462#define regDP_SYM32_ENC1_DP_SYM32_ENC_CONTROL_BASE_IDX 2 12463#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_FIFO_CONTROL 0x3732 12464#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_FIFO_CONTROL_BASE_IDX 2 12465#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL 0x3733 12466#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 12467#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL 0x3734 12468#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 12469#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT 0x3735 12470#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT_BASE_IDX 2 12471#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA0 0x3736 12472#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA0_BASE_IDX 2 12473#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA1 0x3737 12474#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA1_BASE_IDX 2 12475#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA2 0x3738 12476#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA2_BASE_IDX 2 12477#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA3 0x3739 12478#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA3_BASE_IDX 2 12479#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA4 0x373a 12480#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA4_BASE_IDX 2 12481#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA5 0x373b 12482#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA5_BASE_IDX 2 12483#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA6 0x373c 12484#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA6_BASE_IDX 2 12485#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA7 0x373d 12486#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA7_BASE_IDX 2 12487#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA8 0x373e 12488#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA8_BASE_IDX 2 12489#define regDP_SYM32_ENC1_DP_SYM32_ENC_HBLANK_CONTROL 0x373f 12490#define regDP_SYM32_ENC1_DP_SYM32_ENC_HBLANK_CONTROL_BASE_IDX 2 12491#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0 0x3740 12492#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0_BASE_IDX 2 12493#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1 0x3741 12494#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1_BASE_IDX 2 12495#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2 0x3742 12496#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2_BASE_IDX 2 12497#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3 0x3743 12498#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3_BASE_IDX 2 12499#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4 0x3744 12500#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4_BASE_IDX 2 12501#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5 0x3745 12502#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5_BASE_IDX 2 12503#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6 0x3746 12504#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6_BASE_IDX 2 12505#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7 0x3747 12506#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7_BASE_IDX 2 12507#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8 0x3748 12508#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8_BASE_IDX 2 12509#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9 0x3749 12510#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9_BASE_IDX 2 12511#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10 0x374a 12512#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10_BASE_IDX 2 12513#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11 0x374b 12514#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11_BASE_IDX 2 12515#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12 0x374c 12516#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12_BASE_IDX 2 12517#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13 0x374d 12518#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13_BASE_IDX 2 12519#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14 0x374e 12520#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14_BASE_IDX 2 12521#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_CONTROL 0x374f 12522#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_CONTROL_BASE_IDX 2 12523#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0 0x3750 12524#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0_BASE_IDX 2 12525#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL1 0x3751 12526#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL1_BASE_IDX 2 12527#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL 0x3752 12528#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL_BASE_IDX 2 12529#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_CONTROL 0x3757 12530#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_CONTROL_BASE_IDX 2 12531#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_VBID_CONTROL 0x3758 12532#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_VBID_CONTROL_BASE_IDX 2 12533#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_STREAM_CONTROL 0x3759 12534#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_STREAM_CONTROL_BASE_IDX 2 12535#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL 0x375a 12536#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL_BASE_IDX 2 12537#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_CONTROL 0x375b 12538#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_CONTROL_BASE_IDX 2 12539#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT0 0x375c 12540#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT0_BASE_IDX 2 12541#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT1 0x375d 12542#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT1_BASE_IDX 2 12543#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_STATUS 0x375e 12544#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_STATUS_BASE_IDX 2 12545#define regDP_SYM32_ENC1_DP_SYM32_ENC_MEM_POWER_CONTROL 0x375f 12546#define regDP_SYM32_ENC1_DP_SYM32_ENC_MEM_POWER_CONTROL_BASE_IDX 2 12547#define regDP_SYM32_ENC1_DP_SYM32_ENC_SPARE 0x3760 12548#define regDP_SYM32_ENC1_DP_SYM32_ENC_SPARE_BASE_IDX 2 12549 12550 12551// addressBlock: dcn_dc_hpo_dp_stream_enc2_dispdec 12552// base address: 0x1b22c 12553#define regDP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL 0x37cb 12554#define regDP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL_BASE_IDX 2 12555#define regDP_STREAM_ENC2_DP_STREAM_ENC_INPUT_MUX_CONTROL 0x37cc 12556#define regDP_STREAM_ENC2_DP_STREAM_ENC_INPUT_MUX_CONTROL_BASE_IDX 2 12557#define regDP_STREAM_ENC2_DP_STREAM_ENC_AUDIO_CONTROL 0x37cd 12558#define regDP_STREAM_ENC2_DP_STREAM_ENC_AUDIO_CONTROL_BASE_IDX 2 12559#define regDP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0 0x37ce 12560#define regDP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0_BASE_IDX 2 12561#define regDP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1 0x37cf 12562#define regDP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1_BASE_IDX 2 12563#define regDP_STREAM_ENC2_DP_STREAM_ENC_SPARE 0x37d0 12564#define regDP_STREAM_ENC2_DP_STREAM_ENC_SPARE_BASE_IDX 2 12565 12566 12567// addressBlock: dcn_dc_hpo_dp_stream_enc2_apg_apg_dispdec 12568// base address: 0x1b260 12569#define regAPG2_APG_CONTROL 0x37d8 12570#define regAPG2_APG_CONTROL_BASE_IDX 2 12571#define regAPG2_APG_CONTROL2 0x37d9 12572#define regAPG2_APG_CONTROL2_BASE_IDX 2 12573#define regAPG2_APG_DBG_GEN_CONTROL 0x37da 12574#define regAPG2_APG_DBG_GEN_CONTROL_BASE_IDX 2 12575#define regAPG2_APG_PACKET_CONTROL 0x37db 12576#define regAPG2_APG_PACKET_CONTROL_BASE_IDX 2 12577#define regAPG2_APG_AUDIO_CRC_CONTROL 0x37e2 12578#define regAPG2_APG_AUDIO_CRC_CONTROL_BASE_IDX 2 12579#define regAPG2_APG_AUDIO_CRC_CONTROL2 0x37e3 12580#define regAPG2_APG_AUDIO_CRC_CONTROL2_BASE_IDX 2 12581#define regAPG2_APG_AUDIO_CRC_RESULT 0x37e4 12582#define regAPG2_APG_AUDIO_CRC_RESULT_BASE_IDX 2 12583#define regAPG2_APG_STATUS 0x37e9 12584#define regAPG2_APG_STATUS_BASE_IDX 2 12585#define regAPG2_APG_STATUS2 0x37ea 12586#define regAPG2_APG_STATUS2_BASE_IDX 2 12587#define regAPG2_APG_MEM_PWR 0x37ec 12588#define regAPG2_APG_MEM_PWR_BASE_IDX 2 12589#define regAPG2_APG_SPARE 0x37ee 12590#define regAPG2_APG_SPARE_BASE_IDX 2 12591 12592 12593// addressBlock: dcn_dc_hpo_dp_stream_enc2_dme_dme_dispdec 12594// base address: 0x1b2d8 12595#define regDME8_DME_CONTROL 0x37f6 12596#define regDME8_DME_CONTROL_BASE_IDX 2 12597#define regDME8_DME_MEMORY_CONTROL 0x37f7 12598#define regDME8_DME_MEMORY_CONTROL_BASE_IDX 2 12599 12600 12601// addressBlock: dcn_dc_hpo_dp_stream_enc2_vpg_vpg_dispdec 12602// base address: 0x1b2e4 12603#define regVPG8_VPG_GENERIC_PACKET_ACCESS_CTRL 0x37f9 12604#define regVPG8_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2 12605#define regVPG8_VPG_GENERIC_PACKET_DATA 0x37fa 12606#define regVPG8_VPG_GENERIC_PACKET_DATA_BASE_IDX 2 12607#define regVPG8_VPG_GSP_FRAME_UPDATE_CTRL 0x37fb 12608#define regVPG8_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2 12609#define regVPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x37fc 12610#define regVPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2 12611#define regVPG8_VPG_GENERIC_STATUS 0x37fd 12612#define regVPG8_VPG_GENERIC_STATUS_BASE_IDX 2 12613#define regVPG8_VPG_MEM_PWR 0x37fe 12614#define regVPG8_VPG_MEM_PWR_BASE_IDX 2 12615#define regVPG8_VPG_ISRC1_2_ACCESS_CTRL 0x37ff 12616#define regVPG8_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2 12617#define regVPG8_VPG_ISRC1_2_DATA 0x3800 12618#define regVPG8_VPG_ISRC1_2_DATA_BASE_IDX 2 12619#define regVPG8_VPG_MPEG_INFO0 0x3801 12620#define regVPG8_VPG_MPEG_INFO0_BASE_IDX 2 12621#define regVPG8_VPG_MPEG_INFO1 0x3802 12622#define regVPG8_VPG_MPEG_INFO1_BASE_IDX 2 12623 12624 12625// addressBlock: dcn_dc_hpo_dp_sym32_enc2_dispdec 12626// base address: 0x1b314 12627#define regDP_SYM32_ENC2_DP_SYM32_ENC_CONTROL 0x3805 12628#define regDP_SYM32_ENC2_DP_SYM32_ENC_CONTROL_BASE_IDX 2 12629#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_FIFO_CONTROL 0x3806 12630#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_FIFO_CONTROL_BASE_IDX 2 12631#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL 0x3807 12632#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 12633#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL 0x3808 12634#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 12635#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT 0x3809 12636#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT_BASE_IDX 2 12637#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA0 0x380a 12638#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA0_BASE_IDX 2 12639#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA1 0x380b 12640#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA1_BASE_IDX 2 12641#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA2 0x380c 12642#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA2_BASE_IDX 2 12643#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA3 0x380d 12644#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA3_BASE_IDX 2 12645#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA4 0x380e 12646#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA4_BASE_IDX 2 12647#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA5 0x380f 12648#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA5_BASE_IDX 2 12649#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA6 0x3810 12650#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA6_BASE_IDX 2 12651#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA7 0x3811 12652#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA7_BASE_IDX 2 12653#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA8 0x3812 12654#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA8_BASE_IDX 2 12655#define regDP_SYM32_ENC2_DP_SYM32_ENC_HBLANK_CONTROL 0x3813 12656#define regDP_SYM32_ENC2_DP_SYM32_ENC_HBLANK_CONTROL_BASE_IDX 2 12657#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0 0x3814 12658#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0_BASE_IDX 2 12659#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1 0x3815 12660#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1_BASE_IDX 2 12661#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2 0x3816 12662#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2_BASE_IDX 2 12663#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3 0x3817 12664#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3_BASE_IDX 2 12665#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4 0x3818 12666#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4_BASE_IDX 2 12667#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5 0x3819 12668#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5_BASE_IDX 2 12669#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6 0x381a 12670#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6_BASE_IDX 2 12671#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7 0x381b 12672#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7_BASE_IDX 2 12673#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8 0x381c 12674#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8_BASE_IDX 2 12675#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9 0x381d 12676#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9_BASE_IDX 2 12677#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10 0x381e 12678#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10_BASE_IDX 2 12679#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11 0x381f 12680#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11_BASE_IDX 2 12681#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12 0x3820 12682#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12_BASE_IDX 2 12683#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13 0x3821 12684#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13_BASE_IDX 2 12685#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14 0x3822 12686#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14_BASE_IDX 2 12687#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_CONTROL 0x3823 12688#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_CONTROL_BASE_IDX 2 12689#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0 0x3824 12690#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0_BASE_IDX 2 12691#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL1 0x3825 12692#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL1_BASE_IDX 2 12693#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL 0x3826 12694#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL_BASE_IDX 2 12695#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_CONTROL 0x382b 12696#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_CONTROL_BASE_IDX 2 12697#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_VBID_CONTROL 0x382c 12698#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_VBID_CONTROL_BASE_IDX 2 12699#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_STREAM_CONTROL 0x382d 12700#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_STREAM_CONTROL_BASE_IDX 2 12701#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL 0x382e 12702#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL_BASE_IDX 2 12703#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_CONTROL 0x382f 12704#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_CONTROL_BASE_IDX 2 12705#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT0 0x3830 12706#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT0_BASE_IDX 2 12707#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT1 0x3831 12708#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT1_BASE_IDX 2 12709#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_STATUS 0x3832 12710#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_STATUS_BASE_IDX 2 12711#define regDP_SYM32_ENC2_DP_SYM32_ENC_MEM_POWER_CONTROL 0x3833 12712#define regDP_SYM32_ENC2_DP_SYM32_ENC_MEM_POWER_CONTROL_BASE_IDX 2 12713#define regDP_SYM32_ENC2_DP_SYM32_ENC_SPARE 0x3834 12714#define regDP_SYM32_ENC2_DP_SYM32_ENC_SPARE_BASE_IDX 2 12715 12716 12717// addressBlock: dcn_dc_hpo_dp_stream_enc3_dispdec 12718// base address: 0x1b57c 12719#define regDP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL 0x389f 12720#define regDP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL_BASE_IDX 2 12721#define regDP_STREAM_ENC3_DP_STREAM_ENC_INPUT_MUX_CONTROL 0x38a0 12722#define regDP_STREAM_ENC3_DP_STREAM_ENC_INPUT_MUX_CONTROL_BASE_IDX 2 12723#define regDP_STREAM_ENC3_DP_STREAM_ENC_AUDIO_CONTROL 0x38a1 12724#define regDP_STREAM_ENC3_DP_STREAM_ENC_AUDIO_CONTROL_BASE_IDX 2 12725#define regDP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0 0x38a2 12726#define regDP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0_BASE_IDX 2 12727#define regDP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1 0x38a3 12728#define regDP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1_BASE_IDX 2 12729#define regDP_STREAM_ENC3_DP_STREAM_ENC_SPARE 0x38a4 12730#define regDP_STREAM_ENC3_DP_STREAM_ENC_SPARE_BASE_IDX 2 12731 12732 12733// addressBlock: dcn_dc_hpo_dp_stream_enc3_apg_apg_dispdec 12734// base address: 0x1b5b0 12735#define regAPG3_APG_CONTROL 0x38ac 12736#define regAPG3_APG_CONTROL_BASE_IDX 2 12737#define regAPG3_APG_CONTROL2 0x38ad 12738#define regAPG3_APG_CONTROL2_BASE_IDX 2 12739#define regAPG3_APG_DBG_GEN_CONTROL 0x38ae 12740#define regAPG3_APG_DBG_GEN_CONTROL_BASE_IDX 2 12741#define regAPG3_APG_PACKET_CONTROL 0x38af 12742#define regAPG3_APG_PACKET_CONTROL_BASE_IDX 2 12743#define regAPG3_APG_AUDIO_CRC_CONTROL 0x38b6 12744#define regAPG3_APG_AUDIO_CRC_CONTROL_BASE_IDX 2 12745#define regAPG3_APG_AUDIO_CRC_CONTROL2 0x38b7 12746#define regAPG3_APG_AUDIO_CRC_CONTROL2_BASE_IDX 2 12747#define regAPG3_APG_AUDIO_CRC_RESULT 0x38b8 12748#define regAPG3_APG_AUDIO_CRC_RESULT_BASE_IDX 2 12749#define regAPG3_APG_STATUS 0x38bd 12750#define regAPG3_APG_STATUS_BASE_IDX 2 12751#define regAPG3_APG_STATUS2 0x38be 12752#define regAPG3_APG_STATUS2_BASE_IDX 2 12753#define regAPG3_APG_MEM_PWR 0x38c0 12754#define regAPG3_APG_MEM_PWR_BASE_IDX 2 12755#define regAPG3_APG_SPARE 0x38c2 12756#define regAPG3_APG_SPARE_BASE_IDX 2 12757 12758 12759// addressBlock: dcn_dc_hpo_dp_stream_enc3_dme_dme_dispdec 12760// base address: 0x1b628 12761#define regDME9_DME_CONTROL 0x38ca 12762#define regDME9_DME_CONTROL_BASE_IDX 2 12763#define regDME9_DME_MEMORY_CONTROL 0x38cb 12764#define regDME9_DME_MEMORY_CONTROL_BASE_IDX 2 12765 12766 12767// addressBlock: dcn_dc_hpo_dp_stream_enc3_vpg_vpg_dispdec 12768// base address: 0x1b634 12769#define regVPG9_VPG_GENERIC_PACKET_ACCESS_CTRL 0x38cd 12770#define regVPG9_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2 12771#define regVPG9_VPG_GENERIC_PACKET_DATA 0x38ce 12772#define regVPG9_VPG_GENERIC_PACKET_DATA_BASE_IDX 2 12773#define regVPG9_VPG_GSP_FRAME_UPDATE_CTRL 0x38cf 12774#define regVPG9_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2 12775#define regVPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x38d0 12776#define regVPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2 12777#define regVPG9_VPG_GENERIC_STATUS 0x38d1 12778#define regVPG9_VPG_GENERIC_STATUS_BASE_IDX 2 12779#define regVPG9_VPG_MEM_PWR 0x38d2 12780#define regVPG9_VPG_MEM_PWR_BASE_IDX 2 12781#define regVPG9_VPG_ISRC1_2_ACCESS_CTRL 0x38d3 12782#define regVPG9_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2 12783#define regVPG9_VPG_ISRC1_2_DATA 0x38d4 12784#define regVPG9_VPG_ISRC1_2_DATA_BASE_IDX 2 12785#define regVPG9_VPG_MPEG_INFO0 0x38d5 12786#define regVPG9_VPG_MPEG_INFO0_BASE_IDX 2 12787#define regVPG9_VPG_MPEG_INFO1 0x38d6 12788#define regVPG9_VPG_MPEG_INFO1_BASE_IDX 2 12789 12790 12791// addressBlock: dcn_dc_hpo_dp_sym32_enc3_dispdec 12792// base address: 0x1b664 12793#define regDP_SYM32_ENC3_DP_SYM32_ENC_CONTROL 0x38d9 12794#define regDP_SYM32_ENC3_DP_SYM32_ENC_CONTROL_BASE_IDX 2 12795#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_FIFO_CONTROL 0x38da 12796#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_FIFO_CONTROL_BASE_IDX 2 12797#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL 0x38db 12798#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 12799#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL 0x38dc 12800#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 12801#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT 0x38dd 12802#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT_BASE_IDX 2 12803#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA0 0x38de 12804#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA0_BASE_IDX 2 12805#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA1 0x38df 12806#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA1_BASE_IDX 2 12807#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA2 0x38e0 12808#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA2_BASE_IDX 2 12809#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA3 0x38e1 12810#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA3_BASE_IDX 2 12811#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA4 0x38e2 12812#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA4_BASE_IDX 2 12813#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA5 0x38e3 12814#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA5_BASE_IDX 2 12815#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA6 0x38e4 12816#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA6_BASE_IDX 2 12817#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA7 0x38e5 12818#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA7_BASE_IDX 2 12819#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA8 0x38e6 12820#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA8_BASE_IDX 2 12821#define regDP_SYM32_ENC3_DP_SYM32_ENC_HBLANK_CONTROL 0x38e7 12822#define regDP_SYM32_ENC3_DP_SYM32_ENC_HBLANK_CONTROL_BASE_IDX 2 12823#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0 0x38e8 12824#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0_BASE_IDX 2 12825#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1 0x38e9 12826#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1_BASE_IDX 2 12827#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2 0x38ea 12828#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2_BASE_IDX 2 12829#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3 0x38eb 12830#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3_BASE_IDX 2 12831#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4 0x38ec 12832#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4_BASE_IDX 2 12833#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5 0x38ed 12834#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5_BASE_IDX 2 12835#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6 0x38ee 12836#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6_BASE_IDX 2 12837#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7 0x38ef 12838#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7_BASE_IDX 2 12839#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8 0x38f0 12840#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8_BASE_IDX 2 12841#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9 0x38f1 12842#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9_BASE_IDX 2 12843#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10 0x38f2 12844#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10_BASE_IDX 2 12845#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11 0x38f3 12846#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11_BASE_IDX 2 12847#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12 0x38f4 12848#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12_BASE_IDX 2 12849#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13 0x38f5 12850#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13_BASE_IDX 2 12851#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14 0x38f6 12852#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14_BASE_IDX 2 12853#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_CONTROL 0x38f7 12854#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_CONTROL_BASE_IDX 2 12855#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0 0x38f8 12856#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0_BASE_IDX 2 12857#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL1 0x38f9 12858#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL1_BASE_IDX 2 12859#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL 0x38fa 12860#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL_BASE_IDX 2 12861#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_CONTROL 0x38ff 12862#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_CONTROL_BASE_IDX 2 12863#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_VBID_CONTROL 0x3900 12864#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_VBID_CONTROL_BASE_IDX 2 12865#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_STREAM_CONTROL 0x3901 12866#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_STREAM_CONTROL_BASE_IDX 2 12867#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL 0x3902 12868#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL_BASE_IDX 2 12869#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_CONTROL 0x3903 12870#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_CONTROL_BASE_IDX 2 12871#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT0 0x3904 12872#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT0_BASE_IDX 2 12873#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT1 0x3905 12874#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT1_BASE_IDX 2 12875#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_STATUS 0x3906 12876#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_STATUS_BASE_IDX 2 12877#define regDP_SYM32_ENC3_DP_SYM32_ENC_MEM_POWER_CONTROL 0x3907 12878#define regDP_SYM32_ENC3_DP_SYM32_ENC_MEM_POWER_CONTROL_BASE_IDX 2 12879#define regDP_SYM32_ENC3_DP_SYM32_ENC_SPARE 0x3908 12880#define regDP_SYM32_ENC3_DP_SYM32_ENC_SPARE_BASE_IDX 2 12881 12882 12883// addressBlock: dcn_dc_hpo_dp_link_enc0_dispdec 12884// base address: 0x1ad5c 12885#define regDP_LINK_ENC0_DP_LINK_ENC_CLOCK_CONTROL 0x3697 12886#define regDP_LINK_ENC0_DP_LINK_ENC_CLOCK_CONTROL_BASE_IDX 2 12887#define regDP_LINK_ENC0_DP_LINK_ENC_SPARE 0x3698 12888#define regDP_LINK_ENC0_DP_LINK_ENC_SPARE_BASE_IDX 2 12889 12890 12891// addressBlock: dcn_dc_hpo_dp_dphy_sym320_dispdec 12892// base address: 0x1ae00 12893#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL 0x36c0 12894#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL_BASE_IDX 2 12895#define regDP_DPHY_SYM320_DP_DPHY_SYM32_STATUS 0x36c1 12896#define regDP_DPHY_SYM320_DP_DPHY_SYM32_STATUS_BASE_IDX 2 12897#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_UPDATE 0x36c4 12898#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_UPDATE_BASE_IDX 2 12899#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL0 0x36c5 12900#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL0_BASE_IDX 2 12901#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL1 0x36c6 12902#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL1_BASE_IDX 2 12903#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL2 0x36c7 12904#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL2_BASE_IDX 2 12905#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL3 0x36c8 12906#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL3_BASE_IDX 2 12907#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC0 0x36cb 12908#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC0_BASE_IDX 2 12909#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC1 0x36cc 12910#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC1_BASE_IDX 2 12911#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC2 0x36cd 12912#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC2_BASE_IDX 2 12913#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC3 0x36ce 12914#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC3_BASE_IDX 2 12915#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS0 0x36d1 12916#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS0_BASE_IDX 2 12917#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS1 0x36d2 12918#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS1_BASE_IDX 2 12919#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS2 0x36d3 12920#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS2_BASE_IDX 2 12921#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS3 0x36d4 12922#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS3_BASE_IDX 2 12923#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG 0x36d7 12924#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG_BASE_IDX 2 12925#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED0 0x36d8 12926#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED0_BASE_IDX 2 12927#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED1 0x36d9 12928#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED1_BASE_IDX 2 12929#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED2 0x36da 12930#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED2_BASE_IDX 2 12931#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED3 0x36db 12932#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED3_BASE_IDX 2 12933#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_SQ_PULSE 0x36dc 12934#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_SQ_PULSE_BASE_IDX 2 12935#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM0 0x36dd 12936#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM0_BASE_IDX 2 12937#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM1 0x36de 12938#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM1_BASE_IDX 2 12939#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM2 0x36df 12940#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM2_BASE_IDX 2 12941#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM3 0x36e0 12942#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM3_BASE_IDX 2 12943#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM4 0x36e1 12944#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM4_BASE_IDX 2 12945#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM5 0x36e2 12946#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM5_BASE_IDX 2 12947#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM6 0x36e3 12948#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM6_BASE_IDX 2 12949#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM7 0x36e4 12950#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM7_BASE_IDX 2 12951#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM8 0x36e5 12952#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM8_BASE_IDX 2 12953#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM9 0x36e6 12954#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM9_BASE_IDX 2 12955#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM10 0x36e7 12956#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM10_BASE_IDX 2 12957#define regDP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS 0x36e8 12958#define regDP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS_BASE_IDX 2 12959#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE 0x36ea 12960#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE_BASE_IDX 2 12961#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0 0x36eb 12962#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0_BASE_IDX 2 12963#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG1 0x36ec 12964#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG1_BASE_IDX 2 12965#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_STATUS 0x36ed 12966#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_STATUS_BASE_IDX 2 12967#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_COUNT 0x36ee 12968#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_COUNT_BASE_IDX 2 12969 12970 12971// addressBlock: dcn_dc_hpo_dp_link_enc1_dispdec 12972// base address: 0x1b0ac 12973#define regDP_LINK_ENC1_DP_LINK_ENC_CLOCK_CONTROL 0x376b 12974#define regDP_LINK_ENC1_DP_LINK_ENC_CLOCK_CONTROL_BASE_IDX 2 12975#define regDP_LINK_ENC1_DP_LINK_ENC_SPARE 0x376c 12976#define regDP_LINK_ENC1_DP_LINK_ENC_SPARE_BASE_IDX 2 12977 12978 12979// addressBlock: dcn_dc_hpo_dp_dphy_sym321_dispdec 12980// base address: 0x1b150 12981#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL 0x3794 12982#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL_BASE_IDX 2 12983#define regDP_DPHY_SYM321_DP_DPHY_SYM32_STATUS 0x3795 12984#define regDP_DPHY_SYM321_DP_DPHY_SYM32_STATUS_BASE_IDX 2 12985#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_UPDATE 0x3798 12986#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_UPDATE_BASE_IDX 2 12987#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL0 0x3799 12988#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL0_BASE_IDX 2 12989#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL1 0x379a 12990#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL1_BASE_IDX 2 12991#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL2 0x379b 12992#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL2_BASE_IDX 2 12993#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL3 0x379c 12994#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL3_BASE_IDX 2 12995#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC0 0x379f 12996#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC0_BASE_IDX 2 12997#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC1 0x37a0 12998#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC1_BASE_IDX 2 12999#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC2 0x37a1 13000#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC2_BASE_IDX 2 13001#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC3 0x37a2 13002#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC3_BASE_IDX 2 13003#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS0 0x37a5 13004#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS0_BASE_IDX 2 13005#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS1 0x37a6 13006#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS1_BASE_IDX 2 13007#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS2 0x37a7 13008#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS2_BASE_IDX 2 13009#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS3 0x37a8 13010#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS3_BASE_IDX 2 13011#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG 0x37ab 13012#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG_BASE_IDX 2 13013#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED0 0x37ac 13014#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED0_BASE_IDX 2 13015#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED1 0x37ad 13016#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED1_BASE_IDX 2 13017#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED2 0x37ae 13018#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED2_BASE_IDX 2 13019#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED3 0x37af 13020#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED3_BASE_IDX 2 13021#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_SQ_PULSE 0x37b0 13022#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_SQ_PULSE_BASE_IDX 2 13023#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM0 0x37b1 13024#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM0_BASE_IDX 2 13025#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM1 0x37b2 13026#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM1_BASE_IDX 2 13027#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM2 0x37b3 13028#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM2_BASE_IDX 2 13029#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM3 0x37b4 13030#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM3_BASE_IDX 2 13031#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM4 0x37b5 13032#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM4_BASE_IDX 2 13033#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM5 0x37b6 13034#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM5_BASE_IDX 2 13035#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM6 0x37b7 13036#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM6_BASE_IDX 2 13037#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM7 0x37b8 13038#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM7_BASE_IDX 2 13039#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM8 0x37b9 13040#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM8_BASE_IDX 2 13041#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM9 0x37ba 13042#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM9_BASE_IDX 2 13043#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM10 0x37bb 13044#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM10_BASE_IDX 2 13045#define regDP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS 0x37bc 13046#define regDP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS_BASE_IDX 2 13047#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE 0x37be 13048#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE_BASE_IDX 2 13049#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0 0x37bf 13050#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0_BASE_IDX 2 13051#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG1 0x37c0 13052#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG1_BASE_IDX 2 13053#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_STATUS 0x37c1 13054#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_STATUS_BASE_IDX 2 13055#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_COUNT 0x37c2 13056#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_COUNT_BASE_IDX 2 13057 13058 13059// addressBlock: dcn_dpcssys_dpcs0_rdpcspipe0_dispdec 13060// base address: 0x0 13061#define regRDPCSPIPE0_RDPCSPIPE_PHY_CNTL6 0x293b 13062#define regRDPCSPIPE0_RDPCSPIPE_PHY_CNTL6_BASE_IDX 2 13063 13064 13065// addressBlock: dcn_dpcssys_dpcs0_rdpcspipe1_dispdec 13066// base address: 0x360 13067#define regRDPCSPIPE1_RDPCSPIPE_PHY_CNTL6 0x2a13 13068#define regRDPCSPIPE1_RDPCSPIPE_PHY_CNTL6_BASE_IDX 2 13069 13070 13071// addressBlock: dcn_dpcssys_dpcs0_rdpcspipe2_dispdec 13072// base address: 0x6c0 13073#define regRDPCSPIPE2_RDPCSPIPE_PHY_CNTL6 0x2aeb 13074#define regRDPCSPIPE2_RDPCSPIPE_PHY_CNTL6_BASE_IDX 2 13075 13076 13077// addressBlock: dcn_dpcssys_dpcs0_rdpcspipe3_dispdec 13078// base address: 0xa20 13079#define regRDPCSPIPE3_RDPCSPIPE_PHY_CNTL6 0x2bc3 13080#define regRDPCSPIPE3_RDPCSPIPE_PHY_CNTL6_BASE_IDX 2 13081 13082 13083// addressBlock: dcn_dpcssys_dpcs0_rdpcspipe4_dispdec 13084// base address: 0xd80 13085#define regRDPCSPIPE4_RDPCSPIPE_PHY_CNTL6 0x2c9b 13086#define regRDPCSPIPE4_RDPCSPIPE_PHY_CNTL6_BASE_IDX 2 13087 13088 13089// addressBlock: dcn_dc_hda_azcontroller_azdec 13090// base address: 0x0 13091#define regCORB_WRITE_POINTER 0x0000 13092#define regCORB_WRITE_POINTER_BASE_IDX 0 13093#define regCORB_READ_POINTER 0x0000 13094#define regCORB_READ_POINTER_BASE_IDX 0 13095#define regCORB_CONTROL 0x0001 13096#define regCORB_CONTROL_BASE_IDX 0 13097#define regCORB_STATUS 0x0001 13098#define regCORB_STATUS_BASE_IDX 0 13099#define regCORB_SIZE 0x0001 13100#define regCORB_SIZE_BASE_IDX 0 13101#define regRIRB_LOWER_BASE_ADDRESS 0x0002 13102#define regRIRB_LOWER_BASE_ADDRESS_BASE_IDX 0 13103#define regRIRB_UPPER_BASE_ADDRESS 0x0003 13104#define regRIRB_UPPER_BASE_ADDRESS_BASE_IDX 0 13105#define regRIRB_WRITE_POINTER 0x0004 13106#define regRIRB_WRITE_POINTER_BASE_IDX 0 13107#define regRESPONSE_INTERRUPT_COUNT 0x0004 13108#define regRESPONSE_INTERRUPT_COUNT_BASE_IDX 0 13109#define regRIRB_CONTROL 0x0005 13110#define regRIRB_CONTROL_BASE_IDX 0 13111#define regRIRB_STATUS 0x0005 13112#define regRIRB_STATUS_BASE_IDX 0 13113#define regRIRB_SIZE 0x0005 13114#define regRIRB_SIZE_BASE_IDX 0 13115#define regIMMEDIATE_COMMAND_OUTPUT_INTERFACE 0x0006 13116#define regIMMEDIATE_COMMAND_OUTPUT_INTERFACE_BASE_IDX 0 13117#define regIMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x0006 13118#define regIMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX 0 13119#define regIMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x0006 13120#define regIMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX 0 13121#define regIMMEDIATE_RESPONSE_INPUT_INTERFACE 0x0007 13122#define regIMMEDIATE_RESPONSE_INPUT_INTERFACE_BASE_IDX 0 13123#define regIMMEDIATE_COMMAND_STATUS 0x0008 13124#define regIMMEDIATE_COMMAND_STATUS_BASE_IDX 0 13125#define regDMA_POSITION_LOWER_BASE_ADDRESS 0x000a 13126#define regDMA_POSITION_LOWER_BASE_ADDRESS_BASE_IDX 0 13127#define regDMA_POSITION_UPPER_BASE_ADDRESS 0x000b 13128#define regDMA_POSITION_UPPER_BASE_ADDRESS_BASE_IDX 0 13129#define regWALL_CLOCK_COUNTER_ALIAS 0x074c 13130#define regWALL_CLOCK_COUNTER_ALIAS_BASE_IDX 1 13131 13132 13133// addressBlock: dcn_dc_hda_azendpoint_azdec 13134// base address: 0x0 13135#define regAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x0006 13136#define regAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX 0 13137#define regAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x0006 13138#define regAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX 0 13139 13140 13141// addressBlock: dcn_dc_hda_azinputendpoint_azdec 13142// base address: 0x0 13143#define regAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA 0x0006 13144#define regAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA_BASE_IDX 0 13145#define regAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX 0x0006 13146#define regAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX_BASE_IDX 0 13147 13148 13149// addressBlock: dcn_dc_hda_azroot_azdec 13150// base address: 0x0 13151#define regAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x0006 13152#define regAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX 0 13153#define regAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x0006 13154#define regAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX 0 13155 13156 13157// addressBlock: dcn_dc_hda_azstream0_azdec 13158// base address: 0x0 13159#define regAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x000e 13160#define regAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0 13161#define regAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x000f 13162#define regAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0 13163#define regAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0010 13164#define regAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0 13165#define regAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0011 13166#define regAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0 13167#define regAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x0012 13168#define regAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0 13169#define regAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x0012 13170#define regAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0 13171#define regAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x0014 13172#define regAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0 13173#define regAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x0015 13174#define regAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0 13175#define regAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0761 13176#define regAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1 13177 13178 13179// addressBlock: dcn_dc_hda_azstream1_azdec 13180// base address: 0x20 13181#define regAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x0016 13182#define regAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0 13183#define regAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x0017 13184#define regAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0 13185#define regAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0018 13186#define regAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0 13187#define regAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0019 13188#define regAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0 13189#define regAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x001a 13190#define regAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0 13191#define regAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x001a 13192#define regAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0 13193#define regAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x001c 13194#define regAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0 13195#define regAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x001d 13196#define regAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0 13197#define regAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0769 13198#define regAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1 13199 13200 13201// addressBlock: dcn_dc_hda_azstream2_azdec 13202// base address: 0x40 13203#define regAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x001e 13204#define regAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0 13205#define regAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x001f 13206#define regAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0 13207#define regAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0020 13208#define regAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0 13209#define regAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0021 13210#define regAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0 13211#define regAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x0022 13212#define regAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0 13213#define regAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x0022 13214#define regAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0 13215#define regAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x0024 13216#define regAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0 13217#define regAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x0025 13218#define regAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0 13219#define regAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0771 13220#define regAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1 13221 13222 13223// addressBlock: dcn_dc_hda_azstream3_azdec 13224// base address: 0x60 13225#define regAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x0026 13226#define regAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0 13227#define regAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x0027 13228#define regAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0 13229#define regAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0028 13230#define regAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0 13231#define regAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0029 13232#define regAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0 13233#define regAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x002a 13234#define regAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0 13235#define regAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x002a 13236#define regAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0 13237#define regAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x002c 13238#define regAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0 13239#define regAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x002d 13240#define regAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0 13241#define regAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0779 13242#define regAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1 13243 13244 13245// addressBlock: dcn_dc_hda_azstream4_azdec 13246// base address: 0x80 13247#define regAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x002e 13248#define regAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0 13249#define regAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x002f 13250#define regAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0 13251#define regAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0030 13252#define regAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0 13253#define regAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0031 13254#define regAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0 13255#define regAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x0032 13256#define regAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0 13257#define regAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x0032 13258#define regAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0 13259#define regAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x0034 13260#define regAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0 13261#define regAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x0035 13262#define regAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0 13263#define regAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0781 13264#define regAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1 13265 13266 13267// addressBlock: dcn_dc_hda_azstream5_azdec 13268// base address: 0xa0 13269#define regAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x0036 13270#define regAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0 13271#define regAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x0037 13272#define regAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0 13273#define regAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0038 13274#define regAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0 13275#define regAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0039 13276#define regAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0 13277#define regAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x003a 13278#define regAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0 13279#define regAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x003a 13280#define regAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0 13281#define regAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x003c 13282#define regAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0 13283#define regAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x003d 13284#define regAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0 13285#define regAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0789 13286#define regAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1 13287 13288 13289// addressBlock: dcn_dc_hda_azstream6_azdec 13290// base address: 0xc0 13291#define regAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x003e 13292#define regAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0 13293#define regAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x003f 13294#define regAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0 13295#define regAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0040 13296#define regAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0 13297#define regAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0041 13298#define regAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0 13299#define regAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x0042 13300#define regAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0 13301#define regAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x0042 13302#define regAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0 13303#define regAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x0044 13304#define regAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0 13305#define regAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x0045 13306#define regAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0 13307#define regAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0791 13308#define regAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1 13309 13310 13311// addressBlock: dcn_dc_hda_azstream7_azdec 13312// base address: 0xe0 13313#define regAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x0046 13314#define regAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0 13315#define regAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x0047 13316#define regAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0 13317#define regAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0048 13318#define regAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0 13319#define regAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0049 13320#define regAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0 13321#define regAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x004a 13322#define regAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0 13323#define regAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x004a 13324#define regAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0 13325#define regAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x004c 13326#define regAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0 13327#define regAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x004d 13328#define regAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0 13329#define regAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0799 13330#define regAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1 13331 13332 13333// addressBlock: vga_vgaseqind 13334// base address: 0x0 13335#define ixSEQ00 0x0000 13336#define ixSEQ01 0x0001 13337#define ixSEQ02 0x0002 13338#define ixSEQ03 0x0003 13339#define ixSEQ04 0x0004 13340 13341 13342// addressBlock: vga_vgacrtind 13343// base address: 0x0 13344#define ixCRT00 0x0000 13345#define ixCRT01 0x0001 13346#define ixCRT02 0x0002 13347#define ixCRT03 0x0003 13348#define ixCRT04 0x0004 13349#define ixCRT05 0x0005 13350#define ixCRT06 0x0006 13351#define ixCRT07 0x0007 13352#define ixCRT08 0x0008 13353#define ixCRT09 0x0009 13354#define ixCRT0A 0x000a 13355#define ixCRT0B 0x000b 13356#define ixCRT0C 0x000c 13357#define ixCRT0D 0x000d 13358#define ixCRT0E 0x000e 13359#define ixCRT0F 0x000f 13360#define ixCRT10 0x0010 13361#define ixCRT11 0x0011 13362#define ixCRT12 0x0012 13363#define ixCRT13 0x0013 13364#define ixCRT14 0x0014 13365#define ixCRT15 0x0015 13366#define ixCRT16 0x0016 13367#define ixCRT17 0x0017 13368#define ixCRT18 0x0018 13369#define ixCRT1E 0x001e 13370#define ixCRT1F 0x001f 13371#define ixCRT22 0x0022 13372 13373 13374// addressBlock: vga_vgagrphind 13375// base address: 0x0 13376#define ixGRA00 0x0000 13377#define ixGRA01 0x0001 13378#define ixGRA02 0x0002 13379#define ixGRA03 0x0003 13380#define ixGRA04 0x0004 13381#define ixGRA05 0x0005 13382#define ixGRA06 0x0006 13383#define ixGRA07 0x0007 13384#define ixGRA08 0x0008 13385 13386 13387// addressBlock: vga_vgaattrind 13388// base address: 0x0 13389#define ixATTR00 0x0000 13390#define ixATTR01 0x0001 13391#define ixATTR02 0x0002 13392#define ixATTR03 0x0003 13393#define ixATTR04 0x0004 13394#define ixATTR05 0x0005 13395#define ixATTR06 0x0006 13396#define ixATTR07 0x0007 13397#define ixATTR08 0x0008 13398#define ixATTR09 0x0009 13399#define ixATTR0A 0x000a 13400#define ixATTR0B 0x000b 13401#define ixATTR0C 0x000c 13402#define ixATTR0D 0x000d 13403#define ixATTR0E 0x000e 13404#define ixATTR0F 0x000f 13405#define ixATTR10 0x0010 13406#define ixATTR11 0x0011 13407#define ixATTR12 0x0012 13408#define ixATTR13 0x0013 13409#define ixATTR14 0x0014 13410 13411 13412// addressBlock: azendpoint_f2codecind 13413// base address: 0x0 13414#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x2200 13415#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x2706 13416#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x270d 13417#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2 0x270e 13418#define ixAZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL 0x2724 13419#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3 0x273e 13420#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x2770 13421#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x2771 13422#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x2f09 13423#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x2f0a 13424#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x2f0b 13425#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY 0x3702 13426#define ixAZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x3707 13427#define ixAZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x3708 13428#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x3709 13429#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x371c 13430#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2 0x371d 13431#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3 0x371e 13432#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4 0x371f 13433#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION 0x3770 13434#define ixAZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION 0x3771 13435#define ixAZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO 0x3772 13436#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR 0x3776 13437#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA 0x3776 13438#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE 0x3777 13439#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE 0x3778 13440#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE 0x3779 13441#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE 0x377a 13442#define ixAZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC 0x377b 13443#define ixAZALIA_F2_CODEC_PIN_CONTROL_HBR 0x377c 13444#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX 0x3780 13445#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA 0x3781 13446#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE 0x3785 13447#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE 0x3786 13448#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE 0x3787 13449#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE 0x3788 13450#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x3789 13451#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x378a 13452#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x378b 13453#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x378c 13454#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x378d 13455#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x378e 13456#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x378f 13457#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x3790 13458#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x3791 13459#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x3792 13460#define ixAZALIA_F2_CODEC_PIN_ASSOCIATION_INFO 0x3793 13461#define ixAZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x3797 13462#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x3798 13463#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB 0x3799 13464#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x379a 13465#define ixAZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE 0x379b 13466#define ixAZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x379c 13467#define ixAZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x379d 13468#define ixAZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x379e 13469#define ixAZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x3f09 13470#define ixAZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES 0x3f0c 13471#define ixAZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH 0x3f0e 13472 13473 13474// addressBlock: azendpoint_descriptorind 13475// base address: 0x0 13476#define ixAUDIO_DESCRIPTOR0 0x0001 13477#define ixAUDIO_DESCRIPTOR1 0x0002 13478#define ixAUDIO_DESCRIPTOR2 0x0003 13479#define ixAUDIO_DESCRIPTOR3 0x0004 13480#define ixAUDIO_DESCRIPTOR4 0x0005 13481#define ixAUDIO_DESCRIPTOR5 0x0006 13482#define ixAUDIO_DESCRIPTOR6 0x0007 13483#define ixAUDIO_DESCRIPTOR7 0x0008 13484#define ixAUDIO_DESCRIPTOR8 0x0009 13485#define ixAUDIO_DESCRIPTOR9 0x000a 13486#define ixAUDIO_DESCRIPTOR10 0x000b 13487#define ixAUDIO_DESCRIPTOR11 0x000c 13488#define ixAUDIO_DESCRIPTOR12 0x000d 13489#define ixAUDIO_DESCRIPTOR13 0x000e 13490 13491 13492// addressBlock: azendpoint_sinkinfoind 13493// base address: 0x0 13494#define ixAZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID 0x0000 13495#define ixAZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID 0x0001 13496#define ixAZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN 0x0002 13497#define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID0 0x0003 13498#define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID1 0x0004 13499#define ixSINK_DESCRIPTION0 0x0005 13500#define ixSINK_DESCRIPTION1 0x0006 13501#define ixSINK_DESCRIPTION2 0x0007 13502#define ixSINK_DESCRIPTION3 0x0008 13503#define ixSINK_DESCRIPTION4 0x0009 13504#define ixSINK_DESCRIPTION5 0x000a 13505#define ixSINK_DESCRIPTION6 0x000b 13506#define ixSINK_DESCRIPTION7 0x000c 13507#define ixSINK_DESCRIPTION8 0x000d 13508#define ixSINK_DESCRIPTION9 0x000e 13509#define ixSINK_DESCRIPTION10 0x000f 13510#define ixSINK_DESCRIPTION11 0x0010 13511#define ixSINK_DESCRIPTION12 0x0011 13512#define ixSINK_DESCRIPTION13 0x0012 13513#define ixSINK_DESCRIPTION14 0x0013 13514#define ixSINK_DESCRIPTION15 0x0014 13515#define ixSINK_DESCRIPTION16 0x0015 13516#define ixSINK_DESCRIPTION17 0x0016 13517 13518 13519// addressBlock: azf0controller_azinputcrc0resultind 13520// base address: 0x0 13521#define ixAZALIA_INPUT_CRC0_CHANNEL0 0x0000 13522#define ixAZALIA_INPUT_CRC0_CHANNEL1 0x0001 13523#define ixAZALIA_INPUT_CRC0_CHANNEL2 0x0002 13524#define ixAZALIA_INPUT_CRC0_CHANNEL3 0x0003 13525#define ixAZALIA_INPUT_CRC0_CHANNEL4 0x0004 13526#define ixAZALIA_INPUT_CRC0_CHANNEL5 0x0005 13527#define ixAZALIA_INPUT_CRC0_CHANNEL6 0x0006 13528#define ixAZALIA_INPUT_CRC0_CHANNEL7 0x0007 13529 13530 13531// addressBlock: azf0controller_azinputcrc1resultind 13532// base address: 0x0 13533#define ixAZALIA_INPUT_CRC1_CHANNEL0 0x0000 13534#define ixAZALIA_INPUT_CRC1_CHANNEL1 0x0001 13535#define ixAZALIA_INPUT_CRC1_CHANNEL2 0x0002 13536#define ixAZALIA_INPUT_CRC1_CHANNEL3 0x0003 13537#define ixAZALIA_INPUT_CRC1_CHANNEL4 0x0004 13538#define ixAZALIA_INPUT_CRC1_CHANNEL5 0x0005 13539#define ixAZALIA_INPUT_CRC1_CHANNEL6 0x0006 13540#define ixAZALIA_INPUT_CRC1_CHANNEL7 0x0007 13541 13542 13543// addressBlock: azf0controller_azcrc0resultind 13544// base address: 0x0 13545#define ixAZALIA_CRC0_CHANNEL0 0x0000 13546#define ixAZALIA_CRC0_CHANNEL1 0x0001 13547#define ixAZALIA_CRC0_CHANNEL2 0x0002 13548#define ixAZALIA_CRC0_CHANNEL3 0x0003 13549#define ixAZALIA_CRC0_CHANNEL4 0x0004 13550#define ixAZALIA_CRC0_CHANNEL5 0x0005 13551#define ixAZALIA_CRC0_CHANNEL6 0x0006 13552#define ixAZALIA_CRC0_CHANNEL7 0x0007 13553 13554 13555// addressBlock: azf0controller_azcrc1resultind 13556// base address: 0x0 13557#define ixAZALIA_CRC1_CHANNEL0 0x0000 13558#define ixAZALIA_CRC1_CHANNEL1 0x0001 13559#define ixAZALIA_CRC1_CHANNEL2 0x0002 13560#define ixAZALIA_CRC1_CHANNEL3 0x0003 13561#define ixAZALIA_CRC1_CHANNEL4 0x0004 13562#define ixAZALIA_CRC1_CHANNEL5 0x0005 13563#define ixAZALIA_CRC1_CHANNEL6 0x0006 13564#define ixAZALIA_CRC1_CHANNEL7 0x0007 13565 13566 13567// addressBlock: azinputendpoint_f2codecind 13568// base address: 0x0 13569#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x6200 13570#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x6706 13571#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x670d 13572#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x6f09 13573#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x6f0a 13574#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x6f0b 13575#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x7707 13576#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x7708 13577#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE 0x7709 13578#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x771c 13579#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2 0x771d 13580#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3 0x771e 13581#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4 0x771f 13582#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x7771 13583#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE 0x7777 13584#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE 0x7778 13585#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE 0x7779 13586#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE 0x777a 13587#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR 0x777c 13588#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE 0x7785 13589#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE 0x7786 13590#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE 0x7787 13591#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE 0x7788 13592#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x7798 13593#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB 0x7799 13594#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x779a 13595#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x779b 13596#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x779c 13597#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L 0x779d 13598#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H 0x779e 13599#define ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x7f09 13600#define ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x7f0c 13601 13602 13603// addressBlock: azroot_f2codecind 13604// base address: 0x0 13605#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID 0x0f00 13606#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID 0x0f02 13607#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT 0x0f04 13608#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE 0x1705 13609#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID 0x1720 13610#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2 0x1721 13611#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3 0x1722 13612#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4 0x1723 13613#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION 0x1770 13614#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESET 0x17ff 13615#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT 0x1f04 13616#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE 0x1f05 13617#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES 0x1f0a 13618#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS 0x1f0b 13619#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES 0x1f0f 13620 13621 13622// addressBlock: azf0stream0_streamind 13623// base address: 0x0 13624#define ixAZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL 0x0000 13625#define ixAZF0STREAM0_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 13626#define ixAZF0STREAM0_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 13627#define ixAZF0STREAM0_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 13628#define ixAZF0STREAM0_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 13629 13630 13631// addressBlock: azf0stream1_streamind 13632// base address: 0x0 13633#define ixAZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL 0x0000 13634#define ixAZF0STREAM1_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 13635#define ixAZF0STREAM1_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 13636#define ixAZF0STREAM1_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 13637#define ixAZF0STREAM1_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 13638 13639 13640// addressBlock: azf0stream2_streamind 13641// base address: 0x0 13642#define ixAZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL 0x0000 13643#define ixAZF0STREAM2_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 13644#define ixAZF0STREAM2_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 13645#define ixAZF0STREAM2_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 13646#define ixAZF0STREAM2_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 13647 13648 13649// addressBlock: azf0stream3_streamind 13650// base address: 0x0 13651#define ixAZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL 0x0000 13652#define ixAZF0STREAM3_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 13653#define ixAZF0STREAM3_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 13654#define ixAZF0STREAM3_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 13655#define ixAZF0STREAM3_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 13656 13657 13658// addressBlock: azf0stream4_streamind 13659// base address: 0x0 13660#define ixAZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL 0x0000 13661#define ixAZF0STREAM4_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 13662#define ixAZF0STREAM4_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 13663#define ixAZF0STREAM4_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 13664#define ixAZF0STREAM4_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 13665 13666 13667// addressBlock: azf0stream5_streamind 13668// base address: 0x0 13669#define ixAZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL 0x0000 13670#define ixAZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 13671#define ixAZF0STREAM5_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 13672#define ixAZF0STREAM5_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 13673#define ixAZF0STREAM5_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 13674 13675 13676// addressBlock: azf0stream6_streamind 13677// base address: 0x0 13678#define ixAZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL 0x0000 13679#define ixAZF0STREAM6_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 13680#define ixAZF0STREAM6_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 13681#define ixAZF0STREAM6_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 13682#define ixAZF0STREAM6_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 13683 13684 13685// addressBlock: azf0stream7_streamind 13686// base address: 0x0 13687#define ixAZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL 0x0000 13688#define ixAZF0STREAM7_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 13689#define ixAZF0STREAM7_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 13690#define ixAZF0STREAM7_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 13691#define ixAZF0STREAM7_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 13692 13693 13694// addressBlock: azf0stream8_streamind 13695// base address: 0x0 13696#define ixAZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL 0x0000 13697#define ixAZF0STREAM8_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 13698#define ixAZF0STREAM8_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 13699#define ixAZF0STREAM8_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 13700#define ixAZF0STREAM8_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 13701 13702 13703// addressBlock: azf0stream9_streamind 13704// base address: 0x0 13705#define ixAZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL 0x0000 13706#define ixAZF0STREAM9_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 13707#define ixAZF0STREAM9_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 13708#define ixAZF0STREAM9_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 13709#define ixAZF0STREAM9_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 13710 13711 13712// addressBlock: azf0stream10_streamind 13713// base address: 0x0 13714#define ixAZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL 0x0000 13715#define ixAZF0STREAM10_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 13716#define ixAZF0STREAM10_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 13717#define ixAZF0STREAM10_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 13718#define ixAZF0STREAM10_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 13719 13720 13721// addressBlock: azf0stream11_streamind 13722// base address: 0x0 13723#define ixAZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL 0x0000 13724#define ixAZF0STREAM11_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 13725#define ixAZF0STREAM11_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 13726#define ixAZF0STREAM11_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 13727#define ixAZF0STREAM11_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 13728 13729 13730// addressBlock: azf0stream12_streamind 13731// base address: 0x0 13732#define ixAZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL 0x0000 13733#define ixAZF0STREAM12_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 13734#define ixAZF0STREAM12_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 13735#define ixAZF0STREAM12_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 13736#define ixAZF0STREAM12_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 13737 13738 13739// addressBlock: azf0stream13_streamind 13740// base address: 0x0 13741#define ixAZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL 0x0000 13742#define ixAZF0STREAM13_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 13743#define ixAZF0STREAM13_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 13744#define ixAZF0STREAM13_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 13745#define ixAZF0STREAM13_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 13746 13747 13748// addressBlock: azf0stream14_streamind 13749// base address: 0x0 13750#define ixAZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL 0x0000 13751#define ixAZF0STREAM14_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 13752#define ixAZF0STREAM14_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 13753#define ixAZF0STREAM14_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 13754#define ixAZF0STREAM14_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 13755 13756 13757// addressBlock: azf0stream15_streamind 13758// base address: 0x0 13759#define ixAZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL 0x0000 13760#define ixAZF0STREAM15_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 13761#define ixAZF0STREAM15_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 13762#define ixAZF0STREAM15_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 13763#define ixAZF0STREAM15_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 13764 13765 13766// addressBlock: azf0endpoint0_endpointind 13767// base address: 0x0 13768#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 13769#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 13770#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 13771#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 13772#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 13773#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 13774#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 13775#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 13776#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 13777#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c 13778#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d 13779#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e 13780#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 13781#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 13782#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 13783#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 13784#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 13785#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 13786#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 13787#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 13788#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a 13789#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b 13790#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c 13791#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d 13792#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e 13793#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f 13794#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 13795#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 13796#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 13797#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 13798#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 13799#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 13800#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 13801#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 13802#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 13803#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a 13804#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b 13805#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c 13806#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d 13807#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e 13808#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f 13809#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 13810#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 13811#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 13812#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 13813#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 13814#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 13815#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 13816#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 13817#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 13818#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a 13819#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b 13820#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c 13821#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d 13822#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e 13823#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f 13824#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 13825#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 13826#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 13827#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 13828#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 13829#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 13830#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 13831#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 13832#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 13833#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 13834#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a 13835#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b 13836#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c 13837#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d 13838#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e 13839 13840 13841// addressBlock: azf0endpoint1_endpointind 13842// base address: 0x0 13843#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 13844#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 13845#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 13846#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 13847#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 13848#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 13849#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 13850#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 13851#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 13852#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c 13853#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d 13854#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e 13855#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 13856#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 13857#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 13858#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 13859#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 13860#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 13861#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 13862#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 13863#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a 13864#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b 13865#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c 13866#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d 13867#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e 13868#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f 13869#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 13870#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 13871#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 13872#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 13873#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 13874#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 13875#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 13876#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 13877#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 13878#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a 13879#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b 13880#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c 13881#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d 13882#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e 13883#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f 13884#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 13885#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 13886#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 13887#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 13888#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 13889#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 13890#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 13891#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 13892#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 13893#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a 13894#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b 13895#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c 13896#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d 13897#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e 13898#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f 13899#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 13900#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 13901#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 13902#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 13903#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 13904#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 13905#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 13906#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 13907#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 13908#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 13909#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a 13910#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b 13911#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c 13912#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d 13913#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e 13914 13915 13916// addressBlock: azf0endpoint2_endpointind 13917// base address: 0x0 13918#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 13919#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 13920#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 13921#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 13922#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 13923#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 13924#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 13925#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 13926#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 13927#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c 13928#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d 13929#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e 13930#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 13931#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 13932#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 13933#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 13934#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 13935#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 13936#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 13937#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 13938#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a 13939#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b 13940#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c 13941#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d 13942#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e 13943#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f 13944#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 13945#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 13946#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 13947#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 13948#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 13949#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 13950#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 13951#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 13952#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 13953#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a 13954#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b 13955#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c 13956#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d 13957#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e 13958#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f 13959#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 13960#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 13961#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 13962#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 13963#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 13964#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 13965#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 13966#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 13967#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 13968#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a 13969#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b 13970#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c 13971#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d 13972#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e 13973#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f 13974#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 13975#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 13976#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 13977#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 13978#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 13979#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 13980#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 13981#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 13982#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 13983#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 13984#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a 13985#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b 13986#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c 13987#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d 13988#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e 13989 13990 13991// addressBlock: azf0endpoint3_endpointind 13992// base address: 0x0 13993#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 13994#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 13995#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 13996#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 13997#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 13998#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 13999#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 14000#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 14001#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 14002#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c 14003#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d 14004#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e 14005#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 14006#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 14007#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 14008#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 14009#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 14010#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 14011#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 14012#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 14013#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a 14014#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b 14015#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c 14016#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d 14017#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e 14018#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f 14019#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 14020#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 14021#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 14022#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 14023#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 14024#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 14025#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 14026#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 14027#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 14028#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a 14029#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b 14030#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c 14031#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d 14032#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e 14033#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f 14034#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 14035#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 14036#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 14037#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 14038#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 14039#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 14040#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 14041#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 14042#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 14043#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a 14044#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b 14045#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c 14046#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d 14047#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e 14048#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f 14049#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 14050#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 14051#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 14052#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 14053#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 14054#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 14055#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 14056#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 14057#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 14058#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 14059#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a 14060#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b 14061#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c 14062#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d 14063#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e 14064 14065 14066// addressBlock: azf0endpoint4_endpointind 14067// base address: 0x0 14068#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 14069#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 14070#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 14071#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 14072#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 14073#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 14074#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 14075#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 14076#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 14077#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c 14078#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d 14079#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e 14080#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 14081#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 14082#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 14083#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 14084#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 14085#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 14086#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 14087#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 14088#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a 14089#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b 14090#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c 14091#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d 14092#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e 14093#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f 14094#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 14095#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 14096#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 14097#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 14098#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 14099#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 14100#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 14101#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 14102#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 14103#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a 14104#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b 14105#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c 14106#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d 14107#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e 14108#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f 14109#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 14110#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 14111#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 14112#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 14113#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 14114#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 14115#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 14116#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 14117#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 14118#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a 14119#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b 14120#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c 14121#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d 14122#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e 14123#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f 14124#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 14125#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 14126#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 14127#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 14128#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 14129#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 14130#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 14131#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 14132#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 14133#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 14134#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a 14135#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b 14136#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c 14137#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d 14138#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e 14139 14140 14141// addressBlock: azf0endpoint5_endpointind 14142// base address: 0x0 14143#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 14144#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 14145#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 14146#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 14147#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 14148#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 14149#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 14150#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 14151#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 14152#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c 14153#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d 14154#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e 14155#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 14156#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 14157#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 14158#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 14159#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 14160#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 14161#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 14162#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 14163#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a 14164#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b 14165#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c 14166#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d 14167#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e 14168#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f 14169#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 14170#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 14171#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 14172#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 14173#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 14174#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 14175#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 14176#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 14177#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 14178#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a 14179#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b 14180#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c 14181#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d 14182#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e 14183#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f 14184#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 14185#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 14186#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 14187#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 14188#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 14189#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 14190#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 14191#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 14192#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 14193#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a 14194#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b 14195#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c 14196#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d 14197#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e 14198#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f 14199#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 14200#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 14201#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 14202#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 14203#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 14204#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 14205#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 14206#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 14207#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 14208#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 14209#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a 14210#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b 14211#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c 14212#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d 14213#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e 14214 14215 14216// addressBlock: azf0endpoint6_endpointind 14217// base address: 0x0 14218#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 14219#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 14220#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 14221#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 14222#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 14223#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 14224#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 14225#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 14226#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 14227#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c 14228#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d 14229#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e 14230#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 14231#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 14232#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 14233#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 14234#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 14235#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 14236#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 14237#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 14238#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a 14239#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b 14240#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c 14241#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d 14242#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e 14243#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f 14244#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 14245#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 14246#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 14247#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 14248#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 14249#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 14250#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 14251#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 14252#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 14253#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a 14254#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b 14255#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c 14256#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d 14257#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e 14258#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f 14259#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 14260#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 14261#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 14262#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 14263#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 14264#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 14265#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 14266#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 14267#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 14268#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a 14269#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b 14270#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c 14271#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d 14272#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e 14273#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f 14274#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 14275#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 14276#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 14277#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 14278#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 14279#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 14280#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 14281#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 14282#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 14283#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 14284#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a 14285#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b 14286#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c 14287#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d 14288#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e 14289 14290 14291// addressBlock: azf0endpoint7_endpointind 14292// base address: 0x0 14293#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 14294#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 14295#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 14296#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 14297#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 14298#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 14299#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 14300#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 14301#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 14302#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c 14303#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d 14304#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e 14305#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 14306#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 14307#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 14308#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 14309#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 14310#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 14311#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 14312#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 14313#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a 14314#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b 14315#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c 14316#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d 14317#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e 14318#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f 14319#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 14320#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 14321#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 14322#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 14323#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 14324#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 14325#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 14326#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 14327#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 14328#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a 14329#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b 14330#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c 14331#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d 14332#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e 14333#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f 14334#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 14335#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 14336#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 14337#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 14338#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 14339#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 14340#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 14341#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 14342#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 14343#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a 14344#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b 14345#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c 14346#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d 14347#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e 14348#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f 14349#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 14350#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 14351#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 14352#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 14353#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 14354#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 14355#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 14356#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 14357#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 14358#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 14359#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a 14360#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b 14361#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c 14362#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d 14363#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e 14364 14365 14366// addressBlock: azf0inputendpoint0_inputendpointind 14367// base address: 0x0 14368#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 14369#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 14370#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 14371#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 14372#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 14373#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 14374#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 14375#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 14376#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 14377#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 14378#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 14379#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 14380#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 14381#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 14382#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 14383#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 14384#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 14385#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 14386#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 14387#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 14388#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 14389#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 14390#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 14391 14392 14393// addressBlock: azf0inputendpoint1_inputendpointind 14394// base address: 0x0 14395#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 14396#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 14397#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 14398#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 14399#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 14400#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 14401#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 14402#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 14403#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 14404#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 14405#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 14406#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 14407#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 14408#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 14409#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 14410#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 14411#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 14412#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 14413#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 14414#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 14415#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 14416#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 14417#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 14418 14419 14420// addressBlock: azf0inputendpoint2_inputendpointind 14421// base address: 0x0 14422#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 14423#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 14424#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 14425#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 14426#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 14427#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 14428#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 14429#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 14430#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 14431#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 14432#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 14433#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 14434#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 14435#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 14436#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 14437#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 14438#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 14439#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 14440#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 14441#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 14442#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 14443#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 14444#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 14445 14446 14447// addressBlock: azf0inputendpoint3_inputendpointind 14448// base address: 0x0 14449#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 14450#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 14451#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 14452#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 14453#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 14454#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 14455#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 14456#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 14457#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 14458#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 14459#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 14460#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 14461#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 14462#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 14463#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 14464#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 14465#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 14466#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 14467#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 14468#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 14469#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 14470#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 14471#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 14472 14473 14474// addressBlock: azf0inputendpoint4_inputendpointind 14475// base address: 0x0 14476#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 14477#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 14478#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 14479#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 14480#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 14481#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 14482#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 14483#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 14484#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 14485#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 14486#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 14487#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 14488#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 14489#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 14490#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 14491#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 14492#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 14493#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 14494#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 14495#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 14496#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 14497#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 14498#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 14499 14500 14501// addressBlock: azf0inputendpoint5_inputendpointind 14502// base address: 0x0 14503#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 14504#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 14505#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 14506#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 14507#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 14508#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 14509#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 14510#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 14511#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 14512#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 14513#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 14514#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 14515#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 14516#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 14517#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 14518#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 14519#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 14520#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 14521#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 14522#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 14523#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 14524#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 14525#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 14526 14527 14528// addressBlock: azf0inputendpoint6_inputendpointind 14529// base address: 0x0 14530#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 14531#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 14532#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 14533#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 14534#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 14535#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 14536#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 14537#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 14538#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 14539#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 14540#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 14541#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 14542#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 14543#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 14544#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 14545#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 14546#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 14547#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 14548#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 14549#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 14550#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 14551#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 14552#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 14553 14554 14555// addressBlock: azf0inputendpoint7_inputendpointind 14556// base address: 0x0 14557#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 14558#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 14559#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 14560#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 14561#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 14562#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 14563#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 14564#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 14565#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 14566#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 14567#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 14568#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 14569#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 14570#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 14571#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 14572#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 14573#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 14574#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 14575#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 14576#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 14577#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 14578#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 14579#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 14580 14581 14582// addressBlock: c20_phy_cr0_rdpcspipecrind 14583// base address: 0x0 14584#define ixC20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_VGA_STATUS 0x10cc 14585#define ixC20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_VGA_STATUS 0x12cc 14586#define ixC20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_VGA_STATUS 0x14cc 14587#define ixC20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_VGA_STATUS 0x16cc 14588#define ixC20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK 0x2021 14589#define ixC20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK 0x20c0 14590#define ixC20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK 0x2221 14591#define ixC20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK 0x22c0 14592#define ixC20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK 0x2421 14593#define ixC20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK 0x24c0 14594#define ixC20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK 0x2621 14595#define ixC20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK 0x26c0 14596#define ixC20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_VGA_STATUS 0x50cc 14597#define ixC20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK 0x6021 14598#define ixC20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK 0x60c0 14599 14600 14601// addressBlock: c20_phy_cr1_rdpcspipecrind 14602// base address: 0x0 14603#define ixC20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_VGA_STATUS 0x10cc 14604#define ixC20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_VGA_STATUS 0x12cc 14605#define ixC20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_VGA_STATUS 0x14cc 14606#define ixC20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_VGA_STATUS 0x16cc 14607#define ixC20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK 0x2021 14608#define ixC20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK 0x20c0 14609#define ixC20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK 0x2221 14610#define ixC20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK 0x22c0 14611#define ixC20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK 0x2421 14612#define ixC20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK 0x24c0 14613#define ixC20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK 0x2621 14614#define ixC20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK 0x26c0 14615#define ixC20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_VGA_STATUS 0x50cc 14616#define ixC20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK 0x6021 14617#define ixC20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK 0x60c0 14618 14619 14620// addressBlock: c20_phy_cr2_rdpcspipecrind 14621// base address: 0x0 14622#define ixC20_PHY_CR2_LANE0_DIG_RX_ADPTCTL_VGA_STATUS 0x10cc 14623#define ixC20_PHY_CR2_LANE1_DIG_RX_ADPTCTL_VGA_STATUS 0x12cc 14624#define ixC20_PHY_CR2_LANE2_DIG_RX_ADPTCTL_VGA_STATUS 0x14cc 14625#define ixC20_PHY_CR2_LANE3_DIG_RX_ADPTCTL_VGA_STATUS 0x16cc 14626#define ixC20_PHY_CR2_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK 0x2021 14627#define ixC20_PHY_CR2_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK 0x20c0 14628#define ixC20_PHY_CR2_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK 0x2221 14629#define ixC20_PHY_CR2_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK 0x22c0 14630#define ixC20_PHY_CR2_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK 0x2421 14631#define ixC20_PHY_CR2_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK 0x24c0 14632#define ixC20_PHY_CR2_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK 0x2621 14633#define ixC20_PHY_CR2_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK 0x26c0 14634#define ixC20_PHY_CR2_LANEX_DIG_RX_ADPTCTL_VGA_STATUS 0x50cc 14635#define ixC20_PHY_CR2_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK 0x6021 14636#define ixC20_PHY_CR2_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK 0x60c0 14637 14638 14639// addressBlock: c20_phy_cr3_rdpcspipecrind 14640// base address: 0x0 14641#define ixC20_PHY_CR3_LANE0_DIG_RX_ADPTCTL_VGA_STATUS 0x10cc 14642#define ixC20_PHY_CR3_LANE1_DIG_RX_ADPTCTL_VGA_STATUS 0x12cc 14643#define ixC20_PHY_CR3_LANE2_DIG_RX_ADPTCTL_VGA_STATUS 0x14cc 14644#define ixC20_PHY_CR3_LANE3_DIG_RX_ADPTCTL_VGA_STATUS 0x16cc 14645#define ixC20_PHY_CR3_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK 0x2021 14646#define ixC20_PHY_CR3_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK 0x20c0 14647#define ixC20_PHY_CR3_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK 0x2221 14648#define ixC20_PHY_CR3_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK 0x22c0 14649#define ixC20_PHY_CR3_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK 0x2421 14650#define ixC20_PHY_CR3_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK 0x24c0 14651#define ixC20_PHY_CR3_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK 0x2621 14652#define ixC20_PHY_CR3_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK 0x26c0 14653#define ixC20_PHY_CR3_LANEX_DIG_RX_ADPTCTL_VGA_STATUS 0x50cc 14654#define ixC20_PHY_CR3_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK 0x6021 14655#define ixC20_PHY_CR3_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK 0x60c0 14656 14657 14658// addressBlock: c20_phy_cr4_rdpcspipecrind 14659// base address: 0x0 14660#define ixC20_PHY_CR4_LANE0_DIG_RX_ADPTCTL_VGA_STATUS 0x10cc 14661#define ixC20_PHY_CR4_LANE1_DIG_RX_ADPTCTL_VGA_STATUS 0x12cc 14662#define ixC20_PHY_CR4_LANE2_DIG_RX_ADPTCTL_VGA_STATUS 0x14cc 14663#define ixC20_PHY_CR4_LANE3_DIG_RX_ADPTCTL_VGA_STATUS 0x16cc 14664#define ixC20_PHY_CR4_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK 0x2021 14665#define ixC20_PHY_CR4_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK 0x20c0 14666#define ixC20_PHY_CR4_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK 0x2221 14667#define ixC20_PHY_CR4_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK 0x22c0 14668#define ixC20_PHY_CR4_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK 0x2421 14669#define ixC20_PHY_CR4_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK 0x24c0 14670#define ixC20_PHY_CR4_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK 0x2621 14671#define ixC20_PHY_CR4_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK 0x26c0 14672#define ixC20_PHY_CR4_LANEX_DIG_RX_ADPTCTL_VGA_STATUS 0x50cc 14673#define ixC20_PHY_CR4_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK 0x6021 14674#define ixC20_PHY_CR4_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK 0x60c0 14675 14676 14677#endif 14678