1/* SPDX-License-Identifier: MIT */ 2/* Copyright 2024 Advanced Micro Devices, Inc. */ 3#ifndef _dcn_3_5_1_OFFSET_HEADER 4#define _dcn_3_5_1_OFFSET_HEADER 5 6// addressBlock: dce_dc_hda_azcontroller_azdec 7// base address: 0x1300000 8#define regGLOBAL_CAPABILITIES 0x4b7000 9#define regGLOBAL_CAPABILITIES_BASE_IDX 3 10#define regMINOR_VERSION 0x4b7000 11#define regMINOR_VERSION_BASE_IDX 3 12#define regMAJOR_VERSION 0x4b7000 13#define regMAJOR_VERSION_BASE_IDX 3 14#define regOUTPUT_PAYLOAD_CAPABILITY 0x4b7001 15#define regOUTPUT_PAYLOAD_CAPABILITY_BASE_IDX 3 16#define regINPUT_PAYLOAD_CAPABILITY 0x4b7001 17#define regINPUT_PAYLOAD_CAPABILITY_BASE_IDX 3 18#define regGLOBAL_CONTROL 0x4b7002 19#define regGLOBAL_CONTROL_BASE_IDX 3 20#define regWAKE_ENABLE 0x4b7003 21#define regWAKE_ENABLE_BASE_IDX 3 22#define regSTATE_CHANGE_STATUS 0x4b7003 23#define regSTATE_CHANGE_STATUS_BASE_IDX 3 24#define regGLOBAL_STATUS 0x4b7004 25#define regGLOBAL_STATUS_BASE_IDX 3 26#define regOUTPUT_STREAM_PAYLOAD_CAPABILITY 0x4b7006 27#define regOUTPUT_STREAM_PAYLOAD_CAPABILITY_BASE_IDX 3 28#define regINPUT_STREAM_PAYLOAD_CAPABILITY 0x4b7006 29#define regINPUT_STREAM_PAYLOAD_CAPABILITY_BASE_IDX 3 30#define regINTERRUPT_CONTROL 0x4b7008 31#define regINTERRUPT_CONTROL_BASE_IDX 3 32#define regINTERRUPT_STATUS 0x4b7009 33#define regINTERRUPT_STATUS_BASE_IDX 3 34#define regWALL_CLOCK_COUNTER 0x4b700c 35#define regWALL_CLOCK_COUNTER_BASE_IDX 3 36#define regSTREAM_SYNCHRONIZATION 0x4b700e 37#define regSTREAM_SYNCHRONIZATION_BASE_IDX 3 38#define regCORB_LOWER_BASE_ADDRESS 0x4b7010 39#define regCORB_LOWER_BASE_ADDRESS_BASE_IDX 3 40#define regCORB_UPPER_BASE_ADDRESS 0x4b7011 41#define regCORB_UPPER_BASE_ADDRESS_BASE_IDX 3 42#define regAZCONTROLLER0_CORB_WRITE_POINTER 0x4b7012 43#define regAZCONTROLLER0_CORB_WRITE_POINTER_BASE_IDX 3 44#define regAZCONTROLLER0_CORB_READ_POINTER 0x4b7012 45#define regAZCONTROLLER0_CORB_READ_POINTER_BASE_IDX 3 46#define regAZCONTROLLER0_CORB_CONTROL 0x4b7013 47#define regAZCONTROLLER0_CORB_CONTROL_BASE_IDX 3 48#define regAZCONTROLLER0_CORB_STATUS 0x4b7013 49#define regAZCONTROLLER0_CORB_STATUS_BASE_IDX 3 50#define regAZCONTROLLER0_CORB_SIZE 0x4b7013 51#define regAZCONTROLLER0_CORB_SIZE_BASE_IDX 3 52#define regAZCONTROLLER0_RIRB_LOWER_BASE_ADDRESS 0x4b7014 53#define regAZCONTROLLER0_RIRB_LOWER_BASE_ADDRESS_BASE_IDX 3 54#define regAZCONTROLLER0_RIRB_UPPER_BASE_ADDRESS 0x4b7015 55#define regAZCONTROLLER0_RIRB_UPPER_BASE_ADDRESS_BASE_IDX 3 56#define regAZCONTROLLER0_RIRB_WRITE_POINTER 0x4b7016 57#define regAZCONTROLLER0_RIRB_WRITE_POINTER_BASE_IDX 3 58#define regAZCONTROLLER0_RESPONSE_INTERRUPT_COUNT 0x4b7016 59#define regAZCONTROLLER0_RESPONSE_INTERRUPT_COUNT_BASE_IDX 3 60#define regAZCONTROLLER0_RIRB_CONTROL 0x4b7017 61#define regAZCONTROLLER0_RIRB_CONTROL_BASE_IDX 3 62#define regAZCONTROLLER0_RIRB_STATUS 0x4b7017 63#define regAZCONTROLLER0_RIRB_STATUS_BASE_IDX 3 64#define regAZCONTROLLER0_RIRB_SIZE 0x4b7017 65#define regAZCONTROLLER0_RIRB_SIZE_BASE_IDX 3 66#define regAZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE 0x4b7018 67#define regAZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_BASE_IDX 3 68#define regAZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x4b7018 69#define regAZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX 3 70#define regAZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x4b7018 71#define regAZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX 3 72#define regAZCONTROLLER0_IMMEDIATE_RESPONSE_INPUT_INTERFACE 0x4b7019 73#define regAZCONTROLLER0_IMMEDIATE_RESPONSE_INPUT_INTERFACE_BASE_IDX 3 74#define regAZCONTROLLER0_IMMEDIATE_COMMAND_STATUS 0x4b701a 75#define regAZCONTROLLER0_IMMEDIATE_COMMAND_STATUS_BASE_IDX 3 76#define regAZCONTROLLER0_DMA_POSITION_LOWER_BASE_ADDRESS 0x4b701c 77#define regAZCONTROLLER0_DMA_POSITION_LOWER_BASE_ADDRESS_BASE_IDX 3 78#define regAZCONTROLLER0_DMA_POSITION_UPPER_BASE_ADDRESS 0x4b701d 79#define regAZCONTROLLER0_DMA_POSITION_UPPER_BASE_ADDRESS_BASE_IDX 3 80#define regAZCONTROLLER0_WALL_CLOCK_COUNTER_ALIAS 0x4b780c 81#define regAZCONTROLLER0_WALL_CLOCK_COUNTER_ALIAS_BASE_IDX 3 82 83// addressBlock: azendpoint_sinkinfoind 84// base address: 0x0 85#define ixAZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID 0x0000 86#define ixAZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID 0x0001 87#define ixAZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN 0x0002 88#define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID0 0x0003 89#define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID1 0x0004 90#define ixSINK_DESCRIPTION0 0x0005 91#define ixSINK_DESCRIPTION1 0x0006 92#define ixSINK_DESCRIPTION2 0x0007 93#define ixSINK_DESCRIPTION3 0x0008 94#define ixSINK_DESCRIPTION4 0x0009 95#define ixSINK_DESCRIPTION5 0x000a 96#define ixSINK_DESCRIPTION6 0x000b 97#define ixSINK_DESCRIPTION7 0x000c 98#define ixSINK_DESCRIPTION8 0x000d 99#define ixSINK_DESCRIPTION9 0x000e 100#define ixSINK_DESCRIPTION10 0x000f 101#define ixSINK_DESCRIPTION11 0x0010 102#define ixSINK_DESCRIPTION12 0x0011 103#define ixSINK_DESCRIPTION13 0x0012 104#define ixSINK_DESCRIPTION14 0x0013 105#define ixSINK_DESCRIPTION15 0x0014 106#define ixSINK_DESCRIPTION16 0x0015 107#define ixSINK_DESCRIPTION17 0x0016 108 109 110// addressBlock: azf0controller_azinputcrc0resultind 111// base address: 0x0 112#define ixAZALIA_INPUT_CRC0_CHANNEL0 0x0000 113#define ixAZALIA_INPUT_CRC0_CHANNEL1 0x0001 114#define ixAZALIA_INPUT_CRC0_CHANNEL2 0x0002 115#define ixAZALIA_INPUT_CRC0_CHANNEL3 0x0003 116#define ixAZALIA_INPUT_CRC0_CHANNEL4 0x0004 117#define ixAZALIA_INPUT_CRC0_CHANNEL5 0x0005 118#define ixAZALIA_INPUT_CRC0_CHANNEL6 0x0006 119#define ixAZALIA_INPUT_CRC0_CHANNEL7 0x0007 120 121 122// addressBlock: azf0controller_azinputcrc1resultind 123// base address: 0x0 124#define ixAZALIA_INPUT_CRC1_CHANNEL0 0x0000 125#define ixAZALIA_INPUT_CRC1_CHANNEL1 0x0001 126#define ixAZALIA_INPUT_CRC1_CHANNEL2 0x0002 127#define ixAZALIA_INPUT_CRC1_CHANNEL3 0x0003 128#define ixAZALIA_INPUT_CRC1_CHANNEL4 0x0004 129#define ixAZALIA_INPUT_CRC1_CHANNEL5 0x0005 130#define ixAZALIA_INPUT_CRC1_CHANNEL6 0x0006 131#define ixAZALIA_INPUT_CRC1_CHANNEL7 0x0007 132 133 134// addressBlock: azf0controller_azcrc0resultind 135// base address: 0x0 136#define ixAZALIA_CRC0_CHANNEL0 0x0000 137#define ixAZALIA_CRC0_CHANNEL1 0x0001 138#define ixAZALIA_CRC0_CHANNEL2 0x0002 139#define ixAZALIA_CRC0_CHANNEL3 0x0003 140#define ixAZALIA_CRC0_CHANNEL4 0x0004 141#define ixAZALIA_CRC0_CHANNEL5 0x0005 142#define ixAZALIA_CRC0_CHANNEL6 0x0006 143#define ixAZALIA_CRC0_CHANNEL7 0x0007 144 145 146// addressBlock: azf0controller_azcrc1resultind 147// base address: 0x0 148#define ixAZALIA_CRC1_CHANNEL0 0x0000 149#define ixAZALIA_CRC1_CHANNEL1 0x0001 150#define ixAZALIA_CRC1_CHANNEL2 0x0002 151#define ixAZALIA_CRC1_CHANNEL3 0x0003 152#define ixAZALIA_CRC1_CHANNEL4 0x0004 153#define ixAZALIA_CRC1_CHANNEL5 0x0005 154#define ixAZALIA_CRC1_CHANNEL6 0x0006 155#define ixAZALIA_CRC1_CHANNEL7 0x0007 156 157 158// addressBlock: azf0stream0_streamind 159// base address: 0x0 160#define ixAZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL 0x0000 161#define ixAZF0STREAM0_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 162#define ixAZF0STREAM0_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 163#define ixAZF0STREAM0_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 164#define ixAZF0STREAM0_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 165 166 167// addressBlock: azf0stream1_streamind 168// base address: 0x0 169#define ixAZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL 0x0000 170#define ixAZF0STREAM1_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 171#define ixAZF0STREAM1_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 172#define ixAZF0STREAM1_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 173#define ixAZF0STREAM1_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 174 175 176// addressBlock: azf0stream2_streamind 177// base address: 0x0 178#define ixAZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL 0x0000 179#define ixAZF0STREAM2_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 180#define ixAZF0STREAM2_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 181#define ixAZF0STREAM2_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 182#define ixAZF0STREAM2_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 183 184 185// addressBlock: azf0stream3_streamind 186// base address: 0x0 187#define ixAZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL 0x0000 188#define ixAZF0STREAM3_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 189#define ixAZF0STREAM3_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 190#define ixAZF0STREAM3_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 191#define ixAZF0STREAM3_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 192 193 194// addressBlock: azf0stream4_streamind 195// base address: 0x0 196#define ixAZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL 0x0000 197#define ixAZF0STREAM4_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 198#define ixAZF0STREAM4_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 199#define ixAZF0STREAM4_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 200#define ixAZF0STREAM4_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 201 202 203// addressBlock: azf0stream5_streamind 204// base address: 0x0 205#define ixAZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL 0x0000 206#define ixAZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 207#define ixAZF0STREAM5_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 208#define ixAZF0STREAM5_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 209#define ixAZF0STREAM5_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 210 211 212// addressBlock: azf0stream6_streamind 213// base address: 0x0 214#define ixAZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL 0x0000 215#define ixAZF0STREAM6_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 216#define ixAZF0STREAM6_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 217#define ixAZF0STREAM6_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 218#define ixAZF0STREAM6_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 219 220 221// addressBlock: azf0stream7_streamind 222// base address: 0x0 223#define ixAZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL 0x0000 224#define ixAZF0STREAM7_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 225#define ixAZF0STREAM7_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 226#define ixAZF0STREAM7_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 227#define ixAZF0STREAM7_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 228 229 230// addressBlock: azf0stream8_streamind 231// base address: 0x0 232#define ixAZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL 0x0000 233#define ixAZF0STREAM8_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 234#define ixAZF0STREAM8_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 235#define ixAZF0STREAM8_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 236#define ixAZF0STREAM8_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 237 238 239// addressBlock: azf0stream9_streamind 240// base address: 0x0 241#define ixAZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL 0x0000 242#define ixAZF0STREAM9_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 243#define ixAZF0STREAM9_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 244#define ixAZF0STREAM9_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 245#define ixAZF0STREAM9_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 246 247 248// addressBlock: azf0stream10_streamind 249// base address: 0x0 250#define ixAZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL 0x0000 251#define ixAZF0STREAM10_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 252#define ixAZF0STREAM10_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 253#define ixAZF0STREAM10_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 254#define ixAZF0STREAM10_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 255 256 257// addressBlock: azf0stream11_streamind 258// base address: 0x0 259#define ixAZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL 0x0000 260#define ixAZF0STREAM11_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 261#define ixAZF0STREAM11_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 262#define ixAZF0STREAM11_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 263#define ixAZF0STREAM11_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 264 265 266// addressBlock: azf0stream12_streamind 267// base address: 0x0 268#define ixAZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL 0x0000 269#define ixAZF0STREAM12_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 270#define ixAZF0STREAM12_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 271#define ixAZF0STREAM12_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 272#define ixAZF0STREAM12_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 273 274 275// addressBlock: azf0stream13_streamind 276// base address: 0x0 277#define ixAZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL 0x0000 278#define ixAZF0STREAM13_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 279#define ixAZF0STREAM13_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 280#define ixAZF0STREAM13_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 281#define ixAZF0STREAM13_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 282 283 284// addressBlock: azf0stream14_streamind 285// base address: 0x0 286#define ixAZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL 0x0000 287#define ixAZF0STREAM14_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 288#define ixAZF0STREAM14_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 289#define ixAZF0STREAM14_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 290#define ixAZF0STREAM14_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 291 292 293// addressBlock: azf0stream15_streamind 294// base address: 0x0 295#define ixAZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL 0x0000 296#define ixAZF0STREAM15_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 297#define ixAZF0STREAM15_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 298#define ixAZF0STREAM15_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 299#define ixAZF0STREAM15_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 300 301 302// addressBlock: azf0endpoint0_endpointind 303// base address: 0x0 304#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 305#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 306#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 307#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 308#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 309#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 310#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 311#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 312#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 313#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c 314#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d 315#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e 316#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 317#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 318#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 319#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 320#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 321#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 322#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 323#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 324#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a 325#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b 326#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c 327#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d 328#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e 329#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f 330#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 331#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 332#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 333#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 334#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 335#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 336#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 337#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 338#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 339#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a 340#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b 341#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c 342#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d 343#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e 344#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f 345#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 346#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 347#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 348#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 349#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 350#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 351#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 352#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 353#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 354#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a 355#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b 356#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c 357#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d 358#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e 359#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f 360#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 361#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 362#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 363#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 364#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 365#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 366#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 367#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 368#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 369#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 370#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a 371#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b 372#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c 373#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d 374#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e 375#define ixAZF0ENDPOINT0_AZALIA_F0_ENDPOINT_FGCG_REP_DIS 0x0070 376 377 378// addressBlock: azf0endpoint1_endpointind 379// base address: 0x0 380#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 381#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 382#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 383#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 384#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 385#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 386#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 387#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 388#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 389#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c 390#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d 391#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e 392#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 393#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 394#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 395#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 396#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 397#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 398#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 399#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 400#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a 401#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b 402#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c 403#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d 404#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e 405#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f 406#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 407#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 408#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 409#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 410#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 411#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 412#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 413#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 414#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 415#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a 416#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b 417#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c 418#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d 419#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e 420#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f 421#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 422#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 423#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 424#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 425#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 426#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 427#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 428#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 429#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 430#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a 431#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b 432#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c 433#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d 434#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e 435#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f 436#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 437#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 438#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 439#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 440#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 441#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 442#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 443#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 444#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 445#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 446#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a 447#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b 448#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c 449#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d 450#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e 451#define ixAZF0ENDPOINT1_AZALIA_F0_ENDPOINT_FGCG_REP_DIS 0x0070 452 453 454// addressBlock: azf0endpoint2_endpointind 455// base address: 0x0 456#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 457#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 458#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 459#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 460#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 461#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 462#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 463#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 464#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 465#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c 466#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d 467#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e 468#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 469#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 470#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 471#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 472#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 473#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 474#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 475#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 476#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a 477#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b 478#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c 479#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d 480#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e 481#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f 482#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 483#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 484#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 485#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 486#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 487#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 488#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 489#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 490#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 491#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a 492#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b 493#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c 494#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d 495#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e 496#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f 497#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 498#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 499#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 500#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 501#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 502#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 503#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 504#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 505#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 506#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a 507#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b 508#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c 509#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d 510#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e 511#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f 512#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 513#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 514#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 515#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 516#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 517#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 518#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 519#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 520#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 521#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 522#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a 523#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b 524#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c 525#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d 526#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e 527#define ixAZF0ENDPOINT2_AZALIA_F0_ENDPOINT_FGCG_REP_DIS 0x0070 528 529 530// addressBlock: azf0endpoint3_endpointind 531// base address: 0x0 532#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 533#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 534#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 535#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 536#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 537#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 538#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 539#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 540#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 541#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c 542#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d 543#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e 544#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 545#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 546#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 547#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 548#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 549#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 550#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 551#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 552#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a 553#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b 554#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c 555#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d 556#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e 557#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f 558#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 559#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 560#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 561#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 562#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 563#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 564#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 565#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 566#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 567#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a 568#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b 569#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c 570#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d 571#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e 572#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f 573#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 574#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 575#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 576#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 577#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 578#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 579#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 580#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 581#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 582#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a 583#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b 584#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c 585#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d 586#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e 587#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f 588#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 589#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 590#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 591#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 592#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 593#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 594#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 595#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 596#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 597#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 598#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a 599#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b 600#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c 601#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d 602#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e 603#define ixAZF0ENDPOINT3_AZALIA_F0_ENDPOINT_FGCG_REP_DIS 0x0070 604 605 606// addressBlock: azf0endpoint4_endpointind 607// base address: 0x0 608#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 609#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 610#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 611#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 612#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 613#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 614#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 615#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 616#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 617#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c 618#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d 619#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e 620#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 621#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 622#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 623#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 624#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 625#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 626#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 627#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 628#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a 629#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b 630#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c 631#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d 632#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e 633#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f 634#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 635#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 636#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 637#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 638#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 639#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 640#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 641#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 642#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 643#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a 644#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b 645#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c 646#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d 647#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e 648#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f 649#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 650#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 651#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 652#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 653#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 654#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 655#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 656#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 657#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 658#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a 659#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b 660#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c 661#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d 662#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e 663#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f 664#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 665#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 666#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 667#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 668#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 669#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 670#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 671#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 672#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 673#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 674#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a 675#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b 676#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c 677#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d 678#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e 679#define ixAZF0ENDPOINT4_AZALIA_F0_ENDPOINT_FGCG_REP_DIS 0x0070 680 681 682// addressBlock: azf0endpoint5_endpointind 683// base address: 0x0 684#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 685#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 686#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 687#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 688#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 689#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 690#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 691#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 692#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 693#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c 694#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d 695#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e 696#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 697#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 698#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 699#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 700#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 701#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 702#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 703#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 704#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a 705#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b 706#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c 707#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d 708#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e 709#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f 710#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 711#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 712#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 713#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 714#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 715#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 716#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 717#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 718#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 719#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a 720#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b 721#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c 722#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d 723#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e 724#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f 725#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 726#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 727#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 728#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 729#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 730#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 731#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 732#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 733#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 734#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a 735#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b 736#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c 737#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d 738#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e 739#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f 740#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 741#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 742#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 743#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 744#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 745#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 746#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 747#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 748#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 749#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 750#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a 751#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b 752#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c 753#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d 754#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e 755#define ixAZF0ENDPOINT5_AZALIA_F0_ENDPOINT_FGCG_REP_DIS 0x0070 756 757 758// addressBlock: azf0endpoint6_endpointind 759// base address: 0x0 760#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 761#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 762#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 763#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 764#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 765#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 766#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 767#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 768#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 769#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c 770#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d 771#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e 772#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 773#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 774#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 775#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 776#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 777#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 778#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 779#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 780#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a 781#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b 782#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c 783#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d 784#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e 785#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f 786#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 787#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 788#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 789#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 790#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 791#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 792#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 793#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 794#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 795#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a 796#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b 797#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c 798#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d 799#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e 800#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f 801#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 802#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 803#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 804#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 805#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 806#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 807#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 808#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 809#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 810#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a 811#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b 812#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c 813#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d 814#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e 815#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f 816#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 817#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 818#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 819#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 820#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 821#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 822#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 823#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 824#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 825#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 826#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a 827#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b 828#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c 829#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d 830#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e 831#define ixAZF0ENDPOINT6_AZALIA_F0_ENDPOINT_FGCG_REP_DIS 0x0070 832 833 834// addressBlock: azf0endpoint7_endpointind 835// base address: 0x0 836#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 837#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 838#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 839#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 840#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 841#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 842#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 843#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 844#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 845#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c 846#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d 847#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e 848#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 849#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 850#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 851#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 852#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 853#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 854#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 855#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 856#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a 857#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b 858#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c 859#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d 860#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e 861#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f 862#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 863#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 864#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 865#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 866#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 867#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 868#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 869#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 870#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 871#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a 872#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b 873#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c 874#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d 875#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e 876#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f 877#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 878#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 879#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 880#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 881#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 882#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 883#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 884#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 885#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 886#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a 887#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b 888#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c 889#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d 890#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e 891#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f 892#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 893#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 894#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 895#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 896#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 897#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 898#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 899#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 900#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 901#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 902#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a 903#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b 904#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c 905#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d 906#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e 907#define ixAZF0ENDPOINT7_AZALIA_F0_ENDPOINT_FGCG_REP_DIS 0x0070 908 909 910// addressBlock: azf0inputendpoint0_inputendpointind 911// base address: 0x0 912#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 913#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 914#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 915#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 916#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 917#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 918#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 919#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 920#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 921#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 922#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 923#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 924#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 925#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 926#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 927#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 928#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 929#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 930#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 931#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 932#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 933#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 934#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 935 936 937// addressBlock: azf0inputendpoint1_inputendpointind 938// base address: 0x0 939#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 940#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 941#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 942#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 943#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 944#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 945#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 946#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 947#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 948#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 949#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 950#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 951#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 952#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 953#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 954#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 955#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 956#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 957#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 958#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 959#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 960#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 961#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 962 963 964// addressBlock: azf0inputendpoint2_inputendpointind 965// base address: 0x0 966#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 967#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 968#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 969#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 970#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 971#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 972#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 973#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 974#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 975#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 976#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 977#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 978#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 979#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 980#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 981#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 982#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 983#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 984#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 985#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 986#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 987#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 988#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 989 990 991// addressBlock: azf0inputendpoint3_inputendpointind 992// base address: 0x0 993#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 994#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 995#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 996#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 997#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 998#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 999#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 1000#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 1001#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 1002#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 1003#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 1004#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 1005#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 1006#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 1007#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 1008#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 1009#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 1010#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 1011#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 1012#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 1013#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 1014#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 1015#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 1016 1017 1018// addressBlock: azf0inputendpoint4_inputendpointind 1019// base address: 0x0 1020#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 1021#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 1022#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 1023#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 1024#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 1025#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 1026#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 1027#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 1028#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 1029#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 1030#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 1031#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 1032#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 1033#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 1034#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 1035#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 1036#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 1037#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 1038#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 1039#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 1040#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 1041#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 1042#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 1043 1044 1045// addressBlock: azf0inputendpoint5_inputendpointind 1046// base address: 0x0 1047#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 1048#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 1049#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 1050#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 1051#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 1052#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 1053#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 1054#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 1055#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 1056#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 1057#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 1058#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 1059#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 1060#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 1061#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 1062#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 1063#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 1064#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 1065#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 1066#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 1067#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 1068#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 1069#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 1070 1071 1072// addressBlock: azf0inputendpoint6_inputendpointind 1073// base address: 0x0 1074#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 1075#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 1076#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 1077#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 1078#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 1079#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 1080#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 1081#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 1082#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 1083#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 1084#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 1085#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 1086#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 1087#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 1088#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 1089#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 1090#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 1091#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 1092#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 1093#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 1094#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 1095#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 1096#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 1097 1098 1099// addressBlock: azf0inputendpoint7_inputendpointind 1100// base address: 0x0 1101#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 1102#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 1103#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 1104#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 1105#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 1106#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 1107#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 1108#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 1109#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 1110#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 1111#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 1112#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 1113#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 1114#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 1115#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 1116#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 1117#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 1118#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 1119#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 1120#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 1121#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 1122#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 1123#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 1124 1125 1126// addressBlock: azendpoint_descriptorind 1127// base address: 0x0 1128#define ixAUDIO_DESCRIPTOR0 0x0001 1129#define ixAUDIO_DESCRIPTOR1 0x0002 1130#define ixAUDIO_DESCRIPTOR2 0x0003 1131#define ixAUDIO_DESCRIPTOR3 0x0004 1132#define ixAUDIO_DESCRIPTOR4 0x0005 1133#define ixAUDIO_DESCRIPTOR5 0x0006 1134#define ixAUDIO_DESCRIPTOR6 0x0007 1135#define ixAUDIO_DESCRIPTOR7 0x0008 1136#define ixAUDIO_DESCRIPTOR8 0x0009 1137#define ixAUDIO_DESCRIPTOR9 0x000a 1138#define ixAUDIO_DESCRIPTOR10 0x000b 1139#define ixAUDIO_DESCRIPTOR11 0x000c 1140#define ixAUDIO_DESCRIPTOR12 0x000d 1141#define ixAUDIO_DESCRIPTOR13 0x000e 1142 1143// addressBlock: dce_dc_hda_azendpoint_azdec 1144// base address: 0x1300000 1145#define regAZENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x4b7018 1146#define regAZENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX 3 1147#define regAZENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x4b7018 1148#define regAZENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX 3 1149 1150 1151// addressBlock: dce_dc_hda_azinputendpoint_azdec 1152// base address: 0x1300000 1153#define regAZINPUTENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA 0x4b7018 1154#define regAZINPUTENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA_BASE_IDX 3 1155#define regAZINPUTENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX 0x4b7018 1156#define regAZINPUTENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX_BASE_IDX 3 1157 1158 1159// addressBlock: dce_dc_dccg_dccg_dispdec 1160// base address: 0x0 1161#define regPHYPLLA_PIXCLK_RESYNC_CNTL 0x0040 1162#define regPHYPLLA_PIXCLK_RESYNC_CNTL_BASE_IDX 1 1163#define regPHYPLLB_PIXCLK_RESYNC_CNTL 0x0041 1164#define regPHYPLLB_PIXCLK_RESYNC_CNTL_BASE_IDX 1 1165#define regPHYPLLC_PIXCLK_RESYNC_CNTL 0x0042 1166#define regPHYPLLC_PIXCLK_RESYNC_CNTL_BASE_IDX 1 1167#define regPHYPLLD_PIXCLK_RESYNC_CNTL 0x0043 1168#define regPHYPLLD_PIXCLK_RESYNC_CNTL_BASE_IDX 1 1169#define regDP_DTO_DBUF_EN 0x0044 1170#define regDP_DTO_DBUF_EN_BASE_IDX 1 1171#define regDSCCLK3_DTO_PARAM 0x0045 1172#define regDSCCLK3_DTO_PARAM_BASE_IDX 1 1173#define regDPREFCLK_CGTT_BLK_CTRL_REG 0x0048 1174#define regDPREFCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1 1175#define regDCCG_GATE_DISABLE_CNTL4 0x0049 1176#define regDCCG_GATE_DISABLE_CNTL4_BASE_IDX 1 1177#define regDPSTREAMCLK_CNTL 0x004a 1178#define regDPSTREAMCLK_CNTL_BASE_IDX 1 1179#define regREFCLK_CGTT_BLK_CTRL_REG 0x004b 1180#define regREFCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1 1181#define regPHYPLLE_PIXCLK_RESYNC_CNTL 0x004c 1182#define regPHYPLLE_PIXCLK_RESYNC_CNTL_BASE_IDX 1 1183#define regDCCG_PERFMON_CNTL2 0x004e 1184#define regDCCG_PERFMON_CNTL2_BASE_IDX 1 1185#define regDCCG_GLOBAL_FGCG_REP_CNTL 0x0050 1186#define regDCCG_GLOBAL_FGCG_REP_CNTL_BASE_IDX 1 1187#define regDCCG_DS_DTO_INCR 0x0053 1188#define regDCCG_DS_DTO_INCR_BASE_IDX 1 1189#define regDCCG_DS_DTO_MODULO 0x0054 1190#define regDCCG_DS_DTO_MODULO_BASE_IDX 1 1191#define regDCCG_DS_CNTL 0x0055 1192#define regDCCG_DS_CNTL_BASE_IDX 1 1193#define regDCCG_DS_HW_CAL_INTERVAL 0x0056 1194#define regDCCG_DS_HW_CAL_INTERVAL_BASE_IDX 1 1195#define regDPREFCLK_CNTL 0x0058 1196#define regDPREFCLK_CNTL_BASE_IDX 1 1197#define regDCE_VERSION 0x005e 1198#define regDCE_VERSION_BASE_IDX 1 1199#define regDCCG_GTC_CNTL 0x0060 1200#define regDCCG_GTC_CNTL_BASE_IDX 1 1201#define regDCCG_GTC_DTO_INCR 0x0061 1202#define regDCCG_GTC_DTO_INCR_BASE_IDX 1 1203#define regDCCG_GTC_DTO_MODULO 0x0062 1204#define regDCCG_GTC_DTO_MODULO_BASE_IDX 1 1205#define regDCCG_GTC_CURRENT 0x0063 1206#define regDCCG_GTC_CURRENT_BASE_IDX 1 1207#define regSYMCLK32_SE_CNTL 0x0065 1208#define regSYMCLK32_SE_CNTL_BASE_IDX 1 1209#define regSYMCLK32_LE_CNTL 0x0066 1210#define regSYMCLK32_LE_CNTL_BASE_IDX 1 1211#define regDTBCLK_P_CNTL 0x0068 1212#define regDTBCLK_P_CNTL_BASE_IDX 1 1213#define regDCCG_GATE_DISABLE_CNTL5 0x0069 1214#define regDCCG_GATE_DISABLE_CNTL5_BASE_IDX 1 1215#define regDSCCLK0_DTO_PARAM 0x006c 1216#define regDSCCLK0_DTO_PARAM_BASE_IDX 1 1217#define regDSCCLK1_DTO_PARAM 0x006d 1218#define regDSCCLK1_DTO_PARAM_BASE_IDX 1 1219#define regDSCCLK2_DTO_PARAM 0x006e 1220#define regDSCCLK2_DTO_PARAM_BASE_IDX 1 1221#define regOTG_PIXEL_RATE_DIV 0x006f 1222#define regOTG_PIXEL_RATE_DIV_BASE_IDX 1 1223#define regMILLISECOND_TIME_BASE_DIV 0x0070 1224#define regMILLISECOND_TIME_BASE_DIV_BASE_IDX 1 1225#define regDISPCLK_FREQ_CHANGE_CNTL 0x0071 1226#define regDISPCLK_FREQ_CHANGE_CNTL_BASE_IDX 1 1227#define regDC_MEM_GLOBAL_PWR_REQ_CNTL 0x0072 1228#define regDC_MEM_GLOBAL_PWR_REQ_CNTL_BASE_IDX 1 1229#define regDCCG_PERFMON_CNTL 0x0073 1230#define regDCCG_PERFMON_CNTL_BASE_IDX 1 1231#define regDCCG_GATE_DISABLE_CNTL 0x0074 1232#define regDCCG_GATE_DISABLE_CNTL_BASE_IDX 1 1233#define regDISPCLK_CGTT_BLK_CTRL_REG 0x0075 1234#define regDISPCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1 1235#define regSOCCLK_CGTT_BLK_CTRL_REG 0x0076 1236#define regSOCCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1 1237#define regDCCG_CAC_STATUS 0x0077 1238#define regDCCG_CAC_STATUS_BASE_IDX 1 1239#define regMICROSECOND_TIME_BASE_DIV 0x007b 1240#define regMICROSECOND_TIME_BASE_DIV_BASE_IDX 1 1241#define regDCCG_GATE_DISABLE_CNTL2 0x007c 1242#define regDCCG_GATE_DISABLE_CNTL2_BASE_IDX 1 1243#define regSYMCLK_CGTT_BLK_CTRL_REG 0x007d 1244#define regSYMCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1 1245#define regDCCG_DISP_CNTL_REG 0x007f 1246#define regDCCG_DISP_CNTL_REG_BASE_IDX 1 1247#define regOTG0_PIXEL_RATE_CNTL 0x0080 1248#define regOTG0_PIXEL_RATE_CNTL_BASE_IDX 1 1249#define regDP_DTO0_PHASE 0x0081 1250#define regDP_DTO0_PHASE_BASE_IDX 1 1251#define regDP_DTO0_MODULO 0x0082 1252#define regDP_DTO0_MODULO_BASE_IDX 1 1253#define regOTG0_PHYPLL_PIXEL_RATE_CNTL 0x0083 1254#define regOTG0_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1 1255#define regOTG1_PIXEL_RATE_CNTL 0x0084 1256#define regOTG1_PIXEL_RATE_CNTL_BASE_IDX 1 1257#define regDP_DTO1_PHASE 0x0085 1258#define regDP_DTO1_PHASE_BASE_IDX 1 1259#define regDP_DTO1_MODULO 0x0086 1260#define regDP_DTO1_MODULO_BASE_IDX 1 1261#define regOTG1_PHYPLL_PIXEL_RATE_CNTL 0x0087 1262#define regOTG1_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1 1263#define regOTG2_PIXEL_RATE_CNTL 0x0088 1264#define regOTG2_PIXEL_RATE_CNTL_BASE_IDX 1 1265#define regDP_DTO2_PHASE 0x0089 1266#define regDP_DTO2_PHASE_BASE_IDX 1 1267#define regDP_DTO2_MODULO 0x008a 1268#define regDP_DTO2_MODULO_BASE_IDX 1 1269#define regOTG2_PHYPLL_PIXEL_RATE_CNTL 0x008b 1270#define regOTG2_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1 1271#define regOTG3_PIXEL_RATE_CNTL 0x008c 1272#define regOTG3_PIXEL_RATE_CNTL_BASE_IDX 1 1273#define regDP_DTO3_PHASE 0x008d 1274#define regDP_DTO3_PHASE_BASE_IDX 1 1275#define regDP_DTO3_MODULO 0x008e 1276#define regDP_DTO3_MODULO_BASE_IDX 1 1277#define regOTG3_PHYPLL_PIXEL_RATE_CNTL 0x008f 1278#define regOTG3_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1 1279#define regDPPCLK_CGTT_BLK_CTRL_REG 0x0098 1280#define regDPPCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1 1281#define regDPPCLK0_DTO_PARAM 0x0099 1282#define regDPPCLK0_DTO_PARAM_BASE_IDX 1 1283#define regDPPCLK1_DTO_PARAM 0x009a 1284#define regDPPCLK1_DTO_PARAM_BASE_IDX 1 1285#define regDPPCLK2_DTO_PARAM 0x009b 1286#define regDPPCLK2_DTO_PARAM_BASE_IDX 1 1287#define regDPPCLK3_DTO_PARAM 0x009c 1288#define regDPPCLK3_DTO_PARAM_BASE_IDX 1 1289#define regDCCG_CAC_STATUS2 0x009f 1290#define regDCCG_CAC_STATUS2_BASE_IDX 1 1291#define regSYMCLKA_CLOCK_ENABLE 0x00a0 1292#define regSYMCLKA_CLOCK_ENABLE_BASE_IDX 1 1293#define regSYMCLKB_CLOCK_ENABLE 0x00a1 1294#define regSYMCLKB_CLOCK_ENABLE_BASE_IDX 1 1295#define regSYMCLKC_CLOCK_ENABLE 0x00a2 1296#define regSYMCLKC_CLOCK_ENABLE_BASE_IDX 1 1297#define regSYMCLKD_CLOCK_ENABLE 0x00a3 1298#define regSYMCLKD_CLOCK_ENABLE_BASE_IDX 1 1299#define regSYMCLKE_CLOCK_ENABLE 0x00a4 1300#define regSYMCLKE_CLOCK_ENABLE_BASE_IDX 1 1301#define regDCCG_SOFT_RESET 0x00a6 1302#define regDCCG_SOFT_RESET_BASE_IDX 1 1303#define regDSCCLK_DTO_CTRL 0x00a7 1304#define regDSCCLK_DTO_CTRL_BASE_IDX 1 1305#define regDPPCLK_CTRL 0x00a8 1306#define regDPPCLK_CTRL_BASE_IDX 1 1307#define regDCCG_GATE_DISABLE_CNTL6 0x00a9 1308#define regDCCG_GATE_DISABLE_CNTL6_BASE_IDX 1 1309#define regSYMCLK_PSP_CNTL 0x00aa 1310#define regSYMCLK_PSP_CNTL_BASE_IDX 1 1311#define regDCCG_AUDIO_DTO_SOURCE 0x00ab 1312#define regDCCG_AUDIO_DTO_SOURCE_BASE_IDX 1 1313#define regDCCG_AUDIO_DTO0_PHASE 0x00ac 1314#define regDCCG_AUDIO_DTO0_PHASE_BASE_IDX 1 1315#define regDCCG_AUDIO_DTO0_MODULE 0x00ad 1316#define regDCCG_AUDIO_DTO0_MODULE_BASE_IDX 1 1317#define regDCCG_AUDIO_DTO1_PHASE 0x00ae 1318#define regDCCG_AUDIO_DTO1_PHASE_BASE_IDX 1 1319#define regDCCG_AUDIO_DTO1_MODULE 0x00af 1320#define regDCCG_AUDIO_DTO1_MODULE_BASE_IDX 1 1321#define regDCCG_VSYNC_OTG0_LATCH_VALUE 0x00b0 1322#define regDCCG_VSYNC_OTG0_LATCH_VALUE_BASE_IDX 1 1323#define regDCCG_VSYNC_OTG1_LATCH_VALUE 0x00b1 1324#define regDCCG_VSYNC_OTG1_LATCH_VALUE_BASE_IDX 1 1325#define regDCCG_VSYNC_OTG2_LATCH_VALUE 0x00b2 1326#define regDCCG_VSYNC_OTG2_LATCH_VALUE_BASE_IDX 1 1327#define regDCCG_VSYNC_OTG3_LATCH_VALUE 0x00b3 1328#define regDCCG_VSYNC_OTG3_LATCH_VALUE_BASE_IDX 1 1329#define regDCCG_VSYNC_OTG4_LATCH_VALUE 0x00b4 1330#define regDCCG_VSYNC_OTG4_LATCH_VALUE_BASE_IDX 1 1331#define regDCCG_VSYNC_OTG5_LATCH_VALUE 0x00b5 1332#define regDCCG_VSYNC_OTG5_LATCH_VALUE_BASE_IDX 1 1333#define regDPPCLK_DTO_CTRL 0x00b6 1334#define regDPPCLK_DTO_CTRL_BASE_IDX 1 1335#define regDCCG_VSYNC_CNT_CTRL 0x00b8 1336#define regDCCG_VSYNC_CNT_CTRL_BASE_IDX 1 1337#define regDCCG_VSYNC_CNT_INT_CTRL 0x00b9 1338#define regDCCG_VSYNC_CNT_INT_CTRL_BASE_IDX 1 1339#define regFORCE_SYMCLK_DISABLE 0x00ba 1340#define regFORCE_SYMCLK_DISABLE_BASE_IDX 1 1341#define regDTBCLK_DTO0_PHASE 0x0018 1342#define regDTBCLK_DTO0_PHASE_BASE_IDX 2 1343#define regDTBCLK_DTO1_PHASE 0x0019 1344#define regDTBCLK_DTO1_PHASE_BASE_IDX 2 1345#define regDTBCLK_DTO2_PHASE 0x001a 1346#define regDTBCLK_DTO2_PHASE_BASE_IDX 2 1347#define regDTBCLK_DTO3_PHASE 0x001b 1348#define regDTBCLK_DTO3_PHASE_BASE_IDX 2 1349#define regDTBCLK_DTO0_MODULO 0x001f 1350#define regDTBCLK_DTO0_MODULO_BASE_IDX 2 1351#define regDTBCLK_DTO1_MODULO 0x0020 1352#define regDTBCLK_DTO1_MODULO_BASE_IDX 2 1353#define regDTBCLK_DTO2_MODULO 0x0021 1354#define regDTBCLK_DTO2_MODULO_BASE_IDX 2 1355#define regDTBCLK_DTO3_MODULO 0x0022 1356#define regDTBCLK_DTO3_MODULO_BASE_IDX 2 1357#define regHDMICHARCLK0_CLOCK_CNTL 0x004a 1358#define regHDMICHARCLK0_CLOCK_CNTL_BASE_IDX 2 1359#define regPHYASYMCLK_CLOCK_CNTL 0x0052 1360#define regPHYASYMCLK_CLOCK_CNTL_BASE_IDX 2 1361#define regPHYBSYMCLK_CLOCK_CNTL 0x0053 1362#define regPHYBSYMCLK_CLOCK_CNTL_BASE_IDX 2 1363#define regPHYCSYMCLK_CLOCK_CNTL 0x0054 1364#define regPHYCSYMCLK_CLOCK_CNTL_BASE_IDX 2 1365#define regPHYDSYMCLK_CLOCK_CNTL 0x0055 1366#define regPHYDSYMCLK_CLOCK_CNTL_BASE_IDX 2 1367#define regPHYESYMCLK_CLOCK_CNTL 0x0056 1368#define regPHYESYMCLK_CLOCK_CNTL_BASE_IDX 2 1369#define regHDMISTREAMCLK_CNTL 0x0059 1370#define regHDMISTREAMCLK_CNTL_BASE_IDX 2 1371#define regDCCG_GATE_DISABLE_CNTL3 0x005a 1372#define regDCCG_GATE_DISABLE_CNTL3_BASE_IDX 2 1373#define regHDMISTREAMCLK0_DTO_PARAM 0x005b 1374#define regHDMISTREAMCLK0_DTO_PARAM_BASE_IDX 2 1375#define regDCCG_AUDIO_DTBCLK_DTO_PHASE 0x0061 1376#define regDCCG_AUDIO_DTBCLK_DTO_PHASE_BASE_IDX 2 1377#define regDCCG_AUDIO_DTBCLK_DTO_MODULO 0x0062 1378#define regDCCG_AUDIO_DTBCLK_DTO_MODULO_BASE_IDX 2 1379#define regDTBCLK_DTO_DBUF_EN 0x0063 1380#define regDTBCLK_DTO_DBUF_EN_BASE_IDX 2 1381 1382// addressBlock: dce_dc_dccg_dccg_dfs_dispdec 1383// base address: 0x0 1384#define regDENTIST_DISPCLK_CNTL 0x0064 1385#define regDENTIST_DISPCLK_CNTL_BASE_IDX 1 1386 1387 1388// addressBlock: azroot_f2codecind 1389// base address: 0x0 1390#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID 0x0f00 1391#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID 0x0f02 1392#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT 0x0f04 1393#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE 0x1705 1394#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID 0x1720 1395#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2 0x1721 1396#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3 0x1722 1397#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4 0x1723 1398#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION 0x1770 1399#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESET 0x17ff 1400#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT 0x1f04 1401#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE 0x1f05 1402#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES 0x1f0a 1403#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS 0x1f0b 1404#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES 0x1f0f 1405 1406 1407// addressBlock: azendpoint_f2codecind 1408// base address: 0x0 1409#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x2200 1410#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x2706 1411#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x270d 1412#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2 0x270e 1413#define ixAZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL 0x2724 1414#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3 0x273e 1415#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x2770 1416#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x2771 1417#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x2f09 1418#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x2f0a 1419#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x2f0b 1420#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY 0x3702 1421#define ixAZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x3707 1422#define ixAZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x3708 1423#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x3709 1424#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x371c 1425#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2 0x371d 1426#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3 0x371e 1427#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4 0x371f 1428#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION 0x3770 1429#define ixAZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION 0x3771 1430#define ixAZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO 0x3772 1431#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR 0x3776 1432#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA 0x3776 1433#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE 0x3777 1434#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE 0x3778 1435#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE 0x3779 1436#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE 0x377a 1437#define ixAZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC 0x377b 1438#define ixAZALIA_F2_CODEC_PIN_CONTROL_HBR 0x377c 1439#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX 0x3780 1440#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA 0x3781 1441#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE 0x3785 1442#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE 0x3786 1443#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE 0x3787 1444#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE 0x3788 1445#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x3789 1446#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x378a 1447#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x378b 1448#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x378c 1449#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x378d 1450#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x378e 1451#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x378f 1452#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x3790 1453#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x3791 1454#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x3792 1455#define ixAZALIA_F2_CODEC_PIN_ASSOCIATION_INFO 0x3793 1456#define ixAZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x3797 1457#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x3798 1458#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB 0x3799 1459#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x379a 1460#define ixAZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE 0x379b 1461#define ixAZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x379c 1462#define ixAZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x379d 1463#define ixAZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x379e 1464#define ixAZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x3f09 1465#define ixAZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES 0x3f0c 1466#define ixAZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH 0x3f0e 1467 1468 1469// addressBlock: azinputendpoint_f2codecind 1470// base address: 0x0 1471#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x6200 1472#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x6706 1473#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x670d 1474#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x6f09 1475#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x6f0a 1476#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x6f0b 1477#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x7707 1478#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x7708 1479#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE 0x7709 1480#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x771c 1481#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2 0x771d 1482#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3 0x771e 1483#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4 0x771f 1484#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x7771 1485#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE 0x7777 1486#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE 0x7778 1487#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE 0x7779 1488#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE 0x777a 1489#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR 0x777c 1490#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE 0x7785 1491#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE 0x7786 1492#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE 0x7787 1493#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE 0x7788 1494#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x7798 1495#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB 0x7799 1496#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x779a 1497#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x779b 1498#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x779c 1499#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L 0x779d 1500#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H 0x779e 1501#define ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x7f09 1502#define ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x7f0c 1503 1504 1505// addressBlock: dce_dc_dccg_dccg_dcperfmon0_dc_perfmon_dispdec 1506// base address: 0x0 1507#define regDC_PERFMON0_PERFCOUNTER_CNTL 0x0000 1508#define regDC_PERFMON0_PERFCOUNTER_CNTL_BASE_IDX 2 1509#define regDC_PERFMON0_PERFCOUNTER_CNTL2 0x0001 1510#define regDC_PERFMON0_PERFCOUNTER_CNTL2_BASE_IDX 2 1511#define regDC_PERFMON0_PERFCOUNTER_STATE 0x0002 1512#define regDC_PERFMON0_PERFCOUNTER_STATE_BASE_IDX 2 1513#define regDC_PERFMON0_PERFMON_CNTL 0x0003 1514#define regDC_PERFMON0_PERFMON_CNTL_BASE_IDX 2 1515#define regDC_PERFMON0_PERFMON_CNTL2 0x0004 1516#define regDC_PERFMON0_PERFMON_CNTL2_BASE_IDX 2 1517#define regDC_PERFMON0_PERFMON_CVALUE_INT_MISC 0x0005 1518#define regDC_PERFMON0_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 1519#define regDC_PERFMON0_PERFMON_CVALUE_LOW 0x0006 1520#define regDC_PERFMON0_PERFMON_CVALUE_LOW_BASE_IDX 2 1521#define regDC_PERFMON0_PERFMON_HI 0x0007 1522#define regDC_PERFMON0_PERFMON_HI_BASE_IDX 2 1523#define regDC_PERFMON0_PERFMON_LOW 0x0008 1524#define regDC_PERFMON0_PERFMON_LOW_BASE_IDX 2 1525 1526 1527// addressBlock: dce_dc_dccg_dccg_dcperfmon1_dc_perfmon_dispdec 1528// base address: 0x30 1529#define regDC_PERFMON1_PERFCOUNTER_CNTL 0x000c 1530#define regDC_PERFMON1_PERFCOUNTER_CNTL_BASE_IDX 2 1531#define regDC_PERFMON1_PERFCOUNTER_CNTL2 0x000d 1532#define regDC_PERFMON1_PERFCOUNTER_CNTL2_BASE_IDX 2 1533#define regDC_PERFMON1_PERFCOUNTER_STATE 0x000e 1534#define regDC_PERFMON1_PERFCOUNTER_STATE_BASE_IDX 2 1535#define regDC_PERFMON1_PERFMON_CNTL 0x000f 1536#define regDC_PERFMON1_PERFMON_CNTL_BASE_IDX 2 1537#define regDC_PERFMON1_PERFMON_CNTL2 0x0010 1538#define regDC_PERFMON1_PERFMON_CNTL2_BASE_IDX 2 1539#define regDC_PERFMON1_PERFMON_CVALUE_INT_MISC 0x0011 1540#define regDC_PERFMON1_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 1541#define regDC_PERFMON1_PERFMON_CVALUE_LOW 0x0012 1542#define regDC_PERFMON1_PERFMON_CVALUE_LOW_BASE_IDX 2 1543#define regDC_PERFMON1_PERFMON_HI 0x0013 1544#define regDC_PERFMON1_PERFMON_HI_BASE_IDX 2 1545#define regDC_PERFMON1_PERFMON_LOW 0x0014 1546#define regDC_PERFMON1_PERFMON_LOW_BASE_IDX 2 1547 1548 1549// addressBlock: dce_dc_dmu_dc_pg_dispdec 1550// base address: 0x0 1551#define regDOMAIN0_PG_CONFIG 0x0080 1552#define regDOMAIN0_PG_CONFIG_BASE_IDX 2 1553#define regDOMAIN0_PG_STATUS 0x0081 1554#define regDOMAIN0_PG_STATUS_BASE_IDX 2 1555#define regDOMAIN1_PG_CONFIG 0x0082 1556#define regDOMAIN1_PG_CONFIG_BASE_IDX 2 1557#define regDOMAIN1_PG_STATUS 0x0083 1558#define regDOMAIN1_PG_STATUS_BASE_IDX 2 1559#define regDOMAIN2_PG_CONFIG 0x0084 1560#define regDOMAIN2_PG_CONFIG_BASE_IDX 2 1561#define regDOMAIN2_PG_STATUS 0x0085 1562#define regDOMAIN2_PG_STATUS_BASE_IDX 2 1563#define regDOMAIN3_PG_CONFIG 0x0086 1564#define regDOMAIN3_PG_CONFIG_BASE_IDX 2 1565#define regDOMAIN3_PG_STATUS 0x0087 1566#define regDOMAIN3_PG_STATUS_BASE_IDX 2 1567#define regDOMAIN16_PG_CONFIG 0x0089 1568#define regDOMAIN16_PG_CONFIG_BASE_IDX 2 1569#define regDOMAIN16_PG_STATUS 0x008a 1570#define regDOMAIN16_PG_STATUS_BASE_IDX 2 1571#define regDOMAIN17_PG_CONFIG 0x008b 1572#define regDOMAIN17_PG_CONFIG_BASE_IDX 2 1573#define regDOMAIN17_PG_STATUS 0x008c 1574#define regDOMAIN17_PG_STATUS_BASE_IDX 2 1575#define regDOMAIN18_PG_CONFIG 0x008d 1576#define regDOMAIN18_PG_CONFIG_BASE_IDX 2 1577#define regDOMAIN18_PG_STATUS 0x008e 1578#define regDOMAIN18_PG_STATUS_BASE_IDX 2 1579#define regDOMAIN19_PG_CONFIG 0x008f 1580#define regDOMAIN19_PG_CONFIG_BASE_IDX 2 1581#define regDOMAIN19_PG_STATUS 0x0090 1582#define regDOMAIN19_PG_STATUS_BASE_IDX 2 1583#define regDOMAIN22_PG_CONFIG 0x0092 1584#define regDOMAIN22_PG_CONFIG_BASE_IDX 2 1585#define regDOMAIN22_PG_STATUS 0x0093 1586#define regDOMAIN22_PG_STATUS_BASE_IDX 2 1587#define regDOMAIN23_PG_CONFIG 0x0094 1588#define regDOMAIN23_PG_CONFIG_BASE_IDX 2 1589#define regDOMAIN23_PG_STATUS 0x0095 1590#define regDOMAIN23_PG_STATUS_BASE_IDX 2 1591#define regDOMAIN24_PG_CONFIG 0x0096 1592#define regDOMAIN24_PG_CONFIG_BASE_IDX 2 1593#define regDOMAIN24_PG_STATUS 0x0097 1594#define regDOMAIN24_PG_STATUS_BASE_IDX 2 1595#define regDOMAIN25_PG_CONFIG 0x0098 1596#define regDOMAIN25_PG_CONFIG_BASE_IDX 2 1597#define regDOMAIN25_PG_STATUS 0x0099 1598#define regDOMAIN25_PG_STATUS_BASE_IDX 2 1599#define regDCPG_INTERRUPT_STATUS 0x009a 1600#define regDCPG_INTERRUPT_STATUS_BASE_IDX 2 1601#define regDCPG_INTERRUPT_STATUS_2 0x009b 1602#define regDCPG_INTERRUPT_STATUS_2_BASE_IDX 2 1603#define regDCPG_INTERRUPT_STATUS_3 0x009c 1604#define regDCPG_INTERRUPT_STATUS_3_BASE_IDX 2 1605#define regDCPG_INTERRUPT_CONTROL_1 0x009d 1606#define regDCPG_INTERRUPT_CONTROL_1_BASE_IDX 2 1607#define regDCPG_INTERRUPT_CONTROL_2 0x009e 1608#define regDCPG_INTERRUPT_CONTROL_2_BASE_IDX 2 1609#define regDCPG_INTERRUPT_CONTROL_3 0x009f 1610#define regDCPG_INTERRUPT_CONTROL_3_BASE_IDX 2 1611#define regDC_IP_REQUEST_CNTL 0x00a0 1612#define regDC_IP_REQUEST_CNTL_BASE_IDX 2 1613#define regLONO_MEM_PWR_REQ_CNTL 0x00a4 1614#define regLONO_MEM_PWR_REQ_CNTL_BASE_IDX 2 1615 1616 1617// addressBlock: dce_dc_dmu_dmu_dcperfmon_dc_perfmon_dispdec 1618// base address: 0x2f8 1619#define regDC_PERFMON2_PERFCOUNTER_CNTL 0x00be 1620#define regDC_PERFMON2_PERFCOUNTER_CNTL_BASE_IDX 2 1621#define regDC_PERFMON2_PERFCOUNTER_CNTL2 0x00bf 1622#define regDC_PERFMON2_PERFCOUNTER_CNTL2_BASE_IDX 2 1623#define regDC_PERFMON2_PERFCOUNTER_STATE 0x00c0 1624#define regDC_PERFMON2_PERFCOUNTER_STATE_BASE_IDX 2 1625#define regDC_PERFMON2_PERFMON_CNTL 0x00c1 1626#define regDC_PERFMON2_PERFMON_CNTL_BASE_IDX 2 1627#define regDC_PERFMON2_PERFMON_CNTL2 0x00c2 1628#define regDC_PERFMON2_PERFMON_CNTL2_BASE_IDX 2 1629#define regDC_PERFMON2_PERFMON_CVALUE_INT_MISC 0x00c3 1630#define regDC_PERFMON2_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 1631#define regDC_PERFMON2_PERFMON_CVALUE_LOW 0x00c4 1632#define regDC_PERFMON2_PERFMON_CVALUE_LOW_BASE_IDX 2 1633#define regDC_PERFMON2_PERFMON_HI 0x00c5 1634#define regDC_PERFMON2_PERFMON_HI_BASE_IDX 2 1635#define regDC_PERFMON2_PERFMON_LOW 0x00c6 1636#define regDC_PERFMON2_PERFMON_LOW_BASE_IDX 2 1637 1638 1639// addressBlock: dce_dc_dmu_dmu_misc_dispdec 1640// base address: 0x0 1641#define regCC_DC_PIPE_DIS 0x00ca 1642#define regCC_DC_PIPE_DIS_BASE_IDX 2 1643#define regDMU_CLK_CNTL 0x00cb 1644#define regDMU_CLK_CNTL_BASE_IDX 2 1645#define regDMCUB_SMU_INTERRUPT_CNTL 0x00cd 1646#define regDMCUB_SMU_INTERRUPT_CNTL_BASE_IDX 2 1647#define regSMU_INTERRUPT_CONTROL 0x00ce 1648#define regSMU_INTERRUPT_CONTROL_BASE_IDX 2 1649#define regZSC_CNTL 0x00cf 1650#define regZSC_CNTL_BASE_IDX 2 1651#define regZSC_CNTL2 0x00d0 1652#define regZSC_CNTL2_BASE_IDX 2 1653#define regDMU_MISC_ALLOW_DS_FORCE 0x00d6 1654#define regDMU_MISC_ALLOW_DS_FORCE_BASE_IDX 2 1655#define regZSC_STATUS 0x00d7 1656#define regZSC_STATUS_BASE_IDX 2 1657#define regDMU_DISPCLK_CGTT_BLK_CTRL_REG 0x00d8 1658#define regDMU_DISPCLK_CGTT_BLK_CTRL_REG_BASE_IDX 2 1659#define regDMU_SOCCLK_CGTT_BLK_CTRL_REG 0x00d9 1660#define regDMU_SOCCLK_CGTT_BLK_CTRL_REG_BASE_IDX 2 1661#define regZPR_CLK_UNGATE_DELAY 0x00da 1662#define regZPR_CLK_UNGATE_DELAY_BASE_IDX 2 1663 1664 1665 1666// addressBlock: dce_dc_dmu_ihc_dispdec 1667// base address: 0x0 1668#define regDC_GPU_TIMER_START_POSITION_V_UPDATE 0x0126 1669#define regDC_GPU_TIMER_START_POSITION_V_UPDATE_BASE_IDX 2 1670#define regDC_GPU_TIMER_START_POSITION_VSTARTUP 0x0127 1671#define regDC_GPU_TIMER_START_POSITION_VSTARTUP_BASE_IDX 2 1672#define regDC_GPU_TIMER_READ 0x0128 1673#define regDC_GPU_TIMER_READ_BASE_IDX 2 1674#define regDC_GPU_TIMER_READ_CNTL 0x0129 1675#define regDC_GPU_TIMER_READ_CNTL_BASE_IDX 2 1676#define regDISP_INTERRUPT_STATUS 0x012a 1677#define regDISP_INTERRUPT_STATUS_BASE_IDX 2 1678#define regDISP_INTERRUPT_STATUS_CONTINUE 0x012b 1679#define regDISP_INTERRUPT_STATUS_CONTINUE_BASE_IDX 2 1680#define regDISP_INTERRUPT_STATUS_CONTINUE2 0x012c 1681#define regDISP_INTERRUPT_STATUS_CONTINUE2_BASE_IDX 2 1682#define regDISP_INTERRUPT_STATUS_CONTINUE3 0x012d 1683#define regDISP_INTERRUPT_STATUS_CONTINUE3_BASE_IDX 2 1684#define regDISP_INTERRUPT_STATUS_CONTINUE4 0x012e 1685#define regDISP_INTERRUPT_STATUS_CONTINUE4_BASE_IDX 2 1686#define regDISP_INTERRUPT_STATUS_CONTINUE5 0x012f 1687#define regDISP_INTERRUPT_STATUS_CONTINUE5_BASE_IDX 2 1688#define regDISP_INTERRUPT_STATUS_CONTINUE6 0x0130 1689#define regDISP_INTERRUPT_STATUS_CONTINUE6_BASE_IDX 2 1690#define regDISP_INTERRUPT_STATUS_CONTINUE7 0x0131 1691#define regDISP_INTERRUPT_STATUS_CONTINUE7_BASE_IDX 2 1692#define regDISP_INTERRUPT_STATUS_CONTINUE8 0x0132 1693#define regDISP_INTERRUPT_STATUS_CONTINUE8_BASE_IDX 2 1694#define regDISP_INTERRUPT_STATUS_CONTINUE9 0x0133 1695#define regDISP_INTERRUPT_STATUS_CONTINUE9_BASE_IDX 2 1696#define regDISP_INTERRUPT_STATUS_CONTINUE10 0x0134 1697#define regDISP_INTERRUPT_STATUS_CONTINUE10_BASE_IDX 2 1698#define regDISP_INTERRUPT_STATUS_CONTINUE11 0x0135 1699#define regDISP_INTERRUPT_STATUS_CONTINUE11_BASE_IDX 2 1700#define regDISP_INTERRUPT_STATUS_CONTINUE12 0x0136 1701#define regDISP_INTERRUPT_STATUS_CONTINUE12_BASE_IDX 2 1702#define regDISP_INTERRUPT_STATUS_CONTINUE13 0x0137 1703#define regDISP_INTERRUPT_STATUS_CONTINUE13_BASE_IDX 2 1704#define regDISP_INTERRUPT_STATUS_CONTINUE14 0x0138 1705#define regDISP_INTERRUPT_STATUS_CONTINUE14_BASE_IDX 2 1706#define regDISP_INTERRUPT_STATUS_CONTINUE15 0x0139 1707#define regDISP_INTERRUPT_STATUS_CONTINUE15_BASE_IDX 2 1708#define regDISP_INTERRUPT_STATUS_CONTINUE16 0x013a 1709#define regDISP_INTERRUPT_STATUS_CONTINUE16_BASE_IDX 2 1710#define regDISP_INTERRUPT_STATUS_CONTINUE17 0x013b 1711#define regDISP_INTERRUPT_STATUS_CONTINUE17_BASE_IDX 2 1712#define regDISP_INTERRUPT_STATUS_CONTINUE18 0x013c 1713#define regDISP_INTERRUPT_STATUS_CONTINUE18_BASE_IDX 2 1714#define regDISP_INTERRUPT_STATUS_CONTINUE19 0x013d 1715#define regDISP_INTERRUPT_STATUS_CONTINUE19_BASE_IDX 2 1716#define regDISP_INTERRUPT_STATUS_CONTINUE20 0x013e 1717#define regDISP_INTERRUPT_STATUS_CONTINUE20_BASE_IDX 2 1718#define regDISP_INTERRUPT_STATUS_CONTINUE21 0x013f 1719#define regDISP_INTERRUPT_STATUS_CONTINUE21_BASE_IDX 2 1720#define regDISP_INTERRUPT_STATUS_CONTINUE22 0x0140 1721#define regDISP_INTERRUPT_STATUS_CONTINUE22_BASE_IDX 2 1722#define regDC_GPU_TIMER_START_POSITION_VREADY 0x0141 1723#define regDC_GPU_TIMER_START_POSITION_VREADY_BASE_IDX 2 1724#define regDC_GPU_TIMER_START_POSITION_FLIP 0x0142 1725#define regDC_GPU_TIMER_START_POSITION_FLIP_BASE_IDX 2 1726#define regDC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK 0x0143 1727#define regDC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK_BASE_IDX 2 1728#define regDC_GPU_TIMER_START_POSITION_FLIP_AWAY 0x0144 1729#define regDC_GPU_TIMER_START_POSITION_FLIP_AWAY_BASE_IDX 2 1730#define regDISP_INTERRUPT_STATUS_CONTINUE23 0x0145 1731#define regDISP_INTERRUPT_STATUS_CONTINUE23_BASE_IDX 2 1732#define regDISP_INTERRUPT_STATUS_CONTINUE24 0x0146 1733#define regDISP_INTERRUPT_STATUS_CONTINUE24_BASE_IDX 2 1734#define regDISP_INTERRUPT_STATUS_CONTINUE25 0x0147 1735#define regDISP_INTERRUPT_STATUS_CONTINUE25_BASE_IDX 2 1736#define regDCCG_INTERRUPT_DEST 0x0148 1737#define regDCCG_INTERRUPT_DEST_BASE_IDX 2 1738#define regDMU_INTERRUPT_DEST 0x0149 1739#define regDMU_INTERRUPT_DEST_BASE_IDX 2 1740#define regDMU_INTERRUPT_DEST2 0x014a 1741#define regDMU_INTERRUPT_DEST2_BASE_IDX 2 1742#define regDCPG_INTERRUPT_DEST 0x014b 1743#define regDCPG_INTERRUPT_DEST_BASE_IDX 2 1744#define regDCPG_INTERRUPT_DEST2 0x014c 1745#define regDCPG_INTERRUPT_DEST2_BASE_IDX 2 1746#define regMMHUBBUB_INTERRUPT_DEST 0x014d 1747#define regMMHUBBUB_INTERRUPT_DEST_BASE_IDX 2 1748#define regWB_INTERRUPT_DEST 0x014e 1749#define regWB_INTERRUPT_DEST_BASE_IDX 2 1750#define regDCHUB_INTERRUPT_DEST 0x014f 1751#define regDCHUB_INTERRUPT_DEST_BASE_IDX 2 1752#define regDCHUB_PERFCOUNTER_INTERRUPT_DEST 0x0150 1753#define regDCHUB_PERFCOUNTER_INTERRUPT_DEST_BASE_IDX 2 1754#define regDCHUB_INTERRUPT_DEST2 0x0151 1755#define regDCHUB_INTERRUPT_DEST2_BASE_IDX 2 1756#define regDPP_PERFCOUNTER_INTERRUPT_DEST 0x0152 1757#define regDPP_PERFCOUNTER_INTERRUPT_DEST_BASE_IDX 2 1758#define regMPC_INTERRUPT_DEST 0x0153 1759#define regMPC_INTERRUPT_DEST_BASE_IDX 2 1760#define regOPP_INTERRUPT_DEST 0x0154 1761#define regOPP_INTERRUPT_DEST_BASE_IDX 2 1762#define regOPTC_INTERRUPT_DEST 0x0155 1763#define regOPTC_INTERRUPT_DEST_BASE_IDX 2 1764#define regOTG0_INTERRUPT_DEST 0x0156 1765#define regOTG0_INTERRUPT_DEST_BASE_IDX 2 1766#define regOTG1_INTERRUPT_DEST 0x0157 1767#define regOTG1_INTERRUPT_DEST_BASE_IDX 2 1768#define regOTG2_INTERRUPT_DEST 0x0158 1769#define regOTG2_INTERRUPT_DEST_BASE_IDX 2 1770#define regOTG3_INTERRUPT_DEST 0x0159 1771#define regOTG3_INTERRUPT_DEST_BASE_IDX 2 1772#define regOTG4_INTERRUPT_DEST 0x015a 1773#define regOTG4_INTERRUPT_DEST_BASE_IDX 2 1774#define regOTG5_INTERRUPT_DEST 0x015b 1775#define regOTG5_INTERRUPT_DEST_BASE_IDX 2 1776#define regDIG_INTERRUPT_DEST 0x015c 1777#define regDIG_INTERRUPT_DEST_BASE_IDX 2 1778#define regI2C_DDC_HPD_INTERRUPT_DEST 0x015d 1779#define regI2C_DDC_HPD_INTERRUPT_DEST_BASE_IDX 2 1780#define regDIO_INTERRUPT_DEST 0x015f 1781#define regDIO_INTERRUPT_DEST_BASE_IDX 2 1782#define regDCIO_INTERRUPT_DEST 0x0160 1783#define regDCIO_INTERRUPT_DEST_BASE_IDX 2 1784#define regHPD_INTERRUPT_DEST 0x0161 1785#define regHPD_INTERRUPT_DEST_BASE_IDX 2 1786#define regAZ_INTERRUPT_DEST 0x0162 1787#define regAZ_INTERRUPT_DEST_BASE_IDX 2 1788#define regAUX_INTERRUPT_DEST 0x0163 1789#define regAUX_INTERRUPT_DEST_BASE_IDX 2 1790#define regDSC_INTERRUPT_DEST 0x0164 1791#define regDSC_INTERRUPT_DEST_BASE_IDX 2 1792#define regHPO_INTERRUPT_DEST 0x0165 1793#define regHPO_INTERRUPT_DEST_BASE_IDX 2 1794 1795 1796// addressBlock: dce_dc_dmu_fgsec_dispdec 1797// base address: 0x0 1798#define regDMCUB_RBBMIF_SEC_CNTL 0x017a 1799#define regDMCUB_RBBMIF_SEC_CNTL_BASE_IDX 2 1800 1801 1802// addressBlock: dce_dc_dmu_rbbmif_dispdec 1803// base address: 0x0 1804#define regRBBMIF_TIMEOUT 0x017f 1805#define regRBBMIF_TIMEOUT_BASE_IDX 2 1806#define regRBBMIF_STATUS 0x0180 1807#define regRBBMIF_STATUS_BASE_IDX 2 1808#define regRBBMIF_STATUS_2 0x0181 1809#define regRBBMIF_STATUS_2_BASE_IDX 2 1810#define regRBBMIF_INT_STATUS 0x0182 1811#define regRBBMIF_INT_STATUS_BASE_IDX 2 1812#define regRBBMIF_TIMEOUT_DIS 0x0183 1813#define regRBBMIF_TIMEOUT_DIS_BASE_IDX 2 1814#define regRBBMIF_TIMEOUT_DIS_2 0x0184 1815#define regRBBMIF_TIMEOUT_DIS_2_BASE_IDX 2 1816#define regRBBMIF_STATUS_FLAG 0x0185 1817#define regRBBMIF_STATUS_FLAG_BASE_IDX 2 1818 1819 1820// addressBlock: dce_dc_dmu_dmcub_dispdec 1821// base address: 0x0 1822#define regDMCUB_REGION0_OFFSET 0x018e 1823#define regDMCUB_REGION0_OFFSET_BASE_IDX 2 1824#define regDMCUB_REGION0_OFFSET_HIGH 0x018f 1825#define regDMCUB_REGION0_OFFSET_HIGH_BASE_IDX 2 1826#define regDMCUB_REGION1_OFFSET 0x0190 1827#define regDMCUB_REGION1_OFFSET_BASE_IDX 2 1828#define regDMCUB_REGION1_OFFSET_HIGH 0x0191 1829#define regDMCUB_REGION1_OFFSET_HIGH_BASE_IDX 2 1830#define regDMCUB_REGION2_OFFSET 0x0192 1831#define regDMCUB_REGION2_OFFSET_BASE_IDX 2 1832#define regDMCUB_REGION2_OFFSET_HIGH 0x0193 1833#define regDMCUB_REGION2_OFFSET_HIGH_BASE_IDX 2 1834#define regDMCUB_REGION4_OFFSET 0x0196 1835#define regDMCUB_REGION4_OFFSET_BASE_IDX 2 1836#define regDMCUB_REGION4_OFFSET_HIGH 0x0197 1837#define regDMCUB_REGION4_OFFSET_HIGH_BASE_IDX 2 1838#define regDMCUB_REGION5_OFFSET 0x0198 1839#define regDMCUB_REGION5_OFFSET_BASE_IDX 2 1840#define regDMCUB_REGION5_OFFSET_HIGH 0x0199 1841#define regDMCUB_REGION5_OFFSET_HIGH_BASE_IDX 2 1842#define regDMCUB_REGION6_OFFSET 0x019a 1843#define regDMCUB_REGION6_OFFSET_BASE_IDX 2 1844#define regDMCUB_REGION6_OFFSET_HIGH 0x019b 1845#define regDMCUB_REGION6_OFFSET_HIGH_BASE_IDX 2 1846#define regDMCUB_REGION7_OFFSET 0x019c 1847#define regDMCUB_REGION7_OFFSET_BASE_IDX 2 1848#define regDMCUB_REGION7_OFFSET_HIGH 0x019d 1849#define regDMCUB_REGION7_OFFSET_HIGH_BASE_IDX 2 1850#define regDMCUB_REGION0_TOP_ADDRESS 0x019e 1851#define regDMCUB_REGION0_TOP_ADDRESS_BASE_IDX 2 1852#define regDMCUB_REGION1_TOP_ADDRESS 0x019f 1853#define regDMCUB_REGION1_TOP_ADDRESS_BASE_IDX 2 1854#define regDMCUB_REGION2_TOP_ADDRESS 0x01a0 1855#define regDMCUB_REGION2_TOP_ADDRESS_BASE_IDX 2 1856#define regDMCUB_REGION4_TOP_ADDRESS 0x01a1 1857#define regDMCUB_REGION4_TOP_ADDRESS_BASE_IDX 2 1858#define regDMCUB_REGION5_TOP_ADDRESS 0x01a2 1859#define regDMCUB_REGION5_TOP_ADDRESS_BASE_IDX 2 1860#define regDMCUB_REGION6_TOP_ADDRESS 0x01a3 1861#define regDMCUB_REGION6_TOP_ADDRESS_BASE_IDX 2 1862#define regDMCUB_REGION7_TOP_ADDRESS 0x01a4 1863#define regDMCUB_REGION7_TOP_ADDRESS_BASE_IDX 2 1864#define regDMCUB_REGION3_CW0_BASE_ADDRESS 0x01a5 1865#define regDMCUB_REGION3_CW0_BASE_ADDRESS_BASE_IDX 2 1866#define regDMCUB_REGION3_CW1_BASE_ADDRESS 0x01a6 1867#define regDMCUB_REGION3_CW1_BASE_ADDRESS_BASE_IDX 2 1868#define regDMCUB_REGION3_CW2_BASE_ADDRESS 0x01a7 1869#define regDMCUB_REGION3_CW2_BASE_ADDRESS_BASE_IDX 2 1870#define regDMCUB_REGION3_CW3_BASE_ADDRESS 0x01a8 1871#define regDMCUB_REGION3_CW3_BASE_ADDRESS_BASE_IDX 2 1872#define regDMCUB_REGION3_CW4_BASE_ADDRESS 0x01a9 1873#define regDMCUB_REGION3_CW4_BASE_ADDRESS_BASE_IDX 2 1874#define regDMCUB_REGION3_CW5_BASE_ADDRESS 0x01aa 1875#define regDMCUB_REGION3_CW5_BASE_ADDRESS_BASE_IDX 2 1876#define regDMCUB_REGION3_CW6_BASE_ADDRESS 0x01ab 1877#define regDMCUB_REGION3_CW6_BASE_ADDRESS_BASE_IDX 2 1878#define regDMCUB_REGION3_CW7_BASE_ADDRESS 0x01ac 1879#define regDMCUB_REGION3_CW7_BASE_ADDRESS_BASE_IDX 2 1880#define regDMCUB_REGION3_CW0_TOP_ADDRESS 0x01ad 1881#define regDMCUB_REGION3_CW0_TOP_ADDRESS_BASE_IDX 2 1882#define regDMCUB_REGION3_CW1_TOP_ADDRESS 0x01ae 1883#define regDMCUB_REGION3_CW1_TOP_ADDRESS_BASE_IDX 2 1884#define regDMCUB_REGION3_CW2_TOP_ADDRESS 0x01af 1885#define regDMCUB_REGION3_CW2_TOP_ADDRESS_BASE_IDX 2 1886#define regDMCUB_REGION3_CW3_TOP_ADDRESS 0x01b0 1887#define regDMCUB_REGION3_CW3_TOP_ADDRESS_BASE_IDX 2 1888#define regDMCUB_REGION3_CW4_TOP_ADDRESS 0x01b1 1889#define regDMCUB_REGION3_CW4_TOP_ADDRESS_BASE_IDX 2 1890#define regDMCUB_REGION3_CW5_TOP_ADDRESS 0x01b2 1891#define regDMCUB_REGION3_CW5_TOP_ADDRESS_BASE_IDX 2 1892#define regDMCUB_REGION3_CW6_TOP_ADDRESS 0x01b3 1893#define regDMCUB_REGION3_CW6_TOP_ADDRESS_BASE_IDX 2 1894#define regDMCUB_REGION3_CW7_TOP_ADDRESS 0x01b4 1895#define regDMCUB_REGION3_CW7_TOP_ADDRESS_BASE_IDX 2 1896#define regDMCUB_REGION3_CW0_OFFSET 0x01b5 1897#define regDMCUB_REGION3_CW0_OFFSET_BASE_IDX 2 1898#define regDMCUB_REGION3_CW0_OFFSET_HIGH 0x01b6 1899#define regDMCUB_REGION3_CW0_OFFSET_HIGH_BASE_IDX 2 1900#define regDMCUB_REGION3_CW1_OFFSET 0x01b7 1901#define regDMCUB_REGION3_CW1_OFFSET_BASE_IDX 2 1902#define regDMCUB_REGION3_CW1_OFFSET_HIGH 0x01b8 1903#define regDMCUB_REGION3_CW1_OFFSET_HIGH_BASE_IDX 2 1904#define regDMCUB_REGION3_CW2_OFFSET 0x01b9 1905#define regDMCUB_REGION3_CW2_OFFSET_BASE_IDX 2 1906#define regDMCUB_REGION3_CW2_OFFSET_HIGH 0x01ba 1907#define regDMCUB_REGION3_CW2_OFFSET_HIGH_BASE_IDX 2 1908#define regDMCUB_REGION3_CW3_OFFSET 0x01bb 1909#define regDMCUB_REGION3_CW3_OFFSET_BASE_IDX 2 1910#define regDMCUB_REGION3_CW3_OFFSET_HIGH 0x01bc 1911#define regDMCUB_REGION3_CW3_OFFSET_HIGH_BASE_IDX 2 1912#define regDMCUB_REGION3_CW4_OFFSET 0x01bd 1913#define regDMCUB_REGION3_CW4_OFFSET_BASE_IDX 2 1914#define regDMCUB_REGION3_CW4_OFFSET_HIGH 0x01be 1915#define regDMCUB_REGION3_CW4_OFFSET_HIGH_BASE_IDX 2 1916#define regDMCUB_REGION3_CW5_OFFSET 0x01bf 1917#define regDMCUB_REGION3_CW5_OFFSET_BASE_IDX 2 1918#define regDMCUB_REGION3_CW5_OFFSET_HIGH 0x01c0 1919#define regDMCUB_REGION3_CW5_OFFSET_HIGH_BASE_IDX 2 1920#define regDMCUB_REGION3_CW6_OFFSET 0x01c1 1921#define regDMCUB_REGION3_CW6_OFFSET_BASE_IDX 2 1922#define regDMCUB_REGION3_CW6_OFFSET_HIGH 0x01c2 1923#define regDMCUB_REGION3_CW6_OFFSET_HIGH_BASE_IDX 2 1924#define regDMCUB_REGION3_CW7_OFFSET 0x01c3 1925#define regDMCUB_REGION3_CW7_OFFSET_BASE_IDX 2 1926#define regDMCUB_REGION3_CW7_OFFSET_HIGH 0x01c4 1927#define regDMCUB_REGION3_CW7_OFFSET_HIGH_BASE_IDX 2 1928#define regDMCUB_INTERRUPT_ENABLE 0x01c5 1929#define regDMCUB_INTERRUPT_ENABLE_BASE_IDX 2 1930#define regDMCUB_INTERRUPT_ACK 0x01c6 1931#define regDMCUB_INTERRUPT_ACK_BASE_IDX 2 1932#define regDMCUB_INTERRUPT_STATUS 0x01c7 1933#define regDMCUB_INTERRUPT_STATUS_BASE_IDX 2 1934#define regDMCUB_INTERRUPT_TYPE 0x01c8 1935#define regDMCUB_INTERRUPT_TYPE_BASE_IDX 2 1936#define regDMCUB_EXT_INTERRUPT_STATUS 0x01c9 1937#define regDMCUB_EXT_INTERRUPT_STATUS_BASE_IDX 2 1938#define regDMCUB_EXT_INTERRUPT_CTXID 0x01ca 1939#define regDMCUB_EXT_INTERRUPT_CTXID_BASE_IDX 2 1940#define regDMCUB_EXT_INTERRUPT_ACK 0x01cb 1941#define regDMCUB_EXT_INTERRUPT_ACK_BASE_IDX 2 1942#define regDMCUB_INST_FETCH_FAULT_ADDR 0x01cc 1943#define regDMCUB_INST_FETCH_FAULT_ADDR_BASE_IDX 2 1944#define regDMCUB_DATA_WRITE_FAULT_ADDR 0x01cd 1945#define regDMCUB_DATA_WRITE_FAULT_ADDR_BASE_IDX 2 1946#define regDMCUB_SEC_CNTL 0x01ce 1947#define regDMCUB_SEC_CNTL_BASE_IDX 2 1948#define regDMCUB_MEM_CNTL 0x01cf 1949#define regDMCUB_MEM_CNTL_BASE_IDX 2 1950#define regDMCUB_INBOX0_BASE_ADDRESS 0x01d0 1951#define regDMCUB_INBOX0_BASE_ADDRESS_BASE_IDX 2 1952#define regDMCUB_INBOX0_SIZE 0x01d1 1953#define regDMCUB_INBOX0_SIZE_BASE_IDX 2 1954#define regDMCUB_INBOX0_WPTR 0x01d2 1955#define regDMCUB_INBOX0_WPTR_BASE_IDX 2 1956#define regDMCUB_INBOX0_RPTR 0x01d3 1957#define regDMCUB_INBOX0_RPTR_BASE_IDX 2 1958#define regDMCUB_INBOX1_BASE_ADDRESS 0x01d4 1959#define regDMCUB_INBOX1_BASE_ADDRESS_BASE_IDX 2 1960#define regDMCUB_INBOX1_SIZE 0x01d5 1961#define regDMCUB_INBOX1_SIZE_BASE_IDX 2 1962#define regDMCUB_INBOX1_WPTR 0x01d6 1963#define regDMCUB_INBOX1_WPTR_BASE_IDX 2 1964#define regDMCUB_INBOX1_RPTR 0x01d7 1965#define regDMCUB_INBOX1_RPTR_BASE_IDX 2 1966#define regDMCUB_OUTBOX0_BASE_ADDRESS 0x01d8 1967#define regDMCUB_OUTBOX0_BASE_ADDRESS_BASE_IDX 2 1968#define regDMCUB_OUTBOX0_SIZE 0x01d9 1969#define regDMCUB_OUTBOX0_SIZE_BASE_IDX 2 1970#define regDMCUB_OUTBOX0_WPTR 0x01da 1971#define regDMCUB_OUTBOX0_WPTR_BASE_IDX 2 1972#define regDMCUB_OUTBOX0_RPTR 0x01db 1973#define regDMCUB_OUTBOX0_RPTR_BASE_IDX 2 1974#define regDMCUB_OUTBOX1_BASE_ADDRESS 0x01dc 1975#define regDMCUB_OUTBOX1_BASE_ADDRESS_BASE_IDX 2 1976#define regDMCUB_OUTBOX1_SIZE 0x01dd 1977#define regDMCUB_OUTBOX1_SIZE_BASE_IDX 2 1978#define regDMCUB_OUTBOX1_WPTR 0x01de 1979#define regDMCUB_OUTBOX1_WPTR_BASE_IDX 2 1980#define regDMCUB_OUTBOX1_RPTR 0x01df 1981#define regDMCUB_OUTBOX1_RPTR_BASE_IDX 2 1982#define regDMCUB_TIMER_TRIGGER0 0x01e0 1983#define regDMCUB_TIMER_TRIGGER0_BASE_IDX 2 1984#define regDMCUB_TIMER_TRIGGER1 0x01e1 1985#define regDMCUB_TIMER_TRIGGER1_BASE_IDX 2 1986#define regDMCUB_TIMER_WINDOW 0x01e2 1987#define regDMCUB_TIMER_WINDOW_BASE_IDX 2 1988#define regDMCUB_SCRATCH0 0x01e3 1989#define regDMCUB_SCRATCH0_BASE_IDX 2 1990#define regDMCUB_SCRATCH1 0x01e4 1991#define regDMCUB_SCRATCH1_BASE_IDX 2 1992#define regDMCUB_SCRATCH2 0x01e5 1993#define regDMCUB_SCRATCH2_BASE_IDX 2 1994#define regDMCUB_SCRATCH3 0x01e6 1995#define regDMCUB_SCRATCH3_BASE_IDX 2 1996#define regDMCUB_SCRATCH4 0x01e7 1997#define regDMCUB_SCRATCH4_BASE_IDX 2 1998#define regDMCUB_SCRATCH5 0x01e8 1999#define regDMCUB_SCRATCH5_BASE_IDX 2 2000#define regDMCUB_SCRATCH6 0x01e9 2001#define regDMCUB_SCRATCH6_BASE_IDX 2 2002#define regDMCUB_SCRATCH7 0x01ea 2003#define regDMCUB_SCRATCH7_BASE_IDX 2 2004#define regDMCUB_SCRATCH8 0x01eb 2005#define regDMCUB_SCRATCH8_BASE_IDX 2 2006#define regDMCUB_SCRATCH9 0x01ec 2007#define regDMCUB_SCRATCH9_BASE_IDX 2 2008#define regDMCUB_SCRATCH10 0x01ed 2009#define regDMCUB_SCRATCH10_BASE_IDX 2 2010#define regDMCUB_SCRATCH11 0x01ee 2011#define regDMCUB_SCRATCH11_BASE_IDX 2 2012#define regDMCUB_SCRATCH12 0x01ef 2013#define regDMCUB_SCRATCH12_BASE_IDX 2 2014#define regDMCUB_SCRATCH13 0x01f0 2015#define regDMCUB_SCRATCH13_BASE_IDX 2 2016#define regDMCUB_SCRATCH14 0x01f1 2017#define regDMCUB_SCRATCH14_BASE_IDX 2 2018#define regDMCUB_SCRATCH15 0x01f2 2019#define regDMCUB_SCRATCH15_BASE_IDX 2 2020#define regDMCUB_SCRATCH16 0x01f3 2021#define regDMCUB_SCRATCH16_BASE_IDX 2 2022#define regDMCUB_SCRATCH17 0x01f4 2023#define regDMCUB_SCRATCH17_BASE_IDX 2 2024#define regDMCUB_SCRATCH18 0x01f5 2025#define regDMCUB_SCRATCH18_BASE_IDX 2 2026#define regDMCUB_CNTL 0x01f6 2027#define regDMCUB_CNTL_BASE_IDX 2 2028#define regDMCUB_GPINT_DATAIN0 0x01f7 2029#define regDMCUB_GPINT_DATAIN0_BASE_IDX 2 2030#define regDMCUB_GPINT_DATAIN1 0x01f8 2031#define regDMCUB_GPINT_DATAIN1_BASE_IDX 2 2032#define regDMCUB_GPINT_DATAOUT 0x01f9 2033#define regDMCUB_GPINT_DATAOUT_BASE_IDX 2 2034#define regDMCUB_UNDEFINED_ADDRESS_FAULT_ADDR 0x01fa 2035#define regDMCUB_UNDEFINED_ADDRESS_FAULT_ADDR_BASE_IDX 2 2036#define regDMCUB_LS_WAKE_INT_ENABLE 0x01fb 2037#define regDMCUB_LS_WAKE_INT_ENABLE_BASE_IDX 2 2038#define regDMCUB_MEM_PWR_CNTL 0x01fc 2039#define regDMCUB_MEM_PWR_CNTL_BASE_IDX 2 2040#define regDMCUB_TIMER_CURRENT 0x01fd 2041#define regDMCUB_TIMER_CURRENT_BASE_IDX 2 2042#define regDMCUB_PROC_ID 0x01ff 2043#define regDMCUB_PROC_ID_BASE_IDX 2 2044#define regDMCUB_CNTL2 0x0200 2045#define regDMCUB_CNTL2_BASE_IDX 2 2046#define regDMCUB_GPINT_DATAIN2 0x0215 2047#define regDMCUB_GPINT_DATAIN2_BASE_IDX 2 2048#define regDMCUB_GPINT_DATAIN3 0x0216 2049#define regDMCUB_GPINT_DATAIN3_BASE_IDX 2 2050#define regDMCUB_GPINT_DATAIN4 0x0217 2051#define regDMCUB_GPINT_DATAIN4_BASE_IDX 2 2052#define regDMCUB_GPINT_DATAIN5 0x0218 2053#define regDMCUB_GPINT_DATAIN5_BASE_IDX 2 2054#define regDMCUB_GPINT_DATAIN6 0x0219 2055#define regDMCUB_GPINT_DATAIN6_BASE_IDX 2 2056#define regDMCUB_REGION3_TMR_AXI_SPACE 0x021a 2057#define regDMCUB_REGION3_TMR_AXI_SPACE_BASE_IDX 2 2058#define regDMCUB_SCRATCH19 0x022e 2059#define regDMCUB_SCRATCH19_BASE_IDX 2 2060#define regDMCUB_SCRATCH20 0x022f 2061#define regDMCUB_SCRATCH20_BASE_IDX 2 2062#define regDMCUB_SCRATCH21 0x0230 2063#define regDMCUB_SCRATCH21_BASE_IDX 2 2064#define regDMCUB_SCRATCH22 0x0231 2065#define regDMCUB_SCRATCH22_BASE_IDX 2 2066#define regDMCUB_SCRATCH23 0x0232 2067#define regDMCUB_SCRATCH23_BASE_IDX 2 2068 2069 2070// addressBlock: dce_dc_mmhubbub_mcif_wb0_dispdec 2071// base address: 0x0 2072#define regMCIF_WB_BUFMGR_SW_CONTROL 0x0272 2073#define regMCIF_WB_BUFMGR_SW_CONTROL_BASE_IDX 2 2074#define regMCIF_WB_BUFMGR_STATUS 0x0274 2075#define regMCIF_WB_BUFMGR_STATUS_BASE_IDX 2 2076#define regMCIF_WB_BUF_PITCH 0x0275 2077#define regMCIF_WB_BUF_PITCH_BASE_IDX 2 2078#define regMCIF_WB_BUF_1_STATUS 0x0276 2079#define regMCIF_WB_BUF_1_STATUS_BASE_IDX 2 2080#define regMCIF_WB_BUF_1_STATUS2 0x0277 2081#define regMCIF_WB_BUF_1_STATUS2_BASE_IDX 2 2082#define regMCIF_WB_BUF_2_STATUS 0x0278 2083#define regMCIF_WB_BUF_2_STATUS_BASE_IDX 2 2084#define regMCIF_WB_BUF_2_STATUS2 0x0279 2085#define regMCIF_WB_BUF_2_STATUS2_BASE_IDX 2 2086#define regMCIF_WB_BUF_3_STATUS 0x027a 2087#define regMCIF_WB_BUF_3_STATUS_BASE_IDX 2 2088#define regMCIF_WB_BUF_3_STATUS2 0x027b 2089#define regMCIF_WB_BUF_3_STATUS2_BASE_IDX 2 2090#define regMCIF_WB_BUF_4_STATUS 0x027c 2091#define regMCIF_WB_BUF_4_STATUS_BASE_IDX 2 2092#define regMCIF_WB_BUF_4_STATUS2 0x027d 2093#define regMCIF_WB_BUF_4_STATUS2_BASE_IDX 2 2094#define regMCIF_WB_ARBITRATION_CONTROL 0x027e 2095#define regMCIF_WB_ARBITRATION_CONTROL_BASE_IDX 2 2096#define regMCIF_WB_SCLK_CHANGE 0x027f 2097#define regMCIF_WB_SCLK_CHANGE_BASE_IDX 2 2098#define regMCIF_WB_BUF_1_ADDR_Y 0x0282 2099#define regMCIF_WB_BUF_1_ADDR_Y_BASE_IDX 2 2100#define regMCIF_WB_BUF_1_ADDR_C 0x0284 2101#define regMCIF_WB_BUF_1_ADDR_C_BASE_IDX 2 2102#define regMCIF_WB_BUF_2_ADDR_Y 0x0286 2103#define regMCIF_WB_BUF_2_ADDR_Y_BASE_IDX 2 2104#define regMCIF_WB_BUF_2_ADDR_C 0x0288 2105#define regMCIF_WB_BUF_2_ADDR_C_BASE_IDX 2 2106#define regMCIF_WB_BUF_3_ADDR_Y 0x028a 2107#define regMCIF_WB_BUF_3_ADDR_Y_BASE_IDX 2 2108#define regMCIF_WB_BUF_3_ADDR_C 0x028c 2109#define regMCIF_WB_BUF_3_ADDR_C_BASE_IDX 2 2110#define regMCIF_WB_BUF_4_ADDR_Y 0x028e 2111#define regMCIF_WB_BUF_4_ADDR_Y_BASE_IDX 2 2112#define regMCIF_WB_BUF_4_ADDR_C 0x0290 2113#define regMCIF_WB_BUF_4_ADDR_C_BASE_IDX 2 2114#define regMCIF_WB_BUFMGR_VCE_CONTROL 0x0292 2115#define regMCIF_WB_BUFMGR_VCE_CONTROL_BASE_IDX 2 2116#define regMCIF_WB_NB_PSTATE_CONTROL 0x0293 2117#define regMCIF_WB_NB_PSTATE_CONTROL_BASE_IDX 2 2118#define regMCIF_WB_CLOCK_GATER_CONTROL 0x0294 2119#define regMCIF_WB_CLOCK_GATER_CONTROL_BASE_IDX 2 2120#define regMCIF_WB_SELF_REFRESH_CONTROL 0x0296 2121#define regMCIF_WB_SELF_REFRESH_CONTROL_BASE_IDX 2 2122#define regMULTI_LEVEL_QOS_CTRL 0x0297 2123#define regMULTI_LEVEL_QOS_CTRL_BASE_IDX 2 2124#define regMCIF_WB_SECURITY_LEVEL 0x0298 2125#define regMCIF_WB_SECURITY_LEVEL_BASE_IDX 2 2126#define regMCIF_WB_BUF_LUMA_SIZE 0x0299 2127#define regMCIF_WB_BUF_LUMA_SIZE_BASE_IDX 2 2128#define regMCIF_WB_BUF_CHROMA_SIZE 0x029a 2129#define regMCIF_WB_BUF_CHROMA_SIZE_BASE_IDX 2 2130#define regMCIF_WB_BUF_1_ADDR_Y_HIGH 0x029b 2131#define regMCIF_WB_BUF_1_ADDR_Y_HIGH_BASE_IDX 2 2132#define regMCIF_WB_BUF_1_ADDR_C_HIGH 0x029c 2133#define regMCIF_WB_BUF_1_ADDR_C_HIGH_BASE_IDX 2 2134#define regMCIF_WB_BUF_2_ADDR_Y_HIGH 0x029d 2135#define regMCIF_WB_BUF_2_ADDR_Y_HIGH_BASE_IDX 2 2136#define regMCIF_WB_BUF_2_ADDR_C_HIGH 0x029e 2137#define regMCIF_WB_BUF_2_ADDR_C_HIGH_BASE_IDX 2 2138#define regMCIF_WB_BUF_3_ADDR_Y_HIGH 0x029f 2139#define regMCIF_WB_BUF_3_ADDR_Y_HIGH_BASE_IDX 2 2140#define regMCIF_WB_BUF_3_ADDR_C_HIGH 0x02a0 2141#define regMCIF_WB_BUF_3_ADDR_C_HIGH_BASE_IDX 2 2142#define regMCIF_WB_BUF_4_ADDR_Y_HIGH 0x02a1 2143#define regMCIF_WB_BUF_4_ADDR_Y_HIGH_BASE_IDX 2 2144#define regMCIF_WB_BUF_4_ADDR_C_HIGH 0x02a2 2145#define regMCIF_WB_BUF_4_ADDR_C_HIGH_BASE_IDX 2 2146#define regMCIF_WB_BUF_1_RESOLUTION 0x02a3 2147#define regMCIF_WB_BUF_1_RESOLUTION_BASE_IDX 2 2148#define regMCIF_WB_BUF_2_RESOLUTION 0x02a4 2149#define regMCIF_WB_BUF_2_RESOLUTION_BASE_IDX 2 2150#define regMCIF_WB_BUF_3_RESOLUTION 0x02a5 2151#define regMCIF_WB_BUF_3_RESOLUTION_BASE_IDX 2 2152#define regMCIF_WB_BUF_4_RESOLUTION 0x02a6 2153#define regMCIF_WB_BUF_4_RESOLUTION_BASE_IDX 2 2154#define regMCIF_WB_PSTATE_CHANGE_DURATION_VBI 0x02a7 2155#define regMCIF_WB_PSTATE_CHANGE_DURATION_VBI_BASE_IDX 2 2156#define regMCIF_WB_VMID_CONTROL 0x02a8 2157#define regMCIF_WB_VMID_CONTROL_BASE_IDX 2 2158#define regMCIF_WB_MIN_TTO 0x02a9 2159#define regMCIF_WB_MIN_TTO_BASE_IDX 2 2160 2161 2162// addressBlock: dce_dc_mmhubbub_mmhubbub_dispdec 2163// base address: 0x0 2164#define regMCIF_WB_NB_PSTATE_LATENCY_WATERMARK 0x02aa 2165#define regMCIF_WB_NB_PSTATE_LATENCY_WATERMARK_BASE_IDX 2 2166#define regMCIF_WB_WATERMARK 0x02ab 2167#define regMCIF_WB_WATERMARK_BASE_IDX 2 2168#define regMMHUBBUB_WARMUP_CONFIG 0x02ac 2169#define regMMHUBBUB_WARMUP_CONFIG_BASE_IDX 2 2170#define regMMHUBBUB_WARMUP_CONTROL_STATUS 0x02ad 2171#define regMMHUBBUB_WARMUP_CONTROL_STATUS_BASE_IDX 2 2172#define regMMHUBBUB_WARMUP_BASE_ADDR_LOW 0x02ae 2173#define regMMHUBBUB_WARMUP_BASE_ADDR_LOW_BASE_IDX 2 2174#define regMMHUBBUB_WARMUP_BASE_ADDR_HIGH 0x02af 2175#define regMMHUBBUB_WARMUP_BASE_ADDR_HIGH_BASE_IDX 2 2176#define regMMHUBBUB_WARMUP_ADDR_REGION 0x02b0 2177#define regMMHUBBUB_WARMUP_ADDR_REGION_BASE_IDX 2 2178#define regMMHUBBUB_MIN_TTO 0x02b1 2179#define regMMHUBBUB_MIN_TTO_BASE_IDX 2 2180#define regMMHUBBUB_CTRL 0x0333 2181#define regMMHUBBUB_CTRL_BASE_IDX 2 2182#define regWBIF_SMU_WM_CONTROL 0x0334 2183#define regWBIF_SMU_WM_CONTROL_BASE_IDX 2 2184#define regWBIF0_MISC_CTRL 0x0335 2185#define regWBIF0_MISC_CTRL_BASE_IDX 2 2186#define regWBIF0_PHASE0_OUTSTANDING_COUNTER 0x0336 2187#define regWBIF0_PHASE0_OUTSTANDING_COUNTER_BASE_IDX 2 2188#define regWBIF0_PHASE1_OUTSTANDING_COUNTER 0x0337 2189#define regWBIF0_PHASE1_OUTSTANDING_COUNTER_BASE_IDX 2 2190#define regMMHUBBUB_MEM_PWR_STATUS 0x033e 2191#define regMMHUBBUB_MEM_PWR_STATUS_BASE_IDX 2 2192#define regMMHUBBUB_MEM_PWR_CNTL 0x033f 2193#define regMMHUBBUB_MEM_PWR_CNTL_BASE_IDX 2 2194#define regMMHUBBUB_CLOCK_CNTL 0x0340 2195#define regMMHUBBUB_CLOCK_CNTL_BASE_IDX 2 2196#define regMMHUBBUB_SOFT_RESET 0x0341 2197#define regMMHUBBUB_SOFT_RESET_BASE_IDX 2 2198#define regDMU_IF_ERR_STATUS 0x0345 2199#define regDMU_IF_ERR_STATUS_BASE_IDX 2 2200#define regMMHUBBUB_CLIENT_UNIT_ID 0x0346 2201#define regMMHUBBUB_CLIENT_UNIT_ID_BASE_IDX 2 2202#define regMMHUBBUB_WARMUP_VMID_CONTROL 0x0348 2203#define regMMHUBBUB_WARMUP_VMID_CONTROL_BASE_IDX 2 2204 2205 2206// addressBlock: dce_dc_mmhubbub_mmhubbub_dcperfmon_dc_perfmon_dispdec 2207// base address: 0xd48 2208#define regDC_PERFMON4_PERFCOUNTER_CNTL 0x0352 2209#define regDC_PERFMON4_PERFCOUNTER_CNTL_BASE_IDX 2 2210#define regDC_PERFMON4_PERFCOUNTER_CNTL2 0x0353 2211#define regDC_PERFMON4_PERFCOUNTER_CNTL2_BASE_IDX 2 2212#define regDC_PERFMON4_PERFCOUNTER_STATE 0x0354 2213#define regDC_PERFMON4_PERFCOUNTER_STATE_BASE_IDX 2 2214#define regDC_PERFMON4_PERFMON_CNTL 0x0355 2215#define regDC_PERFMON4_PERFMON_CNTL_BASE_IDX 2 2216#define regDC_PERFMON4_PERFMON_CNTL2 0x0356 2217#define regDC_PERFMON4_PERFMON_CNTL2_BASE_IDX 2 2218#define regDC_PERFMON4_PERFMON_CVALUE_INT_MISC 0x0357 2219#define regDC_PERFMON4_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 2220#define regDC_PERFMON4_PERFMON_CVALUE_LOW 0x0358 2221#define regDC_PERFMON4_PERFMON_CVALUE_LOW_BASE_IDX 2 2222#define regDC_PERFMON4_PERFMON_HI 0x0359 2223#define regDC_PERFMON4_PERFMON_HI_BASE_IDX 2 2224#define regDC_PERFMON4_PERFMON_LOW 0x035a 2225#define regDC_PERFMON4_PERFMON_LOW_BASE_IDX 2 2226 2227 2228 2229 2230// addressBlock: dce_dc_hda_azf0stream0_dispdec 2231// base address: 0x0 2232#define regAZF0STREAM0_AZALIA_STREAM_INDEX 0x035e 2233#define regAZF0STREAM0_AZALIA_STREAM_INDEX_BASE_IDX 2 2234#define regAZF0STREAM0_AZALIA_STREAM_DATA 0x035f 2235#define regAZF0STREAM0_AZALIA_STREAM_DATA_BASE_IDX 2 2236 2237 2238// addressBlock: dce_dc_hda_azf0stream1_dispdec 2239// base address: 0x8 2240#define regAZF0STREAM1_AZALIA_STREAM_INDEX 0x0360 2241#define regAZF0STREAM1_AZALIA_STREAM_INDEX_BASE_IDX 2 2242#define regAZF0STREAM1_AZALIA_STREAM_DATA 0x0361 2243#define regAZF0STREAM1_AZALIA_STREAM_DATA_BASE_IDX 2 2244 2245 2246// addressBlock: dce_dc_hda_azf0stream2_dispdec 2247// base address: 0x10 2248#define regAZF0STREAM2_AZALIA_STREAM_INDEX 0x0362 2249#define regAZF0STREAM2_AZALIA_STREAM_INDEX_BASE_IDX 2 2250#define regAZF0STREAM2_AZALIA_STREAM_DATA 0x0363 2251#define regAZF0STREAM2_AZALIA_STREAM_DATA_BASE_IDX 2 2252 2253 2254// addressBlock: dce_dc_hda_azf0stream3_dispdec 2255// base address: 0x18 2256#define regAZF0STREAM3_AZALIA_STREAM_INDEX 0x0364 2257#define regAZF0STREAM3_AZALIA_STREAM_INDEX_BASE_IDX 2 2258#define regAZF0STREAM3_AZALIA_STREAM_DATA 0x0365 2259#define regAZF0STREAM3_AZALIA_STREAM_DATA_BASE_IDX 2 2260 2261 2262// addressBlock: dce_dc_hda_azf0stream4_dispdec 2263// base address: 0x20 2264#define regAZF0STREAM4_AZALIA_STREAM_INDEX 0x0366 2265#define regAZF0STREAM4_AZALIA_STREAM_INDEX_BASE_IDX 2 2266#define regAZF0STREAM4_AZALIA_STREAM_DATA 0x0367 2267#define regAZF0STREAM4_AZALIA_STREAM_DATA_BASE_IDX 2 2268 2269 2270// addressBlock: dce_dc_hda_azf0stream5_dispdec 2271// base address: 0x28 2272#define regAZF0STREAM5_AZALIA_STREAM_INDEX 0x0368 2273#define regAZF0STREAM5_AZALIA_STREAM_INDEX_BASE_IDX 2 2274#define regAZF0STREAM5_AZALIA_STREAM_DATA 0x0369 2275#define regAZF0STREAM5_AZALIA_STREAM_DATA_BASE_IDX 2 2276 2277 2278// addressBlock: dce_dc_hda_azf0stream6_dispdec 2279// base address: 0x30 2280#define regAZF0STREAM6_AZALIA_STREAM_INDEX 0x036a 2281#define regAZF0STREAM6_AZALIA_STREAM_INDEX_BASE_IDX 2 2282#define regAZF0STREAM6_AZALIA_STREAM_DATA 0x036b 2283#define regAZF0STREAM6_AZALIA_STREAM_DATA_BASE_IDX 2 2284 2285 2286// addressBlock: dce_dc_hda_azf0stream7_dispdec 2287// base address: 0x38 2288#define regAZF0STREAM7_AZALIA_STREAM_INDEX 0x036c 2289#define regAZF0STREAM7_AZALIA_STREAM_INDEX_BASE_IDX 2 2290#define regAZF0STREAM7_AZALIA_STREAM_DATA 0x036d 2291#define regAZF0STREAM7_AZALIA_STREAM_DATA_BASE_IDX 2 2292 2293 2294// addressBlock: dce_dc_hda_az_misc_dispdec 2295// base address: 0x0 2296#define regAZ_CLOCK_CNTL 0x0372 2297#define regAZ_CLOCK_CNTL_BASE_IDX 2 2298#define regAZ_MEM_GLOBAL_PWR_REQ_CNTL 0x0373 2299#define regAZ_MEM_GLOBAL_PWR_REQ_CNTL_BASE_IDX 2 2300 2301// addressBlock: dce_dc_hda_az_dcperfmon_dc_perfmon_dispdec 2302// base address: 0xde8 2303#define regDC_PERFMON5_PERFCOUNTER_CNTL 0x037a 2304#define regDC_PERFMON5_PERFCOUNTER_CNTL_BASE_IDX 2 2305#define regDC_PERFMON5_PERFCOUNTER_CNTL2 0x037b 2306#define regDC_PERFMON5_PERFCOUNTER_CNTL2_BASE_IDX 2 2307#define regDC_PERFMON5_PERFCOUNTER_STATE 0x037c 2308#define regDC_PERFMON5_PERFCOUNTER_STATE_BASE_IDX 2 2309#define regDC_PERFMON5_PERFMON_CNTL 0x037d 2310#define regDC_PERFMON5_PERFMON_CNTL_BASE_IDX 2 2311#define regDC_PERFMON5_PERFMON_CNTL2 0x037e 2312#define regDC_PERFMON5_PERFMON_CNTL2_BASE_IDX 2 2313#define regDC_PERFMON5_PERFMON_CVALUE_INT_MISC 0x037f 2314#define regDC_PERFMON5_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 2315#define regDC_PERFMON5_PERFMON_CVALUE_LOW 0x0380 2316#define regDC_PERFMON5_PERFMON_CVALUE_LOW_BASE_IDX 2 2317#define regDC_PERFMON5_PERFMON_HI 0x0381 2318#define regDC_PERFMON5_PERFMON_HI_BASE_IDX 2 2319#define regDC_PERFMON5_PERFMON_LOW 0x0382 2320#define regDC_PERFMON5_PERFMON_LOW_BASE_IDX 2 2321 2322 2323 2324// addressBlock: dce_dc_hda_azf0endpoint0_dispdec 2325// base address: 0x0 2326#define regAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x0386 2327#define regAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 2328#define regAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA 0x0387 2329#define regAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 2330 2331 2332// addressBlock: dce_dc_hda_azf0endpoint1_dispdec 2333// base address: 0x18 2334#define regAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x038c 2335#define regAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 2336#define regAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA 0x038d 2337#define regAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 2338 2339 2340// addressBlock: dce_dc_hda_azf0endpoint2_dispdec 2341// base address: 0x30 2342#define regAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x0392 2343#define regAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 2344#define regAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA 0x0393 2345#define regAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 2346 2347 2348// addressBlock: dce_dc_hda_azf0endpoint3_dispdec 2349// base address: 0x48 2350#define regAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x0398 2351#define regAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 2352#define regAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA 0x0399 2353#define regAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 2354 2355 2356// addressBlock: dce_dc_hda_azf0endpoint4_dispdec 2357// base address: 0x60 2358#define regAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x039e 2359#define regAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 2360#define regAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA 0x039f 2361#define regAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 2362 2363 2364// addressBlock: dce_dc_hda_azf0endpoint5_dispdec 2365// base address: 0x78 2366#define regAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x03a4 2367#define regAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 2368#define regAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA 0x03a5 2369#define regAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 2370 2371 2372// addressBlock: dce_dc_hda_azf0endpoint6_dispdec 2373// base address: 0x90 2374#define regAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x03aa 2375#define regAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 2376#define regAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA 0x03ab 2377#define regAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 2378 2379 2380// addressBlock: dce_dc_hda_azf0endpoint7_dispdec 2381// base address: 0xa8 2382#define regAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x03b0 2383#define regAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 2384#define regAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA 0x03b1 2385#define regAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 2386 2387 2388// addressBlock: dce_dc_hda_azf0controller_dispdec 2389// base address: 0x0 2390#define regAZALIA_CONTROLLER_CLOCK_GATING 0x03c2 2391#define regAZALIA_CONTROLLER_CLOCK_GATING_BASE_IDX 2 2392#define regAZALIA_AUDIO_DTO 0x03c3 2393#define regAZALIA_AUDIO_DTO_BASE_IDX 2 2394#define regAZALIA_AUDIO_DTO_CONTROL 0x03c4 2395#define regAZALIA_AUDIO_DTO_CONTROL_BASE_IDX 2 2396#define regAZALIA_SOCCLK_CONTROL 0x03c5 2397#define regAZALIA_SOCCLK_CONTROL_BASE_IDX 2 2398#define regAZALIA_UNDERFLOW_FILLER_SAMPLE 0x03c6 2399#define regAZALIA_UNDERFLOW_FILLER_SAMPLE_BASE_IDX 2 2400#define regAZALIA_DATA_DMA_CONTROL 0x03c7 2401#define regAZALIA_DATA_DMA_CONTROL_BASE_IDX 2 2402#define regAZALIA_BDL_DMA_CONTROL 0x03c8 2403#define regAZALIA_BDL_DMA_CONTROL_BASE_IDX 2 2404#define regAZALIA_RIRB_AND_DP_CONTROL 0x03c9 2405#define regAZALIA_RIRB_AND_DP_CONTROL_BASE_IDX 2 2406#define regAZALIA_CORB_DMA_CONTROL 0x03ca 2407#define regAZALIA_CORB_DMA_CONTROL_BASE_IDX 2 2408#define regAZALIA_GLOBAL_CAPABILITIES 0x03d3 2409#define regAZALIA_GLOBAL_CAPABILITIES_BASE_IDX 2 2410#define regAZALIA_OUTPUT_PAYLOAD_CAPABILITY 0x03d4 2411#define regAZALIA_OUTPUT_PAYLOAD_CAPABILITY_BASE_IDX 2 2412#define regAZALIA_OUTPUT_STREAM_ARBITER_CONTROL 0x03d5 2413#define regAZALIA_OUTPUT_STREAM_ARBITER_CONTROL_BASE_IDX 2 2414#define regAZALIA_INPUT_PAYLOAD_CAPABILITY 0x03d6 2415#define regAZALIA_INPUT_PAYLOAD_CAPABILITY_BASE_IDX 2 2416#define regAZALIA_INPUT_CRC0_CONTROL0 0x03d9 2417#define regAZALIA_INPUT_CRC0_CONTROL0_BASE_IDX 2 2418#define regAZALIA_INPUT_CRC0_CONTROL1 0x03da 2419#define regAZALIA_INPUT_CRC0_CONTROL1_BASE_IDX 2 2420#define regAZALIA_INPUT_CRC0_CONTROL2 0x03db 2421#define regAZALIA_INPUT_CRC0_CONTROL2_BASE_IDX 2 2422#define regAZALIA_INPUT_CRC0_CONTROL3 0x03dc 2423#define regAZALIA_INPUT_CRC0_CONTROL3_BASE_IDX 2 2424#define regAZALIA_INPUT_CRC0_RESULT 0x03dd 2425#define regAZALIA_INPUT_CRC0_RESULT_BASE_IDX 2 2426#define regAZALIA_INPUT_CRC1_CONTROL0 0x03de 2427#define regAZALIA_INPUT_CRC1_CONTROL0_BASE_IDX 2 2428#define regAZALIA_INPUT_CRC1_CONTROL1 0x03df 2429#define regAZALIA_INPUT_CRC1_CONTROL1_BASE_IDX 2 2430#define regAZALIA_INPUT_CRC1_CONTROL2 0x03e0 2431#define regAZALIA_INPUT_CRC1_CONTROL2_BASE_IDX 2 2432#define regAZALIA_INPUT_CRC1_CONTROL3 0x03e1 2433#define regAZALIA_INPUT_CRC1_CONTROL3_BASE_IDX 2 2434#define regAZALIA_INPUT_CRC1_RESULT 0x03e2 2435#define regAZALIA_INPUT_CRC1_RESULT_BASE_IDX 2 2436#define regAZALIA_CRC0_CONTROL0 0x03e3 2437#define regAZALIA_CRC0_CONTROL0_BASE_IDX 2 2438#define regAZALIA_CRC0_CONTROL1 0x03e4 2439#define regAZALIA_CRC0_CONTROL1_BASE_IDX 2 2440#define regAZALIA_CRC0_CONTROL2 0x03e5 2441#define regAZALIA_CRC0_CONTROL2_BASE_IDX 2 2442#define regAZALIA_CRC0_CONTROL3 0x03e6 2443#define regAZALIA_CRC0_CONTROL3_BASE_IDX 2 2444#define regAZALIA_CRC0_RESULT 0x03e7 2445#define regAZALIA_CRC0_RESULT_BASE_IDX 2 2446#define regAZALIA_CRC1_CONTROL0 0x03e8 2447#define regAZALIA_CRC1_CONTROL0_BASE_IDX 2 2448#define regAZALIA_CRC1_CONTROL1 0x03e9 2449#define regAZALIA_CRC1_CONTROL1_BASE_IDX 2 2450#define regAZALIA_CRC1_CONTROL2 0x03ea 2451#define regAZALIA_CRC1_CONTROL2_BASE_IDX 2 2452#define regAZALIA_CRC1_CONTROL3 0x03eb 2453#define regAZALIA_CRC1_CONTROL3_BASE_IDX 2 2454#define regAZALIA_CRC1_RESULT 0x03ec 2455#define regAZALIA_CRC1_RESULT_BASE_IDX 2 2456#define regAZALIA_MEM_PWR_CTRL 0x03ee 2457#define regAZALIA_MEM_PWR_CTRL_BASE_IDX 2 2458#define regAZALIA_MEM_PWR_STATUS 0x03ef 2459#define regAZALIA_MEM_PWR_STATUS_BASE_IDX 2 2460 2461 2462 2463// addressBlock: dce_dc_hda_azf0root_dispdec 2464// base address: 0x0 2465#define regAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID 0x0406 2466#define regAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_BASE_IDX 2 2467#define regAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID 0x0407 2468#define regAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID_BASE_IDX 2 2469#define regAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL 0x0408 2470#define regAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL_BASE_IDX 2 2471#define regAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL 0x0409 2472#define regAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL_BASE_IDX 2 2473#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE 0x040a 2474#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_BASE_IDX 2 2475#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES 0x040b 2476#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES_BASE_IDX 2 2477#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS 0x040c 2478#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_BASE_IDX 2 2479#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES 0x040d 2480#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES_BASE_IDX 2 2481#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE 0x040e 2482#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE_BASE_IDX 2 2483#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET 0x040f 2484#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET_BASE_IDX 2 2485#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID 0x0410 2486#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_BASE_IDX 2 2487#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION 0x0411 2488#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION_BASE_IDX 2 2489#define regCC_RCU_DC_AUDIO_PORT_CONNECTIVITY 0x0412 2490#define regCC_RCU_DC_AUDIO_PORT_CONNECTIVITY_BASE_IDX 2 2491#define regCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY 0x0413 2492#define regCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_BASE_IDX 2 2493#define regAZALIA_F0_GTC_GROUP_OFFSET0 0x0415 2494#define regAZALIA_F0_GTC_GROUP_OFFSET0_BASE_IDX 2 2495#define regAZALIA_F0_GTC_GROUP_OFFSET1 0x0416 2496#define regAZALIA_F0_GTC_GROUP_OFFSET1_BASE_IDX 2 2497#define regAZALIA_F0_GTC_GROUP_OFFSET2 0x0417 2498#define regAZALIA_F0_GTC_GROUP_OFFSET2_BASE_IDX 2 2499#define regAZALIA_F0_GTC_GROUP_OFFSET3 0x0418 2500#define regAZALIA_F0_GTC_GROUP_OFFSET3_BASE_IDX 2 2501#define regAZALIA_F0_GTC_GROUP_OFFSET4 0x0419 2502#define regAZALIA_F0_GTC_GROUP_OFFSET4_BASE_IDX 2 2503#define regAZALIA_F0_GTC_GROUP_OFFSET5 0x041a 2504#define regAZALIA_F0_GTC_GROUP_OFFSET5_BASE_IDX 2 2505#define regAZALIA_F0_GTC_GROUP_OFFSET6 0x041b 2506#define regAZALIA_F0_GTC_GROUP_OFFSET6_BASE_IDX 2 2507#define regREG_DC_AUDIO_PORT_CONNECTIVITY 0x041c 2508#define regREG_DC_AUDIO_PORT_CONNECTIVITY_BASE_IDX 2 2509#define regREG_DC_AUDIO_INPUT_PORT_CONNECTIVITY 0x041d 2510#define regREG_DC_AUDIO_INPUT_PORT_CONNECTIVITY_BASE_IDX 2 2511 2512 2513 2514// addressBlock: dce_dc_hda_azf0stream8_dispdec 2515// base address: 0x320 2516#define regAZF0STREAM8_AZALIA_STREAM_INDEX 0x0426 2517#define regAZF0STREAM8_AZALIA_STREAM_INDEX_BASE_IDX 2 2518#define regAZF0STREAM8_AZALIA_STREAM_DATA 0x0427 2519#define regAZF0STREAM8_AZALIA_STREAM_DATA_BASE_IDX 2 2520 2521 2522// addressBlock: dce_dc_hda_azf0stream9_dispdec 2523// base address: 0x328 2524#define regAZF0STREAM9_AZALIA_STREAM_INDEX 0x0428 2525#define regAZF0STREAM9_AZALIA_STREAM_INDEX_BASE_IDX 2 2526#define regAZF0STREAM9_AZALIA_STREAM_DATA 0x0429 2527#define regAZF0STREAM9_AZALIA_STREAM_DATA_BASE_IDX 2 2528 2529 2530// addressBlock: dce_dc_hda_azf0stream10_dispdec 2531// base address: 0x330 2532#define regAZF0STREAM10_AZALIA_STREAM_INDEX 0x042a 2533#define regAZF0STREAM10_AZALIA_STREAM_INDEX_BASE_IDX 2 2534#define regAZF0STREAM10_AZALIA_STREAM_DATA 0x042b 2535#define regAZF0STREAM10_AZALIA_STREAM_DATA_BASE_IDX 2 2536 2537 2538// addressBlock: dce_dc_hda_azf0stream11_dispdec 2539// base address: 0x338 2540#define regAZF0STREAM11_AZALIA_STREAM_INDEX 0x042c 2541#define regAZF0STREAM11_AZALIA_STREAM_INDEX_BASE_IDX 2 2542#define regAZF0STREAM11_AZALIA_STREAM_DATA 0x042d 2543#define regAZF0STREAM11_AZALIA_STREAM_DATA_BASE_IDX 2 2544 2545 2546// addressBlock: dce_dc_hda_azf0stream12_dispdec 2547// base address: 0x340 2548#define regAZF0STREAM12_AZALIA_STREAM_INDEX 0x042e 2549#define regAZF0STREAM12_AZALIA_STREAM_INDEX_BASE_IDX 2 2550#define regAZF0STREAM12_AZALIA_STREAM_DATA 0x042f 2551#define regAZF0STREAM12_AZALIA_STREAM_DATA_BASE_IDX 2 2552 2553 2554// addressBlock: dce_dc_hda_azf0stream13_dispdec 2555// base address: 0x348 2556#define regAZF0STREAM13_AZALIA_STREAM_INDEX 0x0430 2557#define regAZF0STREAM13_AZALIA_STREAM_INDEX_BASE_IDX 2 2558#define regAZF0STREAM13_AZALIA_STREAM_DATA 0x0431 2559#define regAZF0STREAM13_AZALIA_STREAM_DATA_BASE_IDX 2 2560 2561 2562// addressBlock: dce_dc_hda_azf0stream14_dispdec 2563// base address: 0x350 2564#define regAZF0STREAM14_AZALIA_STREAM_INDEX 0x0432 2565#define regAZF0STREAM14_AZALIA_STREAM_INDEX_BASE_IDX 2 2566#define regAZF0STREAM14_AZALIA_STREAM_DATA 0x0433 2567#define regAZF0STREAM14_AZALIA_STREAM_DATA_BASE_IDX 2 2568 2569 2570// addressBlock: dce_dc_hda_azf0stream15_dispdec 2571// base address: 0x358 2572#define regAZF0STREAM15_AZALIA_STREAM_INDEX 0x0434 2573#define regAZF0STREAM15_AZALIA_STREAM_INDEX_BASE_IDX 2 2574#define regAZF0STREAM15_AZALIA_STREAM_DATA 0x0435 2575#define regAZF0STREAM15_AZALIA_STREAM_DATA_BASE_IDX 2 2576 2577 2578 2579// addressBlock: dce_dc_hda_azf0inputendpoint0_dispdec 2580// base address: 0x0 2581#define regAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x043a 2582#define regAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 2583#define regAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x043b 2584#define regAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 2585 2586 2587// addressBlock: dce_dc_hda_azf0inputendpoint1_dispdec 2588// base address: 0x10 2589#define regAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x043e 2590#define regAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 2591#define regAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x043f 2592#define regAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 2593 2594 2595// addressBlock: dce_dc_hda_azf0inputendpoint2_dispdec 2596// base address: 0x20 2597#define regAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0442 2598#define regAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 2599#define regAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0443 2600#define regAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 2601 2602 2603// addressBlock: dce_dc_hda_azf0inputendpoint3_dispdec 2604// base address: 0x30 2605#define regAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0446 2606#define regAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 2607#define regAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0447 2608#define regAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 2609 2610 2611// addressBlock: dce_dc_hda_azf0inputendpoint4_dispdec 2612// base address: 0x40 2613#define regAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x044a 2614#define regAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 2615#define regAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x044b 2616#define regAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 2617 2618 2619// addressBlock: dce_dc_hda_azf0inputendpoint5_dispdec 2620// base address: 0x50 2621#define regAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x044e 2622#define regAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 2623#define regAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x044f 2624#define regAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 2625 2626 2627// addressBlock: dce_dc_hda_azf0inputendpoint6_dispdec 2628// base address: 0x60 2629#define regAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0452 2630#define regAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 2631#define regAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0453 2632#define regAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 2633 2634 2635// addressBlock: dce_dc_hda_azf0inputendpoint7_dispdec 2636// base address: 0x70 2637#define regAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0456 2638#define regAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 2639#define regAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0457 2640#define regAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 2641 2642 2643 2644// addressBlock: dce_dc_dchubbubl_hubbub_sdpif_dispdec 2645// base address: 0x0 2646#define regDCHUBBUB_SDPIF_CFG0 0x046f 2647#define regDCHUBBUB_SDPIF_CFG0_BASE_IDX 2 2648#define regDCHUBBUB_SDPIF_CFG1 0x0470 2649#define regDCHUBBUB_SDPIF_CFG1_BASE_IDX 2 2650#define regDCHUBBUB_SDPIF_CFG2 0x0471 2651#define regDCHUBBUB_SDPIF_CFG2_BASE_IDX 2 2652#define regVM_REQUEST_PHYSICAL 0x0472 2653#define regVM_REQUEST_PHYSICAL_BASE_IDX 2 2654#define regDCHUBBUB_FORCE_IO_STATUS_0 0x0473 2655#define regDCHUBBUB_FORCE_IO_STATUS_0_BASE_IDX 2 2656#define regDCHUBBUB_FORCE_IO_STATUS_1 0x0474 2657#define regDCHUBBUB_FORCE_IO_STATUS_1_BASE_IDX 2 2658#define regDCN_VM_FB_LOCATION_BASE 0x0475 2659#define regDCN_VM_FB_LOCATION_BASE_BASE_IDX 2 2660#define regDCN_VM_FB_LOCATION_TOP 0x0476 2661#define regDCN_VM_FB_LOCATION_TOP_BASE_IDX 2 2662#define regDCN_VM_FB_OFFSET 0x0477 2663#define regDCN_VM_FB_OFFSET_BASE_IDX 2 2664#define regDCN_VM_AGP_BOT 0x0478 2665#define regDCN_VM_AGP_BOT_BASE_IDX 2 2666#define regDCN_VM_AGP_TOP 0x0479 2667#define regDCN_VM_AGP_TOP_BASE_IDX 2 2668#define regDCN_VM_AGP_BASE 0x047a 2669#define regDCN_VM_AGP_BASE_BASE_IDX 2 2670#define regDCN_VM_LOCAL_HBM_ADDRESS_START 0x047b 2671#define regDCN_VM_LOCAL_HBM_ADDRESS_START_BASE_IDX 2 2672#define regDCN_VM_LOCAL_HBM_ADDRESS_END 0x047c 2673#define regDCN_VM_LOCAL_HBM_ADDRESS_END_BASE_IDX 2 2674#define regDCN_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL 0x047d 2675#define regDCN_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL_BASE_IDX 2 2676#define regDCHUBBUB_SDPIF_PIPE_SEC_LVL 0x047e 2677#define regDCHUBBUB_SDPIF_PIPE_SEC_LVL_BASE_IDX 2 2678#define regDCHUBBUB_SDPIF_PIPE_NOALLOC 0x047f 2679#define regDCHUBBUB_SDPIF_PIPE_NOALLOC_BASE_IDX 2 2680#define regDCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL 0x0480 2681#define regDCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL_BASE_IDX 2 2682#define regDCHUBBUB_SDPIF_PIPE_DCCMETA_SEC_LVL 0x0481 2683#define regDCHUBBUB_SDPIF_PIPE_DCCMETA_SEC_LVL_BASE_IDX 2 2684#define regDCHUBBUB_SDPIF_PIPE_CURSOR0_SEC_LVL 0x0482 2685#define regDCHUBBUB_SDPIF_PIPE_CURSOR0_SEC_LVL_BASE_IDX 2 2686#define regDCHUBBUB_SDPIF_PIPE_GPUVM_SEC_LVL 0x0483 2687#define regDCHUBBUB_SDPIF_PIPE_GPUVM_SEC_LVL_BASE_IDX 2 2688#define regSDPIF_REQUEST_RATE_LIMIT 0x0484 2689#define regSDPIF_REQUEST_RATE_LIMIT_BASE_IDX 2 2690#define regDCHUBBUB_SDPIF_MEM_PWR_CTRL 0x0485 2691#define regDCHUBBUB_SDPIF_MEM_PWR_CTRL_BASE_IDX 2 2692#define regDCHUBBUB_SDPIF_MEM_PWR_STATUS 0x0486 2693#define regDCHUBBUB_SDPIF_MEM_PWR_STATUS_BASE_IDX 2 2694 2695 2696// addressBlock: dce_dc_dchubbubl_hubbub_ret_path_dispdec 2697// base address: 0x0 2698#define regDCHUBBUB_RET_PATH_MEM_PWR_CTRL 0x04af 2699#define regDCHUBBUB_RET_PATH_MEM_PWR_CTRL_BASE_IDX 2 2700#define regDCHUBBUB_RET_PATH_MEM_PWR_STATUS 0x04b0 2701#define regDCHUBBUB_RET_PATH_MEM_PWR_STATUS_BASE_IDX 2 2702#define regDCHUBBUB_CRC_CTRL 0x04b1 2703#define regDCHUBBUB_CRC_CTRL_BASE_IDX 2 2704#define regDCHUBBUB_CRC0_VAL_R_G 0x04b2 2705#define regDCHUBBUB_CRC0_VAL_R_G_BASE_IDX 2 2706#define regDCHUBBUB_CRC0_VAL_B_A 0x04b3 2707#define regDCHUBBUB_CRC0_VAL_B_A_BASE_IDX 2 2708#define regDCHUBBUB_CRC1_VAL_R_G 0x04b4 2709#define regDCHUBBUB_CRC1_VAL_R_G_BASE_IDX 2 2710#define regDCHUBBUB_CRC1_VAL_B_A 0x04b5 2711#define regDCHUBBUB_CRC1_VAL_B_A_BASE_IDX 2 2712#define regDCHUBBUB_DCC_STAT_CNTL 0x04b6 2713#define regDCHUBBUB_DCC_STAT_CNTL_BASE_IDX 2 2714#define regDCHUBBUB_DCC_STAT0 0x04b7 2715#define regDCHUBBUB_DCC_STAT0_BASE_IDX 2 2716#define regDCHUBBUB_DCC_STAT1 0x04b8 2717#define regDCHUBBUB_DCC_STAT1_BASE_IDX 2 2718#define regDCHUBBUB_DCC_STAT2 0x04b9 2719#define regDCHUBBUB_DCC_STAT2_BASE_IDX 2 2720#define regDCHUBBUB_COMPBUF_CTRL 0x04ba 2721#define regDCHUBBUB_COMPBUF_CTRL_BASE_IDX 2 2722#define regDCHUBBUB_DET0_CTRL 0x04bb 2723#define regDCHUBBUB_DET0_CTRL_BASE_IDX 2 2724#define regDCHUBBUB_DET1_CTRL 0x04bc 2725#define regDCHUBBUB_DET1_CTRL_BASE_IDX 2 2726#define regDCHUBBUB_DET2_CTRL 0x04bd 2727#define regDCHUBBUB_DET2_CTRL_BASE_IDX 2 2728#define regDCHUBBUB_DET3_CTRL 0x04be 2729#define regDCHUBBUB_DET3_CTRL_BASE_IDX 2 2730#define regDCHUBBUB_MEM_PWR_MODE_CTRL 0x04c0 2731#define regDCHUBBUB_MEM_PWR_MODE_CTRL_BASE_IDX 2 2732#define regCOMPBUF_MEM_PWR_CTRL_1 0x04c1 2733#define regCOMPBUF_MEM_PWR_CTRL_1_BASE_IDX 2 2734#define regCOMPBUF_MEM_PWR_CTRL_2 0x04c2 2735#define regCOMPBUF_MEM_PWR_CTRL_2_BASE_IDX 2 2736#define regDCHUBBUB_MEM_PWR_STATUS 0x04c3 2737#define regDCHUBBUB_MEM_PWR_STATUS_BASE_IDX 2 2738#define regCOMPBUF_RESERVED_SPACE 0x04c4 2739#define regCOMPBUF_RESERVED_SPACE_BASE_IDX 2 2740#define regDCHUBBUB_DEBUG_CTRL_0 0x04c5 2741#define regDCHUBBUB_DEBUG_CTRL_0_BASE_IDX 2 2742 2743 2744// addressBlock: dce_dc_dchubbubl_hubbub_dispdec 2745// base address: 0x0 2746#define regDCHUBBUB_ARB_DF_REQ_OUTSTAND 0x04f9 2747#define regDCHUBBUB_ARB_DF_REQ_OUTSTAND_BASE_IDX 2 2748#define regDCHUBBUB_ARB_SAT_LEVEL 0x04fa 2749#define regDCHUBBUB_ARB_SAT_LEVEL_BASE_IDX 2 2750#define regDCHUBBUB_ARB_QOS_FORCE 0x04fb 2751#define regDCHUBBUB_ARB_QOS_FORCE_BASE_IDX 2 2752#define regDCHUBBUB_ARB_DRAM_STATE_CNTL 0x04fc 2753#define regDCHUBBUB_ARB_DRAM_STATE_CNTL_BASE_IDX 2 2754#define regDCHUBBUB_ARB_USR_RETRAINING_CNTL 0x04fd 2755#define regDCHUBBUB_ARB_USR_RETRAINING_CNTL_BASE_IDX 2 2756#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A 0x04fe 2757#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A_BASE_IDX 2 2758#define regDCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A 0x04ff 2759#define regDCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A_BASE_IDX 2 2760#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A 0x0500 2761#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A_BASE_IDX 2 2762#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A 0x0501 2763#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A_BASE_IDX 2 2764#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_A 0x0502 2765#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_A_BASE_IDX 2 2766#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A 0x0503 2767#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A_BASE_IDX 2 2768#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_A 0x0504 2769#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_A_BASE_IDX 2 2770#define regDCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A 0x0505 2771#define regDCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A_BASE_IDX 2 2772#define regDCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A 0x0506 2773#define regDCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A_BASE_IDX 2 2774#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_A 0x0507 2775#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_A_BASE_IDX 2 2776#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_A 0x0508 2777#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_A_BASE_IDX 2 2778#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B 0x0509 2779#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B_BASE_IDX 2 2780#define regDCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B 0x050a 2781#define regDCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B_BASE_IDX 2 2782#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B 0x050b 2783#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B_BASE_IDX 2 2784#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B 0x050c 2785#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B_BASE_IDX 2 2786#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_B 0x050d 2787#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_B_BASE_IDX 2 2788#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B 0x050e 2789#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B_BASE_IDX 2 2790#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_B 0x050f 2791#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_B_BASE_IDX 2 2792#define regDCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B 0x0510 2793#define regDCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B_BASE_IDX 2 2794#define regDCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B 0x0511 2795#define regDCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B_BASE_IDX 2 2796#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_B 0x0512 2797#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_B_BASE_IDX 2 2798#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_B 0x0513 2799#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_B_BASE_IDX 2 2800#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C 0x0514 2801#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C_BASE_IDX 2 2802#define regDCHUBBUB_ARB_USR_RETRAINING_WATERMARK_C 0x0515 2803#define regDCHUBBUB_ARB_USR_RETRAINING_WATERMARK_C_BASE_IDX 2 2804#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C 0x0516 2805#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C_BASE_IDX 2 2806#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C 0x0517 2807#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C_BASE_IDX 2 2808#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_C 0x0518 2809#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_C_BASE_IDX 2 2810#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C 0x0519 2811#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C_BASE_IDX 2 2812#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_C 0x051a 2813#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_C_BASE_IDX 2 2814#define regDCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_C 0x051b 2815#define regDCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_C_BASE_IDX 2 2816#define regDCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_C 0x051c 2817#define regDCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_C_BASE_IDX 2 2818#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_C 0x051d 2819#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_C_BASE_IDX 2 2820#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_C 0x051e 2821#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_C_BASE_IDX 2 2822#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D 0x051f 2823#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D_BASE_IDX 2 2824#define regDCHUBBUB_ARB_USR_RETRAINING_WATERMARK_D 0x0520 2825#define regDCHUBBUB_ARB_USR_RETRAINING_WATERMARK_D_BASE_IDX 2 2826#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D 0x0521 2827#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D_BASE_IDX 2 2828#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D 0x0522 2829#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D_BASE_IDX 2 2830#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_D 0x0523 2831#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_D_BASE_IDX 2 2832#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D 0x0524 2833#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D_BASE_IDX 2 2834#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_D 0x0525 2835#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_D_BASE_IDX 2 2836#define regDCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_D 0x0526 2837#define regDCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_D_BASE_IDX 2 2838#define regDCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_D 0x0527 2839#define regDCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_D_BASE_IDX 2 2840#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_D 0x0528 2841#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_D_BASE_IDX 2 2842#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_D 0x0529 2843#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_D_BASE_IDX 2 2844#define regDCHUBBUB_ARB_HOSTVM_CNTL 0x052a 2845#define regDCHUBBUB_ARB_HOSTVM_CNTL_BASE_IDX 2 2846#define regDCHUBBUB_ARB_WATERMARK_CHANGE_CNTL 0x052b 2847#define regDCHUBBUB_ARB_WATERMARK_CHANGE_CNTL_BASE_IDX 2 2848#define regDCHUBBUB_ARB_MALL_CNTL 0x052c 2849#define regDCHUBBUB_ARB_MALL_CNTL_BASE_IDX 2 2850#define regDCHUBBUB_ARB_TIMEOUT_ENABLE 0x052d 2851#define regDCHUBBUB_ARB_TIMEOUT_ENABLE_BASE_IDX 2 2852#define regDCHUBBUB_GLOBAL_TIMER_CNTL 0x052e 2853#define regDCHUBBUB_GLOBAL_TIMER_CNTL_BASE_IDX 2 2854#define regSURFACE_CHECK0_ADDRESS_LSB 0x052f 2855#define regSURFACE_CHECK0_ADDRESS_LSB_BASE_IDX 2 2856#define regSURFACE_CHECK0_ADDRESS_MSB 0x0530 2857#define regSURFACE_CHECK0_ADDRESS_MSB_BASE_IDX 2 2858#define regSURFACE_CHECK1_ADDRESS_LSB 0x0531 2859#define regSURFACE_CHECK1_ADDRESS_LSB_BASE_IDX 2 2860#define regSURFACE_CHECK1_ADDRESS_MSB 0x0532 2861#define regSURFACE_CHECK1_ADDRESS_MSB_BASE_IDX 2 2862#define regSURFACE_CHECK2_ADDRESS_LSB 0x0533 2863#define regSURFACE_CHECK2_ADDRESS_LSB_BASE_IDX 2 2864#define regSURFACE_CHECK2_ADDRESS_MSB 0x0534 2865#define regSURFACE_CHECK2_ADDRESS_MSB_BASE_IDX 2 2866#define regSURFACE_CHECK3_ADDRESS_LSB 0x0535 2867#define regSURFACE_CHECK3_ADDRESS_LSB_BASE_IDX 2 2868#define regSURFACE_CHECK3_ADDRESS_MSB 0x0536 2869#define regSURFACE_CHECK3_ADDRESS_MSB_BASE_IDX 2 2870#define regVTG0_CONTROL 0x0537 2871#define regVTG0_CONTROL_BASE_IDX 2 2872#define regVTG1_CONTROL 0x0538 2873#define regVTG1_CONTROL_BASE_IDX 2 2874#define regVTG2_CONTROL 0x0539 2875#define regVTG2_CONTROL_BASE_IDX 2 2876#define regVTG3_CONTROL 0x053a 2877#define regVTG3_CONTROL_BASE_IDX 2 2878#define regDCHUBBUB_SOFT_RESET 0x053b 2879#define regDCHUBBUB_SOFT_RESET_BASE_IDX 2 2880#define regDCHUBBUB_CLOCK_CNTL 0x053c 2881#define regDCHUBBUB_CLOCK_CNTL_BASE_IDX 2 2882#define regDCFCLK_CNTL 0x053d 2883#define regDCFCLK_CNTL_BASE_IDX 2 2884#define regDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL 0x053e 2885#define regDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL_BASE_IDX 2 2886#define regDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2 0x053f 2887#define regDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2_BASE_IDX 2 2888#define regDCHUBBUB_VLINE_SNAPSHOT 0x0540 2889#define regDCHUBBUB_VLINE_SNAPSHOT_BASE_IDX 2 2890#define regDCHUBBUB_CTRL_STATUS 0x0541 2891#define regDCHUBBUB_CTRL_STATUS_BASE_IDX 2 2892#define regDCHUBBUB_TIMEOUT_DETECTION_CTRL1 0x0547 2893#define regDCHUBBUB_TIMEOUT_DETECTION_CTRL1_BASE_IDX 2 2894#define regDCHUBBUB_TIMEOUT_DETECTION_CTRL2 0x0548 2895#define regDCHUBBUB_TIMEOUT_DETECTION_CTRL2_BASE_IDX 2 2896#define regDCHUBBUB_TIMEOUT_INTERRUPT_STATUS 0x0549 2897#define regDCHUBBUB_TIMEOUT_INTERRUPT_STATUS_BASE_IDX 2 2898#define regFMON_CTRL 0x054a 2899#define regFMON_CTRL_BASE_IDX 2 2900#define regDCHUBBUB_TEST_DEBUG_INDEX 0x054b 2901#define regDCHUBBUB_TEST_DEBUG_INDEX_BASE_IDX 2 2902#define regDCHUBBUB_TEST_DEBUG_DATA 0x054c 2903#define regDCHUBBUB_TEST_DEBUG_DATA_BASE_IDX 2 2904 2905// addressBlock: dce_dc_dchubbubl_dchubbub_dcperfmon_dc_perfmon_dispdec 2906// base address: 0x1534 2907#define regDC_PERFMON6_PERFCOUNTER_CNTL 0x054d 2908#define regDC_PERFMON6_PERFCOUNTER_CNTL_BASE_IDX 2 2909#define regDC_PERFMON6_PERFCOUNTER_CNTL2 0x054e 2910#define regDC_PERFMON6_PERFCOUNTER_CNTL2_BASE_IDX 2 2911#define regDC_PERFMON6_PERFCOUNTER_STATE 0x054f 2912#define regDC_PERFMON6_PERFCOUNTER_STATE_BASE_IDX 2 2913#define regDC_PERFMON6_PERFMON_CNTL 0x0550 2914#define regDC_PERFMON6_PERFMON_CNTL_BASE_IDX 2 2915#define regDC_PERFMON6_PERFMON_CNTL2 0x0551 2916#define regDC_PERFMON6_PERFMON_CNTL2_BASE_IDX 2 2917#define regDC_PERFMON6_PERFMON_CVALUE_INT_MISC 0x0552 2918#define regDC_PERFMON6_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 2919#define regDC_PERFMON6_PERFMON_CVALUE_LOW 0x0553 2920#define regDC_PERFMON6_PERFMON_CVALUE_LOW_BASE_IDX 2 2921#define regDC_PERFMON6_PERFMON_HI 0x0554 2922#define regDC_PERFMON6_PERFMON_HI_BASE_IDX 2 2923#define regDC_PERFMON6_PERFMON_LOW 0x0555 2924#define regDC_PERFMON6_PERFMON_LOW_BASE_IDX 2 2925 2926 2927// addressBlock: dce_dc_dchubbubl_hubbub_vmrq_if_dispdec 2928// base address: 0x0 2929#define regDCN_VM_CONTEXT0_CNTL 0x0559 2930#define regDCN_VM_CONTEXT0_CNTL_BASE_IDX 2 2931#define regDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 0x055a 2932#define regDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 2933#define regDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 0x055b 2934#define regDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 2935#define regDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 0x055c 2936#define regDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 2937#define regDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 0x055d 2938#define regDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 2939#define regDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 0x055e 2940#define regDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 2941#define regDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 0x055f 2942#define regDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 2943#define regDCN_VM_CONTEXT1_CNTL 0x0560 2944#define regDCN_VM_CONTEXT1_CNTL_BASE_IDX 2 2945#define regDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32 0x0561 2946#define regDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 2947#define regDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 0x0562 2948#define regDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 2949#define regDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32 0x0563 2950#define regDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 2951#define regDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32 0x0564 2952#define regDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 2953#define regDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32 0x0565 2954#define regDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 2955#define regDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32 0x0566 2956#define regDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 2957#define regDCN_VM_CONTEXT2_CNTL 0x0567 2958#define regDCN_VM_CONTEXT2_CNTL_BASE_IDX 2 2959#define regDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32 0x0568 2960#define regDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 2961#define regDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32 0x0569 2962#define regDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 2963#define regDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32 0x056a 2964#define regDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 2965#define regDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32 0x056b 2966#define regDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 2967#define regDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32 0x056c 2968#define regDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 2969#define regDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32 0x056d 2970#define regDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 2971#define regDCN_VM_CONTEXT3_CNTL 0x056e 2972#define regDCN_VM_CONTEXT3_CNTL_BASE_IDX 2 2973#define regDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32 0x056f 2974#define regDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 2975#define regDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32 0x0570 2976#define regDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 2977#define regDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32 0x0571 2978#define regDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 2979#define regDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32 0x0572 2980#define regDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 2981#define regDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32 0x0573 2982#define regDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 2983#define regDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32 0x0574 2984#define regDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 2985#define regDCN_VM_CONTEXT4_CNTL 0x0575 2986#define regDCN_VM_CONTEXT4_CNTL_BASE_IDX 2 2987#define regDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32 0x0576 2988#define regDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 2989#define regDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32 0x0577 2990#define regDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 2991#define regDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32 0x0578 2992#define regDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 2993#define regDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32 0x0579 2994#define regDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 2995#define regDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32 0x057a 2996#define regDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 2997#define regDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32 0x057b 2998#define regDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 2999#define regDCN_VM_CONTEXT5_CNTL 0x057c 3000#define regDCN_VM_CONTEXT5_CNTL_BASE_IDX 2 3001#define regDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32 0x057d 3002#define regDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 3003#define regDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32 0x057e 3004#define regDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 3005#define regDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32 0x057f 3006#define regDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 3007#define regDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32 0x0580 3008#define regDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 3009#define regDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32 0x0581 3010#define regDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 3011#define regDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32 0x0582 3012#define regDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 3013#define regDCN_VM_CONTEXT6_CNTL 0x0583 3014#define regDCN_VM_CONTEXT6_CNTL_BASE_IDX 2 3015#define regDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32 0x0584 3016#define regDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 3017#define regDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32 0x0585 3018#define regDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 3019#define regDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32 0x0586 3020#define regDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 3021#define regDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32 0x0587 3022#define regDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 3023#define regDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32 0x0588 3024#define regDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 3025#define regDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32 0x0589 3026#define regDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 3027#define regDCN_VM_CONTEXT7_CNTL 0x058a 3028#define regDCN_VM_CONTEXT7_CNTL_BASE_IDX 2 3029#define regDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32 0x058b 3030#define regDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 3031#define regDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32 0x058c 3032#define regDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 3033#define regDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32 0x058d 3034#define regDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 3035#define regDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32 0x058e 3036#define regDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 3037#define regDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32 0x058f 3038#define regDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 3039#define regDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32 0x0590 3040#define regDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 3041#define regDCN_VM_CONTEXT8_CNTL 0x0591 3042#define regDCN_VM_CONTEXT8_CNTL_BASE_IDX 2 3043#define regDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32 0x0592 3044#define regDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 3045#define regDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32 0x0593 3046#define regDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 3047#define regDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32 0x0594 3048#define regDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 3049#define regDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32 0x0595 3050#define regDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 3051#define regDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32 0x0596 3052#define regDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 3053#define regDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32 0x0597 3054#define regDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 3055#define regDCN_VM_CONTEXT9_CNTL 0x0598 3056#define regDCN_VM_CONTEXT9_CNTL_BASE_IDX 2 3057#define regDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32 0x0599 3058#define regDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 3059#define regDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32 0x059a 3060#define regDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 3061#define regDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32 0x059b 3062#define regDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 3063#define regDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32 0x059c 3064#define regDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 3065#define regDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32 0x059d 3066#define regDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 3067#define regDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32 0x059e 3068#define regDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 3069#define regDCN_VM_CONTEXT10_CNTL 0x059f 3070#define regDCN_VM_CONTEXT10_CNTL_BASE_IDX 2 3071#define regDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32 0x05a0 3072#define regDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 3073#define regDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32 0x05a1 3074#define regDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 3075#define regDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32 0x05a2 3076#define regDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 3077#define regDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32 0x05a3 3078#define regDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 3079#define regDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32 0x05a4 3080#define regDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 3081#define regDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32 0x05a5 3082#define regDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 3083#define regDCN_VM_CONTEXT11_CNTL 0x05a6 3084#define regDCN_VM_CONTEXT11_CNTL_BASE_IDX 2 3085#define regDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32 0x05a7 3086#define regDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 3087#define regDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32 0x05a8 3088#define regDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 3089#define regDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32 0x05a9 3090#define regDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 3091#define regDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32 0x05aa 3092#define regDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 3093#define regDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32 0x05ab 3094#define regDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 3095#define regDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32 0x05ac 3096#define regDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 3097#define regDCN_VM_CONTEXT12_CNTL 0x05ad 3098#define regDCN_VM_CONTEXT12_CNTL_BASE_IDX 2 3099#define regDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32 0x05ae 3100#define regDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 3101#define regDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32 0x05af 3102#define regDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 3103#define regDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32 0x05b0 3104#define regDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 3105#define regDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32 0x05b1 3106#define regDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 3107#define regDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32 0x05b2 3108#define regDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 3109#define regDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32 0x05b3 3110#define regDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 3111#define regDCN_VM_CONTEXT13_CNTL 0x05b4 3112#define regDCN_VM_CONTEXT13_CNTL_BASE_IDX 2 3113#define regDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32 0x05b5 3114#define regDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 3115#define regDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32 0x05b6 3116#define regDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 3117#define regDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32 0x05b7 3118#define regDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 3119#define regDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32 0x05b8 3120#define regDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 3121#define regDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32 0x05b9 3122#define regDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 3123#define regDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32 0x05ba 3124#define regDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 3125#define regDCN_VM_CONTEXT14_CNTL 0x05bb 3126#define regDCN_VM_CONTEXT14_CNTL_BASE_IDX 2 3127#define regDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32 0x05bc 3128#define regDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 3129#define regDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32 0x05bd 3130#define regDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 3131#define regDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32 0x05be 3132#define regDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 3133#define regDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32 0x05bf 3134#define regDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 3135#define regDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32 0x05c0 3136#define regDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 3137#define regDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32 0x05c1 3138#define regDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 3139#define regDCN_VM_CONTEXT15_CNTL 0x05c2 3140#define regDCN_VM_CONTEXT15_CNTL_BASE_IDX 2 3141#define regDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32 0x05c3 3142#define regDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 3143#define regDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32 0x05c4 3144#define regDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 3145#define regDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32 0x05c5 3146#define regDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 3147#define regDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32 0x05c6 3148#define regDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 3149#define regDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32 0x05c7 3150#define regDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 3151#define regDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32 0x05c8 3152#define regDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 3153#define regDCN_VM_DEFAULT_ADDR_MSB 0x05c9 3154#define regDCN_VM_DEFAULT_ADDR_MSB_BASE_IDX 2 3155#define regDCN_VM_DEFAULT_ADDR_LSB 0x05ca 3156#define regDCN_VM_DEFAULT_ADDR_LSB_BASE_IDX 2 3157#define regDCN_VM_FAULT_CNTL 0x05cb 3158#define regDCN_VM_FAULT_CNTL_BASE_IDX 2 3159#define regDCN_VM_FAULT_STATUS 0x05cc 3160#define regDCN_VM_FAULT_STATUS_BASE_IDX 2 3161#define regDCN_VM_FAULT_ADDR_MSB 0x05cd 3162#define regDCN_VM_FAULT_ADDR_MSB_BASE_IDX 2 3163#define regDCN_VM_FAULT_ADDR_LSB 0x05ce 3164#define regDCN_VM_FAULT_ADDR_LSB_BASE_IDX 2 3165 3166 3167 3168// addressBlock: dce_dc_dcbubp0_dispdec_hubp_dispdec 3169// base address: 0x0 3170#define regHUBP0_DCSURF_SURFACE_CONFIG 0x05e5 3171#define regHUBP0_DCSURF_SURFACE_CONFIG_BASE_IDX 2 3172#define regHUBP0_DCSURF_ADDR_CONFIG 0x05e6 3173#define regHUBP0_DCSURF_ADDR_CONFIG_BASE_IDX 2 3174#define regHUBP0_DCSURF_TILING_CONFIG 0x05e7 3175#define regHUBP0_DCSURF_TILING_CONFIG_BASE_IDX 2 3176#define regHUBP0_DCSURF_PRI_VIEWPORT_START 0x05e9 3177#define regHUBP0_DCSURF_PRI_VIEWPORT_START_BASE_IDX 2 3178#define regHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION 0x05ea 3179#define regHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2 3180#define regHUBP0_DCSURF_PRI_VIEWPORT_START_C 0x05eb 3181#define regHUBP0_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX 2 3182#define regHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C 0x05ec 3183#define regHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX 2 3184#define regHUBP0_DCSURF_SEC_VIEWPORT_START 0x05ed 3185#define regHUBP0_DCSURF_SEC_VIEWPORT_START_BASE_IDX 2 3186#define regHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION 0x05ee 3187#define regHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX 2 3188#define regHUBP0_DCSURF_SEC_VIEWPORT_START_C 0x05ef 3189#define regHUBP0_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX 2 3190#define regHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C 0x05f0 3191#define regHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX 2 3192#define regHUBP0_DCHUBP_REQ_SIZE_CONFIG 0x05f1 3193#define regHUBP0_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX 2 3194#define regHUBP0_DCHUBP_REQ_SIZE_CONFIG_C 0x05f2 3195#define regHUBP0_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX 2 3196#define regHUBP0_DCHUBP_CNTL 0x05f3 3197#define regHUBP0_DCHUBP_CNTL_BASE_IDX 2 3198#define regHUBP0_HUBP_CLK_CNTL 0x05f4 3199#define regHUBP0_HUBP_CLK_CNTL_BASE_IDX 2 3200#define regHUBP0_DCHUBP_VMPG_CONFIG 0x05f5 3201#define regHUBP0_DCHUBP_VMPG_CONFIG_BASE_IDX 2 3202#define regHUBP0_DCHUBP_MALL_CONFIG 0x05f6 3203#define regHUBP0_DCHUBP_MALL_CONFIG_BASE_IDX 2 3204#define regHUBP0_DCHUBP_MALL_SUB_VP 0x05f7 3205#define regHUBP0_DCHUBP_MALL_SUB_VP_BASE_IDX 2 3206#define regHUBP0_HUBPREQ_DEBUG_DB 0x05f8 3207#define regHUBP0_HUBPREQ_DEBUG_DB_BASE_IDX 2 3208#define regHUBP0_HUBPREQ_DEBUG 0x05f9 3209#define regHUBP0_HUBPREQ_DEBUG_BASE_IDX 2 3210#define regHUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK 0x05fd 3211#define regHUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX 2 3212#define regHUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK 0x05fe 3213#define regHUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX 2 3214#define regHUBP0_HUBP_MALL_STATUS 0x05ff 3215#define regHUBP0_HUBP_MALL_STATUS_BASE_IDX 2 3216 3217 3218// addressBlock: dce_dc_dcbubp0_dispdec_hubpreq_dispdec 3219// base address: 0x0 3220#define regHUBPREQ0_DCSURF_SURFACE_PITCH 0x0607 3221#define regHUBPREQ0_DCSURF_SURFACE_PITCH_BASE_IDX 2 3222#define regHUBPREQ0_DCSURF_SURFACE_PITCH_C 0x0608 3223#define regHUBPREQ0_DCSURF_SURFACE_PITCH_C_BASE_IDX 2 3224#define regHUBPREQ0_VMID_SETTINGS_0 0x0609 3225#define regHUBPREQ0_VMID_SETTINGS_0_BASE_IDX 2 3226#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS 0x060a 3227#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2 3228#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH 0x060b 3229#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 3230#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C 0x060c 3231#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX 2 3232#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x060d 3233#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 3234#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS 0x060e 3235#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2 3236#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH 0x060f 3237#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 3238#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C 0x0610 3239#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX 2 3240#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x0611 3241#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 3242#define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS 0x0612 3243#define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX 2 3244#define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH 0x0613 3245#define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 3246#define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C 0x0614 3247#define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 3248#define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C 0x0615 3249#define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 3250#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS 0x0616 3251#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX 2 3252#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH 0x0617 3253#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 3254#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C 0x0618 3255#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 3256#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C 0x0619 3257#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 3258#define regHUBPREQ0_DCSURF_SURFACE_CONTROL 0x061a 3259#define regHUBPREQ0_DCSURF_SURFACE_CONTROL_BASE_IDX 2 3260#define regHUBPREQ0_DCSURF_FLIP_CONTROL 0x061b 3261#define regHUBPREQ0_DCSURF_FLIP_CONTROL_BASE_IDX 2 3262#define regHUBPREQ0_DCSURF_FLIP_CONTROL2 0x061c 3263#define regHUBPREQ0_DCSURF_FLIP_CONTROL2_BASE_IDX 2 3264#define regHUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT 0x061f 3265#define regHUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX 2 3266#define regHUBPREQ0_DCSURF_SURFACE_INUSE 0x0620 3267#define regHUBPREQ0_DCSURF_SURFACE_INUSE_BASE_IDX 2 3268#define regHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH 0x0621 3269#define regHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX 2 3270#define regHUBPREQ0_DCSURF_SURFACE_INUSE_C 0x0622 3271#define regHUBPREQ0_DCSURF_SURFACE_INUSE_C_BASE_IDX 2 3272#define regHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C 0x0623 3273#define regHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX 2 3274#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE 0x0624 3275#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX 2 3276#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH 0x0625 3277#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX 2 3278#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C 0x0626 3279#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX 2 3280#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C 0x0627 3281#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX 2 3282#define regHUBPREQ0_DCN_EXPANSION_MODE 0x0628 3283#define regHUBPREQ0_DCN_EXPANSION_MODE_BASE_IDX 2 3284#define regHUBPREQ0_DCN_TTU_QOS_WM 0x0629 3285#define regHUBPREQ0_DCN_TTU_QOS_WM_BASE_IDX 2 3286#define regHUBPREQ0_DCN_GLOBAL_TTU_CNTL 0x062a 3287#define regHUBPREQ0_DCN_GLOBAL_TTU_CNTL_BASE_IDX 2 3288#define regHUBPREQ0_DCN_SURF0_TTU_CNTL0 0x062b 3289#define regHUBPREQ0_DCN_SURF0_TTU_CNTL0_BASE_IDX 2 3290#define regHUBPREQ0_DCN_SURF0_TTU_CNTL1 0x062c 3291#define regHUBPREQ0_DCN_SURF0_TTU_CNTL1_BASE_IDX 2 3292#define regHUBPREQ0_DCN_SURF1_TTU_CNTL0 0x062d 3293#define regHUBPREQ0_DCN_SURF1_TTU_CNTL0_BASE_IDX 2 3294#define regHUBPREQ0_DCN_SURF1_TTU_CNTL1 0x062e 3295#define regHUBPREQ0_DCN_SURF1_TTU_CNTL1_BASE_IDX 2 3296#define regHUBPREQ0_DCN_CUR0_TTU_CNTL0 0x062f 3297#define regHUBPREQ0_DCN_CUR0_TTU_CNTL0_BASE_IDX 2 3298#define regHUBPREQ0_DCN_CUR0_TTU_CNTL1 0x0630 3299#define regHUBPREQ0_DCN_CUR0_TTU_CNTL1_BASE_IDX 2 3300#define regHUBPREQ0_DCN_CUR1_TTU_CNTL0 0x0631 3301#define regHUBPREQ0_DCN_CUR1_TTU_CNTL0_BASE_IDX 2 3302#define regHUBPREQ0_DCN_CUR1_TTU_CNTL1 0x0632 3303#define regHUBPREQ0_DCN_CUR1_TTU_CNTL1_BASE_IDX 2 3304#define regHUBPREQ0_DCN_DMDATA_VM_CNTL 0x0633 3305#define regHUBPREQ0_DCN_DMDATA_VM_CNTL_BASE_IDX 2 3306#define regHUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR 0x0634 3307#define regHUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 2 3308#define regHUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR 0x0635 3309#define regHUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 2 3310#define regHUBPREQ0_DCN_VM_MX_L1_TLB_CNTL 0x0642 3311#define regHUBPREQ0_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX 2 3312#define regHUBPREQ0_BLANK_OFFSET_0 0x0643 3313#define regHUBPREQ0_BLANK_OFFSET_0_BASE_IDX 2 3314#define regHUBPREQ0_BLANK_OFFSET_1 0x0644 3315#define regHUBPREQ0_BLANK_OFFSET_1_BASE_IDX 2 3316#define regHUBPREQ0_DST_DIMENSIONS 0x0645 3317#define regHUBPREQ0_DST_DIMENSIONS_BASE_IDX 2 3318#define regHUBPREQ0_DST_AFTER_SCALER 0x0646 3319#define regHUBPREQ0_DST_AFTER_SCALER_BASE_IDX 2 3320#define regHUBPREQ0_PREFETCH_SETTINGS 0x0647 3321#define regHUBPREQ0_PREFETCH_SETTINGS_BASE_IDX 2 3322#define regHUBPREQ0_PREFETCH_SETTINGS_C 0x0648 3323#define regHUBPREQ0_PREFETCH_SETTINGS_C_BASE_IDX 2 3324#define regHUBPREQ0_VBLANK_PARAMETERS_0 0x0649 3325#define regHUBPREQ0_VBLANK_PARAMETERS_0_BASE_IDX 2 3326#define regHUBPREQ0_VBLANK_PARAMETERS_1 0x064a 3327#define regHUBPREQ0_VBLANK_PARAMETERS_1_BASE_IDX 2 3328#define regHUBPREQ0_VBLANK_PARAMETERS_2 0x064b 3329#define regHUBPREQ0_VBLANK_PARAMETERS_2_BASE_IDX 2 3330#define regHUBPREQ0_VBLANK_PARAMETERS_3 0x064c 3331#define regHUBPREQ0_VBLANK_PARAMETERS_3_BASE_IDX 2 3332#define regHUBPREQ0_VBLANK_PARAMETERS_4 0x064d 3333#define regHUBPREQ0_VBLANK_PARAMETERS_4_BASE_IDX 2 3334#define regHUBPREQ0_FLIP_PARAMETERS_0 0x064e 3335#define regHUBPREQ0_FLIP_PARAMETERS_0_BASE_IDX 2 3336#define regHUBPREQ0_FLIP_PARAMETERS_1 0x064f 3337#define regHUBPREQ0_FLIP_PARAMETERS_1_BASE_IDX 2 3338#define regHUBPREQ0_FLIP_PARAMETERS_2 0x0650 3339#define regHUBPREQ0_FLIP_PARAMETERS_2_BASE_IDX 2 3340#define regHUBPREQ0_NOM_PARAMETERS_0 0x0651 3341#define regHUBPREQ0_NOM_PARAMETERS_0_BASE_IDX 2 3342#define regHUBPREQ0_NOM_PARAMETERS_1 0x0652 3343#define regHUBPREQ0_NOM_PARAMETERS_1_BASE_IDX 2 3344#define regHUBPREQ0_NOM_PARAMETERS_2 0x0653 3345#define regHUBPREQ0_NOM_PARAMETERS_2_BASE_IDX 2 3346#define regHUBPREQ0_NOM_PARAMETERS_3 0x0654 3347#define regHUBPREQ0_NOM_PARAMETERS_3_BASE_IDX 2 3348#define regHUBPREQ0_NOM_PARAMETERS_4 0x0655 3349#define regHUBPREQ0_NOM_PARAMETERS_4_BASE_IDX 2 3350#define regHUBPREQ0_NOM_PARAMETERS_5 0x0656 3351#define regHUBPREQ0_NOM_PARAMETERS_5_BASE_IDX 2 3352#define regHUBPREQ0_NOM_PARAMETERS_6 0x0657 3353#define regHUBPREQ0_NOM_PARAMETERS_6_BASE_IDX 2 3354#define regHUBPREQ0_NOM_PARAMETERS_7 0x0658 3355#define regHUBPREQ0_NOM_PARAMETERS_7_BASE_IDX 2 3356#define regHUBPREQ0_PER_LINE_DELIVERY_PRE 0x0659 3357#define regHUBPREQ0_PER_LINE_DELIVERY_PRE_BASE_IDX 2 3358#define regHUBPREQ0_PER_LINE_DELIVERY 0x065a 3359#define regHUBPREQ0_PER_LINE_DELIVERY_BASE_IDX 2 3360#define regHUBPREQ0_CURSOR_SETTINGS 0x065b 3361#define regHUBPREQ0_CURSOR_SETTINGS_BASE_IDX 2 3362#define regHUBPREQ0_REF_FREQ_TO_PIX_FREQ 0x065c 3363#define regHUBPREQ0_REF_FREQ_TO_PIX_FREQ_BASE_IDX 2 3364#define regHUBPREQ0_DST_Y_DELTA_DRQ_LIMIT 0x065d 3365#define regHUBPREQ0_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX 2 3366#define regHUBPREQ0_HUBPREQ_MEM_PWR_CTRL 0x065e 3367#define regHUBPREQ0_HUBPREQ_MEM_PWR_CTRL_BASE_IDX 2 3368#define regHUBPREQ0_HUBPREQ_MEM_PWR_STATUS 0x065f 3369#define regHUBPREQ0_HUBPREQ_MEM_PWR_STATUS_BASE_IDX 2 3370#define regHUBPREQ0_VBLANK_PARAMETERS_5 0x0662 3371#define regHUBPREQ0_VBLANK_PARAMETERS_5_BASE_IDX 2 3372#define regHUBPREQ0_VBLANK_PARAMETERS_6 0x0663 3373#define regHUBPREQ0_VBLANK_PARAMETERS_6_BASE_IDX 2 3374#define regHUBPREQ0_FLIP_PARAMETERS_3 0x0664 3375#define regHUBPREQ0_FLIP_PARAMETERS_3_BASE_IDX 2 3376#define regHUBPREQ0_FLIP_PARAMETERS_4 0x0665 3377#define regHUBPREQ0_FLIP_PARAMETERS_4_BASE_IDX 2 3378#define regHUBPREQ0_FLIP_PARAMETERS_5 0x0666 3379#define regHUBPREQ0_FLIP_PARAMETERS_5_BASE_IDX 2 3380#define regHUBPREQ0_FLIP_PARAMETERS_6 0x0667 3381#define regHUBPREQ0_FLIP_PARAMETERS_6_BASE_IDX 2 3382#define regHUBPREQ0_UCLK_PSTATE_FORCE 0x0668 3383#define regHUBPREQ0_UCLK_PSTATE_FORCE_BASE_IDX 2 3384#define regHUBPREQ0_HUBPREQ_STATUS_REG0 0x0669 3385#define regHUBPREQ0_HUBPREQ_STATUS_REG0_BASE_IDX 2 3386#define regHUBPREQ0_HUBPREQ_STATUS_REG1 0x066a 3387#define regHUBPREQ0_HUBPREQ_STATUS_REG1_BASE_IDX 2 3388#define regHUBPREQ0_HUBPREQ_STATUS_REG2 0x066b 3389#define regHUBPREQ0_HUBPREQ_STATUS_REG2_BASE_IDX 2 3390 3391 3392// addressBlock: dce_dc_dcbubp0_dispdec_hubpret_dispdec 3393// base address: 0x0 3394#define regHUBPRET0_HUBPRET_CONTROL 0x066c 3395#define regHUBPRET0_HUBPRET_CONTROL_BASE_IDX 2 3396#define regHUBPRET0_HUBPRET_MEM_PWR_CTRL 0x066d 3397#define regHUBPRET0_HUBPRET_MEM_PWR_CTRL_BASE_IDX 2 3398#define regHUBPRET0_HUBPRET_MEM_PWR_STATUS 0x066e 3399#define regHUBPRET0_HUBPRET_MEM_PWR_STATUS_BASE_IDX 2 3400#define regHUBPRET0_HUBPRET_READ_LINE_CTRL0 0x066f 3401#define regHUBPRET0_HUBPRET_READ_LINE_CTRL0_BASE_IDX 2 3402#define regHUBPRET0_HUBPRET_READ_LINE_CTRL1 0x0670 3403#define regHUBPRET0_HUBPRET_READ_LINE_CTRL1_BASE_IDX 2 3404#define regHUBPRET0_HUBPRET_READ_LINE0 0x0671 3405#define regHUBPRET0_HUBPRET_READ_LINE0_BASE_IDX 2 3406#define regHUBPRET0_HUBPRET_READ_LINE1 0x0672 3407#define regHUBPRET0_HUBPRET_READ_LINE1_BASE_IDX 2 3408#define regHUBPRET0_HUBPRET_INTERRUPT 0x0673 3409#define regHUBPRET0_HUBPRET_INTERRUPT_BASE_IDX 2 3410#define regHUBPRET0_HUBPRET_READ_LINE_VALUE 0x0674 3411#define regHUBPRET0_HUBPRET_READ_LINE_VALUE_BASE_IDX 2 3412#define regHUBPRET0_HUBPRET_READ_LINE_STATUS 0x0675 3413#define regHUBPRET0_HUBPRET_READ_LINE_STATUS_BASE_IDX 2 3414 3415 3416// addressBlock: dce_dc_dcbubp0_dispdec_cursor0_dispdec 3417// base address: 0x0 3418#define regCURSOR0_0_CURSOR_CONTROL 0x0678 3419#define regCURSOR0_0_CURSOR_CONTROL_BASE_IDX 2 3420#define regCURSOR0_0_CURSOR_SURFACE_ADDRESS 0x0679 3421#define regCURSOR0_0_CURSOR_SURFACE_ADDRESS_BASE_IDX 2 3422#define regCURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH 0x067a 3423#define regCURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX 2 3424#define regCURSOR0_0_CURSOR_SIZE 0x067b 3425#define regCURSOR0_0_CURSOR_SIZE_BASE_IDX 2 3426#define regCURSOR0_0_CURSOR_POSITION 0x067c 3427#define regCURSOR0_0_CURSOR_POSITION_BASE_IDX 2 3428#define regCURSOR0_0_CURSOR_HOT_SPOT 0x067d 3429#define regCURSOR0_0_CURSOR_HOT_SPOT_BASE_IDX 2 3430#define regCURSOR0_0_CURSOR_STEREO_CONTROL 0x067e 3431#define regCURSOR0_0_CURSOR_STEREO_CONTROL_BASE_IDX 2 3432#define regCURSOR0_0_CURSOR_DST_OFFSET 0x067f 3433#define regCURSOR0_0_CURSOR_DST_OFFSET_BASE_IDX 2 3434#define regCURSOR0_0_CURSOR_MEM_PWR_CTRL 0x0680 3435#define regCURSOR0_0_CURSOR_MEM_PWR_CTRL_BASE_IDX 2 3436#define regCURSOR0_0_CURSOR_MEM_PWR_STATUS 0x0681 3437#define regCURSOR0_0_CURSOR_MEM_PWR_STATUS_BASE_IDX 2 3438#define regCURSOR0_0_DMDATA_ADDRESS_HIGH 0x0682 3439#define regCURSOR0_0_DMDATA_ADDRESS_HIGH_BASE_IDX 2 3440#define regCURSOR0_0_DMDATA_ADDRESS_LOW 0x0683 3441#define regCURSOR0_0_DMDATA_ADDRESS_LOW_BASE_IDX 2 3442#define regCURSOR0_0_DMDATA_CNTL 0x0684 3443#define regCURSOR0_0_DMDATA_CNTL_BASE_IDX 2 3444#define regCURSOR0_0_DMDATA_QOS_CNTL 0x0685 3445#define regCURSOR0_0_DMDATA_QOS_CNTL_BASE_IDX 2 3446#define regCURSOR0_0_DMDATA_STATUS 0x0686 3447#define regCURSOR0_0_DMDATA_STATUS_BASE_IDX 2 3448#define regCURSOR0_0_DMDATA_SW_CNTL 0x0687 3449#define regCURSOR0_0_DMDATA_SW_CNTL_BASE_IDX 2 3450#define regCURSOR0_0_DMDATA_SW_DATA 0x0688 3451#define regCURSOR0_0_DMDATA_SW_DATA_BASE_IDX 2 3452 3453 3454// addressBlock: dce_dc_dcbubp0_dispdec_hubp_dcperfmon_dc_perfmon_dispdec 3455// base address: 0x1a74 3456#define regDC_PERFMON7_PERFCOUNTER_CNTL 0x069d 3457#define regDC_PERFMON7_PERFCOUNTER_CNTL_BASE_IDX 2 3458#define regDC_PERFMON7_PERFCOUNTER_CNTL2 0x069e 3459#define regDC_PERFMON7_PERFCOUNTER_CNTL2_BASE_IDX 2 3460#define regDC_PERFMON7_PERFCOUNTER_STATE 0x069f 3461#define regDC_PERFMON7_PERFCOUNTER_STATE_BASE_IDX 2 3462#define regDC_PERFMON7_PERFMON_CNTL 0x06a0 3463#define regDC_PERFMON7_PERFMON_CNTL_BASE_IDX 2 3464#define regDC_PERFMON7_PERFMON_CNTL2 0x06a1 3465#define regDC_PERFMON7_PERFMON_CNTL2_BASE_IDX 2 3466#define regDC_PERFMON7_PERFMON_CVALUE_INT_MISC 0x06a2 3467#define regDC_PERFMON7_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 3468#define regDC_PERFMON7_PERFMON_CVALUE_LOW 0x06a3 3469#define regDC_PERFMON7_PERFMON_CVALUE_LOW_BASE_IDX 2 3470#define regDC_PERFMON7_PERFMON_HI 0x06a4 3471#define regDC_PERFMON7_PERFMON_HI_BASE_IDX 2 3472#define regDC_PERFMON7_PERFMON_LOW 0x06a5 3473#define regDC_PERFMON7_PERFMON_LOW_BASE_IDX 2 3474 3475 3476// addressBlock: dce_dc_dcbubp1_dispdec_hubp_dispdec 3477// base address: 0x370 3478#define regHUBP1_DCSURF_SURFACE_CONFIG 0x06c1 3479#define regHUBP1_DCSURF_SURFACE_CONFIG_BASE_IDX 2 3480#define regHUBP1_DCSURF_ADDR_CONFIG 0x06c2 3481#define regHUBP1_DCSURF_ADDR_CONFIG_BASE_IDX 2 3482#define regHUBP1_DCSURF_TILING_CONFIG 0x06c3 3483#define regHUBP1_DCSURF_TILING_CONFIG_BASE_IDX 2 3484#define regHUBP1_DCSURF_PRI_VIEWPORT_START 0x06c5 3485#define regHUBP1_DCSURF_PRI_VIEWPORT_START_BASE_IDX 2 3486#define regHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION 0x06c6 3487#define regHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2 3488#define regHUBP1_DCSURF_PRI_VIEWPORT_START_C 0x06c7 3489#define regHUBP1_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX 2 3490#define regHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C 0x06c8 3491#define regHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX 2 3492#define regHUBP1_DCSURF_SEC_VIEWPORT_START 0x06c9 3493#define regHUBP1_DCSURF_SEC_VIEWPORT_START_BASE_IDX 2 3494#define regHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION 0x06ca 3495#define regHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX 2 3496#define regHUBP1_DCSURF_SEC_VIEWPORT_START_C 0x06cb 3497#define regHUBP1_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX 2 3498#define regHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C 0x06cc 3499#define regHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX 2 3500#define regHUBP1_DCHUBP_REQ_SIZE_CONFIG 0x06cd 3501#define regHUBP1_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX 2 3502#define regHUBP1_DCHUBP_REQ_SIZE_CONFIG_C 0x06ce 3503#define regHUBP1_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX 2 3504#define regHUBP1_DCHUBP_CNTL 0x06cf 3505#define regHUBP1_DCHUBP_CNTL_BASE_IDX 2 3506#define regHUBP1_HUBP_CLK_CNTL 0x06d0 3507#define regHUBP1_HUBP_CLK_CNTL_BASE_IDX 2 3508#define regHUBP1_DCHUBP_VMPG_CONFIG 0x06d1 3509#define regHUBP1_DCHUBP_VMPG_CONFIG_BASE_IDX 2 3510#define regHUBP1_DCHUBP_MALL_CONFIG 0x06d2 3511#define regHUBP1_DCHUBP_MALL_CONFIG_BASE_IDX 2 3512#define regHUBP1_DCHUBP_MALL_SUB_VP 0x06d3 3513#define regHUBP1_DCHUBP_MALL_SUB_VP_BASE_IDX 2 3514#define regHUBP1_HUBPREQ_DEBUG_DB 0x06d4 3515#define regHUBP1_HUBPREQ_DEBUG_DB_BASE_IDX 2 3516#define regHUBP1_HUBPREQ_DEBUG 0x06d5 3517#define regHUBP1_HUBPREQ_DEBUG_BASE_IDX 2 3518#define regHUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK 0x06d9 3519#define regHUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX 2 3520#define regHUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK 0x06da 3521#define regHUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX 2 3522#define regHUBP1_HUBP_MALL_STATUS 0x06db 3523#define regHUBP1_HUBP_MALL_STATUS_BASE_IDX 2 3524 3525 3526// addressBlock: dce_dc_dcbubp1_dispdec_hubpreq_dispdec 3527// base address: 0x370 3528#define regHUBPREQ1_DCSURF_SURFACE_PITCH 0x06e3 3529#define regHUBPREQ1_DCSURF_SURFACE_PITCH_BASE_IDX 2 3530#define regHUBPREQ1_DCSURF_SURFACE_PITCH_C 0x06e4 3531#define regHUBPREQ1_DCSURF_SURFACE_PITCH_C_BASE_IDX 2 3532#define regHUBPREQ1_VMID_SETTINGS_0 0x06e5 3533#define regHUBPREQ1_VMID_SETTINGS_0_BASE_IDX 2 3534#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS 0x06e6 3535#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2 3536#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH 0x06e7 3537#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 3538#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C 0x06e8 3539#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX 2 3540#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x06e9 3541#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 3542#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS 0x06ea 3543#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2 3544#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH 0x06eb 3545#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 3546#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C 0x06ec 3547#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX 2 3548#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x06ed 3549#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 3550#define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS 0x06ee 3551#define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX 2 3552#define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH 0x06ef 3553#define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 3554#define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C 0x06f0 3555#define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 3556#define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C 0x06f1 3557#define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 3558#define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS 0x06f2 3559#define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX 2 3560#define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH 0x06f3 3561#define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 3562#define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C 0x06f4 3563#define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 3564#define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C 0x06f5 3565#define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 3566#define regHUBPREQ1_DCSURF_SURFACE_CONTROL 0x06f6 3567#define regHUBPREQ1_DCSURF_SURFACE_CONTROL_BASE_IDX 2 3568#define regHUBPREQ1_DCSURF_FLIP_CONTROL 0x06f7 3569#define regHUBPREQ1_DCSURF_FLIP_CONTROL_BASE_IDX 2 3570#define regHUBPREQ1_DCSURF_FLIP_CONTROL2 0x06f8 3571#define regHUBPREQ1_DCSURF_FLIP_CONTROL2_BASE_IDX 2 3572#define regHUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT 0x06fb 3573#define regHUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX 2 3574#define regHUBPREQ1_DCSURF_SURFACE_INUSE 0x06fc 3575#define regHUBPREQ1_DCSURF_SURFACE_INUSE_BASE_IDX 2 3576#define regHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH 0x06fd 3577#define regHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX 2 3578#define regHUBPREQ1_DCSURF_SURFACE_INUSE_C 0x06fe 3579#define regHUBPREQ1_DCSURF_SURFACE_INUSE_C_BASE_IDX 2 3580#define regHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C 0x06ff 3581#define regHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX 2 3582#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE 0x0700 3583#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX 2 3584#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH 0x0701 3585#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX 2 3586#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C 0x0702 3587#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX 2 3588#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C 0x0703 3589#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX 2 3590#define regHUBPREQ1_DCN_EXPANSION_MODE 0x0704 3591#define regHUBPREQ1_DCN_EXPANSION_MODE_BASE_IDX 2 3592#define regHUBPREQ1_DCN_TTU_QOS_WM 0x0705 3593#define regHUBPREQ1_DCN_TTU_QOS_WM_BASE_IDX 2 3594#define regHUBPREQ1_DCN_GLOBAL_TTU_CNTL 0x0706 3595#define regHUBPREQ1_DCN_GLOBAL_TTU_CNTL_BASE_IDX 2 3596#define regHUBPREQ1_DCN_SURF0_TTU_CNTL0 0x0707 3597#define regHUBPREQ1_DCN_SURF0_TTU_CNTL0_BASE_IDX 2 3598#define regHUBPREQ1_DCN_SURF0_TTU_CNTL1 0x0708 3599#define regHUBPREQ1_DCN_SURF0_TTU_CNTL1_BASE_IDX 2 3600#define regHUBPREQ1_DCN_SURF1_TTU_CNTL0 0x0709 3601#define regHUBPREQ1_DCN_SURF1_TTU_CNTL0_BASE_IDX 2 3602#define regHUBPREQ1_DCN_SURF1_TTU_CNTL1 0x070a 3603#define regHUBPREQ1_DCN_SURF1_TTU_CNTL1_BASE_IDX 2 3604#define regHUBPREQ1_DCN_CUR0_TTU_CNTL0 0x070b 3605#define regHUBPREQ1_DCN_CUR0_TTU_CNTL0_BASE_IDX 2 3606#define regHUBPREQ1_DCN_CUR0_TTU_CNTL1 0x070c 3607#define regHUBPREQ1_DCN_CUR0_TTU_CNTL1_BASE_IDX 2 3608#define regHUBPREQ1_DCN_CUR1_TTU_CNTL0 0x070d 3609#define regHUBPREQ1_DCN_CUR1_TTU_CNTL0_BASE_IDX 2 3610#define regHUBPREQ1_DCN_CUR1_TTU_CNTL1 0x070e 3611#define regHUBPREQ1_DCN_CUR1_TTU_CNTL1_BASE_IDX 2 3612#define regHUBPREQ1_DCN_DMDATA_VM_CNTL 0x070f 3613#define regHUBPREQ1_DCN_DMDATA_VM_CNTL_BASE_IDX 2 3614#define regHUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR 0x0710 3615#define regHUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 2 3616#define regHUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR 0x0711 3617#define regHUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 2 3618#define regHUBPREQ1_DCN_VM_MX_L1_TLB_CNTL 0x071e 3619#define regHUBPREQ1_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX 2 3620#define regHUBPREQ1_BLANK_OFFSET_0 0x071f 3621#define regHUBPREQ1_BLANK_OFFSET_0_BASE_IDX 2 3622#define regHUBPREQ1_BLANK_OFFSET_1 0x0720 3623#define regHUBPREQ1_BLANK_OFFSET_1_BASE_IDX 2 3624#define regHUBPREQ1_DST_DIMENSIONS 0x0721 3625#define regHUBPREQ1_DST_DIMENSIONS_BASE_IDX 2 3626#define regHUBPREQ1_DST_AFTER_SCALER 0x0722 3627#define regHUBPREQ1_DST_AFTER_SCALER_BASE_IDX 2 3628#define regHUBPREQ1_PREFETCH_SETTINGS 0x0723 3629#define regHUBPREQ1_PREFETCH_SETTINGS_BASE_IDX 2 3630#define regHUBPREQ1_PREFETCH_SETTINGS_C 0x0724 3631#define regHUBPREQ1_PREFETCH_SETTINGS_C_BASE_IDX 2 3632#define regHUBPREQ1_VBLANK_PARAMETERS_0 0x0725 3633#define regHUBPREQ1_VBLANK_PARAMETERS_0_BASE_IDX 2 3634#define regHUBPREQ1_VBLANK_PARAMETERS_1 0x0726 3635#define regHUBPREQ1_VBLANK_PARAMETERS_1_BASE_IDX 2 3636#define regHUBPREQ1_VBLANK_PARAMETERS_2 0x0727 3637#define regHUBPREQ1_VBLANK_PARAMETERS_2_BASE_IDX 2 3638#define regHUBPREQ1_VBLANK_PARAMETERS_3 0x0728 3639#define regHUBPREQ1_VBLANK_PARAMETERS_3_BASE_IDX 2 3640#define regHUBPREQ1_VBLANK_PARAMETERS_4 0x0729 3641#define regHUBPREQ1_VBLANK_PARAMETERS_4_BASE_IDX 2 3642#define regHUBPREQ1_FLIP_PARAMETERS_0 0x072a 3643#define regHUBPREQ1_FLIP_PARAMETERS_0_BASE_IDX 2 3644#define regHUBPREQ1_FLIP_PARAMETERS_1 0x072b 3645#define regHUBPREQ1_FLIP_PARAMETERS_1_BASE_IDX 2 3646#define regHUBPREQ1_FLIP_PARAMETERS_2 0x072c 3647#define regHUBPREQ1_FLIP_PARAMETERS_2_BASE_IDX 2 3648#define regHUBPREQ1_NOM_PARAMETERS_0 0x072d 3649#define regHUBPREQ1_NOM_PARAMETERS_0_BASE_IDX 2 3650#define regHUBPREQ1_NOM_PARAMETERS_1 0x072e 3651#define regHUBPREQ1_NOM_PARAMETERS_1_BASE_IDX 2 3652#define regHUBPREQ1_NOM_PARAMETERS_2 0x072f 3653#define regHUBPREQ1_NOM_PARAMETERS_2_BASE_IDX 2 3654#define regHUBPREQ1_NOM_PARAMETERS_3 0x0730 3655#define regHUBPREQ1_NOM_PARAMETERS_3_BASE_IDX 2 3656#define regHUBPREQ1_NOM_PARAMETERS_4 0x0731 3657#define regHUBPREQ1_NOM_PARAMETERS_4_BASE_IDX 2 3658#define regHUBPREQ1_NOM_PARAMETERS_5 0x0732 3659#define regHUBPREQ1_NOM_PARAMETERS_5_BASE_IDX 2 3660#define regHUBPREQ1_NOM_PARAMETERS_6 0x0733 3661#define regHUBPREQ1_NOM_PARAMETERS_6_BASE_IDX 2 3662#define regHUBPREQ1_NOM_PARAMETERS_7 0x0734 3663#define regHUBPREQ1_NOM_PARAMETERS_7_BASE_IDX 2 3664#define regHUBPREQ1_PER_LINE_DELIVERY_PRE 0x0735 3665#define regHUBPREQ1_PER_LINE_DELIVERY_PRE_BASE_IDX 2 3666#define regHUBPREQ1_PER_LINE_DELIVERY 0x0736 3667#define regHUBPREQ1_PER_LINE_DELIVERY_BASE_IDX 2 3668#define regHUBPREQ1_CURSOR_SETTINGS 0x0737 3669#define regHUBPREQ1_CURSOR_SETTINGS_BASE_IDX 2 3670#define regHUBPREQ1_REF_FREQ_TO_PIX_FREQ 0x0738 3671#define regHUBPREQ1_REF_FREQ_TO_PIX_FREQ_BASE_IDX 2 3672#define regHUBPREQ1_DST_Y_DELTA_DRQ_LIMIT 0x0739 3673#define regHUBPREQ1_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX 2 3674#define regHUBPREQ1_HUBPREQ_MEM_PWR_CTRL 0x073a 3675#define regHUBPREQ1_HUBPREQ_MEM_PWR_CTRL_BASE_IDX 2 3676#define regHUBPREQ1_HUBPREQ_MEM_PWR_STATUS 0x073b 3677#define regHUBPREQ1_HUBPREQ_MEM_PWR_STATUS_BASE_IDX 2 3678#define regHUBPREQ1_VBLANK_PARAMETERS_5 0x073e 3679#define regHUBPREQ1_VBLANK_PARAMETERS_5_BASE_IDX 2 3680#define regHUBPREQ1_VBLANK_PARAMETERS_6 0x073f 3681#define regHUBPREQ1_VBLANK_PARAMETERS_6_BASE_IDX 2 3682#define regHUBPREQ1_FLIP_PARAMETERS_3 0x0740 3683#define regHUBPREQ1_FLIP_PARAMETERS_3_BASE_IDX 2 3684#define regHUBPREQ1_FLIP_PARAMETERS_4 0x0741 3685#define regHUBPREQ1_FLIP_PARAMETERS_4_BASE_IDX 2 3686#define regHUBPREQ1_FLIP_PARAMETERS_5 0x0742 3687#define regHUBPREQ1_FLIP_PARAMETERS_5_BASE_IDX 2 3688#define regHUBPREQ1_FLIP_PARAMETERS_6 0x0743 3689#define regHUBPREQ1_FLIP_PARAMETERS_6_BASE_IDX 2 3690#define regHUBPREQ1_UCLK_PSTATE_FORCE 0x0744 3691#define regHUBPREQ1_UCLK_PSTATE_FORCE_BASE_IDX 2 3692#define regHUBPREQ1_HUBPREQ_STATUS_REG0 0x0745 3693#define regHUBPREQ1_HUBPREQ_STATUS_REG0_BASE_IDX 2 3694#define regHUBPREQ1_HUBPREQ_STATUS_REG1 0x0746 3695#define regHUBPREQ1_HUBPREQ_STATUS_REG1_BASE_IDX 2 3696#define regHUBPREQ1_HUBPREQ_STATUS_REG2 0x0747 3697#define regHUBPREQ1_HUBPREQ_STATUS_REG2_BASE_IDX 2 3698 3699 3700// addressBlock: dce_dc_dcbubp1_dispdec_hubpret_dispdec 3701// base address: 0x370 3702#define regHUBPRET1_HUBPRET_CONTROL 0x0748 3703#define regHUBPRET1_HUBPRET_CONTROL_BASE_IDX 2 3704#define regHUBPRET1_HUBPRET_MEM_PWR_CTRL 0x0749 3705#define regHUBPRET1_HUBPRET_MEM_PWR_CTRL_BASE_IDX 2 3706#define regHUBPRET1_HUBPRET_MEM_PWR_STATUS 0x074a 3707#define regHUBPRET1_HUBPRET_MEM_PWR_STATUS_BASE_IDX 2 3708#define regHUBPRET1_HUBPRET_READ_LINE_CTRL0 0x074b 3709#define regHUBPRET1_HUBPRET_READ_LINE_CTRL0_BASE_IDX 2 3710#define regHUBPRET1_HUBPRET_READ_LINE_CTRL1 0x074c 3711#define regHUBPRET1_HUBPRET_READ_LINE_CTRL1_BASE_IDX 2 3712#define regHUBPRET1_HUBPRET_READ_LINE0 0x074d 3713#define regHUBPRET1_HUBPRET_READ_LINE0_BASE_IDX 2 3714#define regHUBPRET1_HUBPRET_READ_LINE1 0x074e 3715#define regHUBPRET1_HUBPRET_READ_LINE1_BASE_IDX 2 3716#define regHUBPRET1_HUBPRET_INTERRUPT 0x074f 3717#define regHUBPRET1_HUBPRET_INTERRUPT_BASE_IDX 2 3718#define regHUBPRET1_HUBPRET_READ_LINE_VALUE 0x0750 3719#define regHUBPRET1_HUBPRET_READ_LINE_VALUE_BASE_IDX 2 3720#define regHUBPRET1_HUBPRET_READ_LINE_STATUS 0x0751 3721#define regHUBPRET1_HUBPRET_READ_LINE_STATUS_BASE_IDX 2 3722 3723 3724// addressBlock: dce_dc_dcbubp1_dispdec_cursor0_dispdec 3725// base address: 0x370 3726#define regCURSOR0_1_CURSOR_CONTROL 0x0754 3727#define regCURSOR0_1_CURSOR_CONTROL_BASE_IDX 2 3728#define regCURSOR0_1_CURSOR_SURFACE_ADDRESS 0x0755 3729#define regCURSOR0_1_CURSOR_SURFACE_ADDRESS_BASE_IDX 2 3730#define regCURSOR0_1_CURSOR_SURFACE_ADDRESS_HIGH 0x0756 3731#define regCURSOR0_1_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX 2 3732#define regCURSOR0_1_CURSOR_SIZE 0x0757 3733#define regCURSOR0_1_CURSOR_SIZE_BASE_IDX 2 3734#define regCURSOR0_1_CURSOR_POSITION 0x0758 3735#define regCURSOR0_1_CURSOR_POSITION_BASE_IDX 2 3736#define regCURSOR0_1_CURSOR_HOT_SPOT 0x0759 3737#define regCURSOR0_1_CURSOR_HOT_SPOT_BASE_IDX 2 3738#define regCURSOR0_1_CURSOR_STEREO_CONTROL 0x075a 3739#define regCURSOR0_1_CURSOR_STEREO_CONTROL_BASE_IDX 2 3740#define regCURSOR0_1_CURSOR_DST_OFFSET 0x075b 3741#define regCURSOR0_1_CURSOR_DST_OFFSET_BASE_IDX 2 3742#define regCURSOR0_1_CURSOR_MEM_PWR_CTRL 0x075c 3743#define regCURSOR0_1_CURSOR_MEM_PWR_CTRL_BASE_IDX 2 3744#define regCURSOR0_1_CURSOR_MEM_PWR_STATUS 0x075d 3745#define regCURSOR0_1_CURSOR_MEM_PWR_STATUS_BASE_IDX 2 3746#define regCURSOR0_1_DMDATA_ADDRESS_HIGH 0x075e 3747#define regCURSOR0_1_DMDATA_ADDRESS_HIGH_BASE_IDX 2 3748#define regCURSOR0_1_DMDATA_ADDRESS_LOW 0x075f 3749#define regCURSOR0_1_DMDATA_ADDRESS_LOW_BASE_IDX 2 3750#define regCURSOR0_1_DMDATA_CNTL 0x0760 3751#define regCURSOR0_1_DMDATA_CNTL_BASE_IDX 2 3752#define regCURSOR0_1_DMDATA_QOS_CNTL 0x0761 3753#define regCURSOR0_1_DMDATA_QOS_CNTL_BASE_IDX 2 3754#define regCURSOR0_1_DMDATA_STATUS 0x0762 3755#define regCURSOR0_1_DMDATA_STATUS_BASE_IDX 2 3756#define regCURSOR0_1_DMDATA_SW_CNTL 0x0763 3757#define regCURSOR0_1_DMDATA_SW_CNTL_BASE_IDX 2 3758#define regCURSOR0_1_DMDATA_SW_DATA 0x0764 3759#define regCURSOR0_1_DMDATA_SW_DATA_BASE_IDX 2 3760 3761 3762// addressBlock: dce_dc_dcbubp1_dispdec_hubp_dcperfmon_dc_perfmon_dispdec 3763// base address: 0x1de4 3764#define regDC_PERFMON8_PERFCOUNTER_CNTL 0x0779 3765#define regDC_PERFMON8_PERFCOUNTER_CNTL_BASE_IDX 2 3766#define regDC_PERFMON8_PERFCOUNTER_CNTL2 0x077a 3767#define regDC_PERFMON8_PERFCOUNTER_CNTL2_BASE_IDX 2 3768#define regDC_PERFMON8_PERFCOUNTER_STATE 0x077b 3769#define regDC_PERFMON8_PERFCOUNTER_STATE_BASE_IDX 2 3770#define regDC_PERFMON8_PERFMON_CNTL 0x077c 3771#define regDC_PERFMON8_PERFMON_CNTL_BASE_IDX 2 3772#define regDC_PERFMON8_PERFMON_CNTL2 0x077d 3773#define regDC_PERFMON8_PERFMON_CNTL2_BASE_IDX 2 3774#define regDC_PERFMON8_PERFMON_CVALUE_INT_MISC 0x077e 3775#define regDC_PERFMON8_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 3776#define regDC_PERFMON8_PERFMON_CVALUE_LOW 0x077f 3777#define regDC_PERFMON8_PERFMON_CVALUE_LOW_BASE_IDX 2 3778#define regDC_PERFMON8_PERFMON_HI 0x0780 3779#define regDC_PERFMON8_PERFMON_HI_BASE_IDX 2 3780#define regDC_PERFMON8_PERFMON_LOW 0x0781 3781#define regDC_PERFMON8_PERFMON_LOW_BASE_IDX 2 3782 3783 3784// addressBlock: dce_dc_dcbubp2_dispdec_hubp_dispdec 3785// base address: 0x6e0 3786#define regHUBP2_DCSURF_SURFACE_CONFIG 0x079d 3787#define regHUBP2_DCSURF_SURFACE_CONFIG_BASE_IDX 2 3788#define regHUBP2_DCSURF_ADDR_CONFIG 0x079e 3789#define regHUBP2_DCSURF_ADDR_CONFIG_BASE_IDX 2 3790#define regHUBP2_DCSURF_TILING_CONFIG 0x079f 3791#define regHUBP2_DCSURF_TILING_CONFIG_BASE_IDX 2 3792#define regHUBP2_DCSURF_PRI_VIEWPORT_START 0x07a1 3793#define regHUBP2_DCSURF_PRI_VIEWPORT_START_BASE_IDX 2 3794#define regHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION 0x07a2 3795#define regHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2 3796#define regHUBP2_DCSURF_PRI_VIEWPORT_START_C 0x07a3 3797#define regHUBP2_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX 2 3798#define regHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C 0x07a4 3799#define regHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX 2 3800#define regHUBP2_DCSURF_SEC_VIEWPORT_START 0x07a5 3801#define regHUBP2_DCSURF_SEC_VIEWPORT_START_BASE_IDX 2 3802#define regHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION 0x07a6 3803#define regHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX 2 3804#define regHUBP2_DCSURF_SEC_VIEWPORT_START_C 0x07a7 3805#define regHUBP2_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX 2 3806#define regHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C 0x07a8 3807#define regHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX 2 3808#define regHUBP2_DCHUBP_REQ_SIZE_CONFIG 0x07a9 3809#define regHUBP2_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX 2 3810#define regHUBP2_DCHUBP_REQ_SIZE_CONFIG_C 0x07aa 3811#define regHUBP2_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX 2 3812#define regHUBP2_DCHUBP_CNTL 0x07ab 3813#define regHUBP2_DCHUBP_CNTL_BASE_IDX 2 3814#define regHUBP2_HUBP_CLK_CNTL 0x07ac 3815#define regHUBP2_HUBP_CLK_CNTL_BASE_IDX 2 3816#define regHUBP2_DCHUBP_VMPG_CONFIG 0x07ad 3817#define regHUBP2_DCHUBP_VMPG_CONFIG_BASE_IDX 2 3818#define regHUBP2_DCHUBP_MALL_CONFIG 0x07ae 3819#define regHUBP2_DCHUBP_MALL_CONFIG_BASE_IDX 2 3820#define regHUBP2_DCHUBP_MALL_SUB_VP 0x07af 3821#define regHUBP2_DCHUBP_MALL_SUB_VP_BASE_IDX 2 3822#define regHUBP2_HUBPREQ_DEBUG_DB 0x07b0 3823#define regHUBP2_HUBPREQ_DEBUG_DB_BASE_IDX 2 3824#define regHUBP2_HUBPREQ_DEBUG 0x07b1 3825#define regHUBP2_HUBPREQ_DEBUG_BASE_IDX 2 3826#define regHUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK 0x07b5 3827#define regHUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX 2 3828#define regHUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK 0x07b6 3829#define regHUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX 2 3830#define regHUBP2_HUBP_MALL_STATUS 0x07b7 3831#define regHUBP2_HUBP_MALL_STATUS_BASE_IDX 2 3832 3833 3834// addressBlock: dce_dc_dcbubp2_dispdec_hubpreq_dispdec 3835// base address: 0x6e0 3836#define regHUBPREQ2_DCSURF_SURFACE_PITCH 0x07bf 3837#define regHUBPREQ2_DCSURF_SURFACE_PITCH_BASE_IDX 2 3838#define regHUBPREQ2_DCSURF_SURFACE_PITCH_C 0x07c0 3839#define regHUBPREQ2_DCSURF_SURFACE_PITCH_C_BASE_IDX 2 3840#define regHUBPREQ2_VMID_SETTINGS_0 0x07c1 3841#define regHUBPREQ2_VMID_SETTINGS_0_BASE_IDX 2 3842#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS 0x07c2 3843#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2 3844#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH 0x07c3 3845#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 3846#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C 0x07c4 3847#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX 2 3848#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x07c5 3849#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 3850#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS 0x07c6 3851#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2 3852#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH 0x07c7 3853#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 3854#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C 0x07c8 3855#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX 2 3856#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x07c9 3857#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 3858#define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS 0x07ca 3859#define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX 2 3860#define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH 0x07cb 3861#define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 3862#define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C 0x07cc 3863#define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 3864#define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C 0x07cd 3865#define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 3866#define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS 0x07ce 3867#define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX 2 3868#define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH 0x07cf 3869#define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 3870#define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C 0x07d0 3871#define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 3872#define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C 0x07d1 3873#define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 3874#define regHUBPREQ2_DCSURF_SURFACE_CONTROL 0x07d2 3875#define regHUBPREQ2_DCSURF_SURFACE_CONTROL_BASE_IDX 2 3876#define regHUBPREQ2_DCSURF_FLIP_CONTROL 0x07d3 3877#define regHUBPREQ2_DCSURF_FLIP_CONTROL_BASE_IDX 2 3878#define regHUBPREQ2_DCSURF_FLIP_CONTROL2 0x07d4 3879#define regHUBPREQ2_DCSURF_FLIP_CONTROL2_BASE_IDX 2 3880#define regHUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT 0x07d7 3881#define regHUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX 2 3882#define regHUBPREQ2_DCSURF_SURFACE_INUSE 0x07d8 3883#define regHUBPREQ2_DCSURF_SURFACE_INUSE_BASE_IDX 2 3884#define regHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH 0x07d9 3885#define regHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX 2 3886#define regHUBPREQ2_DCSURF_SURFACE_INUSE_C 0x07da 3887#define regHUBPREQ2_DCSURF_SURFACE_INUSE_C_BASE_IDX 2 3888#define regHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C 0x07db 3889#define regHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX 2 3890#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE 0x07dc 3891#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX 2 3892#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH 0x07dd 3893#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX 2 3894#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C 0x07de 3895#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX 2 3896#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C 0x07df 3897#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX 2 3898#define regHUBPREQ2_DCN_EXPANSION_MODE 0x07e0 3899#define regHUBPREQ2_DCN_EXPANSION_MODE_BASE_IDX 2 3900#define regHUBPREQ2_DCN_TTU_QOS_WM 0x07e1 3901#define regHUBPREQ2_DCN_TTU_QOS_WM_BASE_IDX 2 3902#define regHUBPREQ2_DCN_GLOBAL_TTU_CNTL 0x07e2 3903#define regHUBPREQ2_DCN_GLOBAL_TTU_CNTL_BASE_IDX 2 3904#define regHUBPREQ2_DCN_SURF0_TTU_CNTL0 0x07e3 3905#define regHUBPREQ2_DCN_SURF0_TTU_CNTL0_BASE_IDX 2 3906#define regHUBPREQ2_DCN_SURF0_TTU_CNTL1 0x07e4 3907#define regHUBPREQ2_DCN_SURF0_TTU_CNTL1_BASE_IDX 2 3908#define regHUBPREQ2_DCN_SURF1_TTU_CNTL0 0x07e5 3909#define regHUBPREQ2_DCN_SURF1_TTU_CNTL0_BASE_IDX 2 3910#define regHUBPREQ2_DCN_SURF1_TTU_CNTL1 0x07e6 3911#define regHUBPREQ2_DCN_SURF1_TTU_CNTL1_BASE_IDX 2 3912#define regHUBPREQ2_DCN_CUR0_TTU_CNTL0 0x07e7 3913#define regHUBPREQ2_DCN_CUR0_TTU_CNTL0_BASE_IDX 2 3914#define regHUBPREQ2_DCN_CUR0_TTU_CNTL1 0x07e8 3915#define regHUBPREQ2_DCN_CUR0_TTU_CNTL1_BASE_IDX 2 3916#define regHUBPREQ2_DCN_CUR1_TTU_CNTL0 0x07e9 3917#define regHUBPREQ2_DCN_CUR1_TTU_CNTL0_BASE_IDX 2 3918#define regHUBPREQ2_DCN_CUR1_TTU_CNTL1 0x07ea 3919#define regHUBPREQ2_DCN_CUR1_TTU_CNTL1_BASE_IDX 2 3920#define regHUBPREQ2_DCN_DMDATA_VM_CNTL 0x07eb 3921#define regHUBPREQ2_DCN_DMDATA_VM_CNTL_BASE_IDX 2 3922#define regHUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR 0x07ec 3923#define regHUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 2 3924#define regHUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR 0x07ed 3925#define regHUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 2 3926#define regHUBPREQ2_DCN_VM_MX_L1_TLB_CNTL 0x07fa 3927#define regHUBPREQ2_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX 2 3928#define regHUBPREQ2_BLANK_OFFSET_0 0x07fb 3929#define regHUBPREQ2_BLANK_OFFSET_0_BASE_IDX 2 3930#define regHUBPREQ2_BLANK_OFFSET_1 0x07fc 3931#define regHUBPREQ2_BLANK_OFFSET_1_BASE_IDX 2 3932#define regHUBPREQ2_DST_DIMENSIONS 0x07fd 3933#define regHUBPREQ2_DST_DIMENSIONS_BASE_IDX 2 3934#define regHUBPREQ2_DST_AFTER_SCALER 0x07fe 3935#define regHUBPREQ2_DST_AFTER_SCALER_BASE_IDX 2 3936#define regHUBPREQ2_PREFETCH_SETTINGS 0x07ff 3937#define regHUBPREQ2_PREFETCH_SETTINGS_BASE_IDX 2 3938#define regHUBPREQ2_PREFETCH_SETTINGS_C 0x0800 3939#define regHUBPREQ2_PREFETCH_SETTINGS_C_BASE_IDX 2 3940#define regHUBPREQ2_VBLANK_PARAMETERS_0 0x0801 3941#define regHUBPREQ2_VBLANK_PARAMETERS_0_BASE_IDX 2 3942#define regHUBPREQ2_VBLANK_PARAMETERS_1 0x0802 3943#define regHUBPREQ2_VBLANK_PARAMETERS_1_BASE_IDX 2 3944#define regHUBPREQ2_VBLANK_PARAMETERS_2 0x0803 3945#define regHUBPREQ2_VBLANK_PARAMETERS_2_BASE_IDX 2 3946#define regHUBPREQ2_VBLANK_PARAMETERS_3 0x0804 3947#define regHUBPREQ2_VBLANK_PARAMETERS_3_BASE_IDX 2 3948#define regHUBPREQ2_VBLANK_PARAMETERS_4 0x0805 3949#define regHUBPREQ2_VBLANK_PARAMETERS_4_BASE_IDX 2 3950#define regHUBPREQ2_FLIP_PARAMETERS_0 0x0806 3951#define regHUBPREQ2_FLIP_PARAMETERS_0_BASE_IDX 2 3952#define regHUBPREQ2_FLIP_PARAMETERS_1 0x0807 3953#define regHUBPREQ2_FLIP_PARAMETERS_1_BASE_IDX 2 3954#define regHUBPREQ2_FLIP_PARAMETERS_2 0x0808 3955#define regHUBPREQ2_FLIP_PARAMETERS_2_BASE_IDX 2 3956#define regHUBPREQ2_NOM_PARAMETERS_0 0x0809 3957#define regHUBPREQ2_NOM_PARAMETERS_0_BASE_IDX 2 3958#define regHUBPREQ2_NOM_PARAMETERS_1 0x080a 3959#define regHUBPREQ2_NOM_PARAMETERS_1_BASE_IDX 2 3960#define regHUBPREQ2_NOM_PARAMETERS_2 0x080b 3961#define regHUBPREQ2_NOM_PARAMETERS_2_BASE_IDX 2 3962#define regHUBPREQ2_NOM_PARAMETERS_3 0x080c 3963#define regHUBPREQ2_NOM_PARAMETERS_3_BASE_IDX 2 3964#define regHUBPREQ2_NOM_PARAMETERS_4 0x080d 3965#define regHUBPREQ2_NOM_PARAMETERS_4_BASE_IDX 2 3966#define regHUBPREQ2_NOM_PARAMETERS_5 0x080e 3967#define regHUBPREQ2_NOM_PARAMETERS_5_BASE_IDX 2 3968#define regHUBPREQ2_NOM_PARAMETERS_6 0x080f 3969#define regHUBPREQ2_NOM_PARAMETERS_6_BASE_IDX 2 3970#define regHUBPREQ2_NOM_PARAMETERS_7 0x0810 3971#define regHUBPREQ2_NOM_PARAMETERS_7_BASE_IDX 2 3972#define regHUBPREQ2_PER_LINE_DELIVERY_PRE 0x0811 3973#define regHUBPREQ2_PER_LINE_DELIVERY_PRE_BASE_IDX 2 3974#define regHUBPREQ2_PER_LINE_DELIVERY 0x0812 3975#define regHUBPREQ2_PER_LINE_DELIVERY_BASE_IDX 2 3976#define regHUBPREQ2_CURSOR_SETTINGS 0x0813 3977#define regHUBPREQ2_CURSOR_SETTINGS_BASE_IDX 2 3978#define regHUBPREQ2_REF_FREQ_TO_PIX_FREQ 0x0814 3979#define regHUBPREQ2_REF_FREQ_TO_PIX_FREQ_BASE_IDX 2 3980#define regHUBPREQ2_DST_Y_DELTA_DRQ_LIMIT 0x0815 3981#define regHUBPREQ2_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX 2 3982#define regHUBPREQ2_HUBPREQ_MEM_PWR_CTRL 0x0816 3983#define regHUBPREQ2_HUBPREQ_MEM_PWR_CTRL_BASE_IDX 2 3984#define regHUBPREQ2_HUBPREQ_MEM_PWR_STATUS 0x0817 3985#define regHUBPREQ2_HUBPREQ_MEM_PWR_STATUS_BASE_IDX 2 3986#define regHUBPREQ2_VBLANK_PARAMETERS_5 0x081a 3987#define regHUBPREQ2_VBLANK_PARAMETERS_5_BASE_IDX 2 3988#define regHUBPREQ2_VBLANK_PARAMETERS_6 0x081b 3989#define regHUBPREQ2_VBLANK_PARAMETERS_6_BASE_IDX 2 3990#define regHUBPREQ2_FLIP_PARAMETERS_3 0x081c 3991#define regHUBPREQ2_FLIP_PARAMETERS_3_BASE_IDX 2 3992#define regHUBPREQ2_FLIP_PARAMETERS_4 0x081d 3993#define regHUBPREQ2_FLIP_PARAMETERS_4_BASE_IDX 2 3994#define regHUBPREQ2_FLIP_PARAMETERS_5 0x081e 3995#define regHUBPREQ2_FLIP_PARAMETERS_5_BASE_IDX 2 3996#define regHUBPREQ2_FLIP_PARAMETERS_6 0x081f 3997#define regHUBPREQ2_FLIP_PARAMETERS_6_BASE_IDX 2 3998#define regHUBPREQ2_UCLK_PSTATE_FORCE 0x0820 3999#define regHUBPREQ2_UCLK_PSTATE_FORCE_BASE_IDX 2 4000#define regHUBPREQ2_HUBPREQ_STATUS_REG0 0x0821 4001#define regHUBPREQ2_HUBPREQ_STATUS_REG0_BASE_IDX 2 4002#define regHUBPREQ2_HUBPREQ_STATUS_REG1 0x0822 4003#define regHUBPREQ2_HUBPREQ_STATUS_REG1_BASE_IDX 2 4004#define regHUBPREQ2_HUBPREQ_STATUS_REG2 0x0823 4005#define regHUBPREQ2_HUBPREQ_STATUS_REG2_BASE_IDX 2 4006 4007 4008// addressBlock: dce_dc_dcbubp2_dispdec_hubpret_dispdec 4009// base address: 0x6e0 4010#define regHUBPRET2_HUBPRET_CONTROL 0x0824 4011#define regHUBPRET2_HUBPRET_CONTROL_BASE_IDX 2 4012#define regHUBPRET2_HUBPRET_MEM_PWR_CTRL 0x0825 4013#define regHUBPRET2_HUBPRET_MEM_PWR_CTRL_BASE_IDX 2 4014#define regHUBPRET2_HUBPRET_MEM_PWR_STATUS 0x0826 4015#define regHUBPRET2_HUBPRET_MEM_PWR_STATUS_BASE_IDX 2 4016#define regHUBPRET2_HUBPRET_READ_LINE_CTRL0 0x0827 4017#define regHUBPRET2_HUBPRET_READ_LINE_CTRL0_BASE_IDX 2 4018#define regHUBPRET2_HUBPRET_READ_LINE_CTRL1 0x0828 4019#define regHUBPRET2_HUBPRET_READ_LINE_CTRL1_BASE_IDX 2 4020#define regHUBPRET2_HUBPRET_READ_LINE0 0x0829 4021#define regHUBPRET2_HUBPRET_READ_LINE0_BASE_IDX 2 4022#define regHUBPRET2_HUBPRET_READ_LINE1 0x082a 4023#define regHUBPRET2_HUBPRET_READ_LINE1_BASE_IDX 2 4024#define regHUBPRET2_HUBPRET_INTERRUPT 0x082b 4025#define regHUBPRET2_HUBPRET_INTERRUPT_BASE_IDX 2 4026#define regHUBPRET2_HUBPRET_READ_LINE_VALUE 0x082c 4027#define regHUBPRET2_HUBPRET_READ_LINE_VALUE_BASE_IDX 2 4028#define regHUBPRET2_HUBPRET_READ_LINE_STATUS 0x082d 4029#define regHUBPRET2_HUBPRET_READ_LINE_STATUS_BASE_IDX 2 4030 4031 4032// addressBlock: dce_dc_dcbubp2_dispdec_cursor0_dispdec 4033// base address: 0x6e0 4034#define regCURSOR0_2_CURSOR_CONTROL 0x0830 4035#define regCURSOR0_2_CURSOR_CONTROL_BASE_IDX 2 4036#define regCURSOR0_2_CURSOR_SURFACE_ADDRESS 0x0831 4037#define regCURSOR0_2_CURSOR_SURFACE_ADDRESS_BASE_IDX 2 4038#define regCURSOR0_2_CURSOR_SURFACE_ADDRESS_HIGH 0x0832 4039#define regCURSOR0_2_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX 2 4040#define regCURSOR0_2_CURSOR_SIZE 0x0833 4041#define regCURSOR0_2_CURSOR_SIZE_BASE_IDX 2 4042#define regCURSOR0_2_CURSOR_POSITION 0x0834 4043#define regCURSOR0_2_CURSOR_POSITION_BASE_IDX 2 4044#define regCURSOR0_2_CURSOR_HOT_SPOT 0x0835 4045#define regCURSOR0_2_CURSOR_HOT_SPOT_BASE_IDX 2 4046#define regCURSOR0_2_CURSOR_STEREO_CONTROL 0x0836 4047#define regCURSOR0_2_CURSOR_STEREO_CONTROL_BASE_IDX 2 4048#define regCURSOR0_2_CURSOR_DST_OFFSET 0x0837 4049#define regCURSOR0_2_CURSOR_DST_OFFSET_BASE_IDX 2 4050#define regCURSOR0_2_CURSOR_MEM_PWR_CTRL 0x0838 4051#define regCURSOR0_2_CURSOR_MEM_PWR_CTRL_BASE_IDX 2 4052#define regCURSOR0_2_CURSOR_MEM_PWR_STATUS 0x0839 4053#define regCURSOR0_2_CURSOR_MEM_PWR_STATUS_BASE_IDX 2 4054#define regCURSOR0_2_DMDATA_ADDRESS_HIGH 0x083a 4055#define regCURSOR0_2_DMDATA_ADDRESS_HIGH_BASE_IDX 2 4056#define regCURSOR0_2_DMDATA_ADDRESS_LOW 0x083b 4057#define regCURSOR0_2_DMDATA_ADDRESS_LOW_BASE_IDX 2 4058#define regCURSOR0_2_DMDATA_CNTL 0x083c 4059#define regCURSOR0_2_DMDATA_CNTL_BASE_IDX 2 4060#define regCURSOR0_2_DMDATA_QOS_CNTL 0x083d 4061#define regCURSOR0_2_DMDATA_QOS_CNTL_BASE_IDX 2 4062#define regCURSOR0_2_DMDATA_STATUS 0x083e 4063#define regCURSOR0_2_DMDATA_STATUS_BASE_IDX 2 4064#define regCURSOR0_2_DMDATA_SW_CNTL 0x083f 4065#define regCURSOR0_2_DMDATA_SW_CNTL_BASE_IDX 2 4066#define regCURSOR0_2_DMDATA_SW_DATA 0x0840 4067#define regCURSOR0_2_DMDATA_SW_DATA_BASE_IDX 2 4068 4069 4070// addressBlock: dce_dc_dcbubp2_dispdec_hubp_dcperfmon_dc_perfmon_dispdec 4071// base address: 0x2154 4072#define regDC_PERFMON9_PERFCOUNTER_CNTL 0x0855 4073#define regDC_PERFMON9_PERFCOUNTER_CNTL_BASE_IDX 2 4074#define regDC_PERFMON9_PERFCOUNTER_CNTL2 0x0856 4075#define regDC_PERFMON9_PERFCOUNTER_CNTL2_BASE_IDX 2 4076#define regDC_PERFMON9_PERFCOUNTER_STATE 0x0857 4077#define regDC_PERFMON9_PERFCOUNTER_STATE_BASE_IDX 2 4078#define regDC_PERFMON9_PERFMON_CNTL 0x0858 4079#define regDC_PERFMON9_PERFMON_CNTL_BASE_IDX 2 4080#define regDC_PERFMON9_PERFMON_CNTL2 0x0859 4081#define regDC_PERFMON9_PERFMON_CNTL2_BASE_IDX 2 4082#define regDC_PERFMON9_PERFMON_CVALUE_INT_MISC 0x085a 4083#define regDC_PERFMON9_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 4084#define regDC_PERFMON9_PERFMON_CVALUE_LOW 0x085b 4085#define regDC_PERFMON9_PERFMON_CVALUE_LOW_BASE_IDX 2 4086#define regDC_PERFMON9_PERFMON_HI 0x085c 4087#define regDC_PERFMON9_PERFMON_HI_BASE_IDX 2 4088#define regDC_PERFMON9_PERFMON_LOW 0x085d 4089#define regDC_PERFMON9_PERFMON_LOW_BASE_IDX 2 4090 4091 4092// addressBlock: dce_dc_dcbubp3_dispdec_hubp_dispdec 4093// base address: 0xa50 4094#define regHUBP3_DCSURF_SURFACE_CONFIG 0x0879 4095#define regHUBP3_DCSURF_SURFACE_CONFIG_BASE_IDX 2 4096#define regHUBP3_DCSURF_ADDR_CONFIG 0x087a 4097#define regHUBP3_DCSURF_ADDR_CONFIG_BASE_IDX 2 4098#define regHUBP3_DCSURF_TILING_CONFIG 0x087b 4099#define regHUBP3_DCSURF_TILING_CONFIG_BASE_IDX 2 4100#define regHUBP3_DCSURF_PRI_VIEWPORT_START 0x087d 4101#define regHUBP3_DCSURF_PRI_VIEWPORT_START_BASE_IDX 2 4102#define regHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION 0x087e 4103#define regHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2 4104#define regHUBP3_DCSURF_PRI_VIEWPORT_START_C 0x087f 4105#define regHUBP3_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX 2 4106#define regHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C 0x0880 4107#define regHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX 2 4108#define regHUBP3_DCSURF_SEC_VIEWPORT_START 0x0881 4109#define regHUBP3_DCSURF_SEC_VIEWPORT_START_BASE_IDX 2 4110#define regHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION 0x0882 4111#define regHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX 2 4112#define regHUBP3_DCSURF_SEC_VIEWPORT_START_C 0x0883 4113#define regHUBP3_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX 2 4114#define regHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C 0x0884 4115#define regHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX 2 4116#define regHUBP3_DCHUBP_REQ_SIZE_CONFIG 0x0885 4117#define regHUBP3_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX 2 4118#define regHUBP3_DCHUBP_REQ_SIZE_CONFIG_C 0x0886 4119#define regHUBP3_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX 2 4120#define regHUBP3_DCHUBP_CNTL 0x0887 4121#define regHUBP3_DCHUBP_CNTL_BASE_IDX 2 4122#define regHUBP3_HUBP_CLK_CNTL 0x0888 4123#define regHUBP3_HUBP_CLK_CNTL_BASE_IDX 2 4124#define regHUBP3_DCHUBP_VMPG_CONFIG 0x0889 4125#define regHUBP3_DCHUBP_VMPG_CONFIG_BASE_IDX 2 4126#define regHUBP3_DCHUBP_MALL_CONFIG 0x088a 4127#define regHUBP3_DCHUBP_MALL_CONFIG_BASE_IDX 2 4128#define regHUBP3_DCHUBP_MALL_SUB_VP 0x088b 4129#define regHUBP3_DCHUBP_MALL_SUB_VP_BASE_IDX 2 4130#define regHUBP3_HUBPREQ_DEBUG_DB 0x088c 4131#define regHUBP3_HUBPREQ_DEBUG_DB_BASE_IDX 2 4132#define regHUBP3_HUBPREQ_DEBUG 0x088d 4133#define regHUBP3_HUBPREQ_DEBUG_BASE_IDX 2 4134#define regHUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK 0x0891 4135#define regHUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX 2 4136#define regHUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK 0x0892 4137#define regHUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX 2 4138#define regHUBP3_HUBP_MALL_STATUS 0x0893 4139#define regHUBP3_HUBP_MALL_STATUS_BASE_IDX 2 4140 4141 4142// addressBlock: dce_dc_dcbubp3_dispdec_hubpreq_dispdec 4143// base address: 0xa50 4144#define regHUBPREQ3_DCSURF_SURFACE_PITCH 0x089b 4145#define regHUBPREQ3_DCSURF_SURFACE_PITCH_BASE_IDX 2 4146#define regHUBPREQ3_DCSURF_SURFACE_PITCH_C 0x089c 4147#define regHUBPREQ3_DCSURF_SURFACE_PITCH_C_BASE_IDX 2 4148#define regHUBPREQ3_VMID_SETTINGS_0 0x089d 4149#define regHUBPREQ3_VMID_SETTINGS_0_BASE_IDX 2 4150#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS 0x089e 4151#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2 4152#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH 0x089f 4153#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 4154#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C 0x08a0 4155#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX 2 4156#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x08a1 4157#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 4158#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS 0x08a2 4159#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2 4160#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH 0x08a3 4161#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 4162#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C 0x08a4 4163#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX 2 4164#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x08a5 4165#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 4166#define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS 0x08a6 4167#define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX 2 4168#define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH 0x08a7 4169#define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 4170#define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C 0x08a8 4171#define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 4172#define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C 0x08a9 4173#define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 4174#define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS 0x08aa 4175#define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX 2 4176#define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH 0x08ab 4177#define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 4178#define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C 0x08ac 4179#define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 4180#define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C 0x08ad 4181#define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 4182#define regHUBPREQ3_DCSURF_SURFACE_CONTROL 0x08ae 4183#define regHUBPREQ3_DCSURF_SURFACE_CONTROL_BASE_IDX 2 4184#define regHUBPREQ3_DCSURF_FLIP_CONTROL 0x08af 4185#define regHUBPREQ3_DCSURF_FLIP_CONTROL_BASE_IDX 2 4186#define regHUBPREQ3_DCSURF_FLIP_CONTROL2 0x08b0 4187#define regHUBPREQ3_DCSURF_FLIP_CONTROL2_BASE_IDX 2 4188#define regHUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT 0x08b3 4189#define regHUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX 2 4190#define regHUBPREQ3_DCSURF_SURFACE_INUSE 0x08b4 4191#define regHUBPREQ3_DCSURF_SURFACE_INUSE_BASE_IDX 2 4192#define regHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH 0x08b5 4193#define regHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX 2 4194#define regHUBPREQ3_DCSURF_SURFACE_INUSE_C 0x08b6 4195#define regHUBPREQ3_DCSURF_SURFACE_INUSE_C_BASE_IDX 2 4196#define regHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C 0x08b7 4197#define regHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX 2 4198#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE 0x08b8 4199#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX 2 4200#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH 0x08b9 4201#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX 2 4202#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C 0x08ba 4203#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX 2 4204#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C 0x08bb 4205#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX 2 4206#define regHUBPREQ3_DCN_EXPANSION_MODE 0x08bc 4207#define regHUBPREQ3_DCN_EXPANSION_MODE_BASE_IDX 2 4208#define regHUBPREQ3_DCN_TTU_QOS_WM 0x08bd 4209#define regHUBPREQ3_DCN_TTU_QOS_WM_BASE_IDX 2 4210#define regHUBPREQ3_DCN_GLOBAL_TTU_CNTL 0x08be 4211#define regHUBPREQ3_DCN_GLOBAL_TTU_CNTL_BASE_IDX 2 4212#define regHUBPREQ3_DCN_SURF0_TTU_CNTL0 0x08bf 4213#define regHUBPREQ3_DCN_SURF0_TTU_CNTL0_BASE_IDX 2 4214#define regHUBPREQ3_DCN_SURF0_TTU_CNTL1 0x08c0 4215#define regHUBPREQ3_DCN_SURF0_TTU_CNTL1_BASE_IDX 2 4216#define regHUBPREQ3_DCN_SURF1_TTU_CNTL0 0x08c1 4217#define regHUBPREQ3_DCN_SURF1_TTU_CNTL0_BASE_IDX 2 4218#define regHUBPREQ3_DCN_SURF1_TTU_CNTL1 0x08c2 4219#define regHUBPREQ3_DCN_SURF1_TTU_CNTL1_BASE_IDX 2 4220#define regHUBPREQ3_DCN_CUR0_TTU_CNTL0 0x08c3 4221#define regHUBPREQ3_DCN_CUR0_TTU_CNTL0_BASE_IDX 2 4222#define regHUBPREQ3_DCN_CUR0_TTU_CNTL1 0x08c4 4223#define regHUBPREQ3_DCN_CUR0_TTU_CNTL1_BASE_IDX 2 4224#define regHUBPREQ3_DCN_CUR1_TTU_CNTL0 0x08c5 4225#define regHUBPREQ3_DCN_CUR1_TTU_CNTL0_BASE_IDX 2 4226#define regHUBPREQ3_DCN_CUR1_TTU_CNTL1 0x08c6 4227#define regHUBPREQ3_DCN_CUR1_TTU_CNTL1_BASE_IDX 2 4228#define regHUBPREQ3_DCN_DMDATA_VM_CNTL 0x08c7 4229#define regHUBPREQ3_DCN_DMDATA_VM_CNTL_BASE_IDX 2 4230#define regHUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR 0x08c8 4231#define regHUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 2 4232#define regHUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR 0x08c9 4233#define regHUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 2 4234#define regHUBPREQ3_DCN_VM_MX_L1_TLB_CNTL 0x08d6 4235#define regHUBPREQ3_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX 2 4236#define regHUBPREQ3_BLANK_OFFSET_0 0x08d7 4237#define regHUBPREQ3_BLANK_OFFSET_0_BASE_IDX 2 4238#define regHUBPREQ3_BLANK_OFFSET_1 0x08d8 4239#define regHUBPREQ3_BLANK_OFFSET_1_BASE_IDX 2 4240#define regHUBPREQ3_DST_DIMENSIONS 0x08d9 4241#define regHUBPREQ3_DST_DIMENSIONS_BASE_IDX 2 4242#define regHUBPREQ3_DST_AFTER_SCALER 0x08da 4243#define regHUBPREQ3_DST_AFTER_SCALER_BASE_IDX 2 4244#define regHUBPREQ3_PREFETCH_SETTINGS 0x08db 4245#define regHUBPREQ3_PREFETCH_SETTINGS_BASE_IDX 2 4246#define regHUBPREQ3_PREFETCH_SETTINGS_C 0x08dc 4247#define regHUBPREQ3_PREFETCH_SETTINGS_C_BASE_IDX 2 4248#define regHUBPREQ3_VBLANK_PARAMETERS_0 0x08dd 4249#define regHUBPREQ3_VBLANK_PARAMETERS_0_BASE_IDX 2 4250#define regHUBPREQ3_VBLANK_PARAMETERS_1 0x08de 4251#define regHUBPREQ3_VBLANK_PARAMETERS_1_BASE_IDX 2 4252#define regHUBPREQ3_VBLANK_PARAMETERS_2 0x08df 4253#define regHUBPREQ3_VBLANK_PARAMETERS_2_BASE_IDX 2 4254#define regHUBPREQ3_VBLANK_PARAMETERS_3 0x08e0 4255#define regHUBPREQ3_VBLANK_PARAMETERS_3_BASE_IDX 2 4256#define regHUBPREQ3_VBLANK_PARAMETERS_4 0x08e1 4257#define regHUBPREQ3_VBLANK_PARAMETERS_4_BASE_IDX 2 4258#define regHUBPREQ3_FLIP_PARAMETERS_0 0x08e2 4259#define regHUBPREQ3_FLIP_PARAMETERS_0_BASE_IDX 2 4260#define regHUBPREQ3_FLIP_PARAMETERS_1 0x08e3 4261#define regHUBPREQ3_FLIP_PARAMETERS_1_BASE_IDX 2 4262#define regHUBPREQ3_FLIP_PARAMETERS_2 0x08e4 4263#define regHUBPREQ3_FLIP_PARAMETERS_2_BASE_IDX 2 4264#define regHUBPREQ3_NOM_PARAMETERS_0 0x08e5 4265#define regHUBPREQ3_NOM_PARAMETERS_0_BASE_IDX 2 4266#define regHUBPREQ3_NOM_PARAMETERS_1 0x08e6 4267#define regHUBPREQ3_NOM_PARAMETERS_1_BASE_IDX 2 4268#define regHUBPREQ3_NOM_PARAMETERS_2 0x08e7 4269#define regHUBPREQ3_NOM_PARAMETERS_2_BASE_IDX 2 4270#define regHUBPREQ3_NOM_PARAMETERS_3 0x08e8 4271#define regHUBPREQ3_NOM_PARAMETERS_3_BASE_IDX 2 4272#define regHUBPREQ3_NOM_PARAMETERS_4 0x08e9 4273#define regHUBPREQ3_NOM_PARAMETERS_4_BASE_IDX 2 4274#define regHUBPREQ3_NOM_PARAMETERS_5 0x08ea 4275#define regHUBPREQ3_NOM_PARAMETERS_5_BASE_IDX 2 4276#define regHUBPREQ3_NOM_PARAMETERS_6 0x08eb 4277#define regHUBPREQ3_NOM_PARAMETERS_6_BASE_IDX 2 4278#define regHUBPREQ3_NOM_PARAMETERS_7 0x08ec 4279#define regHUBPREQ3_NOM_PARAMETERS_7_BASE_IDX 2 4280#define regHUBPREQ3_PER_LINE_DELIVERY_PRE 0x08ed 4281#define regHUBPREQ3_PER_LINE_DELIVERY_PRE_BASE_IDX 2 4282#define regHUBPREQ3_PER_LINE_DELIVERY 0x08ee 4283#define regHUBPREQ3_PER_LINE_DELIVERY_BASE_IDX 2 4284#define regHUBPREQ3_CURSOR_SETTINGS 0x08ef 4285#define regHUBPREQ3_CURSOR_SETTINGS_BASE_IDX 2 4286#define regHUBPREQ3_REF_FREQ_TO_PIX_FREQ 0x08f0 4287#define regHUBPREQ3_REF_FREQ_TO_PIX_FREQ_BASE_IDX 2 4288#define regHUBPREQ3_DST_Y_DELTA_DRQ_LIMIT 0x08f1 4289#define regHUBPREQ3_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX 2 4290#define regHUBPREQ3_HUBPREQ_MEM_PWR_CTRL 0x08f2 4291#define regHUBPREQ3_HUBPREQ_MEM_PWR_CTRL_BASE_IDX 2 4292#define regHUBPREQ3_HUBPREQ_MEM_PWR_STATUS 0x08f3 4293#define regHUBPREQ3_HUBPREQ_MEM_PWR_STATUS_BASE_IDX 2 4294#define regHUBPREQ3_VBLANK_PARAMETERS_5 0x08f6 4295#define regHUBPREQ3_VBLANK_PARAMETERS_5_BASE_IDX 2 4296#define regHUBPREQ3_VBLANK_PARAMETERS_6 0x08f7 4297#define regHUBPREQ3_VBLANK_PARAMETERS_6_BASE_IDX 2 4298#define regHUBPREQ3_FLIP_PARAMETERS_3 0x08f8 4299#define regHUBPREQ3_FLIP_PARAMETERS_3_BASE_IDX 2 4300#define regHUBPREQ3_FLIP_PARAMETERS_4 0x08f9 4301#define regHUBPREQ3_FLIP_PARAMETERS_4_BASE_IDX 2 4302#define regHUBPREQ3_FLIP_PARAMETERS_5 0x08fa 4303#define regHUBPREQ3_FLIP_PARAMETERS_5_BASE_IDX 2 4304#define regHUBPREQ3_FLIP_PARAMETERS_6 0x08fb 4305#define regHUBPREQ3_FLIP_PARAMETERS_6_BASE_IDX 2 4306#define regHUBPREQ3_UCLK_PSTATE_FORCE 0x08fc 4307#define regHUBPREQ3_UCLK_PSTATE_FORCE_BASE_IDX 2 4308#define regHUBPREQ3_HUBPREQ_STATUS_REG0 0x08fd 4309#define regHUBPREQ3_HUBPREQ_STATUS_REG0_BASE_IDX 2 4310#define regHUBPREQ3_HUBPREQ_STATUS_REG1 0x08fe 4311#define regHUBPREQ3_HUBPREQ_STATUS_REG1_BASE_IDX 2 4312#define regHUBPREQ3_HUBPREQ_STATUS_REG2 0x08ff 4313#define regHUBPREQ3_HUBPREQ_STATUS_REG2_BASE_IDX 2 4314 4315 4316// addressBlock: dce_dc_dcbubp3_dispdec_hubpret_dispdec 4317// base address: 0xa50 4318#define regHUBPRET3_HUBPRET_CONTROL 0x0900 4319#define regHUBPRET3_HUBPRET_CONTROL_BASE_IDX 2 4320#define regHUBPRET3_HUBPRET_MEM_PWR_CTRL 0x0901 4321#define regHUBPRET3_HUBPRET_MEM_PWR_CTRL_BASE_IDX 2 4322#define regHUBPRET3_HUBPRET_MEM_PWR_STATUS 0x0902 4323#define regHUBPRET3_HUBPRET_MEM_PWR_STATUS_BASE_IDX 2 4324#define regHUBPRET3_HUBPRET_READ_LINE_CTRL0 0x0903 4325#define regHUBPRET3_HUBPRET_READ_LINE_CTRL0_BASE_IDX 2 4326#define regHUBPRET3_HUBPRET_READ_LINE_CTRL1 0x0904 4327#define regHUBPRET3_HUBPRET_READ_LINE_CTRL1_BASE_IDX 2 4328#define regHUBPRET3_HUBPRET_READ_LINE0 0x0905 4329#define regHUBPRET3_HUBPRET_READ_LINE0_BASE_IDX 2 4330#define regHUBPRET3_HUBPRET_READ_LINE1 0x0906 4331#define regHUBPRET3_HUBPRET_READ_LINE1_BASE_IDX 2 4332#define regHUBPRET3_HUBPRET_INTERRUPT 0x0907 4333#define regHUBPRET3_HUBPRET_INTERRUPT_BASE_IDX 2 4334#define regHUBPRET3_HUBPRET_READ_LINE_VALUE 0x0908 4335#define regHUBPRET3_HUBPRET_READ_LINE_VALUE_BASE_IDX 2 4336#define regHUBPRET3_HUBPRET_READ_LINE_STATUS 0x0909 4337#define regHUBPRET3_HUBPRET_READ_LINE_STATUS_BASE_IDX 2 4338 4339 4340// addressBlock: dce_dc_dcbubp3_dispdec_cursor0_dispdec 4341// base address: 0xa50 4342#define regCURSOR0_3_CURSOR_CONTROL 0x090c 4343#define regCURSOR0_3_CURSOR_CONTROL_BASE_IDX 2 4344#define regCURSOR0_3_CURSOR_SURFACE_ADDRESS 0x090d 4345#define regCURSOR0_3_CURSOR_SURFACE_ADDRESS_BASE_IDX 2 4346#define regCURSOR0_3_CURSOR_SURFACE_ADDRESS_HIGH 0x090e 4347#define regCURSOR0_3_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX 2 4348#define regCURSOR0_3_CURSOR_SIZE 0x090f 4349#define regCURSOR0_3_CURSOR_SIZE_BASE_IDX 2 4350#define regCURSOR0_3_CURSOR_POSITION 0x0910 4351#define regCURSOR0_3_CURSOR_POSITION_BASE_IDX 2 4352#define regCURSOR0_3_CURSOR_HOT_SPOT 0x0911 4353#define regCURSOR0_3_CURSOR_HOT_SPOT_BASE_IDX 2 4354#define regCURSOR0_3_CURSOR_STEREO_CONTROL 0x0912 4355#define regCURSOR0_3_CURSOR_STEREO_CONTROL_BASE_IDX 2 4356#define regCURSOR0_3_CURSOR_DST_OFFSET 0x0913 4357#define regCURSOR0_3_CURSOR_DST_OFFSET_BASE_IDX 2 4358#define regCURSOR0_3_CURSOR_MEM_PWR_CTRL 0x0914 4359#define regCURSOR0_3_CURSOR_MEM_PWR_CTRL_BASE_IDX 2 4360#define regCURSOR0_3_CURSOR_MEM_PWR_STATUS 0x0915 4361#define regCURSOR0_3_CURSOR_MEM_PWR_STATUS_BASE_IDX 2 4362#define regCURSOR0_3_DMDATA_ADDRESS_HIGH 0x0916 4363#define regCURSOR0_3_DMDATA_ADDRESS_HIGH_BASE_IDX 2 4364#define regCURSOR0_3_DMDATA_ADDRESS_LOW 0x0917 4365#define regCURSOR0_3_DMDATA_ADDRESS_LOW_BASE_IDX 2 4366#define regCURSOR0_3_DMDATA_CNTL 0x0918 4367#define regCURSOR0_3_DMDATA_CNTL_BASE_IDX 2 4368#define regCURSOR0_3_DMDATA_QOS_CNTL 0x0919 4369#define regCURSOR0_3_DMDATA_QOS_CNTL_BASE_IDX 2 4370#define regCURSOR0_3_DMDATA_STATUS 0x091a 4371#define regCURSOR0_3_DMDATA_STATUS_BASE_IDX 2 4372#define regCURSOR0_3_DMDATA_SW_CNTL 0x091b 4373#define regCURSOR0_3_DMDATA_SW_CNTL_BASE_IDX 2 4374#define regCURSOR0_3_DMDATA_SW_DATA 0x091c 4375#define regCURSOR0_3_DMDATA_SW_DATA_BASE_IDX 2 4376 4377 4378// addressBlock: dce_dc_dcbubp3_dispdec_hubp_dcperfmon_dc_perfmon_dispdec 4379// base address: 0x24c4 4380#define regDC_PERFMON10_PERFCOUNTER_CNTL 0x0931 4381#define regDC_PERFMON10_PERFCOUNTER_CNTL_BASE_IDX 2 4382#define regDC_PERFMON10_PERFCOUNTER_CNTL2 0x0932 4383#define regDC_PERFMON10_PERFCOUNTER_CNTL2_BASE_IDX 2 4384#define regDC_PERFMON10_PERFCOUNTER_STATE 0x0933 4385#define regDC_PERFMON10_PERFCOUNTER_STATE_BASE_IDX 2 4386#define regDC_PERFMON10_PERFMON_CNTL 0x0934 4387#define regDC_PERFMON10_PERFMON_CNTL_BASE_IDX 2 4388#define regDC_PERFMON10_PERFMON_CNTL2 0x0935 4389#define regDC_PERFMON10_PERFMON_CNTL2_BASE_IDX 2 4390#define regDC_PERFMON10_PERFMON_CVALUE_INT_MISC 0x0936 4391#define regDC_PERFMON10_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 4392#define regDC_PERFMON10_PERFMON_CVALUE_LOW 0x0937 4393#define regDC_PERFMON10_PERFMON_CVALUE_LOW_BASE_IDX 2 4394#define regDC_PERFMON10_PERFMON_HI 0x0938 4395#define regDC_PERFMON10_PERFMON_HI_BASE_IDX 2 4396#define regDC_PERFMON10_PERFMON_LOW 0x0939 4397#define regDC_PERFMON10_PERFMON_LOW_BASE_IDX 2 4398 4399 4400// addressBlock: dce_dc_dpp0_dispdec_dpp_top_dispdec 4401// base address: 0x0 4402#define regDPP_TOP0_DPP_CONTROL 0x0cc5 4403#define regDPP_TOP0_DPP_CONTROL_BASE_IDX 2 4404#define regDPP_TOP0_DPP_SOFT_RESET 0x0cc6 4405#define regDPP_TOP0_DPP_SOFT_RESET_BASE_IDX 2 4406#define regDPP_TOP0_DPP_CRC_VAL_R_G 0x0cc7 4407#define regDPP_TOP0_DPP_CRC_VAL_R_G_BASE_IDX 2 4408#define regDPP_TOP0_DPP_CRC_VAL_B_A 0x0cc8 4409#define regDPP_TOP0_DPP_CRC_VAL_B_A_BASE_IDX 2 4410#define regDPP_TOP0_DPP_CRC_CTRL 0x0cc9 4411#define regDPP_TOP0_DPP_CRC_CTRL_BASE_IDX 2 4412#define regDPP_TOP0_HOST_READ_CONTROL 0x0cca 4413#define regDPP_TOP0_HOST_READ_CONTROL_BASE_IDX 2 4414 4415 4416// addressBlock: dce_dc_dpp0_dispdec_cnvc_cfg_dispdec 4417// base address: 0x0 4418#define regCNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT 0x0ccf 4419#define regCNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX 2 4420#define regCNVC_CFG0_FORMAT_CONTROL 0x0cd0 4421#define regCNVC_CFG0_FORMAT_CONTROL_BASE_IDX 2 4422#define regCNVC_CFG0_FCNV_FP_BIAS_R 0x0cd1 4423#define regCNVC_CFG0_FCNV_FP_BIAS_R_BASE_IDX 2 4424#define regCNVC_CFG0_FCNV_FP_BIAS_G 0x0cd2 4425#define regCNVC_CFG0_FCNV_FP_BIAS_G_BASE_IDX 2 4426#define regCNVC_CFG0_FCNV_FP_BIAS_B 0x0cd3 4427#define regCNVC_CFG0_FCNV_FP_BIAS_B_BASE_IDX 2 4428#define regCNVC_CFG0_FCNV_FP_SCALE_R 0x0cd4 4429#define regCNVC_CFG0_FCNV_FP_SCALE_R_BASE_IDX 2 4430#define regCNVC_CFG0_FCNV_FP_SCALE_G 0x0cd5 4431#define regCNVC_CFG0_FCNV_FP_SCALE_G_BASE_IDX 2 4432#define regCNVC_CFG0_FCNV_FP_SCALE_B 0x0cd6 4433#define regCNVC_CFG0_FCNV_FP_SCALE_B_BASE_IDX 2 4434#define regCNVC_CFG0_COLOR_KEYER_CONTROL 0x0cd7 4435#define regCNVC_CFG0_COLOR_KEYER_CONTROL_BASE_IDX 2 4436#define regCNVC_CFG0_COLOR_KEYER_ALPHA 0x0cd8 4437#define regCNVC_CFG0_COLOR_KEYER_ALPHA_BASE_IDX 2 4438#define regCNVC_CFG0_COLOR_KEYER_RED 0x0cd9 4439#define regCNVC_CFG0_COLOR_KEYER_RED_BASE_IDX 2 4440#define regCNVC_CFG0_COLOR_KEYER_GREEN 0x0cda 4441#define regCNVC_CFG0_COLOR_KEYER_GREEN_BASE_IDX 2 4442#define regCNVC_CFG0_COLOR_KEYER_BLUE 0x0cdb 4443#define regCNVC_CFG0_COLOR_KEYER_BLUE_BASE_IDX 2 4444#define regCNVC_CFG0_ALPHA_2BIT_LUT 0x0cdd 4445#define regCNVC_CFG0_ALPHA_2BIT_LUT_BASE_IDX 2 4446#define regCNVC_CFG0_PRE_DEALPHA 0x0cde 4447#define regCNVC_CFG0_PRE_DEALPHA_BASE_IDX 2 4448#define regCNVC_CFG0_PRE_CSC_MODE 0x0cdf 4449#define regCNVC_CFG0_PRE_CSC_MODE_BASE_IDX 2 4450#define regCNVC_CFG0_PRE_CSC_C11_C12 0x0ce0 4451#define regCNVC_CFG0_PRE_CSC_C11_C12_BASE_IDX 2 4452#define regCNVC_CFG0_PRE_CSC_C13_C14 0x0ce1 4453#define regCNVC_CFG0_PRE_CSC_C13_C14_BASE_IDX 2 4454#define regCNVC_CFG0_PRE_CSC_C21_C22 0x0ce2 4455#define regCNVC_CFG0_PRE_CSC_C21_C22_BASE_IDX 2 4456#define regCNVC_CFG0_PRE_CSC_C23_C24 0x0ce3 4457#define regCNVC_CFG0_PRE_CSC_C23_C24_BASE_IDX 2 4458#define regCNVC_CFG0_PRE_CSC_C31_C32 0x0ce4 4459#define regCNVC_CFG0_PRE_CSC_C31_C32_BASE_IDX 2 4460#define regCNVC_CFG0_PRE_CSC_C33_C34 0x0ce5 4461#define regCNVC_CFG0_PRE_CSC_C33_C34_BASE_IDX 2 4462#define regCNVC_CFG0_PRE_CSC_B_C11_C12 0x0ce6 4463#define regCNVC_CFG0_PRE_CSC_B_C11_C12_BASE_IDX 2 4464#define regCNVC_CFG0_PRE_CSC_B_C13_C14 0x0ce7 4465#define regCNVC_CFG0_PRE_CSC_B_C13_C14_BASE_IDX 2 4466#define regCNVC_CFG0_PRE_CSC_B_C21_C22 0x0ce8 4467#define regCNVC_CFG0_PRE_CSC_B_C21_C22_BASE_IDX 2 4468#define regCNVC_CFG0_PRE_CSC_B_C23_C24 0x0ce9 4469#define regCNVC_CFG0_PRE_CSC_B_C23_C24_BASE_IDX 2 4470#define regCNVC_CFG0_PRE_CSC_B_C31_C32 0x0cea 4471#define regCNVC_CFG0_PRE_CSC_B_C31_C32_BASE_IDX 2 4472#define regCNVC_CFG0_PRE_CSC_B_C33_C34 0x0ceb 4473#define regCNVC_CFG0_PRE_CSC_B_C33_C34_BASE_IDX 2 4474#define regCNVC_CFG0_CNVC_COEF_FORMAT 0x0cec 4475#define regCNVC_CFG0_CNVC_COEF_FORMAT_BASE_IDX 2 4476#define regCNVC_CFG0_PRE_DEGAM 0x0ced 4477#define regCNVC_CFG0_PRE_DEGAM_BASE_IDX 2 4478#define regCNVC_CFG0_PRE_REALPHA 0x0cee 4479#define regCNVC_CFG0_PRE_REALPHA_BASE_IDX 2 4480 4481 4482// addressBlock: dce_dc_dpp0_dispdec_cnvc_cur_dispdec 4483// base address: 0x0 4484#define regCNVC_CUR0_CURSOR0_CONTROL 0x0cf1 4485#define regCNVC_CUR0_CURSOR0_CONTROL_BASE_IDX 2 4486#define regCNVC_CUR0_CURSOR0_COLOR0 0x0cf2 4487#define regCNVC_CUR0_CURSOR0_COLOR0_BASE_IDX 2 4488#define regCNVC_CUR0_CURSOR0_COLOR1 0x0cf3 4489#define regCNVC_CUR0_CURSOR0_COLOR1_BASE_IDX 2 4490#define regCNVC_CUR0_CURSOR0_FP_SCALE_BIAS 0x0cf4 4491#define regCNVC_CUR0_CURSOR0_FP_SCALE_BIAS_BASE_IDX 2 4492 4493 4494// addressBlock: dce_dc_dpp0_dispdec_dscl_dispdec 4495// base address: 0x0 4496#define regDSCL0_SCL_COEF_RAM_TAP_SELECT 0x0cf9 4497#define regDSCL0_SCL_COEF_RAM_TAP_SELECT_BASE_IDX 2 4498#define regDSCL0_SCL_COEF_RAM_TAP_DATA 0x0cfa 4499#define regDSCL0_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2 4500#define regDSCL0_SCL_MODE 0x0cfb 4501#define regDSCL0_SCL_MODE_BASE_IDX 2 4502#define regDSCL0_SCL_TAP_CONTROL 0x0cfc 4503#define regDSCL0_SCL_TAP_CONTROL_BASE_IDX 2 4504#define regDSCL0_DSCL_CONTROL 0x0cfd 4505#define regDSCL0_DSCL_CONTROL_BASE_IDX 2 4506#define regDSCL0_DSCL_2TAP_CONTROL 0x0cfe 4507#define regDSCL0_DSCL_2TAP_CONTROL_BASE_IDX 2 4508#define regDSCL0_SCL_MANUAL_REPLICATE_CONTROL 0x0cff 4509#define regDSCL0_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2 4510#define regDSCL0_SCL_HORZ_FILTER_SCALE_RATIO 0x0d00 4511#define regDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2 4512#define regDSCL0_SCL_HORZ_FILTER_INIT 0x0d01 4513#define regDSCL0_SCL_HORZ_FILTER_INIT_BASE_IDX 2 4514#define regDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C 0x0d02 4515#define regDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX 2 4516#define regDSCL0_SCL_HORZ_FILTER_INIT_C 0x0d03 4517#define regDSCL0_SCL_HORZ_FILTER_INIT_C_BASE_IDX 2 4518#define regDSCL0_SCL_VERT_FILTER_SCALE_RATIO 0x0d04 4519#define regDSCL0_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2 4520#define regDSCL0_SCL_VERT_FILTER_INIT 0x0d05 4521#define regDSCL0_SCL_VERT_FILTER_INIT_BASE_IDX 2 4522#define regDSCL0_SCL_VERT_FILTER_INIT_BOT 0x0d06 4523#define regDSCL0_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2 4524#define regDSCL0_SCL_VERT_FILTER_SCALE_RATIO_C 0x0d07 4525#define regDSCL0_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX 2 4526#define regDSCL0_SCL_VERT_FILTER_INIT_C 0x0d08 4527#define regDSCL0_SCL_VERT_FILTER_INIT_C_BASE_IDX 2 4528#define regDSCL0_SCL_VERT_FILTER_INIT_BOT_C 0x0d09 4529#define regDSCL0_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX 2 4530#define regDSCL0_SCL_BLACK_COLOR 0x0d0a 4531#define regDSCL0_SCL_BLACK_COLOR_BASE_IDX 2 4532#define regDSCL0_DSCL_UPDATE 0x0d0b 4533#define regDSCL0_DSCL_UPDATE_BASE_IDX 2 4534#define regDSCL0_DSCL_AUTOCAL 0x0d0c 4535#define regDSCL0_DSCL_AUTOCAL_BASE_IDX 2 4536#define regDSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT 0x0d0d 4537#define regDSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2 4538#define regDSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM 0x0d0e 4539#define regDSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2 4540#define regDSCL0_OTG_H_BLANK 0x0d0f 4541#define regDSCL0_OTG_H_BLANK_BASE_IDX 2 4542#define regDSCL0_OTG_V_BLANK 0x0d10 4543#define regDSCL0_OTG_V_BLANK_BASE_IDX 2 4544#define regDSCL0_RECOUT_START 0x0d11 4545#define regDSCL0_RECOUT_START_BASE_IDX 2 4546#define regDSCL0_RECOUT_SIZE 0x0d12 4547#define regDSCL0_RECOUT_SIZE_BASE_IDX 2 4548#define regDSCL0_MPC_SIZE 0x0d13 4549#define regDSCL0_MPC_SIZE_BASE_IDX 2 4550#define regDSCL0_LB_DATA_FORMAT 0x0d14 4551#define regDSCL0_LB_DATA_FORMAT_BASE_IDX 2 4552#define regDSCL0_LB_MEMORY_CTRL 0x0d15 4553#define regDSCL0_LB_MEMORY_CTRL_BASE_IDX 2 4554#define regDSCL0_LB_V_COUNTER 0x0d16 4555#define regDSCL0_LB_V_COUNTER_BASE_IDX 2 4556#define regDSCL0_DSCL_MEM_PWR_CTRL 0x0d17 4557#define regDSCL0_DSCL_MEM_PWR_CTRL_BASE_IDX 2 4558#define regDSCL0_DSCL_MEM_PWR_STATUS 0x0d18 4559#define regDSCL0_DSCL_MEM_PWR_STATUS_BASE_IDX 2 4560#define regDSCL0_OBUF_CONTROL 0x0d19 4561#define regDSCL0_OBUF_CONTROL_BASE_IDX 2 4562#define regDSCL0_OBUF_MEM_PWR_CTRL 0x0d1a 4563#define regDSCL0_OBUF_MEM_PWR_CTRL_BASE_IDX 2 4564 4565 4566// addressBlock: dce_dc_dpp0_dispdec_cm_dispdec 4567// base address: 0x0 4568#define regCM0_CM_CONTROL 0x0d20 4569#define regCM0_CM_CONTROL_BASE_IDX 2 4570#define regCM0_CM_POST_CSC_CONTROL 0x0d21 4571#define regCM0_CM_POST_CSC_CONTROL_BASE_IDX 2 4572#define regCM0_CM_POST_CSC_C11_C12 0x0d22 4573#define regCM0_CM_POST_CSC_C11_C12_BASE_IDX 2 4574#define regCM0_CM_POST_CSC_C13_C14 0x0d23 4575#define regCM0_CM_POST_CSC_C13_C14_BASE_IDX 2 4576#define regCM0_CM_POST_CSC_C21_C22 0x0d24 4577#define regCM0_CM_POST_CSC_C21_C22_BASE_IDX 2 4578#define regCM0_CM_POST_CSC_C23_C24 0x0d25 4579#define regCM0_CM_POST_CSC_C23_C24_BASE_IDX 2 4580#define regCM0_CM_POST_CSC_C31_C32 0x0d26 4581#define regCM0_CM_POST_CSC_C31_C32_BASE_IDX 2 4582#define regCM0_CM_POST_CSC_C33_C34 0x0d27 4583#define regCM0_CM_POST_CSC_C33_C34_BASE_IDX 2 4584#define regCM0_CM_POST_CSC_B_C11_C12 0x0d28 4585#define regCM0_CM_POST_CSC_B_C11_C12_BASE_IDX 2 4586#define regCM0_CM_POST_CSC_B_C13_C14 0x0d29 4587#define regCM0_CM_POST_CSC_B_C13_C14_BASE_IDX 2 4588#define regCM0_CM_POST_CSC_B_C21_C22 0x0d2a 4589#define regCM0_CM_POST_CSC_B_C21_C22_BASE_IDX 2 4590#define regCM0_CM_POST_CSC_B_C23_C24 0x0d2b 4591#define regCM0_CM_POST_CSC_B_C23_C24_BASE_IDX 2 4592#define regCM0_CM_POST_CSC_B_C31_C32 0x0d2c 4593#define regCM0_CM_POST_CSC_B_C31_C32_BASE_IDX 2 4594#define regCM0_CM_POST_CSC_B_C33_C34 0x0d2d 4595#define regCM0_CM_POST_CSC_B_C33_C34_BASE_IDX 2 4596#define regCM0_CM_GAMUT_REMAP_CONTROL 0x0d2e 4597#define regCM0_CM_GAMUT_REMAP_CONTROL_BASE_IDX 2 4598#define regCM0_CM_GAMUT_REMAP_C11_C12 0x0d2f 4599#define regCM0_CM_GAMUT_REMAP_C11_C12_BASE_IDX 2 4600#define regCM0_CM_GAMUT_REMAP_C13_C14 0x0d30 4601#define regCM0_CM_GAMUT_REMAP_C13_C14_BASE_IDX 2 4602#define regCM0_CM_GAMUT_REMAP_C21_C22 0x0d31 4603#define regCM0_CM_GAMUT_REMAP_C21_C22_BASE_IDX 2 4604#define regCM0_CM_GAMUT_REMAP_C23_C24 0x0d32 4605#define regCM0_CM_GAMUT_REMAP_C23_C24_BASE_IDX 2 4606#define regCM0_CM_GAMUT_REMAP_C31_C32 0x0d33 4607#define regCM0_CM_GAMUT_REMAP_C31_C32_BASE_IDX 2 4608#define regCM0_CM_GAMUT_REMAP_C33_C34 0x0d34 4609#define regCM0_CM_GAMUT_REMAP_C33_C34_BASE_IDX 2 4610#define regCM0_CM_GAMUT_REMAP_B_C11_C12 0x0d35 4611#define regCM0_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX 2 4612#define regCM0_CM_GAMUT_REMAP_B_C13_C14 0x0d36 4613#define regCM0_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX 2 4614#define regCM0_CM_GAMUT_REMAP_B_C21_C22 0x0d37 4615#define regCM0_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX 2 4616#define regCM0_CM_GAMUT_REMAP_B_C23_C24 0x0d38 4617#define regCM0_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX 2 4618#define regCM0_CM_GAMUT_REMAP_B_C31_C32 0x0d39 4619#define regCM0_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX 2 4620#define regCM0_CM_GAMUT_REMAP_B_C33_C34 0x0d3a 4621#define regCM0_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX 2 4622#define regCM0_CM_BIAS_CR_R 0x0d3b 4623#define regCM0_CM_BIAS_CR_R_BASE_IDX 2 4624#define regCM0_CM_BIAS_Y_G_CB_B 0x0d3c 4625#define regCM0_CM_BIAS_Y_G_CB_B_BASE_IDX 2 4626#define regCM0_CM_GAMCOR_CONTROL 0x0d3d 4627#define regCM0_CM_GAMCOR_CONTROL_BASE_IDX 2 4628#define regCM0_CM_GAMCOR_LUT_INDEX 0x0d3e 4629#define regCM0_CM_GAMCOR_LUT_INDEX_BASE_IDX 2 4630#define regCM0_CM_GAMCOR_LUT_DATA 0x0d3f 4631#define regCM0_CM_GAMCOR_LUT_DATA_BASE_IDX 2 4632#define regCM0_CM_GAMCOR_LUT_CONTROL 0x0d40 4633#define regCM0_CM_GAMCOR_LUT_CONTROL_BASE_IDX 2 4634#define regCM0_CM_GAMCOR_RAMA_START_CNTL_B 0x0d41 4635#define regCM0_CM_GAMCOR_RAMA_START_CNTL_B_BASE_IDX 2 4636#define regCM0_CM_GAMCOR_RAMA_START_CNTL_G 0x0d42 4637#define regCM0_CM_GAMCOR_RAMA_START_CNTL_G_BASE_IDX 2 4638#define regCM0_CM_GAMCOR_RAMA_START_CNTL_R 0x0d43 4639#define regCM0_CM_GAMCOR_RAMA_START_CNTL_R_BASE_IDX 2 4640#define regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B 0x0d44 4641#define regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B_BASE_IDX 2 4642#define regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G 0x0d45 4643#define regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2 4644#define regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R 0x0d46 4645#define regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R_BASE_IDX 2 4646#define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_B 0x0d47 4647#define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_B_BASE_IDX 2 4648#define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_G 0x0d48 4649#define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_G_BASE_IDX 2 4650#define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_R 0x0d49 4651#define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_R_BASE_IDX 2 4652#define regCM0_CM_GAMCOR_RAMA_END_CNTL1_B 0x0d4a 4653#define regCM0_CM_GAMCOR_RAMA_END_CNTL1_B_BASE_IDX 2 4654#define regCM0_CM_GAMCOR_RAMA_END_CNTL2_B 0x0d4b 4655#define regCM0_CM_GAMCOR_RAMA_END_CNTL2_B_BASE_IDX 2 4656#define regCM0_CM_GAMCOR_RAMA_END_CNTL1_G 0x0d4c 4657#define regCM0_CM_GAMCOR_RAMA_END_CNTL1_G_BASE_IDX 2 4658#define regCM0_CM_GAMCOR_RAMA_END_CNTL2_G 0x0d4d 4659#define regCM0_CM_GAMCOR_RAMA_END_CNTL2_G_BASE_IDX 2 4660#define regCM0_CM_GAMCOR_RAMA_END_CNTL1_R 0x0d4e 4661#define regCM0_CM_GAMCOR_RAMA_END_CNTL1_R_BASE_IDX 2 4662#define regCM0_CM_GAMCOR_RAMA_END_CNTL2_R 0x0d4f 4663#define regCM0_CM_GAMCOR_RAMA_END_CNTL2_R_BASE_IDX 2 4664#define regCM0_CM_GAMCOR_RAMA_OFFSET_B 0x0d50 4665#define regCM0_CM_GAMCOR_RAMA_OFFSET_B_BASE_IDX 2 4666#define regCM0_CM_GAMCOR_RAMA_OFFSET_G 0x0d51 4667#define regCM0_CM_GAMCOR_RAMA_OFFSET_G_BASE_IDX 2 4668#define regCM0_CM_GAMCOR_RAMA_OFFSET_R 0x0d52 4669#define regCM0_CM_GAMCOR_RAMA_OFFSET_R_BASE_IDX 2 4670#define regCM0_CM_GAMCOR_RAMA_REGION_0_1 0x0d53 4671#define regCM0_CM_GAMCOR_RAMA_REGION_0_1_BASE_IDX 2 4672#define regCM0_CM_GAMCOR_RAMA_REGION_2_3 0x0d54 4673#define regCM0_CM_GAMCOR_RAMA_REGION_2_3_BASE_IDX 2 4674#define regCM0_CM_GAMCOR_RAMA_REGION_4_5 0x0d55 4675#define regCM0_CM_GAMCOR_RAMA_REGION_4_5_BASE_IDX 2 4676#define regCM0_CM_GAMCOR_RAMA_REGION_6_7 0x0d56 4677#define regCM0_CM_GAMCOR_RAMA_REGION_6_7_BASE_IDX 2 4678#define regCM0_CM_GAMCOR_RAMA_REGION_8_9 0x0d57 4679#define regCM0_CM_GAMCOR_RAMA_REGION_8_9_BASE_IDX 2 4680#define regCM0_CM_GAMCOR_RAMA_REGION_10_11 0x0d58 4681#define regCM0_CM_GAMCOR_RAMA_REGION_10_11_BASE_IDX 2 4682#define regCM0_CM_GAMCOR_RAMA_REGION_12_13 0x0d59 4683#define regCM0_CM_GAMCOR_RAMA_REGION_12_13_BASE_IDX 2 4684#define regCM0_CM_GAMCOR_RAMA_REGION_14_15 0x0d5a 4685#define regCM0_CM_GAMCOR_RAMA_REGION_14_15_BASE_IDX 2 4686#define regCM0_CM_GAMCOR_RAMA_REGION_16_17 0x0d5b 4687#define regCM0_CM_GAMCOR_RAMA_REGION_16_17_BASE_IDX 2 4688#define regCM0_CM_GAMCOR_RAMA_REGION_18_19 0x0d5c 4689#define regCM0_CM_GAMCOR_RAMA_REGION_18_19_BASE_IDX 2 4690#define regCM0_CM_GAMCOR_RAMA_REGION_20_21 0x0d5d 4691#define regCM0_CM_GAMCOR_RAMA_REGION_20_21_BASE_IDX 2 4692#define regCM0_CM_GAMCOR_RAMA_REGION_22_23 0x0d5e 4693#define regCM0_CM_GAMCOR_RAMA_REGION_22_23_BASE_IDX 2 4694#define regCM0_CM_GAMCOR_RAMA_REGION_24_25 0x0d5f 4695#define regCM0_CM_GAMCOR_RAMA_REGION_24_25_BASE_IDX 2 4696#define regCM0_CM_GAMCOR_RAMA_REGION_26_27 0x0d60 4697#define regCM0_CM_GAMCOR_RAMA_REGION_26_27_BASE_IDX 2 4698#define regCM0_CM_GAMCOR_RAMA_REGION_28_29 0x0d61 4699#define regCM0_CM_GAMCOR_RAMA_REGION_28_29_BASE_IDX 2 4700#define regCM0_CM_GAMCOR_RAMA_REGION_30_31 0x0d62 4701#define regCM0_CM_GAMCOR_RAMA_REGION_30_31_BASE_IDX 2 4702#define regCM0_CM_GAMCOR_RAMA_REGION_32_33 0x0d63 4703#define regCM0_CM_GAMCOR_RAMA_REGION_32_33_BASE_IDX 2 4704#define regCM0_CM_GAMCOR_RAMB_START_CNTL_B 0x0d64 4705#define regCM0_CM_GAMCOR_RAMB_START_CNTL_B_BASE_IDX 2 4706#define regCM0_CM_GAMCOR_RAMB_START_CNTL_G 0x0d65 4707#define regCM0_CM_GAMCOR_RAMB_START_CNTL_G_BASE_IDX 2 4708#define regCM0_CM_GAMCOR_RAMB_START_CNTL_R 0x0d66 4709#define regCM0_CM_GAMCOR_RAMB_START_CNTL_R_BASE_IDX 2 4710#define regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B 0x0d67 4711#define regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B_BASE_IDX 2 4712#define regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G 0x0d68 4713#define regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G_BASE_IDX 2 4714#define regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R 0x0d69 4715#define regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R_BASE_IDX 2 4716#define regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_B 0x0d6a 4717#define regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_B_BASE_IDX 2 4718#define regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_G 0x0d6b 4719#define regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_G_BASE_IDX 2 4720#define regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_R 0x0d6c 4721#define regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_R_BASE_IDX 2 4722#define regCM0_CM_GAMCOR_RAMB_END_CNTL1_B 0x0d6d 4723#define regCM0_CM_GAMCOR_RAMB_END_CNTL1_B_BASE_IDX 2 4724#define regCM0_CM_GAMCOR_RAMB_END_CNTL2_B 0x0d6e 4725#define regCM0_CM_GAMCOR_RAMB_END_CNTL2_B_BASE_IDX 2 4726#define regCM0_CM_GAMCOR_RAMB_END_CNTL1_G 0x0d6f 4727#define regCM0_CM_GAMCOR_RAMB_END_CNTL1_G_BASE_IDX 2 4728#define regCM0_CM_GAMCOR_RAMB_END_CNTL2_G 0x0d70 4729#define regCM0_CM_GAMCOR_RAMB_END_CNTL2_G_BASE_IDX 2 4730#define regCM0_CM_GAMCOR_RAMB_END_CNTL1_R 0x0d71 4731#define regCM0_CM_GAMCOR_RAMB_END_CNTL1_R_BASE_IDX 2 4732#define regCM0_CM_GAMCOR_RAMB_END_CNTL2_R 0x0d72 4733#define regCM0_CM_GAMCOR_RAMB_END_CNTL2_R_BASE_IDX 2 4734#define regCM0_CM_GAMCOR_RAMB_OFFSET_B 0x0d73 4735#define regCM0_CM_GAMCOR_RAMB_OFFSET_B_BASE_IDX 2 4736#define regCM0_CM_GAMCOR_RAMB_OFFSET_G 0x0d74 4737#define regCM0_CM_GAMCOR_RAMB_OFFSET_G_BASE_IDX 2 4738#define regCM0_CM_GAMCOR_RAMB_OFFSET_R 0x0d75 4739#define regCM0_CM_GAMCOR_RAMB_OFFSET_R_BASE_IDX 2 4740#define regCM0_CM_GAMCOR_RAMB_REGION_0_1 0x0d76 4741#define regCM0_CM_GAMCOR_RAMB_REGION_0_1_BASE_IDX 2 4742#define regCM0_CM_GAMCOR_RAMB_REGION_2_3 0x0d77 4743#define regCM0_CM_GAMCOR_RAMB_REGION_2_3_BASE_IDX 2 4744#define regCM0_CM_GAMCOR_RAMB_REGION_4_5 0x0d78 4745#define regCM0_CM_GAMCOR_RAMB_REGION_4_5_BASE_IDX 2 4746#define regCM0_CM_GAMCOR_RAMB_REGION_6_7 0x0d79 4747#define regCM0_CM_GAMCOR_RAMB_REGION_6_7_BASE_IDX 2 4748#define regCM0_CM_GAMCOR_RAMB_REGION_8_9 0x0d7a 4749#define regCM0_CM_GAMCOR_RAMB_REGION_8_9_BASE_IDX 2 4750#define regCM0_CM_GAMCOR_RAMB_REGION_10_11 0x0d7b 4751#define regCM0_CM_GAMCOR_RAMB_REGION_10_11_BASE_IDX 2 4752#define regCM0_CM_GAMCOR_RAMB_REGION_12_13 0x0d7c 4753#define regCM0_CM_GAMCOR_RAMB_REGION_12_13_BASE_IDX 2 4754#define regCM0_CM_GAMCOR_RAMB_REGION_14_15 0x0d7d 4755#define regCM0_CM_GAMCOR_RAMB_REGION_14_15_BASE_IDX 2 4756#define regCM0_CM_GAMCOR_RAMB_REGION_16_17 0x0d7e 4757#define regCM0_CM_GAMCOR_RAMB_REGION_16_17_BASE_IDX 2 4758#define regCM0_CM_GAMCOR_RAMB_REGION_18_19 0x0d7f 4759#define regCM0_CM_GAMCOR_RAMB_REGION_18_19_BASE_IDX 2 4760#define regCM0_CM_GAMCOR_RAMB_REGION_20_21 0x0d80 4761#define regCM0_CM_GAMCOR_RAMB_REGION_20_21_BASE_IDX 2 4762#define regCM0_CM_GAMCOR_RAMB_REGION_22_23 0x0d81 4763#define regCM0_CM_GAMCOR_RAMB_REGION_22_23_BASE_IDX 2 4764#define regCM0_CM_GAMCOR_RAMB_REGION_24_25 0x0d82 4765#define regCM0_CM_GAMCOR_RAMB_REGION_24_25_BASE_IDX 2 4766#define regCM0_CM_GAMCOR_RAMB_REGION_26_27 0x0d83 4767#define regCM0_CM_GAMCOR_RAMB_REGION_26_27_BASE_IDX 2 4768#define regCM0_CM_GAMCOR_RAMB_REGION_28_29 0x0d84 4769#define regCM0_CM_GAMCOR_RAMB_REGION_28_29_BASE_IDX 2 4770#define regCM0_CM_GAMCOR_RAMB_REGION_30_31 0x0d85 4771#define regCM0_CM_GAMCOR_RAMB_REGION_30_31_BASE_IDX 2 4772#define regCM0_CM_GAMCOR_RAMB_REGION_32_33 0x0d86 4773#define regCM0_CM_GAMCOR_RAMB_REGION_32_33_BASE_IDX 2 4774#define regCM0_CM_HDR_MULT_COEF 0x0d87 4775#define regCM0_CM_HDR_MULT_COEF_BASE_IDX 2 4776#define regCM0_CM_MEM_PWR_CTRL 0x0d88 4777#define regCM0_CM_MEM_PWR_CTRL_BASE_IDX 2 4778#define regCM0_CM_MEM_PWR_STATUS 0x0d89 4779#define regCM0_CM_MEM_PWR_STATUS_BASE_IDX 2 4780#define regCM0_CM_DEALPHA 0x0d8b 4781#define regCM0_CM_DEALPHA_BASE_IDX 2 4782#define regCM0_CM_COEF_FORMAT 0x0d8c 4783#define regCM0_CM_COEF_FORMAT_BASE_IDX 2 4784#define regCM0_CM_TEST_DEBUG_INDEX 0x0d8d 4785#define regCM0_CM_TEST_DEBUG_INDEX_BASE_IDX 2 4786#define regCM0_CM_TEST_DEBUG_DATA 0x0d8e 4787#define regCM0_CM_TEST_DEBUG_DATA_BASE_IDX 2 4788 4789 4790// addressBlock: dce_dc_dpp0_dispdec_dpp_dcperfmon_dc_perfmon_dispdec 4791// base address: 0x3890 4792#define regDC_PERFMON11_PERFCOUNTER_CNTL 0x0e24 4793#define regDC_PERFMON11_PERFCOUNTER_CNTL_BASE_IDX 2 4794#define regDC_PERFMON11_PERFCOUNTER_CNTL2 0x0e25 4795#define regDC_PERFMON11_PERFCOUNTER_CNTL2_BASE_IDX 2 4796#define regDC_PERFMON11_PERFCOUNTER_STATE 0x0e26 4797#define regDC_PERFMON11_PERFCOUNTER_STATE_BASE_IDX 2 4798#define regDC_PERFMON11_PERFMON_CNTL 0x0e27 4799#define regDC_PERFMON11_PERFMON_CNTL_BASE_IDX 2 4800#define regDC_PERFMON11_PERFMON_CNTL2 0x0e28 4801#define regDC_PERFMON11_PERFMON_CNTL2_BASE_IDX 2 4802#define regDC_PERFMON11_PERFMON_CVALUE_INT_MISC 0x0e29 4803#define regDC_PERFMON11_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 4804#define regDC_PERFMON11_PERFMON_CVALUE_LOW 0x0e2a 4805#define regDC_PERFMON11_PERFMON_CVALUE_LOW_BASE_IDX 2 4806#define regDC_PERFMON11_PERFMON_HI 0x0e2b 4807#define regDC_PERFMON11_PERFMON_HI_BASE_IDX 2 4808#define regDC_PERFMON11_PERFMON_LOW 0x0e2c 4809#define regDC_PERFMON11_PERFMON_LOW_BASE_IDX 2 4810 4811 4812// addressBlock: dce_dc_dpp1_dispdec_dpp_top_dispdec 4813// base address: 0x5ac 4814#define regDPP_TOP1_DPP_CONTROL 0x0e30 4815#define regDPP_TOP1_DPP_CONTROL_BASE_IDX 2 4816#define regDPP_TOP1_DPP_SOFT_RESET 0x0e31 4817#define regDPP_TOP1_DPP_SOFT_RESET_BASE_IDX 2 4818#define regDPP_TOP1_DPP_CRC_VAL_R_G 0x0e32 4819#define regDPP_TOP1_DPP_CRC_VAL_R_G_BASE_IDX 2 4820#define regDPP_TOP1_DPP_CRC_VAL_B_A 0x0e33 4821#define regDPP_TOP1_DPP_CRC_VAL_B_A_BASE_IDX 2 4822#define regDPP_TOP1_DPP_CRC_CTRL 0x0e34 4823#define regDPP_TOP1_DPP_CRC_CTRL_BASE_IDX 2 4824#define regDPP_TOP1_HOST_READ_CONTROL 0x0e35 4825#define regDPP_TOP1_HOST_READ_CONTROL_BASE_IDX 2 4826 4827 4828// addressBlock: dce_dc_dpp1_dispdec_cnvc_cfg_dispdec 4829// base address: 0x5ac 4830#define regCNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT 0x0e3a 4831#define regCNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX 2 4832#define regCNVC_CFG1_FORMAT_CONTROL 0x0e3b 4833#define regCNVC_CFG1_FORMAT_CONTROL_BASE_IDX 2 4834#define regCNVC_CFG1_FCNV_FP_BIAS_R 0x0e3c 4835#define regCNVC_CFG1_FCNV_FP_BIAS_R_BASE_IDX 2 4836#define regCNVC_CFG1_FCNV_FP_BIAS_G 0x0e3d 4837#define regCNVC_CFG1_FCNV_FP_BIAS_G_BASE_IDX 2 4838#define regCNVC_CFG1_FCNV_FP_BIAS_B 0x0e3e 4839#define regCNVC_CFG1_FCNV_FP_BIAS_B_BASE_IDX 2 4840#define regCNVC_CFG1_FCNV_FP_SCALE_R 0x0e3f 4841#define regCNVC_CFG1_FCNV_FP_SCALE_R_BASE_IDX 2 4842#define regCNVC_CFG1_FCNV_FP_SCALE_G 0x0e40 4843#define regCNVC_CFG1_FCNV_FP_SCALE_G_BASE_IDX 2 4844#define regCNVC_CFG1_FCNV_FP_SCALE_B 0x0e41 4845#define regCNVC_CFG1_FCNV_FP_SCALE_B_BASE_IDX 2 4846#define regCNVC_CFG1_COLOR_KEYER_CONTROL 0x0e42 4847#define regCNVC_CFG1_COLOR_KEYER_CONTROL_BASE_IDX 2 4848#define regCNVC_CFG1_COLOR_KEYER_ALPHA 0x0e43 4849#define regCNVC_CFG1_COLOR_KEYER_ALPHA_BASE_IDX 2 4850#define regCNVC_CFG1_COLOR_KEYER_RED 0x0e44 4851#define regCNVC_CFG1_COLOR_KEYER_RED_BASE_IDX 2 4852#define regCNVC_CFG1_COLOR_KEYER_GREEN 0x0e45 4853#define regCNVC_CFG1_COLOR_KEYER_GREEN_BASE_IDX 2 4854#define regCNVC_CFG1_COLOR_KEYER_BLUE 0x0e46 4855#define regCNVC_CFG1_COLOR_KEYER_BLUE_BASE_IDX 2 4856#define regCNVC_CFG1_ALPHA_2BIT_LUT 0x0e48 4857#define regCNVC_CFG1_ALPHA_2BIT_LUT_BASE_IDX 2 4858#define regCNVC_CFG1_PRE_DEALPHA 0x0e49 4859#define regCNVC_CFG1_PRE_DEALPHA_BASE_IDX 2 4860#define regCNVC_CFG1_PRE_CSC_MODE 0x0e4a 4861#define regCNVC_CFG1_PRE_CSC_MODE_BASE_IDX 2 4862#define regCNVC_CFG1_PRE_CSC_C11_C12 0x0e4b 4863#define regCNVC_CFG1_PRE_CSC_C11_C12_BASE_IDX 2 4864#define regCNVC_CFG1_PRE_CSC_C13_C14 0x0e4c 4865#define regCNVC_CFG1_PRE_CSC_C13_C14_BASE_IDX 2 4866#define regCNVC_CFG1_PRE_CSC_C21_C22 0x0e4d 4867#define regCNVC_CFG1_PRE_CSC_C21_C22_BASE_IDX 2 4868#define regCNVC_CFG1_PRE_CSC_C23_C24 0x0e4e 4869#define regCNVC_CFG1_PRE_CSC_C23_C24_BASE_IDX 2 4870#define regCNVC_CFG1_PRE_CSC_C31_C32 0x0e4f 4871#define regCNVC_CFG1_PRE_CSC_C31_C32_BASE_IDX 2 4872#define regCNVC_CFG1_PRE_CSC_C33_C34 0x0e50 4873#define regCNVC_CFG1_PRE_CSC_C33_C34_BASE_IDX 2 4874#define regCNVC_CFG1_PRE_CSC_B_C11_C12 0x0e51 4875#define regCNVC_CFG1_PRE_CSC_B_C11_C12_BASE_IDX 2 4876#define regCNVC_CFG1_PRE_CSC_B_C13_C14 0x0e52 4877#define regCNVC_CFG1_PRE_CSC_B_C13_C14_BASE_IDX 2 4878#define regCNVC_CFG1_PRE_CSC_B_C21_C22 0x0e53 4879#define regCNVC_CFG1_PRE_CSC_B_C21_C22_BASE_IDX 2 4880#define regCNVC_CFG1_PRE_CSC_B_C23_C24 0x0e54 4881#define regCNVC_CFG1_PRE_CSC_B_C23_C24_BASE_IDX 2 4882#define regCNVC_CFG1_PRE_CSC_B_C31_C32 0x0e55 4883#define regCNVC_CFG1_PRE_CSC_B_C31_C32_BASE_IDX 2 4884#define regCNVC_CFG1_PRE_CSC_B_C33_C34 0x0e56 4885#define regCNVC_CFG1_PRE_CSC_B_C33_C34_BASE_IDX 2 4886#define regCNVC_CFG1_CNVC_COEF_FORMAT 0x0e57 4887#define regCNVC_CFG1_CNVC_COEF_FORMAT_BASE_IDX 2 4888#define regCNVC_CFG1_PRE_DEGAM 0x0e58 4889#define regCNVC_CFG1_PRE_DEGAM_BASE_IDX 2 4890#define regCNVC_CFG1_PRE_REALPHA 0x0e59 4891#define regCNVC_CFG1_PRE_REALPHA_BASE_IDX 2 4892 4893 4894// addressBlock: dce_dc_dpp1_dispdec_cnvc_cur_dispdec 4895// base address: 0x5ac 4896#define regCNVC_CUR1_CURSOR0_CONTROL 0x0e5c 4897#define regCNVC_CUR1_CURSOR0_CONTROL_BASE_IDX 2 4898#define regCNVC_CUR1_CURSOR0_COLOR0 0x0e5d 4899#define regCNVC_CUR1_CURSOR0_COLOR0_BASE_IDX 2 4900#define regCNVC_CUR1_CURSOR0_COLOR1 0x0e5e 4901#define regCNVC_CUR1_CURSOR0_COLOR1_BASE_IDX 2 4902#define regCNVC_CUR1_CURSOR0_FP_SCALE_BIAS 0x0e5f 4903#define regCNVC_CUR1_CURSOR0_FP_SCALE_BIAS_BASE_IDX 2 4904 4905 4906// addressBlock: dce_dc_dpp1_dispdec_dscl_dispdec 4907// base address: 0x5ac 4908#define regDSCL1_SCL_COEF_RAM_TAP_SELECT 0x0e64 4909#define regDSCL1_SCL_COEF_RAM_TAP_SELECT_BASE_IDX 2 4910#define regDSCL1_SCL_COEF_RAM_TAP_DATA 0x0e65 4911#define regDSCL1_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2 4912#define regDSCL1_SCL_MODE 0x0e66 4913#define regDSCL1_SCL_MODE_BASE_IDX 2 4914#define regDSCL1_SCL_TAP_CONTROL 0x0e67 4915#define regDSCL1_SCL_TAP_CONTROL_BASE_IDX 2 4916#define regDSCL1_DSCL_CONTROL 0x0e68 4917#define regDSCL1_DSCL_CONTROL_BASE_IDX 2 4918#define regDSCL1_DSCL_2TAP_CONTROL 0x0e69 4919#define regDSCL1_DSCL_2TAP_CONTROL_BASE_IDX 2 4920#define regDSCL1_SCL_MANUAL_REPLICATE_CONTROL 0x0e6a 4921#define regDSCL1_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2 4922#define regDSCL1_SCL_HORZ_FILTER_SCALE_RATIO 0x0e6b 4923#define regDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2 4924#define regDSCL1_SCL_HORZ_FILTER_INIT 0x0e6c 4925#define regDSCL1_SCL_HORZ_FILTER_INIT_BASE_IDX 2 4926#define regDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C 0x0e6d 4927#define regDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX 2 4928#define regDSCL1_SCL_HORZ_FILTER_INIT_C 0x0e6e 4929#define regDSCL1_SCL_HORZ_FILTER_INIT_C_BASE_IDX 2 4930#define regDSCL1_SCL_VERT_FILTER_SCALE_RATIO 0x0e6f 4931#define regDSCL1_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2 4932#define regDSCL1_SCL_VERT_FILTER_INIT 0x0e70 4933#define regDSCL1_SCL_VERT_FILTER_INIT_BASE_IDX 2 4934#define regDSCL1_SCL_VERT_FILTER_INIT_BOT 0x0e71 4935#define regDSCL1_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2 4936#define regDSCL1_SCL_VERT_FILTER_SCALE_RATIO_C 0x0e72 4937#define regDSCL1_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX 2 4938#define regDSCL1_SCL_VERT_FILTER_INIT_C 0x0e73 4939#define regDSCL1_SCL_VERT_FILTER_INIT_C_BASE_IDX 2 4940#define regDSCL1_SCL_VERT_FILTER_INIT_BOT_C 0x0e74 4941#define regDSCL1_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX 2 4942#define regDSCL1_SCL_BLACK_COLOR 0x0e75 4943#define regDSCL1_SCL_BLACK_COLOR_BASE_IDX 2 4944#define regDSCL1_DSCL_UPDATE 0x0e76 4945#define regDSCL1_DSCL_UPDATE_BASE_IDX 2 4946#define regDSCL1_DSCL_AUTOCAL 0x0e77 4947#define regDSCL1_DSCL_AUTOCAL_BASE_IDX 2 4948#define regDSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT 0x0e78 4949#define regDSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2 4950#define regDSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM 0x0e79 4951#define regDSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2 4952#define regDSCL1_OTG_H_BLANK 0x0e7a 4953#define regDSCL1_OTG_H_BLANK_BASE_IDX 2 4954#define regDSCL1_OTG_V_BLANK 0x0e7b 4955#define regDSCL1_OTG_V_BLANK_BASE_IDX 2 4956#define regDSCL1_RECOUT_START 0x0e7c 4957#define regDSCL1_RECOUT_START_BASE_IDX 2 4958#define regDSCL1_RECOUT_SIZE 0x0e7d 4959#define regDSCL1_RECOUT_SIZE_BASE_IDX 2 4960#define regDSCL1_MPC_SIZE 0x0e7e 4961#define regDSCL1_MPC_SIZE_BASE_IDX 2 4962#define regDSCL1_LB_DATA_FORMAT 0x0e7f 4963#define regDSCL1_LB_DATA_FORMAT_BASE_IDX 2 4964#define regDSCL1_LB_MEMORY_CTRL 0x0e80 4965#define regDSCL1_LB_MEMORY_CTRL_BASE_IDX 2 4966#define regDSCL1_LB_V_COUNTER 0x0e81 4967#define regDSCL1_LB_V_COUNTER_BASE_IDX 2 4968#define regDSCL1_DSCL_MEM_PWR_CTRL 0x0e82 4969#define regDSCL1_DSCL_MEM_PWR_CTRL_BASE_IDX 2 4970#define regDSCL1_DSCL_MEM_PWR_STATUS 0x0e83 4971#define regDSCL1_DSCL_MEM_PWR_STATUS_BASE_IDX 2 4972#define regDSCL1_OBUF_CONTROL 0x0e84 4973#define regDSCL1_OBUF_CONTROL_BASE_IDX 2 4974#define regDSCL1_OBUF_MEM_PWR_CTRL 0x0e85 4975#define regDSCL1_OBUF_MEM_PWR_CTRL_BASE_IDX 2 4976 4977 4978// addressBlock: dce_dc_dpp1_dispdec_cm_dispdec 4979// base address: 0x5ac 4980#define regCM1_CM_CONTROL 0x0e8b 4981#define regCM1_CM_CONTROL_BASE_IDX 2 4982#define regCM1_CM_POST_CSC_CONTROL 0x0e8c 4983#define regCM1_CM_POST_CSC_CONTROL_BASE_IDX 2 4984#define regCM1_CM_POST_CSC_C11_C12 0x0e8d 4985#define regCM1_CM_POST_CSC_C11_C12_BASE_IDX 2 4986#define regCM1_CM_POST_CSC_C13_C14 0x0e8e 4987#define regCM1_CM_POST_CSC_C13_C14_BASE_IDX 2 4988#define regCM1_CM_POST_CSC_C21_C22 0x0e8f 4989#define regCM1_CM_POST_CSC_C21_C22_BASE_IDX 2 4990#define regCM1_CM_POST_CSC_C23_C24 0x0e90 4991#define regCM1_CM_POST_CSC_C23_C24_BASE_IDX 2 4992#define regCM1_CM_POST_CSC_C31_C32 0x0e91 4993#define regCM1_CM_POST_CSC_C31_C32_BASE_IDX 2 4994#define regCM1_CM_POST_CSC_C33_C34 0x0e92 4995#define regCM1_CM_POST_CSC_C33_C34_BASE_IDX 2 4996#define regCM1_CM_POST_CSC_B_C11_C12 0x0e93 4997#define regCM1_CM_POST_CSC_B_C11_C12_BASE_IDX 2 4998#define regCM1_CM_POST_CSC_B_C13_C14 0x0e94 4999#define regCM1_CM_POST_CSC_B_C13_C14_BASE_IDX 2 5000#define regCM1_CM_POST_CSC_B_C21_C22 0x0e95 5001#define regCM1_CM_POST_CSC_B_C21_C22_BASE_IDX 2 5002#define regCM1_CM_POST_CSC_B_C23_C24 0x0e96 5003#define regCM1_CM_POST_CSC_B_C23_C24_BASE_IDX 2 5004#define regCM1_CM_POST_CSC_B_C31_C32 0x0e97 5005#define regCM1_CM_POST_CSC_B_C31_C32_BASE_IDX 2 5006#define regCM1_CM_POST_CSC_B_C33_C34 0x0e98 5007#define regCM1_CM_POST_CSC_B_C33_C34_BASE_IDX 2 5008#define regCM1_CM_GAMUT_REMAP_CONTROL 0x0e99 5009#define regCM1_CM_GAMUT_REMAP_CONTROL_BASE_IDX 2 5010#define regCM1_CM_GAMUT_REMAP_C11_C12 0x0e9a 5011#define regCM1_CM_GAMUT_REMAP_C11_C12_BASE_IDX 2 5012#define regCM1_CM_GAMUT_REMAP_C13_C14 0x0e9b 5013#define regCM1_CM_GAMUT_REMAP_C13_C14_BASE_IDX 2 5014#define regCM1_CM_GAMUT_REMAP_C21_C22 0x0e9c 5015#define regCM1_CM_GAMUT_REMAP_C21_C22_BASE_IDX 2 5016#define regCM1_CM_GAMUT_REMAP_C23_C24 0x0e9d 5017#define regCM1_CM_GAMUT_REMAP_C23_C24_BASE_IDX 2 5018#define regCM1_CM_GAMUT_REMAP_C31_C32 0x0e9e 5019#define regCM1_CM_GAMUT_REMAP_C31_C32_BASE_IDX 2 5020#define regCM1_CM_GAMUT_REMAP_C33_C34 0x0e9f 5021#define regCM1_CM_GAMUT_REMAP_C33_C34_BASE_IDX 2 5022#define regCM1_CM_GAMUT_REMAP_B_C11_C12 0x0ea0 5023#define regCM1_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX 2 5024#define regCM1_CM_GAMUT_REMAP_B_C13_C14 0x0ea1 5025#define regCM1_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX 2 5026#define regCM1_CM_GAMUT_REMAP_B_C21_C22 0x0ea2 5027#define regCM1_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX 2 5028#define regCM1_CM_GAMUT_REMAP_B_C23_C24 0x0ea3 5029#define regCM1_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX 2 5030#define regCM1_CM_GAMUT_REMAP_B_C31_C32 0x0ea4 5031#define regCM1_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX 2 5032#define regCM1_CM_GAMUT_REMAP_B_C33_C34 0x0ea5 5033#define regCM1_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX 2 5034#define regCM1_CM_BIAS_CR_R 0x0ea6 5035#define regCM1_CM_BIAS_CR_R_BASE_IDX 2 5036#define regCM1_CM_BIAS_Y_G_CB_B 0x0ea7 5037#define regCM1_CM_BIAS_Y_G_CB_B_BASE_IDX 2 5038#define regCM1_CM_GAMCOR_CONTROL 0x0ea8 5039#define regCM1_CM_GAMCOR_CONTROL_BASE_IDX 2 5040#define regCM1_CM_GAMCOR_LUT_INDEX 0x0ea9 5041#define regCM1_CM_GAMCOR_LUT_INDEX_BASE_IDX 2 5042#define regCM1_CM_GAMCOR_LUT_DATA 0x0eaa 5043#define regCM1_CM_GAMCOR_LUT_DATA_BASE_IDX 2 5044#define regCM1_CM_GAMCOR_LUT_CONTROL 0x0eab 5045#define regCM1_CM_GAMCOR_LUT_CONTROL_BASE_IDX 2 5046#define regCM1_CM_GAMCOR_RAMA_START_CNTL_B 0x0eac 5047#define regCM1_CM_GAMCOR_RAMA_START_CNTL_B_BASE_IDX 2 5048#define regCM1_CM_GAMCOR_RAMA_START_CNTL_G 0x0ead 5049#define regCM1_CM_GAMCOR_RAMA_START_CNTL_G_BASE_IDX 2 5050#define regCM1_CM_GAMCOR_RAMA_START_CNTL_R 0x0eae 5051#define regCM1_CM_GAMCOR_RAMA_START_CNTL_R_BASE_IDX 2 5052#define regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B 0x0eaf 5053#define regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B_BASE_IDX 2 5054#define regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G 0x0eb0 5055#define regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2 5056#define regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R 0x0eb1 5057#define regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R_BASE_IDX 2 5058#define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_B 0x0eb2 5059#define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_B_BASE_IDX 2 5060#define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_G 0x0eb3 5061#define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_G_BASE_IDX 2 5062#define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_R 0x0eb4 5063#define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_R_BASE_IDX 2 5064#define regCM1_CM_GAMCOR_RAMA_END_CNTL1_B 0x0eb5 5065#define regCM1_CM_GAMCOR_RAMA_END_CNTL1_B_BASE_IDX 2 5066#define regCM1_CM_GAMCOR_RAMA_END_CNTL2_B 0x0eb6 5067#define regCM1_CM_GAMCOR_RAMA_END_CNTL2_B_BASE_IDX 2 5068#define regCM1_CM_GAMCOR_RAMA_END_CNTL1_G 0x0eb7 5069#define regCM1_CM_GAMCOR_RAMA_END_CNTL1_G_BASE_IDX 2 5070#define regCM1_CM_GAMCOR_RAMA_END_CNTL2_G 0x0eb8 5071#define regCM1_CM_GAMCOR_RAMA_END_CNTL2_G_BASE_IDX 2 5072#define regCM1_CM_GAMCOR_RAMA_END_CNTL1_R 0x0eb9 5073#define regCM1_CM_GAMCOR_RAMA_END_CNTL1_R_BASE_IDX 2 5074#define regCM1_CM_GAMCOR_RAMA_END_CNTL2_R 0x0eba 5075#define regCM1_CM_GAMCOR_RAMA_END_CNTL2_R_BASE_IDX 2 5076#define regCM1_CM_GAMCOR_RAMA_OFFSET_B 0x0ebb 5077#define regCM1_CM_GAMCOR_RAMA_OFFSET_B_BASE_IDX 2 5078#define regCM1_CM_GAMCOR_RAMA_OFFSET_G 0x0ebc 5079#define regCM1_CM_GAMCOR_RAMA_OFFSET_G_BASE_IDX 2 5080#define regCM1_CM_GAMCOR_RAMA_OFFSET_R 0x0ebd 5081#define regCM1_CM_GAMCOR_RAMA_OFFSET_R_BASE_IDX 2 5082#define regCM1_CM_GAMCOR_RAMA_REGION_0_1 0x0ebe 5083#define regCM1_CM_GAMCOR_RAMA_REGION_0_1_BASE_IDX 2 5084#define regCM1_CM_GAMCOR_RAMA_REGION_2_3 0x0ebf 5085#define regCM1_CM_GAMCOR_RAMA_REGION_2_3_BASE_IDX 2 5086#define regCM1_CM_GAMCOR_RAMA_REGION_4_5 0x0ec0 5087#define regCM1_CM_GAMCOR_RAMA_REGION_4_5_BASE_IDX 2 5088#define regCM1_CM_GAMCOR_RAMA_REGION_6_7 0x0ec1 5089#define regCM1_CM_GAMCOR_RAMA_REGION_6_7_BASE_IDX 2 5090#define regCM1_CM_GAMCOR_RAMA_REGION_8_9 0x0ec2 5091#define regCM1_CM_GAMCOR_RAMA_REGION_8_9_BASE_IDX 2 5092#define regCM1_CM_GAMCOR_RAMA_REGION_10_11 0x0ec3 5093#define regCM1_CM_GAMCOR_RAMA_REGION_10_11_BASE_IDX 2 5094#define regCM1_CM_GAMCOR_RAMA_REGION_12_13 0x0ec4 5095#define regCM1_CM_GAMCOR_RAMA_REGION_12_13_BASE_IDX 2 5096#define regCM1_CM_GAMCOR_RAMA_REGION_14_15 0x0ec5 5097#define regCM1_CM_GAMCOR_RAMA_REGION_14_15_BASE_IDX 2 5098#define regCM1_CM_GAMCOR_RAMA_REGION_16_17 0x0ec6 5099#define regCM1_CM_GAMCOR_RAMA_REGION_16_17_BASE_IDX 2 5100#define regCM1_CM_GAMCOR_RAMA_REGION_18_19 0x0ec7 5101#define regCM1_CM_GAMCOR_RAMA_REGION_18_19_BASE_IDX 2 5102#define regCM1_CM_GAMCOR_RAMA_REGION_20_21 0x0ec8 5103#define regCM1_CM_GAMCOR_RAMA_REGION_20_21_BASE_IDX 2 5104#define regCM1_CM_GAMCOR_RAMA_REGION_22_23 0x0ec9 5105#define regCM1_CM_GAMCOR_RAMA_REGION_22_23_BASE_IDX 2 5106#define regCM1_CM_GAMCOR_RAMA_REGION_24_25 0x0eca 5107#define regCM1_CM_GAMCOR_RAMA_REGION_24_25_BASE_IDX 2 5108#define regCM1_CM_GAMCOR_RAMA_REGION_26_27 0x0ecb 5109#define regCM1_CM_GAMCOR_RAMA_REGION_26_27_BASE_IDX 2 5110#define regCM1_CM_GAMCOR_RAMA_REGION_28_29 0x0ecc 5111#define regCM1_CM_GAMCOR_RAMA_REGION_28_29_BASE_IDX 2 5112#define regCM1_CM_GAMCOR_RAMA_REGION_30_31 0x0ecd 5113#define regCM1_CM_GAMCOR_RAMA_REGION_30_31_BASE_IDX 2 5114#define regCM1_CM_GAMCOR_RAMA_REGION_32_33 0x0ece 5115#define regCM1_CM_GAMCOR_RAMA_REGION_32_33_BASE_IDX 2 5116#define regCM1_CM_GAMCOR_RAMB_START_CNTL_B 0x0ecf 5117#define regCM1_CM_GAMCOR_RAMB_START_CNTL_B_BASE_IDX 2 5118#define regCM1_CM_GAMCOR_RAMB_START_CNTL_G 0x0ed0 5119#define regCM1_CM_GAMCOR_RAMB_START_CNTL_G_BASE_IDX 2 5120#define regCM1_CM_GAMCOR_RAMB_START_CNTL_R 0x0ed1 5121#define regCM1_CM_GAMCOR_RAMB_START_CNTL_R_BASE_IDX 2 5122#define regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B 0x0ed2 5123#define regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B_BASE_IDX 2 5124#define regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G 0x0ed3 5125#define regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G_BASE_IDX 2 5126#define regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R 0x0ed4 5127#define regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R_BASE_IDX 2 5128#define regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_B 0x0ed5 5129#define regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_B_BASE_IDX 2 5130#define regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_G 0x0ed6 5131#define regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_G_BASE_IDX 2 5132#define regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_R 0x0ed7 5133#define regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_R_BASE_IDX 2 5134#define regCM1_CM_GAMCOR_RAMB_END_CNTL1_B 0x0ed8 5135#define regCM1_CM_GAMCOR_RAMB_END_CNTL1_B_BASE_IDX 2 5136#define regCM1_CM_GAMCOR_RAMB_END_CNTL2_B 0x0ed9 5137#define regCM1_CM_GAMCOR_RAMB_END_CNTL2_B_BASE_IDX 2 5138#define regCM1_CM_GAMCOR_RAMB_END_CNTL1_G 0x0eda 5139#define regCM1_CM_GAMCOR_RAMB_END_CNTL1_G_BASE_IDX 2 5140#define regCM1_CM_GAMCOR_RAMB_END_CNTL2_G 0x0edb 5141#define regCM1_CM_GAMCOR_RAMB_END_CNTL2_G_BASE_IDX 2 5142#define regCM1_CM_GAMCOR_RAMB_END_CNTL1_R 0x0edc 5143#define regCM1_CM_GAMCOR_RAMB_END_CNTL1_R_BASE_IDX 2 5144#define regCM1_CM_GAMCOR_RAMB_END_CNTL2_R 0x0edd 5145#define regCM1_CM_GAMCOR_RAMB_END_CNTL2_R_BASE_IDX 2 5146#define regCM1_CM_GAMCOR_RAMB_OFFSET_B 0x0ede 5147#define regCM1_CM_GAMCOR_RAMB_OFFSET_B_BASE_IDX 2 5148#define regCM1_CM_GAMCOR_RAMB_OFFSET_G 0x0edf 5149#define regCM1_CM_GAMCOR_RAMB_OFFSET_G_BASE_IDX 2 5150#define regCM1_CM_GAMCOR_RAMB_OFFSET_R 0x0ee0 5151#define regCM1_CM_GAMCOR_RAMB_OFFSET_R_BASE_IDX 2 5152#define regCM1_CM_GAMCOR_RAMB_REGION_0_1 0x0ee1 5153#define regCM1_CM_GAMCOR_RAMB_REGION_0_1_BASE_IDX 2 5154#define regCM1_CM_GAMCOR_RAMB_REGION_2_3 0x0ee2 5155#define regCM1_CM_GAMCOR_RAMB_REGION_2_3_BASE_IDX 2 5156#define regCM1_CM_GAMCOR_RAMB_REGION_4_5 0x0ee3 5157#define regCM1_CM_GAMCOR_RAMB_REGION_4_5_BASE_IDX 2 5158#define regCM1_CM_GAMCOR_RAMB_REGION_6_7 0x0ee4 5159#define regCM1_CM_GAMCOR_RAMB_REGION_6_7_BASE_IDX 2 5160#define regCM1_CM_GAMCOR_RAMB_REGION_8_9 0x0ee5 5161#define regCM1_CM_GAMCOR_RAMB_REGION_8_9_BASE_IDX 2 5162#define regCM1_CM_GAMCOR_RAMB_REGION_10_11 0x0ee6 5163#define regCM1_CM_GAMCOR_RAMB_REGION_10_11_BASE_IDX 2 5164#define regCM1_CM_GAMCOR_RAMB_REGION_12_13 0x0ee7 5165#define regCM1_CM_GAMCOR_RAMB_REGION_12_13_BASE_IDX 2 5166#define regCM1_CM_GAMCOR_RAMB_REGION_14_15 0x0ee8 5167#define regCM1_CM_GAMCOR_RAMB_REGION_14_15_BASE_IDX 2 5168#define regCM1_CM_GAMCOR_RAMB_REGION_16_17 0x0ee9 5169#define regCM1_CM_GAMCOR_RAMB_REGION_16_17_BASE_IDX 2 5170#define regCM1_CM_GAMCOR_RAMB_REGION_18_19 0x0eea 5171#define regCM1_CM_GAMCOR_RAMB_REGION_18_19_BASE_IDX 2 5172#define regCM1_CM_GAMCOR_RAMB_REGION_20_21 0x0eeb 5173#define regCM1_CM_GAMCOR_RAMB_REGION_20_21_BASE_IDX 2 5174#define regCM1_CM_GAMCOR_RAMB_REGION_22_23 0x0eec 5175#define regCM1_CM_GAMCOR_RAMB_REGION_22_23_BASE_IDX 2 5176#define regCM1_CM_GAMCOR_RAMB_REGION_24_25 0x0eed 5177#define regCM1_CM_GAMCOR_RAMB_REGION_24_25_BASE_IDX 2 5178#define regCM1_CM_GAMCOR_RAMB_REGION_26_27 0x0eee 5179#define regCM1_CM_GAMCOR_RAMB_REGION_26_27_BASE_IDX 2 5180#define regCM1_CM_GAMCOR_RAMB_REGION_28_29 0x0eef 5181#define regCM1_CM_GAMCOR_RAMB_REGION_28_29_BASE_IDX 2 5182#define regCM1_CM_GAMCOR_RAMB_REGION_30_31 0x0ef0 5183#define regCM1_CM_GAMCOR_RAMB_REGION_30_31_BASE_IDX 2 5184#define regCM1_CM_GAMCOR_RAMB_REGION_32_33 0x0ef1 5185#define regCM1_CM_GAMCOR_RAMB_REGION_32_33_BASE_IDX 2 5186#define regCM1_CM_HDR_MULT_COEF 0x0ef2 5187#define regCM1_CM_HDR_MULT_COEF_BASE_IDX 2 5188#define regCM1_CM_MEM_PWR_CTRL 0x0ef3 5189#define regCM1_CM_MEM_PWR_CTRL_BASE_IDX 2 5190#define regCM1_CM_MEM_PWR_STATUS 0x0ef4 5191#define regCM1_CM_MEM_PWR_STATUS_BASE_IDX 2 5192#define regCM1_CM_DEALPHA 0x0ef6 5193#define regCM1_CM_DEALPHA_BASE_IDX 2 5194#define regCM1_CM_COEF_FORMAT 0x0ef7 5195#define regCM1_CM_COEF_FORMAT_BASE_IDX 2 5196#define regCM1_CM_TEST_DEBUG_INDEX 0x0ef8 5197#define regCM1_CM_TEST_DEBUG_INDEX_BASE_IDX 2 5198#define regCM1_CM_TEST_DEBUG_DATA 0x0ef9 5199#define regCM1_CM_TEST_DEBUG_DATA_BASE_IDX 2 5200 5201 5202// addressBlock: dce_dc_dpp1_dispdec_dpp_dcperfmon_dc_perfmon_dispdec 5203// base address: 0x3e3c 5204#define regDC_PERFMON12_PERFCOUNTER_CNTL 0x0f8f 5205#define regDC_PERFMON12_PERFCOUNTER_CNTL_BASE_IDX 2 5206#define regDC_PERFMON12_PERFCOUNTER_CNTL2 0x0f90 5207#define regDC_PERFMON12_PERFCOUNTER_CNTL2_BASE_IDX 2 5208#define regDC_PERFMON12_PERFCOUNTER_STATE 0x0f91 5209#define regDC_PERFMON12_PERFCOUNTER_STATE_BASE_IDX 2 5210#define regDC_PERFMON12_PERFMON_CNTL 0x0f92 5211#define regDC_PERFMON12_PERFMON_CNTL_BASE_IDX 2 5212#define regDC_PERFMON12_PERFMON_CNTL2 0x0f93 5213#define regDC_PERFMON12_PERFMON_CNTL2_BASE_IDX 2 5214#define regDC_PERFMON12_PERFMON_CVALUE_INT_MISC 0x0f94 5215#define regDC_PERFMON12_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 5216#define regDC_PERFMON12_PERFMON_CVALUE_LOW 0x0f95 5217#define regDC_PERFMON12_PERFMON_CVALUE_LOW_BASE_IDX 2 5218#define regDC_PERFMON12_PERFMON_HI 0x0f96 5219#define regDC_PERFMON12_PERFMON_HI_BASE_IDX 2 5220#define regDC_PERFMON12_PERFMON_LOW 0x0f97 5221#define regDC_PERFMON12_PERFMON_LOW_BASE_IDX 2 5222 5223 5224// addressBlock: dce_dc_dpp2_dispdec_dpp_top_dispdec 5225// base address: 0xb58 5226#define regDPP_TOP2_DPP_CONTROL 0x0f9b 5227#define regDPP_TOP2_DPP_CONTROL_BASE_IDX 2 5228#define regDPP_TOP2_DPP_SOFT_RESET 0x0f9c 5229#define regDPP_TOP2_DPP_SOFT_RESET_BASE_IDX 2 5230#define regDPP_TOP2_DPP_CRC_VAL_R_G 0x0f9d 5231#define regDPP_TOP2_DPP_CRC_VAL_R_G_BASE_IDX 2 5232#define regDPP_TOP2_DPP_CRC_VAL_B_A 0x0f9e 5233#define regDPP_TOP2_DPP_CRC_VAL_B_A_BASE_IDX 2 5234#define regDPP_TOP2_DPP_CRC_CTRL 0x0f9f 5235#define regDPP_TOP2_DPP_CRC_CTRL_BASE_IDX 2 5236#define regDPP_TOP2_HOST_READ_CONTROL 0x0fa0 5237#define regDPP_TOP2_HOST_READ_CONTROL_BASE_IDX 2 5238 5239 5240// addressBlock: dce_dc_dpp2_dispdec_cnvc_cfg_dispdec 5241// base address: 0xb58 5242#define regCNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT 0x0fa5 5243#define regCNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX 2 5244#define regCNVC_CFG2_FORMAT_CONTROL 0x0fa6 5245#define regCNVC_CFG2_FORMAT_CONTROL_BASE_IDX 2 5246#define regCNVC_CFG2_FCNV_FP_BIAS_R 0x0fa7 5247#define regCNVC_CFG2_FCNV_FP_BIAS_R_BASE_IDX 2 5248#define regCNVC_CFG2_FCNV_FP_BIAS_G 0x0fa8 5249#define regCNVC_CFG2_FCNV_FP_BIAS_G_BASE_IDX 2 5250#define regCNVC_CFG2_FCNV_FP_BIAS_B 0x0fa9 5251#define regCNVC_CFG2_FCNV_FP_BIAS_B_BASE_IDX 2 5252#define regCNVC_CFG2_FCNV_FP_SCALE_R 0x0faa 5253#define regCNVC_CFG2_FCNV_FP_SCALE_R_BASE_IDX 2 5254#define regCNVC_CFG2_FCNV_FP_SCALE_G 0x0fab 5255#define regCNVC_CFG2_FCNV_FP_SCALE_G_BASE_IDX 2 5256#define regCNVC_CFG2_FCNV_FP_SCALE_B 0x0fac 5257#define regCNVC_CFG2_FCNV_FP_SCALE_B_BASE_IDX 2 5258#define regCNVC_CFG2_COLOR_KEYER_CONTROL 0x0fad 5259#define regCNVC_CFG2_COLOR_KEYER_CONTROL_BASE_IDX 2 5260#define regCNVC_CFG2_COLOR_KEYER_ALPHA 0x0fae 5261#define regCNVC_CFG2_COLOR_KEYER_ALPHA_BASE_IDX 2 5262#define regCNVC_CFG2_COLOR_KEYER_RED 0x0faf 5263#define regCNVC_CFG2_COLOR_KEYER_RED_BASE_IDX 2 5264#define regCNVC_CFG2_COLOR_KEYER_GREEN 0x0fb0 5265#define regCNVC_CFG2_COLOR_KEYER_GREEN_BASE_IDX 2 5266#define regCNVC_CFG2_COLOR_KEYER_BLUE 0x0fb1 5267#define regCNVC_CFG2_COLOR_KEYER_BLUE_BASE_IDX 2 5268#define regCNVC_CFG2_ALPHA_2BIT_LUT 0x0fb3 5269#define regCNVC_CFG2_ALPHA_2BIT_LUT_BASE_IDX 2 5270#define regCNVC_CFG2_PRE_DEALPHA 0x0fb4 5271#define regCNVC_CFG2_PRE_DEALPHA_BASE_IDX 2 5272#define regCNVC_CFG2_PRE_CSC_MODE 0x0fb5 5273#define regCNVC_CFG2_PRE_CSC_MODE_BASE_IDX 2 5274#define regCNVC_CFG2_PRE_CSC_C11_C12 0x0fb6 5275#define regCNVC_CFG2_PRE_CSC_C11_C12_BASE_IDX 2 5276#define regCNVC_CFG2_PRE_CSC_C13_C14 0x0fb7 5277#define regCNVC_CFG2_PRE_CSC_C13_C14_BASE_IDX 2 5278#define regCNVC_CFG2_PRE_CSC_C21_C22 0x0fb8 5279#define regCNVC_CFG2_PRE_CSC_C21_C22_BASE_IDX 2 5280#define regCNVC_CFG2_PRE_CSC_C23_C24 0x0fb9 5281#define regCNVC_CFG2_PRE_CSC_C23_C24_BASE_IDX 2 5282#define regCNVC_CFG2_PRE_CSC_C31_C32 0x0fba 5283#define regCNVC_CFG2_PRE_CSC_C31_C32_BASE_IDX 2 5284#define regCNVC_CFG2_PRE_CSC_C33_C34 0x0fbb 5285#define regCNVC_CFG2_PRE_CSC_C33_C34_BASE_IDX 2 5286#define regCNVC_CFG2_PRE_CSC_B_C11_C12 0x0fbc 5287#define regCNVC_CFG2_PRE_CSC_B_C11_C12_BASE_IDX 2 5288#define regCNVC_CFG2_PRE_CSC_B_C13_C14 0x0fbd 5289#define regCNVC_CFG2_PRE_CSC_B_C13_C14_BASE_IDX 2 5290#define regCNVC_CFG2_PRE_CSC_B_C21_C22 0x0fbe 5291#define regCNVC_CFG2_PRE_CSC_B_C21_C22_BASE_IDX 2 5292#define regCNVC_CFG2_PRE_CSC_B_C23_C24 0x0fbf 5293#define regCNVC_CFG2_PRE_CSC_B_C23_C24_BASE_IDX 2 5294#define regCNVC_CFG2_PRE_CSC_B_C31_C32 0x0fc0 5295#define regCNVC_CFG2_PRE_CSC_B_C31_C32_BASE_IDX 2 5296#define regCNVC_CFG2_PRE_CSC_B_C33_C34 0x0fc1 5297#define regCNVC_CFG2_PRE_CSC_B_C33_C34_BASE_IDX 2 5298#define regCNVC_CFG2_CNVC_COEF_FORMAT 0x0fc2 5299#define regCNVC_CFG2_CNVC_COEF_FORMAT_BASE_IDX 2 5300#define regCNVC_CFG2_PRE_DEGAM 0x0fc3 5301#define regCNVC_CFG2_PRE_DEGAM_BASE_IDX 2 5302#define regCNVC_CFG2_PRE_REALPHA 0x0fc4 5303#define regCNVC_CFG2_PRE_REALPHA_BASE_IDX 2 5304 5305 5306// addressBlock: dce_dc_dpp2_dispdec_cnvc_cur_dispdec 5307// base address: 0xb58 5308#define regCNVC_CUR2_CURSOR0_CONTROL 0x0fc7 5309#define regCNVC_CUR2_CURSOR0_CONTROL_BASE_IDX 2 5310#define regCNVC_CUR2_CURSOR0_COLOR0 0x0fc8 5311#define regCNVC_CUR2_CURSOR0_COLOR0_BASE_IDX 2 5312#define regCNVC_CUR2_CURSOR0_COLOR1 0x0fc9 5313#define regCNVC_CUR2_CURSOR0_COLOR1_BASE_IDX 2 5314#define regCNVC_CUR2_CURSOR0_FP_SCALE_BIAS 0x0fca 5315#define regCNVC_CUR2_CURSOR0_FP_SCALE_BIAS_BASE_IDX 2 5316 5317 5318// addressBlock: dce_dc_dpp2_dispdec_dscl_dispdec 5319// base address: 0xb58 5320#define regDSCL2_SCL_COEF_RAM_TAP_SELECT 0x0fcf 5321#define regDSCL2_SCL_COEF_RAM_TAP_SELECT_BASE_IDX 2 5322#define regDSCL2_SCL_COEF_RAM_TAP_DATA 0x0fd0 5323#define regDSCL2_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2 5324#define regDSCL2_SCL_MODE 0x0fd1 5325#define regDSCL2_SCL_MODE_BASE_IDX 2 5326#define regDSCL2_SCL_TAP_CONTROL 0x0fd2 5327#define regDSCL2_SCL_TAP_CONTROL_BASE_IDX 2 5328#define regDSCL2_DSCL_CONTROL 0x0fd3 5329#define regDSCL2_DSCL_CONTROL_BASE_IDX 2 5330#define regDSCL2_DSCL_2TAP_CONTROL 0x0fd4 5331#define regDSCL2_DSCL_2TAP_CONTROL_BASE_IDX 2 5332#define regDSCL2_SCL_MANUAL_REPLICATE_CONTROL 0x0fd5 5333#define regDSCL2_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2 5334#define regDSCL2_SCL_HORZ_FILTER_SCALE_RATIO 0x0fd6 5335#define regDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2 5336#define regDSCL2_SCL_HORZ_FILTER_INIT 0x0fd7 5337#define regDSCL2_SCL_HORZ_FILTER_INIT_BASE_IDX 2 5338#define regDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C 0x0fd8 5339#define regDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX 2 5340#define regDSCL2_SCL_HORZ_FILTER_INIT_C 0x0fd9 5341#define regDSCL2_SCL_HORZ_FILTER_INIT_C_BASE_IDX 2 5342#define regDSCL2_SCL_VERT_FILTER_SCALE_RATIO 0x0fda 5343#define regDSCL2_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2 5344#define regDSCL2_SCL_VERT_FILTER_INIT 0x0fdb 5345#define regDSCL2_SCL_VERT_FILTER_INIT_BASE_IDX 2 5346#define regDSCL2_SCL_VERT_FILTER_INIT_BOT 0x0fdc 5347#define regDSCL2_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2 5348#define regDSCL2_SCL_VERT_FILTER_SCALE_RATIO_C 0x0fdd 5349#define regDSCL2_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX 2 5350#define regDSCL2_SCL_VERT_FILTER_INIT_C 0x0fde 5351#define regDSCL2_SCL_VERT_FILTER_INIT_C_BASE_IDX 2 5352#define regDSCL2_SCL_VERT_FILTER_INIT_BOT_C 0x0fdf 5353#define regDSCL2_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX 2 5354#define regDSCL2_SCL_BLACK_COLOR 0x0fe0 5355#define regDSCL2_SCL_BLACK_COLOR_BASE_IDX 2 5356#define regDSCL2_DSCL_UPDATE 0x0fe1 5357#define regDSCL2_DSCL_UPDATE_BASE_IDX 2 5358#define regDSCL2_DSCL_AUTOCAL 0x0fe2 5359#define regDSCL2_DSCL_AUTOCAL_BASE_IDX 2 5360#define regDSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT 0x0fe3 5361#define regDSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2 5362#define regDSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM 0x0fe4 5363#define regDSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2 5364#define regDSCL2_OTG_H_BLANK 0x0fe5 5365#define regDSCL2_OTG_H_BLANK_BASE_IDX 2 5366#define regDSCL2_OTG_V_BLANK 0x0fe6 5367#define regDSCL2_OTG_V_BLANK_BASE_IDX 2 5368#define regDSCL2_RECOUT_START 0x0fe7 5369#define regDSCL2_RECOUT_START_BASE_IDX 2 5370#define regDSCL2_RECOUT_SIZE 0x0fe8 5371#define regDSCL2_RECOUT_SIZE_BASE_IDX 2 5372#define regDSCL2_MPC_SIZE 0x0fe9 5373#define regDSCL2_MPC_SIZE_BASE_IDX 2 5374#define regDSCL2_LB_DATA_FORMAT 0x0fea 5375#define regDSCL2_LB_DATA_FORMAT_BASE_IDX 2 5376#define regDSCL2_LB_MEMORY_CTRL 0x0feb 5377#define regDSCL2_LB_MEMORY_CTRL_BASE_IDX 2 5378#define regDSCL2_LB_V_COUNTER 0x0fec 5379#define regDSCL2_LB_V_COUNTER_BASE_IDX 2 5380#define regDSCL2_DSCL_MEM_PWR_CTRL 0x0fed 5381#define regDSCL2_DSCL_MEM_PWR_CTRL_BASE_IDX 2 5382#define regDSCL2_DSCL_MEM_PWR_STATUS 0x0fee 5383#define regDSCL2_DSCL_MEM_PWR_STATUS_BASE_IDX 2 5384#define regDSCL2_OBUF_CONTROL 0x0fef 5385#define regDSCL2_OBUF_CONTROL_BASE_IDX 2 5386#define regDSCL2_OBUF_MEM_PWR_CTRL 0x0ff0 5387#define regDSCL2_OBUF_MEM_PWR_CTRL_BASE_IDX 2 5388 5389 5390// addressBlock: dce_dc_dpp2_dispdec_cm_dispdec 5391// base address: 0xb58 5392#define regCM2_CM_CONTROL 0x0ff6 5393#define regCM2_CM_CONTROL_BASE_IDX 2 5394#define regCM2_CM_POST_CSC_CONTROL 0x0ff7 5395#define regCM2_CM_POST_CSC_CONTROL_BASE_IDX 2 5396#define regCM2_CM_POST_CSC_C11_C12 0x0ff8 5397#define regCM2_CM_POST_CSC_C11_C12_BASE_IDX 2 5398#define regCM2_CM_POST_CSC_C13_C14 0x0ff9 5399#define regCM2_CM_POST_CSC_C13_C14_BASE_IDX 2 5400#define regCM2_CM_POST_CSC_C21_C22 0x0ffa 5401#define regCM2_CM_POST_CSC_C21_C22_BASE_IDX 2 5402#define regCM2_CM_POST_CSC_C23_C24 0x0ffb 5403#define regCM2_CM_POST_CSC_C23_C24_BASE_IDX 2 5404#define regCM2_CM_POST_CSC_C31_C32 0x0ffc 5405#define regCM2_CM_POST_CSC_C31_C32_BASE_IDX 2 5406#define regCM2_CM_POST_CSC_C33_C34 0x0ffd 5407#define regCM2_CM_POST_CSC_C33_C34_BASE_IDX 2 5408#define regCM2_CM_POST_CSC_B_C11_C12 0x0ffe 5409#define regCM2_CM_POST_CSC_B_C11_C12_BASE_IDX 2 5410#define regCM2_CM_POST_CSC_B_C13_C14 0x0fff 5411#define regCM2_CM_POST_CSC_B_C13_C14_BASE_IDX 2 5412#define regCM2_CM_POST_CSC_B_C21_C22 0x1000 5413#define regCM2_CM_POST_CSC_B_C21_C22_BASE_IDX 2 5414#define regCM2_CM_POST_CSC_B_C23_C24 0x1001 5415#define regCM2_CM_POST_CSC_B_C23_C24_BASE_IDX 2 5416#define regCM2_CM_POST_CSC_B_C31_C32 0x1002 5417#define regCM2_CM_POST_CSC_B_C31_C32_BASE_IDX 2 5418#define regCM2_CM_POST_CSC_B_C33_C34 0x1003 5419#define regCM2_CM_POST_CSC_B_C33_C34_BASE_IDX 2 5420#define regCM2_CM_GAMUT_REMAP_CONTROL 0x1004 5421#define regCM2_CM_GAMUT_REMAP_CONTROL_BASE_IDX 2 5422#define regCM2_CM_GAMUT_REMAP_C11_C12 0x1005 5423#define regCM2_CM_GAMUT_REMAP_C11_C12_BASE_IDX 2 5424#define regCM2_CM_GAMUT_REMAP_C13_C14 0x1006 5425#define regCM2_CM_GAMUT_REMAP_C13_C14_BASE_IDX 2 5426#define regCM2_CM_GAMUT_REMAP_C21_C22 0x1007 5427#define regCM2_CM_GAMUT_REMAP_C21_C22_BASE_IDX 2 5428#define regCM2_CM_GAMUT_REMAP_C23_C24 0x1008 5429#define regCM2_CM_GAMUT_REMAP_C23_C24_BASE_IDX 2 5430#define regCM2_CM_GAMUT_REMAP_C31_C32 0x1009 5431#define regCM2_CM_GAMUT_REMAP_C31_C32_BASE_IDX 2 5432#define regCM2_CM_GAMUT_REMAP_C33_C34 0x100a 5433#define regCM2_CM_GAMUT_REMAP_C33_C34_BASE_IDX 2 5434#define regCM2_CM_GAMUT_REMAP_B_C11_C12 0x100b 5435#define regCM2_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX 2 5436#define regCM2_CM_GAMUT_REMAP_B_C13_C14 0x100c 5437#define regCM2_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX 2 5438#define regCM2_CM_GAMUT_REMAP_B_C21_C22 0x100d 5439#define regCM2_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX 2 5440#define regCM2_CM_GAMUT_REMAP_B_C23_C24 0x100e 5441#define regCM2_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX 2 5442#define regCM2_CM_GAMUT_REMAP_B_C31_C32 0x100f 5443#define regCM2_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX 2 5444#define regCM2_CM_GAMUT_REMAP_B_C33_C34 0x1010 5445#define regCM2_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX 2 5446#define regCM2_CM_BIAS_CR_R 0x1011 5447#define regCM2_CM_BIAS_CR_R_BASE_IDX 2 5448#define regCM2_CM_BIAS_Y_G_CB_B 0x1012 5449#define regCM2_CM_BIAS_Y_G_CB_B_BASE_IDX 2 5450#define regCM2_CM_GAMCOR_CONTROL 0x1013 5451#define regCM2_CM_GAMCOR_CONTROL_BASE_IDX 2 5452#define regCM2_CM_GAMCOR_LUT_INDEX 0x1014 5453#define regCM2_CM_GAMCOR_LUT_INDEX_BASE_IDX 2 5454#define regCM2_CM_GAMCOR_LUT_DATA 0x1015 5455#define regCM2_CM_GAMCOR_LUT_DATA_BASE_IDX 2 5456#define regCM2_CM_GAMCOR_LUT_CONTROL 0x1016 5457#define regCM2_CM_GAMCOR_LUT_CONTROL_BASE_IDX 2 5458#define regCM2_CM_GAMCOR_RAMA_START_CNTL_B 0x1017 5459#define regCM2_CM_GAMCOR_RAMA_START_CNTL_B_BASE_IDX 2 5460#define regCM2_CM_GAMCOR_RAMA_START_CNTL_G 0x1018 5461#define regCM2_CM_GAMCOR_RAMA_START_CNTL_G_BASE_IDX 2 5462#define regCM2_CM_GAMCOR_RAMA_START_CNTL_R 0x1019 5463#define regCM2_CM_GAMCOR_RAMA_START_CNTL_R_BASE_IDX 2 5464#define regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B 0x101a 5465#define regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B_BASE_IDX 2 5466#define regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G 0x101b 5467#define regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2 5468#define regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R 0x101c 5469#define regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R_BASE_IDX 2 5470#define regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_B 0x101d 5471#define regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_B_BASE_IDX 2 5472#define regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_G 0x101e 5473#define regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_G_BASE_IDX 2 5474#define regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_R 0x101f 5475#define regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_R_BASE_IDX 2 5476#define regCM2_CM_GAMCOR_RAMA_END_CNTL1_B 0x1020 5477#define regCM2_CM_GAMCOR_RAMA_END_CNTL1_B_BASE_IDX 2 5478#define regCM2_CM_GAMCOR_RAMA_END_CNTL2_B 0x1021 5479#define regCM2_CM_GAMCOR_RAMA_END_CNTL2_B_BASE_IDX 2 5480#define regCM2_CM_GAMCOR_RAMA_END_CNTL1_G 0x1022 5481#define regCM2_CM_GAMCOR_RAMA_END_CNTL1_G_BASE_IDX 2 5482#define regCM2_CM_GAMCOR_RAMA_END_CNTL2_G 0x1023 5483#define regCM2_CM_GAMCOR_RAMA_END_CNTL2_G_BASE_IDX 2 5484#define regCM2_CM_GAMCOR_RAMA_END_CNTL1_R 0x1024 5485#define regCM2_CM_GAMCOR_RAMA_END_CNTL1_R_BASE_IDX 2 5486#define regCM2_CM_GAMCOR_RAMA_END_CNTL2_R 0x1025 5487#define regCM2_CM_GAMCOR_RAMA_END_CNTL2_R_BASE_IDX 2 5488#define regCM2_CM_GAMCOR_RAMA_OFFSET_B 0x1026 5489#define regCM2_CM_GAMCOR_RAMA_OFFSET_B_BASE_IDX 2 5490#define regCM2_CM_GAMCOR_RAMA_OFFSET_G 0x1027 5491#define regCM2_CM_GAMCOR_RAMA_OFFSET_G_BASE_IDX 2 5492#define regCM2_CM_GAMCOR_RAMA_OFFSET_R 0x1028 5493#define regCM2_CM_GAMCOR_RAMA_OFFSET_R_BASE_IDX 2 5494#define regCM2_CM_GAMCOR_RAMA_REGION_0_1 0x1029 5495#define regCM2_CM_GAMCOR_RAMA_REGION_0_1_BASE_IDX 2 5496#define regCM2_CM_GAMCOR_RAMA_REGION_2_3 0x102a 5497#define regCM2_CM_GAMCOR_RAMA_REGION_2_3_BASE_IDX 2 5498#define regCM2_CM_GAMCOR_RAMA_REGION_4_5 0x102b 5499#define regCM2_CM_GAMCOR_RAMA_REGION_4_5_BASE_IDX 2 5500#define regCM2_CM_GAMCOR_RAMA_REGION_6_7 0x102c 5501#define regCM2_CM_GAMCOR_RAMA_REGION_6_7_BASE_IDX 2 5502#define regCM2_CM_GAMCOR_RAMA_REGION_8_9 0x102d 5503#define regCM2_CM_GAMCOR_RAMA_REGION_8_9_BASE_IDX 2 5504#define regCM2_CM_GAMCOR_RAMA_REGION_10_11 0x102e 5505#define regCM2_CM_GAMCOR_RAMA_REGION_10_11_BASE_IDX 2 5506#define regCM2_CM_GAMCOR_RAMA_REGION_12_13 0x102f 5507#define regCM2_CM_GAMCOR_RAMA_REGION_12_13_BASE_IDX 2 5508#define regCM2_CM_GAMCOR_RAMA_REGION_14_15 0x1030 5509#define regCM2_CM_GAMCOR_RAMA_REGION_14_15_BASE_IDX 2 5510#define regCM2_CM_GAMCOR_RAMA_REGION_16_17 0x1031 5511#define regCM2_CM_GAMCOR_RAMA_REGION_16_17_BASE_IDX 2 5512#define regCM2_CM_GAMCOR_RAMA_REGION_18_19 0x1032 5513#define regCM2_CM_GAMCOR_RAMA_REGION_18_19_BASE_IDX 2 5514#define regCM2_CM_GAMCOR_RAMA_REGION_20_21 0x1033 5515#define regCM2_CM_GAMCOR_RAMA_REGION_20_21_BASE_IDX 2 5516#define regCM2_CM_GAMCOR_RAMA_REGION_22_23 0x1034 5517#define regCM2_CM_GAMCOR_RAMA_REGION_22_23_BASE_IDX 2 5518#define regCM2_CM_GAMCOR_RAMA_REGION_24_25 0x1035 5519#define regCM2_CM_GAMCOR_RAMA_REGION_24_25_BASE_IDX 2 5520#define regCM2_CM_GAMCOR_RAMA_REGION_26_27 0x1036 5521#define regCM2_CM_GAMCOR_RAMA_REGION_26_27_BASE_IDX 2 5522#define regCM2_CM_GAMCOR_RAMA_REGION_28_29 0x1037 5523#define regCM2_CM_GAMCOR_RAMA_REGION_28_29_BASE_IDX 2 5524#define regCM2_CM_GAMCOR_RAMA_REGION_30_31 0x1038 5525#define regCM2_CM_GAMCOR_RAMA_REGION_30_31_BASE_IDX 2 5526#define regCM2_CM_GAMCOR_RAMA_REGION_32_33 0x1039 5527#define regCM2_CM_GAMCOR_RAMA_REGION_32_33_BASE_IDX 2 5528#define regCM2_CM_GAMCOR_RAMB_START_CNTL_B 0x103a 5529#define regCM2_CM_GAMCOR_RAMB_START_CNTL_B_BASE_IDX 2 5530#define regCM2_CM_GAMCOR_RAMB_START_CNTL_G 0x103b 5531#define regCM2_CM_GAMCOR_RAMB_START_CNTL_G_BASE_IDX 2 5532#define regCM2_CM_GAMCOR_RAMB_START_CNTL_R 0x103c 5533#define regCM2_CM_GAMCOR_RAMB_START_CNTL_R_BASE_IDX 2 5534#define regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B 0x103d 5535#define regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B_BASE_IDX 2 5536#define regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G 0x103e 5537#define regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G_BASE_IDX 2 5538#define regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R 0x103f 5539#define regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R_BASE_IDX 2 5540#define regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_B 0x1040 5541#define regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_B_BASE_IDX 2 5542#define regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_G 0x1041 5543#define regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_G_BASE_IDX 2 5544#define regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_R 0x1042 5545#define regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_R_BASE_IDX 2 5546#define regCM2_CM_GAMCOR_RAMB_END_CNTL1_B 0x1043 5547#define regCM2_CM_GAMCOR_RAMB_END_CNTL1_B_BASE_IDX 2 5548#define regCM2_CM_GAMCOR_RAMB_END_CNTL2_B 0x1044 5549#define regCM2_CM_GAMCOR_RAMB_END_CNTL2_B_BASE_IDX 2 5550#define regCM2_CM_GAMCOR_RAMB_END_CNTL1_G 0x1045 5551#define regCM2_CM_GAMCOR_RAMB_END_CNTL1_G_BASE_IDX 2 5552#define regCM2_CM_GAMCOR_RAMB_END_CNTL2_G 0x1046 5553#define regCM2_CM_GAMCOR_RAMB_END_CNTL2_G_BASE_IDX 2 5554#define regCM2_CM_GAMCOR_RAMB_END_CNTL1_R 0x1047 5555#define regCM2_CM_GAMCOR_RAMB_END_CNTL1_R_BASE_IDX 2 5556#define regCM2_CM_GAMCOR_RAMB_END_CNTL2_R 0x1048 5557#define regCM2_CM_GAMCOR_RAMB_END_CNTL2_R_BASE_IDX 2 5558#define regCM2_CM_GAMCOR_RAMB_OFFSET_B 0x1049 5559#define regCM2_CM_GAMCOR_RAMB_OFFSET_B_BASE_IDX 2 5560#define regCM2_CM_GAMCOR_RAMB_OFFSET_G 0x104a 5561#define regCM2_CM_GAMCOR_RAMB_OFFSET_G_BASE_IDX 2 5562#define regCM2_CM_GAMCOR_RAMB_OFFSET_R 0x104b 5563#define regCM2_CM_GAMCOR_RAMB_OFFSET_R_BASE_IDX 2 5564#define regCM2_CM_GAMCOR_RAMB_REGION_0_1 0x104c 5565#define regCM2_CM_GAMCOR_RAMB_REGION_0_1_BASE_IDX 2 5566#define regCM2_CM_GAMCOR_RAMB_REGION_2_3 0x104d 5567#define regCM2_CM_GAMCOR_RAMB_REGION_2_3_BASE_IDX 2 5568#define regCM2_CM_GAMCOR_RAMB_REGION_4_5 0x104e 5569#define regCM2_CM_GAMCOR_RAMB_REGION_4_5_BASE_IDX 2 5570#define regCM2_CM_GAMCOR_RAMB_REGION_6_7 0x104f 5571#define regCM2_CM_GAMCOR_RAMB_REGION_6_7_BASE_IDX 2 5572#define regCM2_CM_GAMCOR_RAMB_REGION_8_9 0x1050 5573#define regCM2_CM_GAMCOR_RAMB_REGION_8_9_BASE_IDX 2 5574#define regCM2_CM_GAMCOR_RAMB_REGION_10_11 0x1051 5575#define regCM2_CM_GAMCOR_RAMB_REGION_10_11_BASE_IDX 2 5576#define regCM2_CM_GAMCOR_RAMB_REGION_12_13 0x1052 5577#define regCM2_CM_GAMCOR_RAMB_REGION_12_13_BASE_IDX 2 5578#define regCM2_CM_GAMCOR_RAMB_REGION_14_15 0x1053 5579#define regCM2_CM_GAMCOR_RAMB_REGION_14_15_BASE_IDX 2 5580#define regCM2_CM_GAMCOR_RAMB_REGION_16_17 0x1054 5581#define regCM2_CM_GAMCOR_RAMB_REGION_16_17_BASE_IDX 2 5582#define regCM2_CM_GAMCOR_RAMB_REGION_18_19 0x1055 5583#define regCM2_CM_GAMCOR_RAMB_REGION_18_19_BASE_IDX 2 5584#define regCM2_CM_GAMCOR_RAMB_REGION_20_21 0x1056 5585#define regCM2_CM_GAMCOR_RAMB_REGION_20_21_BASE_IDX 2 5586#define regCM2_CM_GAMCOR_RAMB_REGION_22_23 0x1057 5587#define regCM2_CM_GAMCOR_RAMB_REGION_22_23_BASE_IDX 2 5588#define regCM2_CM_GAMCOR_RAMB_REGION_24_25 0x1058 5589#define regCM2_CM_GAMCOR_RAMB_REGION_24_25_BASE_IDX 2 5590#define regCM2_CM_GAMCOR_RAMB_REGION_26_27 0x1059 5591#define regCM2_CM_GAMCOR_RAMB_REGION_26_27_BASE_IDX 2 5592#define regCM2_CM_GAMCOR_RAMB_REGION_28_29 0x105a 5593#define regCM2_CM_GAMCOR_RAMB_REGION_28_29_BASE_IDX 2 5594#define regCM2_CM_GAMCOR_RAMB_REGION_30_31 0x105b 5595#define regCM2_CM_GAMCOR_RAMB_REGION_30_31_BASE_IDX 2 5596#define regCM2_CM_GAMCOR_RAMB_REGION_32_33 0x105c 5597#define regCM2_CM_GAMCOR_RAMB_REGION_32_33_BASE_IDX 2 5598#define regCM2_CM_HDR_MULT_COEF 0x105d 5599#define regCM2_CM_HDR_MULT_COEF_BASE_IDX 2 5600#define regCM2_CM_MEM_PWR_CTRL 0x105e 5601#define regCM2_CM_MEM_PWR_CTRL_BASE_IDX 2 5602#define regCM2_CM_MEM_PWR_STATUS 0x105f 5603#define regCM2_CM_MEM_PWR_STATUS_BASE_IDX 2 5604#define regCM2_CM_DEALPHA 0x1061 5605#define regCM2_CM_DEALPHA_BASE_IDX 2 5606#define regCM2_CM_COEF_FORMAT 0x1062 5607#define regCM2_CM_COEF_FORMAT_BASE_IDX 2 5608#define regCM2_CM_TEST_DEBUG_INDEX 0x1063 5609#define regCM2_CM_TEST_DEBUG_INDEX_BASE_IDX 2 5610#define regCM2_CM_TEST_DEBUG_DATA 0x1064 5611#define regCM2_CM_TEST_DEBUG_DATA_BASE_IDX 2 5612 5613 5614// addressBlock: dce_dc_dpp2_dispdec_dpp_dcperfmon_dc_perfmon_dispdec 5615// base address: 0x43e8 5616#define regDC_PERFMON13_PERFCOUNTER_CNTL 0x10fa 5617#define regDC_PERFMON13_PERFCOUNTER_CNTL_BASE_IDX 2 5618#define regDC_PERFMON13_PERFCOUNTER_CNTL2 0x10fb 5619#define regDC_PERFMON13_PERFCOUNTER_CNTL2_BASE_IDX 2 5620#define regDC_PERFMON13_PERFCOUNTER_STATE 0x10fc 5621#define regDC_PERFMON13_PERFCOUNTER_STATE_BASE_IDX 2 5622#define regDC_PERFMON13_PERFMON_CNTL 0x10fd 5623#define regDC_PERFMON13_PERFMON_CNTL_BASE_IDX 2 5624#define regDC_PERFMON13_PERFMON_CNTL2 0x10fe 5625#define regDC_PERFMON13_PERFMON_CNTL2_BASE_IDX 2 5626#define regDC_PERFMON13_PERFMON_CVALUE_INT_MISC 0x10ff 5627#define regDC_PERFMON13_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 5628#define regDC_PERFMON13_PERFMON_CVALUE_LOW 0x1100 5629#define regDC_PERFMON13_PERFMON_CVALUE_LOW_BASE_IDX 2 5630#define regDC_PERFMON13_PERFMON_HI 0x1101 5631#define regDC_PERFMON13_PERFMON_HI_BASE_IDX 2 5632#define regDC_PERFMON13_PERFMON_LOW 0x1102 5633#define regDC_PERFMON13_PERFMON_LOW_BASE_IDX 2 5634 5635 5636// addressBlock: dce_dc_dpp3_dispdec_dpp_top_dispdec 5637// base address: 0x1104 5638#define regDPP_TOP3_DPP_CONTROL 0x1106 5639#define regDPP_TOP3_DPP_CONTROL_BASE_IDX 2 5640#define regDPP_TOP3_DPP_SOFT_RESET 0x1107 5641#define regDPP_TOP3_DPP_SOFT_RESET_BASE_IDX 2 5642#define regDPP_TOP3_DPP_CRC_VAL_R_G 0x1108 5643#define regDPP_TOP3_DPP_CRC_VAL_R_G_BASE_IDX 2 5644#define regDPP_TOP3_DPP_CRC_VAL_B_A 0x1109 5645#define regDPP_TOP3_DPP_CRC_VAL_B_A_BASE_IDX 2 5646#define regDPP_TOP3_DPP_CRC_CTRL 0x110a 5647#define regDPP_TOP3_DPP_CRC_CTRL_BASE_IDX 2 5648#define regDPP_TOP3_HOST_READ_CONTROL 0x110b 5649#define regDPP_TOP3_HOST_READ_CONTROL_BASE_IDX 2 5650 5651 5652// addressBlock: dce_dc_dpp3_dispdec_cnvc_cfg_dispdec 5653// base address: 0x1104 5654#define regCNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT 0x1110 5655#define regCNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX 2 5656#define regCNVC_CFG3_FORMAT_CONTROL 0x1111 5657#define regCNVC_CFG3_FORMAT_CONTROL_BASE_IDX 2 5658#define regCNVC_CFG3_FCNV_FP_BIAS_R 0x1112 5659#define regCNVC_CFG3_FCNV_FP_BIAS_R_BASE_IDX 2 5660#define regCNVC_CFG3_FCNV_FP_BIAS_G 0x1113 5661#define regCNVC_CFG3_FCNV_FP_BIAS_G_BASE_IDX 2 5662#define regCNVC_CFG3_FCNV_FP_BIAS_B 0x1114 5663#define regCNVC_CFG3_FCNV_FP_BIAS_B_BASE_IDX 2 5664#define regCNVC_CFG3_FCNV_FP_SCALE_R 0x1115 5665#define regCNVC_CFG3_FCNV_FP_SCALE_R_BASE_IDX 2 5666#define regCNVC_CFG3_FCNV_FP_SCALE_G 0x1116 5667#define regCNVC_CFG3_FCNV_FP_SCALE_G_BASE_IDX 2 5668#define regCNVC_CFG3_FCNV_FP_SCALE_B 0x1117 5669#define regCNVC_CFG3_FCNV_FP_SCALE_B_BASE_IDX 2 5670#define regCNVC_CFG3_COLOR_KEYER_CONTROL 0x1118 5671#define regCNVC_CFG3_COLOR_KEYER_CONTROL_BASE_IDX 2 5672#define regCNVC_CFG3_COLOR_KEYER_ALPHA 0x1119 5673#define regCNVC_CFG3_COLOR_KEYER_ALPHA_BASE_IDX 2 5674#define regCNVC_CFG3_COLOR_KEYER_RED 0x111a 5675#define regCNVC_CFG3_COLOR_KEYER_RED_BASE_IDX 2 5676#define regCNVC_CFG3_COLOR_KEYER_GREEN 0x111b 5677#define regCNVC_CFG3_COLOR_KEYER_GREEN_BASE_IDX 2 5678#define regCNVC_CFG3_COLOR_KEYER_BLUE 0x111c 5679#define regCNVC_CFG3_COLOR_KEYER_BLUE_BASE_IDX 2 5680#define regCNVC_CFG3_ALPHA_2BIT_LUT 0x111e 5681#define regCNVC_CFG3_ALPHA_2BIT_LUT_BASE_IDX 2 5682#define regCNVC_CFG3_PRE_DEALPHA 0x111f 5683#define regCNVC_CFG3_PRE_DEALPHA_BASE_IDX 2 5684#define regCNVC_CFG3_PRE_CSC_MODE 0x1120 5685#define regCNVC_CFG3_PRE_CSC_MODE_BASE_IDX 2 5686#define regCNVC_CFG3_PRE_CSC_C11_C12 0x1121 5687#define regCNVC_CFG3_PRE_CSC_C11_C12_BASE_IDX 2 5688#define regCNVC_CFG3_PRE_CSC_C13_C14 0x1122 5689#define regCNVC_CFG3_PRE_CSC_C13_C14_BASE_IDX 2 5690#define regCNVC_CFG3_PRE_CSC_C21_C22 0x1123 5691#define regCNVC_CFG3_PRE_CSC_C21_C22_BASE_IDX 2 5692#define regCNVC_CFG3_PRE_CSC_C23_C24 0x1124 5693#define regCNVC_CFG3_PRE_CSC_C23_C24_BASE_IDX 2 5694#define regCNVC_CFG3_PRE_CSC_C31_C32 0x1125 5695#define regCNVC_CFG3_PRE_CSC_C31_C32_BASE_IDX 2 5696#define regCNVC_CFG3_PRE_CSC_C33_C34 0x1126 5697#define regCNVC_CFG3_PRE_CSC_C33_C34_BASE_IDX 2 5698#define regCNVC_CFG3_PRE_CSC_B_C11_C12 0x1127 5699#define regCNVC_CFG3_PRE_CSC_B_C11_C12_BASE_IDX 2 5700#define regCNVC_CFG3_PRE_CSC_B_C13_C14 0x1128 5701#define regCNVC_CFG3_PRE_CSC_B_C13_C14_BASE_IDX 2 5702#define regCNVC_CFG3_PRE_CSC_B_C21_C22 0x1129 5703#define regCNVC_CFG3_PRE_CSC_B_C21_C22_BASE_IDX 2 5704#define regCNVC_CFG3_PRE_CSC_B_C23_C24 0x112a 5705#define regCNVC_CFG3_PRE_CSC_B_C23_C24_BASE_IDX 2 5706#define regCNVC_CFG3_PRE_CSC_B_C31_C32 0x112b 5707#define regCNVC_CFG3_PRE_CSC_B_C31_C32_BASE_IDX 2 5708#define regCNVC_CFG3_PRE_CSC_B_C33_C34 0x112c 5709#define regCNVC_CFG3_PRE_CSC_B_C33_C34_BASE_IDX 2 5710#define regCNVC_CFG3_CNVC_COEF_FORMAT 0x112d 5711#define regCNVC_CFG3_CNVC_COEF_FORMAT_BASE_IDX 2 5712#define regCNVC_CFG3_PRE_DEGAM 0x112e 5713#define regCNVC_CFG3_PRE_DEGAM_BASE_IDX 2 5714#define regCNVC_CFG3_PRE_REALPHA 0x112f 5715#define regCNVC_CFG3_PRE_REALPHA_BASE_IDX 2 5716 5717 5718// addressBlock: dce_dc_dpp3_dispdec_cnvc_cur_dispdec 5719// base address: 0x1104 5720#define regCNVC_CUR3_CURSOR0_CONTROL 0x1132 5721#define regCNVC_CUR3_CURSOR0_CONTROL_BASE_IDX 2 5722#define regCNVC_CUR3_CURSOR0_COLOR0 0x1133 5723#define regCNVC_CUR3_CURSOR0_COLOR0_BASE_IDX 2 5724#define regCNVC_CUR3_CURSOR0_COLOR1 0x1134 5725#define regCNVC_CUR3_CURSOR0_COLOR1_BASE_IDX 2 5726#define regCNVC_CUR3_CURSOR0_FP_SCALE_BIAS 0x1135 5727#define regCNVC_CUR3_CURSOR0_FP_SCALE_BIAS_BASE_IDX 2 5728 5729 5730// addressBlock: dce_dc_dpp3_dispdec_dscl_dispdec 5731// base address: 0x1104 5732#define regDSCL3_SCL_COEF_RAM_TAP_SELECT 0x113a 5733#define regDSCL3_SCL_COEF_RAM_TAP_SELECT_BASE_IDX 2 5734#define regDSCL3_SCL_COEF_RAM_TAP_DATA 0x113b 5735#define regDSCL3_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2 5736#define regDSCL3_SCL_MODE 0x113c 5737#define regDSCL3_SCL_MODE_BASE_IDX 2 5738#define regDSCL3_SCL_TAP_CONTROL 0x113d 5739#define regDSCL3_SCL_TAP_CONTROL_BASE_IDX 2 5740#define regDSCL3_DSCL_CONTROL 0x113e 5741#define regDSCL3_DSCL_CONTROL_BASE_IDX 2 5742#define regDSCL3_DSCL_2TAP_CONTROL 0x113f 5743#define regDSCL3_DSCL_2TAP_CONTROL_BASE_IDX 2 5744#define regDSCL3_SCL_MANUAL_REPLICATE_CONTROL 0x1140 5745#define regDSCL3_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2 5746#define regDSCL3_SCL_HORZ_FILTER_SCALE_RATIO 0x1141 5747#define regDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2 5748#define regDSCL3_SCL_HORZ_FILTER_INIT 0x1142 5749#define regDSCL3_SCL_HORZ_FILTER_INIT_BASE_IDX 2 5750#define regDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C 0x1143 5751#define regDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX 2 5752#define regDSCL3_SCL_HORZ_FILTER_INIT_C 0x1144 5753#define regDSCL3_SCL_HORZ_FILTER_INIT_C_BASE_IDX 2 5754#define regDSCL3_SCL_VERT_FILTER_SCALE_RATIO 0x1145 5755#define regDSCL3_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2 5756#define regDSCL3_SCL_VERT_FILTER_INIT 0x1146 5757#define regDSCL3_SCL_VERT_FILTER_INIT_BASE_IDX 2 5758#define regDSCL3_SCL_VERT_FILTER_INIT_BOT 0x1147 5759#define regDSCL3_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2 5760#define regDSCL3_SCL_VERT_FILTER_SCALE_RATIO_C 0x1148 5761#define regDSCL3_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX 2 5762#define regDSCL3_SCL_VERT_FILTER_INIT_C 0x1149 5763#define regDSCL3_SCL_VERT_FILTER_INIT_C_BASE_IDX 2 5764#define regDSCL3_SCL_VERT_FILTER_INIT_BOT_C 0x114a 5765#define regDSCL3_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX 2 5766#define regDSCL3_SCL_BLACK_COLOR 0x114b 5767#define regDSCL3_SCL_BLACK_COLOR_BASE_IDX 2 5768#define regDSCL3_DSCL_UPDATE 0x114c 5769#define regDSCL3_DSCL_UPDATE_BASE_IDX 2 5770#define regDSCL3_DSCL_AUTOCAL 0x114d 5771#define regDSCL3_DSCL_AUTOCAL_BASE_IDX 2 5772#define regDSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT 0x114e 5773#define regDSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2 5774#define regDSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM 0x114f 5775#define regDSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2 5776#define regDSCL3_OTG_H_BLANK 0x1150 5777#define regDSCL3_OTG_H_BLANK_BASE_IDX 2 5778#define regDSCL3_OTG_V_BLANK 0x1151 5779#define regDSCL3_OTG_V_BLANK_BASE_IDX 2 5780#define regDSCL3_RECOUT_START 0x1152 5781#define regDSCL3_RECOUT_START_BASE_IDX 2 5782#define regDSCL3_RECOUT_SIZE 0x1153 5783#define regDSCL3_RECOUT_SIZE_BASE_IDX 2 5784#define regDSCL3_MPC_SIZE 0x1154 5785#define regDSCL3_MPC_SIZE_BASE_IDX 2 5786#define regDSCL3_LB_DATA_FORMAT 0x1155 5787#define regDSCL3_LB_DATA_FORMAT_BASE_IDX 2 5788#define regDSCL3_LB_MEMORY_CTRL 0x1156 5789#define regDSCL3_LB_MEMORY_CTRL_BASE_IDX 2 5790#define regDSCL3_LB_V_COUNTER 0x1157 5791#define regDSCL3_LB_V_COUNTER_BASE_IDX 2 5792#define regDSCL3_DSCL_MEM_PWR_CTRL 0x1158 5793#define regDSCL3_DSCL_MEM_PWR_CTRL_BASE_IDX 2 5794#define regDSCL3_DSCL_MEM_PWR_STATUS 0x1159 5795#define regDSCL3_DSCL_MEM_PWR_STATUS_BASE_IDX 2 5796#define regDSCL3_OBUF_CONTROL 0x115a 5797#define regDSCL3_OBUF_CONTROL_BASE_IDX 2 5798#define regDSCL3_OBUF_MEM_PWR_CTRL 0x115b 5799#define regDSCL3_OBUF_MEM_PWR_CTRL_BASE_IDX 2 5800 5801 5802// addressBlock: dce_dc_dpp3_dispdec_cm_dispdec 5803// base address: 0x1104 5804#define regCM3_CM_CONTROL 0x1161 5805#define regCM3_CM_CONTROL_BASE_IDX 2 5806#define regCM3_CM_POST_CSC_CONTROL 0x1162 5807#define regCM3_CM_POST_CSC_CONTROL_BASE_IDX 2 5808#define regCM3_CM_POST_CSC_C11_C12 0x1163 5809#define regCM3_CM_POST_CSC_C11_C12_BASE_IDX 2 5810#define regCM3_CM_POST_CSC_C13_C14 0x1164 5811#define regCM3_CM_POST_CSC_C13_C14_BASE_IDX 2 5812#define regCM3_CM_POST_CSC_C21_C22 0x1165 5813#define regCM3_CM_POST_CSC_C21_C22_BASE_IDX 2 5814#define regCM3_CM_POST_CSC_C23_C24 0x1166 5815#define regCM3_CM_POST_CSC_C23_C24_BASE_IDX 2 5816#define regCM3_CM_POST_CSC_C31_C32 0x1167 5817#define regCM3_CM_POST_CSC_C31_C32_BASE_IDX 2 5818#define regCM3_CM_POST_CSC_C33_C34 0x1168 5819#define regCM3_CM_POST_CSC_C33_C34_BASE_IDX 2 5820#define regCM3_CM_POST_CSC_B_C11_C12 0x1169 5821#define regCM3_CM_POST_CSC_B_C11_C12_BASE_IDX 2 5822#define regCM3_CM_POST_CSC_B_C13_C14 0x116a 5823#define regCM3_CM_POST_CSC_B_C13_C14_BASE_IDX 2 5824#define regCM3_CM_POST_CSC_B_C21_C22 0x116b 5825#define regCM3_CM_POST_CSC_B_C21_C22_BASE_IDX 2 5826#define regCM3_CM_POST_CSC_B_C23_C24 0x116c 5827#define regCM3_CM_POST_CSC_B_C23_C24_BASE_IDX 2 5828#define regCM3_CM_POST_CSC_B_C31_C32 0x116d 5829#define regCM3_CM_POST_CSC_B_C31_C32_BASE_IDX 2 5830#define regCM3_CM_POST_CSC_B_C33_C34 0x116e 5831#define regCM3_CM_POST_CSC_B_C33_C34_BASE_IDX 2 5832#define regCM3_CM_GAMUT_REMAP_CONTROL 0x116f 5833#define regCM3_CM_GAMUT_REMAP_CONTROL_BASE_IDX 2 5834#define regCM3_CM_GAMUT_REMAP_C11_C12 0x1170 5835#define regCM3_CM_GAMUT_REMAP_C11_C12_BASE_IDX 2 5836#define regCM3_CM_GAMUT_REMAP_C13_C14 0x1171 5837#define regCM3_CM_GAMUT_REMAP_C13_C14_BASE_IDX 2 5838#define regCM3_CM_GAMUT_REMAP_C21_C22 0x1172 5839#define regCM3_CM_GAMUT_REMAP_C21_C22_BASE_IDX 2 5840#define regCM3_CM_GAMUT_REMAP_C23_C24 0x1173 5841#define regCM3_CM_GAMUT_REMAP_C23_C24_BASE_IDX 2 5842#define regCM3_CM_GAMUT_REMAP_C31_C32 0x1174 5843#define regCM3_CM_GAMUT_REMAP_C31_C32_BASE_IDX 2 5844#define regCM3_CM_GAMUT_REMAP_C33_C34 0x1175 5845#define regCM3_CM_GAMUT_REMAP_C33_C34_BASE_IDX 2 5846#define regCM3_CM_GAMUT_REMAP_B_C11_C12 0x1176 5847#define regCM3_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX 2 5848#define regCM3_CM_GAMUT_REMAP_B_C13_C14 0x1177 5849#define regCM3_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX 2 5850#define regCM3_CM_GAMUT_REMAP_B_C21_C22 0x1178 5851#define regCM3_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX 2 5852#define regCM3_CM_GAMUT_REMAP_B_C23_C24 0x1179 5853#define regCM3_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX 2 5854#define regCM3_CM_GAMUT_REMAP_B_C31_C32 0x117a 5855#define regCM3_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX 2 5856#define regCM3_CM_GAMUT_REMAP_B_C33_C34 0x117b 5857#define regCM3_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX 2 5858#define regCM3_CM_BIAS_CR_R 0x117c 5859#define regCM3_CM_BIAS_CR_R_BASE_IDX 2 5860#define regCM3_CM_BIAS_Y_G_CB_B 0x117d 5861#define regCM3_CM_BIAS_Y_G_CB_B_BASE_IDX 2 5862#define regCM3_CM_GAMCOR_CONTROL 0x117e 5863#define regCM3_CM_GAMCOR_CONTROL_BASE_IDX 2 5864#define regCM3_CM_GAMCOR_LUT_INDEX 0x117f 5865#define regCM3_CM_GAMCOR_LUT_INDEX_BASE_IDX 2 5866#define regCM3_CM_GAMCOR_LUT_DATA 0x1180 5867#define regCM3_CM_GAMCOR_LUT_DATA_BASE_IDX 2 5868#define regCM3_CM_GAMCOR_LUT_CONTROL 0x1181 5869#define regCM3_CM_GAMCOR_LUT_CONTROL_BASE_IDX 2 5870#define regCM3_CM_GAMCOR_RAMA_START_CNTL_B 0x1182 5871#define regCM3_CM_GAMCOR_RAMA_START_CNTL_B_BASE_IDX 2 5872#define regCM3_CM_GAMCOR_RAMA_START_CNTL_G 0x1183 5873#define regCM3_CM_GAMCOR_RAMA_START_CNTL_G_BASE_IDX 2 5874#define regCM3_CM_GAMCOR_RAMA_START_CNTL_R 0x1184 5875#define regCM3_CM_GAMCOR_RAMA_START_CNTL_R_BASE_IDX 2 5876#define regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B 0x1185 5877#define regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B_BASE_IDX 2 5878#define regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G 0x1186 5879#define regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2 5880#define regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R 0x1187 5881#define regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R_BASE_IDX 2 5882#define regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_B 0x1188 5883#define regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_B_BASE_IDX 2 5884#define regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_G 0x1189 5885#define regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_G_BASE_IDX 2 5886#define regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_R 0x118a 5887#define regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_R_BASE_IDX 2 5888#define regCM3_CM_GAMCOR_RAMA_END_CNTL1_B 0x118b 5889#define regCM3_CM_GAMCOR_RAMA_END_CNTL1_B_BASE_IDX 2 5890#define regCM3_CM_GAMCOR_RAMA_END_CNTL2_B 0x118c 5891#define regCM3_CM_GAMCOR_RAMA_END_CNTL2_B_BASE_IDX 2 5892#define regCM3_CM_GAMCOR_RAMA_END_CNTL1_G 0x118d 5893#define regCM3_CM_GAMCOR_RAMA_END_CNTL1_G_BASE_IDX 2 5894#define regCM3_CM_GAMCOR_RAMA_END_CNTL2_G 0x118e 5895#define regCM3_CM_GAMCOR_RAMA_END_CNTL2_G_BASE_IDX 2 5896#define regCM3_CM_GAMCOR_RAMA_END_CNTL1_R 0x118f 5897#define regCM3_CM_GAMCOR_RAMA_END_CNTL1_R_BASE_IDX 2 5898#define regCM3_CM_GAMCOR_RAMA_END_CNTL2_R 0x1190 5899#define regCM3_CM_GAMCOR_RAMA_END_CNTL2_R_BASE_IDX 2 5900#define regCM3_CM_GAMCOR_RAMA_OFFSET_B 0x1191 5901#define regCM3_CM_GAMCOR_RAMA_OFFSET_B_BASE_IDX 2 5902#define regCM3_CM_GAMCOR_RAMA_OFFSET_G 0x1192 5903#define regCM3_CM_GAMCOR_RAMA_OFFSET_G_BASE_IDX 2 5904#define regCM3_CM_GAMCOR_RAMA_OFFSET_R 0x1193 5905#define regCM3_CM_GAMCOR_RAMA_OFFSET_R_BASE_IDX 2 5906#define regCM3_CM_GAMCOR_RAMA_REGION_0_1 0x1194 5907#define regCM3_CM_GAMCOR_RAMA_REGION_0_1_BASE_IDX 2 5908#define regCM3_CM_GAMCOR_RAMA_REGION_2_3 0x1195 5909#define regCM3_CM_GAMCOR_RAMA_REGION_2_3_BASE_IDX 2 5910#define regCM3_CM_GAMCOR_RAMA_REGION_4_5 0x1196 5911#define regCM3_CM_GAMCOR_RAMA_REGION_4_5_BASE_IDX 2 5912#define regCM3_CM_GAMCOR_RAMA_REGION_6_7 0x1197 5913#define regCM3_CM_GAMCOR_RAMA_REGION_6_7_BASE_IDX 2 5914#define regCM3_CM_GAMCOR_RAMA_REGION_8_9 0x1198 5915#define regCM3_CM_GAMCOR_RAMA_REGION_8_9_BASE_IDX 2 5916#define regCM3_CM_GAMCOR_RAMA_REGION_10_11 0x1199 5917#define regCM3_CM_GAMCOR_RAMA_REGION_10_11_BASE_IDX 2 5918#define regCM3_CM_GAMCOR_RAMA_REGION_12_13 0x119a 5919#define regCM3_CM_GAMCOR_RAMA_REGION_12_13_BASE_IDX 2 5920#define regCM3_CM_GAMCOR_RAMA_REGION_14_15 0x119b 5921#define regCM3_CM_GAMCOR_RAMA_REGION_14_15_BASE_IDX 2 5922#define regCM3_CM_GAMCOR_RAMA_REGION_16_17 0x119c 5923#define regCM3_CM_GAMCOR_RAMA_REGION_16_17_BASE_IDX 2 5924#define regCM3_CM_GAMCOR_RAMA_REGION_18_19 0x119d 5925#define regCM3_CM_GAMCOR_RAMA_REGION_18_19_BASE_IDX 2 5926#define regCM3_CM_GAMCOR_RAMA_REGION_20_21 0x119e 5927#define regCM3_CM_GAMCOR_RAMA_REGION_20_21_BASE_IDX 2 5928#define regCM3_CM_GAMCOR_RAMA_REGION_22_23 0x119f 5929#define regCM3_CM_GAMCOR_RAMA_REGION_22_23_BASE_IDX 2 5930#define regCM3_CM_GAMCOR_RAMA_REGION_24_25 0x11a0 5931#define regCM3_CM_GAMCOR_RAMA_REGION_24_25_BASE_IDX 2 5932#define regCM3_CM_GAMCOR_RAMA_REGION_26_27 0x11a1 5933#define regCM3_CM_GAMCOR_RAMA_REGION_26_27_BASE_IDX 2 5934#define regCM3_CM_GAMCOR_RAMA_REGION_28_29 0x11a2 5935#define regCM3_CM_GAMCOR_RAMA_REGION_28_29_BASE_IDX 2 5936#define regCM3_CM_GAMCOR_RAMA_REGION_30_31 0x11a3 5937#define regCM3_CM_GAMCOR_RAMA_REGION_30_31_BASE_IDX 2 5938#define regCM3_CM_GAMCOR_RAMA_REGION_32_33 0x11a4 5939#define regCM3_CM_GAMCOR_RAMA_REGION_32_33_BASE_IDX 2 5940#define regCM3_CM_GAMCOR_RAMB_START_CNTL_B 0x11a5 5941#define regCM3_CM_GAMCOR_RAMB_START_CNTL_B_BASE_IDX 2 5942#define regCM3_CM_GAMCOR_RAMB_START_CNTL_G 0x11a6 5943#define regCM3_CM_GAMCOR_RAMB_START_CNTL_G_BASE_IDX 2 5944#define regCM3_CM_GAMCOR_RAMB_START_CNTL_R 0x11a7 5945#define regCM3_CM_GAMCOR_RAMB_START_CNTL_R_BASE_IDX 2 5946#define regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B 0x11a8 5947#define regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B_BASE_IDX 2 5948#define regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G 0x11a9 5949#define regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G_BASE_IDX 2 5950#define regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R 0x11aa 5951#define regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R_BASE_IDX 2 5952#define regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_B 0x11ab 5953#define regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_B_BASE_IDX 2 5954#define regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_G 0x11ac 5955#define regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_G_BASE_IDX 2 5956#define regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_R 0x11ad 5957#define regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_R_BASE_IDX 2 5958#define regCM3_CM_GAMCOR_RAMB_END_CNTL1_B 0x11ae 5959#define regCM3_CM_GAMCOR_RAMB_END_CNTL1_B_BASE_IDX 2 5960#define regCM3_CM_GAMCOR_RAMB_END_CNTL2_B 0x11af 5961#define regCM3_CM_GAMCOR_RAMB_END_CNTL2_B_BASE_IDX 2 5962#define regCM3_CM_GAMCOR_RAMB_END_CNTL1_G 0x11b0 5963#define regCM3_CM_GAMCOR_RAMB_END_CNTL1_G_BASE_IDX 2 5964#define regCM3_CM_GAMCOR_RAMB_END_CNTL2_G 0x11b1 5965#define regCM3_CM_GAMCOR_RAMB_END_CNTL2_G_BASE_IDX 2 5966#define regCM3_CM_GAMCOR_RAMB_END_CNTL1_R 0x11b2 5967#define regCM3_CM_GAMCOR_RAMB_END_CNTL1_R_BASE_IDX 2 5968#define regCM3_CM_GAMCOR_RAMB_END_CNTL2_R 0x11b3 5969#define regCM3_CM_GAMCOR_RAMB_END_CNTL2_R_BASE_IDX 2 5970#define regCM3_CM_GAMCOR_RAMB_OFFSET_B 0x11b4 5971#define regCM3_CM_GAMCOR_RAMB_OFFSET_B_BASE_IDX 2 5972#define regCM3_CM_GAMCOR_RAMB_OFFSET_G 0x11b5 5973#define regCM3_CM_GAMCOR_RAMB_OFFSET_G_BASE_IDX 2 5974#define regCM3_CM_GAMCOR_RAMB_OFFSET_R 0x11b6 5975#define regCM3_CM_GAMCOR_RAMB_OFFSET_R_BASE_IDX 2 5976#define regCM3_CM_GAMCOR_RAMB_REGION_0_1 0x11b7 5977#define regCM3_CM_GAMCOR_RAMB_REGION_0_1_BASE_IDX 2 5978#define regCM3_CM_GAMCOR_RAMB_REGION_2_3 0x11b8 5979#define regCM3_CM_GAMCOR_RAMB_REGION_2_3_BASE_IDX 2 5980#define regCM3_CM_GAMCOR_RAMB_REGION_4_5 0x11b9 5981#define regCM3_CM_GAMCOR_RAMB_REGION_4_5_BASE_IDX 2 5982#define regCM3_CM_GAMCOR_RAMB_REGION_6_7 0x11ba 5983#define regCM3_CM_GAMCOR_RAMB_REGION_6_7_BASE_IDX 2 5984#define regCM3_CM_GAMCOR_RAMB_REGION_8_9 0x11bb 5985#define regCM3_CM_GAMCOR_RAMB_REGION_8_9_BASE_IDX 2 5986#define regCM3_CM_GAMCOR_RAMB_REGION_10_11 0x11bc 5987#define regCM3_CM_GAMCOR_RAMB_REGION_10_11_BASE_IDX 2 5988#define regCM3_CM_GAMCOR_RAMB_REGION_12_13 0x11bd 5989#define regCM3_CM_GAMCOR_RAMB_REGION_12_13_BASE_IDX 2 5990#define regCM3_CM_GAMCOR_RAMB_REGION_14_15 0x11be 5991#define regCM3_CM_GAMCOR_RAMB_REGION_14_15_BASE_IDX 2 5992#define regCM3_CM_GAMCOR_RAMB_REGION_16_17 0x11bf 5993#define regCM3_CM_GAMCOR_RAMB_REGION_16_17_BASE_IDX 2 5994#define regCM3_CM_GAMCOR_RAMB_REGION_18_19 0x11c0 5995#define regCM3_CM_GAMCOR_RAMB_REGION_18_19_BASE_IDX 2 5996#define regCM3_CM_GAMCOR_RAMB_REGION_20_21 0x11c1 5997#define regCM3_CM_GAMCOR_RAMB_REGION_20_21_BASE_IDX 2 5998#define regCM3_CM_GAMCOR_RAMB_REGION_22_23 0x11c2 5999#define regCM3_CM_GAMCOR_RAMB_REGION_22_23_BASE_IDX 2 6000#define regCM3_CM_GAMCOR_RAMB_REGION_24_25 0x11c3 6001#define regCM3_CM_GAMCOR_RAMB_REGION_24_25_BASE_IDX 2 6002#define regCM3_CM_GAMCOR_RAMB_REGION_26_27 0x11c4 6003#define regCM3_CM_GAMCOR_RAMB_REGION_26_27_BASE_IDX 2 6004#define regCM3_CM_GAMCOR_RAMB_REGION_28_29 0x11c5 6005#define regCM3_CM_GAMCOR_RAMB_REGION_28_29_BASE_IDX 2 6006#define regCM3_CM_GAMCOR_RAMB_REGION_30_31 0x11c6 6007#define regCM3_CM_GAMCOR_RAMB_REGION_30_31_BASE_IDX 2 6008#define regCM3_CM_GAMCOR_RAMB_REGION_32_33 0x11c7 6009#define regCM3_CM_GAMCOR_RAMB_REGION_32_33_BASE_IDX 2 6010#define regCM3_CM_HDR_MULT_COEF 0x11c8 6011#define regCM3_CM_HDR_MULT_COEF_BASE_IDX 2 6012#define regCM3_CM_MEM_PWR_CTRL 0x11c9 6013#define regCM3_CM_MEM_PWR_CTRL_BASE_IDX 2 6014#define regCM3_CM_MEM_PWR_STATUS 0x11ca 6015#define regCM3_CM_MEM_PWR_STATUS_BASE_IDX 2 6016#define regCM3_CM_DEALPHA 0x11cc 6017#define regCM3_CM_DEALPHA_BASE_IDX 2 6018#define regCM3_CM_COEF_FORMAT 0x11cd 6019#define regCM3_CM_COEF_FORMAT_BASE_IDX 2 6020#define regCM3_CM_TEST_DEBUG_INDEX 0x11ce 6021#define regCM3_CM_TEST_DEBUG_INDEX_BASE_IDX 2 6022#define regCM3_CM_TEST_DEBUG_DATA 0x11cf 6023#define regCM3_CM_TEST_DEBUG_DATA_BASE_IDX 2 6024 6025 6026// addressBlock: dce_dc_dpp3_dispdec_dpp_dcperfmon_dc_perfmon_dispdec 6027// base address: 0x4994 6028#define regDC_PERFMON14_PERFCOUNTER_CNTL 0x1265 6029#define regDC_PERFMON14_PERFCOUNTER_CNTL_BASE_IDX 2 6030#define regDC_PERFMON14_PERFCOUNTER_CNTL2 0x1266 6031#define regDC_PERFMON14_PERFCOUNTER_CNTL2_BASE_IDX 2 6032#define regDC_PERFMON14_PERFCOUNTER_STATE 0x1267 6033#define regDC_PERFMON14_PERFCOUNTER_STATE_BASE_IDX 2 6034#define regDC_PERFMON14_PERFMON_CNTL 0x1268 6035#define regDC_PERFMON14_PERFMON_CNTL_BASE_IDX 2 6036#define regDC_PERFMON14_PERFMON_CNTL2 0x1269 6037#define regDC_PERFMON14_PERFMON_CNTL2_BASE_IDX 2 6038#define regDC_PERFMON14_PERFMON_CVALUE_INT_MISC 0x126a 6039#define regDC_PERFMON14_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 6040#define regDC_PERFMON14_PERFMON_CVALUE_LOW 0x126b 6041#define regDC_PERFMON14_PERFMON_CVALUE_LOW_BASE_IDX 2 6042#define regDC_PERFMON14_PERFMON_HI 0x126c 6043#define regDC_PERFMON14_PERFMON_HI_BASE_IDX 2 6044#define regDC_PERFMON14_PERFMON_LOW 0x126d 6045#define regDC_PERFMON14_PERFMON_LOW_BASE_IDX 2 6046 6047 6048// addressBlock: dce_dc_opp_fmt0_dispdec 6049// base address: 0x0 6050#define regFMT0_FMT_CLAMP_COMPONENT_R 0x183c 6051#define regFMT0_FMT_CLAMP_COMPONENT_R_BASE_IDX 2 6052#define regFMT0_FMT_CLAMP_COMPONENT_G 0x183d 6053#define regFMT0_FMT_CLAMP_COMPONENT_G_BASE_IDX 2 6054#define regFMT0_FMT_CLAMP_COMPONENT_B 0x183e 6055#define regFMT0_FMT_CLAMP_COMPONENT_B_BASE_IDX 2 6056#define regFMT0_FMT_DYNAMIC_EXP_CNTL 0x183f 6057#define regFMT0_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2 6058#define regFMT0_FMT_CONTROL 0x1840 6059#define regFMT0_FMT_CONTROL_BASE_IDX 2 6060#define regFMT0_FMT_BIT_DEPTH_CONTROL 0x1841 6061#define regFMT0_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2 6062#define regFMT0_FMT_DITHER_RAND_R_SEED 0x1842 6063#define regFMT0_FMT_DITHER_RAND_R_SEED_BASE_IDX 2 6064#define regFMT0_FMT_DITHER_RAND_G_SEED 0x1843 6065#define regFMT0_FMT_DITHER_RAND_G_SEED_BASE_IDX 2 6066#define regFMT0_FMT_DITHER_RAND_B_SEED 0x1844 6067#define regFMT0_FMT_DITHER_RAND_B_SEED_BASE_IDX 2 6068#define regFMT0_FMT_CLAMP_CNTL 0x1845 6069#define regFMT0_FMT_CLAMP_CNTL_BASE_IDX 2 6070#define regFMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x1846 6071#define regFMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2 6072#define regFMT0_FMT_MAP420_MEMORY_CONTROL 0x1847 6073#define regFMT0_FMT_MAP420_MEMORY_CONTROL_BASE_IDX 2 6074#define regFMT0_FMT_422_CONTROL 0x1849 6075#define regFMT0_FMT_422_CONTROL_BASE_IDX 2 6076 6077 6078// addressBlock: dce_dc_opp_dpg0_dispdec 6079// base address: 0x0 6080#define regDPG0_DPG_CONTROL 0x1854 6081#define regDPG0_DPG_CONTROL_BASE_IDX 2 6082#define regDPG0_DPG_RAMP_CONTROL 0x1855 6083#define regDPG0_DPG_RAMP_CONTROL_BASE_IDX 2 6084#define regDPG0_DPG_DIMENSIONS 0x1856 6085#define regDPG0_DPG_DIMENSIONS_BASE_IDX 2 6086#define regDPG0_DPG_COLOUR_R_CR 0x1857 6087#define regDPG0_DPG_COLOUR_R_CR_BASE_IDX 2 6088#define regDPG0_DPG_COLOUR_G_Y 0x1858 6089#define regDPG0_DPG_COLOUR_G_Y_BASE_IDX 2 6090#define regDPG0_DPG_COLOUR_B_CB 0x1859 6091#define regDPG0_DPG_COLOUR_B_CB_BASE_IDX 2 6092#define regDPG0_DPG_OFFSET_SEGMENT 0x185a 6093#define regDPG0_DPG_OFFSET_SEGMENT_BASE_IDX 2 6094#define regDPG0_DPG_STATUS 0x185b 6095#define regDPG0_DPG_STATUS_BASE_IDX 2 6096 6097 6098// addressBlock: dce_dc_opp_oppbuf0_dispdec 6099// base address: 0x0 6100#define regOPPBUF0_OPPBUF_CONTROL 0x1884 6101#define regOPPBUF0_OPPBUF_CONTROL_BASE_IDX 2 6102#define regOPPBUF0_OPPBUF_3D_PARAMETERS_0 0x1885 6103#define regOPPBUF0_OPPBUF_3D_PARAMETERS_0_BASE_IDX 2 6104#define regOPPBUF0_OPPBUF_3D_PARAMETERS_1 0x1886 6105#define regOPPBUF0_OPPBUF_3D_PARAMETERS_1_BASE_IDX 2 6106#define regOPPBUF0_OPPBUF_CONTROL1 0x1889 6107#define regOPPBUF0_OPPBUF_CONTROL1_BASE_IDX 2 6108 6109 6110// addressBlock: dce_dc_opp_opp_pipe0_dispdec 6111// base address: 0x0 6112#define regOPP_PIPE0_OPP_PIPE_CONTROL 0x188c 6113#define regOPP_PIPE0_OPP_PIPE_CONTROL_BASE_IDX 2 6114 6115 6116// addressBlock: dce_dc_opp_opp_pipe_crc0_dispdec 6117// base address: 0x0 6118#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL 0x1891 6119#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL_BASE_IDX 2 6120#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_MASK 0x1892 6121#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_MASK_BASE_IDX 2 6122#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0 0x1893 6123#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0_BASE_IDX 2 6124#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1 0x1894 6125#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1_BASE_IDX 2 6126#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2 0x1895 6127#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2_BASE_IDX 2 6128 6129 6130// addressBlock: dce_dc_opp_fmt1_dispdec 6131// base address: 0x168 6132#define regFMT1_FMT_CLAMP_COMPONENT_R 0x1896 6133#define regFMT1_FMT_CLAMP_COMPONENT_R_BASE_IDX 2 6134#define regFMT1_FMT_CLAMP_COMPONENT_G 0x1897 6135#define regFMT1_FMT_CLAMP_COMPONENT_G_BASE_IDX 2 6136#define regFMT1_FMT_CLAMP_COMPONENT_B 0x1898 6137#define regFMT1_FMT_CLAMP_COMPONENT_B_BASE_IDX 2 6138#define regFMT1_FMT_DYNAMIC_EXP_CNTL 0x1899 6139#define regFMT1_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2 6140#define regFMT1_FMT_CONTROL 0x189a 6141#define regFMT1_FMT_CONTROL_BASE_IDX 2 6142#define regFMT1_FMT_BIT_DEPTH_CONTROL 0x189b 6143#define regFMT1_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2 6144#define regFMT1_FMT_DITHER_RAND_R_SEED 0x189c 6145#define regFMT1_FMT_DITHER_RAND_R_SEED_BASE_IDX 2 6146#define regFMT1_FMT_DITHER_RAND_G_SEED 0x189d 6147#define regFMT1_FMT_DITHER_RAND_G_SEED_BASE_IDX 2 6148#define regFMT1_FMT_DITHER_RAND_B_SEED 0x189e 6149#define regFMT1_FMT_DITHER_RAND_B_SEED_BASE_IDX 2 6150#define regFMT1_FMT_CLAMP_CNTL 0x189f 6151#define regFMT1_FMT_CLAMP_CNTL_BASE_IDX 2 6152#define regFMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x18a0 6153#define regFMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2 6154#define regFMT1_FMT_MAP420_MEMORY_CONTROL 0x18a1 6155#define regFMT1_FMT_MAP420_MEMORY_CONTROL_BASE_IDX 2 6156#define regFMT1_FMT_422_CONTROL 0x18a3 6157#define regFMT1_FMT_422_CONTROL_BASE_IDX 2 6158 6159 6160// addressBlock: dce_dc_opp_dpg1_dispdec 6161// base address: 0x168 6162#define regDPG1_DPG_CONTROL 0x18ae 6163#define regDPG1_DPG_CONTROL_BASE_IDX 2 6164#define regDPG1_DPG_RAMP_CONTROL 0x18af 6165#define regDPG1_DPG_RAMP_CONTROL_BASE_IDX 2 6166#define regDPG1_DPG_DIMENSIONS 0x18b0 6167#define regDPG1_DPG_DIMENSIONS_BASE_IDX 2 6168#define regDPG1_DPG_COLOUR_R_CR 0x18b1 6169#define regDPG1_DPG_COLOUR_R_CR_BASE_IDX 2 6170#define regDPG1_DPG_COLOUR_G_Y 0x18b2 6171#define regDPG1_DPG_COLOUR_G_Y_BASE_IDX 2 6172#define regDPG1_DPG_COLOUR_B_CB 0x18b3 6173#define regDPG1_DPG_COLOUR_B_CB_BASE_IDX 2 6174#define regDPG1_DPG_OFFSET_SEGMENT 0x18b4 6175#define regDPG1_DPG_OFFSET_SEGMENT_BASE_IDX 2 6176#define regDPG1_DPG_STATUS 0x18b5 6177#define regDPG1_DPG_STATUS_BASE_IDX 2 6178 6179// addressBlock: dce_dc_opp_oppbuf1_dispdec 6180// base address: 0x168 6181#define regOPPBUF1_OPPBUF_CONTROL 0x18de 6182#define regOPPBUF1_OPPBUF_CONTROL_BASE_IDX 2 6183#define regOPPBUF1_OPPBUF_3D_PARAMETERS_0 0x18df 6184#define regOPPBUF1_OPPBUF_3D_PARAMETERS_0_BASE_IDX 2 6185#define regOPPBUF1_OPPBUF_3D_PARAMETERS_1 0x18e0 6186#define regOPPBUF1_OPPBUF_3D_PARAMETERS_1_BASE_IDX 2 6187#define regOPPBUF1_OPPBUF_CONTROL1 0x18e3 6188#define regOPPBUF1_OPPBUF_CONTROL1_BASE_IDX 2 6189 6190 6191// addressBlock: dce_dc_opp_opp_pipe1_dispdec 6192// base address: 0x168 6193#define regOPP_PIPE1_OPP_PIPE_CONTROL 0x18e6 6194#define regOPP_PIPE1_OPP_PIPE_CONTROL_BASE_IDX 2 6195 6196 6197// addressBlock: dce_dc_opp_opp_pipe_crc1_dispdec 6198// base address: 0x168 6199#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL 0x18eb 6200#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL_BASE_IDX 2 6201#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_MASK 0x18ec 6202#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_MASK_BASE_IDX 2 6203#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0 0x18ed 6204#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0_BASE_IDX 2 6205#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1 0x18ee 6206#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1_BASE_IDX 2 6207#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2 0x18ef 6208#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2_BASE_IDX 2 6209 6210 6211// addressBlock: dce_dc_opp_fmt2_dispdec 6212// base address: 0x2d0 6213#define regFMT2_FMT_CLAMP_COMPONENT_R 0x18f0 6214#define regFMT2_FMT_CLAMP_COMPONENT_R_BASE_IDX 2 6215#define regFMT2_FMT_CLAMP_COMPONENT_G 0x18f1 6216#define regFMT2_FMT_CLAMP_COMPONENT_G_BASE_IDX 2 6217#define regFMT2_FMT_CLAMP_COMPONENT_B 0x18f2 6218#define regFMT2_FMT_CLAMP_COMPONENT_B_BASE_IDX 2 6219#define regFMT2_FMT_DYNAMIC_EXP_CNTL 0x18f3 6220#define regFMT2_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2 6221#define regFMT2_FMT_CONTROL 0x18f4 6222#define regFMT2_FMT_CONTROL_BASE_IDX 2 6223#define regFMT2_FMT_BIT_DEPTH_CONTROL 0x18f5 6224#define regFMT2_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2 6225#define regFMT2_FMT_DITHER_RAND_R_SEED 0x18f6 6226#define regFMT2_FMT_DITHER_RAND_R_SEED_BASE_IDX 2 6227#define regFMT2_FMT_DITHER_RAND_G_SEED 0x18f7 6228#define regFMT2_FMT_DITHER_RAND_G_SEED_BASE_IDX 2 6229#define regFMT2_FMT_DITHER_RAND_B_SEED 0x18f8 6230#define regFMT2_FMT_DITHER_RAND_B_SEED_BASE_IDX 2 6231#define regFMT2_FMT_CLAMP_CNTL 0x18f9 6232#define regFMT2_FMT_CLAMP_CNTL_BASE_IDX 2 6233#define regFMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x18fa 6234#define regFMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2 6235#define regFMT2_FMT_MAP420_MEMORY_CONTROL 0x18fb 6236#define regFMT2_FMT_MAP420_MEMORY_CONTROL_BASE_IDX 2 6237#define regFMT2_FMT_422_CONTROL 0x18fd 6238#define regFMT2_FMT_422_CONTROL_BASE_IDX 2 6239 6240 6241// addressBlock: dce_dc_opp_dpg2_dispdec 6242// base address: 0x2d0 6243#define regDPG2_DPG_CONTROL 0x1908 6244#define regDPG2_DPG_CONTROL_BASE_IDX 2 6245#define regDPG2_DPG_RAMP_CONTROL 0x1909 6246#define regDPG2_DPG_RAMP_CONTROL_BASE_IDX 2 6247#define regDPG2_DPG_DIMENSIONS 0x190a 6248#define regDPG2_DPG_DIMENSIONS_BASE_IDX 2 6249#define regDPG2_DPG_COLOUR_R_CR 0x190b 6250#define regDPG2_DPG_COLOUR_R_CR_BASE_IDX 2 6251#define regDPG2_DPG_COLOUR_G_Y 0x190c 6252#define regDPG2_DPG_COLOUR_G_Y_BASE_IDX 2 6253#define regDPG2_DPG_COLOUR_B_CB 0x190d 6254#define regDPG2_DPG_COLOUR_B_CB_BASE_IDX 2 6255#define regDPG2_DPG_OFFSET_SEGMENT 0x190e 6256#define regDPG2_DPG_OFFSET_SEGMENT_BASE_IDX 2 6257#define regDPG2_DPG_STATUS 0x190f 6258#define regDPG2_DPG_STATUS_BASE_IDX 2 6259 6260 6261// addressBlock: dce_dc_opp_oppbuf2_dispdec 6262// base address: 0x2d0 6263#define regOPPBUF2_OPPBUF_CONTROL 0x1938 6264#define regOPPBUF2_OPPBUF_CONTROL_BASE_IDX 2 6265#define regOPPBUF2_OPPBUF_3D_PARAMETERS_0 0x1939 6266#define regOPPBUF2_OPPBUF_3D_PARAMETERS_0_BASE_IDX 2 6267#define regOPPBUF2_OPPBUF_3D_PARAMETERS_1 0x193a 6268#define regOPPBUF2_OPPBUF_3D_PARAMETERS_1_BASE_IDX 2 6269#define regOPPBUF2_OPPBUF_CONTROL1 0x193d 6270#define regOPPBUF2_OPPBUF_CONTROL1_BASE_IDX 2 6271 6272 6273// addressBlock: dce_dc_opp_opp_pipe2_dispdec 6274// base address: 0x2d0 6275#define regOPP_PIPE2_OPP_PIPE_CONTROL 0x1940 6276#define regOPP_PIPE2_OPP_PIPE_CONTROL_BASE_IDX 2 6277 6278 6279// addressBlock: dce_dc_opp_opp_pipe_crc2_dispdec 6280// base address: 0x2d0 6281#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL 0x1945 6282#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL_BASE_IDX 2 6283#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_MASK 0x1946 6284#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_MASK_BASE_IDX 2 6285#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0 0x1947 6286#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0_BASE_IDX 2 6287#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1 0x1948 6288#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1_BASE_IDX 2 6289#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT2 0x1949 6290#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT2_BASE_IDX 2 6291 6292 6293// addressBlock: dce_dc_opp_fmt3_dispdec 6294// base address: 0x438 6295#define regFMT3_FMT_CLAMP_COMPONENT_R 0x194a 6296#define regFMT3_FMT_CLAMP_COMPONENT_R_BASE_IDX 2 6297#define regFMT3_FMT_CLAMP_COMPONENT_G 0x194b 6298#define regFMT3_FMT_CLAMP_COMPONENT_G_BASE_IDX 2 6299#define regFMT3_FMT_CLAMP_COMPONENT_B 0x194c 6300#define regFMT3_FMT_CLAMP_COMPONENT_B_BASE_IDX 2 6301#define regFMT3_FMT_DYNAMIC_EXP_CNTL 0x194d 6302#define regFMT3_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2 6303#define regFMT3_FMT_CONTROL 0x194e 6304#define regFMT3_FMT_CONTROL_BASE_IDX 2 6305#define regFMT3_FMT_BIT_DEPTH_CONTROL 0x194f 6306#define regFMT3_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2 6307#define regFMT3_FMT_DITHER_RAND_R_SEED 0x1950 6308#define regFMT3_FMT_DITHER_RAND_R_SEED_BASE_IDX 2 6309#define regFMT3_FMT_DITHER_RAND_G_SEED 0x1951 6310#define regFMT3_FMT_DITHER_RAND_G_SEED_BASE_IDX 2 6311#define regFMT3_FMT_DITHER_RAND_B_SEED 0x1952 6312#define regFMT3_FMT_DITHER_RAND_B_SEED_BASE_IDX 2 6313#define regFMT3_FMT_CLAMP_CNTL 0x1953 6314#define regFMT3_FMT_CLAMP_CNTL_BASE_IDX 2 6315#define regFMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x1954 6316#define regFMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2 6317#define regFMT3_FMT_MAP420_MEMORY_CONTROL 0x1955 6318#define regFMT3_FMT_MAP420_MEMORY_CONTROL_BASE_IDX 2 6319#define regFMT3_FMT_422_CONTROL 0x1957 6320#define regFMT3_FMT_422_CONTROL_BASE_IDX 2 6321 6322 6323// addressBlock: dce_dc_opp_dpg3_dispdec 6324// base address: 0x438 6325#define regDPG3_DPG_CONTROL 0x1962 6326#define regDPG3_DPG_CONTROL_BASE_IDX 2 6327#define regDPG3_DPG_RAMP_CONTROL 0x1963 6328#define regDPG3_DPG_RAMP_CONTROL_BASE_IDX 2 6329#define regDPG3_DPG_DIMENSIONS 0x1964 6330#define regDPG3_DPG_DIMENSIONS_BASE_IDX 2 6331#define regDPG3_DPG_COLOUR_R_CR 0x1965 6332#define regDPG3_DPG_COLOUR_R_CR_BASE_IDX 2 6333#define regDPG3_DPG_COLOUR_G_Y 0x1966 6334#define regDPG3_DPG_COLOUR_G_Y_BASE_IDX 2 6335#define regDPG3_DPG_COLOUR_B_CB 0x1967 6336#define regDPG3_DPG_COLOUR_B_CB_BASE_IDX 2 6337#define regDPG3_DPG_OFFSET_SEGMENT 0x1968 6338#define regDPG3_DPG_OFFSET_SEGMENT_BASE_IDX 2 6339#define regDPG3_DPG_STATUS 0x1969 6340#define regDPG3_DPG_STATUS_BASE_IDX 2 6341 6342 6343// addressBlock: dce_dc_opp_oppbuf3_dispdec 6344// base address: 0x438 6345#define regOPPBUF3_OPPBUF_CONTROL 0x1992 6346#define regOPPBUF3_OPPBUF_CONTROL_BASE_IDX 2 6347#define regOPPBUF3_OPPBUF_3D_PARAMETERS_0 0x1993 6348#define regOPPBUF3_OPPBUF_3D_PARAMETERS_0_BASE_IDX 2 6349#define regOPPBUF3_OPPBUF_3D_PARAMETERS_1 0x1994 6350#define regOPPBUF3_OPPBUF_3D_PARAMETERS_1_BASE_IDX 2 6351#define regOPPBUF3_OPPBUF_CONTROL1 0x1997 6352#define regOPPBUF3_OPPBUF_CONTROL1_BASE_IDX 2 6353 6354 6355// addressBlock: dce_dc_opp_opp_pipe3_dispdec 6356// base address: 0x438 6357#define regOPP_PIPE3_OPP_PIPE_CONTROL 0x199a 6358#define regOPP_PIPE3_OPP_PIPE_CONTROL_BASE_IDX 2 6359 6360 6361// addressBlock: dce_dc_opp_opp_pipe_crc3_dispdec 6362// base address: 0x438 6363#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL 0x199f 6364#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL_BASE_IDX 2 6365#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_MASK 0x19a0 6366#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_MASK_BASE_IDX 2 6367#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0 0x19a1 6368#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0_BASE_IDX 2 6369#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1 0x19a2 6370#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1_BASE_IDX 2 6371#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT2 0x19a3 6372#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT2_BASE_IDX 2 6373 6374 6375// addressBlock: dce_dc_opp_opp_top_dispdec 6376// base address: 0x0 6377#define regOPP_TOP_CLK_CONTROL 0x1a5e 6378#define regOPP_TOP_CLK_CONTROL_BASE_IDX 2 6379#define regOPP_ABM_CONTROL 0x1a60 6380#define regOPP_ABM_CONTROL_BASE_IDX 2 6381 6382 6383// addressBlock: dce_dc_opp_dscrm0_dispdec 6384// base address: 0x0 6385#define regDSCRM0_DSCRM_DSC_FORWARD_CONFIG 0x1a64 6386#define regDSCRM0_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX 2 6387 6388 6389// addressBlock: dce_dc_opp_dscrm1_dispdec 6390// base address: 0x4 6391#define regDSCRM1_DSCRM_DSC_FORWARD_CONFIG 0x1a65 6392#define regDSCRM1_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX 2 6393 6394 6395// addressBlock: dce_dc_opp_dscrm2_dispdec 6396// base address: 0x8 6397#define regDSCRM2_DSCRM_DSC_FORWARD_CONFIG 0x1a66 6398#define regDSCRM2_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX 2 6399 6400 6401// addressBlock: dce_dc_opp_dscrm3_dispdec 6402// base address: 0xc 6403#define regDSCRM3_DSCRM_DSC_FORWARD_CONFIG 0x1a67 6404#define regDSCRM3_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX 2 6405 6406 6407// addressBlock: dce_dc_opp_opp_dcperfmon_dc_perfmon_dispdec 6408// base address: 0x6af8 6409#define regDC_PERFMON16_PERFCOUNTER_CNTL 0x1abe 6410#define regDC_PERFMON16_PERFCOUNTER_CNTL_BASE_IDX 2 6411#define regDC_PERFMON16_PERFCOUNTER_CNTL2 0x1abf 6412#define regDC_PERFMON16_PERFCOUNTER_CNTL2_BASE_IDX 2 6413#define regDC_PERFMON16_PERFCOUNTER_STATE 0x1ac0 6414#define regDC_PERFMON16_PERFCOUNTER_STATE_BASE_IDX 2 6415#define regDC_PERFMON16_PERFMON_CNTL 0x1ac1 6416#define regDC_PERFMON16_PERFMON_CNTL_BASE_IDX 2 6417#define regDC_PERFMON16_PERFMON_CNTL2 0x1ac2 6418#define regDC_PERFMON16_PERFMON_CNTL2_BASE_IDX 2 6419#define regDC_PERFMON16_PERFMON_CVALUE_INT_MISC 0x1ac3 6420#define regDC_PERFMON16_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 6421#define regDC_PERFMON16_PERFMON_CVALUE_LOW 0x1ac4 6422#define regDC_PERFMON16_PERFMON_CVALUE_LOW_BASE_IDX 2 6423#define regDC_PERFMON16_PERFMON_HI 0x1ac5 6424#define regDC_PERFMON16_PERFMON_HI_BASE_IDX 2 6425#define regDC_PERFMON16_PERFMON_LOW 0x1ac6 6426#define regDC_PERFMON16_PERFMON_LOW_BASE_IDX 2 6427 6428 6429// addressBlock: dce_dc_optc_odm0_dispdec 6430// base address: 0x0 6431#define regODM0_OPTC_INPUT_GLOBAL_CONTROL 0x1aca 6432#define regODM0_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX 2 6433#define regODM0_OPTC_DATA_SOURCE_SELECT 0x1acb 6434#define regODM0_OPTC_DATA_SOURCE_SELECT_BASE_IDX 2 6435#define regODM0_OPTC_DATA_FORMAT_CONTROL 0x1acc 6436#define regODM0_OPTC_DATA_FORMAT_CONTROL_BASE_IDX 2 6437#define regODM0_OPTC_BYTES_PER_PIXEL 0x1acd 6438#define regODM0_OPTC_BYTES_PER_PIXEL_BASE_IDX 2 6439#define regODM0_OPTC_WIDTH_CONTROL 0x1ace 6440#define regODM0_OPTC_WIDTH_CONTROL_BASE_IDX 2 6441#define regODM0_OPTC_INPUT_CLOCK_CONTROL 0x1acf 6442#define regODM0_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX 2 6443#define regODM0_OPTC_MEMORY_CONFIG 0x1ad0 6444#define regODM0_OPTC_MEMORY_CONFIG_BASE_IDX 2 6445#define regODM0_OPTC_INPUT_SPARE_REGISTER 0x1ad1 6446#define regODM0_OPTC_INPUT_SPARE_REGISTER_BASE_IDX 2 6447 6448 6449// addressBlock: dce_dc_optc_odm1_dispdec 6450// base address: 0x40 6451#define regODM1_OPTC_INPUT_GLOBAL_CONTROL 0x1ada 6452#define regODM1_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX 2 6453#define regODM1_OPTC_DATA_SOURCE_SELECT 0x1adb 6454#define regODM1_OPTC_DATA_SOURCE_SELECT_BASE_IDX 2 6455#define regODM1_OPTC_DATA_FORMAT_CONTROL 0x1adc 6456#define regODM1_OPTC_DATA_FORMAT_CONTROL_BASE_IDX 2 6457#define regODM1_OPTC_BYTES_PER_PIXEL 0x1add 6458#define regODM1_OPTC_BYTES_PER_PIXEL_BASE_IDX 2 6459#define regODM1_OPTC_WIDTH_CONTROL 0x1ade 6460#define regODM1_OPTC_WIDTH_CONTROL_BASE_IDX 2 6461#define regODM1_OPTC_INPUT_CLOCK_CONTROL 0x1adf 6462#define regODM1_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX 2 6463#define regODM1_OPTC_MEMORY_CONFIG 0x1ae0 6464#define regODM1_OPTC_MEMORY_CONFIG_BASE_IDX 2 6465#define regODM1_OPTC_INPUT_SPARE_REGISTER 0x1ae1 6466#define regODM1_OPTC_INPUT_SPARE_REGISTER_BASE_IDX 2 6467 6468 6469// addressBlock: dce_dc_optc_odm2_dispdec 6470// base address: 0x80 6471#define regODM2_OPTC_INPUT_GLOBAL_CONTROL 0x1aea 6472#define regODM2_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX 2 6473#define regODM2_OPTC_DATA_SOURCE_SELECT 0x1aeb 6474#define regODM2_OPTC_DATA_SOURCE_SELECT_BASE_IDX 2 6475#define regODM2_OPTC_DATA_FORMAT_CONTROL 0x1aec 6476#define regODM2_OPTC_DATA_FORMAT_CONTROL_BASE_IDX 2 6477#define regODM2_OPTC_BYTES_PER_PIXEL 0x1aed 6478#define regODM2_OPTC_BYTES_PER_PIXEL_BASE_IDX 2 6479#define regODM2_OPTC_WIDTH_CONTROL 0x1aee 6480#define regODM2_OPTC_WIDTH_CONTROL_BASE_IDX 2 6481#define regODM2_OPTC_INPUT_CLOCK_CONTROL 0x1aef 6482#define regODM2_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX 2 6483#define regODM2_OPTC_MEMORY_CONFIG 0x1af0 6484#define regODM2_OPTC_MEMORY_CONFIG_BASE_IDX 2 6485#define regODM2_OPTC_INPUT_SPARE_REGISTER 0x1af1 6486#define regODM2_OPTC_INPUT_SPARE_REGISTER_BASE_IDX 2 6487 6488 6489// addressBlock: dce_dc_optc_odm3_dispdec 6490// base address: 0xc0 6491#define regODM3_OPTC_INPUT_GLOBAL_CONTROL 0x1afa 6492#define regODM3_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX 2 6493#define regODM3_OPTC_DATA_SOURCE_SELECT 0x1afb 6494#define regODM3_OPTC_DATA_SOURCE_SELECT_BASE_IDX 2 6495#define regODM3_OPTC_DATA_FORMAT_CONTROL 0x1afc 6496#define regODM3_OPTC_DATA_FORMAT_CONTROL_BASE_IDX 2 6497#define regODM3_OPTC_BYTES_PER_PIXEL 0x1afd 6498#define regODM3_OPTC_BYTES_PER_PIXEL_BASE_IDX 2 6499#define regODM3_OPTC_WIDTH_CONTROL 0x1afe 6500#define regODM3_OPTC_WIDTH_CONTROL_BASE_IDX 2 6501#define regODM3_OPTC_INPUT_CLOCK_CONTROL 0x1aff 6502#define regODM3_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX 2 6503#define regODM3_OPTC_MEMORY_CONFIG 0x1b00 6504#define regODM3_OPTC_MEMORY_CONFIG_BASE_IDX 2 6505#define regODM3_OPTC_INPUT_SPARE_REGISTER 0x1b01 6506#define regODM3_OPTC_INPUT_SPARE_REGISTER_BASE_IDX 2 6507 6508 6509// addressBlock: dce_dc_optc_otg0_dispdec 6510// base address: 0x0 6511#define regOTG0_OTG_H_TOTAL 0x1b2a 6512#define regOTG0_OTG_H_TOTAL_BASE_IDX 2 6513#define regOTG0_OTG_H_BLANK_START_END 0x1b2b 6514#define regOTG0_OTG_H_BLANK_START_END_BASE_IDX 2 6515#define regOTG0_OTG_H_SYNC_A 0x1b2c 6516#define regOTG0_OTG_H_SYNC_A_BASE_IDX 2 6517#define regOTG0_OTG_H_SYNC_A_CNTL 0x1b2d 6518#define regOTG0_OTG_H_SYNC_A_CNTL_BASE_IDX 2 6519#define regOTG0_OTG_H_TIMING_CNTL 0x1b2e 6520#define regOTG0_OTG_H_TIMING_CNTL_BASE_IDX 2 6521#define regOTG0_OTG_V_TOTAL 0x1b2f 6522#define regOTG0_OTG_V_TOTAL_BASE_IDX 2 6523#define regOTG0_OTG_V_TOTAL_MIN 0x1b30 6524#define regOTG0_OTG_V_TOTAL_MIN_BASE_IDX 2 6525#define regOTG0_OTG_V_TOTAL_MAX 0x1b31 6526#define regOTG0_OTG_V_TOTAL_MAX_BASE_IDX 2 6527#define regOTG0_OTG_V_TOTAL_MID 0x1b32 6528#define regOTG0_OTG_V_TOTAL_MID_BASE_IDX 2 6529#define regOTG0_OTG_V_TOTAL_CONTROL 0x1b33 6530#define regOTG0_OTG_V_TOTAL_CONTROL_BASE_IDX 2 6531#define regOTG0_OTG_V_COUNT_STOP_CONTROL 0x1b34 6532#define regOTG0_OTG_V_COUNT_STOP_CONTROL_BASE_IDX 2 6533#define regOTG0_OTG_V_COUNT_STOP_CONTROL2 0x1b35 6534#define regOTG0_OTG_V_COUNT_STOP_CONTROL2_BASE_IDX 2 6535#define regOTG0_OTG_V_TOTAL_INT_STATUS 0x1b36 6536#define regOTG0_OTG_V_TOTAL_INT_STATUS_BASE_IDX 2 6537#define regOTG0_OTG_VSYNC_NOM_INT_STATUS 0x1b37 6538#define regOTG0_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX 2 6539#define regOTG0_OTG_V_BLANK_START_END 0x1b38 6540#define regOTG0_OTG_V_BLANK_START_END_BASE_IDX 2 6541#define regOTG0_OTG_V_SYNC_A 0x1b39 6542#define regOTG0_OTG_V_SYNC_A_BASE_IDX 2 6543#define regOTG0_OTG_V_SYNC_A_CNTL 0x1b3a 6544#define regOTG0_OTG_V_SYNC_A_CNTL_BASE_IDX 2 6545#define regOTG0_OTG_TRIGA_CNTL 0x1b3b 6546#define regOTG0_OTG_TRIGA_CNTL_BASE_IDX 2 6547#define regOTG0_OTG_TRIGA_MANUAL_TRIG 0x1b3c 6548#define regOTG0_OTG_TRIGA_MANUAL_TRIG_BASE_IDX 2 6549#define regOTG0_OTG_TRIGB_CNTL 0x1b3d 6550#define regOTG0_OTG_TRIGB_CNTL_BASE_IDX 2 6551#define regOTG0_OTG_TRIGB_MANUAL_TRIG 0x1b3e 6552#define regOTG0_OTG_TRIGB_MANUAL_TRIG_BASE_IDX 2 6553#define regOTG0_OTG_FORCE_COUNT_NOW_CNTL 0x1b3f 6554#define regOTG0_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX 2 6555#define regOTG0_OTG_STEREO_FORCE_NEXT_EYE 0x1b41 6556#define regOTG0_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX 2 6557#define regOTG0_OTG_CONTROL 0x1b43 6558#define regOTG0_OTG_CONTROL_BASE_IDX 2 6559#define regOTG0_OTG_DLPC_CONTROL 0x1b44 6560#define regOTG0_OTG_DLPC_CONTROL_BASE_IDX 2 6561#define regOTG0_OTG_INTERLACE_CONTROL 0x1b45 6562#define regOTG0_OTG_INTERLACE_CONTROL_BASE_IDX 2 6563#define regOTG0_OTG_INTERLACE_STATUS 0x1b46 6564#define regOTG0_OTG_INTERLACE_STATUS_BASE_IDX 2 6565#define regOTG0_OTG_PIXEL_DATA_READBACK0 0x1b47 6566#define regOTG0_OTG_PIXEL_DATA_READBACK0_BASE_IDX 2 6567#define regOTG0_OTG_PIXEL_DATA_READBACK1 0x1b48 6568#define regOTG0_OTG_PIXEL_DATA_READBACK1_BASE_IDX 2 6569#define regOTG0_OTG_STATUS 0x1b49 6570#define regOTG0_OTG_STATUS_BASE_IDX 2 6571#define regOTG0_OTG_STATUS_POSITION 0x1b4a 6572#define regOTG0_OTG_STATUS_POSITION_BASE_IDX 2 6573#define regOTG0_OTG_LONG_VBLANK_STATUS 0x1b4b 6574#define regOTG0_OTG_LONG_VBLANK_STATUS_BASE_IDX 2 6575#define regOTG0_OTG_NOM_VERT_POSITION 0x1b4c 6576#define regOTG0_OTG_NOM_VERT_POSITION_BASE_IDX 2 6577#define regOTG0_OTG_STATUS_FRAME_COUNT 0x1b4d 6578#define regOTG0_OTG_STATUS_FRAME_COUNT_BASE_IDX 2 6579#define regOTG0_OTG_STATUS_VF_COUNT 0x1b4e 6580#define regOTG0_OTG_STATUS_VF_COUNT_BASE_IDX 2 6581#define regOTG0_OTG_STATUS_HV_COUNT 0x1b4f 6582#define regOTG0_OTG_STATUS_HV_COUNT_BASE_IDX 2 6583#define regOTG0_OTG_COUNT_CONTROL 0x1b50 6584#define regOTG0_OTG_COUNT_CONTROL_BASE_IDX 2 6585#define regOTG0_OTG_COUNT_RESET 0x1b51 6586#define regOTG0_OTG_COUNT_RESET_BASE_IDX 2 6587#define regOTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1b52 6588#define regOTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2 6589#define regOTG0_OTG_VERT_SYNC_CONTROL 0x1b53 6590#define regOTG0_OTG_VERT_SYNC_CONTROL_BASE_IDX 2 6591#define regOTG0_OTG_STEREO_STATUS 0x1b54 6592#define regOTG0_OTG_STEREO_STATUS_BASE_IDX 2 6593#define regOTG0_OTG_STEREO_CONTROL 0x1b55 6594#define regOTG0_OTG_STEREO_CONTROL_BASE_IDX 2 6595#define regOTG0_OTG_SNAPSHOT_STATUS 0x1b56 6596#define regOTG0_OTG_SNAPSHOT_STATUS_BASE_IDX 2 6597#define regOTG0_OTG_SNAPSHOT_CONTROL 0x1b57 6598#define regOTG0_OTG_SNAPSHOT_CONTROL_BASE_IDX 2 6599#define regOTG0_OTG_SNAPSHOT_POSITION 0x1b58 6600#define regOTG0_OTG_SNAPSHOT_POSITION_BASE_IDX 2 6601#define regOTG0_OTG_SNAPSHOT_FRAME 0x1b59 6602#define regOTG0_OTG_SNAPSHOT_FRAME_BASE_IDX 2 6603#define regOTG0_OTG_INTERRUPT_CONTROL 0x1b5a 6604#define regOTG0_OTG_INTERRUPT_CONTROL_BASE_IDX 2 6605#define regOTG0_OTG_UPDATE_LOCK 0x1b5b 6606#define regOTG0_OTG_UPDATE_LOCK_BASE_IDX 2 6607#define regOTG0_OTG_DOUBLE_BUFFER_CONTROL 0x1b5c 6608#define regOTG0_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 6609#define regOTG0_OTG_MASTER_EN 0x1b5d 6610#define regOTG0_OTG_MASTER_EN_BASE_IDX 2 6611#define regOTG0_OTG_VERTICAL_INTERRUPT0_POSITION 0x1b5f 6612#define regOTG0_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2 6613#define regOTG0_OTG_VERTICAL_INTERRUPT0_CONTROL 0x1b60 6614#define regOTG0_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2 6615#define regOTG0_OTG_VERTICAL_INTERRUPT1_POSITION 0x1b61 6616#define regOTG0_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2 6617#define regOTG0_OTG_VERTICAL_INTERRUPT1_CONTROL 0x1b62 6618#define regOTG0_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2 6619#define regOTG0_OTG_VERTICAL_INTERRUPT2_POSITION 0x1b63 6620#define regOTG0_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2 6621#define regOTG0_OTG_VERTICAL_INTERRUPT2_CONTROL 0x1b64 6622#define regOTG0_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2 6623#define regOTG0_OTG_CRC_CNTL 0x1b65 6624#define regOTG0_OTG_CRC_CNTL_BASE_IDX 2 6625#define regOTG0_OTG_CRC0_WINDOWA_X_CONTROL 0x1b66 6626#define regOTG0_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2 6627#define regOTG0_OTG_CRC0_WINDOWA_Y_CONTROL 0x1b67 6628#define regOTG0_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2 6629#define regOTG0_OTG_CRC0_WINDOWB_X_CONTROL 0x1b68 6630#define regOTG0_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2 6631#define regOTG0_OTG_CRC0_WINDOWB_Y_CONTROL 0x1b69 6632#define regOTG0_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2 6633#define regOTG0_OTG_CRC0_DATA_RG 0x1b6a 6634#define regOTG0_OTG_CRC0_DATA_RG_BASE_IDX 2 6635#define regOTG0_OTG_CRC0_DATA_B 0x1b6b 6636#define regOTG0_OTG_CRC0_DATA_B_BASE_IDX 2 6637#define regOTG0_OTG_CRC1_WINDOWA_X_CONTROL 0x1b6c 6638#define regOTG0_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2 6639#define regOTG0_OTG_CRC1_WINDOWA_Y_CONTROL 0x1b6d 6640#define regOTG0_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2 6641#define regOTG0_OTG_CRC1_WINDOWB_X_CONTROL 0x1b6e 6642#define regOTG0_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2 6643#define regOTG0_OTG_CRC1_WINDOWB_Y_CONTROL 0x1b6f 6644#define regOTG0_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2 6645#define regOTG0_OTG_CRC1_DATA_RG 0x1b70 6646#define regOTG0_OTG_CRC1_DATA_RG_BASE_IDX 2 6647#define regOTG0_OTG_CRC1_DATA_B 0x1b71 6648#define regOTG0_OTG_CRC1_DATA_B_BASE_IDX 2 6649#define regOTG0_OTG_CRC2_DATA_RG 0x1b72 6650#define regOTG0_OTG_CRC2_DATA_RG_BASE_IDX 2 6651#define regOTG0_OTG_CRC2_DATA_B 0x1b73 6652#define regOTG0_OTG_CRC2_DATA_B_BASE_IDX 2 6653#define regOTG0_OTG_CRC3_DATA_RG 0x1b74 6654#define regOTG0_OTG_CRC3_DATA_RG_BASE_IDX 2 6655#define regOTG0_OTG_CRC3_DATA_B 0x1b75 6656#define regOTG0_OTG_CRC3_DATA_B_BASE_IDX 2 6657#define regOTG0_OTG_CRC_SIG_RED_GREEN_MASK 0x1b76 6658#define regOTG0_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2 6659#define regOTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK 0x1b77 6660#define regOTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2 6661#define regOTG0_OTG_CRC0_WINDOWA_X_CONTROL_READBACK 0x1b78 6662#define regOTG0_OTG_CRC0_WINDOWA_X_CONTROL_READBACK_BASE_IDX 2 6663#define regOTG0_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK 0x1b79 6664#define regOTG0_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK_BASE_IDX 2 6665#define regOTG0_OTG_CRC0_WINDOWB_X_CONTROL_READBACK 0x1b7a 6666#define regOTG0_OTG_CRC0_WINDOWB_X_CONTROL_READBACK_BASE_IDX 2 6667#define regOTG0_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK 0x1b7b 6668#define regOTG0_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK_BASE_IDX 2 6669#define regOTG0_OTG_CRC1_WINDOWA_X_CONTROL_READBACK 0x1b7c 6670#define regOTG0_OTG_CRC1_WINDOWA_X_CONTROL_READBACK_BASE_IDX 2 6671#define regOTG0_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK 0x1b7d 6672#define regOTG0_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK_BASE_IDX 2 6673#define regOTG0_OTG_CRC1_WINDOWB_X_CONTROL_READBACK 0x1b7e 6674#define regOTG0_OTG_CRC1_WINDOWB_X_CONTROL_READBACK_BASE_IDX 2 6675#define regOTG0_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK 0x1b7f 6676#define regOTG0_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK_BASE_IDX 2 6677#define regOTG0_OTG_STATIC_SCREEN_CONTROL 0x1b80 6678#define regOTG0_OTG_STATIC_SCREEN_CONTROL_BASE_IDX 2 6679#define regOTG0_OTG_3D_STRUCTURE_CONTROL 0x1b81 6680#define regOTG0_OTG_3D_STRUCTURE_CONTROL_BASE_IDX 2 6681#define regOTG0_OTG_GSL_VSYNC_GAP 0x1b82 6682#define regOTG0_OTG_GSL_VSYNC_GAP_BASE_IDX 2 6683#define regOTG0_OTG_MASTER_UPDATE_MODE 0x1b83 6684#define regOTG0_OTG_MASTER_UPDATE_MODE_BASE_IDX 2 6685#define regOTG0_OTG_CLOCK_CONTROL 0x1b84 6686#define regOTG0_OTG_CLOCK_CONTROL_BASE_IDX 2 6687#define regOTG0_OTG_VSTARTUP_PARAM 0x1b85 6688#define regOTG0_OTG_VSTARTUP_PARAM_BASE_IDX 2 6689#define regOTG0_OTG_VUPDATE_PARAM 0x1b86 6690#define regOTG0_OTG_VUPDATE_PARAM_BASE_IDX 2 6691#define regOTG0_OTG_VREADY_PARAM 0x1b87 6692#define regOTG0_OTG_VREADY_PARAM_BASE_IDX 2 6693#define regOTG0_OTG_GLOBAL_SYNC_STATUS 0x1b88 6694#define regOTG0_OTG_GLOBAL_SYNC_STATUS_BASE_IDX 2 6695#define regOTG0_OTG_MASTER_UPDATE_LOCK 0x1b89 6696#define regOTG0_OTG_MASTER_UPDATE_LOCK_BASE_IDX 2 6697#define regOTG0_OTG_GSL_CONTROL 0x1b8a 6698#define regOTG0_OTG_GSL_CONTROL_BASE_IDX 2 6699#define regOTG0_OTG_GSL_WINDOW_X 0x1b8b 6700#define regOTG0_OTG_GSL_WINDOW_X_BASE_IDX 2 6701#define regOTG0_OTG_GSL_WINDOW_Y 0x1b8c 6702#define regOTG0_OTG_GSL_WINDOW_Y_BASE_IDX 2 6703#define regOTG0_OTG_VUPDATE_KEEPOUT 0x1b8d 6704#define regOTG0_OTG_VUPDATE_KEEPOUT_BASE_IDX 2 6705#define regOTG0_OTG_GLOBAL_CONTROL0 0x1b8e 6706#define regOTG0_OTG_GLOBAL_CONTROL0_BASE_IDX 2 6707#define regOTG0_OTG_GLOBAL_CONTROL1 0x1b8f 6708#define regOTG0_OTG_GLOBAL_CONTROL1_BASE_IDX 2 6709#define regOTG0_OTG_GLOBAL_CONTROL2 0x1b90 6710#define regOTG0_OTG_GLOBAL_CONTROL2_BASE_IDX 2 6711#define regOTG0_OTG_GLOBAL_CONTROL3 0x1b91 6712#define regOTG0_OTG_GLOBAL_CONTROL3_BASE_IDX 2 6713#define regOTG0_OTG_GLOBAL_CONTROL4 0x1b92 6714#define regOTG0_OTG_GLOBAL_CONTROL4_BASE_IDX 2 6715#define regOTG0_OTG_TRIG_MANUAL_CONTROL 0x1b93 6716#define regOTG0_OTG_TRIG_MANUAL_CONTROL_BASE_IDX 2 6717#define regOTG0_OTG_DRR_TIMING_INT_STATUS 0x1b95 6718#define regOTG0_OTG_DRR_TIMING_INT_STATUS_BASE_IDX 2 6719#define regOTG0_OTG_DRR_V_TOTAL_REACH_RANGE 0x1b96 6720#define regOTG0_OTG_DRR_V_TOTAL_REACH_RANGE_BASE_IDX 2 6721#define regOTG0_OTG_DRR_V_TOTAL_CHANGE 0x1b97 6722#define regOTG0_OTG_DRR_V_TOTAL_CHANGE_BASE_IDX 2 6723#define regOTG0_OTG_DRR_TRIGGER_WINDOW 0x1b98 6724#define regOTG0_OTG_DRR_TRIGGER_WINDOW_BASE_IDX 2 6725#define regOTG0_OTG_DRR_CONTROL 0x1b99 6726#define regOTG0_OTG_DRR_CONTROL_BASE_IDX 2 6727#define regOTG0_OTG_DRR_CONTOL2 0x1b9a 6728#define regOTG0_OTG_DRR_CONTOL2_BASE_IDX 2 6729#define regOTG0_OTG_M_CONST_DTO0 0x1b9b 6730#define regOTG0_OTG_M_CONST_DTO0_BASE_IDX 2 6731#define regOTG0_OTG_M_CONST_DTO1 0x1b9c 6732#define regOTG0_OTG_M_CONST_DTO1_BASE_IDX 2 6733#define regOTG0_OTG_REQUEST_CONTROL 0x1b9d 6734#define regOTG0_OTG_REQUEST_CONTROL_BASE_IDX 2 6735#define regOTG0_OTG_DSC_START_POSITION 0x1b9e 6736#define regOTG0_OTG_DSC_START_POSITION_BASE_IDX 2 6737#define regOTG0_OTG_PIPE_UPDATE_STATUS 0x1b9f 6738#define regOTG0_OTG_PIPE_UPDATE_STATUS_BASE_IDX 2 6739#define regOTG0_OTG_SPARE_REGISTER 0x1ba0 6740#define regOTG0_OTG_SPARE_REGISTER_BASE_IDX 2 6741 6742 6743// addressBlock: dce_dc_optc_otg1_dispdec 6744// base address: 0x200 6745#define regOTG1_OTG_H_TOTAL 0x1baa 6746#define regOTG1_OTG_H_TOTAL_BASE_IDX 2 6747#define regOTG1_OTG_H_BLANK_START_END 0x1bab 6748#define regOTG1_OTG_H_BLANK_START_END_BASE_IDX 2 6749#define regOTG1_OTG_H_SYNC_A 0x1bac 6750#define regOTG1_OTG_H_SYNC_A_BASE_IDX 2 6751#define regOTG1_OTG_H_SYNC_A_CNTL 0x1bad 6752#define regOTG1_OTG_H_SYNC_A_CNTL_BASE_IDX 2 6753#define regOTG1_OTG_H_TIMING_CNTL 0x1bae 6754#define regOTG1_OTG_H_TIMING_CNTL_BASE_IDX 2 6755#define regOTG1_OTG_V_TOTAL 0x1baf 6756#define regOTG1_OTG_V_TOTAL_BASE_IDX 2 6757#define regOTG1_OTG_V_TOTAL_MIN 0x1bb0 6758#define regOTG1_OTG_V_TOTAL_MIN_BASE_IDX 2 6759#define regOTG1_OTG_V_TOTAL_MAX 0x1bb1 6760#define regOTG1_OTG_V_TOTAL_MAX_BASE_IDX 2 6761#define regOTG1_OTG_V_TOTAL_MID 0x1bb2 6762#define regOTG1_OTG_V_TOTAL_MID_BASE_IDX 2 6763#define regOTG1_OTG_V_TOTAL_CONTROL 0x1bb3 6764#define regOTG1_OTG_V_TOTAL_CONTROL_BASE_IDX 2 6765#define regOTG1_OTG_V_COUNT_STOP_CONTROL 0x1bb4 6766#define regOTG1_OTG_V_COUNT_STOP_CONTROL_BASE_IDX 2 6767#define regOTG1_OTG_V_COUNT_STOP_CONTROL2 0x1bb5 6768#define regOTG1_OTG_V_COUNT_STOP_CONTROL2_BASE_IDX 2 6769#define regOTG1_OTG_V_TOTAL_INT_STATUS 0x1bb6 6770#define regOTG1_OTG_V_TOTAL_INT_STATUS_BASE_IDX 2 6771#define regOTG1_OTG_VSYNC_NOM_INT_STATUS 0x1bb7 6772#define regOTG1_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX 2 6773#define regOTG1_OTG_V_BLANK_START_END 0x1bb8 6774#define regOTG1_OTG_V_BLANK_START_END_BASE_IDX 2 6775#define regOTG1_OTG_V_SYNC_A 0x1bb9 6776#define regOTG1_OTG_V_SYNC_A_BASE_IDX 2 6777#define regOTG1_OTG_V_SYNC_A_CNTL 0x1bba 6778#define regOTG1_OTG_V_SYNC_A_CNTL_BASE_IDX 2 6779#define regOTG1_OTG_TRIGA_CNTL 0x1bbb 6780#define regOTG1_OTG_TRIGA_CNTL_BASE_IDX 2 6781#define regOTG1_OTG_TRIGA_MANUAL_TRIG 0x1bbc 6782#define regOTG1_OTG_TRIGA_MANUAL_TRIG_BASE_IDX 2 6783#define regOTG1_OTG_TRIGB_CNTL 0x1bbd 6784#define regOTG1_OTG_TRIGB_CNTL_BASE_IDX 2 6785#define regOTG1_OTG_TRIGB_MANUAL_TRIG 0x1bbe 6786#define regOTG1_OTG_TRIGB_MANUAL_TRIG_BASE_IDX 2 6787#define regOTG1_OTG_FORCE_COUNT_NOW_CNTL 0x1bbf 6788#define regOTG1_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX 2 6789#define regOTG1_OTG_STEREO_FORCE_NEXT_EYE 0x1bc1 6790#define regOTG1_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX 2 6791#define regOTG1_OTG_CONTROL 0x1bc3 6792#define regOTG1_OTG_CONTROL_BASE_IDX 2 6793#define regOTG1_OTG_DLPC_CONTROL 0x1bc4 6794#define regOTG1_OTG_DLPC_CONTROL_BASE_IDX 2 6795#define regOTG1_OTG_INTERLACE_CONTROL 0x1bc5 6796#define regOTG1_OTG_INTERLACE_CONTROL_BASE_IDX 2 6797#define regOTG1_OTG_INTERLACE_STATUS 0x1bc6 6798#define regOTG1_OTG_INTERLACE_STATUS_BASE_IDX 2 6799#define regOTG1_OTG_PIXEL_DATA_READBACK0 0x1bc7 6800#define regOTG1_OTG_PIXEL_DATA_READBACK0_BASE_IDX 2 6801#define regOTG1_OTG_PIXEL_DATA_READBACK1 0x1bc8 6802#define regOTG1_OTG_PIXEL_DATA_READBACK1_BASE_IDX 2 6803#define regOTG1_OTG_STATUS 0x1bc9 6804#define regOTG1_OTG_STATUS_BASE_IDX 2 6805#define regOTG1_OTG_STATUS_POSITION 0x1bca 6806#define regOTG1_OTG_STATUS_POSITION_BASE_IDX 2 6807#define regOTG1_OTG_LONG_VBLANK_STATUS 0x1bcb 6808#define regOTG1_OTG_LONG_VBLANK_STATUS_BASE_IDX 2 6809#define regOTG1_OTG_NOM_VERT_POSITION 0x1bcc 6810#define regOTG1_OTG_NOM_VERT_POSITION_BASE_IDX 2 6811#define regOTG1_OTG_STATUS_FRAME_COUNT 0x1bcd 6812#define regOTG1_OTG_STATUS_FRAME_COUNT_BASE_IDX 2 6813#define regOTG1_OTG_STATUS_VF_COUNT 0x1bce 6814#define regOTG1_OTG_STATUS_VF_COUNT_BASE_IDX 2 6815#define regOTG1_OTG_STATUS_HV_COUNT 0x1bcf 6816#define regOTG1_OTG_STATUS_HV_COUNT_BASE_IDX 2 6817#define regOTG1_OTG_COUNT_CONTROL 0x1bd0 6818#define regOTG1_OTG_COUNT_CONTROL_BASE_IDX 2 6819#define regOTG1_OTG_COUNT_RESET 0x1bd1 6820#define regOTG1_OTG_COUNT_RESET_BASE_IDX 2 6821#define regOTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1bd2 6822#define regOTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2 6823#define regOTG1_OTG_VERT_SYNC_CONTROL 0x1bd3 6824#define regOTG1_OTG_VERT_SYNC_CONTROL_BASE_IDX 2 6825#define regOTG1_OTG_STEREO_STATUS 0x1bd4 6826#define regOTG1_OTG_STEREO_STATUS_BASE_IDX 2 6827#define regOTG1_OTG_STEREO_CONTROL 0x1bd5 6828#define regOTG1_OTG_STEREO_CONTROL_BASE_IDX 2 6829#define regOTG1_OTG_SNAPSHOT_STATUS 0x1bd6 6830#define regOTG1_OTG_SNAPSHOT_STATUS_BASE_IDX 2 6831#define regOTG1_OTG_SNAPSHOT_CONTROL 0x1bd7 6832#define regOTG1_OTG_SNAPSHOT_CONTROL_BASE_IDX 2 6833#define regOTG1_OTG_SNAPSHOT_POSITION 0x1bd8 6834#define regOTG1_OTG_SNAPSHOT_POSITION_BASE_IDX 2 6835#define regOTG1_OTG_SNAPSHOT_FRAME 0x1bd9 6836#define regOTG1_OTG_SNAPSHOT_FRAME_BASE_IDX 2 6837#define regOTG1_OTG_INTERRUPT_CONTROL 0x1bda 6838#define regOTG1_OTG_INTERRUPT_CONTROL_BASE_IDX 2 6839#define regOTG1_OTG_UPDATE_LOCK 0x1bdb 6840#define regOTG1_OTG_UPDATE_LOCK_BASE_IDX 2 6841#define regOTG1_OTG_DOUBLE_BUFFER_CONTROL 0x1bdc 6842#define regOTG1_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 6843#define regOTG1_OTG_MASTER_EN 0x1bdd 6844#define regOTG1_OTG_MASTER_EN_BASE_IDX 2 6845#define regOTG1_OTG_VERTICAL_INTERRUPT0_POSITION 0x1bdf 6846#define regOTG1_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2 6847#define regOTG1_OTG_VERTICAL_INTERRUPT0_CONTROL 0x1be0 6848#define regOTG1_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2 6849#define regOTG1_OTG_VERTICAL_INTERRUPT1_POSITION 0x1be1 6850#define regOTG1_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2 6851#define regOTG1_OTG_VERTICAL_INTERRUPT1_CONTROL 0x1be2 6852#define regOTG1_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2 6853#define regOTG1_OTG_VERTICAL_INTERRUPT2_POSITION 0x1be3 6854#define regOTG1_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2 6855#define regOTG1_OTG_VERTICAL_INTERRUPT2_CONTROL 0x1be4 6856#define regOTG1_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2 6857#define regOTG1_OTG_CRC_CNTL 0x1be5 6858#define regOTG1_OTG_CRC_CNTL_BASE_IDX 2 6859#define regOTG1_OTG_CRC0_WINDOWA_X_CONTROL 0x1be6 6860#define regOTG1_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2 6861#define regOTG1_OTG_CRC0_WINDOWA_Y_CONTROL 0x1be7 6862#define regOTG1_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2 6863#define regOTG1_OTG_CRC0_WINDOWB_X_CONTROL 0x1be8 6864#define regOTG1_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2 6865#define regOTG1_OTG_CRC0_WINDOWB_Y_CONTROL 0x1be9 6866#define regOTG1_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2 6867#define regOTG1_OTG_CRC0_DATA_RG 0x1bea 6868#define regOTG1_OTG_CRC0_DATA_RG_BASE_IDX 2 6869#define regOTG1_OTG_CRC0_DATA_B 0x1beb 6870#define regOTG1_OTG_CRC0_DATA_B_BASE_IDX 2 6871#define regOTG1_OTG_CRC1_WINDOWA_X_CONTROL 0x1bec 6872#define regOTG1_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2 6873#define regOTG1_OTG_CRC1_WINDOWA_Y_CONTROL 0x1bed 6874#define regOTG1_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2 6875#define regOTG1_OTG_CRC1_WINDOWB_X_CONTROL 0x1bee 6876#define regOTG1_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2 6877#define regOTG1_OTG_CRC1_WINDOWB_Y_CONTROL 0x1bef 6878#define regOTG1_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2 6879#define regOTG1_OTG_CRC1_DATA_RG 0x1bf0 6880#define regOTG1_OTG_CRC1_DATA_RG_BASE_IDX 2 6881#define regOTG1_OTG_CRC1_DATA_B 0x1bf1 6882#define regOTG1_OTG_CRC1_DATA_B_BASE_IDX 2 6883#define regOTG1_OTG_CRC2_DATA_RG 0x1bf2 6884#define regOTG1_OTG_CRC2_DATA_RG_BASE_IDX 2 6885#define regOTG1_OTG_CRC2_DATA_B 0x1bf3 6886#define regOTG1_OTG_CRC2_DATA_B_BASE_IDX 2 6887#define regOTG1_OTG_CRC3_DATA_RG 0x1bf4 6888#define regOTG1_OTG_CRC3_DATA_RG_BASE_IDX 2 6889#define regOTG1_OTG_CRC3_DATA_B 0x1bf5 6890#define regOTG1_OTG_CRC3_DATA_B_BASE_IDX 2 6891#define regOTG1_OTG_CRC_SIG_RED_GREEN_MASK 0x1bf6 6892#define regOTG1_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2 6893#define regOTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK 0x1bf7 6894#define regOTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2 6895#define regOTG1_OTG_CRC0_WINDOWA_X_CONTROL_READBACK 0x1bf8 6896#define regOTG1_OTG_CRC0_WINDOWA_X_CONTROL_READBACK_BASE_IDX 2 6897#define regOTG1_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK 0x1bf9 6898#define regOTG1_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK_BASE_IDX 2 6899#define regOTG1_OTG_CRC0_WINDOWB_X_CONTROL_READBACK 0x1bfa 6900#define regOTG1_OTG_CRC0_WINDOWB_X_CONTROL_READBACK_BASE_IDX 2 6901#define regOTG1_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK 0x1bfb 6902#define regOTG1_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK_BASE_IDX 2 6903#define regOTG1_OTG_CRC1_WINDOWA_X_CONTROL_READBACK 0x1bfc 6904#define regOTG1_OTG_CRC1_WINDOWA_X_CONTROL_READBACK_BASE_IDX 2 6905#define regOTG1_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK 0x1bfd 6906#define regOTG1_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK_BASE_IDX 2 6907#define regOTG1_OTG_CRC1_WINDOWB_X_CONTROL_READBACK 0x1bfe 6908#define regOTG1_OTG_CRC1_WINDOWB_X_CONTROL_READBACK_BASE_IDX 2 6909#define regOTG1_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK 0x1bff 6910#define regOTG1_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK_BASE_IDX 2 6911#define regOTG1_OTG_STATIC_SCREEN_CONTROL 0x1c00 6912#define regOTG1_OTG_STATIC_SCREEN_CONTROL_BASE_IDX 2 6913#define regOTG1_OTG_3D_STRUCTURE_CONTROL 0x1c01 6914#define regOTG1_OTG_3D_STRUCTURE_CONTROL_BASE_IDX 2 6915#define regOTG1_OTG_GSL_VSYNC_GAP 0x1c02 6916#define regOTG1_OTG_GSL_VSYNC_GAP_BASE_IDX 2 6917#define regOTG1_OTG_MASTER_UPDATE_MODE 0x1c03 6918#define regOTG1_OTG_MASTER_UPDATE_MODE_BASE_IDX 2 6919#define regOTG1_OTG_CLOCK_CONTROL 0x1c04 6920#define regOTG1_OTG_CLOCK_CONTROL_BASE_IDX 2 6921#define regOTG1_OTG_VSTARTUP_PARAM 0x1c05 6922#define regOTG1_OTG_VSTARTUP_PARAM_BASE_IDX 2 6923#define regOTG1_OTG_VUPDATE_PARAM 0x1c06 6924#define regOTG1_OTG_VUPDATE_PARAM_BASE_IDX 2 6925#define regOTG1_OTG_VREADY_PARAM 0x1c07 6926#define regOTG1_OTG_VREADY_PARAM_BASE_IDX 2 6927#define regOTG1_OTG_GLOBAL_SYNC_STATUS 0x1c08 6928#define regOTG1_OTG_GLOBAL_SYNC_STATUS_BASE_IDX 2 6929#define regOTG1_OTG_MASTER_UPDATE_LOCK 0x1c09 6930#define regOTG1_OTG_MASTER_UPDATE_LOCK_BASE_IDX 2 6931#define regOTG1_OTG_GSL_CONTROL 0x1c0a 6932#define regOTG1_OTG_GSL_CONTROL_BASE_IDX 2 6933#define regOTG1_OTG_GSL_WINDOW_X 0x1c0b 6934#define regOTG1_OTG_GSL_WINDOW_X_BASE_IDX 2 6935#define regOTG1_OTG_GSL_WINDOW_Y 0x1c0c 6936#define regOTG1_OTG_GSL_WINDOW_Y_BASE_IDX 2 6937#define regOTG1_OTG_VUPDATE_KEEPOUT 0x1c0d 6938#define regOTG1_OTG_VUPDATE_KEEPOUT_BASE_IDX 2 6939#define regOTG1_OTG_GLOBAL_CONTROL0 0x1c0e 6940#define regOTG1_OTG_GLOBAL_CONTROL0_BASE_IDX 2 6941#define regOTG1_OTG_GLOBAL_CONTROL1 0x1c0f 6942#define regOTG1_OTG_GLOBAL_CONTROL1_BASE_IDX 2 6943#define regOTG1_OTG_GLOBAL_CONTROL2 0x1c10 6944#define regOTG1_OTG_GLOBAL_CONTROL2_BASE_IDX 2 6945#define regOTG1_OTG_GLOBAL_CONTROL3 0x1c11 6946#define regOTG1_OTG_GLOBAL_CONTROL3_BASE_IDX 2 6947#define regOTG1_OTG_GLOBAL_CONTROL4 0x1c12 6948#define regOTG1_OTG_GLOBAL_CONTROL4_BASE_IDX 2 6949#define regOTG1_OTG_TRIG_MANUAL_CONTROL 0x1c13 6950#define regOTG1_OTG_TRIG_MANUAL_CONTROL_BASE_IDX 2 6951#define regOTG1_OTG_DRR_TIMING_INT_STATUS 0x1c15 6952#define regOTG1_OTG_DRR_TIMING_INT_STATUS_BASE_IDX 2 6953#define regOTG1_OTG_DRR_V_TOTAL_REACH_RANGE 0x1c16 6954#define regOTG1_OTG_DRR_V_TOTAL_REACH_RANGE_BASE_IDX 2 6955#define regOTG1_OTG_DRR_V_TOTAL_CHANGE 0x1c17 6956#define regOTG1_OTG_DRR_V_TOTAL_CHANGE_BASE_IDX 2 6957#define regOTG1_OTG_DRR_TRIGGER_WINDOW 0x1c18 6958#define regOTG1_OTG_DRR_TRIGGER_WINDOW_BASE_IDX 2 6959#define regOTG1_OTG_DRR_CONTROL 0x1c19 6960#define regOTG1_OTG_DRR_CONTROL_BASE_IDX 2 6961#define regOTG1_OTG_DRR_CONTOL2 0x1c1a 6962#define regOTG1_OTG_DRR_CONTOL2_BASE_IDX 2 6963#define regOTG1_OTG_M_CONST_DTO0 0x1c1b 6964#define regOTG1_OTG_M_CONST_DTO0_BASE_IDX 2 6965#define regOTG1_OTG_M_CONST_DTO1 0x1c1c 6966#define regOTG1_OTG_M_CONST_DTO1_BASE_IDX 2 6967#define regOTG1_OTG_REQUEST_CONTROL 0x1c1d 6968#define regOTG1_OTG_REQUEST_CONTROL_BASE_IDX 2 6969#define regOTG1_OTG_DSC_START_POSITION 0x1c1e 6970#define regOTG1_OTG_DSC_START_POSITION_BASE_IDX 2 6971#define regOTG1_OTG_PIPE_UPDATE_STATUS 0x1c1f 6972#define regOTG1_OTG_PIPE_UPDATE_STATUS_BASE_IDX 2 6973#define regOTG1_OTG_SPARE_REGISTER 0x1c20 6974#define regOTG1_OTG_SPARE_REGISTER_BASE_IDX 2 6975 6976 6977// addressBlock: dce_dc_optc_otg2_dispdec 6978// base address: 0x400 6979#define regOTG2_OTG_H_TOTAL 0x1c2a 6980#define regOTG2_OTG_H_TOTAL_BASE_IDX 2 6981#define regOTG2_OTG_H_BLANK_START_END 0x1c2b 6982#define regOTG2_OTG_H_BLANK_START_END_BASE_IDX 2 6983#define regOTG2_OTG_H_SYNC_A 0x1c2c 6984#define regOTG2_OTG_H_SYNC_A_BASE_IDX 2 6985#define regOTG2_OTG_H_SYNC_A_CNTL 0x1c2d 6986#define regOTG2_OTG_H_SYNC_A_CNTL_BASE_IDX 2 6987#define regOTG2_OTG_H_TIMING_CNTL 0x1c2e 6988#define regOTG2_OTG_H_TIMING_CNTL_BASE_IDX 2 6989#define regOTG2_OTG_V_TOTAL 0x1c2f 6990#define regOTG2_OTG_V_TOTAL_BASE_IDX 2 6991#define regOTG2_OTG_V_TOTAL_MIN 0x1c30 6992#define regOTG2_OTG_V_TOTAL_MIN_BASE_IDX 2 6993#define regOTG2_OTG_V_TOTAL_MAX 0x1c31 6994#define regOTG2_OTG_V_TOTAL_MAX_BASE_IDX 2 6995#define regOTG2_OTG_V_TOTAL_MID 0x1c32 6996#define regOTG2_OTG_V_TOTAL_MID_BASE_IDX 2 6997#define regOTG2_OTG_V_TOTAL_CONTROL 0x1c33 6998#define regOTG2_OTG_V_TOTAL_CONTROL_BASE_IDX 2 6999#define regOTG2_OTG_V_COUNT_STOP_CONTROL 0x1c34 7000#define regOTG2_OTG_V_COUNT_STOP_CONTROL_BASE_IDX 2 7001#define regOTG2_OTG_V_COUNT_STOP_CONTROL2 0x1c35 7002#define regOTG2_OTG_V_COUNT_STOP_CONTROL2_BASE_IDX 2 7003#define regOTG2_OTG_V_TOTAL_INT_STATUS 0x1c36 7004#define regOTG2_OTG_V_TOTAL_INT_STATUS_BASE_IDX 2 7005#define regOTG2_OTG_VSYNC_NOM_INT_STATUS 0x1c37 7006#define regOTG2_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX 2 7007#define regOTG2_OTG_V_BLANK_START_END 0x1c38 7008#define regOTG2_OTG_V_BLANK_START_END_BASE_IDX 2 7009#define regOTG2_OTG_V_SYNC_A 0x1c39 7010#define regOTG2_OTG_V_SYNC_A_BASE_IDX 2 7011#define regOTG2_OTG_V_SYNC_A_CNTL 0x1c3a 7012#define regOTG2_OTG_V_SYNC_A_CNTL_BASE_IDX 2 7013#define regOTG2_OTG_TRIGA_CNTL 0x1c3b 7014#define regOTG2_OTG_TRIGA_CNTL_BASE_IDX 2 7015#define regOTG2_OTG_TRIGA_MANUAL_TRIG 0x1c3c 7016#define regOTG2_OTG_TRIGA_MANUAL_TRIG_BASE_IDX 2 7017#define regOTG2_OTG_TRIGB_CNTL 0x1c3d 7018#define regOTG2_OTG_TRIGB_CNTL_BASE_IDX 2 7019#define regOTG2_OTG_TRIGB_MANUAL_TRIG 0x1c3e 7020#define regOTG2_OTG_TRIGB_MANUAL_TRIG_BASE_IDX 2 7021#define regOTG2_OTG_FORCE_COUNT_NOW_CNTL 0x1c3f 7022#define regOTG2_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX 2 7023#define regOTG2_OTG_STEREO_FORCE_NEXT_EYE 0x1c41 7024#define regOTG2_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX 2 7025#define regOTG2_OTG_CONTROL 0x1c43 7026#define regOTG2_OTG_CONTROL_BASE_IDX 2 7027#define regOTG2_OTG_DLPC_CONTROL 0x1c44 7028#define regOTG2_OTG_DLPC_CONTROL_BASE_IDX 2 7029#define regOTG2_OTG_INTERLACE_CONTROL 0x1c45 7030#define regOTG2_OTG_INTERLACE_CONTROL_BASE_IDX 2 7031#define regOTG2_OTG_INTERLACE_STATUS 0x1c46 7032#define regOTG2_OTG_INTERLACE_STATUS_BASE_IDX 2 7033#define regOTG2_OTG_PIXEL_DATA_READBACK0 0x1c47 7034#define regOTG2_OTG_PIXEL_DATA_READBACK0_BASE_IDX 2 7035#define regOTG2_OTG_PIXEL_DATA_READBACK1 0x1c48 7036#define regOTG2_OTG_PIXEL_DATA_READBACK1_BASE_IDX 2 7037#define regOTG2_OTG_STATUS 0x1c49 7038#define regOTG2_OTG_STATUS_BASE_IDX 2 7039#define regOTG2_OTG_STATUS_POSITION 0x1c4a 7040#define regOTG2_OTG_STATUS_POSITION_BASE_IDX 2 7041#define regOTG2_OTG_LONG_VBLANK_STATUS 0x1c4b 7042#define regOTG2_OTG_LONG_VBLANK_STATUS_BASE_IDX 2 7043#define regOTG2_OTG_NOM_VERT_POSITION 0x1c4c 7044#define regOTG2_OTG_NOM_VERT_POSITION_BASE_IDX 2 7045#define regOTG2_OTG_STATUS_FRAME_COUNT 0x1c4d 7046#define regOTG2_OTG_STATUS_FRAME_COUNT_BASE_IDX 2 7047#define regOTG2_OTG_STATUS_VF_COUNT 0x1c4e 7048#define regOTG2_OTG_STATUS_VF_COUNT_BASE_IDX 2 7049#define regOTG2_OTG_STATUS_HV_COUNT 0x1c4f 7050#define regOTG2_OTG_STATUS_HV_COUNT_BASE_IDX 2 7051#define regOTG2_OTG_COUNT_CONTROL 0x1c50 7052#define regOTG2_OTG_COUNT_CONTROL_BASE_IDX 2 7053#define regOTG2_OTG_COUNT_RESET 0x1c51 7054#define regOTG2_OTG_COUNT_RESET_BASE_IDX 2 7055#define regOTG2_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1c52 7056#define regOTG2_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2 7057#define regOTG2_OTG_VERT_SYNC_CONTROL 0x1c53 7058#define regOTG2_OTG_VERT_SYNC_CONTROL_BASE_IDX 2 7059#define regOTG2_OTG_STEREO_STATUS 0x1c54 7060#define regOTG2_OTG_STEREO_STATUS_BASE_IDX 2 7061#define regOTG2_OTG_STEREO_CONTROL 0x1c55 7062#define regOTG2_OTG_STEREO_CONTROL_BASE_IDX 2 7063#define regOTG2_OTG_SNAPSHOT_STATUS 0x1c56 7064#define regOTG2_OTG_SNAPSHOT_STATUS_BASE_IDX 2 7065#define regOTG2_OTG_SNAPSHOT_CONTROL 0x1c57 7066#define regOTG2_OTG_SNAPSHOT_CONTROL_BASE_IDX 2 7067#define regOTG2_OTG_SNAPSHOT_POSITION 0x1c58 7068#define regOTG2_OTG_SNAPSHOT_POSITION_BASE_IDX 2 7069#define regOTG2_OTG_SNAPSHOT_FRAME 0x1c59 7070#define regOTG2_OTG_SNAPSHOT_FRAME_BASE_IDX 2 7071#define regOTG2_OTG_INTERRUPT_CONTROL 0x1c5a 7072#define regOTG2_OTG_INTERRUPT_CONTROL_BASE_IDX 2 7073#define regOTG2_OTG_UPDATE_LOCK 0x1c5b 7074#define regOTG2_OTG_UPDATE_LOCK_BASE_IDX 2 7075#define regOTG2_OTG_DOUBLE_BUFFER_CONTROL 0x1c5c 7076#define regOTG2_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 7077#define regOTG2_OTG_MASTER_EN 0x1c5d 7078#define regOTG2_OTG_MASTER_EN_BASE_IDX 2 7079#define regOTG2_OTG_VERTICAL_INTERRUPT0_POSITION 0x1c5f 7080#define regOTG2_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2 7081#define regOTG2_OTG_VERTICAL_INTERRUPT0_CONTROL 0x1c60 7082#define regOTG2_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2 7083#define regOTG2_OTG_VERTICAL_INTERRUPT1_POSITION 0x1c61 7084#define regOTG2_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2 7085#define regOTG2_OTG_VERTICAL_INTERRUPT1_CONTROL 0x1c62 7086#define regOTG2_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2 7087#define regOTG2_OTG_VERTICAL_INTERRUPT2_POSITION 0x1c63 7088#define regOTG2_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2 7089#define regOTG2_OTG_VERTICAL_INTERRUPT2_CONTROL 0x1c64 7090#define regOTG2_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2 7091#define regOTG2_OTG_CRC_CNTL 0x1c65 7092#define regOTG2_OTG_CRC_CNTL_BASE_IDX 2 7093#define regOTG2_OTG_CRC0_WINDOWA_X_CONTROL 0x1c66 7094#define regOTG2_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2 7095#define regOTG2_OTG_CRC0_WINDOWA_Y_CONTROL 0x1c67 7096#define regOTG2_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2 7097#define regOTG2_OTG_CRC0_WINDOWB_X_CONTROL 0x1c68 7098#define regOTG2_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2 7099#define regOTG2_OTG_CRC0_WINDOWB_Y_CONTROL 0x1c69 7100#define regOTG2_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2 7101#define regOTG2_OTG_CRC0_DATA_RG 0x1c6a 7102#define regOTG2_OTG_CRC0_DATA_RG_BASE_IDX 2 7103#define regOTG2_OTG_CRC0_DATA_B 0x1c6b 7104#define regOTG2_OTG_CRC0_DATA_B_BASE_IDX 2 7105#define regOTG2_OTG_CRC1_WINDOWA_X_CONTROL 0x1c6c 7106#define regOTG2_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2 7107#define regOTG2_OTG_CRC1_WINDOWA_Y_CONTROL 0x1c6d 7108#define regOTG2_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2 7109#define regOTG2_OTG_CRC1_WINDOWB_X_CONTROL 0x1c6e 7110#define regOTG2_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2 7111#define regOTG2_OTG_CRC1_WINDOWB_Y_CONTROL 0x1c6f 7112#define regOTG2_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2 7113#define regOTG2_OTG_CRC1_DATA_RG 0x1c70 7114#define regOTG2_OTG_CRC1_DATA_RG_BASE_IDX 2 7115#define regOTG2_OTG_CRC1_DATA_B 0x1c71 7116#define regOTG2_OTG_CRC1_DATA_B_BASE_IDX 2 7117#define regOTG2_OTG_CRC2_DATA_RG 0x1c72 7118#define regOTG2_OTG_CRC2_DATA_RG_BASE_IDX 2 7119#define regOTG2_OTG_CRC2_DATA_B 0x1c73 7120#define regOTG2_OTG_CRC2_DATA_B_BASE_IDX 2 7121#define regOTG2_OTG_CRC3_DATA_RG 0x1c74 7122#define regOTG2_OTG_CRC3_DATA_RG_BASE_IDX 2 7123#define regOTG2_OTG_CRC3_DATA_B 0x1c75 7124#define regOTG2_OTG_CRC3_DATA_B_BASE_IDX 2 7125#define regOTG2_OTG_CRC_SIG_RED_GREEN_MASK 0x1c76 7126#define regOTG2_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2 7127#define regOTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK 0x1c77 7128#define regOTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2 7129#define regOTG2_OTG_CRC0_WINDOWA_X_CONTROL_READBACK 0x1c78 7130#define regOTG2_OTG_CRC0_WINDOWA_X_CONTROL_READBACK_BASE_IDX 2 7131#define regOTG2_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK 0x1c79 7132#define regOTG2_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK_BASE_IDX 2 7133#define regOTG2_OTG_CRC0_WINDOWB_X_CONTROL_READBACK 0x1c7a 7134#define regOTG2_OTG_CRC0_WINDOWB_X_CONTROL_READBACK_BASE_IDX 2 7135#define regOTG2_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK 0x1c7b 7136#define regOTG2_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK_BASE_IDX 2 7137#define regOTG2_OTG_CRC1_WINDOWA_X_CONTROL_READBACK 0x1c7c 7138#define regOTG2_OTG_CRC1_WINDOWA_X_CONTROL_READBACK_BASE_IDX 2 7139#define regOTG2_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK 0x1c7d 7140#define regOTG2_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK_BASE_IDX 2 7141#define regOTG2_OTG_CRC1_WINDOWB_X_CONTROL_READBACK 0x1c7e 7142#define regOTG2_OTG_CRC1_WINDOWB_X_CONTROL_READBACK_BASE_IDX 2 7143#define regOTG2_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK 0x1c7f 7144#define regOTG2_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK_BASE_IDX 2 7145#define regOTG2_OTG_STATIC_SCREEN_CONTROL 0x1c80 7146#define regOTG2_OTG_STATIC_SCREEN_CONTROL_BASE_IDX 2 7147#define regOTG2_OTG_3D_STRUCTURE_CONTROL 0x1c81 7148#define regOTG2_OTG_3D_STRUCTURE_CONTROL_BASE_IDX 2 7149#define regOTG2_OTG_GSL_VSYNC_GAP 0x1c82 7150#define regOTG2_OTG_GSL_VSYNC_GAP_BASE_IDX 2 7151#define regOTG2_OTG_MASTER_UPDATE_MODE 0x1c83 7152#define regOTG2_OTG_MASTER_UPDATE_MODE_BASE_IDX 2 7153#define regOTG2_OTG_CLOCK_CONTROL 0x1c84 7154#define regOTG2_OTG_CLOCK_CONTROL_BASE_IDX 2 7155#define regOTG2_OTG_VSTARTUP_PARAM 0x1c85 7156#define regOTG2_OTG_VSTARTUP_PARAM_BASE_IDX 2 7157#define regOTG2_OTG_VUPDATE_PARAM 0x1c86 7158#define regOTG2_OTG_VUPDATE_PARAM_BASE_IDX 2 7159#define regOTG2_OTG_VREADY_PARAM 0x1c87 7160#define regOTG2_OTG_VREADY_PARAM_BASE_IDX 2 7161#define regOTG2_OTG_GLOBAL_SYNC_STATUS 0x1c88 7162#define regOTG2_OTG_GLOBAL_SYNC_STATUS_BASE_IDX 2 7163#define regOTG2_OTG_MASTER_UPDATE_LOCK 0x1c89 7164#define regOTG2_OTG_MASTER_UPDATE_LOCK_BASE_IDX 2 7165#define regOTG2_OTG_GSL_CONTROL 0x1c8a 7166#define regOTG2_OTG_GSL_CONTROL_BASE_IDX 2 7167#define regOTG2_OTG_GSL_WINDOW_X 0x1c8b 7168#define regOTG2_OTG_GSL_WINDOW_X_BASE_IDX 2 7169#define regOTG2_OTG_GSL_WINDOW_Y 0x1c8c 7170#define regOTG2_OTG_GSL_WINDOW_Y_BASE_IDX 2 7171#define regOTG2_OTG_VUPDATE_KEEPOUT 0x1c8d 7172#define regOTG2_OTG_VUPDATE_KEEPOUT_BASE_IDX 2 7173#define regOTG2_OTG_GLOBAL_CONTROL0 0x1c8e 7174#define regOTG2_OTG_GLOBAL_CONTROL0_BASE_IDX 2 7175#define regOTG2_OTG_GLOBAL_CONTROL1 0x1c8f 7176#define regOTG2_OTG_GLOBAL_CONTROL1_BASE_IDX 2 7177#define regOTG2_OTG_GLOBAL_CONTROL2 0x1c90 7178#define regOTG2_OTG_GLOBAL_CONTROL2_BASE_IDX 2 7179#define regOTG2_OTG_GLOBAL_CONTROL3 0x1c91 7180#define regOTG2_OTG_GLOBAL_CONTROL3_BASE_IDX 2 7181#define regOTG2_OTG_GLOBAL_CONTROL4 0x1c92 7182#define regOTG2_OTG_GLOBAL_CONTROL4_BASE_IDX 2 7183#define regOTG2_OTG_TRIG_MANUAL_CONTROL 0x1c93 7184#define regOTG2_OTG_TRIG_MANUAL_CONTROL_BASE_IDX 2 7185#define regOTG2_OTG_DRR_TIMING_INT_STATUS 0x1c95 7186#define regOTG2_OTG_DRR_TIMING_INT_STATUS_BASE_IDX 2 7187#define regOTG2_OTG_DRR_V_TOTAL_REACH_RANGE 0x1c96 7188#define regOTG2_OTG_DRR_V_TOTAL_REACH_RANGE_BASE_IDX 2 7189#define regOTG2_OTG_DRR_V_TOTAL_CHANGE 0x1c97 7190#define regOTG2_OTG_DRR_V_TOTAL_CHANGE_BASE_IDX 2 7191#define regOTG2_OTG_DRR_TRIGGER_WINDOW 0x1c98 7192#define regOTG2_OTG_DRR_TRIGGER_WINDOW_BASE_IDX 2 7193#define regOTG2_OTG_DRR_CONTROL 0x1c99 7194#define regOTG2_OTG_DRR_CONTROL_BASE_IDX 2 7195#define regOTG2_OTG_DRR_CONTOL2 0x1c9a 7196#define regOTG2_OTG_DRR_CONTOL2_BASE_IDX 2 7197#define regOTG2_OTG_M_CONST_DTO0 0x1c9b 7198#define regOTG2_OTG_M_CONST_DTO0_BASE_IDX 2 7199#define regOTG2_OTG_M_CONST_DTO1 0x1c9c 7200#define regOTG2_OTG_M_CONST_DTO1_BASE_IDX 2 7201#define regOTG2_OTG_REQUEST_CONTROL 0x1c9d 7202#define regOTG2_OTG_REQUEST_CONTROL_BASE_IDX 2 7203#define regOTG2_OTG_DSC_START_POSITION 0x1c9e 7204#define regOTG2_OTG_DSC_START_POSITION_BASE_IDX 2 7205#define regOTG2_OTG_PIPE_UPDATE_STATUS 0x1c9f 7206#define regOTG2_OTG_PIPE_UPDATE_STATUS_BASE_IDX 2 7207#define regOTG2_OTG_SPARE_REGISTER 0x1ca0 7208#define regOTG2_OTG_SPARE_REGISTER_BASE_IDX 2 7209 7210 7211// addressBlock: dce_dc_optc_otg3_dispdec 7212// base address: 0x600 7213#define regOTG3_OTG_H_TOTAL 0x1caa 7214#define regOTG3_OTG_H_TOTAL_BASE_IDX 2 7215#define regOTG3_OTG_H_BLANK_START_END 0x1cab 7216#define regOTG3_OTG_H_BLANK_START_END_BASE_IDX 2 7217#define regOTG3_OTG_H_SYNC_A 0x1cac 7218#define regOTG3_OTG_H_SYNC_A_BASE_IDX 2 7219#define regOTG3_OTG_H_SYNC_A_CNTL 0x1cad 7220#define regOTG3_OTG_H_SYNC_A_CNTL_BASE_IDX 2 7221#define regOTG3_OTG_H_TIMING_CNTL 0x1cae 7222#define regOTG3_OTG_H_TIMING_CNTL_BASE_IDX 2 7223#define regOTG3_OTG_V_TOTAL 0x1caf 7224#define regOTG3_OTG_V_TOTAL_BASE_IDX 2 7225#define regOTG3_OTG_V_TOTAL_MIN 0x1cb0 7226#define regOTG3_OTG_V_TOTAL_MIN_BASE_IDX 2 7227#define regOTG3_OTG_V_TOTAL_MAX 0x1cb1 7228#define regOTG3_OTG_V_TOTAL_MAX_BASE_IDX 2 7229#define regOTG3_OTG_V_TOTAL_MID 0x1cb2 7230#define regOTG3_OTG_V_TOTAL_MID_BASE_IDX 2 7231#define regOTG3_OTG_V_TOTAL_CONTROL 0x1cb3 7232#define regOTG3_OTG_V_TOTAL_CONTROL_BASE_IDX 2 7233#define regOTG3_OTG_V_COUNT_STOP_CONTROL 0x1cb4 7234#define regOTG3_OTG_V_COUNT_STOP_CONTROL_BASE_IDX 2 7235#define regOTG3_OTG_V_COUNT_STOP_CONTROL2 0x1cb5 7236#define regOTG3_OTG_V_COUNT_STOP_CONTROL2_BASE_IDX 2 7237#define regOTG3_OTG_V_TOTAL_INT_STATUS 0x1cb6 7238#define regOTG3_OTG_V_TOTAL_INT_STATUS_BASE_IDX 2 7239#define regOTG3_OTG_VSYNC_NOM_INT_STATUS 0x1cb7 7240#define regOTG3_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX 2 7241#define regOTG3_OTG_V_BLANK_START_END 0x1cb8 7242#define regOTG3_OTG_V_BLANK_START_END_BASE_IDX 2 7243#define regOTG3_OTG_V_SYNC_A 0x1cb9 7244#define regOTG3_OTG_V_SYNC_A_BASE_IDX 2 7245#define regOTG3_OTG_V_SYNC_A_CNTL 0x1cba 7246#define regOTG3_OTG_V_SYNC_A_CNTL_BASE_IDX 2 7247#define regOTG3_OTG_TRIGA_CNTL 0x1cbb 7248#define regOTG3_OTG_TRIGA_CNTL_BASE_IDX 2 7249#define regOTG3_OTG_TRIGA_MANUAL_TRIG 0x1cbc 7250#define regOTG3_OTG_TRIGA_MANUAL_TRIG_BASE_IDX 2 7251#define regOTG3_OTG_TRIGB_CNTL 0x1cbd 7252#define regOTG3_OTG_TRIGB_CNTL_BASE_IDX 2 7253#define regOTG3_OTG_TRIGB_MANUAL_TRIG 0x1cbe 7254#define regOTG3_OTG_TRIGB_MANUAL_TRIG_BASE_IDX 2 7255#define regOTG3_OTG_FORCE_COUNT_NOW_CNTL 0x1cbf 7256#define regOTG3_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX 2 7257#define regOTG3_OTG_STEREO_FORCE_NEXT_EYE 0x1cc1 7258#define regOTG3_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX 2 7259#define regOTG3_OTG_CONTROL 0x1cc3 7260#define regOTG3_OTG_CONTROL_BASE_IDX 2 7261#define regOTG3_OTG_DLPC_CONTROL 0x1cc4 7262#define regOTG3_OTG_DLPC_CONTROL_BASE_IDX 2 7263#define regOTG3_OTG_INTERLACE_CONTROL 0x1cc5 7264#define regOTG3_OTG_INTERLACE_CONTROL_BASE_IDX 2 7265#define regOTG3_OTG_INTERLACE_STATUS 0x1cc6 7266#define regOTG3_OTG_INTERLACE_STATUS_BASE_IDX 2 7267#define regOTG3_OTG_PIXEL_DATA_READBACK0 0x1cc7 7268#define regOTG3_OTG_PIXEL_DATA_READBACK0_BASE_IDX 2 7269#define regOTG3_OTG_PIXEL_DATA_READBACK1 0x1cc8 7270#define regOTG3_OTG_PIXEL_DATA_READBACK1_BASE_IDX 2 7271#define regOTG3_OTG_STATUS 0x1cc9 7272#define regOTG3_OTG_STATUS_BASE_IDX 2 7273#define regOTG3_OTG_STATUS_POSITION 0x1cca 7274#define regOTG3_OTG_STATUS_POSITION_BASE_IDX 2 7275#define regOTG3_OTG_LONG_VBLANK_STATUS 0x1ccb 7276#define regOTG3_OTG_LONG_VBLANK_STATUS_BASE_IDX 2 7277#define regOTG3_OTG_NOM_VERT_POSITION 0x1ccc 7278#define regOTG3_OTG_NOM_VERT_POSITION_BASE_IDX 2 7279#define regOTG3_OTG_STATUS_FRAME_COUNT 0x1ccd 7280#define regOTG3_OTG_STATUS_FRAME_COUNT_BASE_IDX 2 7281#define regOTG3_OTG_STATUS_VF_COUNT 0x1cce 7282#define regOTG3_OTG_STATUS_VF_COUNT_BASE_IDX 2 7283#define regOTG3_OTG_STATUS_HV_COUNT 0x1ccf 7284#define regOTG3_OTG_STATUS_HV_COUNT_BASE_IDX 2 7285#define regOTG3_OTG_COUNT_CONTROL 0x1cd0 7286#define regOTG3_OTG_COUNT_CONTROL_BASE_IDX 2 7287#define regOTG3_OTG_COUNT_RESET 0x1cd1 7288#define regOTG3_OTG_COUNT_RESET_BASE_IDX 2 7289#define regOTG3_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1cd2 7290#define regOTG3_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2 7291#define regOTG3_OTG_VERT_SYNC_CONTROL 0x1cd3 7292#define regOTG3_OTG_VERT_SYNC_CONTROL_BASE_IDX 2 7293#define regOTG3_OTG_STEREO_STATUS 0x1cd4 7294#define regOTG3_OTG_STEREO_STATUS_BASE_IDX 2 7295#define regOTG3_OTG_STEREO_CONTROL 0x1cd5 7296#define regOTG3_OTG_STEREO_CONTROL_BASE_IDX 2 7297#define regOTG3_OTG_SNAPSHOT_STATUS 0x1cd6 7298#define regOTG3_OTG_SNAPSHOT_STATUS_BASE_IDX 2 7299#define regOTG3_OTG_SNAPSHOT_CONTROL 0x1cd7 7300#define regOTG3_OTG_SNAPSHOT_CONTROL_BASE_IDX 2 7301#define regOTG3_OTG_SNAPSHOT_POSITION 0x1cd8 7302#define regOTG3_OTG_SNAPSHOT_POSITION_BASE_IDX 2 7303#define regOTG3_OTG_SNAPSHOT_FRAME 0x1cd9 7304#define regOTG3_OTG_SNAPSHOT_FRAME_BASE_IDX 2 7305#define regOTG3_OTG_INTERRUPT_CONTROL 0x1cda 7306#define regOTG3_OTG_INTERRUPT_CONTROL_BASE_IDX 2 7307#define regOTG3_OTG_UPDATE_LOCK 0x1cdb 7308#define regOTG3_OTG_UPDATE_LOCK_BASE_IDX 2 7309#define regOTG3_OTG_DOUBLE_BUFFER_CONTROL 0x1cdc 7310#define regOTG3_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 7311#define regOTG3_OTG_MASTER_EN 0x1cdd 7312#define regOTG3_OTG_MASTER_EN_BASE_IDX 2 7313#define regOTG3_OTG_VERTICAL_INTERRUPT0_POSITION 0x1cdf 7314#define regOTG3_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2 7315#define regOTG3_OTG_VERTICAL_INTERRUPT0_CONTROL 0x1ce0 7316#define regOTG3_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2 7317#define regOTG3_OTG_VERTICAL_INTERRUPT1_POSITION 0x1ce1 7318#define regOTG3_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2 7319#define regOTG3_OTG_VERTICAL_INTERRUPT1_CONTROL 0x1ce2 7320#define regOTG3_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2 7321#define regOTG3_OTG_VERTICAL_INTERRUPT2_POSITION 0x1ce3 7322#define regOTG3_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2 7323#define regOTG3_OTG_VERTICAL_INTERRUPT2_CONTROL 0x1ce4 7324#define regOTG3_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2 7325#define regOTG3_OTG_CRC_CNTL 0x1ce5 7326#define regOTG3_OTG_CRC_CNTL_BASE_IDX 2 7327#define regOTG3_OTG_CRC0_WINDOWA_X_CONTROL 0x1ce6 7328#define regOTG3_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2 7329#define regOTG3_OTG_CRC0_WINDOWA_Y_CONTROL 0x1ce7 7330#define regOTG3_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2 7331#define regOTG3_OTG_CRC0_WINDOWB_X_CONTROL 0x1ce8 7332#define regOTG3_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2 7333#define regOTG3_OTG_CRC0_WINDOWB_Y_CONTROL 0x1ce9 7334#define regOTG3_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2 7335#define regOTG3_OTG_CRC0_DATA_RG 0x1cea 7336#define regOTG3_OTG_CRC0_DATA_RG_BASE_IDX 2 7337#define regOTG3_OTG_CRC0_DATA_B 0x1ceb 7338#define regOTG3_OTG_CRC0_DATA_B_BASE_IDX 2 7339#define regOTG3_OTG_CRC1_WINDOWA_X_CONTROL 0x1cec 7340#define regOTG3_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2 7341#define regOTG3_OTG_CRC1_WINDOWA_Y_CONTROL 0x1ced 7342#define regOTG3_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2 7343#define regOTG3_OTG_CRC1_WINDOWB_X_CONTROL 0x1cee 7344#define regOTG3_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2 7345#define regOTG3_OTG_CRC1_WINDOWB_Y_CONTROL 0x1cef 7346#define regOTG3_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2 7347#define regOTG3_OTG_CRC1_DATA_RG 0x1cf0 7348#define regOTG3_OTG_CRC1_DATA_RG_BASE_IDX 2 7349#define regOTG3_OTG_CRC1_DATA_B 0x1cf1 7350#define regOTG3_OTG_CRC1_DATA_B_BASE_IDX 2 7351#define regOTG3_OTG_CRC2_DATA_RG 0x1cf2 7352#define regOTG3_OTG_CRC2_DATA_RG_BASE_IDX 2 7353#define regOTG3_OTG_CRC2_DATA_B 0x1cf3 7354#define regOTG3_OTG_CRC2_DATA_B_BASE_IDX 2 7355#define regOTG3_OTG_CRC3_DATA_RG 0x1cf4 7356#define regOTG3_OTG_CRC3_DATA_RG_BASE_IDX 2 7357#define regOTG3_OTG_CRC3_DATA_B 0x1cf5 7358#define regOTG3_OTG_CRC3_DATA_B_BASE_IDX 2 7359#define regOTG3_OTG_CRC_SIG_RED_GREEN_MASK 0x1cf6 7360#define regOTG3_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2 7361#define regOTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK 0x1cf7 7362#define regOTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2 7363#define regOTG3_OTG_CRC0_WINDOWA_X_CONTROL_READBACK 0x1cf8 7364#define regOTG3_OTG_CRC0_WINDOWA_X_CONTROL_READBACK_BASE_IDX 2 7365#define regOTG3_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK 0x1cf9 7366#define regOTG3_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK_BASE_IDX 2 7367#define regOTG3_OTG_CRC0_WINDOWB_X_CONTROL_READBACK 0x1cfa 7368#define regOTG3_OTG_CRC0_WINDOWB_X_CONTROL_READBACK_BASE_IDX 2 7369#define regOTG3_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK 0x1cfb 7370#define regOTG3_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK_BASE_IDX 2 7371#define regOTG3_OTG_CRC1_WINDOWA_X_CONTROL_READBACK 0x1cfc 7372#define regOTG3_OTG_CRC1_WINDOWA_X_CONTROL_READBACK_BASE_IDX 2 7373#define regOTG3_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK 0x1cfd 7374#define regOTG3_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK_BASE_IDX 2 7375#define regOTG3_OTG_CRC1_WINDOWB_X_CONTROL_READBACK 0x1cfe 7376#define regOTG3_OTG_CRC1_WINDOWB_X_CONTROL_READBACK_BASE_IDX 2 7377#define regOTG3_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK 0x1cff 7378#define regOTG3_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK_BASE_IDX 2 7379#define regOTG3_OTG_STATIC_SCREEN_CONTROL 0x1d00 7380#define regOTG3_OTG_STATIC_SCREEN_CONTROL_BASE_IDX 2 7381#define regOTG3_OTG_3D_STRUCTURE_CONTROL 0x1d01 7382#define regOTG3_OTG_3D_STRUCTURE_CONTROL_BASE_IDX 2 7383#define regOTG3_OTG_GSL_VSYNC_GAP 0x1d02 7384#define regOTG3_OTG_GSL_VSYNC_GAP_BASE_IDX 2 7385#define regOTG3_OTG_MASTER_UPDATE_MODE 0x1d03 7386#define regOTG3_OTG_MASTER_UPDATE_MODE_BASE_IDX 2 7387#define regOTG3_OTG_CLOCK_CONTROL 0x1d04 7388#define regOTG3_OTG_CLOCK_CONTROL_BASE_IDX 2 7389#define regOTG3_OTG_VSTARTUP_PARAM 0x1d05 7390#define regOTG3_OTG_VSTARTUP_PARAM_BASE_IDX 2 7391#define regOTG3_OTG_VUPDATE_PARAM 0x1d06 7392#define regOTG3_OTG_VUPDATE_PARAM_BASE_IDX 2 7393#define regOTG3_OTG_VREADY_PARAM 0x1d07 7394#define regOTG3_OTG_VREADY_PARAM_BASE_IDX 2 7395#define regOTG3_OTG_GLOBAL_SYNC_STATUS 0x1d08 7396#define regOTG3_OTG_GLOBAL_SYNC_STATUS_BASE_IDX 2 7397#define regOTG3_OTG_MASTER_UPDATE_LOCK 0x1d09 7398#define regOTG3_OTG_MASTER_UPDATE_LOCK_BASE_IDX 2 7399#define regOTG3_OTG_GSL_CONTROL 0x1d0a 7400#define regOTG3_OTG_GSL_CONTROL_BASE_IDX 2 7401#define regOTG3_OTG_GSL_WINDOW_X 0x1d0b 7402#define regOTG3_OTG_GSL_WINDOW_X_BASE_IDX 2 7403#define regOTG3_OTG_GSL_WINDOW_Y 0x1d0c 7404#define regOTG3_OTG_GSL_WINDOW_Y_BASE_IDX 2 7405#define regOTG3_OTG_VUPDATE_KEEPOUT 0x1d0d 7406#define regOTG3_OTG_VUPDATE_KEEPOUT_BASE_IDX 2 7407#define regOTG3_OTG_GLOBAL_CONTROL0 0x1d0e 7408#define regOTG3_OTG_GLOBAL_CONTROL0_BASE_IDX 2 7409#define regOTG3_OTG_GLOBAL_CONTROL1 0x1d0f 7410#define regOTG3_OTG_GLOBAL_CONTROL1_BASE_IDX 2 7411#define regOTG3_OTG_GLOBAL_CONTROL2 0x1d10 7412#define regOTG3_OTG_GLOBAL_CONTROL2_BASE_IDX 2 7413#define regOTG3_OTG_GLOBAL_CONTROL3 0x1d11 7414#define regOTG3_OTG_GLOBAL_CONTROL3_BASE_IDX 2 7415#define regOTG3_OTG_GLOBAL_CONTROL4 0x1d12 7416#define regOTG3_OTG_GLOBAL_CONTROL4_BASE_IDX 2 7417#define regOTG3_OTG_TRIG_MANUAL_CONTROL 0x1d13 7418#define regOTG3_OTG_TRIG_MANUAL_CONTROL_BASE_IDX 2 7419#define regOTG3_OTG_DRR_TIMING_INT_STATUS 0x1d15 7420#define regOTG3_OTG_DRR_TIMING_INT_STATUS_BASE_IDX 2 7421#define regOTG3_OTG_DRR_V_TOTAL_REACH_RANGE 0x1d16 7422#define regOTG3_OTG_DRR_V_TOTAL_REACH_RANGE_BASE_IDX 2 7423#define regOTG3_OTG_DRR_V_TOTAL_CHANGE 0x1d17 7424#define regOTG3_OTG_DRR_V_TOTAL_CHANGE_BASE_IDX 2 7425#define regOTG3_OTG_DRR_TRIGGER_WINDOW 0x1d18 7426#define regOTG3_OTG_DRR_TRIGGER_WINDOW_BASE_IDX 2 7427#define regOTG3_OTG_DRR_CONTROL 0x1d19 7428#define regOTG3_OTG_DRR_CONTROL_BASE_IDX 2 7429#define regOTG3_OTG_DRR_CONTOL2 0x1d1a 7430#define regOTG3_OTG_DRR_CONTOL2_BASE_IDX 2 7431#define regOTG3_OTG_M_CONST_DTO0 0x1d1b 7432#define regOTG3_OTG_M_CONST_DTO0_BASE_IDX 2 7433#define regOTG3_OTG_M_CONST_DTO1 0x1d1c 7434#define regOTG3_OTG_M_CONST_DTO1_BASE_IDX 2 7435#define regOTG3_OTG_REQUEST_CONTROL 0x1d1d 7436#define regOTG3_OTG_REQUEST_CONTROL_BASE_IDX 2 7437#define regOTG3_OTG_DSC_START_POSITION 0x1d1e 7438#define regOTG3_OTG_DSC_START_POSITION_BASE_IDX 2 7439#define regOTG3_OTG_PIPE_UPDATE_STATUS 0x1d1f 7440#define regOTG3_OTG_PIPE_UPDATE_STATUS_BASE_IDX 2 7441#define regOTG3_OTG_SPARE_REGISTER 0x1d20 7442#define regOTG3_OTG_SPARE_REGISTER_BASE_IDX 2 7443 7444 7445// addressBlock: dce_dc_optc_optc_misc_dispdec 7446// base address: 0x0 7447#define regGSL_SOURCE_SELECT 0x1e2b 7448#define regGSL_SOURCE_SELECT_BASE_IDX 2 7449#define regOPTC_DLPC_CONTROL 0x1e2c 7450#define regOPTC_DLPC_CONTROL_BASE_IDX 2 7451#define regOPTC_CLOCK_CONTROL 0x1e2d 7452#define regOPTC_CLOCK_CONTROL_BASE_IDX 2 7453#define regODM_MEM_PWR_CTRL 0x1e2e 7454#define regODM_MEM_PWR_CTRL_BASE_IDX 2 7455#define regODM_MEM_PWR_CTRL3 0x1e30 7456#define regODM_MEM_PWR_CTRL3_BASE_IDX 2 7457#define regODM_MEM_PWR_STATUS 0x1e31 7458#define regODM_MEM_PWR_STATUS_BASE_IDX 2 7459#define regOPTC_MISC_SPARE_REGISTER 0x1e32 7460#define regOPTC_MISC_SPARE_REGISTER_BASE_IDX 2 7461 7462 7463// addressBlock: dce_dc_optc_optc_dcperfmon_dc_perfmon_dispdec 7464// base address: 0x79a8 7465#define regDC_PERFMON17_PERFCOUNTER_CNTL 0x1e6a 7466#define regDC_PERFMON17_PERFCOUNTER_CNTL_BASE_IDX 2 7467#define regDC_PERFMON17_PERFCOUNTER_CNTL2 0x1e6b 7468#define regDC_PERFMON17_PERFCOUNTER_CNTL2_BASE_IDX 2 7469#define regDC_PERFMON17_PERFCOUNTER_STATE 0x1e6c 7470#define regDC_PERFMON17_PERFCOUNTER_STATE_BASE_IDX 2 7471#define regDC_PERFMON17_PERFMON_CNTL 0x1e6d 7472#define regDC_PERFMON17_PERFMON_CNTL_BASE_IDX 2 7473#define regDC_PERFMON17_PERFMON_CNTL2 0x1e6e 7474#define regDC_PERFMON17_PERFMON_CNTL2_BASE_IDX 2 7475#define regDC_PERFMON17_PERFMON_CVALUE_INT_MISC 0x1e6f 7476#define regDC_PERFMON17_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 7477#define regDC_PERFMON17_PERFMON_CVALUE_LOW 0x1e70 7478#define regDC_PERFMON17_PERFMON_CVALUE_LOW_BASE_IDX 2 7479#define regDC_PERFMON17_PERFMON_HI 0x1e71 7480#define regDC_PERFMON17_PERFMON_HI_BASE_IDX 2 7481#define regDC_PERFMON17_PERFMON_LOW 0x1e72 7482#define regDC_PERFMON17_PERFMON_LOW_BASE_IDX 2 7483 7484 7485// addressBlock: dce_dc_dio_dout_i2c_dispdec 7486// base address: 0x0 7487#define regDC_I2C_CONTROL 0x1e98 7488#define regDC_I2C_CONTROL_BASE_IDX 2 7489#define regDC_I2C_ARBITRATION 0x1e99 7490#define regDC_I2C_ARBITRATION_BASE_IDX 2 7491#define regDC_I2C_INTERRUPT_CONTROL 0x1e9a 7492#define regDC_I2C_INTERRUPT_CONTROL_BASE_IDX 2 7493#define regDC_I2C_SW_STATUS 0x1e9b 7494#define regDC_I2C_SW_STATUS_BASE_IDX 2 7495#define regDC_I2C_DDC1_HW_STATUS 0x1e9c 7496#define regDC_I2C_DDC1_HW_STATUS_BASE_IDX 2 7497#define regDC_I2C_DDC2_HW_STATUS 0x1e9d 7498#define regDC_I2C_DDC2_HW_STATUS_BASE_IDX 2 7499#define regDC_I2C_DDC3_HW_STATUS 0x1e9e 7500#define regDC_I2C_DDC3_HW_STATUS_BASE_IDX 2 7501#define regDC_I2C_DDC4_HW_STATUS 0x1e9f 7502#define regDC_I2C_DDC4_HW_STATUS_BASE_IDX 2 7503#define regDC_I2C_DDC5_HW_STATUS 0x1ea0 7504#define regDC_I2C_DDC5_HW_STATUS_BASE_IDX 2 7505#define regDC_I2C_DDC1_SPEED 0x1ea2 7506#define regDC_I2C_DDC1_SPEED_BASE_IDX 2 7507#define regDC_I2C_DDC1_SETUP 0x1ea3 7508#define regDC_I2C_DDC1_SETUP_BASE_IDX 2 7509#define regDC_I2C_DDC2_SPEED 0x1ea4 7510#define regDC_I2C_DDC2_SPEED_BASE_IDX 2 7511#define regDC_I2C_DDC2_SETUP 0x1ea5 7512#define regDC_I2C_DDC2_SETUP_BASE_IDX 2 7513#define regDC_I2C_DDC3_SPEED 0x1ea6 7514#define regDC_I2C_DDC3_SPEED_BASE_IDX 2 7515#define regDC_I2C_DDC3_SETUP 0x1ea7 7516#define regDC_I2C_DDC3_SETUP_BASE_IDX 2 7517#define regDC_I2C_DDC4_SPEED 0x1ea8 7518#define regDC_I2C_DDC4_SPEED_BASE_IDX 2 7519#define regDC_I2C_DDC4_SETUP 0x1ea9 7520#define regDC_I2C_DDC4_SETUP_BASE_IDX 2 7521#define regDC_I2C_DDC5_SPEED 0x1eaa 7522#define regDC_I2C_DDC5_SPEED_BASE_IDX 2 7523#define regDC_I2C_DDC5_SETUP 0x1eab 7524#define regDC_I2C_DDC5_SETUP_BASE_IDX 2 7525#define regDC_I2C_TRANSACTION0 0x1eae 7526#define regDC_I2C_TRANSACTION0_BASE_IDX 2 7527#define regDC_I2C_TRANSACTION1 0x1eaf 7528#define regDC_I2C_TRANSACTION1_BASE_IDX 2 7529#define regDC_I2C_TRANSACTION2 0x1eb0 7530#define regDC_I2C_TRANSACTION2_BASE_IDX 2 7531#define regDC_I2C_TRANSACTION3 0x1eb1 7532#define regDC_I2C_TRANSACTION3_BASE_IDX 2 7533#define regDC_I2C_DATA 0x1eb2 7534#define regDC_I2C_DATA_BASE_IDX 2 7535#define regDC_I2C_EDID_DETECT_CTRL 0x1eb6 7536#define regDC_I2C_EDID_DETECT_CTRL_BASE_IDX 2 7537#define regDC_I2C_READ_REQUEST_INTERRUPT 0x1eb7 7538#define regDC_I2C_READ_REQUEST_INTERRUPT_BASE_IDX 2 7539 7540 7541// addressBlock: dce_dc_dio_dio_misc_dispdec 7542// base address: 0x0 7543#define regDIO_DCN_STATUS 0x1ec3 7544#define regDIO_DCN_STATUS_BASE_IDX 2 7545#define regDIO_SCRATCH0 0x1eca 7546#define regDIO_SCRATCH0_BASE_IDX 2 7547#define regDIO_SCRATCH1 0x1ecb 7548#define regDIO_SCRATCH1_BASE_IDX 2 7549#define regDIO_SCRATCH2 0x1ecc 7550#define regDIO_SCRATCH2_BASE_IDX 2 7551#define regDIO_SCRATCH3 0x1ecd 7552#define regDIO_SCRATCH3_BASE_IDX 2 7553#define regDIO_SCRATCH4 0x1ece 7554#define regDIO_SCRATCH4_BASE_IDX 2 7555#define regDIO_SCRATCH5 0x1ecf 7556#define regDIO_SCRATCH5_BASE_IDX 2 7557#define regDIO_SCRATCH6 0x1ed0 7558#define regDIO_SCRATCH6_BASE_IDX 2 7559#define regDIO_SCRATCH7 0x1ed1 7560#define regDIO_SCRATCH7_BASE_IDX 2 7561#define regDIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS 0x1ed3 7562#define regDIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS_BASE_IDX 2 7563#define regDIO_MEM_PWR_STATUS 0x1edd 7564#define regDIO_MEM_PWR_STATUS_BASE_IDX 2 7565#define regDIO_MEM_PWR_CTRL 0x1ede 7566#define regDIO_MEM_PWR_CTRL_BASE_IDX 2 7567#define regDIO_MEM_PWR_CTRL2 0x1edf 7568#define regDIO_MEM_PWR_CTRL2_BASE_IDX 2 7569#define regDIO_CLK_CNTL 0x1ee0 7570#define regDIO_CLK_CNTL_BASE_IDX 2 7571#define regDIO_POWER_MANAGEMENT_CNTL 0x1ee4 7572#define regDIO_POWER_MANAGEMENT_CNTL_BASE_IDX 2 7573#define regDIO_HDMI_RXSTATUS_TIMER_CONTROL 0x1eff 7574#define regDIO_HDMI_RXSTATUS_TIMER_CONTROL_BASE_IDX 2 7575#define regDIO_PSP_INTERRUPT_STATUS 0x1f00 7576#define regDIO_PSP_INTERRUPT_STATUS_BASE_IDX 2 7577#define regDIO_PSP_INTERRUPT_CLEAR 0x1f01 7578#define regDIO_PSP_INTERRUPT_CLEAR_BASE_IDX 2 7579#define regDIO_STATUS 0x1f02 7580#define regDIO_STATUS_BASE_IDX 2 7581#define regDIO_LINKA_CNTL 0x1f04 7582#define regDIO_LINKA_CNTL_BASE_IDX 2 7583#define regDIO_LINKB_CNTL 0x1f05 7584#define regDIO_LINKB_CNTL_BASE_IDX 2 7585#define regDIO_LINKC_CNTL 0x1f06 7586#define regDIO_LINKC_CNTL_BASE_IDX 2 7587#define regDIO_LINKD_CNTL 0x1f07 7588#define regDIO_LINKD_CNTL_BASE_IDX 2 7589#define regDIO_LINKE_CNTL 0x1f08 7590#define regDIO_LINKE_CNTL_BASE_IDX 2 7591#define regDIO_LINKF_CNTL 0x1f09 7592#define regDIO_LINKF_CNTL_BASE_IDX 2 7593 7594 7595// addressBlock: dce_dc_dio_hpd0_dispdec 7596// base address: 0x0 7597#define regHPD0_DC_HPD_INT_STATUS 0x1f14 7598#define regHPD0_DC_HPD_INT_STATUS_BASE_IDX 2 7599#define regHPD0_DC_HPD_INT_CONTROL 0x1f15 7600#define regHPD0_DC_HPD_INT_CONTROL_BASE_IDX 2 7601#define regHPD0_DC_HPD_CONTROL 0x1f16 7602#define regHPD0_DC_HPD_CONTROL_BASE_IDX 2 7603#define regHPD0_DC_HPD_FAST_TRAIN_CNTL 0x1f17 7604#define regHPD0_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2 7605#define regHPD0_DC_HPD_TOGGLE_FILT_CNTL 0x1f18 7606#define regHPD0_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2 7607 7608 7609// addressBlock: dce_dc_dio_hpd1_dispdec 7610// base address: 0x20 7611#define regHPD1_DC_HPD_INT_STATUS 0x1f1c 7612#define regHPD1_DC_HPD_INT_STATUS_BASE_IDX 2 7613#define regHPD1_DC_HPD_INT_CONTROL 0x1f1d 7614#define regHPD1_DC_HPD_INT_CONTROL_BASE_IDX 2 7615#define regHPD1_DC_HPD_CONTROL 0x1f1e 7616#define regHPD1_DC_HPD_CONTROL_BASE_IDX 2 7617#define regHPD1_DC_HPD_FAST_TRAIN_CNTL 0x1f1f 7618#define regHPD1_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2 7619#define regHPD1_DC_HPD_TOGGLE_FILT_CNTL 0x1f20 7620#define regHPD1_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2 7621 7622 7623// addressBlock: dce_dc_dio_hpd2_dispdec 7624// base address: 0x40 7625#define regHPD2_DC_HPD_INT_STATUS 0x1f24 7626#define regHPD2_DC_HPD_INT_STATUS_BASE_IDX 2 7627#define regHPD2_DC_HPD_INT_CONTROL 0x1f25 7628#define regHPD2_DC_HPD_INT_CONTROL_BASE_IDX 2 7629#define regHPD2_DC_HPD_CONTROL 0x1f26 7630#define regHPD2_DC_HPD_CONTROL_BASE_IDX 2 7631#define regHPD2_DC_HPD_FAST_TRAIN_CNTL 0x1f27 7632#define regHPD2_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2 7633#define regHPD2_DC_HPD_TOGGLE_FILT_CNTL 0x1f28 7634#define regHPD2_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2 7635 7636 7637// addressBlock: dce_dc_dio_hpd3_dispdec 7638// base address: 0x60 7639#define regHPD3_DC_HPD_INT_STATUS 0x1f2c 7640#define regHPD3_DC_HPD_INT_STATUS_BASE_IDX 2 7641#define regHPD3_DC_HPD_INT_CONTROL 0x1f2d 7642#define regHPD3_DC_HPD_INT_CONTROL_BASE_IDX 2 7643#define regHPD3_DC_HPD_CONTROL 0x1f2e 7644#define regHPD3_DC_HPD_CONTROL_BASE_IDX 2 7645#define regHPD3_DC_HPD_FAST_TRAIN_CNTL 0x1f2f 7646#define regHPD3_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2 7647#define regHPD3_DC_HPD_TOGGLE_FILT_CNTL 0x1f30 7648#define regHPD3_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2 7649 7650 7651// addressBlock: dce_dc_dio_hpd4_dispdec 7652// base address: 0x80 7653#define regHPD4_DC_HPD_INT_STATUS 0x1f34 7654#define regHPD4_DC_HPD_INT_STATUS_BASE_IDX 2 7655#define regHPD4_DC_HPD_INT_CONTROL 0x1f35 7656#define regHPD4_DC_HPD_INT_CONTROL_BASE_IDX 2 7657#define regHPD4_DC_HPD_CONTROL 0x1f36 7658#define regHPD4_DC_HPD_CONTROL_BASE_IDX 2 7659#define regHPD4_DC_HPD_FAST_TRAIN_CNTL 0x1f37 7660#define regHPD4_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2 7661#define regHPD4_DC_HPD_TOGGLE_FILT_CNTL 0x1f38 7662#define regHPD4_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2 7663 7664 7665// addressBlock: dce_dc_dio_dio_dcperfmon_dc_perfmon_dispdec 7666// base address: 0x7d10 7667#define regDC_PERFMON18_PERFCOUNTER_CNTL 0x1f44 7668#define regDC_PERFMON18_PERFCOUNTER_CNTL_BASE_IDX 2 7669#define regDC_PERFMON18_PERFCOUNTER_CNTL2 0x1f45 7670#define regDC_PERFMON18_PERFCOUNTER_CNTL2_BASE_IDX 2 7671#define regDC_PERFMON18_PERFCOUNTER_STATE 0x1f46 7672#define regDC_PERFMON18_PERFCOUNTER_STATE_BASE_IDX 2 7673#define regDC_PERFMON18_PERFMON_CNTL 0x1f47 7674#define regDC_PERFMON18_PERFMON_CNTL_BASE_IDX 2 7675#define regDC_PERFMON18_PERFMON_CNTL2 0x1f48 7676#define regDC_PERFMON18_PERFMON_CNTL2_BASE_IDX 2 7677#define regDC_PERFMON18_PERFMON_CVALUE_INT_MISC 0x1f49 7678#define regDC_PERFMON18_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 7679#define regDC_PERFMON18_PERFMON_CVALUE_LOW 0x1f4a 7680#define regDC_PERFMON18_PERFMON_CVALUE_LOW_BASE_IDX 2 7681#define regDC_PERFMON18_PERFMON_HI 0x1f4b 7682#define regDC_PERFMON18_PERFMON_HI_BASE_IDX 2 7683#define regDC_PERFMON18_PERFMON_LOW 0x1f4c 7684#define regDC_PERFMON18_PERFMON_LOW_BASE_IDX 2 7685 7686 7687// addressBlock: dce_dc_dio_dp_aux0_dispdec 7688// base address: 0x0 7689#define regDP_AUX0_AUX_CONTROL 0x1f50 7690#define regDP_AUX0_AUX_CONTROL_BASE_IDX 2 7691#define regDP_AUX0_AUX_SW_CONTROL 0x1f51 7692#define regDP_AUX0_AUX_SW_CONTROL_BASE_IDX 2 7693#define regDP_AUX0_AUX_ARB_CONTROL 0x1f52 7694#define regDP_AUX0_AUX_ARB_CONTROL_BASE_IDX 2 7695#define regDP_AUX0_AUX_INTERRUPT_CONTROL 0x1f53 7696#define regDP_AUX0_AUX_INTERRUPT_CONTROL_BASE_IDX 2 7697#define regDP_AUX0_AUX_SW_STATUS 0x1f54 7698#define regDP_AUX0_AUX_SW_STATUS_BASE_IDX 2 7699#define regDP_AUX0_AUX_LS_STATUS 0x1f55 7700#define regDP_AUX0_AUX_LS_STATUS_BASE_IDX 2 7701#define regDP_AUX0_AUX_SW_DATA 0x1f56 7702#define regDP_AUX0_AUX_SW_DATA_BASE_IDX 2 7703#define regDP_AUX0_AUX_LS_DATA 0x1f57 7704#define regDP_AUX0_AUX_LS_DATA_BASE_IDX 2 7705#define regDP_AUX0_AUX_DPHY_TX_REF_CONTROL 0x1f58 7706#define regDP_AUX0_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2 7707#define regDP_AUX0_AUX_DPHY_TX_CONTROL 0x1f59 7708#define regDP_AUX0_AUX_DPHY_TX_CONTROL_BASE_IDX 2 7709#define regDP_AUX0_AUX_DPHY_RX_CONTROL0 0x1f5a 7710#define regDP_AUX0_AUX_DPHY_RX_CONTROL0_BASE_IDX 2 7711#define regDP_AUX0_AUX_DPHY_RX_CONTROL1 0x1f5b 7712#define regDP_AUX0_AUX_DPHY_RX_CONTROL1_BASE_IDX 2 7713#define regDP_AUX0_AUX_DPHY_TX_STATUS 0x1f5c 7714#define regDP_AUX0_AUX_DPHY_TX_STATUS_BASE_IDX 2 7715#define regDP_AUX0_AUX_DPHY_RX_STATUS 0x1f5d 7716#define regDP_AUX0_AUX_DPHY_RX_STATUS_BASE_IDX 2 7717#define regDP_AUX0_AUX_GTC_SYNC_CONTROL 0x1f5e 7718#define regDP_AUX0_AUX_GTC_SYNC_CONTROL_BASE_IDX 2 7719#define regDP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL 0x1f5f 7720#define regDP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2 7721#define regDP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1f60 7722#define regDP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2 7723#define regDP_AUX0_AUX_GTC_SYNC_STATUS 0x1f61 7724#define regDP_AUX0_AUX_GTC_SYNC_STATUS_BASE_IDX 2 7725#define regDP_AUX0_AUX_PHY_WAKE_CNTL 0x1f66 7726#define regDP_AUX0_AUX_PHY_WAKE_CNTL_BASE_IDX 2 7727 7728 7729// addressBlock: dce_dc_dio_dp_aux1_dispdec 7730// base address: 0x70 7731#define regDP_AUX1_AUX_CONTROL 0x1f6c 7732#define regDP_AUX1_AUX_CONTROL_BASE_IDX 2 7733#define regDP_AUX1_AUX_SW_CONTROL 0x1f6d 7734#define regDP_AUX1_AUX_SW_CONTROL_BASE_IDX 2 7735#define regDP_AUX1_AUX_ARB_CONTROL 0x1f6e 7736#define regDP_AUX1_AUX_ARB_CONTROL_BASE_IDX 2 7737#define regDP_AUX1_AUX_INTERRUPT_CONTROL 0x1f6f 7738#define regDP_AUX1_AUX_INTERRUPT_CONTROL_BASE_IDX 2 7739#define regDP_AUX1_AUX_SW_STATUS 0x1f70 7740#define regDP_AUX1_AUX_SW_STATUS_BASE_IDX 2 7741#define regDP_AUX1_AUX_LS_STATUS 0x1f71 7742#define regDP_AUX1_AUX_LS_STATUS_BASE_IDX 2 7743#define regDP_AUX1_AUX_SW_DATA 0x1f72 7744#define regDP_AUX1_AUX_SW_DATA_BASE_IDX 2 7745#define regDP_AUX1_AUX_LS_DATA 0x1f73 7746#define regDP_AUX1_AUX_LS_DATA_BASE_IDX 2 7747#define regDP_AUX1_AUX_DPHY_TX_REF_CONTROL 0x1f74 7748#define regDP_AUX1_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2 7749#define regDP_AUX1_AUX_DPHY_TX_CONTROL 0x1f75 7750#define regDP_AUX1_AUX_DPHY_TX_CONTROL_BASE_IDX 2 7751#define regDP_AUX1_AUX_DPHY_RX_CONTROL0 0x1f76 7752#define regDP_AUX1_AUX_DPHY_RX_CONTROL0_BASE_IDX 2 7753#define regDP_AUX1_AUX_DPHY_RX_CONTROL1 0x1f77 7754#define regDP_AUX1_AUX_DPHY_RX_CONTROL1_BASE_IDX 2 7755#define regDP_AUX1_AUX_DPHY_TX_STATUS 0x1f78 7756#define regDP_AUX1_AUX_DPHY_TX_STATUS_BASE_IDX 2 7757#define regDP_AUX1_AUX_DPHY_RX_STATUS 0x1f79 7758#define regDP_AUX1_AUX_DPHY_RX_STATUS_BASE_IDX 2 7759#define regDP_AUX1_AUX_GTC_SYNC_CONTROL 0x1f7a 7760#define regDP_AUX1_AUX_GTC_SYNC_CONTROL_BASE_IDX 2 7761#define regDP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL 0x1f7b 7762#define regDP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2 7763#define regDP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1f7c 7764#define regDP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2 7765#define regDP_AUX1_AUX_GTC_SYNC_STATUS 0x1f7d 7766#define regDP_AUX1_AUX_GTC_SYNC_STATUS_BASE_IDX 2 7767#define regDP_AUX1_AUX_PHY_WAKE_CNTL 0x1f82 7768#define regDP_AUX1_AUX_PHY_WAKE_CNTL_BASE_IDX 2 7769 7770 7771// addressBlock: dce_dc_dio_dp_aux2_dispdec 7772// base address: 0xe0 7773#define regDP_AUX2_AUX_CONTROL 0x1f88 7774#define regDP_AUX2_AUX_CONTROL_BASE_IDX 2 7775#define regDP_AUX2_AUX_SW_CONTROL 0x1f89 7776#define regDP_AUX2_AUX_SW_CONTROL_BASE_IDX 2 7777#define regDP_AUX2_AUX_ARB_CONTROL 0x1f8a 7778#define regDP_AUX2_AUX_ARB_CONTROL_BASE_IDX 2 7779#define regDP_AUX2_AUX_INTERRUPT_CONTROL 0x1f8b 7780#define regDP_AUX2_AUX_INTERRUPT_CONTROL_BASE_IDX 2 7781#define regDP_AUX2_AUX_SW_STATUS 0x1f8c 7782#define regDP_AUX2_AUX_SW_STATUS_BASE_IDX 2 7783#define regDP_AUX2_AUX_LS_STATUS 0x1f8d 7784#define regDP_AUX2_AUX_LS_STATUS_BASE_IDX 2 7785#define regDP_AUX2_AUX_SW_DATA 0x1f8e 7786#define regDP_AUX2_AUX_SW_DATA_BASE_IDX 2 7787#define regDP_AUX2_AUX_LS_DATA 0x1f8f 7788#define regDP_AUX2_AUX_LS_DATA_BASE_IDX 2 7789#define regDP_AUX2_AUX_DPHY_TX_REF_CONTROL 0x1f90 7790#define regDP_AUX2_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2 7791#define regDP_AUX2_AUX_DPHY_TX_CONTROL 0x1f91 7792#define regDP_AUX2_AUX_DPHY_TX_CONTROL_BASE_IDX 2 7793#define regDP_AUX2_AUX_DPHY_RX_CONTROL0 0x1f92 7794#define regDP_AUX2_AUX_DPHY_RX_CONTROL0_BASE_IDX 2 7795#define regDP_AUX2_AUX_DPHY_RX_CONTROL1 0x1f93 7796#define regDP_AUX2_AUX_DPHY_RX_CONTROL1_BASE_IDX 2 7797#define regDP_AUX2_AUX_DPHY_TX_STATUS 0x1f94 7798#define regDP_AUX2_AUX_DPHY_TX_STATUS_BASE_IDX 2 7799#define regDP_AUX2_AUX_DPHY_RX_STATUS 0x1f95 7800#define regDP_AUX2_AUX_DPHY_RX_STATUS_BASE_IDX 2 7801#define regDP_AUX2_AUX_GTC_SYNC_CONTROL 0x1f96 7802#define regDP_AUX2_AUX_GTC_SYNC_CONTROL_BASE_IDX 2 7803#define regDP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL 0x1f97 7804#define regDP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2 7805#define regDP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1f98 7806#define regDP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2 7807#define regDP_AUX2_AUX_GTC_SYNC_STATUS 0x1f99 7808#define regDP_AUX2_AUX_GTC_SYNC_STATUS_BASE_IDX 2 7809#define regDP_AUX2_AUX_PHY_WAKE_CNTL 0x1f9e 7810#define regDP_AUX2_AUX_PHY_WAKE_CNTL_BASE_IDX 2 7811 7812 7813// addressBlock: dce_dc_dio_dp_aux3_dispdec 7814// base address: 0x150 7815#define regDP_AUX3_AUX_CONTROL 0x1fa4 7816#define regDP_AUX3_AUX_CONTROL_BASE_IDX 2 7817#define regDP_AUX3_AUX_SW_CONTROL 0x1fa5 7818#define regDP_AUX3_AUX_SW_CONTROL_BASE_IDX 2 7819#define regDP_AUX3_AUX_ARB_CONTROL 0x1fa6 7820#define regDP_AUX3_AUX_ARB_CONTROL_BASE_IDX 2 7821#define regDP_AUX3_AUX_INTERRUPT_CONTROL 0x1fa7 7822#define regDP_AUX3_AUX_INTERRUPT_CONTROL_BASE_IDX 2 7823#define regDP_AUX3_AUX_SW_STATUS 0x1fa8 7824#define regDP_AUX3_AUX_SW_STATUS_BASE_IDX 2 7825#define regDP_AUX3_AUX_LS_STATUS 0x1fa9 7826#define regDP_AUX3_AUX_LS_STATUS_BASE_IDX 2 7827#define regDP_AUX3_AUX_SW_DATA 0x1faa 7828#define regDP_AUX3_AUX_SW_DATA_BASE_IDX 2 7829#define regDP_AUX3_AUX_LS_DATA 0x1fab 7830#define regDP_AUX3_AUX_LS_DATA_BASE_IDX 2 7831#define regDP_AUX3_AUX_DPHY_TX_REF_CONTROL 0x1fac 7832#define regDP_AUX3_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2 7833#define regDP_AUX3_AUX_DPHY_TX_CONTROL 0x1fad 7834#define regDP_AUX3_AUX_DPHY_TX_CONTROL_BASE_IDX 2 7835#define regDP_AUX3_AUX_DPHY_RX_CONTROL0 0x1fae 7836#define regDP_AUX3_AUX_DPHY_RX_CONTROL0_BASE_IDX 2 7837#define regDP_AUX3_AUX_DPHY_RX_CONTROL1 0x1faf 7838#define regDP_AUX3_AUX_DPHY_RX_CONTROL1_BASE_IDX 2 7839#define regDP_AUX3_AUX_DPHY_TX_STATUS 0x1fb0 7840#define regDP_AUX3_AUX_DPHY_TX_STATUS_BASE_IDX 2 7841#define regDP_AUX3_AUX_DPHY_RX_STATUS 0x1fb1 7842#define regDP_AUX3_AUX_DPHY_RX_STATUS_BASE_IDX 2 7843#define regDP_AUX3_AUX_GTC_SYNC_CONTROL 0x1fb2 7844#define regDP_AUX3_AUX_GTC_SYNC_CONTROL_BASE_IDX 2 7845#define regDP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL 0x1fb3 7846#define regDP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2 7847#define regDP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1fb4 7848#define regDP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2 7849#define regDP_AUX3_AUX_GTC_SYNC_STATUS 0x1fb5 7850#define regDP_AUX3_AUX_GTC_SYNC_STATUS_BASE_IDX 2 7851#define regDP_AUX3_AUX_PHY_WAKE_CNTL 0x1fba 7852#define regDP_AUX3_AUX_PHY_WAKE_CNTL_BASE_IDX 2 7853 7854 7855// addressBlock: dce_dc_dio_dp_aux4_dispdec 7856// base address: 0x1c0 7857#define regDP_AUX4_AUX_CONTROL 0x1fc0 7858#define regDP_AUX4_AUX_CONTROL_BASE_IDX 2 7859#define regDP_AUX4_AUX_SW_CONTROL 0x1fc1 7860#define regDP_AUX4_AUX_SW_CONTROL_BASE_IDX 2 7861#define regDP_AUX4_AUX_ARB_CONTROL 0x1fc2 7862#define regDP_AUX4_AUX_ARB_CONTROL_BASE_IDX 2 7863#define regDP_AUX4_AUX_INTERRUPT_CONTROL 0x1fc3 7864#define regDP_AUX4_AUX_INTERRUPT_CONTROL_BASE_IDX 2 7865#define regDP_AUX4_AUX_SW_STATUS 0x1fc4 7866#define regDP_AUX4_AUX_SW_STATUS_BASE_IDX 2 7867#define regDP_AUX4_AUX_LS_STATUS 0x1fc5 7868#define regDP_AUX4_AUX_LS_STATUS_BASE_IDX 2 7869#define regDP_AUX4_AUX_SW_DATA 0x1fc6 7870#define regDP_AUX4_AUX_SW_DATA_BASE_IDX 2 7871#define regDP_AUX4_AUX_LS_DATA 0x1fc7 7872#define regDP_AUX4_AUX_LS_DATA_BASE_IDX 2 7873#define regDP_AUX4_AUX_DPHY_TX_REF_CONTROL 0x1fc8 7874#define regDP_AUX4_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2 7875#define regDP_AUX4_AUX_DPHY_TX_CONTROL 0x1fc9 7876#define regDP_AUX4_AUX_DPHY_TX_CONTROL_BASE_IDX 2 7877#define regDP_AUX4_AUX_DPHY_RX_CONTROL0 0x1fca 7878#define regDP_AUX4_AUX_DPHY_RX_CONTROL0_BASE_IDX 2 7879#define regDP_AUX4_AUX_DPHY_RX_CONTROL1 0x1fcb 7880#define regDP_AUX4_AUX_DPHY_RX_CONTROL1_BASE_IDX 2 7881#define regDP_AUX4_AUX_DPHY_TX_STATUS 0x1fcc 7882#define regDP_AUX4_AUX_DPHY_TX_STATUS_BASE_IDX 2 7883#define regDP_AUX4_AUX_DPHY_RX_STATUS 0x1fcd 7884#define regDP_AUX4_AUX_DPHY_RX_STATUS_BASE_IDX 2 7885#define regDP_AUX4_AUX_GTC_SYNC_CONTROL 0x1fce 7886#define regDP_AUX4_AUX_GTC_SYNC_CONTROL_BASE_IDX 2 7887#define regDP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL 0x1fcf 7888#define regDP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2 7889#define regDP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1fd0 7890#define regDP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2 7891#define regDP_AUX4_AUX_GTC_SYNC_STATUS 0x1fd1 7892#define regDP_AUX4_AUX_GTC_SYNC_STATUS_BASE_IDX 2 7893#define regDP_AUX4_AUX_PHY_WAKE_CNTL 0x1fd6 7894#define regDP_AUX4_AUX_PHY_WAKE_CNTL_BASE_IDX 2 7895 7896 7897// addressBlock: dce_dc_dio_dig0_vpg_vpg_dispdec 7898// base address: 0x154a0 7899#define regVPG0_VPG_GENERIC_PACKET_ACCESS_CTRL 0x2068 7900#define regVPG0_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2 7901#define regVPG0_VPG_GENERIC_PACKET_DATA 0x2069 7902#define regVPG0_VPG_GENERIC_PACKET_DATA_BASE_IDX 2 7903#define regVPG0_VPG_GSP_FRAME_UPDATE_CTRL 0x206a 7904#define regVPG0_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2 7905#define regVPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x206b 7906#define regVPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2 7907#define regVPG0_VPG_GENERIC_STATUS 0x206c 7908#define regVPG0_VPG_GENERIC_STATUS_BASE_IDX 2 7909#define regVPG0_VPG_MEM_PWR 0x206d 7910#define regVPG0_VPG_MEM_PWR_BASE_IDX 2 7911#define regVPG0_VPG_ISRC1_2_ACCESS_CTRL 0x206e 7912#define regVPG0_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2 7913#define regVPG0_VPG_ISRC1_2_DATA 0x206f 7914#define regVPG0_VPG_ISRC1_2_DATA_BASE_IDX 2 7915#define regVPG0_VPG_MPEG_INFO0 0x2070 7916#define regVPG0_VPG_MPEG_INFO0_BASE_IDX 2 7917#define regVPG0_VPG_MPEG_INFO1 0x2071 7918#define regVPG0_VPG_MPEG_INFO1_BASE_IDX 2 7919 7920 7921// addressBlock: dce_dc_dio_dig0_afmt_afmt_dispdec 7922// base address: 0x154cc 7923#define regAFMT0_AFMT_ACP 0x2073 7924#define regAFMT0_AFMT_ACP_BASE_IDX 2 7925#define regAFMT0_AFMT_VBI_PACKET_CONTROL 0x2074 7926#define regAFMT0_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2 7927#define regAFMT0_AFMT_AUDIO_PACKET_CONTROL2 0x2075 7928#define regAFMT0_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2 7929#define regAFMT0_AFMT_AUDIO_INFO0 0x2076 7930#define regAFMT0_AFMT_AUDIO_INFO0_BASE_IDX 2 7931#define regAFMT0_AFMT_AUDIO_INFO1 0x2077 7932#define regAFMT0_AFMT_AUDIO_INFO1_BASE_IDX 2 7933#define regAFMT0_AFMT_60958_0 0x2078 7934#define regAFMT0_AFMT_60958_0_BASE_IDX 2 7935#define regAFMT0_AFMT_60958_1 0x2079 7936#define regAFMT0_AFMT_60958_1_BASE_IDX 2 7937#define regAFMT0_AFMT_AUDIO_CRC_CONTROL 0x207a 7938#define regAFMT0_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2 7939#define regAFMT0_AFMT_RAMP_CONTROL0 0x207b 7940#define regAFMT0_AFMT_RAMP_CONTROL0_BASE_IDX 2 7941#define regAFMT0_AFMT_RAMP_CONTROL1 0x207c 7942#define regAFMT0_AFMT_RAMP_CONTROL1_BASE_IDX 2 7943#define regAFMT0_AFMT_RAMP_CONTROL2 0x207d 7944#define regAFMT0_AFMT_RAMP_CONTROL2_BASE_IDX 2 7945#define regAFMT0_AFMT_RAMP_CONTROL3 0x207e 7946#define regAFMT0_AFMT_RAMP_CONTROL3_BASE_IDX 2 7947#define regAFMT0_AFMT_60958_2 0x207f 7948#define regAFMT0_AFMT_60958_2_BASE_IDX 2 7949#define regAFMT0_AFMT_AUDIO_CRC_RESULT 0x2080 7950#define regAFMT0_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2 7951#define regAFMT0_AFMT_STATUS 0x2081 7952#define regAFMT0_AFMT_STATUS_BASE_IDX 2 7953#define regAFMT0_AFMT_AUDIO_PACKET_CONTROL 0x2082 7954#define regAFMT0_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2 7955#define regAFMT0_AFMT_INFOFRAME_CONTROL0 0x2083 7956#define regAFMT0_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2 7957#define regAFMT0_AFMT_INTERRUPT_STATUS 0x2084 7958#define regAFMT0_AFMT_INTERRUPT_STATUS_BASE_IDX 2 7959#define regAFMT0_AFMT_AUDIO_SRC_CONTROL 0x2085 7960#define regAFMT0_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2 7961#define regAFMT0_AFMT_MEM_PWR 0x2087 7962#define regAFMT0_AFMT_MEM_PWR_BASE_IDX 2 7963 7964 7965// addressBlock: dce_dc_dio_dig0_dme_dme_dispdec 7966// base address: 0x15544 7967#define regDME0_DME_CONTROL 0x2091 7968#define regDME0_DME_CONTROL_BASE_IDX 2 7969#define regDME0_DME_MEMORY_CONTROL 0x2092 7970#define regDME0_DME_MEMORY_CONTROL_BASE_IDX 2 7971 7972 7973 7974// addressBlock: dce_dc_dio_dig0_dispdec 7975// base address: 0x0 7976#define regDIG0_DIG_FE_CNTL 0x2093 7977#define regDIG0_DIG_FE_CNTL_BASE_IDX 2 7978#define regDIG0_DIG_FE_CLK_CNTL 0x2094 7979#define regDIG0_DIG_FE_CLK_CNTL_BASE_IDX 2 7980#define regDIG0_DIG_FE_EN_CNTL 0x2095 7981#define regDIG0_DIG_FE_EN_CNTL_BASE_IDX 2 7982#define regDIG0_DIG_OUTPUT_CRC_CNTL 0x2096 7983#define regDIG0_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2 7984#define regDIG0_DIG_OUTPUT_CRC_RESULT 0x2097 7985#define regDIG0_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2 7986#define regDIG0_DIG_CLOCK_PATTERN 0x2098 7987#define regDIG0_DIG_CLOCK_PATTERN_BASE_IDX 2 7988#define regDIG0_DIG_TEST_PATTERN 0x2099 7989#define regDIG0_DIG_TEST_PATTERN_BASE_IDX 2 7990#define regDIG0_DIG_RANDOM_PATTERN_SEED 0x209a 7991#define regDIG0_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2 7992#define regDIG0_DIG_FIFO_CTRL0 0x209b 7993#define regDIG0_DIG_FIFO_CTRL0_BASE_IDX 2 7994#define regDIG0_DIG_FIFO_CTRL1 0x209c 7995#define regDIG0_DIG_FIFO_CTRL1_BASE_IDX 2 7996#define regDIG0_HDMI_METADATA_PACKET_CONTROL 0x209d 7997#define regDIG0_HDMI_METADATA_PACKET_CONTROL_BASE_IDX 2 7998#define regDIG0_HDMI_CONTROL 0x209e 7999#define regDIG0_HDMI_CONTROL_BASE_IDX 2 8000#define regDIG0_HDMI_STATUS 0x209f 8001#define regDIG0_HDMI_STATUS_BASE_IDX 2 8002#define regDIG0_HDMI_AUDIO_PACKET_CONTROL 0x20a0 8003#define regDIG0_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2 8004#define regDIG0_HDMI_ACR_PACKET_CONTROL 0x20a1 8005#define regDIG0_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2 8006#define regDIG0_HDMI_VBI_PACKET_CONTROL 0x20a2 8007#define regDIG0_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2 8008#define regDIG0_HDMI_INFOFRAME_CONTROL0 0x20a3 8009#define regDIG0_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2 8010#define regDIG0_HDMI_INFOFRAME_CONTROL1 0x20a4 8011#define regDIG0_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2 8012#define regDIG0_HDMI_GENERIC_PACKET_CONTROL0 0x20a5 8013#define regDIG0_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2 8014#define regDIG0_HDMI_GENERIC_PACKET_CONTROL6 0x20a6 8015#define regDIG0_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX 2 8016#define regDIG0_HDMI_GENERIC_PACKET_CONTROL5 0x20a7 8017#define regDIG0_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX 2 8018#define regDIG0_HDMI_GC 0x20a8 8019#define regDIG0_HDMI_GC_BASE_IDX 2 8020#define regDIG0_HDMI_GENERIC_PACKET_CONTROL1 0x20a9 8021#define regDIG0_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2 8022#define regDIG0_HDMI_GENERIC_PACKET_CONTROL2 0x20aa 8023#define regDIG0_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2 8024#define regDIG0_HDMI_GENERIC_PACKET_CONTROL3 0x20ab 8025#define regDIG0_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2 8026#define regDIG0_HDMI_GENERIC_PACKET_CONTROL4 0x20ac 8027#define regDIG0_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX 2 8028#define regDIG0_HDMI_GENERIC_PACKET_CONTROL7 0x20ad 8029#define regDIG0_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX 2 8030#define regDIG0_HDMI_GENERIC_PACKET_CONTROL8 0x20ae 8031#define regDIG0_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX 2 8032#define regDIG0_HDMI_GENERIC_PACKET_CONTROL9 0x20af 8033#define regDIG0_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX 2 8034#define regDIG0_HDMI_GENERIC_PACKET_CONTROL10 0x20b0 8035#define regDIG0_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX 2 8036#define regDIG0_HDMI_DB_CONTROL 0x20b1 8037#define regDIG0_HDMI_DB_CONTROL_BASE_IDX 2 8038#define regDIG0_HDMI_ACR_32_0 0x20b2 8039#define regDIG0_HDMI_ACR_32_0_BASE_IDX 2 8040#define regDIG0_HDMI_ACR_32_1 0x20b3 8041#define regDIG0_HDMI_ACR_32_1_BASE_IDX 2 8042#define regDIG0_HDMI_ACR_44_0 0x20b4 8043#define regDIG0_HDMI_ACR_44_0_BASE_IDX 2 8044#define regDIG0_HDMI_ACR_44_1 0x20b5 8045#define regDIG0_HDMI_ACR_44_1_BASE_IDX 2 8046#define regDIG0_HDMI_ACR_48_0 0x20b6 8047#define regDIG0_HDMI_ACR_48_0_BASE_IDX 2 8048#define regDIG0_HDMI_ACR_48_1 0x20b7 8049#define regDIG0_HDMI_ACR_48_1_BASE_IDX 2 8050#define regDIG0_HDMI_ACR_STATUS_0 0x20b8 8051#define regDIG0_HDMI_ACR_STATUS_0_BASE_IDX 2 8052#define regDIG0_HDMI_ACR_STATUS_1 0x20b9 8053#define regDIG0_HDMI_ACR_STATUS_1_BASE_IDX 2 8054#define regDIG0_AFMT_CNTL 0x20ba 8055#define regDIG0_AFMT_CNTL_BASE_IDX 2 8056#define regDIG0_DIG_BE_CLK_CNTL 0x20bb 8057#define regDIG0_DIG_BE_CLK_CNTL_BASE_IDX 2 8058#define regDIG0_DIG_BE_CNTL 0x20bc 8059#define regDIG0_DIG_BE_CNTL_BASE_IDX 2 8060#define regDIG0_DIG_BE_EN_CNTL 0x20bd 8061#define regDIG0_DIG_BE_EN_CNTL_BASE_IDX 2 8062#define regDIG0_TMDS_CNTL 0x20e4 8063#define regDIG0_TMDS_CNTL_BASE_IDX 2 8064#define regDIG0_TMDS_CONTROL_CHAR 0x20e5 8065#define regDIG0_TMDS_CONTROL_CHAR_BASE_IDX 2 8066#define regDIG0_TMDS_CONTROL0_FEEDBACK 0x20e6 8067#define regDIG0_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2 8068#define regDIG0_TMDS_STEREOSYNC_CTL_SEL 0x20e7 8069#define regDIG0_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2 8070#define regDIG0_TMDS_SYNC_CHAR_PATTERN_0_1 0x20e8 8071#define regDIG0_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2 8072#define regDIG0_TMDS_SYNC_CHAR_PATTERN_2_3 0x20e9 8073#define regDIG0_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2 8074#define regDIG0_TMDS_CTL_BITS 0x20eb 8075#define regDIG0_TMDS_CTL_BITS_BASE_IDX 2 8076#define regDIG0_TMDS_DCBALANCER_CONTROL 0x20ec 8077#define regDIG0_TMDS_DCBALANCER_CONTROL_BASE_IDX 2 8078#define regDIG0_TMDS_SYNC_DCBALANCE_CHAR 0x20ed 8079#define regDIG0_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX 2 8080#define regDIG0_TMDS_CTL0_1_GEN_CNTL 0x20ee 8081#define regDIG0_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2 8082#define regDIG0_TMDS_CTL2_3_GEN_CNTL 0x20ef 8083#define regDIG0_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2 8084#define regDIG0_DIG_VERSION 0x20f1 8085#define regDIG0_DIG_VERSION_BASE_IDX 2 8086 8087 8088// addressBlock: dce_dc_dio_dp0_dispdec 8089// base address: 0x0 8090#define regDP0_DP_LINK_CNTL 0x211e 8091#define regDP0_DP_LINK_CNTL_BASE_IDX 2 8092#define regDP0_DP_PIXEL_FORMAT 0x211f 8093#define regDP0_DP_PIXEL_FORMAT_BASE_IDX 2 8094#define regDP0_DP_MSA_COLORIMETRY 0x2120 8095#define regDP0_DP_MSA_COLORIMETRY_BASE_IDX 2 8096#define regDP0_DP_CONFIG 0x2121 8097#define regDP0_DP_CONFIG_BASE_IDX 2 8098#define regDP0_DP_VID_STREAM_CNTL 0x2122 8099#define regDP0_DP_VID_STREAM_CNTL_BASE_IDX 2 8100#define regDP0_DP_STEER_FIFO 0x2123 8101#define regDP0_DP_STEER_FIFO_BASE_IDX 2 8102#define regDP0_DP_MSA_MISC 0x2124 8103#define regDP0_DP_MSA_MISC_BASE_IDX 2 8104#define regDP0_DP_DPHY_INTERNAL_CTRL 0x2125 8105#define regDP0_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 8106#define regDP0_DP_VID_TIMING 0x2126 8107#define regDP0_DP_VID_TIMING_BASE_IDX 2 8108#define regDP0_DP_VID_N 0x2127 8109#define regDP0_DP_VID_N_BASE_IDX 2 8110#define regDP0_DP_VID_M 0x2128 8111#define regDP0_DP_VID_M_BASE_IDX 2 8112#define regDP0_DP_LINK_FRAMING_CNTL 0x2129 8113#define regDP0_DP_LINK_FRAMING_CNTL_BASE_IDX 2 8114#define regDP0_DP_HBR2_EYE_PATTERN 0x212a 8115#define regDP0_DP_HBR2_EYE_PATTERN_BASE_IDX 2 8116#define regDP0_DP_VID_MSA_VBID 0x212b 8117#define regDP0_DP_VID_MSA_VBID_BASE_IDX 2 8118#define regDP0_DP_VID_INTERRUPT_CNTL 0x212c 8119#define regDP0_DP_VID_INTERRUPT_CNTL_BASE_IDX 2 8120#define regDP0_DP_DPHY_CNTL 0x212d 8121#define regDP0_DP_DPHY_CNTL_BASE_IDX 2 8122#define regDP0_DP_DPHY_TRAINING_PATTERN_SEL 0x212e 8123#define regDP0_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2 8124#define regDP0_DP_DPHY_SYM0 0x212f 8125#define regDP0_DP_DPHY_SYM0_BASE_IDX 2 8126#define regDP0_DP_DPHY_SYM1 0x2130 8127#define regDP0_DP_DPHY_SYM1_BASE_IDX 2 8128#define regDP0_DP_DPHY_SYM2 0x2131 8129#define regDP0_DP_DPHY_SYM2_BASE_IDX 2 8130#define regDP0_DP_DPHY_8B10B_CNTL 0x2132 8131#define regDP0_DP_DPHY_8B10B_CNTL_BASE_IDX 2 8132#define regDP0_DP_DPHY_PRBS_CNTL 0x2133 8133#define regDP0_DP_DPHY_PRBS_CNTL_BASE_IDX 2 8134#define regDP0_DP_DPHY_SCRAM_CNTL 0x2134 8135#define regDP0_DP_DPHY_SCRAM_CNTL_BASE_IDX 2 8136#define regDP0_DP_DPHY_CRC_EN 0x2135 8137#define regDP0_DP_DPHY_CRC_EN_BASE_IDX 2 8138#define regDP0_DP_DPHY_CRC_CNTL 0x2136 8139#define regDP0_DP_DPHY_CRC_CNTL_BASE_IDX 2 8140#define regDP0_DP_DPHY_CRC_RESULT 0x2137 8141#define regDP0_DP_DPHY_CRC_RESULT_BASE_IDX 2 8142#define regDP0_DP_DPHY_CRC_MST_CNTL 0x2138 8143#define regDP0_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2 8144#define regDP0_DP_DPHY_CRC_MST_STATUS 0x2139 8145#define regDP0_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2 8146#define regDP0_DP_DPHY_FAST_TRAINING 0x213a 8147#define regDP0_DP_DPHY_FAST_TRAINING_BASE_IDX 2 8148#define regDP0_DP_DPHY_FAST_TRAINING_STATUS 0x213b 8149#define regDP0_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2 8150#define regDP0_DP_SEC_CNTL 0x2141 8151#define regDP0_DP_SEC_CNTL_BASE_IDX 2 8152#define regDP0_DP_SEC_CNTL1 0x2142 8153#define regDP0_DP_SEC_CNTL1_BASE_IDX 2 8154#define regDP0_DP_SEC_FRAMING1 0x2143 8155#define regDP0_DP_SEC_FRAMING1_BASE_IDX 2 8156#define regDP0_DP_SEC_FRAMING2 0x2144 8157#define regDP0_DP_SEC_FRAMING2_BASE_IDX 2 8158#define regDP0_DP_SEC_FRAMING3 0x2145 8159#define regDP0_DP_SEC_FRAMING3_BASE_IDX 2 8160#define regDP0_DP_SEC_FRAMING4 0x2146 8161#define regDP0_DP_SEC_FRAMING4_BASE_IDX 2 8162#define regDP0_DP_SEC_AUD_N 0x2147 8163#define regDP0_DP_SEC_AUD_N_BASE_IDX 2 8164#define regDP0_DP_SEC_AUD_N_READBACK 0x2148 8165#define regDP0_DP_SEC_AUD_N_READBACK_BASE_IDX 2 8166#define regDP0_DP_SEC_AUD_M 0x2149 8167#define regDP0_DP_SEC_AUD_M_BASE_IDX 2 8168#define regDP0_DP_SEC_AUD_M_READBACK 0x214a 8169#define regDP0_DP_SEC_AUD_M_READBACK_BASE_IDX 2 8170#define regDP0_DP_SEC_TIMESTAMP 0x214b 8171#define regDP0_DP_SEC_TIMESTAMP_BASE_IDX 2 8172#define regDP0_DP_SEC_PACKET_CNTL 0x214c 8173#define regDP0_DP_SEC_PACKET_CNTL_BASE_IDX 2 8174#define regDP0_DP_MSE_RATE_CNTL 0x214d 8175#define regDP0_DP_MSE_RATE_CNTL_BASE_IDX 2 8176#define regDP0_DP_MSE_RATE_UPDATE 0x214f 8177#define regDP0_DP_MSE_RATE_UPDATE_BASE_IDX 2 8178#define regDP0_DP_MSE_SAT0 0x2150 8179#define regDP0_DP_MSE_SAT0_BASE_IDX 2 8180#define regDP0_DP_MSE_SAT1 0x2151 8181#define regDP0_DP_MSE_SAT1_BASE_IDX 2 8182#define regDP0_DP_MSE_SAT2 0x2152 8183#define regDP0_DP_MSE_SAT2_BASE_IDX 2 8184#define regDP0_DP_MSE_SAT_UPDATE 0x2153 8185#define regDP0_DP_MSE_SAT_UPDATE_BASE_IDX 2 8186#define regDP0_DP_MSE_LINK_TIMING 0x2154 8187#define regDP0_DP_MSE_LINK_TIMING_BASE_IDX 2 8188#define regDP0_DP_MSE_MISC_CNTL 0x2155 8189#define regDP0_DP_MSE_MISC_CNTL_BASE_IDX 2 8190#define regDP0_DP_DPHY_BS_SR_SWAP_CNTL 0x215a 8191#define regDP0_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2 8192#define regDP0_DP_DPHY_HBR2_PATTERN_CONTROL 0x215b 8193#define regDP0_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2 8194#define regDP0_DP_MSE_SAT0_STATUS 0x215d 8195#define regDP0_DP_MSE_SAT0_STATUS_BASE_IDX 2 8196#define regDP0_DP_MSE_SAT1_STATUS 0x215e 8197#define regDP0_DP_MSE_SAT1_STATUS_BASE_IDX 2 8198#define regDP0_DP_MSE_SAT2_STATUS 0x215f 8199#define regDP0_DP_MSE_SAT2_STATUS_BASE_IDX 2 8200#define regDP0_DP_DPIA_SPARE 0x2160 8201#define regDP0_DP_DPIA_SPARE_BASE_IDX 2 8202#define regDP0_DP_MSA_TIMING_PARAM1 0x2162 8203#define regDP0_DP_MSA_TIMING_PARAM1_BASE_IDX 2 8204#define regDP0_DP_MSA_TIMING_PARAM2 0x2163 8205#define regDP0_DP_MSA_TIMING_PARAM2_BASE_IDX 2 8206#define regDP0_DP_MSA_TIMING_PARAM3 0x2164 8207#define regDP0_DP_MSA_TIMING_PARAM3_BASE_IDX 2 8208#define regDP0_DP_MSA_TIMING_PARAM4 0x2165 8209#define regDP0_DP_MSA_TIMING_PARAM4_BASE_IDX 2 8210#define regDP0_DP_MSO_CNTL 0x2166 8211#define regDP0_DP_MSO_CNTL_BASE_IDX 2 8212#define regDP0_DP_MSO_CNTL1 0x2167 8213#define regDP0_DP_MSO_CNTL1_BASE_IDX 2 8214#define regDP0_DP_DSC_CNTL 0x2168 8215#define regDP0_DP_DSC_CNTL_BASE_IDX 2 8216#define regDP0_DP_SEC_CNTL2 0x2169 8217#define regDP0_DP_SEC_CNTL2_BASE_IDX 2 8218#define regDP0_DP_SEC_CNTL3 0x216a 8219#define regDP0_DP_SEC_CNTL3_BASE_IDX 2 8220#define regDP0_DP_SEC_CNTL4 0x216b 8221#define regDP0_DP_SEC_CNTL4_BASE_IDX 2 8222#define regDP0_DP_SEC_CNTL5 0x216c 8223#define regDP0_DP_SEC_CNTL5_BASE_IDX 2 8224#define regDP0_DP_SEC_CNTL6 0x216d 8225#define regDP0_DP_SEC_CNTL6_BASE_IDX 2 8226#define regDP0_DP_SEC_CNTL7 0x216e 8227#define regDP0_DP_SEC_CNTL7_BASE_IDX 2 8228#define regDP0_DP_DB_CNTL 0x216f 8229#define regDP0_DP_DB_CNTL_BASE_IDX 2 8230#define regDP0_DP_MSA_VBID_MISC 0x2170 8231#define regDP0_DP_MSA_VBID_MISC_BASE_IDX 2 8232#define regDP0_DP_SEC_METADATA_TRANSMISSION 0x2171 8233#define regDP0_DP_SEC_METADATA_TRANSMISSION_BASE_IDX 2 8234#define regDP0_DP_ALPM_CNTL 0x2173 8235#define regDP0_DP_ALPM_CNTL_BASE_IDX 2 8236#define regDP0_DP_GSP8_CNTL 0x2174 8237#define regDP0_DP_GSP8_CNTL_BASE_IDX 2 8238#define regDP0_DP_GSP9_CNTL 0x2175 8239#define regDP0_DP_GSP9_CNTL_BASE_IDX 2 8240#define regDP0_DP_GSP10_CNTL 0x2176 8241#define regDP0_DP_GSP10_CNTL_BASE_IDX 2 8242#define regDP0_DP_GSP11_CNTL 0x2177 8243#define regDP0_DP_GSP11_CNTL_BASE_IDX 2 8244#define regDP0_DP_GSP_EN_DB_STATUS 0x2178 8245#define regDP0_DP_GSP_EN_DB_STATUS_BASE_IDX 2 8246#define regDP0_DP_AUXLESS_ALPM_CNTL1 0x2179 8247#define regDP0_DP_AUXLESS_ALPM_CNTL1_BASE_IDX 2 8248#define regDP0_DP_AUXLESS_ALPM_CNTL2 0x217a 8249#define regDP0_DP_AUXLESS_ALPM_CNTL2_BASE_IDX 2 8250#define regDP0_DP_AUXLESS_ALPM_CNTL3 0x217b 8251#define regDP0_DP_AUXLESS_ALPM_CNTL3_BASE_IDX 2 8252#define regDP0_DP_AUXLESS_ALPM_CNTL4 0x217c 8253#define regDP0_DP_AUXLESS_ALPM_CNTL4_BASE_IDX 2 8254#define regDP0_DP_AUXLESS_ALPM_CNTL5 0x217d 8255#define regDP0_DP_AUXLESS_ALPM_CNTL5_BASE_IDX 2 8256#define regDP0_DP_STREAM_SYMBOL_COUNT_STATUS 0x217e 8257#define regDP0_DP_STREAM_SYMBOL_COUNT_STATUS_BASE_IDX 2 8258#define regDP0_DP_STREAM_SYMBOL_COUNT_CONTROL 0x217f 8259#define regDP0_DP_STREAM_SYMBOL_COUNT_CONTROL_BASE_IDX 2 8260#define regDP0_DP_LINK_SYMBOL_COUNT_STATUS0 0x2180 8261#define regDP0_DP_LINK_SYMBOL_COUNT_STATUS0_BASE_IDX 2 8262#define regDP0_DP_LINK_SYMBOL_COUNT_STATUS1 0x2181 8263#define regDP0_DP_LINK_SYMBOL_COUNT_STATUS1_BASE_IDX 2 8264#define regDP0_DP_LINK_SYMBOL_COUNT_CONTROL 0x2182 8265#define regDP0_DP_LINK_SYMBOL_COUNT_CONTROL_BASE_IDX 2 8266 8267 8268// addressBlock: dce_dc_dio_dig1_vpg_vpg_dispdec 8269// base address: 0x15930 8270#define regVPG1_VPG_GENERIC_PACKET_ACCESS_CTRL 0x218c 8271#define regVPG1_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2 8272#define regVPG1_VPG_GENERIC_PACKET_DATA 0x218d 8273#define regVPG1_VPG_GENERIC_PACKET_DATA_BASE_IDX 2 8274#define regVPG1_VPG_GSP_FRAME_UPDATE_CTRL 0x218e 8275#define regVPG1_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2 8276#define regVPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x218f 8277#define regVPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2 8278#define regVPG1_VPG_GENERIC_STATUS 0x2190 8279#define regVPG1_VPG_GENERIC_STATUS_BASE_IDX 2 8280#define regVPG1_VPG_MEM_PWR 0x2191 8281#define regVPG1_VPG_MEM_PWR_BASE_IDX 2 8282#define regVPG1_VPG_ISRC1_2_ACCESS_CTRL 0x2192 8283#define regVPG1_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2 8284#define regVPG1_VPG_ISRC1_2_DATA 0x2193 8285#define regVPG1_VPG_ISRC1_2_DATA_BASE_IDX 2 8286#define regVPG1_VPG_MPEG_INFO0 0x2194 8287#define regVPG1_VPG_MPEG_INFO0_BASE_IDX 2 8288#define regVPG1_VPG_MPEG_INFO1 0x2195 8289#define regVPG1_VPG_MPEG_INFO1_BASE_IDX 2 8290 8291 8292// addressBlock: dce_dc_dio_dig1_afmt_afmt_dispdec 8293// base address: 0x1595c 8294#define regAFMT1_AFMT_ACP 0x2197 8295#define regAFMT1_AFMT_ACP_BASE_IDX 2 8296#define regAFMT1_AFMT_VBI_PACKET_CONTROL 0x2198 8297#define regAFMT1_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2 8298#define regAFMT1_AFMT_AUDIO_PACKET_CONTROL2 0x2199 8299#define regAFMT1_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2 8300#define regAFMT1_AFMT_AUDIO_INFO0 0x219a 8301#define regAFMT1_AFMT_AUDIO_INFO0_BASE_IDX 2 8302#define regAFMT1_AFMT_AUDIO_INFO1 0x219b 8303#define regAFMT1_AFMT_AUDIO_INFO1_BASE_IDX 2 8304#define regAFMT1_AFMT_60958_0 0x219c 8305#define regAFMT1_AFMT_60958_0_BASE_IDX 2 8306#define regAFMT1_AFMT_60958_1 0x219d 8307#define regAFMT1_AFMT_60958_1_BASE_IDX 2 8308#define regAFMT1_AFMT_AUDIO_CRC_CONTROL 0x219e 8309#define regAFMT1_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2 8310#define regAFMT1_AFMT_RAMP_CONTROL0 0x219f 8311#define regAFMT1_AFMT_RAMP_CONTROL0_BASE_IDX 2 8312#define regAFMT1_AFMT_RAMP_CONTROL1 0x21a0 8313#define regAFMT1_AFMT_RAMP_CONTROL1_BASE_IDX 2 8314#define regAFMT1_AFMT_RAMP_CONTROL2 0x21a1 8315#define regAFMT1_AFMT_RAMP_CONTROL2_BASE_IDX 2 8316#define regAFMT1_AFMT_RAMP_CONTROL3 0x21a2 8317#define regAFMT1_AFMT_RAMP_CONTROL3_BASE_IDX 2 8318#define regAFMT1_AFMT_60958_2 0x21a3 8319#define regAFMT1_AFMT_60958_2_BASE_IDX 2 8320#define regAFMT1_AFMT_AUDIO_CRC_RESULT 0x21a4 8321#define regAFMT1_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2 8322#define regAFMT1_AFMT_STATUS 0x21a5 8323#define regAFMT1_AFMT_STATUS_BASE_IDX 2 8324#define regAFMT1_AFMT_AUDIO_PACKET_CONTROL 0x21a6 8325#define regAFMT1_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2 8326#define regAFMT1_AFMT_INFOFRAME_CONTROL0 0x21a7 8327#define regAFMT1_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2 8328#define regAFMT1_AFMT_INTERRUPT_STATUS 0x21a8 8329#define regAFMT1_AFMT_INTERRUPT_STATUS_BASE_IDX 2 8330#define regAFMT1_AFMT_AUDIO_SRC_CONTROL 0x21a9 8331#define regAFMT1_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2 8332#define regAFMT1_AFMT_MEM_PWR 0x21ab 8333#define regAFMT1_AFMT_MEM_PWR_BASE_IDX 2 8334 8335 8336// addressBlock: dce_dc_dio_dig1_dme_dme_dispdec 8337// base address: 0x159d4 8338#define regDME1_DME_CONTROL 0x21b5 8339#define regDME1_DME_CONTROL_BASE_IDX 2 8340#define regDME1_DME_MEMORY_CONTROL 0x21b6 8341#define regDME1_DME_MEMORY_CONTROL_BASE_IDX 2 8342 8343 8344// addressBlock: dce_dc_dio_dig1_dispdec 8345// base address: 0x490 8346#define regDIG1_DIG_FE_CNTL 0x21b7 8347#define regDIG1_DIG_FE_CNTL_BASE_IDX 2 8348#define regDIG1_DIG_FE_CLK_CNTL 0x21b8 8349#define regDIG1_DIG_FE_CLK_CNTL_BASE_IDX 2 8350#define regDIG1_DIG_FE_EN_CNTL 0x21b9 8351#define regDIG1_DIG_FE_EN_CNTL_BASE_IDX 2 8352#define regDIG1_DIG_OUTPUT_CRC_CNTL 0x21ba 8353#define regDIG1_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2 8354#define regDIG1_DIG_OUTPUT_CRC_RESULT 0x21bb 8355#define regDIG1_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2 8356#define regDIG1_DIG_CLOCK_PATTERN 0x21bc 8357#define regDIG1_DIG_CLOCK_PATTERN_BASE_IDX 2 8358#define regDIG1_DIG_TEST_PATTERN 0x21bd 8359#define regDIG1_DIG_TEST_PATTERN_BASE_IDX 2 8360#define regDIG1_DIG_RANDOM_PATTERN_SEED 0x21be 8361#define regDIG1_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2 8362#define regDIG1_DIG_FIFO_CTRL0 0x21bf 8363#define regDIG1_DIG_FIFO_CTRL0_BASE_IDX 2 8364#define regDIG1_DIG_FIFO_CTRL1 0x21c0 8365#define regDIG1_DIG_FIFO_CTRL1_BASE_IDX 2 8366#define regDIG1_HDMI_METADATA_PACKET_CONTROL 0x21c1 8367#define regDIG1_HDMI_METADATA_PACKET_CONTROL_BASE_IDX 2 8368#define regDIG1_HDMI_CONTROL 0x21c2 8369#define regDIG1_HDMI_CONTROL_BASE_IDX 2 8370#define regDIG1_HDMI_STATUS 0x21c3 8371#define regDIG1_HDMI_STATUS_BASE_IDX 2 8372#define regDIG1_HDMI_AUDIO_PACKET_CONTROL 0x21c4 8373#define regDIG1_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2 8374#define regDIG1_HDMI_ACR_PACKET_CONTROL 0x21c5 8375#define regDIG1_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2 8376#define regDIG1_HDMI_VBI_PACKET_CONTROL 0x21c6 8377#define regDIG1_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2 8378#define regDIG1_HDMI_INFOFRAME_CONTROL0 0x21c7 8379#define regDIG1_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2 8380#define regDIG1_HDMI_INFOFRAME_CONTROL1 0x21c8 8381#define regDIG1_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2 8382#define regDIG1_HDMI_GENERIC_PACKET_CONTROL0 0x21c9 8383#define regDIG1_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2 8384#define regDIG1_HDMI_GENERIC_PACKET_CONTROL6 0x21ca 8385#define regDIG1_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX 2 8386#define regDIG1_HDMI_GENERIC_PACKET_CONTROL5 0x21cb 8387#define regDIG1_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX 2 8388#define regDIG1_HDMI_GC 0x21cc 8389#define regDIG1_HDMI_GC_BASE_IDX 2 8390#define regDIG1_HDMI_GENERIC_PACKET_CONTROL1 0x21cd 8391#define regDIG1_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2 8392#define regDIG1_HDMI_GENERIC_PACKET_CONTROL2 0x21ce 8393#define regDIG1_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2 8394#define regDIG1_HDMI_GENERIC_PACKET_CONTROL3 0x21cf 8395#define regDIG1_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2 8396#define regDIG1_HDMI_GENERIC_PACKET_CONTROL4 0x21d0 8397#define regDIG1_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX 2 8398#define regDIG1_HDMI_GENERIC_PACKET_CONTROL7 0x21d1 8399#define regDIG1_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX 2 8400#define regDIG1_HDMI_GENERIC_PACKET_CONTROL8 0x21d2 8401#define regDIG1_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX 2 8402#define regDIG1_HDMI_GENERIC_PACKET_CONTROL9 0x21d3 8403#define regDIG1_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX 2 8404#define regDIG1_HDMI_GENERIC_PACKET_CONTROL10 0x21d4 8405#define regDIG1_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX 2 8406#define regDIG1_HDMI_DB_CONTROL 0x21d5 8407#define regDIG1_HDMI_DB_CONTROL_BASE_IDX 2 8408#define regDIG1_HDMI_ACR_32_0 0x21d6 8409#define regDIG1_HDMI_ACR_32_0_BASE_IDX 2 8410#define regDIG1_HDMI_ACR_32_1 0x21d7 8411#define regDIG1_HDMI_ACR_32_1_BASE_IDX 2 8412#define regDIG1_HDMI_ACR_44_0 0x21d8 8413#define regDIG1_HDMI_ACR_44_0_BASE_IDX 2 8414#define regDIG1_HDMI_ACR_44_1 0x21d9 8415#define regDIG1_HDMI_ACR_44_1_BASE_IDX 2 8416#define regDIG1_HDMI_ACR_48_0 0x21da 8417#define regDIG1_HDMI_ACR_48_0_BASE_IDX 2 8418#define regDIG1_HDMI_ACR_48_1 0x21db 8419#define regDIG1_HDMI_ACR_48_1_BASE_IDX 2 8420#define regDIG1_HDMI_ACR_STATUS_0 0x21dc 8421#define regDIG1_HDMI_ACR_STATUS_0_BASE_IDX 2 8422#define regDIG1_HDMI_ACR_STATUS_1 0x21dd 8423#define regDIG1_HDMI_ACR_STATUS_1_BASE_IDX 2 8424#define regDIG1_AFMT_CNTL 0x21de 8425#define regDIG1_AFMT_CNTL_BASE_IDX 2 8426#define regDIG1_DIG_BE_CLK_CNTL 0x21df 8427#define regDIG1_DIG_BE_CLK_CNTL_BASE_IDX 2 8428#define regDIG1_DIG_BE_CNTL 0x21e0 8429#define regDIG1_DIG_BE_CNTL_BASE_IDX 2 8430#define regDIG1_DIG_BE_EN_CNTL 0x21e1 8431#define regDIG1_DIG_BE_EN_CNTL_BASE_IDX 2 8432#define regDIG1_TMDS_CNTL 0x2208 8433#define regDIG1_TMDS_CNTL_BASE_IDX 2 8434#define regDIG1_TMDS_CONTROL_CHAR 0x2209 8435#define regDIG1_TMDS_CONTROL_CHAR_BASE_IDX 2 8436#define regDIG1_TMDS_CONTROL0_FEEDBACK 0x220a 8437#define regDIG1_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2 8438#define regDIG1_TMDS_STEREOSYNC_CTL_SEL 0x220b 8439#define regDIG1_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2 8440#define regDIG1_TMDS_SYNC_CHAR_PATTERN_0_1 0x220c 8441#define regDIG1_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2 8442#define regDIG1_TMDS_SYNC_CHAR_PATTERN_2_3 0x220d 8443#define regDIG1_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2 8444#define regDIG1_TMDS_CTL_BITS 0x220f 8445#define regDIG1_TMDS_CTL_BITS_BASE_IDX 2 8446#define regDIG1_TMDS_DCBALANCER_CONTROL 0x2210 8447#define regDIG1_TMDS_DCBALANCER_CONTROL_BASE_IDX 2 8448#define regDIG1_TMDS_SYNC_DCBALANCE_CHAR 0x2211 8449#define regDIG1_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX 2 8450#define regDIG1_TMDS_CTL0_1_GEN_CNTL 0x2212 8451#define regDIG1_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2 8452#define regDIG1_TMDS_CTL2_3_GEN_CNTL 0x2213 8453#define regDIG1_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2 8454#define regDIG1_DIG_VERSION 0x2215 8455#define regDIG1_DIG_VERSION_BASE_IDX 2 8456 8457 8458// addressBlock: dce_dc_dio_dp1_dispdec 8459// base address: 0x490 8460#define regDP1_DP_LINK_CNTL 0x2242 8461#define regDP1_DP_LINK_CNTL_BASE_IDX 2 8462#define regDP1_DP_PIXEL_FORMAT 0x2243 8463#define regDP1_DP_PIXEL_FORMAT_BASE_IDX 2 8464#define regDP1_DP_MSA_COLORIMETRY 0x2244 8465#define regDP1_DP_MSA_COLORIMETRY_BASE_IDX 2 8466#define regDP1_DP_CONFIG 0x2245 8467#define regDP1_DP_CONFIG_BASE_IDX 2 8468#define regDP1_DP_VID_STREAM_CNTL 0x2246 8469#define regDP1_DP_VID_STREAM_CNTL_BASE_IDX 2 8470#define regDP1_DP_STEER_FIFO 0x2247 8471#define regDP1_DP_STEER_FIFO_BASE_IDX 2 8472#define regDP1_DP_MSA_MISC 0x2248 8473#define regDP1_DP_MSA_MISC_BASE_IDX 2 8474#define regDP1_DP_DPHY_INTERNAL_CTRL 0x2249 8475#define regDP1_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 8476#define regDP1_DP_VID_TIMING 0x224a 8477#define regDP1_DP_VID_TIMING_BASE_IDX 2 8478#define regDP1_DP_VID_N 0x224b 8479#define regDP1_DP_VID_N_BASE_IDX 2 8480#define regDP1_DP_VID_M 0x224c 8481#define regDP1_DP_VID_M_BASE_IDX 2 8482#define regDP1_DP_LINK_FRAMING_CNTL 0x224d 8483#define regDP1_DP_LINK_FRAMING_CNTL_BASE_IDX 2 8484#define regDP1_DP_HBR2_EYE_PATTERN 0x224e 8485#define regDP1_DP_HBR2_EYE_PATTERN_BASE_IDX 2 8486#define regDP1_DP_VID_MSA_VBID 0x224f 8487#define regDP1_DP_VID_MSA_VBID_BASE_IDX 2 8488#define regDP1_DP_VID_INTERRUPT_CNTL 0x2250 8489#define regDP1_DP_VID_INTERRUPT_CNTL_BASE_IDX 2 8490#define regDP1_DP_DPHY_CNTL 0x2251 8491#define regDP1_DP_DPHY_CNTL_BASE_IDX 2 8492#define regDP1_DP_DPHY_TRAINING_PATTERN_SEL 0x2252 8493#define regDP1_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2 8494#define regDP1_DP_DPHY_SYM0 0x2253 8495#define regDP1_DP_DPHY_SYM0_BASE_IDX 2 8496#define regDP1_DP_DPHY_SYM1 0x2254 8497#define regDP1_DP_DPHY_SYM1_BASE_IDX 2 8498#define regDP1_DP_DPHY_SYM2 0x2255 8499#define regDP1_DP_DPHY_SYM2_BASE_IDX 2 8500#define regDP1_DP_DPHY_8B10B_CNTL 0x2256 8501#define regDP1_DP_DPHY_8B10B_CNTL_BASE_IDX 2 8502#define regDP1_DP_DPHY_PRBS_CNTL 0x2257 8503#define regDP1_DP_DPHY_PRBS_CNTL_BASE_IDX 2 8504#define regDP1_DP_DPHY_SCRAM_CNTL 0x2258 8505#define regDP1_DP_DPHY_SCRAM_CNTL_BASE_IDX 2 8506#define regDP1_DP_DPHY_CRC_EN 0x2259 8507#define regDP1_DP_DPHY_CRC_EN_BASE_IDX 2 8508#define regDP1_DP_DPHY_CRC_CNTL 0x225a 8509#define regDP1_DP_DPHY_CRC_CNTL_BASE_IDX 2 8510#define regDP1_DP_DPHY_CRC_RESULT 0x225b 8511#define regDP1_DP_DPHY_CRC_RESULT_BASE_IDX 2 8512#define regDP1_DP_DPHY_CRC_MST_CNTL 0x225c 8513#define regDP1_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2 8514#define regDP1_DP_DPHY_CRC_MST_STATUS 0x225d 8515#define regDP1_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2 8516#define regDP1_DP_DPHY_FAST_TRAINING 0x225e 8517#define regDP1_DP_DPHY_FAST_TRAINING_BASE_IDX 2 8518#define regDP1_DP_DPHY_FAST_TRAINING_STATUS 0x225f 8519#define regDP1_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2 8520#define regDP1_DP_SEC_CNTL 0x2265 8521#define regDP1_DP_SEC_CNTL_BASE_IDX 2 8522#define regDP1_DP_SEC_CNTL1 0x2266 8523#define regDP1_DP_SEC_CNTL1_BASE_IDX 2 8524#define regDP1_DP_SEC_FRAMING1 0x2267 8525#define regDP1_DP_SEC_FRAMING1_BASE_IDX 2 8526#define regDP1_DP_SEC_FRAMING2 0x2268 8527#define regDP1_DP_SEC_FRAMING2_BASE_IDX 2 8528#define regDP1_DP_SEC_FRAMING3 0x2269 8529#define regDP1_DP_SEC_FRAMING3_BASE_IDX 2 8530#define regDP1_DP_SEC_FRAMING4 0x226a 8531#define regDP1_DP_SEC_FRAMING4_BASE_IDX 2 8532#define regDP1_DP_SEC_AUD_N 0x226b 8533#define regDP1_DP_SEC_AUD_N_BASE_IDX 2 8534#define regDP1_DP_SEC_AUD_N_READBACK 0x226c 8535#define regDP1_DP_SEC_AUD_N_READBACK_BASE_IDX 2 8536#define regDP1_DP_SEC_AUD_M 0x226d 8537#define regDP1_DP_SEC_AUD_M_BASE_IDX 2 8538#define regDP1_DP_SEC_AUD_M_READBACK 0x226e 8539#define regDP1_DP_SEC_AUD_M_READBACK_BASE_IDX 2 8540#define regDP1_DP_SEC_TIMESTAMP 0x226f 8541#define regDP1_DP_SEC_TIMESTAMP_BASE_IDX 2 8542#define regDP1_DP_SEC_PACKET_CNTL 0x2270 8543#define regDP1_DP_SEC_PACKET_CNTL_BASE_IDX 2 8544#define regDP1_DP_MSE_RATE_CNTL 0x2271 8545#define regDP1_DP_MSE_RATE_CNTL_BASE_IDX 2 8546#define regDP1_DP_MSE_RATE_UPDATE 0x2273 8547#define regDP1_DP_MSE_RATE_UPDATE_BASE_IDX 2 8548#define regDP1_DP_MSE_SAT0 0x2274 8549#define regDP1_DP_MSE_SAT0_BASE_IDX 2 8550#define regDP1_DP_MSE_SAT1 0x2275 8551#define regDP1_DP_MSE_SAT1_BASE_IDX 2 8552#define regDP1_DP_MSE_SAT2 0x2276 8553#define regDP1_DP_MSE_SAT2_BASE_IDX 2 8554#define regDP1_DP_MSE_SAT_UPDATE 0x2277 8555#define regDP1_DP_MSE_SAT_UPDATE_BASE_IDX 2 8556#define regDP1_DP_MSE_LINK_TIMING 0x2278 8557#define regDP1_DP_MSE_LINK_TIMING_BASE_IDX 2 8558#define regDP1_DP_MSE_MISC_CNTL 0x2279 8559#define regDP1_DP_MSE_MISC_CNTL_BASE_IDX 2 8560#define regDP1_DP_DPHY_BS_SR_SWAP_CNTL 0x227e 8561#define regDP1_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2 8562#define regDP1_DP_DPHY_HBR2_PATTERN_CONTROL 0x227f 8563#define regDP1_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2 8564#define regDP1_DP_MSE_SAT0_STATUS 0x2281 8565#define regDP1_DP_MSE_SAT0_STATUS_BASE_IDX 2 8566#define regDP1_DP_MSE_SAT1_STATUS 0x2282 8567#define regDP1_DP_MSE_SAT1_STATUS_BASE_IDX 2 8568#define regDP1_DP_MSE_SAT2_STATUS 0x2283 8569#define regDP1_DP_MSE_SAT2_STATUS_BASE_IDX 2 8570#define regDP1_DP_DPIA_SPARE 0x2284 8571#define regDP1_DP_DPIA_SPARE_BASE_IDX 2 8572#define regDP1_DP_MSA_TIMING_PARAM1 0x2286 8573#define regDP1_DP_MSA_TIMING_PARAM1_BASE_IDX 2 8574#define regDP1_DP_MSA_TIMING_PARAM2 0x2287 8575#define regDP1_DP_MSA_TIMING_PARAM2_BASE_IDX 2 8576#define regDP1_DP_MSA_TIMING_PARAM3 0x2288 8577#define regDP1_DP_MSA_TIMING_PARAM3_BASE_IDX 2 8578#define regDP1_DP_MSA_TIMING_PARAM4 0x2289 8579#define regDP1_DP_MSA_TIMING_PARAM4_BASE_IDX 2 8580#define regDP1_DP_MSO_CNTL 0x228a 8581#define regDP1_DP_MSO_CNTL_BASE_IDX 2 8582#define regDP1_DP_MSO_CNTL1 0x228b 8583#define regDP1_DP_MSO_CNTL1_BASE_IDX 2 8584#define regDP1_DP_DSC_CNTL 0x228c 8585#define regDP1_DP_DSC_CNTL_BASE_IDX 2 8586#define regDP1_DP_SEC_CNTL2 0x228d 8587#define regDP1_DP_SEC_CNTL2_BASE_IDX 2 8588#define regDP1_DP_SEC_CNTL3 0x228e 8589#define regDP1_DP_SEC_CNTL3_BASE_IDX 2 8590#define regDP1_DP_SEC_CNTL4 0x228f 8591#define regDP1_DP_SEC_CNTL4_BASE_IDX 2 8592#define regDP1_DP_SEC_CNTL5 0x2290 8593#define regDP1_DP_SEC_CNTL5_BASE_IDX 2 8594#define regDP1_DP_SEC_CNTL6 0x2291 8595#define regDP1_DP_SEC_CNTL6_BASE_IDX 2 8596#define regDP1_DP_SEC_CNTL7 0x2292 8597#define regDP1_DP_SEC_CNTL7_BASE_IDX 2 8598#define regDP1_DP_DB_CNTL 0x2293 8599#define regDP1_DP_DB_CNTL_BASE_IDX 2 8600#define regDP1_DP_MSA_VBID_MISC 0x2294 8601#define regDP1_DP_MSA_VBID_MISC_BASE_IDX 2 8602#define regDP1_DP_SEC_METADATA_TRANSMISSION 0x2295 8603#define regDP1_DP_SEC_METADATA_TRANSMISSION_BASE_IDX 2 8604#define regDP1_DP_ALPM_CNTL 0x2297 8605#define regDP1_DP_ALPM_CNTL_BASE_IDX 2 8606#define regDP1_DP_GSP8_CNTL 0x2298 8607#define regDP1_DP_GSP8_CNTL_BASE_IDX 2 8608#define regDP1_DP_GSP9_CNTL 0x2299 8609#define regDP1_DP_GSP9_CNTL_BASE_IDX 2 8610#define regDP1_DP_GSP10_CNTL 0x229a 8611#define regDP1_DP_GSP10_CNTL_BASE_IDX 2 8612#define regDP1_DP_GSP11_CNTL 0x229b 8613#define regDP1_DP_GSP11_CNTL_BASE_IDX 2 8614#define regDP1_DP_GSP_EN_DB_STATUS 0x229c 8615#define regDP1_DP_GSP_EN_DB_STATUS_BASE_IDX 2 8616#define regDP1_DP_AUXLESS_ALPM_CNTL1 0x229d 8617#define regDP1_DP_AUXLESS_ALPM_CNTL1_BASE_IDX 2 8618#define regDP1_DP_AUXLESS_ALPM_CNTL2 0x229e 8619#define regDP1_DP_AUXLESS_ALPM_CNTL2_BASE_IDX 2 8620#define regDP1_DP_AUXLESS_ALPM_CNTL3 0x229f 8621#define regDP1_DP_AUXLESS_ALPM_CNTL3_BASE_IDX 2 8622#define regDP1_DP_AUXLESS_ALPM_CNTL4 0x22a0 8623#define regDP1_DP_AUXLESS_ALPM_CNTL4_BASE_IDX 2 8624#define regDP1_DP_AUXLESS_ALPM_CNTL5 0x22a1 8625#define regDP1_DP_AUXLESS_ALPM_CNTL5_BASE_IDX 2 8626#define regDP1_DP_STREAM_SYMBOL_COUNT_STATUS 0x22a2 8627#define regDP1_DP_STREAM_SYMBOL_COUNT_STATUS_BASE_IDX 2 8628#define regDP1_DP_STREAM_SYMBOL_COUNT_CONTROL 0x22a3 8629#define regDP1_DP_STREAM_SYMBOL_COUNT_CONTROL_BASE_IDX 2 8630#define regDP1_DP_LINK_SYMBOL_COUNT_STATUS0 0x22a4 8631#define regDP1_DP_LINK_SYMBOL_COUNT_STATUS0_BASE_IDX 2 8632#define regDP1_DP_LINK_SYMBOL_COUNT_STATUS1 0x22a5 8633#define regDP1_DP_LINK_SYMBOL_COUNT_STATUS1_BASE_IDX 2 8634#define regDP1_DP_LINK_SYMBOL_COUNT_CONTROL 0x22a6 8635#define regDP1_DP_LINK_SYMBOL_COUNT_CONTROL_BASE_IDX 2 8636 8637 8638// addressBlock: dce_dc_dio_dig2_vpg_vpg_dispdec 8639// base address: 0x15dc0 8640#define regVPG2_VPG_GENERIC_PACKET_ACCESS_CTRL 0x22b0 8641#define regVPG2_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2 8642#define regVPG2_VPG_GENERIC_PACKET_DATA 0x22b1 8643#define regVPG2_VPG_GENERIC_PACKET_DATA_BASE_IDX 2 8644#define regVPG2_VPG_GSP_FRAME_UPDATE_CTRL 0x22b2 8645#define regVPG2_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2 8646#define regVPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x22b3 8647#define regVPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2 8648#define regVPG2_VPG_GENERIC_STATUS 0x22b4 8649#define regVPG2_VPG_GENERIC_STATUS_BASE_IDX 2 8650#define regVPG2_VPG_MEM_PWR 0x22b5 8651#define regVPG2_VPG_MEM_PWR_BASE_IDX 2 8652#define regVPG2_VPG_ISRC1_2_ACCESS_CTRL 0x22b6 8653#define regVPG2_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2 8654#define regVPG2_VPG_ISRC1_2_DATA 0x22b7 8655#define regVPG2_VPG_ISRC1_2_DATA_BASE_IDX 2 8656#define regVPG2_VPG_MPEG_INFO0 0x22b8 8657#define regVPG2_VPG_MPEG_INFO0_BASE_IDX 2 8658#define regVPG2_VPG_MPEG_INFO1 0x22b9 8659#define regVPG2_VPG_MPEG_INFO1_BASE_IDX 2 8660 8661 8662// addressBlock: dce_dc_dio_dig2_afmt_afmt_dispdec 8663// base address: 0x15dec 8664#define regAFMT2_AFMT_ACP 0x22bb 8665#define regAFMT2_AFMT_ACP_BASE_IDX 2 8666#define regAFMT2_AFMT_VBI_PACKET_CONTROL 0x22bc 8667#define regAFMT2_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2 8668#define regAFMT2_AFMT_AUDIO_PACKET_CONTROL2 0x22bd 8669#define regAFMT2_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2 8670#define regAFMT2_AFMT_AUDIO_INFO0 0x22be 8671#define regAFMT2_AFMT_AUDIO_INFO0_BASE_IDX 2 8672#define regAFMT2_AFMT_AUDIO_INFO1 0x22bf 8673#define regAFMT2_AFMT_AUDIO_INFO1_BASE_IDX 2 8674#define regAFMT2_AFMT_60958_0 0x22c0 8675#define regAFMT2_AFMT_60958_0_BASE_IDX 2 8676#define regAFMT2_AFMT_60958_1 0x22c1 8677#define regAFMT2_AFMT_60958_1_BASE_IDX 2 8678#define regAFMT2_AFMT_AUDIO_CRC_CONTROL 0x22c2 8679#define regAFMT2_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2 8680#define regAFMT2_AFMT_RAMP_CONTROL0 0x22c3 8681#define regAFMT2_AFMT_RAMP_CONTROL0_BASE_IDX 2 8682#define regAFMT2_AFMT_RAMP_CONTROL1 0x22c4 8683#define regAFMT2_AFMT_RAMP_CONTROL1_BASE_IDX 2 8684#define regAFMT2_AFMT_RAMP_CONTROL2 0x22c5 8685#define regAFMT2_AFMT_RAMP_CONTROL2_BASE_IDX 2 8686#define regAFMT2_AFMT_RAMP_CONTROL3 0x22c6 8687#define regAFMT2_AFMT_RAMP_CONTROL3_BASE_IDX 2 8688#define regAFMT2_AFMT_60958_2 0x22c7 8689#define regAFMT2_AFMT_60958_2_BASE_IDX 2 8690#define regAFMT2_AFMT_AUDIO_CRC_RESULT 0x22c8 8691#define regAFMT2_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2 8692#define regAFMT2_AFMT_STATUS 0x22c9 8693#define regAFMT2_AFMT_STATUS_BASE_IDX 2 8694#define regAFMT2_AFMT_AUDIO_PACKET_CONTROL 0x22ca 8695#define regAFMT2_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2 8696#define regAFMT2_AFMT_INFOFRAME_CONTROL0 0x22cb 8697#define regAFMT2_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2 8698#define regAFMT2_AFMT_INTERRUPT_STATUS 0x22cc 8699#define regAFMT2_AFMT_INTERRUPT_STATUS_BASE_IDX 2 8700#define regAFMT2_AFMT_AUDIO_SRC_CONTROL 0x22cd 8701#define regAFMT2_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2 8702#define regAFMT2_AFMT_MEM_PWR 0x22cf 8703#define regAFMT2_AFMT_MEM_PWR_BASE_IDX 2 8704 8705 8706// addressBlock: dce_dc_dio_dig2_dme_dme_dispdec 8707// base address: 0x15e64 8708#define regDME2_DME_CONTROL 0x22d9 8709#define regDME2_DME_CONTROL_BASE_IDX 2 8710#define regDME2_DME_MEMORY_CONTROL 0x22da 8711#define regDME2_DME_MEMORY_CONTROL_BASE_IDX 2 8712 8713 8714// addressBlock: dce_dc_dio_dig2_dispdec 8715// base address: 0x920 8716#define regDIG2_DIG_FE_CNTL 0x22db 8717#define regDIG2_DIG_FE_CNTL_BASE_IDX 2 8718#define regDIG2_DIG_FE_CLK_CNTL 0x22dc 8719#define regDIG2_DIG_FE_CLK_CNTL_BASE_IDX 2 8720#define regDIG2_DIG_FE_EN_CNTL 0x22dd 8721#define regDIG2_DIG_FE_EN_CNTL_BASE_IDX 2 8722#define regDIG2_DIG_OUTPUT_CRC_CNTL 0x22de 8723#define regDIG2_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2 8724#define regDIG2_DIG_OUTPUT_CRC_RESULT 0x22df 8725#define regDIG2_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2 8726#define regDIG2_DIG_CLOCK_PATTERN 0x22e0 8727#define regDIG2_DIG_CLOCK_PATTERN_BASE_IDX 2 8728#define regDIG2_DIG_TEST_PATTERN 0x22e1 8729#define regDIG2_DIG_TEST_PATTERN_BASE_IDX 2 8730#define regDIG2_DIG_RANDOM_PATTERN_SEED 0x22e2 8731#define regDIG2_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2 8732#define regDIG2_DIG_FIFO_CTRL0 0x22e3 8733#define regDIG2_DIG_FIFO_CTRL0_BASE_IDX 2 8734#define regDIG2_DIG_FIFO_CTRL1 0x22e4 8735#define regDIG2_DIG_FIFO_CTRL1_BASE_IDX 2 8736#define regDIG2_HDMI_METADATA_PACKET_CONTROL 0x22e5 8737#define regDIG2_HDMI_METADATA_PACKET_CONTROL_BASE_IDX 2 8738#define regDIG2_HDMI_CONTROL 0x22e6 8739#define regDIG2_HDMI_CONTROL_BASE_IDX 2 8740#define regDIG2_HDMI_STATUS 0x22e7 8741#define regDIG2_HDMI_STATUS_BASE_IDX 2 8742#define regDIG2_HDMI_AUDIO_PACKET_CONTROL 0x22e8 8743#define regDIG2_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2 8744#define regDIG2_HDMI_ACR_PACKET_CONTROL 0x22e9 8745#define regDIG2_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2 8746#define regDIG2_HDMI_VBI_PACKET_CONTROL 0x22ea 8747#define regDIG2_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2 8748#define regDIG2_HDMI_INFOFRAME_CONTROL0 0x22eb 8749#define regDIG2_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2 8750#define regDIG2_HDMI_INFOFRAME_CONTROL1 0x22ec 8751#define regDIG2_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2 8752#define regDIG2_HDMI_GENERIC_PACKET_CONTROL0 0x22ed 8753#define regDIG2_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2 8754#define regDIG2_HDMI_GENERIC_PACKET_CONTROL6 0x22ee 8755#define regDIG2_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX 2 8756#define regDIG2_HDMI_GENERIC_PACKET_CONTROL5 0x22ef 8757#define regDIG2_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX 2 8758#define regDIG2_HDMI_GC 0x22f0 8759#define regDIG2_HDMI_GC_BASE_IDX 2 8760#define regDIG2_HDMI_GENERIC_PACKET_CONTROL1 0x22f1 8761#define regDIG2_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2 8762#define regDIG2_HDMI_GENERIC_PACKET_CONTROL2 0x22f2 8763#define regDIG2_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2 8764#define regDIG2_HDMI_GENERIC_PACKET_CONTROL3 0x22f3 8765#define regDIG2_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2 8766#define regDIG2_HDMI_GENERIC_PACKET_CONTROL4 0x22f4 8767#define regDIG2_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX 2 8768#define regDIG2_HDMI_GENERIC_PACKET_CONTROL7 0x22f5 8769#define regDIG2_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX 2 8770#define regDIG2_HDMI_GENERIC_PACKET_CONTROL8 0x22f6 8771#define regDIG2_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX 2 8772#define regDIG2_HDMI_GENERIC_PACKET_CONTROL9 0x22f7 8773#define regDIG2_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX 2 8774#define regDIG2_HDMI_GENERIC_PACKET_CONTROL10 0x22f8 8775#define regDIG2_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX 2 8776#define regDIG2_HDMI_DB_CONTROL 0x22f9 8777#define regDIG2_HDMI_DB_CONTROL_BASE_IDX 2 8778#define regDIG2_HDMI_ACR_32_0 0x22fa 8779#define regDIG2_HDMI_ACR_32_0_BASE_IDX 2 8780#define regDIG2_HDMI_ACR_32_1 0x22fb 8781#define regDIG2_HDMI_ACR_32_1_BASE_IDX 2 8782#define regDIG2_HDMI_ACR_44_0 0x22fc 8783#define regDIG2_HDMI_ACR_44_0_BASE_IDX 2 8784#define regDIG2_HDMI_ACR_44_1 0x22fd 8785#define regDIG2_HDMI_ACR_44_1_BASE_IDX 2 8786#define regDIG2_HDMI_ACR_48_0 0x22fe 8787#define regDIG2_HDMI_ACR_48_0_BASE_IDX 2 8788#define regDIG2_HDMI_ACR_48_1 0x22ff 8789#define regDIG2_HDMI_ACR_48_1_BASE_IDX 2 8790#define regDIG2_HDMI_ACR_STATUS_0 0x2300 8791#define regDIG2_HDMI_ACR_STATUS_0_BASE_IDX 2 8792#define regDIG2_HDMI_ACR_STATUS_1 0x2301 8793#define regDIG2_HDMI_ACR_STATUS_1_BASE_IDX 2 8794#define regDIG2_AFMT_CNTL 0x2302 8795#define regDIG2_AFMT_CNTL_BASE_IDX 2 8796#define regDIG2_DIG_BE_CLK_CNTL 0x2303 8797#define regDIG2_DIG_BE_CLK_CNTL_BASE_IDX 2 8798#define regDIG2_DIG_BE_CNTL 0x2304 8799#define regDIG2_DIG_BE_CNTL_BASE_IDX 2 8800#define regDIG2_DIG_BE_EN_CNTL 0x2305 8801#define regDIG2_DIG_BE_EN_CNTL_BASE_IDX 2 8802#define regDIG2_TMDS_CNTL 0x232c 8803#define regDIG2_TMDS_CNTL_BASE_IDX 2 8804#define regDIG2_TMDS_CONTROL_CHAR 0x232d 8805#define regDIG2_TMDS_CONTROL_CHAR_BASE_IDX 2 8806#define regDIG2_TMDS_CONTROL0_FEEDBACK 0x232e 8807#define regDIG2_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2 8808#define regDIG2_TMDS_STEREOSYNC_CTL_SEL 0x232f 8809#define regDIG2_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2 8810#define regDIG2_TMDS_SYNC_CHAR_PATTERN_0_1 0x2330 8811#define regDIG2_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2 8812#define regDIG2_TMDS_SYNC_CHAR_PATTERN_2_3 0x2331 8813#define regDIG2_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2 8814#define regDIG2_TMDS_CTL_BITS 0x2333 8815#define regDIG2_TMDS_CTL_BITS_BASE_IDX 2 8816#define regDIG2_TMDS_DCBALANCER_CONTROL 0x2334 8817#define regDIG2_TMDS_DCBALANCER_CONTROL_BASE_IDX 2 8818#define regDIG2_TMDS_SYNC_DCBALANCE_CHAR 0x2335 8819#define regDIG2_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX 2 8820#define regDIG2_TMDS_CTL0_1_GEN_CNTL 0x2336 8821#define regDIG2_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2 8822#define regDIG2_TMDS_CTL2_3_GEN_CNTL 0x2337 8823#define regDIG2_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2 8824#define regDIG2_DIG_VERSION 0x2339 8825#define regDIG2_DIG_VERSION_BASE_IDX 2 8826 8827 8828// addressBlock: dce_dc_dio_dp2_dispdec 8829// base address: 0x920 8830#define regDP2_DP_LINK_CNTL 0x2366 8831#define regDP2_DP_LINK_CNTL_BASE_IDX 2 8832#define regDP2_DP_PIXEL_FORMAT 0x2367 8833#define regDP2_DP_PIXEL_FORMAT_BASE_IDX 2 8834#define regDP2_DP_MSA_COLORIMETRY 0x2368 8835#define regDP2_DP_MSA_COLORIMETRY_BASE_IDX 2 8836#define regDP2_DP_CONFIG 0x2369 8837#define regDP2_DP_CONFIG_BASE_IDX 2 8838#define regDP2_DP_VID_STREAM_CNTL 0x236a 8839#define regDP2_DP_VID_STREAM_CNTL_BASE_IDX 2 8840#define regDP2_DP_STEER_FIFO 0x236b 8841#define regDP2_DP_STEER_FIFO_BASE_IDX 2 8842#define regDP2_DP_MSA_MISC 0x236c 8843#define regDP2_DP_MSA_MISC_BASE_IDX 2 8844#define regDP2_DP_DPHY_INTERNAL_CTRL 0x236d 8845#define regDP2_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 8846#define regDP2_DP_VID_TIMING 0x236e 8847#define regDP2_DP_VID_TIMING_BASE_IDX 2 8848#define regDP2_DP_VID_N 0x236f 8849#define regDP2_DP_VID_N_BASE_IDX 2 8850#define regDP2_DP_VID_M 0x2370 8851#define regDP2_DP_VID_M_BASE_IDX 2 8852#define regDP2_DP_LINK_FRAMING_CNTL 0x2371 8853#define regDP2_DP_LINK_FRAMING_CNTL_BASE_IDX 2 8854#define regDP2_DP_HBR2_EYE_PATTERN 0x2372 8855#define regDP2_DP_HBR2_EYE_PATTERN_BASE_IDX 2 8856#define regDP2_DP_VID_MSA_VBID 0x2373 8857#define regDP2_DP_VID_MSA_VBID_BASE_IDX 2 8858#define regDP2_DP_VID_INTERRUPT_CNTL 0x2374 8859#define regDP2_DP_VID_INTERRUPT_CNTL_BASE_IDX 2 8860#define regDP2_DP_DPHY_CNTL 0x2375 8861#define regDP2_DP_DPHY_CNTL_BASE_IDX 2 8862#define regDP2_DP_DPHY_TRAINING_PATTERN_SEL 0x2376 8863#define regDP2_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2 8864#define regDP2_DP_DPHY_SYM0 0x2377 8865#define regDP2_DP_DPHY_SYM0_BASE_IDX 2 8866#define regDP2_DP_DPHY_SYM1 0x2378 8867#define regDP2_DP_DPHY_SYM1_BASE_IDX 2 8868#define regDP2_DP_DPHY_SYM2 0x2379 8869#define regDP2_DP_DPHY_SYM2_BASE_IDX 2 8870#define regDP2_DP_DPHY_8B10B_CNTL 0x237a 8871#define regDP2_DP_DPHY_8B10B_CNTL_BASE_IDX 2 8872#define regDP2_DP_DPHY_PRBS_CNTL 0x237b 8873#define regDP2_DP_DPHY_PRBS_CNTL_BASE_IDX 2 8874#define regDP2_DP_DPHY_SCRAM_CNTL 0x237c 8875#define regDP2_DP_DPHY_SCRAM_CNTL_BASE_IDX 2 8876#define regDP2_DP_DPHY_CRC_EN 0x237d 8877#define regDP2_DP_DPHY_CRC_EN_BASE_IDX 2 8878#define regDP2_DP_DPHY_CRC_CNTL 0x237e 8879#define regDP2_DP_DPHY_CRC_CNTL_BASE_IDX 2 8880#define regDP2_DP_DPHY_CRC_RESULT 0x237f 8881#define regDP2_DP_DPHY_CRC_RESULT_BASE_IDX 2 8882#define regDP2_DP_DPHY_CRC_MST_CNTL 0x2380 8883#define regDP2_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2 8884#define regDP2_DP_DPHY_CRC_MST_STATUS 0x2381 8885#define regDP2_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2 8886#define regDP2_DP_DPHY_FAST_TRAINING 0x2382 8887#define regDP2_DP_DPHY_FAST_TRAINING_BASE_IDX 2 8888#define regDP2_DP_DPHY_FAST_TRAINING_STATUS 0x2383 8889#define regDP2_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2 8890#define regDP2_DP_SEC_CNTL 0x2389 8891#define regDP2_DP_SEC_CNTL_BASE_IDX 2 8892#define regDP2_DP_SEC_CNTL1 0x238a 8893#define regDP2_DP_SEC_CNTL1_BASE_IDX 2 8894#define regDP2_DP_SEC_FRAMING1 0x238b 8895#define regDP2_DP_SEC_FRAMING1_BASE_IDX 2 8896#define regDP2_DP_SEC_FRAMING2 0x238c 8897#define regDP2_DP_SEC_FRAMING2_BASE_IDX 2 8898#define regDP2_DP_SEC_FRAMING3 0x238d 8899#define regDP2_DP_SEC_FRAMING3_BASE_IDX 2 8900#define regDP2_DP_SEC_FRAMING4 0x238e 8901#define regDP2_DP_SEC_FRAMING4_BASE_IDX 2 8902#define regDP2_DP_SEC_AUD_N 0x238f 8903#define regDP2_DP_SEC_AUD_N_BASE_IDX 2 8904#define regDP2_DP_SEC_AUD_N_READBACK 0x2390 8905#define regDP2_DP_SEC_AUD_N_READBACK_BASE_IDX 2 8906#define regDP2_DP_SEC_AUD_M 0x2391 8907#define regDP2_DP_SEC_AUD_M_BASE_IDX 2 8908#define regDP2_DP_SEC_AUD_M_READBACK 0x2392 8909#define regDP2_DP_SEC_AUD_M_READBACK_BASE_IDX 2 8910#define regDP2_DP_SEC_TIMESTAMP 0x2393 8911#define regDP2_DP_SEC_TIMESTAMP_BASE_IDX 2 8912#define regDP2_DP_SEC_PACKET_CNTL 0x2394 8913#define regDP2_DP_SEC_PACKET_CNTL_BASE_IDX 2 8914#define regDP2_DP_MSE_RATE_CNTL 0x2395 8915#define regDP2_DP_MSE_RATE_CNTL_BASE_IDX 2 8916#define regDP2_DP_MSE_RATE_UPDATE 0x2397 8917#define regDP2_DP_MSE_RATE_UPDATE_BASE_IDX 2 8918#define regDP2_DP_MSE_SAT0 0x2398 8919#define regDP2_DP_MSE_SAT0_BASE_IDX 2 8920#define regDP2_DP_MSE_SAT1 0x2399 8921#define regDP2_DP_MSE_SAT1_BASE_IDX 2 8922#define regDP2_DP_MSE_SAT2 0x239a 8923#define regDP2_DP_MSE_SAT2_BASE_IDX 2 8924#define regDP2_DP_MSE_SAT_UPDATE 0x239b 8925#define regDP2_DP_MSE_SAT_UPDATE_BASE_IDX 2 8926#define regDP2_DP_MSE_LINK_TIMING 0x239c 8927#define regDP2_DP_MSE_LINK_TIMING_BASE_IDX 2 8928#define regDP2_DP_MSE_MISC_CNTL 0x239d 8929#define regDP2_DP_MSE_MISC_CNTL_BASE_IDX 2 8930#define regDP2_DP_DPHY_BS_SR_SWAP_CNTL 0x23a2 8931#define regDP2_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2 8932#define regDP2_DP_DPHY_HBR2_PATTERN_CONTROL 0x23a3 8933#define regDP2_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2 8934#define regDP2_DP_MSE_SAT0_STATUS 0x23a5 8935#define regDP2_DP_MSE_SAT0_STATUS_BASE_IDX 2 8936#define regDP2_DP_MSE_SAT1_STATUS 0x23a6 8937#define regDP2_DP_MSE_SAT1_STATUS_BASE_IDX 2 8938#define regDP2_DP_MSE_SAT2_STATUS 0x23a7 8939#define regDP2_DP_MSE_SAT2_STATUS_BASE_IDX 2 8940#define regDP2_DP_DPIA_SPARE 0x23a8 8941#define regDP2_DP_DPIA_SPARE_BASE_IDX 2 8942#define regDP2_DP_MSA_TIMING_PARAM1 0x23aa 8943#define regDP2_DP_MSA_TIMING_PARAM1_BASE_IDX 2 8944#define regDP2_DP_MSA_TIMING_PARAM2 0x23ab 8945#define regDP2_DP_MSA_TIMING_PARAM2_BASE_IDX 2 8946#define regDP2_DP_MSA_TIMING_PARAM3 0x23ac 8947#define regDP2_DP_MSA_TIMING_PARAM3_BASE_IDX 2 8948#define regDP2_DP_MSA_TIMING_PARAM4 0x23ad 8949#define regDP2_DP_MSA_TIMING_PARAM4_BASE_IDX 2 8950#define regDP2_DP_MSO_CNTL 0x23ae 8951#define regDP2_DP_MSO_CNTL_BASE_IDX 2 8952#define regDP2_DP_MSO_CNTL1 0x23af 8953#define regDP2_DP_MSO_CNTL1_BASE_IDX 2 8954#define regDP2_DP_DSC_CNTL 0x23b0 8955#define regDP2_DP_DSC_CNTL_BASE_IDX 2 8956#define regDP2_DP_SEC_CNTL2 0x23b1 8957#define regDP2_DP_SEC_CNTL2_BASE_IDX 2 8958#define regDP2_DP_SEC_CNTL3 0x23b2 8959#define regDP2_DP_SEC_CNTL3_BASE_IDX 2 8960#define regDP2_DP_SEC_CNTL4 0x23b3 8961#define regDP2_DP_SEC_CNTL4_BASE_IDX 2 8962#define regDP2_DP_SEC_CNTL5 0x23b4 8963#define regDP2_DP_SEC_CNTL5_BASE_IDX 2 8964#define regDP2_DP_SEC_CNTL6 0x23b5 8965#define regDP2_DP_SEC_CNTL6_BASE_IDX 2 8966#define regDP2_DP_SEC_CNTL7 0x23b6 8967#define regDP2_DP_SEC_CNTL7_BASE_IDX 2 8968#define regDP2_DP_DB_CNTL 0x23b7 8969#define regDP2_DP_DB_CNTL_BASE_IDX 2 8970#define regDP2_DP_MSA_VBID_MISC 0x23b8 8971#define regDP2_DP_MSA_VBID_MISC_BASE_IDX 2 8972#define regDP2_DP_SEC_METADATA_TRANSMISSION 0x23b9 8973#define regDP2_DP_SEC_METADATA_TRANSMISSION_BASE_IDX 2 8974#define regDP2_DP_ALPM_CNTL 0x23bb 8975#define regDP2_DP_ALPM_CNTL_BASE_IDX 2 8976#define regDP2_DP_GSP8_CNTL 0x23bc 8977#define regDP2_DP_GSP8_CNTL_BASE_IDX 2 8978#define regDP2_DP_GSP9_CNTL 0x23bd 8979#define regDP2_DP_GSP9_CNTL_BASE_IDX 2 8980#define regDP2_DP_GSP10_CNTL 0x23be 8981#define regDP2_DP_GSP10_CNTL_BASE_IDX 2 8982#define regDP2_DP_GSP11_CNTL 0x23bf 8983#define regDP2_DP_GSP11_CNTL_BASE_IDX 2 8984#define regDP2_DP_GSP_EN_DB_STATUS 0x23c0 8985#define regDP2_DP_GSP_EN_DB_STATUS_BASE_IDX 2 8986#define regDP2_DP_AUXLESS_ALPM_CNTL1 0x23c1 8987#define regDP2_DP_AUXLESS_ALPM_CNTL1_BASE_IDX 2 8988#define regDP2_DP_AUXLESS_ALPM_CNTL2 0x23c2 8989#define regDP2_DP_AUXLESS_ALPM_CNTL2_BASE_IDX 2 8990#define regDP2_DP_AUXLESS_ALPM_CNTL3 0x23c3 8991#define regDP2_DP_AUXLESS_ALPM_CNTL3_BASE_IDX 2 8992#define regDP2_DP_AUXLESS_ALPM_CNTL4 0x23c4 8993#define regDP2_DP_AUXLESS_ALPM_CNTL4_BASE_IDX 2 8994#define regDP2_DP_AUXLESS_ALPM_CNTL5 0x23c5 8995#define regDP2_DP_AUXLESS_ALPM_CNTL5_BASE_IDX 2 8996#define regDP2_DP_STREAM_SYMBOL_COUNT_STATUS 0x23c6 8997#define regDP2_DP_STREAM_SYMBOL_COUNT_STATUS_BASE_IDX 2 8998#define regDP2_DP_STREAM_SYMBOL_COUNT_CONTROL 0x23c7 8999#define regDP2_DP_STREAM_SYMBOL_COUNT_CONTROL_BASE_IDX 2 9000#define regDP2_DP_LINK_SYMBOL_COUNT_STATUS0 0x23c8 9001#define regDP2_DP_LINK_SYMBOL_COUNT_STATUS0_BASE_IDX 2 9002#define regDP2_DP_LINK_SYMBOL_COUNT_STATUS1 0x23c9 9003#define regDP2_DP_LINK_SYMBOL_COUNT_STATUS1_BASE_IDX 2 9004#define regDP2_DP_LINK_SYMBOL_COUNT_CONTROL 0x23ca 9005#define regDP2_DP_LINK_SYMBOL_COUNT_CONTROL_BASE_IDX 2 9006 9007 9008// addressBlock: dce_dc_dio_dig3_vpg_vpg_dispdec 9009// base address: 0x16250 9010#define regVPG3_VPG_GENERIC_PACKET_ACCESS_CTRL 0x23d4 9011#define regVPG3_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2 9012#define regVPG3_VPG_GENERIC_PACKET_DATA 0x23d5 9013#define regVPG3_VPG_GENERIC_PACKET_DATA_BASE_IDX 2 9014#define regVPG3_VPG_GSP_FRAME_UPDATE_CTRL 0x23d6 9015#define regVPG3_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2 9016#define regVPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x23d7 9017#define regVPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2 9018#define regVPG3_VPG_GENERIC_STATUS 0x23d8 9019#define regVPG3_VPG_GENERIC_STATUS_BASE_IDX 2 9020#define regVPG3_VPG_MEM_PWR 0x23d9 9021#define regVPG3_VPG_MEM_PWR_BASE_IDX 2 9022#define regVPG3_VPG_ISRC1_2_ACCESS_CTRL 0x23da 9023#define regVPG3_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2 9024#define regVPG3_VPG_ISRC1_2_DATA 0x23db 9025#define regVPG3_VPG_ISRC1_2_DATA_BASE_IDX 2 9026#define regVPG3_VPG_MPEG_INFO0 0x23dc 9027#define regVPG3_VPG_MPEG_INFO0_BASE_IDX 2 9028#define regVPG3_VPG_MPEG_INFO1 0x23dd 9029#define regVPG3_VPG_MPEG_INFO1_BASE_IDX 2 9030 9031 9032// addressBlock: dce_dc_dio_dig3_afmt_afmt_dispdec 9033// base address: 0x1627c 9034#define regAFMT3_AFMT_ACP 0x23df 9035#define regAFMT3_AFMT_ACP_BASE_IDX 2 9036#define regAFMT3_AFMT_VBI_PACKET_CONTROL 0x23e0 9037#define regAFMT3_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2 9038#define regAFMT3_AFMT_AUDIO_PACKET_CONTROL2 0x23e1 9039#define regAFMT3_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2 9040#define regAFMT3_AFMT_AUDIO_INFO0 0x23e2 9041#define regAFMT3_AFMT_AUDIO_INFO0_BASE_IDX 2 9042#define regAFMT3_AFMT_AUDIO_INFO1 0x23e3 9043#define regAFMT3_AFMT_AUDIO_INFO1_BASE_IDX 2 9044#define regAFMT3_AFMT_60958_0 0x23e4 9045#define regAFMT3_AFMT_60958_0_BASE_IDX 2 9046#define regAFMT3_AFMT_60958_1 0x23e5 9047#define regAFMT3_AFMT_60958_1_BASE_IDX 2 9048#define regAFMT3_AFMT_AUDIO_CRC_CONTROL 0x23e6 9049#define regAFMT3_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2 9050#define regAFMT3_AFMT_RAMP_CONTROL0 0x23e7 9051#define regAFMT3_AFMT_RAMP_CONTROL0_BASE_IDX 2 9052#define regAFMT3_AFMT_RAMP_CONTROL1 0x23e8 9053#define regAFMT3_AFMT_RAMP_CONTROL1_BASE_IDX 2 9054#define regAFMT3_AFMT_RAMP_CONTROL2 0x23e9 9055#define regAFMT3_AFMT_RAMP_CONTROL2_BASE_IDX 2 9056#define regAFMT3_AFMT_RAMP_CONTROL3 0x23ea 9057#define regAFMT3_AFMT_RAMP_CONTROL3_BASE_IDX 2 9058#define regAFMT3_AFMT_60958_2 0x23eb 9059#define regAFMT3_AFMT_60958_2_BASE_IDX 2 9060#define regAFMT3_AFMT_AUDIO_CRC_RESULT 0x23ec 9061#define regAFMT3_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2 9062#define regAFMT3_AFMT_STATUS 0x23ed 9063#define regAFMT3_AFMT_STATUS_BASE_IDX 2 9064#define regAFMT3_AFMT_AUDIO_PACKET_CONTROL 0x23ee 9065#define regAFMT3_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2 9066#define regAFMT3_AFMT_INFOFRAME_CONTROL0 0x23ef 9067#define regAFMT3_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2 9068#define regAFMT3_AFMT_INTERRUPT_STATUS 0x23f0 9069#define regAFMT3_AFMT_INTERRUPT_STATUS_BASE_IDX 2 9070#define regAFMT3_AFMT_AUDIO_SRC_CONTROL 0x23f1 9071#define regAFMT3_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2 9072#define regAFMT3_AFMT_MEM_PWR 0x23f3 9073#define regAFMT3_AFMT_MEM_PWR_BASE_IDX 2 9074 9075 9076// addressBlock: dce_dc_dio_dig3_dme_dme_dispdec 9077// base address: 0x162f4 9078#define regDME3_DME_CONTROL 0x23fd 9079#define regDME3_DME_CONTROL_BASE_IDX 2 9080#define regDME3_DME_MEMORY_CONTROL 0x23fe 9081#define regDME3_DME_MEMORY_CONTROL_BASE_IDX 2 9082 9083 9084// addressBlock: dce_dc_dio_dig3_dispdec 9085// base address: 0xdb0 9086#define regDIG3_DIG_FE_CNTL 0x23ff 9087#define regDIG3_DIG_FE_CNTL_BASE_IDX 2 9088#define regDIG3_DIG_FE_CLK_CNTL 0x2400 9089#define regDIG3_DIG_FE_CLK_CNTL_BASE_IDX 2 9090#define regDIG3_DIG_FE_EN_CNTL 0x2401 9091#define regDIG3_DIG_FE_EN_CNTL_BASE_IDX 2 9092#define regDIG3_DIG_OUTPUT_CRC_CNTL 0x2402 9093#define regDIG3_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2 9094#define regDIG3_DIG_OUTPUT_CRC_RESULT 0x2403 9095#define regDIG3_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2 9096#define regDIG3_DIG_CLOCK_PATTERN 0x2404 9097#define regDIG3_DIG_CLOCK_PATTERN_BASE_IDX 2 9098#define regDIG3_DIG_TEST_PATTERN 0x2405 9099#define regDIG3_DIG_TEST_PATTERN_BASE_IDX 2 9100#define regDIG3_DIG_RANDOM_PATTERN_SEED 0x2406 9101#define regDIG3_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2 9102#define regDIG3_DIG_FIFO_CTRL0 0x2407 9103#define regDIG3_DIG_FIFO_CTRL0_BASE_IDX 2 9104#define regDIG3_DIG_FIFO_CTRL1 0x2408 9105#define regDIG3_DIG_FIFO_CTRL1_BASE_IDX 2 9106#define regDIG3_HDMI_METADATA_PACKET_CONTROL 0x2409 9107#define regDIG3_HDMI_METADATA_PACKET_CONTROL_BASE_IDX 2 9108#define regDIG3_HDMI_CONTROL 0x240a 9109#define regDIG3_HDMI_CONTROL_BASE_IDX 2 9110#define regDIG3_HDMI_STATUS 0x240b 9111#define regDIG3_HDMI_STATUS_BASE_IDX 2 9112#define regDIG3_HDMI_AUDIO_PACKET_CONTROL 0x240c 9113#define regDIG3_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2 9114#define regDIG3_HDMI_ACR_PACKET_CONTROL 0x240d 9115#define regDIG3_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2 9116#define regDIG3_HDMI_VBI_PACKET_CONTROL 0x240e 9117#define regDIG3_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2 9118#define regDIG3_HDMI_INFOFRAME_CONTROL0 0x240f 9119#define regDIG3_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2 9120#define regDIG3_HDMI_INFOFRAME_CONTROL1 0x2410 9121#define regDIG3_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2 9122#define regDIG3_HDMI_GENERIC_PACKET_CONTROL0 0x2411 9123#define regDIG3_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2 9124#define regDIG3_HDMI_GENERIC_PACKET_CONTROL6 0x2412 9125#define regDIG3_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX 2 9126#define regDIG3_HDMI_GENERIC_PACKET_CONTROL5 0x2413 9127#define regDIG3_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX 2 9128#define regDIG3_HDMI_GC 0x2414 9129#define regDIG3_HDMI_GC_BASE_IDX 2 9130#define regDIG3_HDMI_GENERIC_PACKET_CONTROL1 0x2415 9131#define regDIG3_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2 9132#define regDIG3_HDMI_GENERIC_PACKET_CONTROL2 0x2416 9133#define regDIG3_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2 9134#define regDIG3_HDMI_GENERIC_PACKET_CONTROL3 0x2417 9135#define regDIG3_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2 9136#define regDIG3_HDMI_GENERIC_PACKET_CONTROL4 0x2418 9137#define regDIG3_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX 2 9138#define regDIG3_HDMI_GENERIC_PACKET_CONTROL7 0x2419 9139#define regDIG3_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX 2 9140#define regDIG3_HDMI_GENERIC_PACKET_CONTROL8 0x241a 9141#define regDIG3_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX 2 9142#define regDIG3_HDMI_GENERIC_PACKET_CONTROL9 0x241b 9143#define regDIG3_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX 2 9144#define regDIG3_HDMI_GENERIC_PACKET_CONTROL10 0x241c 9145#define regDIG3_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX 2 9146#define regDIG3_HDMI_DB_CONTROL 0x241d 9147#define regDIG3_HDMI_DB_CONTROL_BASE_IDX 2 9148#define regDIG3_HDMI_ACR_32_0 0x241e 9149#define regDIG3_HDMI_ACR_32_0_BASE_IDX 2 9150#define regDIG3_HDMI_ACR_32_1 0x241f 9151#define regDIG3_HDMI_ACR_32_1_BASE_IDX 2 9152#define regDIG3_HDMI_ACR_44_0 0x2420 9153#define regDIG3_HDMI_ACR_44_0_BASE_IDX 2 9154#define regDIG3_HDMI_ACR_44_1 0x2421 9155#define regDIG3_HDMI_ACR_44_1_BASE_IDX 2 9156#define regDIG3_HDMI_ACR_48_0 0x2422 9157#define regDIG3_HDMI_ACR_48_0_BASE_IDX 2 9158#define regDIG3_HDMI_ACR_48_1 0x2423 9159#define regDIG3_HDMI_ACR_48_1_BASE_IDX 2 9160#define regDIG3_HDMI_ACR_STATUS_0 0x2424 9161#define regDIG3_HDMI_ACR_STATUS_0_BASE_IDX 2 9162#define regDIG3_HDMI_ACR_STATUS_1 0x2425 9163#define regDIG3_HDMI_ACR_STATUS_1_BASE_IDX 2 9164#define regDIG3_AFMT_CNTL 0x2426 9165#define regDIG3_AFMT_CNTL_BASE_IDX 2 9166#define regDIG3_DIG_BE_CLK_CNTL 0x2427 9167#define regDIG3_DIG_BE_CLK_CNTL_BASE_IDX 2 9168#define regDIG3_DIG_BE_CNTL 0x2428 9169#define regDIG3_DIG_BE_CNTL_BASE_IDX 2 9170#define regDIG3_DIG_BE_EN_CNTL 0x2429 9171#define regDIG3_DIG_BE_EN_CNTL_BASE_IDX 2 9172#define regDIG3_TMDS_CNTL 0x2450 9173#define regDIG3_TMDS_CNTL_BASE_IDX 2 9174#define regDIG3_TMDS_CONTROL_CHAR 0x2451 9175#define regDIG3_TMDS_CONTROL_CHAR_BASE_IDX 2 9176#define regDIG3_TMDS_CONTROL0_FEEDBACK 0x2452 9177#define regDIG3_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2 9178#define regDIG3_TMDS_STEREOSYNC_CTL_SEL 0x2453 9179#define regDIG3_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2 9180#define regDIG3_TMDS_SYNC_CHAR_PATTERN_0_1 0x2454 9181#define regDIG3_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2 9182#define regDIG3_TMDS_SYNC_CHAR_PATTERN_2_3 0x2455 9183#define regDIG3_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2 9184#define regDIG3_TMDS_CTL_BITS 0x2457 9185#define regDIG3_TMDS_CTL_BITS_BASE_IDX 2 9186#define regDIG3_TMDS_DCBALANCER_CONTROL 0x2458 9187#define regDIG3_TMDS_DCBALANCER_CONTROL_BASE_IDX 2 9188#define regDIG3_TMDS_SYNC_DCBALANCE_CHAR 0x2459 9189#define regDIG3_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX 2 9190#define regDIG3_TMDS_CTL0_1_GEN_CNTL 0x245a 9191#define regDIG3_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2 9192#define regDIG3_TMDS_CTL2_3_GEN_CNTL 0x245b 9193#define regDIG3_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2 9194#define regDIG3_DIG_VERSION 0x245d 9195#define regDIG3_DIG_VERSION_BASE_IDX 2 9196 9197 9198// addressBlock: dce_dc_dio_dp3_dispdec 9199// base address: 0xdb0 9200#define regDP3_DP_LINK_CNTL 0x248a 9201#define regDP3_DP_LINK_CNTL_BASE_IDX 2 9202#define regDP3_DP_PIXEL_FORMAT 0x248b 9203#define regDP3_DP_PIXEL_FORMAT_BASE_IDX 2 9204#define regDP3_DP_MSA_COLORIMETRY 0x248c 9205#define regDP3_DP_MSA_COLORIMETRY_BASE_IDX 2 9206#define regDP3_DP_CONFIG 0x248d 9207#define regDP3_DP_CONFIG_BASE_IDX 2 9208#define regDP3_DP_VID_STREAM_CNTL 0x248e 9209#define regDP3_DP_VID_STREAM_CNTL_BASE_IDX 2 9210#define regDP3_DP_STEER_FIFO 0x248f 9211#define regDP3_DP_STEER_FIFO_BASE_IDX 2 9212#define regDP3_DP_MSA_MISC 0x2490 9213#define regDP3_DP_MSA_MISC_BASE_IDX 2 9214#define regDP3_DP_DPHY_INTERNAL_CTRL 0x2491 9215#define regDP3_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 9216#define regDP3_DP_VID_TIMING 0x2492 9217#define regDP3_DP_VID_TIMING_BASE_IDX 2 9218#define regDP3_DP_VID_N 0x2493 9219#define regDP3_DP_VID_N_BASE_IDX 2 9220#define regDP3_DP_VID_M 0x2494 9221#define regDP3_DP_VID_M_BASE_IDX 2 9222#define regDP3_DP_LINK_FRAMING_CNTL 0x2495 9223#define regDP3_DP_LINK_FRAMING_CNTL_BASE_IDX 2 9224#define regDP3_DP_HBR2_EYE_PATTERN 0x2496 9225#define regDP3_DP_HBR2_EYE_PATTERN_BASE_IDX 2 9226#define regDP3_DP_VID_MSA_VBID 0x2497 9227#define regDP3_DP_VID_MSA_VBID_BASE_IDX 2 9228#define regDP3_DP_VID_INTERRUPT_CNTL 0x2498 9229#define regDP3_DP_VID_INTERRUPT_CNTL_BASE_IDX 2 9230#define regDP3_DP_DPHY_CNTL 0x2499 9231#define regDP3_DP_DPHY_CNTL_BASE_IDX 2 9232#define regDP3_DP_DPHY_TRAINING_PATTERN_SEL 0x249a 9233#define regDP3_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2 9234#define regDP3_DP_DPHY_SYM0 0x249b 9235#define regDP3_DP_DPHY_SYM0_BASE_IDX 2 9236#define regDP3_DP_DPHY_SYM1 0x249c 9237#define regDP3_DP_DPHY_SYM1_BASE_IDX 2 9238#define regDP3_DP_DPHY_SYM2 0x249d 9239#define regDP3_DP_DPHY_SYM2_BASE_IDX 2 9240#define regDP3_DP_DPHY_8B10B_CNTL 0x249e 9241#define regDP3_DP_DPHY_8B10B_CNTL_BASE_IDX 2 9242#define regDP3_DP_DPHY_PRBS_CNTL 0x249f 9243#define regDP3_DP_DPHY_PRBS_CNTL_BASE_IDX 2 9244#define regDP3_DP_DPHY_SCRAM_CNTL 0x24a0 9245#define regDP3_DP_DPHY_SCRAM_CNTL_BASE_IDX 2 9246#define regDP3_DP_DPHY_CRC_EN 0x24a1 9247#define regDP3_DP_DPHY_CRC_EN_BASE_IDX 2 9248#define regDP3_DP_DPHY_CRC_CNTL 0x24a2 9249#define regDP3_DP_DPHY_CRC_CNTL_BASE_IDX 2 9250#define regDP3_DP_DPHY_CRC_RESULT 0x24a3 9251#define regDP3_DP_DPHY_CRC_RESULT_BASE_IDX 2 9252#define regDP3_DP_DPHY_CRC_MST_CNTL 0x24a4 9253#define regDP3_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2 9254#define regDP3_DP_DPHY_CRC_MST_STATUS 0x24a5 9255#define regDP3_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2 9256#define regDP3_DP_DPHY_FAST_TRAINING 0x24a6 9257#define regDP3_DP_DPHY_FAST_TRAINING_BASE_IDX 2 9258#define regDP3_DP_DPHY_FAST_TRAINING_STATUS 0x24a7 9259#define regDP3_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2 9260#define regDP3_DP_SEC_CNTL 0x24ad 9261#define regDP3_DP_SEC_CNTL_BASE_IDX 2 9262#define regDP3_DP_SEC_CNTL1 0x24ae 9263#define regDP3_DP_SEC_CNTL1_BASE_IDX 2 9264#define regDP3_DP_SEC_FRAMING1 0x24af 9265#define regDP3_DP_SEC_FRAMING1_BASE_IDX 2 9266#define regDP3_DP_SEC_FRAMING2 0x24b0 9267#define regDP3_DP_SEC_FRAMING2_BASE_IDX 2 9268#define regDP3_DP_SEC_FRAMING3 0x24b1 9269#define regDP3_DP_SEC_FRAMING3_BASE_IDX 2 9270#define regDP3_DP_SEC_FRAMING4 0x24b2 9271#define regDP3_DP_SEC_FRAMING4_BASE_IDX 2 9272#define regDP3_DP_SEC_AUD_N 0x24b3 9273#define regDP3_DP_SEC_AUD_N_BASE_IDX 2 9274#define regDP3_DP_SEC_AUD_N_READBACK 0x24b4 9275#define regDP3_DP_SEC_AUD_N_READBACK_BASE_IDX 2 9276#define regDP3_DP_SEC_AUD_M 0x24b5 9277#define regDP3_DP_SEC_AUD_M_BASE_IDX 2 9278#define regDP3_DP_SEC_AUD_M_READBACK 0x24b6 9279#define regDP3_DP_SEC_AUD_M_READBACK_BASE_IDX 2 9280#define regDP3_DP_SEC_TIMESTAMP 0x24b7 9281#define regDP3_DP_SEC_TIMESTAMP_BASE_IDX 2 9282#define regDP3_DP_SEC_PACKET_CNTL 0x24b8 9283#define regDP3_DP_SEC_PACKET_CNTL_BASE_IDX 2 9284#define regDP3_DP_MSE_RATE_CNTL 0x24b9 9285#define regDP3_DP_MSE_RATE_CNTL_BASE_IDX 2 9286#define regDP3_DP_MSE_RATE_UPDATE 0x24bb 9287#define regDP3_DP_MSE_RATE_UPDATE_BASE_IDX 2 9288#define regDP3_DP_MSE_SAT0 0x24bc 9289#define regDP3_DP_MSE_SAT0_BASE_IDX 2 9290#define regDP3_DP_MSE_SAT1 0x24bd 9291#define regDP3_DP_MSE_SAT1_BASE_IDX 2 9292#define regDP3_DP_MSE_SAT2 0x24be 9293#define regDP3_DP_MSE_SAT2_BASE_IDX 2 9294#define regDP3_DP_MSE_SAT_UPDATE 0x24bf 9295#define regDP3_DP_MSE_SAT_UPDATE_BASE_IDX 2 9296#define regDP3_DP_MSE_LINK_TIMING 0x24c0 9297#define regDP3_DP_MSE_LINK_TIMING_BASE_IDX 2 9298#define regDP3_DP_MSE_MISC_CNTL 0x24c1 9299#define regDP3_DP_MSE_MISC_CNTL_BASE_IDX 2 9300#define regDP3_DP_DPHY_BS_SR_SWAP_CNTL 0x24c6 9301#define regDP3_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2 9302#define regDP3_DP_DPHY_HBR2_PATTERN_CONTROL 0x24c7 9303#define regDP3_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2 9304#define regDP3_DP_MSE_SAT0_STATUS 0x24c9 9305#define regDP3_DP_MSE_SAT0_STATUS_BASE_IDX 2 9306#define regDP3_DP_MSE_SAT1_STATUS 0x24ca 9307#define regDP3_DP_MSE_SAT1_STATUS_BASE_IDX 2 9308#define regDP3_DP_MSE_SAT2_STATUS 0x24cb 9309#define regDP3_DP_MSE_SAT2_STATUS_BASE_IDX 2 9310#define regDP3_DP_DPIA_SPARE 0x24cc 9311#define regDP3_DP_DPIA_SPARE_BASE_IDX 2 9312#define regDP3_DP_MSA_TIMING_PARAM1 0x24ce 9313#define regDP3_DP_MSA_TIMING_PARAM1_BASE_IDX 2 9314#define regDP3_DP_MSA_TIMING_PARAM2 0x24cf 9315#define regDP3_DP_MSA_TIMING_PARAM2_BASE_IDX 2 9316#define regDP3_DP_MSA_TIMING_PARAM3 0x24d0 9317#define regDP3_DP_MSA_TIMING_PARAM3_BASE_IDX 2 9318#define regDP3_DP_MSA_TIMING_PARAM4 0x24d1 9319#define regDP3_DP_MSA_TIMING_PARAM4_BASE_IDX 2 9320#define regDP3_DP_MSO_CNTL 0x24d2 9321#define regDP3_DP_MSO_CNTL_BASE_IDX 2 9322#define regDP3_DP_MSO_CNTL1 0x24d3 9323#define regDP3_DP_MSO_CNTL1_BASE_IDX 2 9324#define regDP3_DP_DSC_CNTL 0x24d4 9325#define regDP3_DP_DSC_CNTL_BASE_IDX 2 9326#define regDP3_DP_SEC_CNTL2 0x24d5 9327#define regDP3_DP_SEC_CNTL2_BASE_IDX 2 9328#define regDP3_DP_SEC_CNTL3 0x24d6 9329#define regDP3_DP_SEC_CNTL3_BASE_IDX 2 9330#define regDP3_DP_SEC_CNTL4 0x24d7 9331#define regDP3_DP_SEC_CNTL4_BASE_IDX 2 9332#define regDP3_DP_SEC_CNTL5 0x24d8 9333#define regDP3_DP_SEC_CNTL5_BASE_IDX 2 9334#define regDP3_DP_SEC_CNTL6 0x24d9 9335#define regDP3_DP_SEC_CNTL6_BASE_IDX 2 9336#define regDP3_DP_SEC_CNTL7 0x24da 9337#define regDP3_DP_SEC_CNTL7_BASE_IDX 2 9338#define regDP3_DP_DB_CNTL 0x24db 9339#define regDP3_DP_DB_CNTL_BASE_IDX 2 9340#define regDP3_DP_MSA_VBID_MISC 0x24dc 9341#define regDP3_DP_MSA_VBID_MISC_BASE_IDX 2 9342#define regDP3_DP_SEC_METADATA_TRANSMISSION 0x24dd 9343#define regDP3_DP_SEC_METADATA_TRANSMISSION_BASE_IDX 2 9344#define regDP3_DP_ALPM_CNTL 0x24df 9345#define regDP3_DP_ALPM_CNTL_BASE_IDX 2 9346#define regDP3_DP_GSP8_CNTL 0x24e0 9347#define regDP3_DP_GSP8_CNTL_BASE_IDX 2 9348#define regDP3_DP_GSP9_CNTL 0x24e1 9349#define regDP3_DP_GSP9_CNTL_BASE_IDX 2 9350#define regDP3_DP_GSP10_CNTL 0x24e2 9351#define regDP3_DP_GSP10_CNTL_BASE_IDX 2 9352#define regDP3_DP_GSP11_CNTL 0x24e3 9353#define regDP3_DP_GSP11_CNTL_BASE_IDX 2 9354#define regDP3_DP_GSP_EN_DB_STATUS 0x24e4 9355#define regDP3_DP_GSP_EN_DB_STATUS_BASE_IDX 2 9356#define regDP3_DP_AUXLESS_ALPM_CNTL1 0x24e5 9357#define regDP3_DP_AUXLESS_ALPM_CNTL1_BASE_IDX 2 9358#define regDP3_DP_AUXLESS_ALPM_CNTL2 0x24e6 9359#define regDP3_DP_AUXLESS_ALPM_CNTL2_BASE_IDX 2 9360#define regDP3_DP_AUXLESS_ALPM_CNTL3 0x24e7 9361#define regDP3_DP_AUXLESS_ALPM_CNTL3_BASE_IDX 2 9362#define regDP3_DP_AUXLESS_ALPM_CNTL4 0x24e8 9363#define regDP3_DP_AUXLESS_ALPM_CNTL4_BASE_IDX 2 9364#define regDP3_DP_AUXLESS_ALPM_CNTL5 0x24e9 9365#define regDP3_DP_AUXLESS_ALPM_CNTL5_BASE_IDX 2 9366#define regDP3_DP_STREAM_SYMBOL_COUNT_STATUS 0x24ea 9367#define regDP3_DP_STREAM_SYMBOL_COUNT_STATUS_BASE_IDX 2 9368#define regDP3_DP_STREAM_SYMBOL_COUNT_CONTROL 0x24eb 9369#define regDP3_DP_STREAM_SYMBOL_COUNT_CONTROL_BASE_IDX 2 9370#define regDP3_DP_LINK_SYMBOL_COUNT_STATUS0 0x24ec 9371#define regDP3_DP_LINK_SYMBOL_COUNT_STATUS0_BASE_IDX 2 9372#define regDP3_DP_LINK_SYMBOL_COUNT_STATUS1 0x24ed 9373#define regDP3_DP_LINK_SYMBOL_COUNT_STATUS1_BASE_IDX 2 9374#define regDP3_DP_LINK_SYMBOL_COUNT_CONTROL 0x24ee 9375#define regDP3_DP_LINK_SYMBOL_COUNT_CONTROL_BASE_IDX 2 9376 9377 9378// addressBlock: dce_dc_dio_dig4_vpg_vpg_dispdec 9379// base address: 0x166e0 9380#define regVPG4_VPG_GENERIC_PACKET_ACCESS_CTRL 0x24f8 9381#define regVPG4_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2 9382#define regVPG4_VPG_GENERIC_PACKET_DATA 0x24f9 9383#define regVPG4_VPG_GENERIC_PACKET_DATA_BASE_IDX 2 9384#define regVPG4_VPG_GSP_FRAME_UPDATE_CTRL 0x24fa 9385#define regVPG4_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2 9386#define regVPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x24fb 9387#define regVPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2 9388#define regVPG4_VPG_GENERIC_STATUS 0x24fc 9389#define regVPG4_VPG_GENERIC_STATUS_BASE_IDX 2 9390#define regVPG4_VPG_MEM_PWR 0x24fd 9391#define regVPG4_VPG_MEM_PWR_BASE_IDX 2 9392#define regVPG4_VPG_ISRC1_2_ACCESS_CTRL 0x24fe 9393#define regVPG4_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2 9394#define regVPG4_VPG_ISRC1_2_DATA 0x24ff 9395#define regVPG4_VPG_ISRC1_2_DATA_BASE_IDX 2 9396#define regVPG4_VPG_MPEG_INFO0 0x2500 9397#define regVPG4_VPG_MPEG_INFO0_BASE_IDX 2 9398#define regVPG4_VPG_MPEG_INFO1 0x2501 9399#define regVPG4_VPG_MPEG_INFO1_BASE_IDX 2 9400 9401 9402// addressBlock: dce_dc_dio_dig4_afmt_afmt_dispdec 9403// base address: 0x1670c 9404#define regAFMT4_AFMT_ACP 0x2503 9405#define regAFMT4_AFMT_ACP_BASE_IDX 2 9406#define regAFMT4_AFMT_VBI_PACKET_CONTROL 0x2504 9407#define regAFMT4_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2 9408#define regAFMT4_AFMT_AUDIO_PACKET_CONTROL2 0x2505 9409#define regAFMT4_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2 9410#define regAFMT4_AFMT_AUDIO_INFO0 0x2506 9411#define regAFMT4_AFMT_AUDIO_INFO0_BASE_IDX 2 9412#define regAFMT4_AFMT_AUDIO_INFO1 0x2507 9413#define regAFMT4_AFMT_AUDIO_INFO1_BASE_IDX 2 9414#define regAFMT4_AFMT_60958_0 0x2508 9415#define regAFMT4_AFMT_60958_0_BASE_IDX 2 9416#define regAFMT4_AFMT_60958_1 0x2509 9417#define regAFMT4_AFMT_60958_1_BASE_IDX 2 9418#define regAFMT4_AFMT_AUDIO_CRC_CONTROL 0x250a 9419#define regAFMT4_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2 9420#define regAFMT4_AFMT_RAMP_CONTROL0 0x250b 9421#define regAFMT4_AFMT_RAMP_CONTROL0_BASE_IDX 2 9422#define regAFMT4_AFMT_RAMP_CONTROL1 0x250c 9423#define regAFMT4_AFMT_RAMP_CONTROL1_BASE_IDX 2 9424#define regAFMT4_AFMT_RAMP_CONTROL2 0x250d 9425#define regAFMT4_AFMT_RAMP_CONTROL2_BASE_IDX 2 9426#define regAFMT4_AFMT_RAMP_CONTROL3 0x250e 9427#define regAFMT4_AFMT_RAMP_CONTROL3_BASE_IDX 2 9428#define regAFMT4_AFMT_60958_2 0x250f 9429#define regAFMT4_AFMT_60958_2_BASE_IDX 2 9430#define regAFMT4_AFMT_AUDIO_CRC_RESULT 0x2510 9431#define regAFMT4_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2 9432#define regAFMT4_AFMT_STATUS 0x2511 9433#define regAFMT4_AFMT_STATUS_BASE_IDX 2 9434#define regAFMT4_AFMT_AUDIO_PACKET_CONTROL 0x2512 9435#define regAFMT4_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2 9436#define regAFMT4_AFMT_INFOFRAME_CONTROL0 0x2513 9437#define regAFMT4_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2 9438#define regAFMT4_AFMT_INTERRUPT_STATUS 0x2514 9439#define regAFMT4_AFMT_INTERRUPT_STATUS_BASE_IDX 2 9440#define regAFMT4_AFMT_AUDIO_SRC_CONTROL 0x2515 9441#define regAFMT4_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2 9442#define regAFMT4_AFMT_MEM_PWR 0x2517 9443#define regAFMT4_AFMT_MEM_PWR_BASE_IDX 2 9444 9445 9446// addressBlock: dce_dc_dio_dig4_dme_dme_dispdec 9447// base address: 0x16784 9448#define regDME4_DME_CONTROL 0x2521 9449#define regDME4_DME_CONTROL_BASE_IDX 2 9450#define regDME4_DME_MEMORY_CONTROL 0x2522 9451#define regDME4_DME_MEMORY_CONTROL_BASE_IDX 2 9452 9453 9454// addressBlock: dce_dc_dio_dig4_dispdec 9455// base address: 0x1240 9456#define regDIG4_DIG_FE_CNTL 0x2523 9457#define regDIG4_DIG_FE_CNTL_BASE_IDX 2 9458#define regDIG4_DIG_FE_CLK_CNTL 0x2524 9459#define regDIG4_DIG_FE_CLK_CNTL_BASE_IDX 2 9460#define regDIG4_DIG_FE_EN_CNTL 0x2525 9461#define regDIG4_DIG_FE_EN_CNTL_BASE_IDX 2 9462#define regDIG4_DIG_OUTPUT_CRC_CNTL 0x2526 9463#define regDIG4_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2 9464#define regDIG4_DIG_OUTPUT_CRC_RESULT 0x2527 9465#define regDIG4_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2 9466#define regDIG4_DIG_CLOCK_PATTERN 0x2528 9467#define regDIG4_DIG_CLOCK_PATTERN_BASE_IDX 2 9468#define regDIG4_DIG_TEST_PATTERN 0x2529 9469#define regDIG4_DIG_TEST_PATTERN_BASE_IDX 2 9470#define regDIG4_DIG_RANDOM_PATTERN_SEED 0x252a 9471#define regDIG4_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2 9472#define regDIG4_DIG_FIFO_CTRL0 0x252b 9473#define regDIG4_DIG_FIFO_CTRL0_BASE_IDX 2 9474#define regDIG4_DIG_FIFO_CTRL1 0x252c 9475#define regDIG4_DIG_FIFO_CTRL1_BASE_IDX 2 9476#define regDIG4_HDMI_METADATA_PACKET_CONTROL 0x252d 9477#define regDIG4_HDMI_METADATA_PACKET_CONTROL_BASE_IDX 2 9478#define regDIG4_HDMI_CONTROL 0x252e 9479#define regDIG4_HDMI_CONTROL_BASE_IDX 2 9480#define regDIG4_HDMI_STATUS 0x252f 9481#define regDIG4_HDMI_STATUS_BASE_IDX 2 9482#define regDIG4_HDMI_AUDIO_PACKET_CONTROL 0x2530 9483#define regDIG4_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2 9484#define regDIG4_HDMI_ACR_PACKET_CONTROL 0x2531 9485#define regDIG4_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2 9486#define regDIG4_HDMI_VBI_PACKET_CONTROL 0x2532 9487#define regDIG4_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2 9488#define regDIG4_HDMI_INFOFRAME_CONTROL0 0x2533 9489#define regDIG4_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2 9490#define regDIG4_HDMI_INFOFRAME_CONTROL1 0x2534 9491#define regDIG4_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2 9492#define regDIG4_HDMI_GENERIC_PACKET_CONTROL0 0x2535 9493#define regDIG4_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2 9494#define regDIG4_HDMI_GENERIC_PACKET_CONTROL6 0x2536 9495#define regDIG4_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX 2 9496#define regDIG4_HDMI_GENERIC_PACKET_CONTROL5 0x2537 9497#define regDIG4_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX 2 9498#define regDIG4_HDMI_GC 0x2538 9499#define regDIG4_HDMI_GC_BASE_IDX 2 9500#define regDIG4_HDMI_GENERIC_PACKET_CONTROL1 0x2539 9501#define regDIG4_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2 9502#define regDIG4_HDMI_GENERIC_PACKET_CONTROL2 0x253a 9503#define regDIG4_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2 9504#define regDIG4_HDMI_GENERIC_PACKET_CONTROL3 0x253b 9505#define regDIG4_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2 9506#define regDIG4_HDMI_GENERIC_PACKET_CONTROL4 0x253c 9507#define regDIG4_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX 2 9508#define regDIG4_HDMI_GENERIC_PACKET_CONTROL7 0x253d 9509#define regDIG4_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX 2 9510#define regDIG4_HDMI_GENERIC_PACKET_CONTROL8 0x253e 9511#define regDIG4_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX 2 9512#define regDIG4_HDMI_GENERIC_PACKET_CONTROL9 0x253f 9513#define regDIG4_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX 2 9514#define regDIG4_HDMI_GENERIC_PACKET_CONTROL10 0x2540 9515#define regDIG4_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX 2 9516#define regDIG4_HDMI_DB_CONTROL 0x2541 9517#define regDIG4_HDMI_DB_CONTROL_BASE_IDX 2 9518#define regDIG4_HDMI_ACR_32_0 0x2542 9519#define regDIG4_HDMI_ACR_32_0_BASE_IDX 2 9520#define regDIG4_HDMI_ACR_32_1 0x2543 9521#define regDIG4_HDMI_ACR_32_1_BASE_IDX 2 9522#define regDIG4_HDMI_ACR_44_0 0x2544 9523#define regDIG4_HDMI_ACR_44_0_BASE_IDX 2 9524#define regDIG4_HDMI_ACR_44_1 0x2545 9525#define regDIG4_HDMI_ACR_44_1_BASE_IDX 2 9526#define regDIG4_HDMI_ACR_48_0 0x2546 9527#define regDIG4_HDMI_ACR_48_0_BASE_IDX 2 9528#define regDIG4_HDMI_ACR_48_1 0x2547 9529#define regDIG4_HDMI_ACR_48_1_BASE_IDX 2 9530#define regDIG4_HDMI_ACR_STATUS_0 0x2548 9531#define regDIG4_HDMI_ACR_STATUS_0_BASE_IDX 2 9532#define regDIG4_HDMI_ACR_STATUS_1 0x2549 9533#define regDIG4_HDMI_ACR_STATUS_1_BASE_IDX 2 9534#define regDIG4_AFMT_CNTL 0x254a 9535#define regDIG4_AFMT_CNTL_BASE_IDX 2 9536#define regDIG4_DIG_BE_CLK_CNTL 0x254b 9537#define regDIG4_DIG_BE_CLK_CNTL_BASE_IDX 2 9538#define regDIG4_DIG_BE_CNTL 0x254c 9539#define regDIG4_DIG_BE_CNTL_BASE_IDX 2 9540#define regDIG4_DIG_BE_EN_CNTL 0x254d 9541#define regDIG4_DIG_BE_EN_CNTL_BASE_IDX 2 9542#define regDIG4_TMDS_CNTL 0x2574 9543#define regDIG4_TMDS_CNTL_BASE_IDX 2 9544#define regDIG4_TMDS_CONTROL_CHAR 0x2575 9545#define regDIG4_TMDS_CONTROL_CHAR_BASE_IDX 2 9546#define regDIG4_TMDS_CONTROL0_FEEDBACK 0x2576 9547#define regDIG4_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2 9548#define regDIG4_TMDS_STEREOSYNC_CTL_SEL 0x2577 9549#define regDIG4_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2 9550#define regDIG4_TMDS_SYNC_CHAR_PATTERN_0_1 0x2578 9551#define regDIG4_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2 9552#define regDIG4_TMDS_SYNC_CHAR_PATTERN_2_3 0x2579 9553#define regDIG4_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2 9554#define regDIG4_TMDS_CTL_BITS 0x257b 9555#define regDIG4_TMDS_CTL_BITS_BASE_IDX 2 9556#define regDIG4_TMDS_DCBALANCER_CONTROL 0x257c 9557#define regDIG4_TMDS_DCBALANCER_CONTROL_BASE_IDX 2 9558#define regDIG4_TMDS_SYNC_DCBALANCE_CHAR 0x257d 9559#define regDIG4_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX 2 9560#define regDIG4_TMDS_CTL0_1_GEN_CNTL 0x257e 9561#define regDIG4_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2 9562#define regDIG4_TMDS_CTL2_3_GEN_CNTL 0x257f 9563#define regDIG4_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2 9564#define regDIG4_DIG_VERSION 0x2581 9565#define regDIG4_DIG_VERSION_BASE_IDX 2 9566 9567 9568// addressBlock: dce_dc_dio_dp4_dispdec 9569// base address: 0x1240 9570#define regDP4_DP_LINK_CNTL 0x25ae 9571#define regDP4_DP_LINK_CNTL_BASE_IDX 2 9572#define regDP4_DP_PIXEL_FORMAT 0x25af 9573#define regDP4_DP_PIXEL_FORMAT_BASE_IDX 2 9574#define regDP4_DP_MSA_COLORIMETRY 0x25b0 9575#define regDP4_DP_MSA_COLORIMETRY_BASE_IDX 2 9576#define regDP4_DP_CONFIG 0x25b1 9577#define regDP4_DP_CONFIG_BASE_IDX 2 9578#define regDP4_DP_VID_STREAM_CNTL 0x25b2 9579#define regDP4_DP_VID_STREAM_CNTL_BASE_IDX 2 9580#define regDP4_DP_STEER_FIFO 0x25b3 9581#define regDP4_DP_STEER_FIFO_BASE_IDX 2 9582#define regDP4_DP_MSA_MISC 0x25b4 9583#define regDP4_DP_MSA_MISC_BASE_IDX 2 9584#define regDP4_DP_DPHY_INTERNAL_CTRL 0x25b5 9585#define regDP4_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 9586#define regDP4_DP_VID_TIMING 0x25b6 9587#define regDP4_DP_VID_TIMING_BASE_IDX 2 9588#define regDP4_DP_VID_N 0x25b7 9589#define regDP4_DP_VID_N_BASE_IDX 2 9590#define regDP4_DP_VID_M 0x25b8 9591#define regDP4_DP_VID_M_BASE_IDX 2 9592#define regDP4_DP_LINK_FRAMING_CNTL 0x25b9 9593#define regDP4_DP_LINK_FRAMING_CNTL_BASE_IDX 2 9594#define regDP4_DP_HBR2_EYE_PATTERN 0x25ba 9595#define regDP4_DP_HBR2_EYE_PATTERN_BASE_IDX 2 9596#define regDP4_DP_VID_MSA_VBID 0x25bb 9597#define regDP4_DP_VID_MSA_VBID_BASE_IDX 2 9598#define regDP4_DP_VID_INTERRUPT_CNTL 0x25bc 9599#define regDP4_DP_VID_INTERRUPT_CNTL_BASE_IDX 2 9600#define regDP4_DP_DPHY_CNTL 0x25bd 9601#define regDP4_DP_DPHY_CNTL_BASE_IDX 2 9602#define regDP4_DP_DPHY_TRAINING_PATTERN_SEL 0x25be 9603#define regDP4_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2 9604#define regDP4_DP_DPHY_SYM0 0x25bf 9605#define regDP4_DP_DPHY_SYM0_BASE_IDX 2 9606#define regDP4_DP_DPHY_SYM1 0x25c0 9607#define regDP4_DP_DPHY_SYM1_BASE_IDX 2 9608#define regDP4_DP_DPHY_SYM2 0x25c1 9609#define regDP4_DP_DPHY_SYM2_BASE_IDX 2 9610#define regDP4_DP_DPHY_8B10B_CNTL 0x25c2 9611#define regDP4_DP_DPHY_8B10B_CNTL_BASE_IDX 2 9612#define regDP4_DP_DPHY_PRBS_CNTL 0x25c3 9613#define regDP4_DP_DPHY_PRBS_CNTL_BASE_IDX 2 9614#define regDP4_DP_DPHY_SCRAM_CNTL 0x25c4 9615#define regDP4_DP_DPHY_SCRAM_CNTL_BASE_IDX 2 9616#define regDP4_DP_DPHY_CRC_EN 0x25c5 9617#define regDP4_DP_DPHY_CRC_EN_BASE_IDX 2 9618#define regDP4_DP_DPHY_CRC_CNTL 0x25c6 9619#define regDP4_DP_DPHY_CRC_CNTL_BASE_IDX 2 9620#define regDP4_DP_DPHY_CRC_RESULT 0x25c7 9621#define regDP4_DP_DPHY_CRC_RESULT_BASE_IDX 2 9622#define regDP4_DP_DPHY_CRC_MST_CNTL 0x25c8 9623#define regDP4_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2 9624#define regDP4_DP_DPHY_CRC_MST_STATUS 0x25c9 9625#define regDP4_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2 9626#define regDP4_DP_DPHY_FAST_TRAINING 0x25ca 9627#define regDP4_DP_DPHY_FAST_TRAINING_BASE_IDX 2 9628#define regDP4_DP_DPHY_FAST_TRAINING_STATUS 0x25cb 9629#define regDP4_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2 9630#define regDP4_DP_SEC_CNTL 0x25d1 9631#define regDP4_DP_SEC_CNTL_BASE_IDX 2 9632#define regDP4_DP_SEC_CNTL1 0x25d2 9633#define regDP4_DP_SEC_CNTL1_BASE_IDX 2 9634#define regDP4_DP_SEC_FRAMING1 0x25d3 9635#define regDP4_DP_SEC_FRAMING1_BASE_IDX 2 9636#define regDP4_DP_SEC_FRAMING2 0x25d4 9637#define regDP4_DP_SEC_FRAMING2_BASE_IDX 2 9638#define regDP4_DP_SEC_FRAMING3 0x25d5 9639#define regDP4_DP_SEC_FRAMING3_BASE_IDX 2 9640#define regDP4_DP_SEC_FRAMING4 0x25d6 9641#define regDP4_DP_SEC_FRAMING4_BASE_IDX 2 9642#define regDP4_DP_SEC_AUD_N 0x25d7 9643#define regDP4_DP_SEC_AUD_N_BASE_IDX 2 9644#define regDP4_DP_SEC_AUD_N_READBACK 0x25d8 9645#define regDP4_DP_SEC_AUD_N_READBACK_BASE_IDX 2 9646#define regDP4_DP_SEC_AUD_M 0x25d9 9647#define regDP4_DP_SEC_AUD_M_BASE_IDX 2 9648#define regDP4_DP_SEC_AUD_M_READBACK 0x25da 9649#define regDP4_DP_SEC_AUD_M_READBACK_BASE_IDX 2 9650#define regDP4_DP_SEC_TIMESTAMP 0x25db 9651#define regDP4_DP_SEC_TIMESTAMP_BASE_IDX 2 9652#define regDP4_DP_SEC_PACKET_CNTL 0x25dc 9653#define regDP4_DP_SEC_PACKET_CNTL_BASE_IDX 2 9654#define regDP4_DP_MSE_RATE_CNTL 0x25dd 9655#define regDP4_DP_MSE_RATE_CNTL_BASE_IDX 2 9656#define regDP4_DP_MSE_RATE_UPDATE 0x25df 9657#define regDP4_DP_MSE_RATE_UPDATE_BASE_IDX 2 9658#define regDP4_DP_MSE_SAT0 0x25e0 9659#define regDP4_DP_MSE_SAT0_BASE_IDX 2 9660#define regDP4_DP_MSE_SAT1 0x25e1 9661#define regDP4_DP_MSE_SAT1_BASE_IDX 2 9662#define regDP4_DP_MSE_SAT2 0x25e2 9663#define regDP4_DP_MSE_SAT2_BASE_IDX 2 9664#define regDP4_DP_MSE_SAT_UPDATE 0x25e3 9665#define regDP4_DP_MSE_SAT_UPDATE_BASE_IDX 2 9666#define regDP4_DP_MSE_LINK_TIMING 0x25e4 9667#define regDP4_DP_MSE_LINK_TIMING_BASE_IDX 2 9668#define regDP4_DP_MSE_MISC_CNTL 0x25e5 9669#define regDP4_DP_MSE_MISC_CNTL_BASE_IDX 2 9670#define regDP4_DP_DPHY_BS_SR_SWAP_CNTL 0x25ea 9671#define regDP4_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2 9672#define regDP4_DP_DPHY_HBR2_PATTERN_CONTROL 0x25eb 9673#define regDP4_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2 9674#define regDP4_DP_MSE_SAT0_STATUS 0x25ed 9675#define regDP4_DP_MSE_SAT0_STATUS_BASE_IDX 2 9676#define regDP4_DP_MSE_SAT1_STATUS 0x25ee 9677#define regDP4_DP_MSE_SAT1_STATUS_BASE_IDX 2 9678#define regDP4_DP_MSE_SAT2_STATUS 0x25ef 9679#define regDP4_DP_MSE_SAT2_STATUS_BASE_IDX 2 9680#define regDP4_DP_DPIA_SPARE 0x25f0 9681#define regDP4_DP_DPIA_SPARE_BASE_IDX 2 9682#define regDP4_DP_MSA_TIMING_PARAM1 0x25f2 9683#define regDP4_DP_MSA_TIMING_PARAM1_BASE_IDX 2 9684#define regDP4_DP_MSA_TIMING_PARAM2 0x25f3 9685#define regDP4_DP_MSA_TIMING_PARAM2_BASE_IDX 2 9686#define regDP4_DP_MSA_TIMING_PARAM3 0x25f4 9687#define regDP4_DP_MSA_TIMING_PARAM3_BASE_IDX 2 9688#define regDP4_DP_MSA_TIMING_PARAM4 0x25f5 9689#define regDP4_DP_MSA_TIMING_PARAM4_BASE_IDX 2 9690#define regDP4_DP_MSO_CNTL 0x25f6 9691#define regDP4_DP_MSO_CNTL_BASE_IDX 2 9692#define regDP4_DP_MSO_CNTL1 0x25f7 9693#define regDP4_DP_MSO_CNTL1_BASE_IDX 2 9694#define regDP4_DP_DSC_CNTL 0x25f8 9695#define regDP4_DP_DSC_CNTL_BASE_IDX 2 9696#define regDP4_DP_SEC_CNTL2 0x25f9 9697#define regDP4_DP_SEC_CNTL2_BASE_IDX 2 9698#define regDP4_DP_SEC_CNTL3 0x25fa 9699#define regDP4_DP_SEC_CNTL3_BASE_IDX 2 9700#define regDP4_DP_SEC_CNTL4 0x25fb 9701#define regDP4_DP_SEC_CNTL4_BASE_IDX 2 9702#define regDP4_DP_SEC_CNTL5 0x25fc 9703#define regDP4_DP_SEC_CNTL5_BASE_IDX 2 9704#define regDP4_DP_SEC_CNTL6 0x25fd 9705#define regDP4_DP_SEC_CNTL6_BASE_IDX 2 9706#define regDP4_DP_SEC_CNTL7 0x25fe 9707#define regDP4_DP_SEC_CNTL7_BASE_IDX 2 9708#define regDP4_DP_DB_CNTL 0x25ff 9709#define regDP4_DP_DB_CNTL_BASE_IDX 2 9710#define regDP4_DP_MSA_VBID_MISC 0x2600 9711#define regDP4_DP_MSA_VBID_MISC_BASE_IDX 2 9712#define regDP4_DP_SEC_METADATA_TRANSMISSION 0x2601 9713#define regDP4_DP_SEC_METADATA_TRANSMISSION_BASE_IDX 2 9714#define regDP4_DP_ALPM_CNTL 0x2603 9715#define regDP4_DP_ALPM_CNTL_BASE_IDX 2 9716#define regDP4_DP_GSP8_CNTL 0x2604 9717#define regDP4_DP_GSP8_CNTL_BASE_IDX 2 9718#define regDP4_DP_GSP9_CNTL 0x2605 9719#define regDP4_DP_GSP9_CNTL_BASE_IDX 2 9720#define regDP4_DP_GSP10_CNTL 0x2606 9721#define regDP4_DP_GSP10_CNTL_BASE_IDX 2 9722#define regDP4_DP_GSP11_CNTL 0x2607 9723#define regDP4_DP_GSP11_CNTL_BASE_IDX 2 9724#define regDP4_DP_GSP_EN_DB_STATUS 0x2608 9725#define regDP4_DP_GSP_EN_DB_STATUS_BASE_IDX 2 9726#define regDP4_DP_AUXLESS_ALPM_CNTL1 0x2609 9727#define regDP4_DP_AUXLESS_ALPM_CNTL1_BASE_IDX 2 9728#define regDP4_DP_AUXLESS_ALPM_CNTL2 0x260a 9729#define regDP4_DP_AUXLESS_ALPM_CNTL2_BASE_IDX 2 9730#define regDP4_DP_AUXLESS_ALPM_CNTL3 0x260b 9731#define regDP4_DP_AUXLESS_ALPM_CNTL3_BASE_IDX 2 9732#define regDP4_DP_AUXLESS_ALPM_CNTL4 0x260c 9733#define regDP4_DP_AUXLESS_ALPM_CNTL4_BASE_IDX 2 9734#define regDP4_DP_AUXLESS_ALPM_CNTL5 0x260d 9735#define regDP4_DP_AUXLESS_ALPM_CNTL5_BASE_IDX 2 9736#define regDP4_DP_STREAM_SYMBOL_COUNT_STATUS 0x260e 9737#define regDP4_DP_STREAM_SYMBOL_COUNT_STATUS_BASE_IDX 2 9738#define regDP4_DP_STREAM_SYMBOL_COUNT_CONTROL 0x260f 9739#define regDP4_DP_STREAM_SYMBOL_COUNT_CONTROL_BASE_IDX 2 9740#define regDP4_DP_LINK_SYMBOL_COUNT_STATUS0 0x2610 9741#define regDP4_DP_LINK_SYMBOL_COUNT_STATUS0_BASE_IDX 2 9742#define regDP4_DP_LINK_SYMBOL_COUNT_STATUS1 0x2611 9743#define regDP4_DP_LINK_SYMBOL_COUNT_STATUS1_BASE_IDX 2 9744#define regDP4_DP_LINK_SYMBOL_COUNT_CONTROL 0x2612 9745#define regDP4_DP_LINK_SYMBOL_COUNT_CONTROL_BASE_IDX 2 9746 9747 9748// addressBlock: dce_dc_dcio_dcio_dispdec 9749// base address: 0x0 9750#define regDC_GENERICA 0x2868 9751#define regDC_GENERICA_BASE_IDX 2 9752#define regDC_GENERICB 0x2869 9753#define regDC_GENERICB_BASE_IDX 2 9754#define regDCIO_CLOCK_CNTL 0x286a 9755#define regDCIO_CLOCK_CNTL_BASE_IDX 2 9756#define regDC_REF_CLK_CNTL 0x286b 9757#define regDC_REF_CLK_CNTL_BASE_IDX 2 9758#define regUNIPHYA_LINK_CNTL 0x286d 9759#define regUNIPHYA_LINK_CNTL_BASE_IDX 2 9760#define regUNIPHYA_CHANNEL_XBAR_CNTL 0x286e 9761#define regUNIPHYA_CHANNEL_XBAR_CNTL_BASE_IDX 2 9762#define regUNIPHYB_LINK_CNTL 0x286f 9763#define regUNIPHYB_LINK_CNTL_BASE_IDX 2 9764#define regUNIPHYB_CHANNEL_XBAR_CNTL 0x2870 9765#define regUNIPHYB_CHANNEL_XBAR_CNTL_BASE_IDX 2 9766#define regUNIPHYC_LINK_CNTL 0x2871 9767#define regUNIPHYC_LINK_CNTL_BASE_IDX 2 9768#define regUNIPHYC_CHANNEL_XBAR_CNTL 0x2872 9769#define regUNIPHYC_CHANNEL_XBAR_CNTL_BASE_IDX 2 9770#define regUNIPHYD_CHANNEL_XBAR_CNTL 0x2874 9771#define regUNIPHYD_CHANNEL_XBAR_CNTL_BASE_IDX 2 9772#define regUNIPHYE_CHANNEL_XBAR_CNTL 0x2876 9773#define regUNIPHYE_CHANNEL_XBAR_CNTL_BASE_IDX 2 9774#define regDCIO_WRCMD_DELAY 0x287e 9775#define regDCIO_WRCMD_DELAY_BASE_IDX 2 9776#define regDC_PINSTRAPS 0x2880 9777#define regDC_PINSTRAPS_BASE_IDX 2 9778#define regDCIO_SPARE 0x2882 9779#define regDCIO_SPARE_BASE_IDX 2 9780#define regINTERCEPT_STATE 0x2884 9781#define regINTERCEPT_STATE_BASE_IDX 2 9782#define regDCIO_PATTERN_GEN_PAT 0x2886 9783#define regDCIO_PATTERN_GEN_PAT_BASE_IDX 2 9784#define regDCIO_PATTERN_GEN_EN 0x2887 9785#define regDCIO_PATTERN_GEN_EN_BASE_IDX 2 9786#define regDCIO_BL_PWM_FRAME_START_DISP_SEL 0x288b 9787#define regDCIO_BL_PWM_FRAME_START_DISP_SEL_BASE_IDX 2 9788#define regDCIO_GSL_GENLK_PAD_CNTL 0x288c 9789#define regDCIO_GSL_GENLK_PAD_CNTL_BASE_IDX 2 9790#define regDCIO_GSL_SWAPLOCK_PAD_CNTL 0x288d 9791#define regDCIO_GSL_SWAPLOCK_PAD_CNTL_BASE_IDX 2 9792#define regDCIO_SOFT_RESET 0x289e 9793#define regDCIO_SOFT_RESET_BASE_IDX 2 9794 9795 9796// addressBlock: dce_dc_dcio_dcio_chip_dispdec 9797// base address: 0x0 9798#define regDC_GPIO_GENERIC_MASK 0x28c8 9799#define regDC_GPIO_GENERIC_MASK_BASE_IDX 2 9800#define regDC_GPIO_GENERIC_A 0x28c9 9801#define regDC_GPIO_GENERIC_A_BASE_IDX 2 9802#define regDC_GPIO_GENERIC_EN 0x28ca 9803#define regDC_GPIO_GENERIC_EN_BASE_IDX 2 9804#define regDC_GPIO_GENERIC_Y 0x28cb 9805#define regDC_GPIO_GENERIC_Y_BASE_IDX 2 9806#define regDC_GPIO_DDC1_MASK 0x28d0 9807#define regDC_GPIO_DDC1_MASK_BASE_IDX 2 9808#define regDC_GPIO_DDC1_A 0x28d1 9809#define regDC_GPIO_DDC1_A_BASE_IDX 2 9810#define regDC_GPIO_DDC1_EN 0x28d2 9811#define regDC_GPIO_DDC1_EN_BASE_IDX 2 9812#define regDC_GPIO_DDC1_Y 0x28d3 9813#define regDC_GPIO_DDC1_Y_BASE_IDX 2 9814#define regDC_GPIO_DDC2_MASK 0x28d4 9815#define regDC_GPIO_DDC2_MASK_BASE_IDX 2 9816#define regDC_GPIO_DDC2_A 0x28d5 9817#define regDC_GPIO_DDC2_A_BASE_IDX 2 9818#define regDC_GPIO_DDC2_EN 0x28d6 9819#define regDC_GPIO_DDC2_EN_BASE_IDX 2 9820#define regDC_GPIO_DDC2_Y 0x28d7 9821#define regDC_GPIO_DDC2_Y_BASE_IDX 2 9822#define regDC_GPIO_DDC3_MASK 0x28d8 9823#define regDC_GPIO_DDC3_MASK_BASE_IDX 2 9824#define regDC_GPIO_DDC3_A 0x28d9 9825#define regDC_GPIO_DDC3_A_BASE_IDX 2 9826#define regDC_GPIO_DDC3_EN 0x28da 9827#define regDC_GPIO_DDC3_EN_BASE_IDX 2 9828#define regDC_GPIO_DDC3_Y 0x28db 9829#define regDC_GPIO_DDC3_Y_BASE_IDX 2 9830#define regDC_GPIO_DDC4_MASK 0x28dc 9831#define regDC_GPIO_DDC4_MASK_BASE_IDX 2 9832#define regDC_GPIO_DDC4_A 0x28dd 9833#define regDC_GPIO_DDC4_A_BASE_IDX 2 9834#define regDC_GPIO_DDC4_EN 0x28de 9835#define regDC_GPIO_DDC4_EN_BASE_IDX 2 9836#define regDC_GPIO_DDC4_Y 0x28df 9837#define regDC_GPIO_DDC4_Y_BASE_IDX 2 9838#define regDC_GPIO_DDC5_MASK 0x28e0 9839#define regDC_GPIO_DDC5_MASK_BASE_IDX 2 9840#define regDC_GPIO_DDC5_A 0x28e1 9841#define regDC_GPIO_DDC5_A_BASE_IDX 2 9842#define regDC_GPIO_DDC5_EN 0x28e2 9843#define regDC_GPIO_DDC5_EN_BASE_IDX 2 9844#define regDC_GPIO_DDC5_Y 0x28e3 9845#define regDC_GPIO_DDC5_Y_BASE_IDX 2 9846#define regDC_GPIO_DDCVGA_MASK 0x28e8 9847#define regDC_GPIO_DDCVGA_MASK_BASE_IDX 2 9848#define regDC_GPIO_DDCVGA_A 0x28e9 9849#define regDC_GPIO_DDCVGA_A_BASE_IDX 2 9850#define regDC_GPIO_DDCVGA_EN 0x28ea 9851#define regDC_GPIO_DDCVGA_EN_BASE_IDX 2 9852#define regDC_GPIO_DDCVGA_Y 0x28eb 9853#define regDC_GPIO_DDCVGA_Y_BASE_IDX 2 9854#define regDC_GPIO_GENLK_MASK 0x28f0 9855#define regDC_GPIO_GENLK_MASK_BASE_IDX 2 9856#define regDC_GPIO_GENLK_A 0x28f1 9857#define regDC_GPIO_GENLK_A_BASE_IDX 2 9858#define regDC_GPIO_GENLK_EN 0x28f2 9859#define regDC_GPIO_GENLK_EN_BASE_IDX 2 9860#define regDC_GPIO_GENLK_Y 0x28f3 9861#define regDC_GPIO_GENLK_Y_BASE_IDX 2 9862#define regDC_GPIO_HPD_MASK 0x28f4 9863#define regDC_GPIO_HPD_MASK_BASE_IDX 2 9864#define regDC_GPIO_HPD_A 0x28f5 9865#define regDC_GPIO_HPD_A_BASE_IDX 2 9866#define regDC_GPIO_HPD_EN 0x28f6 9867#define regDC_GPIO_HPD_EN_BASE_IDX 2 9868#define regDC_GPIO_HPD_Y 0x28f7 9869#define regDC_GPIO_HPD_Y_BASE_IDX 2 9870#define regDC_GPIO_DRIVE_STRENGTH_S0 0x28f8 9871#define regDC_GPIO_DRIVE_STRENGTH_S0_BASE_IDX 2 9872#define regDC_GPIO_DRIVE_STRENGTH_S1 0x28f9 9873#define regDC_GPIO_DRIVE_STRENGTH_S1_BASE_IDX 2 9874#define regDC_GPIO_PWRSEQ0_EN 0x28fa 9875#define regDC_GPIO_PWRSEQ0_EN_BASE_IDX 2 9876#define regDC_GPIO_PAD_STRENGTH_1 0x28fc 9877#define regDC_GPIO_PAD_STRENGTH_1_BASE_IDX 2 9878#define regDC_GPIO_PAD_STRENGTH_2 0x28fd 9879#define regDC_GPIO_PAD_STRENGTH_2_BASE_IDX 2 9880#define regPHY_AUX_CNTL 0x28ff 9881#define regPHY_AUX_CNTL_BASE_IDX 2 9882#define regDC_GPIO_DRIVE_TXIMPSEL 0x2900 9883#define regDC_GPIO_DRIVE_TXIMPSEL_BASE_IDX 2 9884#define regDC_GPIO_PWRSEQ1_EN 0x2902 9885#define regDC_GPIO_PWRSEQ1_EN_BASE_IDX 2 9886#define regDC_GPIO_TX12_EN 0x2915 9887#define regDC_GPIO_TX12_EN_BASE_IDX 2 9888#define regDC_GPIO_AUX_CTRL_0 0x2916 9889#define regDC_GPIO_AUX_CTRL_0_BASE_IDX 2 9890#define regDC_GPIO_AUX_CTRL_1 0x2917 9891#define regDC_GPIO_AUX_CTRL_1_BASE_IDX 2 9892#define regDC_GPIO_AUX_CTRL_2 0x2918 9893#define regDC_GPIO_AUX_CTRL_2_BASE_IDX 2 9894#define regDC_GPIO_RXEN 0x2919 9895#define regDC_GPIO_RXEN_BASE_IDX 2 9896#define regDC_GPIO_PULLUPEN 0x291a 9897#define regDC_GPIO_PULLUPEN_BASE_IDX 2 9898#define regDC_GPIO_AUX_CTRL_3 0x291b 9899#define regDC_GPIO_AUX_CTRL_3_BASE_IDX 2 9900#define regDC_GPIO_AUX_CTRL_4 0x291c 9901#define regDC_GPIO_AUX_CTRL_4_BASE_IDX 2 9902#define regDC_GPIO_AUX_CTRL_5 0x291d 9903#define regDC_GPIO_AUX_CTRL_5_BASE_IDX 2 9904#define regAUXI2C_PAD_ALL_PWR_OK 0x291e 9905#define regAUXI2C_PAD_ALL_PWR_OK_BASE_IDX 2 9906 9907 9908// addressBlock: dce_dc_dcio_dcio_uniphy0_dispdec 9909// base address: 0x0 9910 9911 9912// addressBlock: dce_dc_dcio_dcio_uniphy1_dispdec 9913// base address: 0x360 9914#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0 0x2a00 9915#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2 9916#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1 0x2a01 9917#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2 9918#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2 0x2a02 9919#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2 9920#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3 0x2a03 9921#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2 9922#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4 0x2a04 9923#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2 9924#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5 0x2a05 9925#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2 9926#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6 0x2a06 9927#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2 9928#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7 0x2a07 9929#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2 9930#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8 0x2a08 9931#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2 9932#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9 0x2a09 9933#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2 9934#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10 0x2a0a 9935#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2 9936#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11 0x2a0b 9937#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2 9938#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12 0x2a0c 9939#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2 9940#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13 0x2a0d 9941#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2 9942#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14 0x2a0e 9943#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2 9944#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15 0x2a0f 9945#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2 9946#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16 0x2a10 9947#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2 9948#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17 0x2a11 9949#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2 9950#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18 0x2a12 9951#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2 9952#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19 0x2a13 9953#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2 9954#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20 0x2a14 9955#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2 9956#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21 0x2a15 9957#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2 9958#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22 0x2a16 9959#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2 9960#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23 0x2a17 9961#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2 9962#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24 0x2a18 9963#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2 9964#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25 0x2a19 9965#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2 9966#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26 0x2a1a 9967#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2 9968#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27 0x2a1b 9969#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2 9970#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28 0x2a1c 9971#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2 9972#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29 0x2a1d 9973#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2 9974#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30 0x2a1e 9975#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2 9976#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31 0x2a1f 9977#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2 9978#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32 0x2a20 9979#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2 9980#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33 0x2a21 9981#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2 9982#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34 0x2a22 9983#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2 9984#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35 0x2a23 9985#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2 9986#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36 0x2a24 9987#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2 9988#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37 0x2a25 9989#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2 9990#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38 0x2a26 9991#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2 9992#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39 0x2a27 9993#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2 9994#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40 0x2a28 9995#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2 9996#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41 0x2a29 9997#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2 9998#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42 0x2a2a 9999#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2 10000#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43 0x2a2b 10001#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2 10002#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44 0x2a2c 10003#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2 10004#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45 0x2a2d 10005#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2 10006#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46 0x2a2e 10007#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2 10008#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47 0x2a2f 10009#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2 10010#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48 0x2a30 10011#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX 2 10012#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49 0x2a31 10013#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX 2 10014#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50 0x2a32 10015#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX 2 10016#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51 0x2a33 10017#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX 2 10018#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52 0x2a34 10019#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX 2 10020#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53 0x2a35 10021#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX 2 10022#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54 0x2a36 10023#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX 2 10024#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55 0x2a37 10025#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX 2 10026#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56 0x2a38 10027#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX 2 10028#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57 0x2a39 10029#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX 2 10030 10031 10032// addressBlock: dce_dc_dcio_dcio_uniphy2_dispdec 10033// base address: 0x6c0 10034#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0 0x2ad8 10035#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2 10036#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1 0x2ad9 10037#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2 10038#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2 0x2ada 10039#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2 10040#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3 0x2adb 10041#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2 10042#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4 0x2adc 10043#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2 10044#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5 0x2add 10045#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2 10046#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6 0x2ade 10047#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2 10048#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7 0x2adf 10049#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2 10050#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8 0x2ae0 10051#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2 10052#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9 0x2ae1 10053#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2 10054#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10 0x2ae2 10055#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2 10056#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11 0x2ae3 10057#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2 10058#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12 0x2ae4 10059#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2 10060#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13 0x2ae5 10061#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2 10062#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14 0x2ae6 10063#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2 10064#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15 0x2ae7 10065#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2 10066#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16 0x2ae8 10067#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2 10068#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17 0x2ae9 10069#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2 10070#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18 0x2aea 10071#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2 10072#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19 0x2aeb 10073#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2 10074#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20 0x2aec 10075#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2 10076#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21 0x2aed 10077#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2 10078#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22 0x2aee 10079#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2 10080#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23 0x2aef 10081#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2 10082#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24 0x2af0 10083#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2 10084#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25 0x2af1 10085#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2 10086#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26 0x2af2 10087#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2 10088#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27 0x2af3 10089#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2 10090#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28 0x2af4 10091#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2 10092#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29 0x2af5 10093#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2 10094#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30 0x2af6 10095#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2 10096#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31 0x2af7 10097#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2 10098#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32 0x2af8 10099#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2 10100#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33 0x2af9 10101#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2 10102#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34 0x2afa 10103#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2 10104#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35 0x2afb 10105#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2 10106#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36 0x2afc 10107#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2 10108#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37 0x2afd 10109#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2 10110#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38 0x2afe 10111#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2 10112#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39 0x2aff 10113#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2 10114#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40 0x2b00 10115#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2 10116#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41 0x2b01 10117#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2 10118#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42 0x2b02 10119#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2 10120#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43 0x2b03 10121#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2 10122#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44 0x2b04 10123#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2 10124#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45 0x2b05 10125#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2 10126#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46 0x2b06 10127#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2 10128#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47 0x2b07 10129#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2 10130#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48 0x2b08 10131#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX 2 10132#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49 0x2b09 10133#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX 2 10134#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50 0x2b0a 10135#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX 2 10136#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51 0x2b0b 10137#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX 2 10138#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52 0x2b0c 10139#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX 2 10140#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53 0x2b0d 10141#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX 2 10142#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54 0x2b0e 10143#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX 2 10144#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55 0x2b0f 10145#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX 2 10146#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56 0x2b10 10147#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX 2 10148#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57 0x2b11 10149#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX 2 10150 10151 10152// addressBlock: dce_dc_dcio_dcio_uniphy3_dispdec 10153// base address: 0xa20 10154#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0 0x2bb0 10155#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2 10156#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1 0x2bb1 10157#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2 10158#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2 0x2bb2 10159#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2 10160#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3 0x2bb3 10161#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2 10162#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4 0x2bb4 10163#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2 10164#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5 0x2bb5 10165#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2 10166#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6 0x2bb6 10167#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2 10168#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7 0x2bb7 10169#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2 10170#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8 0x2bb8 10171#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2 10172#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9 0x2bb9 10173#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2 10174#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10 0x2bba 10175#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2 10176#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11 0x2bbb 10177#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2 10178#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12 0x2bbc 10179#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2 10180#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13 0x2bbd 10181#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2 10182#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14 0x2bbe 10183#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2 10184#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15 0x2bbf 10185#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2 10186#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16 0x2bc0 10187#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2 10188#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17 0x2bc1 10189#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2 10190#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18 0x2bc2 10191#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2 10192#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19 0x2bc3 10193#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2 10194#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20 0x2bc4 10195#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2 10196#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21 0x2bc5 10197#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2 10198#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22 0x2bc6 10199#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2 10200#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23 0x2bc7 10201#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2 10202#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24 0x2bc8 10203#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2 10204#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25 0x2bc9 10205#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2 10206#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26 0x2bca 10207#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2 10208#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27 0x2bcb 10209#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2 10210#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28 0x2bcc 10211#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2 10212#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29 0x2bcd 10213#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2 10214#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30 0x2bce 10215#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2 10216#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31 0x2bcf 10217#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2 10218#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32 0x2bd0 10219#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2 10220#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33 0x2bd1 10221#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2 10222#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34 0x2bd2 10223#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2 10224#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35 0x2bd3 10225#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2 10226#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36 0x2bd4 10227#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2 10228#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37 0x2bd5 10229#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2 10230#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38 0x2bd6 10231#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2 10232#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39 0x2bd7 10233#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2 10234#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40 0x2bd8 10235#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2 10236#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41 0x2bd9 10237#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2 10238#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42 0x2bda 10239#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2 10240#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43 0x2bdb 10241#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2 10242#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44 0x2bdc 10243#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2 10244#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45 0x2bdd 10245#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2 10246#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46 0x2bde 10247#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2 10248#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47 0x2bdf 10249#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2 10250#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48 0x2be0 10251#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX 2 10252#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49 0x2be1 10253#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX 2 10254#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50 0x2be2 10255#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX 2 10256#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51 0x2be3 10257#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX 2 10258#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52 0x2be4 10259#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX 2 10260#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53 0x2be5 10261#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX 2 10262#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54 0x2be6 10263#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX 2 10264#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55 0x2be7 10265#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX 2 10266#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56 0x2be8 10267#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX 2 10268#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57 0x2be9 10269#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX 2 10270 10271 10272// addressBlock: dce_dc_dcio_dcio_uniphy4_dispdec 10273// base address: 0xd80 10274#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED0 0x2c88 10275#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2 10276#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED1 0x2c89 10277#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2 10278#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED2 0x2c8a 10279#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2 10280#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED3 0x2c8b 10281#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2 10282#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED4 0x2c8c 10283#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2 10284#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED5 0x2c8d 10285#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2 10286#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED6 0x2c8e 10287#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2 10288#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED7 0x2c8f 10289#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2 10290#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED8 0x2c90 10291#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2 10292#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED9 0x2c91 10293#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2 10294#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED10 0x2c92 10295#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2 10296#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED11 0x2c93 10297#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2 10298#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED12 0x2c94 10299#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2 10300#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED13 0x2c95 10301#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2 10302#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14 0x2c96 10303#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2 10304#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15 0x2c97 10305#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2 10306#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16 0x2c98 10307#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2 10308#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17 0x2c99 10309#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2 10310#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18 0x2c9a 10311#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2 10312#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19 0x2c9b 10313#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2 10314#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED20 0x2c9c 10315#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2 10316#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED21 0x2c9d 10317#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2 10318#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED22 0x2c9e 10319#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2 10320#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23 0x2c9f 10321#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2 10322#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24 0x2ca0 10323#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2 10324#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25 0x2ca1 10325#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2 10326#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26 0x2ca2 10327#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2 10328#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27 0x2ca3 10329#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2 10330#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28 0x2ca4 10331#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2 10332#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29 0x2ca5 10333#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2 10334#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30 0x2ca6 10335#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2 10336#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31 0x2ca7 10337#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2 10338#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED32 0x2ca8 10339#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2 10340#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED33 0x2ca9 10341#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2 10342#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED34 0x2caa 10343#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2 10344#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED35 0x2cab 10345#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2 10346#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED36 0x2cac 10347#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2 10348#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED37 0x2cad 10349#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2 10350#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED38 0x2cae 10351#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2 10352#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED39 0x2caf 10353#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2 10354#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED40 0x2cb0 10355#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2 10356#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED41 0x2cb1 10357#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2 10358#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED42 0x2cb2 10359#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2 10360#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED43 0x2cb3 10361#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2 10362#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED44 0x2cb4 10363#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2 10364#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED45 0x2cb5 10365#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2 10366#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED46 0x2cb6 10367#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2 10368#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED47 0x2cb7 10369#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2 10370#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED48 0x2cb8 10371#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX 2 10372#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED49 0x2cb9 10373#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX 2 10374#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED50 0x2cba 10375#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX 2 10376#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED51 0x2cbb 10377#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX 2 10378#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED52 0x2cbc 10379#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX 2 10380#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED53 0x2cbd 10381#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX 2 10382#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED54 0x2cbe 10383#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX 2 10384#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED55 0x2cbf 10385#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX 2 10386#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED56 0x2cc0 10387#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX 2 10388#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED57 0x2cc1 10389#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX 2 10390 10391 10392// addressBlock: dce_dc_pwrseq0_dispdec_pwrseq_dispdec 10393// base address: 0x0 10394#define regPWRSEQ0_DC_GPIO_PWRSEQ_EN 0x2f10 10395#define regPWRSEQ0_DC_GPIO_PWRSEQ_EN_BASE_IDX 2 10396#define regPWRSEQ0_DC_GPIO_PWRSEQ_CTRL 0x2f11 10397#define regPWRSEQ0_DC_GPIO_PWRSEQ_CTRL_BASE_IDX 2 10398#define regPWRSEQ0_DC_GPIO_PWRSEQ_MASK 0x2f12 10399#define regPWRSEQ0_DC_GPIO_PWRSEQ_MASK_BASE_IDX 2 10400#define regPWRSEQ0_DC_GPIO_PWRSEQ_A_Y 0x2f13 10401#define regPWRSEQ0_DC_GPIO_PWRSEQ_A_Y_BASE_IDX 2 10402#define regPWRSEQ0_PANEL_PWRSEQ_CNTL 0x2f14 10403#define regPWRSEQ0_PANEL_PWRSEQ_CNTL_BASE_IDX 2 10404#define regPWRSEQ0_PANEL_PWRSEQ_STATE 0x2f15 10405#define regPWRSEQ0_PANEL_PWRSEQ_STATE_BASE_IDX 2 10406#define regPWRSEQ0_PANEL_PWRSEQ_DELAY1 0x2f16 10407#define regPWRSEQ0_PANEL_PWRSEQ_DELAY1_BASE_IDX 2 10408#define regPWRSEQ0_PANEL_PWRSEQ_DELAY2 0x2f17 10409#define regPWRSEQ0_PANEL_PWRSEQ_DELAY2_BASE_IDX 2 10410#define regPWRSEQ0_PANEL_PWRSEQ_REF_DIV1 0x2f18 10411#define regPWRSEQ0_PANEL_PWRSEQ_REF_DIV1_BASE_IDX 2 10412#define regPWRSEQ0_BL_PWM_CNTL 0x2f19 10413#define regPWRSEQ0_BL_PWM_CNTL_BASE_IDX 2 10414#define regPWRSEQ0_BL_PWM_CNTL2 0x2f1a 10415#define regPWRSEQ0_BL_PWM_CNTL2_BASE_IDX 2 10416#define regPWRSEQ0_BL_PWM_PERIOD_CNTL 0x2f1b 10417#define regPWRSEQ0_BL_PWM_PERIOD_CNTL_BASE_IDX 2 10418#define regPWRSEQ0_BL_PWM_GRP1_REG_LOCK 0x2f1c 10419#define regPWRSEQ0_BL_PWM_GRP1_REG_LOCK_BASE_IDX 2 10420#define regPWRSEQ0_PANEL_PWRSEQ_REF_DIV2 0x2f1d 10421#define regPWRSEQ0_PANEL_PWRSEQ_REF_DIV2_BASE_IDX 2 10422#define regPWRSEQ0_PWRSEQ_SPARE 0x2f21 10423#define regPWRSEQ0_PWRSEQ_SPARE_BASE_IDX 2 10424 10425 10426// addressBlock: dce_dc_pwrseq1_dispdec_pwrseq_dispdec 10427// base address: 0x1b0 10428#define regPWRSEQ1_DC_GPIO_PWRSEQ_EN 0x2f7c 10429#define regPWRSEQ1_DC_GPIO_PWRSEQ_EN_BASE_IDX 2 10430#define regPWRSEQ1_DC_GPIO_PWRSEQ_CTRL 0x2f7d 10431#define regPWRSEQ1_DC_GPIO_PWRSEQ_CTRL_BASE_IDX 2 10432#define regPWRSEQ1_DC_GPIO_PWRSEQ_MASK 0x2f7e 10433#define regPWRSEQ1_DC_GPIO_PWRSEQ_MASK_BASE_IDX 2 10434#define regPWRSEQ1_DC_GPIO_PWRSEQ_A_Y 0x2f7f 10435#define regPWRSEQ1_DC_GPIO_PWRSEQ_A_Y_BASE_IDX 2 10436#define regPWRSEQ1_PANEL_PWRSEQ_CNTL 0x2f80 10437#define regPWRSEQ1_PANEL_PWRSEQ_CNTL_BASE_IDX 2 10438#define regPWRSEQ1_PANEL_PWRSEQ_STATE 0x2f81 10439#define regPWRSEQ1_PANEL_PWRSEQ_STATE_BASE_IDX 2 10440#define regPWRSEQ1_PANEL_PWRSEQ_DELAY1 0x2f82 10441#define regPWRSEQ1_PANEL_PWRSEQ_DELAY1_BASE_IDX 2 10442#define regPWRSEQ1_PANEL_PWRSEQ_DELAY2 0x2f83 10443#define regPWRSEQ1_PANEL_PWRSEQ_DELAY2_BASE_IDX 2 10444#define regPWRSEQ1_PANEL_PWRSEQ_REF_DIV1 0x2f84 10445#define regPWRSEQ1_PANEL_PWRSEQ_REF_DIV1_BASE_IDX 2 10446#define regPWRSEQ1_BL_PWM_CNTL 0x2f85 10447#define regPWRSEQ1_BL_PWM_CNTL_BASE_IDX 2 10448#define regPWRSEQ1_BL_PWM_CNTL2 0x2f86 10449#define regPWRSEQ1_BL_PWM_CNTL2_BASE_IDX 2 10450#define regPWRSEQ1_BL_PWM_PERIOD_CNTL 0x2f87 10451#define regPWRSEQ1_BL_PWM_PERIOD_CNTL_BASE_IDX 2 10452#define regPWRSEQ1_BL_PWM_GRP1_REG_LOCK 0x2f88 10453#define regPWRSEQ1_BL_PWM_GRP1_REG_LOCK_BASE_IDX 2 10454#define regPWRSEQ1_PANEL_PWRSEQ_REF_DIV2 0x2f89 10455#define regPWRSEQ1_PANEL_PWRSEQ_REF_DIV2_BASE_IDX 2 10456#define regPWRSEQ1_PWRSEQ_SPARE 0x2f8d 10457#define regPWRSEQ1_PWRSEQ_SPARE_BASE_IDX 2 10458 10459 10460// addressBlock: dce_dc_dsc0_dispdec_dsc_top_dispdec 10461// base address: 0x0 10462#define regDSC_TOP0_DSC_TOP_CONTROL 0x3000 10463#define regDSC_TOP0_DSC_TOP_CONTROL_BASE_IDX 2 10464#define regDSC_TOP0_DSC_DEBUG_CONTROL 0x3001 10465#define regDSC_TOP0_DSC_DEBUG_CONTROL_BASE_IDX 2 10466 10467 10468// addressBlock: dce_dc_dsc0_dispdec_dsccif_dispdec 10469// base address: 0x0 10470#define regDSCCIF0_DSCCIF_CONFIG0 0x3005 10471#define regDSCCIF0_DSCCIF_CONFIG0_BASE_IDX 2 10472#define regDSCCIF0_DSCCIF_CONFIG1 0x3006 10473#define regDSCCIF0_DSCCIF_CONFIG1_BASE_IDX 2 10474 10475 10476// addressBlock: dce_dc_dsc0_dispdec_dscc_dispdec 10477// base address: 0x0 10478#define regDSCC0_DSCC_CONFIG0 0x300a 10479#define regDSCC0_DSCC_CONFIG0_BASE_IDX 2 10480#define regDSCC0_DSCC_CONFIG1 0x300b 10481#define regDSCC0_DSCC_CONFIG1_BASE_IDX 2 10482#define regDSCC0_DSCC_STATUS 0x300c 10483#define regDSCC0_DSCC_STATUS_BASE_IDX 2 10484#define regDSCC0_DSCC_INTERRUPT_CONTROL_STATUS 0x300d 10485#define regDSCC0_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX 2 10486#define regDSCC0_DSCC_PPS_CONFIG0 0x300e 10487#define regDSCC0_DSCC_PPS_CONFIG0_BASE_IDX 2 10488#define regDSCC0_DSCC_PPS_CONFIG1 0x300f 10489#define regDSCC0_DSCC_PPS_CONFIG1_BASE_IDX 2 10490#define regDSCC0_DSCC_PPS_CONFIG2 0x3010 10491#define regDSCC0_DSCC_PPS_CONFIG2_BASE_IDX 2 10492#define regDSCC0_DSCC_PPS_CONFIG3 0x3011 10493#define regDSCC0_DSCC_PPS_CONFIG3_BASE_IDX 2 10494#define regDSCC0_DSCC_PPS_CONFIG4 0x3012 10495#define regDSCC0_DSCC_PPS_CONFIG4_BASE_IDX 2 10496#define regDSCC0_DSCC_PPS_CONFIG5 0x3013 10497#define regDSCC0_DSCC_PPS_CONFIG5_BASE_IDX 2 10498#define regDSCC0_DSCC_PPS_CONFIG6 0x3014 10499#define regDSCC0_DSCC_PPS_CONFIG6_BASE_IDX 2 10500#define regDSCC0_DSCC_PPS_CONFIG7 0x3015 10501#define regDSCC0_DSCC_PPS_CONFIG7_BASE_IDX 2 10502#define regDSCC0_DSCC_PPS_CONFIG8 0x3016 10503#define regDSCC0_DSCC_PPS_CONFIG8_BASE_IDX 2 10504#define regDSCC0_DSCC_PPS_CONFIG9 0x3017 10505#define regDSCC0_DSCC_PPS_CONFIG9_BASE_IDX 2 10506#define regDSCC0_DSCC_PPS_CONFIG10 0x3018 10507#define regDSCC0_DSCC_PPS_CONFIG10_BASE_IDX 2 10508#define regDSCC0_DSCC_PPS_CONFIG11 0x3019 10509#define regDSCC0_DSCC_PPS_CONFIG11_BASE_IDX 2 10510#define regDSCC0_DSCC_PPS_CONFIG12 0x301a 10511#define regDSCC0_DSCC_PPS_CONFIG12_BASE_IDX 2 10512#define regDSCC0_DSCC_PPS_CONFIG13 0x301b 10513#define regDSCC0_DSCC_PPS_CONFIG13_BASE_IDX 2 10514#define regDSCC0_DSCC_PPS_CONFIG14 0x301c 10515#define regDSCC0_DSCC_PPS_CONFIG14_BASE_IDX 2 10516#define regDSCC0_DSCC_PPS_CONFIG15 0x301d 10517#define regDSCC0_DSCC_PPS_CONFIG15_BASE_IDX 2 10518#define regDSCC0_DSCC_PPS_CONFIG16 0x301e 10519#define regDSCC0_DSCC_PPS_CONFIG16_BASE_IDX 2 10520#define regDSCC0_DSCC_PPS_CONFIG17 0x301f 10521#define regDSCC0_DSCC_PPS_CONFIG17_BASE_IDX 2 10522#define regDSCC0_DSCC_PPS_CONFIG18 0x3020 10523#define regDSCC0_DSCC_PPS_CONFIG18_BASE_IDX 2 10524#define regDSCC0_DSCC_PPS_CONFIG19 0x3021 10525#define regDSCC0_DSCC_PPS_CONFIG19_BASE_IDX 2 10526#define regDSCC0_DSCC_PPS_CONFIG20 0x3022 10527#define regDSCC0_DSCC_PPS_CONFIG20_BASE_IDX 2 10528#define regDSCC0_DSCC_PPS_CONFIG21 0x3023 10529#define regDSCC0_DSCC_PPS_CONFIG21_BASE_IDX 2 10530#define regDSCC0_DSCC_PPS_CONFIG22 0x3024 10531#define regDSCC0_DSCC_PPS_CONFIG22_BASE_IDX 2 10532#define regDSCC0_DSCC_MEM_POWER_CONTROL 0x3025 10533#define regDSCC0_DSCC_MEM_POWER_CONTROL_BASE_IDX 2 10534#define regDSCC0_DSCC_R_Y_SQUARED_ERROR_LOWER 0x3026 10535#define regDSCC0_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX 2 10536#define regDSCC0_DSCC_R_Y_SQUARED_ERROR_UPPER 0x3027 10537#define regDSCC0_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX 2 10538#define regDSCC0_DSCC_G_CB_SQUARED_ERROR_LOWER 0x3028 10539#define regDSCC0_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX 2 10540#define regDSCC0_DSCC_G_CB_SQUARED_ERROR_UPPER 0x3029 10541#define regDSCC0_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX 2 10542#define regDSCC0_DSCC_B_CR_SQUARED_ERROR_LOWER 0x302a 10543#define regDSCC0_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX 2 10544#define regDSCC0_DSCC_B_CR_SQUARED_ERROR_UPPER 0x302b 10545#define regDSCC0_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX 2 10546#define regDSCC0_DSCC_MAX_ABS_ERROR0 0x302c 10547#define regDSCC0_DSCC_MAX_ABS_ERROR0_BASE_IDX 2 10548#define regDSCC0_DSCC_MAX_ABS_ERROR1 0x302d 10549#define regDSCC0_DSCC_MAX_ABS_ERROR1_BASE_IDX 2 10550#define regDSCC0_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL 0x302e 10551#define regDSCC0_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2 10552#define regDSCC0_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL 0x302f 10553#define regDSCC0_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2 10554#define regDSCC0_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL 0x3030 10555#define regDSCC0_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2 10556#define regDSCC0_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL 0x3031 10557#define regDSCC0_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2 10558#define regDSCC0_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL 0x3032 10559#define regDSCC0_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2 10560#define regDSCC0_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL 0x3033 10561#define regDSCC0_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2 10562#define regDSCC0_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL 0x3034 10563#define regDSCC0_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2 10564#define regDSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL 0x3035 10565#define regDSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2 10566#define regDSCC0_DSCC_TEST_DEBUG_BUS_ROTATE 0x303a 10567#define regDSCC0_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX 2 10568 10569 10570// addressBlock: dce_dc_dsc0_dispdec_dsc_dcperfmon_dc_perfmon_dispdec 10571// base address: 0xc140 10572#define regDC_PERFMON19_PERFCOUNTER_CNTL 0x3050 10573#define regDC_PERFMON19_PERFCOUNTER_CNTL_BASE_IDX 2 10574#define regDC_PERFMON19_PERFCOUNTER_CNTL2 0x3051 10575#define regDC_PERFMON19_PERFCOUNTER_CNTL2_BASE_IDX 2 10576#define regDC_PERFMON19_PERFCOUNTER_STATE 0x3052 10577#define regDC_PERFMON19_PERFCOUNTER_STATE_BASE_IDX 2 10578#define regDC_PERFMON19_PERFMON_CNTL 0x3053 10579#define regDC_PERFMON19_PERFMON_CNTL_BASE_IDX 2 10580#define regDC_PERFMON19_PERFMON_CNTL2 0x3054 10581#define regDC_PERFMON19_PERFMON_CNTL2_BASE_IDX 2 10582#define regDC_PERFMON19_PERFMON_CVALUE_INT_MISC 0x3055 10583#define regDC_PERFMON19_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 10584#define regDC_PERFMON19_PERFMON_CVALUE_LOW 0x3056 10585#define regDC_PERFMON19_PERFMON_CVALUE_LOW_BASE_IDX 2 10586#define regDC_PERFMON19_PERFMON_HI 0x3057 10587#define regDC_PERFMON19_PERFMON_HI_BASE_IDX 2 10588#define regDC_PERFMON19_PERFMON_LOW 0x3058 10589#define regDC_PERFMON19_PERFMON_LOW_BASE_IDX 2 10590 10591 10592// addressBlock: dce_dc_dsc1_dispdec_dsc_top_dispdec 10593// base address: 0x170 10594#define regDSC_TOP1_DSC_TOP_CONTROL 0x305c 10595#define regDSC_TOP1_DSC_TOP_CONTROL_BASE_IDX 2 10596#define regDSC_TOP1_DSC_DEBUG_CONTROL 0x305d 10597#define regDSC_TOP1_DSC_DEBUG_CONTROL_BASE_IDX 2 10598 10599// addressBlock: dce_dc_dsc1_dispdec_dsccif_dispdec 10600// base address: 0x170 10601#define regDSCCIF1_DSCCIF_CONFIG0 0x3061 10602#define regDSCCIF1_DSCCIF_CONFIG0_BASE_IDX 2 10603#define regDSCCIF1_DSCCIF_CONFIG1 0x3062 10604#define regDSCCIF1_DSCCIF_CONFIG1_BASE_IDX 2 10605 10606 10607// addressBlock: dce_dc_dsc1_dispdec_dscc_dispdec 10608// base address: 0x170 10609#define regDSCC1_DSCC_CONFIG0 0x3066 10610#define regDSCC1_DSCC_CONFIG0_BASE_IDX 2 10611#define regDSCC1_DSCC_CONFIG1 0x3067 10612#define regDSCC1_DSCC_CONFIG1_BASE_IDX 2 10613#define regDSCC1_DSCC_STATUS 0x3068 10614#define regDSCC1_DSCC_STATUS_BASE_IDX 2 10615#define regDSCC1_DSCC_INTERRUPT_CONTROL_STATUS 0x3069 10616#define regDSCC1_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX 2 10617#define regDSCC1_DSCC_PPS_CONFIG0 0x306a 10618#define regDSCC1_DSCC_PPS_CONFIG0_BASE_IDX 2 10619#define regDSCC1_DSCC_PPS_CONFIG1 0x306b 10620#define regDSCC1_DSCC_PPS_CONFIG1_BASE_IDX 2 10621#define regDSCC1_DSCC_PPS_CONFIG2 0x306c 10622#define regDSCC1_DSCC_PPS_CONFIG2_BASE_IDX 2 10623#define regDSCC1_DSCC_PPS_CONFIG3 0x306d 10624#define regDSCC1_DSCC_PPS_CONFIG3_BASE_IDX 2 10625#define regDSCC1_DSCC_PPS_CONFIG4 0x306e 10626#define regDSCC1_DSCC_PPS_CONFIG4_BASE_IDX 2 10627#define regDSCC1_DSCC_PPS_CONFIG5 0x306f 10628#define regDSCC1_DSCC_PPS_CONFIG5_BASE_IDX 2 10629#define regDSCC1_DSCC_PPS_CONFIG6 0x3070 10630#define regDSCC1_DSCC_PPS_CONFIG6_BASE_IDX 2 10631#define regDSCC1_DSCC_PPS_CONFIG7 0x3071 10632#define regDSCC1_DSCC_PPS_CONFIG7_BASE_IDX 2 10633#define regDSCC1_DSCC_PPS_CONFIG8 0x3072 10634#define regDSCC1_DSCC_PPS_CONFIG8_BASE_IDX 2 10635#define regDSCC1_DSCC_PPS_CONFIG9 0x3073 10636#define regDSCC1_DSCC_PPS_CONFIG9_BASE_IDX 2 10637#define regDSCC1_DSCC_PPS_CONFIG10 0x3074 10638#define regDSCC1_DSCC_PPS_CONFIG10_BASE_IDX 2 10639#define regDSCC1_DSCC_PPS_CONFIG11 0x3075 10640#define regDSCC1_DSCC_PPS_CONFIG11_BASE_IDX 2 10641#define regDSCC1_DSCC_PPS_CONFIG12 0x3076 10642#define regDSCC1_DSCC_PPS_CONFIG12_BASE_IDX 2 10643#define regDSCC1_DSCC_PPS_CONFIG13 0x3077 10644#define regDSCC1_DSCC_PPS_CONFIG13_BASE_IDX 2 10645#define regDSCC1_DSCC_PPS_CONFIG14 0x3078 10646#define regDSCC1_DSCC_PPS_CONFIG14_BASE_IDX 2 10647#define regDSCC1_DSCC_PPS_CONFIG15 0x3079 10648#define regDSCC1_DSCC_PPS_CONFIG15_BASE_IDX 2 10649#define regDSCC1_DSCC_PPS_CONFIG16 0x307a 10650#define regDSCC1_DSCC_PPS_CONFIG16_BASE_IDX 2 10651#define regDSCC1_DSCC_PPS_CONFIG17 0x307b 10652#define regDSCC1_DSCC_PPS_CONFIG17_BASE_IDX 2 10653#define regDSCC1_DSCC_PPS_CONFIG18 0x307c 10654#define regDSCC1_DSCC_PPS_CONFIG18_BASE_IDX 2 10655#define regDSCC1_DSCC_PPS_CONFIG19 0x307d 10656#define regDSCC1_DSCC_PPS_CONFIG19_BASE_IDX 2 10657#define regDSCC1_DSCC_PPS_CONFIG20 0x307e 10658#define regDSCC1_DSCC_PPS_CONFIG20_BASE_IDX 2 10659#define regDSCC1_DSCC_PPS_CONFIG21 0x307f 10660#define regDSCC1_DSCC_PPS_CONFIG21_BASE_IDX 2 10661#define regDSCC1_DSCC_PPS_CONFIG22 0x3080 10662#define regDSCC1_DSCC_PPS_CONFIG22_BASE_IDX 2 10663#define regDSCC1_DSCC_MEM_POWER_CONTROL 0x3081 10664#define regDSCC1_DSCC_MEM_POWER_CONTROL_BASE_IDX 2 10665#define regDSCC1_DSCC_R_Y_SQUARED_ERROR_LOWER 0x3082 10666#define regDSCC1_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX 2 10667#define regDSCC1_DSCC_R_Y_SQUARED_ERROR_UPPER 0x3083 10668#define regDSCC1_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX 2 10669#define regDSCC1_DSCC_G_CB_SQUARED_ERROR_LOWER 0x3084 10670#define regDSCC1_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX 2 10671#define regDSCC1_DSCC_G_CB_SQUARED_ERROR_UPPER 0x3085 10672#define regDSCC1_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX 2 10673#define regDSCC1_DSCC_B_CR_SQUARED_ERROR_LOWER 0x3086 10674#define regDSCC1_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX 2 10675#define regDSCC1_DSCC_B_CR_SQUARED_ERROR_UPPER 0x3087 10676#define regDSCC1_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX 2 10677#define regDSCC1_DSCC_MAX_ABS_ERROR0 0x3088 10678#define regDSCC1_DSCC_MAX_ABS_ERROR0_BASE_IDX 2 10679#define regDSCC1_DSCC_MAX_ABS_ERROR1 0x3089 10680#define regDSCC1_DSCC_MAX_ABS_ERROR1_BASE_IDX 2 10681#define regDSCC1_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL 0x308a 10682#define regDSCC1_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2 10683#define regDSCC1_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL 0x308b 10684#define regDSCC1_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2 10685#define regDSCC1_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL 0x308c 10686#define regDSCC1_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2 10687#define regDSCC1_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL 0x308d 10688#define regDSCC1_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2 10689#define regDSCC1_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL 0x308e 10690#define regDSCC1_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2 10691#define regDSCC1_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL 0x308f 10692#define regDSCC1_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2 10693#define regDSCC1_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL 0x3090 10694#define regDSCC1_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2 10695#define regDSCC1_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL 0x3091 10696#define regDSCC1_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2 10697#define regDSCC1_DSCC_TEST_DEBUG_BUS_ROTATE 0x3096 10698#define regDSCC1_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX 2 10699 10700 10701// addressBlock: dce_dc_dsc1_dispdec_dsc_dcperfmon_dc_perfmon_dispdec 10702// base address: 0xc2b0 10703#define regDC_PERFMON20_PERFCOUNTER_CNTL 0x30ac 10704#define regDC_PERFMON20_PERFCOUNTER_CNTL_BASE_IDX 2 10705#define regDC_PERFMON20_PERFCOUNTER_CNTL2 0x30ad 10706#define regDC_PERFMON20_PERFCOUNTER_CNTL2_BASE_IDX 2 10707#define regDC_PERFMON20_PERFCOUNTER_STATE 0x30ae 10708#define regDC_PERFMON20_PERFCOUNTER_STATE_BASE_IDX 2 10709#define regDC_PERFMON20_PERFMON_CNTL 0x30af 10710#define regDC_PERFMON20_PERFMON_CNTL_BASE_IDX 2 10711#define regDC_PERFMON20_PERFMON_CNTL2 0x30b0 10712#define regDC_PERFMON20_PERFMON_CNTL2_BASE_IDX 2 10713#define regDC_PERFMON20_PERFMON_CVALUE_INT_MISC 0x30b1 10714#define regDC_PERFMON20_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 10715#define regDC_PERFMON20_PERFMON_CVALUE_LOW 0x30b2 10716#define regDC_PERFMON20_PERFMON_CVALUE_LOW_BASE_IDX 2 10717#define regDC_PERFMON20_PERFMON_HI 0x30b3 10718#define regDC_PERFMON20_PERFMON_HI_BASE_IDX 2 10719#define regDC_PERFMON20_PERFMON_LOW 0x30b4 10720#define regDC_PERFMON20_PERFMON_LOW_BASE_IDX 2 10721 10722 10723// addressBlock: dce_dc_dsc2_dispdec_dsc_top_dispdec 10724// base address: 0x2e0 10725#define regDSC_TOP2_DSC_TOP_CONTROL 0x30b8 10726#define regDSC_TOP2_DSC_TOP_CONTROL_BASE_IDX 2 10727#define regDSC_TOP2_DSC_DEBUG_CONTROL 0x30b9 10728#define regDSC_TOP2_DSC_DEBUG_CONTROL_BASE_IDX 2 10729 10730 10731// addressBlock: dce_dc_dsc2_dispdec_dsccif_dispdec 10732// base address: 0x2e0 10733#define regDSCCIF2_DSCCIF_CONFIG0 0x30bd 10734#define regDSCCIF2_DSCCIF_CONFIG0_BASE_IDX 2 10735#define regDSCCIF2_DSCCIF_CONFIG1 0x30be 10736#define regDSCCIF2_DSCCIF_CONFIG1_BASE_IDX 2 10737 10738 10739// addressBlock: dce_dc_dsc2_dispdec_dscc_dispdec 10740// base address: 0x2e0 10741#define regDSCC2_DSCC_CONFIG0 0x30c2 10742#define regDSCC2_DSCC_CONFIG0_BASE_IDX 2 10743#define regDSCC2_DSCC_CONFIG1 0x30c3 10744#define regDSCC2_DSCC_CONFIG1_BASE_IDX 2 10745#define regDSCC2_DSCC_STATUS 0x30c4 10746#define regDSCC2_DSCC_STATUS_BASE_IDX 2 10747#define regDSCC2_DSCC_INTERRUPT_CONTROL_STATUS 0x30c5 10748#define regDSCC2_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX 2 10749#define regDSCC2_DSCC_PPS_CONFIG0 0x30c6 10750#define regDSCC2_DSCC_PPS_CONFIG0_BASE_IDX 2 10751#define regDSCC2_DSCC_PPS_CONFIG1 0x30c7 10752#define regDSCC2_DSCC_PPS_CONFIG1_BASE_IDX 2 10753#define regDSCC2_DSCC_PPS_CONFIG2 0x30c8 10754#define regDSCC2_DSCC_PPS_CONFIG2_BASE_IDX 2 10755#define regDSCC2_DSCC_PPS_CONFIG3 0x30c9 10756#define regDSCC2_DSCC_PPS_CONFIG3_BASE_IDX 2 10757#define regDSCC2_DSCC_PPS_CONFIG4 0x30ca 10758#define regDSCC2_DSCC_PPS_CONFIG4_BASE_IDX 2 10759#define regDSCC2_DSCC_PPS_CONFIG5 0x30cb 10760#define regDSCC2_DSCC_PPS_CONFIG5_BASE_IDX 2 10761#define regDSCC2_DSCC_PPS_CONFIG6 0x30cc 10762#define regDSCC2_DSCC_PPS_CONFIG6_BASE_IDX 2 10763#define regDSCC2_DSCC_PPS_CONFIG7 0x30cd 10764#define regDSCC2_DSCC_PPS_CONFIG7_BASE_IDX 2 10765#define regDSCC2_DSCC_PPS_CONFIG8 0x30ce 10766#define regDSCC2_DSCC_PPS_CONFIG8_BASE_IDX 2 10767#define regDSCC2_DSCC_PPS_CONFIG9 0x30cf 10768#define regDSCC2_DSCC_PPS_CONFIG9_BASE_IDX 2 10769#define regDSCC2_DSCC_PPS_CONFIG10 0x30d0 10770#define regDSCC2_DSCC_PPS_CONFIG10_BASE_IDX 2 10771#define regDSCC2_DSCC_PPS_CONFIG11 0x30d1 10772#define regDSCC2_DSCC_PPS_CONFIG11_BASE_IDX 2 10773#define regDSCC2_DSCC_PPS_CONFIG12 0x30d2 10774#define regDSCC2_DSCC_PPS_CONFIG12_BASE_IDX 2 10775#define regDSCC2_DSCC_PPS_CONFIG13 0x30d3 10776#define regDSCC2_DSCC_PPS_CONFIG13_BASE_IDX 2 10777#define regDSCC2_DSCC_PPS_CONFIG14 0x30d4 10778#define regDSCC2_DSCC_PPS_CONFIG14_BASE_IDX 2 10779#define regDSCC2_DSCC_PPS_CONFIG15 0x30d5 10780#define regDSCC2_DSCC_PPS_CONFIG15_BASE_IDX 2 10781#define regDSCC2_DSCC_PPS_CONFIG16 0x30d6 10782#define regDSCC2_DSCC_PPS_CONFIG16_BASE_IDX 2 10783#define regDSCC2_DSCC_PPS_CONFIG17 0x30d7 10784#define regDSCC2_DSCC_PPS_CONFIG17_BASE_IDX 2 10785#define regDSCC2_DSCC_PPS_CONFIG18 0x30d8 10786#define regDSCC2_DSCC_PPS_CONFIG18_BASE_IDX 2 10787#define regDSCC2_DSCC_PPS_CONFIG19 0x30d9 10788#define regDSCC2_DSCC_PPS_CONFIG19_BASE_IDX 2 10789#define regDSCC2_DSCC_PPS_CONFIG20 0x30da 10790#define regDSCC2_DSCC_PPS_CONFIG20_BASE_IDX 2 10791#define regDSCC2_DSCC_PPS_CONFIG21 0x30db 10792#define regDSCC2_DSCC_PPS_CONFIG21_BASE_IDX 2 10793#define regDSCC2_DSCC_PPS_CONFIG22 0x30dc 10794#define regDSCC2_DSCC_PPS_CONFIG22_BASE_IDX 2 10795#define regDSCC2_DSCC_MEM_POWER_CONTROL 0x30dd 10796#define regDSCC2_DSCC_MEM_POWER_CONTROL_BASE_IDX 2 10797#define regDSCC2_DSCC_R_Y_SQUARED_ERROR_LOWER 0x30de 10798#define regDSCC2_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX 2 10799#define regDSCC2_DSCC_R_Y_SQUARED_ERROR_UPPER 0x30df 10800#define regDSCC2_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX 2 10801#define regDSCC2_DSCC_G_CB_SQUARED_ERROR_LOWER 0x30e0 10802#define regDSCC2_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX 2 10803#define regDSCC2_DSCC_G_CB_SQUARED_ERROR_UPPER 0x30e1 10804#define regDSCC2_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX 2 10805#define regDSCC2_DSCC_B_CR_SQUARED_ERROR_LOWER 0x30e2 10806#define regDSCC2_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX 2 10807#define regDSCC2_DSCC_B_CR_SQUARED_ERROR_UPPER 0x30e3 10808#define regDSCC2_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX 2 10809#define regDSCC2_DSCC_MAX_ABS_ERROR0 0x30e4 10810#define regDSCC2_DSCC_MAX_ABS_ERROR0_BASE_IDX 2 10811#define regDSCC2_DSCC_MAX_ABS_ERROR1 0x30e5 10812#define regDSCC2_DSCC_MAX_ABS_ERROR1_BASE_IDX 2 10813#define regDSCC2_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL 0x30e6 10814#define regDSCC2_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2 10815#define regDSCC2_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL 0x30e7 10816#define regDSCC2_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2 10817#define regDSCC2_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL 0x30e8 10818#define regDSCC2_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2 10819#define regDSCC2_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL 0x30e9 10820#define regDSCC2_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2 10821#define regDSCC2_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL 0x30ea 10822#define regDSCC2_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2 10823#define regDSCC2_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL 0x30eb 10824#define regDSCC2_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2 10825#define regDSCC2_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL 0x30ec 10826#define regDSCC2_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2 10827#define regDSCC2_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL 0x30ed 10828#define regDSCC2_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2 10829#define regDSCC2_DSCC_TEST_DEBUG_BUS_ROTATE 0x30f2 10830#define regDSCC2_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX 2 10831 10832 10833// addressBlock: dce_dc_dsc2_dispdec_dsc_dcperfmon_dc_perfmon_dispdec 10834// base address: 0xc420 10835#define regDC_PERFMON21_PERFCOUNTER_CNTL 0x3108 10836#define regDC_PERFMON21_PERFCOUNTER_CNTL_BASE_IDX 2 10837#define regDC_PERFMON21_PERFCOUNTER_CNTL2 0x3109 10838#define regDC_PERFMON21_PERFCOUNTER_CNTL2_BASE_IDX 2 10839#define regDC_PERFMON21_PERFCOUNTER_STATE 0x310a 10840#define regDC_PERFMON21_PERFCOUNTER_STATE_BASE_IDX 2 10841#define regDC_PERFMON21_PERFMON_CNTL 0x310b 10842#define regDC_PERFMON21_PERFMON_CNTL_BASE_IDX 2 10843#define regDC_PERFMON21_PERFMON_CNTL2 0x310c 10844#define regDC_PERFMON21_PERFMON_CNTL2_BASE_IDX 2 10845#define regDC_PERFMON21_PERFMON_CVALUE_INT_MISC 0x310d 10846#define regDC_PERFMON21_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 10847#define regDC_PERFMON21_PERFMON_CVALUE_LOW 0x310e 10848#define regDC_PERFMON21_PERFMON_CVALUE_LOW_BASE_IDX 2 10849#define regDC_PERFMON21_PERFMON_HI 0x310f 10850#define regDC_PERFMON21_PERFMON_HI_BASE_IDX 2 10851#define regDC_PERFMON21_PERFMON_LOW 0x3110 10852#define regDC_PERFMON21_PERFMON_LOW_BASE_IDX 2 10853 10854 10855// addressBlock: dce_dc_dsc3_dispdec_dsc_top_dispdec 10856// base address: 0x450 10857#define regDSC_TOP3_DSC_TOP_CONTROL 0x3114 10858#define regDSC_TOP3_DSC_TOP_CONTROL_BASE_IDX 2 10859#define regDSC_TOP3_DSC_DEBUG_CONTROL 0x3115 10860#define regDSC_TOP3_DSC_DEBUG_CONTROL_BASE_IDX 2 10861 10862 10863// addressBlock: dce_dc_dsc3_dispdec_dsccif_dispdec 10864// base address: 0x450 10865#define regDSCCIF3_DSCCIF_CONFIG0 0x3119 10866#define regDSCCIF3_DSCCIF_CONFIG0_BASE_IDX 2 10867#define regDSCCIF3_DSCCIF_CONFIG1 0x311a 10868#define regDSCCIF3_DSCCIF_CONFIG1_BASE_IDX 2 10869 10870 10871// addressBlock: dce_dc_dsc3_dispdec_dscc_dispdec 10872// base address: 0x450 10873#define regDSCC3_DSCC_CONFIG0 0x311e 10874#define regDSCC3_DSCC_CONFIG0_BASE_IDX 2 10875#define regDSCC3_DSCC_CONFIG1 0x311f 10876#define regDSCC3_DSCC_CONFIG1_BASE_IDX 2 10877#define regDSCC3_DSCC_STATUS 0x3120 10878#define regDSCC3_DSCC_STATUS_BASE_IDX 2 10879#define regDSCC3_DSCC_INTERRUPT_CONTROL_STATUS 0x3121 10880#define regDSCC3_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX 2 10881#define regDSCC3_DSCC_PPS_CONFIG0 0x3122 10882#define regDSCC3_DSCC_PPS_CONFIG0_BASE_IDX 2 10883#define regDSCC3_DSCC_PPS_CONFIG1 0x3123 10884#define regDSCC3_DSCC_PPS_CONFIG1_BASE_IDX 2 10885#define regDSCC3_DSCC_PPS_CONFIG2 0x3124 10886#define regDSCC3_DSCC_PPS_CONFIG2_BASE_IDX 2 10887#define regDSCC3_DSCC_PPS_CONFIG3 0x3125 10888#define regDSCC3_DSCC_PPS_CONFIG3_BASE_IDX 2 10889#define regDSCC3_DSCC_PPS_CONFIG4 0x3126 10890#define regDSCC3_DSCC_PPS_CONFIG4_BASE_IDX 2 10891#define regDSCC3_DSCC_PPS_CONFIG5 0x3127 10892#define regDSCC3_DSCC_PPS_CONFIG5_BASE_IDX 2 10893#define regDSCC3_DSCC_PPS_CONFIG6 0x3128 10894#define regDSCC3_DSCC_PPS_CONFIG6_BASE_IDX 2 10895#define regDSCC3_DSCC_PPS_CONFIG7 0x3129 10896#define regDSCC3_DSCC_PPS_CONFIG7_BASE_IDX 2 10897#define regDSCC3_DSCC_PPS_CONFIG8 0x312a 10898#define regDSCC3_DSCC_PPS_CONFIG8_BASE_IDX 2 10899#define regDSCC3_DSCC_PPS_CONFIG9 0x312b 10900#define regDSCC3_DSCC_PPS_CONFIG9_BASE_IDX 2 10901#define regDSCC3_DSCC_PPS_CONFIG10 0x312c 10902#define regDSCC3_DSCC_PPS_CONFIG10_BASE_IDX 2 10903#define regDSCC3_DSCC_PPS_CONFIG11 0x312d 10904#define regDSCC3_DSCC_PPS_CONFIG11_BASE_IDX 2 10905#define regDSCC3_DSCC_PPS_CONFIG12 0x312e 10906#define regDSCC3_DSCC_PPS_CONFIG12_BASE_IDX 2 10907#define regDSCC3_DSCC_PPS_CONFIG13 0x312f 10908#define regDSCC3_DSCC_PPS_CONFIG13_BASE_IDX 2 10909#define regDSCC3_DSCC_PPS_CONFIG14 0x3130 10910#define regDSCC3_DSCC_PPS_CONFIG14_BASE_IDX 2 10911#define regDSCC3_DSCC_PPS_CONFIG15 0x3131 10912#define regDSCC3_DSCC_PPS_CONFIG15_BASE_IDX 2 10913#define regDSCC3_DSCC_PPS_CONFIG16 0x3132 10914#define regDSCC3_DSCC_PPS_CONFIG16_BASE_IDX 2 10915#define regDSCC3_DSCC_PPS_CONFIG17 0x3133 10916#define regDSCC3_DSCC_PPS_CONFIG17_BASE_IDX 2 10917#define regDSCC3_DSCC_PPS_CONFIG18 0x3134 10918#define regDSCC3_DSCC_PPS_CONFIG18_BASE_IDX 2 10919#define regDSCC3_DSCC_PPS_CONFIG19 0x3135 10920#define regDSCC3_DSCC_PPS_CONFIG19_BASE_IDX 2 10921#define regDSCC3_DSCC_PPS_CONFIG20 0x3136 10922#define regDSCC3_DSCC_PPS_CONFIG20_BASE_IDX 2 10923#define regDSCC3_DSCC_PPS_CONFIG21 0x3137 10924#define regDSCC3_DSCC_PPS_CONFIG21_BASE_IDX 2 10925#define regDSCC3_DSCC_PPS_CONFIG22 0x3138 10926#define regDSCC3_DSCC_PPS_CONFIG22_BASE_IDX 2 10927#define regDSCC3_DSCC_MEM_POWER_CONTROL 0x3139 10928#define regDSCC3_DSCC_MEM_POWER_CONTROL_BASE_IDX 2 10929#define regDSCC3_DSCC_R_Y_SQUARED_ERROR_LOWER 0x313a 10930#define regDSCC3_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX 2 10931#define regDSCC3_DSCC_R_Y_SQUARED_ERROR_UPPER 0x313b 10932#define regDSCC3_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX 2 10933#define regDSCC3_DSCC_G_CB_SQUARED_ERROR_LOWER 0x313c 10934#define regDSCC3_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX 2 10935#define regDSCC3_DSCC_G_CB_SQUARED_ERROR_UPPER 0x313d 10936#define regDSCC3_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX 2 10937#define regDSCC3_DSCC_B_CR_SQUARED_ERROR_LOWER 0x313e 10938#define regDSCC3_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX 2 10939#define regDSCC3_DSCC_B_CR_SQUARED_ERROR_UPPER 0x313f 10940#define regDSCC3_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX 2 10941#define regDSCC3_DSCC_MAX_ABS_ERROR0 0x3140 10942#define regDSCC3_DSCC_MAX_ABS_ERROR0_BASE_IDX 2 10943#define regDSCC3_DSCC_MAX_ABS_ERROR1 0x3141 10944#define regDSCC3_DSCC_MAX_ABS_ERROR1_BASE_IDX 2 10945#define regDSCC3_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL 0x3142 10946#define regDSCC3_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2 10947#define regDSCC3_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL 0x3143 10948#define regDSCC3_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2 10949#define regDSCC3_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL 0x3144 10950#define regDSCC3_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2 10951#define regDSCC3_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL 0x3145 10952#define regDSCC3_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2 10953#define regDSCC3_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL 0x3146 10954#define regDSCC3_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2 10955#define regDSCC3_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL 0x3147 10956#define regDSCC3_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2 10957#define regDSCC3_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL 0x3148 10958#define regDSCC3_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2 10959#define regDSCC3_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL 0x3149 10960#define regDSCC3_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2 10961#define regDSCC3_DSCC_TEST_DEBUG_BUS_ROTATE 0x314e 10962#define regDSCC3_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX 2 10963 10964 10965// addressBlock: dce_dc_dsc3_dispdec_dsc_dcperfmon_dc_perfmon_dispdec 10966// base address: 0xc590 10967#define regDC_PERFMON22_PERFCOUNTER_CNTL 0x3164 10968#define regDC_PERFMON22_PERFCOUNTER_CNTL_BASE_IDX 2 10969#define regDC_PERFMON22_PERFCOUNTER_CNTL2 0x3165 10970#define regDC_PERFMON22_PERFCOUNTER_CNTL2_BASE_IDX 2 10971#define regDC_PERFMON22_PERFCOUNTER_STATE 0x3166 10972#define regDC_PERFMON22_PERFCOUNTER_STATE_BASE_IDX 2 10973#define regDC_PERFMON22_PERFMON_CNTL 0x3167 10974#define regDC_PERFMON22_PERFMON_CNTL_BASE_IDX 2 10975#define regDC_PERFMON22_PERFMON_CNTL2 0x3168 10976#define regDC_PERFMON22_PERFMON_CNTL2_BASE_IDX 2 10977#define regDC_PERFMON22_PERFMON_CVALUE_INT_MISC 0x3169 10978#define regDC_PERFMON22_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 10979#define regDC_PERFMON22_PERFMON_CVALUE_LOW 0x316a 10980#define regDC_PERFMON22_PERFMON_CVALUE_LOW_BASE_IDX 2 10981#define regDC_PERFMON22_PERFMON_HI 0x316b 10982#define regDC_PERFMON22_PERFMON_HI_BASE_IDX 2 10983#define regDC_PERFMON22_PERFMON_LOW 0x316c 10984#define regDC_PERFMON22_PERFMON_LOW_BASE_IDX 2 10985 10986 10987// addressBlock: dce_dc_wb0_dispdec_dwb_top_dispdec 10988// base address: 0x0 10989#define regDWB_ENABLE_CLK_CTRL 0x3228 10990#define regDWB_ENABLE_CLK_CTRL_BASE_IDX 2 10991#define regDWB_MEM_PWR_CTRL 0x3229 10992#define regDWB_MEM_PWR_CTRL_BASE_IDX 2 10993#define regFC_MODE_CTRL 0x322a 10994#define regFC_MODE_CTRL_BASE_IDX 2 10995#define regFC_FLOW_CTRL 0x322b 10996#define regFC_FLOW_CTRL_BASE_IDX 2 10997#define regFC_WINDOW_START 0x322c 10998#define regFC_WINDOW_START_BASE_IDX 2 10999#define regFC_WINDOW_SIZE 0x322d 11000#define regFC_WINDOW_SIZE_BASE_IDX 2 11001#define regFC_SOURCE_SIZE 0x322e 11002#define regFC_SOURCE_SIZE_BASE_IDX 2 11003#define regDWB_UPDATE_CTRL 0x322f 11004#define regDWB_UPDATE_CTRL_BASE_IDX 2 11005#define regDWB_CRC_CTRL 0x3230 11006#define regDWB_CRC_CTRL_BASE_IDX 2 11007#define regDWB_CRC_MASK_R_G 0x3231 11008#define regDWB_CRC_MASK_R_G_BASE_IDX 2 11009#define regDWB_CRC_MASK_B_A 0x3232 11010#define regDWB_CRC_MASK_B_A_BASE_IDX 2 11011#define regDWB_CRC_VAL_R_G 0x3233 11012#define regDWB_CRC_VAL_R_G_BASE_IDX 2 11013#define regDWB_CRC_VAL_B_A 0x3234 11014#define regDWB_CRC_VAL_B_A_BASE_IDX 2 11015#define regDWB_OUT_CTRL 0x3235 11016#define regDWB_OUT_CTRL_BASE_IDX 2 11017#define regDWB_MMHUBBUB_BACKPRESSURE_CNT_EN 0x3236 11018#define regDWB_MMHUBBUB_BACKPRESSURE_CNT_EN_BASE_IDX 2 11019#define regDWB_MMHUBBUB_BACKPRESSURE_CNT 0x3237 11020#define regDWB_MMHUBBUB_BACKPRESSURE_CNT_BASE_IDX 2 11021#define regDWB_HOST_READ_CONTROL 0x3238 11022#define regDWB_HOST_READ_CONTROL_BASE_IDX 2 11023#define regDWB_OVERFLOW_STATUS 0x3239 11024#define regDWB_OVERFLOW_STATUS_BASE_IDX 2 11025#define regDWB_OVERFLOW_COUNTER 0x323a 11026#define regDWB_OVERFLOW_COUNTER_BASE_IDX 2 11027#define regDWB_SOFT_RESET 0x323b 11028#define regDWB_SOFT_RESET_BASE_IDX 2 11029 11030 11031// addressBlock: dce_dc_wb0_dispdec_wb_dcperfmon_dc_perfmon_dispdec 11032// base address: 0xca20 11033#define regDC_PERFMON3_PERFCOUNTER_CNTL 0x3288 11034#define regDC_PERFMON3_PERFCOUNTER_CNTL_BASE_IDX 2 11035#define regDC_PERFMON3_PERFCOUNTER_CNTL2 0x3289 11036#define regDC_PERFMON3_PERFCOUNTER_CNTL2_BASE_IDX 2 11037#define regDC_PERFMON3_PERFCOUNTER_STATE 0x328a 11038#define regDC_PERFMON3_PERFCOUNTER_STATE_BASE_IDX 2 11039#define regDC_PERFMON3_PERFMON_CNTL 0x328b 11040#define regDC_PERFMON3_PERFMON_CNTL_BASE_IDX 2 11041#define regDC_PERFMON3_PERFMON_CNTL2 0x328c 11042#define regDC_PERFMON3_PERFMON_CNTL2_BASE_IDX 2 11043#define regDC_PERFMON3_PERFMON_CVALUE_INT_MISC 0x328d 11044#define regDC_PERFMON3_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 11045#define regDC_PERFMON3_PERFMON_CVALUE_LOW 0x328e 11046#define regDC_PERFMON3_PERFMON_CVALUE_LOW_BASE_IDX 2 11047#define regDC_PERFMON3_PERFMON_HI 0x328f 11048#define regDC_PERFMON3_PERFMON_HI_BASE_IDX 2 11049#define regDC_PERFMON3_PERFMON_LOW 0x3290 11050#define regDC_PERFMON3_PERFMON_LOW_BASE_IDX 2 11051 11052 11053// addressBlock: dce_dc_wb0_dispdec_dwbcp_dispdec 11054// base address: 0x0 11055#define regDWB_HDR_MULT_COEF 0x3294 11056#define regDWB_HDR_MULT_COEF_BASE_IDX 2 11057#define regDWB_GAMUT_REMAP_MODE 0x3295 11058#define regDWB_GAMUT_REMAP_MODE_BASE_IDX 2 11059#define regDWB_GAMUT_REMAP_COEF_FORMAT 0x3296 11060#define regDWB_GAMUT_REMAP_COEF_FORMAT_BASE_IDX 2 11061#define regDWB_GAMUT_REMAPA_C11_C12 0x3297 11062#define regDWB_GAMUT_REMAPA_C11_C12_BASE_IDX 2 11063#define regDWB_GAMUT_REMAPA_C13_C14 0x3298 11064#define regDWB_GAMUT_REMAPA_C13_C14_BASE_IDX 2 11065#define regDWB_GAMUT_REMAPA_C21_C22 0x3299 11066#define regDWB_GAMUT_REMAPA_C21_C22_BASE_IDX 2 11067#define regDWB_GAMUT_REMAPA_C23_C24 0x329a 11068#define regDWB_GAMUT_REMAPA_C23_C24_BASE_IDX 2 11069#define regDWB_GAMUT_REMAPA_C31_C32 0x329b 11070#define regDWB_GAMUT_REMAPA_C31_C32_BASE_IDX 2 11071#define regDWB_GAMUT_REMAPA_C33_C34 0x329c 11072#define regDWB_GAMUT_REMAPA_C33_C34_BASE_IDX 2 11073#define regDWB_GAMUT_REMAPB_C11_C12 0x329d 11074#define regDWB_GAMUT_REMAPB_C11_C12_BASE_IDX 2 11075#define regDWB_GAMUT_REMAPB_C13_C14 0x329e 11076#define regDWB_GAMUT_REMAPB_C13_C14_BASE_IDX 2 11077#define regDWB_GAMUT_REMAPB_C21_C22 0x329f 11078#define regDWB_GAMUT_REMAPB_C21_C22_BASE_IDX 2 11079#define regDWB_GAMUT_REMAPB_C23_C24 0x32a0 11080#define regDWB_GAMUT_REMAPB_C23_C24_BASE_IDX 2 11081#define regDWB_GAMUT_REMAPB_C31_C32 0x32a1 11082#define regDWB_GAMUT_REMAPB_C31_C32_BASE_IDX 2 11083#define regDWB_GAMUT_REMAPB_C33_C34 0x32a2 11084#define regDWB_GAMUT_REMAPB_C33_C34_BASE_IDX 2 11085#define regDWB_OGAM_CONTROL 0x32a3 11086#define regDWB_OGAM_CONTROL_BASE_IDX 2 11087#define regDWB_OGAM_LUT_INDEX 0x32a4 11088#define regDWB_OGAM_LUT_INDEX_BASE_IDX 2 11089#define regDWB_OGAM_LUT_DATA 0x32a5 11090#define regDWB_OGAM_LUT_DATA_BASE_IDX 2 11091#define regDWB_OGAM_LUT_CONTROL 0x32a6 11092#define regDWB_OGAM_LUT_CONTROL_BASE_IDX 2 11093#define regDWB_OGAM_RAMA_START_CNTL_B 0x32a7 11094#define regDWB_OGAM_RAMA_START_CNTL_B_BASE_IDX 2 11095#define regDWB_OGAM_RAMA_START_CNTL_G 0x32a8 11096#define regDWB_OGAM_RAMA_START_CNTL_G_BASE_IDX 2 11097#define regDWB_OGAM_RAMA_START_CNTL_R 0x32a9 11098#define regDWB_OGAM_RAMA_START_CNTL_R_BASE_IDX 2 11099#define regDWB_OGAM_RAMA_START_BASE_CNTL_B 0x32aa 11100#define regDWB_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX 2 11101#define regDWB_OGAM_RAMA_START_SLOPE_CNTL_B 0x32ab 11102#define regDWB_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX 2 11103#define regDWB_OGAM_RAMA_START_BASE_CNTL_G 0x32ac 11104#define regDWB_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX 2 11105#define regDWB_OGAM_RAMA_START_SLOPE_CNTL_G 0x32ad 11106#define regDWB_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2 11107#define regDWB_OGAM_RAMA_START_BASE_CNTL_R 0x32ae 11108#define regDWB_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX 2 11109#define regDWB_OGAM_RAMA_START_SLOPE_CNTL_R 0x32af 11110#define regDWB_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX 2 11111#define regDWB_OGAM_RAMA_END_CNTL1_B 0x32b0 11112#define regDWB_OGAM_RAMA_END_CNTL1_B_BASE_IDX 2 11113#define regDWB_OGAM_RAMA_END_CNTL2_B 0x32b1 11114#define regDWB_OGAM_RAMA_END_CNTL2_B_BASE_IDX 2 11115#define regDWB_OGAM_RAMA_END_CNTL1_G 0x32b2 11116#define regDWB_OGAM_RAMA_END_CNTL1_G_BASE_IDX 2 11117#define regDWB_OGAM_RAMA_END_CNTL2_G 0x32b3 11118#define regDWB_OGAM_RAMA_END_CNTL2_G_BASE_IDX 2 11119#define regDWB_OGAM_RAMA_END_CNTL1_R 0x32b4 11120#define regDWB_OGAM_RAMA_END_CNTL1_R_BASE_IDX 2 11121#define regDWB_OGAM_RAMA_END_CNTL2_R 0x32b5 11122#define regDWB_OGAM_RAMA_END_CNTL2_R_BASE_IDX 2 11123#define regDWB_OGAM_RAMA_OFFSET_B 0x32b6 11124#define regDWB_OGAM_RAMA_OFFSET_B_BASE_IDX 2 11125#define regDWB_OGAM_RAMA_OFFSET_G 0x32b7 11126#define regDWB_OGAM_RAMA_OFFSET_G_BASE_IDX 2 11127#define regDWB_OGAM_RAMA_OFFSET_R 0x32b8 11128#define regDWB_OGAM_RAMA_OFFSET_R_BASE_IDX 2 11129#define regDWB_OGAM_RAMA_REGION_0_1 0x32b9 11130#define regDWB_OGAM_RAMA_REGION_0_1_BASE_IDX 2 11131#define regDWB_OGAM_RAMA_REGION_2_3 0x32ba 11132#define regDWB_OGAM_RAMA_REGION_2_3_BASE_IDX 2 11133#define regDWB_OGAM_RAMA_REGION_4_5 0x32bb 11134#define regDWB_OGAM_RAMA_REGION_4_5_BASE_IDX 2 11135#define regDWB_OGAM_RAMA_REGION_6_7 0x32bc 11136#define regDWB_OGAM_RAMA_REGION_6_7_BASE_IDX 2 11137#define regDWB_OGAM_RAMA_REGION_8_9 0x32bd 11138#define regDWB_OGAM_RAMA_REGION_8_9_BASE_IDX 2 11139#define regDWB_OGAM_RAMA_REGION_10_11 0x32be 11140#define regDWB_OGAM_RAMA_REGION_10_11_BASE_IDX 2 11141#define regDWB_OGAM_RAMA_REGION_12_13 0x32bf 11142#define regDWB_OGAM_RAMA_REGION_12_13_BASE_IDX 2 11143#define regDWB_OGAM_RAMA_REGION_14_15 0x32c0 11144#define regDWB_OGAM_RAMA_REGION_14_15_BASE_IDX 2 11145#define regDWB_OGAM_RAMA_REGION_16_17 0x32c1 11146#define regDWB_OGAM_RAMA_REGION_16_17_BASE_IDX 2 11147#define regDWB_OGAM_RAMA_REGION_18_19 0x32c2 11148#define regDWB_OGAM_RAMA_REGION_18_19_BASE_IDX 2 11149#define regDWB_OGAM_RAMA_REGION_20_21 0x32c3 11150#define regDWB_OGAM_RAMA_REGION_20_21_BASE_IDX 2 11151#define regDWB_OGAM_RAMA_REGION_22_23 0x32c4 11152#define regDWB_OGAM_RAMA_REGION_22_23_BASE_IDX 2 11153#define regDWB_OGAM_RAMA_REGION_24_25 0x32c5 11154#define regDWB_OGAM_RAMA_REGION_24_25_BASE_IDX 2 11155#define regDWB_OGAM_RAMA_REGION_26_27 0x32c6 11156#define regDWB_OGAM_RAMA_REGION_26_27_BASE_IDX 2 11157#define regDWB_OGAM_RAMA_REGION_28_29 0x32c7 11158#define regDWB_OGAM_RAMA_REGION_28_29_BASE_IDX 2 11159#define regDWB_OGAM_RAMA_REGION_30_31 0x32c8 11160#define regDWB_OGAM_RAMA_REGION_30_31_BASE_IDX 2 11161#define regDWB_OGAM_RAMA_REGION_32_33 0x32c9 11162#define regDWB_OGAM_RAMA_REGION_32_33_BASE_IDX 2 11163#define regDWB_OGAM_RAMB_START_CNTL_B 0x32ca 11164#define regDWB_OGAM_RAMB_START_CNTL_B_BASE_IDX 2 11165#define regDWB_OGAM_RAMB_START_CNTL_G 0x32cb 11166#define regDWB_OGAM_RAMB_START_CNTL_G_BASE_IDX 2 11167#define regDWB_OGAM_RAMB_START_CNTL_R 0x32cc 11168#define regDWB_OGAM_RAMB_START_CNTL_R_BASE_IDX 2 11169#define regDWB_OGAM_RAMB_START_BASE_CNTL_B 0x32cd 11170#define regDWB_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX 2 11171#define regDWB_OGAM_RAMB_START_SLOPE_CNTL_B 0x32ce 11172#define regDWB_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX 2 11173#define regDWB_OGAM_RAMB_START_BASE_CNTL_G 0x32cf 11174#define regDWB_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX 2 11175#define regDWB_OGAM_RAMB_START_SLOPE_CNTL_G 0x32d0 11176#define regDWB_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX 2 11177#define regDWB_OGAM_RAMB_START_BASE_CNTL_R 0x32d1 11178#define regDWB_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX 2 11179#define regDWB_OGAM_RAMB_START_SLOPE_CNTL_R 0x32d2 11180#define regDWB_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX 2 11181#define regDWB_OGAM_RAMB_END_CNTL1_B 0x32d3 11182#define regDWB_OGAM_RAMB_END_CNTL1_B_BASE_IDX 2 11183#define regDWB_OGAM_RAMB_END_CNTL2_B 0x32d4 11184#define regDWB_OGAM_RAMB_END_CNTL2_B_BASE_IDX 2 11185#define regDWB_OGAM_RAMB_END_CNTL1_G 0x32d5 11186#define regDWB_OGAM_RAMB_END_CNTL1_G_BASE_IDX 2 11187#define regDWB_OGAM_RAMB_END_CNTL2_G 0x32d6 11188#define regDWB_OGAM_RAMB_END_CNTL2_G_BASE_IDX 2 11189#define regDWB_OGAM_RAMB_END_CNTL1_R 0x32d7 11190#define regDWB_OGAM_RAMB_END_CNTL1_R_BASE_IDX 2 11191#define regDWB_OGAM_RAMB_END_CNTL2_R 0x32d8 11192#define regDWB_OGAM_RAMB_END_CNTL2_R_BASE_IDX 2 11193#define regDWB_OGAM_RAMB_OFFSET_B 0x32d9 11194#define regDWB_OGAM_RAMB_OFFSET_B_BASE_IDX 2 11195#define regDWB_OGAM_RAMB_OFFSET_G 0x32da 11196#define regDWB_OGAM_RAMB_OFFSET_G_BASE_IDX 2 11197#define regDWB_OGAM_RAMB_OFFSET_R 0x32db 11198#define regDWB_OGAM_RAMB_OFFSET_R_BASE_IDX 2 11199#define regDWB_OGAM_RAMB_REGION_0_1 0x32dc 11200#define regDWB_OGAM_RAMB_REGION_0_1_BASE_IDX 2 11201#define regDWB_OGAM_RAMB_REGION_2_3 0x32dd 11202#define regDWB_OGAM_RAMB_REGION_2_3_BASE_IDX 2 11203#define regDWB_OGAM_RAMB_REGION_4_5 0x32de 11204#define regDWB_OGAM_RAMB_REGION_4_5_BASE_IDX 2 11205#define regDWB_OGAM_RAMB_REGION_6_7 0x32df 11206#define regDWB_OGAM_RAMB_REGION_6_7_BASE_IDX 2 11207#define regDWB_OGAM_RAMB_REGION_8_9 0x32e0 11208#define regDWB_OGAM_RAMB_REGION_8_9_BASE_IDX 2 11209#define regDWB_OGAM_RAMB_REGION_10_11 0x32e1 11210#define regDWB_OGAM_RAMB_REGION_10_11_BASE_IDX 2 11211#define regDWB_OGAM_RAMB_REGION_12_13 0x32e2 11212#define regDWB_OGAM_RAMB_REGION_12_13_BASE_IDX 2 11213#define regDWB_OGAM_RAMB_REGION_14_15 0x32e3 11214#define regDWB_OGAM_RAMB_REGION_14_15_BASE_IDX 2 11215#define regDWB_OGAM_RAMB_REGION_16_17 0x32e4 11216#define regDWB_OGAM_RAMB_REGION_16_17_BASE_IDX 2 11217#define regDWB_OGAM_RAMB_REGION_18_19 0x32e5 11218#define regDWB_OGAM_RAMB_REGION_18_19_BASE_IDX 2 11219#define regDWB_OGAM_RAMB_REGION_20_21 0x32e6 11220#define regDWB_OGAM_RAMB_REGION_20_21_BASE_IDX 2 11221#define regDWB_OGAM_RAMB_REGION_22_23 0x32e7 11222#define regDWB_OGAM_RAMB_REGION_22_23_BASE_IDX 2 11223#define regDWB_OGAM_RAMB_REGION_24_25 0x32e8 11224#define regDWB_OGAM_RAMB_REGION_24_25_BASE_IDX 2 11225#define regDWB_OGAM_RAMB_REGION_26_27 0x32e9 11226#define regDWB_OGAM_RAMB_REGION_26_27_BASE_IDX 2 11227#define regDWB_OGAM_RAMB_REGION_28_29 0x32ea 11228#define regDWB_OGAM_RAMB_REGION_28_29_BASE_IDX 2 11229#define regDWB_OGAM_RAMB_REGION_30_31 0x32eb 11230#define regDWB_OGAM_RAMB_REGION_30_31_BASE_IDX 2 11231#define regDWB_OGAM_RAMB_REGION_32_33 0x32ec 11232#define regDWB_OGAM_RAMB_REGION_32_33_BASE_IDX 2 11233 11234 11235// addressBlock: dce_dc_dchvm_hvm_dispdec 11236// base address: 0x0 11237#define regDCHVM_CTRL0 0x3603 11238#define regDCHVM_CTRL0_BASE_IDX 2 11239#define regDCHVM_CTRL1 0x3604 11240#define regDCHVM_CTRL1_BASE_IDX 2 11241#define regDCHVM_CLK_CTRL 0x3605 11242#define regDCHVM_CLK_CTRL_BASE_IDX 2 11243#define regDCHVM_MEM_CTRL 0x3606 11244#define regDCHVM_MEM_CTRL_BASE_IDX 2 11245#define regDCHVM_RIOMMU_CTRL0 0x3607 11246#define regDCHVM_RIOMMU_CTRL0_BASE_IDX 2 11247#define regDCHVM_RIOMMU_STAT0 0x3608 11248#define regDCHVM_RIOMMU_STAT0_BASE_IDX 2 11249 11250 11251// addressBlock: dce_dc_hpo_dp_stream_enc0_dispdec 11252// base address: 0x1ab8c 11253#define regDP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL 0x3623 11254#define regDP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL_BASE_IDX 2 11255#define regDP_STREAM_ENC0_DP_STREAM_ENC_INPUT_MUX_CONTROL 0x3624 11256#define regDP_STREAM_ENC0_DP_STREAM_ENC_INPUT_MUX_CONTROL_BASE_IDX 2 11257#define regDP_STREAM_ENC0_DP_STREAM_ENC_AUDIO_CONTROL 0x3625 11258#define regDP_STREAM_ENC0_DP_STREAM_ENC_AUDIO_CONTROL_BASE_IDX 2 11259#define regDP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0 0x3626 11260#define regDP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0_BASE_IDX 2 11261#define regDP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1 0x3627 11262#define regDP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1_BASE_IDX 2 11263#define regDP_STREAM_ENC0_DP_STREAM_ENC_SPARE 0x3628 11264#define regDP_STREAM_ENC0_DP_STREAM_ENC_SPARE_BASE_IDX 2 11265 11266 11267// addressBlock: dce_dc_hpo_dp_stream_enc0_apg_apg_dispdec 11268// base address: 0x1abc0 11269#define regAPG0_APG_CONTROL 0x3630 11270#define regAPG0_APG_CONTROL_BASE_IDX 2 11271#define regAPG0_APG_CONTROL2 0x3631 11272#define regAPG0_APG_CONTROL2_BASE_IDX 2 11273#define regAPG0_APG_DBG_GEN_CONTROL 0x3632 11274#define regAPG0_APG_DBG_GEN_CONTROL_BASE_IDX 2 11275#define regAPG0_APG_PACKET_CONTROL 0x3633 11276#define regAPG0_APG_PACKET_CONTROL_BASE_IDX 2 11277#define regAPG0_APG_AUDIO_CRC_CONTROL 0x363a 11278#define regAPG0_APG_AUDIO_CRC_CONTROL_BASE_IDX 2 11279#define regAPG0_APG_AUDIO_CRC_CONTROL2 0x363b 11280#define regAPG0_APG_AUDIO_CRC_CONTROL2_BASE_IDX 2 11281#define regAPG0_APG_AUDIO_CRC_RESULT 0x363c 11282#define regAPG0_APG_AUDIO_CRC_RESULT_BASE_IDX 2 11283#define regAPG0_APG_STATUS 0x3641 11284#define regAPG0_APG_STATUS_BASE_IDX 2 11285#define regAPG0_APG_STATUS2 0x3642 11286#define regAPG0_APG_STATUS2_BASE_IDX 2 11287#define regAPG0_APG_MEM_PWR 0x3644 11288#define regAPG0_APG_MEM_PWR_BASE_IDX 2 11289#define regAPG0_APG_SPARE 0x3646 11290#define regAPG0_APG_SPARE_BASE_IDX 2 11291 11292 11293// addressBlock: dce_dc_hpo_dp_stream_enc0_dme_dme_dispdec 11294// base address: 0x1ac38 11295#define regDME6_DME_CONTROL 0x364e 11296#define regDME6_DME_CONTROL_BASE_IDX 2 11297#define regDME6_DME_MEMORY_CONTROL 0x364f 11298#define regDME6_DME_MEMORY_CONTROL_BASE_IDX 2 11299 11300 11301// addressBlock: dce_dc_hpo_dp_stream_enc0_vpg_vpg_dispdec 11302// base address: 0x1ac44 11303#define regVPG6_VPG_GENERIC_PACKET_ACCESS_CTRL 0x3651 11304#define regVPG6_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2 11305#define regVPG6_VPG_GENERIC_PACKET_DATA 0x3652 11306#define regVPG6_VPG_GENERIC_PACKET_DATA_BASE_IDX 2 11307#define regVPG6_VPG_GSP_FRAME_UPDATE_CTRL 0x3653 11308#define regVPG6_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2 11309#define regVPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x3654 11310#define regVPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2 11311#define regVPG6_VPG_GENERIC_STATUS 0x3655 11312#define regVPG6_VPG_GENERIC_STATUS_BASE_IDX 2 11313#define regVPG6_VPG_MEM_PWR 0x3656 11314#define regVPG6_VPG_MEM_PWR_BASE_IDX 2 11315#define regVPG6_VPG_ISRC1_2_ACCESS_CTRL 0x3657 11316#define regVPG6_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2 11317#define regVPG6_VPG_ISRC1_2_DATA 0x3658 11318#define regVPG6_VPG_ISRC1_2_DATA_BASE_IDX 2 11319#define regVPG6_VPG_MPEG_INFO0 0x3659 11320#define regVPG6_VPG_MPEG_INFO0_BASE_IDX 2 11321#define regVPG6_VPG_MPEG_INFO1 0x365a 11322#define regVPG6_VPG_MPEG_INFO1_BASE_IDX 2 11323 11324 11325// addressBlock: dce_dc_hpo_dp_sym32_enc0_dispdec 11326// base address: 0x1ac74 11327#define regDP_SYM32_ENC0_DP_SYM32_ENC_CONTROL 0x365d 11328#define regDP_SYM32_ENC0_DP_SYM32_ENC_CONTROL_BASE_IDX 2 11329#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL 0x365e 11330#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL_BASE_IDX 2 11331#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL 0x365f 11332#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 11333#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL 0x3660 11334#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 11335#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT 0x3661 11336#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT_BASE_IDX 2 11337#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA0 0x3662 11338#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA0_BASE_IDX 2 11339#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA1 0x3663 11340#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA1_BASE_IDX 2 11341#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA2 0x3664 11342#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA2_BASE_IDX 2 11343#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA3 0x3665 11344#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA3_BASE_IDX 2 11345#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA4 0x3666 11346#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA4_BASE_IDX 2 11347#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA5 0x3667 11348#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA5_BASE_IDX 2 11349#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA6 0x3668 11350#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA6_BASE_IDX 2 11351#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA7 0x3669 11352#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA7_BASE_IDX 2 11353#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA8 0x366a 11354#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA8_BASE_IDX 2 11355#define regDP_SYM32_ENC0_DP_SYM32_ENC_HBLANK_CONTROL 0x366b 11356#define regDP_SYM32_ENC0_DP_SYM32_ENC_HBLANK_CONTROL_BASE_IDX 2 11357#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0 0x366c 11358#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0_BASE_IDX 2 11359#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1 0x366d 11360#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1_BASE_IDX 2 11361#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2 0x366e 11362#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2_BASE_IDX 2 11363#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3 0x366f 11364#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3_BASE_IDX 2 11365#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4 0x3670 11366#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4_BASE_IDX 2 11367#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5 0x3671 11368#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5_BASE_IDX 2 11369#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6 0x3672 11370#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6_BASE_IDX 2 11371#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7 0x3673 11372#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7_BASE_IDX 2 11373#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8 0x3674 11374#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8_BASE_IDX 2 11375#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9 0x3675 11376#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9_BASE_IDX 2 11377#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10 0x3676 11378#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10_BASE_IDX 2 11379#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11 0x3677 11380#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11_BASE_IDX 2 11381#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12 0x3678 11382#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12_BASE_IDX 2 11383#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13 0x3679 11384#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13_BASE_IDX 2 11385#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14 0x367a 11386#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14_BASE_IDX 2 11387#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_CONTROL 0x367b 11388#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_CONTROL_BASE_IDX 2 11389#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0 0x367c 11390#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0_BASE_IDX 2 11391#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL1 0x367d 11392#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL1_BASE_IDX 2 11393#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL 0x367e 11394#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL_BASE_IDX 2 11395#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_CONTROL 0x3683 11396#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_CONTROL_BASE_IDX 2 11397#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_VBID_CONTROL 0x3684 11398#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_VBID_CONTROL_BASE_IDX 2 11399#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_STREAM_CONTROL 0x3685 11400#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_STREAM_CONTROL_BASE_IDX 2 11401#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL 0x3686 11402#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL_BASE_IDX 2 11403#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_CONTROL 0x3687 11404#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_CONTROL_BASE_IDX 2 11405#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT0 0x3688 11406#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT0_BASE_IDX 2 11407#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT1 0x3689 11408#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT1_BASE_IDX 2 11409#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_STATUS 0x368a 11410#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_STATUS_BASE_IDX 2 11411#define regDP_SYM32_ENC0_DP_SYM32_ENC_SYMBOL_COUNT_STATUS 0x368b 11412#define regDP_SYM32_ENC0_DP_SYM32_ENC_SYMBOL_COUNT_STATUS_BASE_IDX 2 11413#define regDP_SYM32_ENC0_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL 0x368c 11414#define regDP_SYM32_ENC0_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL_BASE_IDX 2 11415#define regDP_SYM32_ENC0_DP_SYM32_ENC_MEM_POWER_CONTROL 0x368d 11416#define regDP_SYM32_ENC0_DP_SYM32_ENC_MEM_POWER_CONTROL_BASE_IDX 2 11417#define regDP_SYM32_ENC0_DP_SYM32_ENC_SPARE 0x368e 11418#define regDP_SYM32_ENC0_DP_SYM32_ENC_SPARE_BASE_IDX 2 11419 11420 11421// addressBlock: dce_dc_hpo_dp_link_enc0_dispdec 11422// base address: 0x1ad5c 11423#define regDP_LINK_ENC0_DP_LINK_ENC_CLOCK_CONTROL 0x3697 11424#define regDP_LINK_ENC0_DP_LINK_ENC_CLOCK_CONTROL_BASE_IDX 2 11425#define regDP_LINK_ENC0_DP_LINK_ENC_SPARE 0x3698 11426#define regDP_LINK_ENC0_DP_LINK_ENC_SPARE_BASE_IDX 2 11427 11428 11429// addressBlock: dce_dc_hpo_dp_dphy_sym320_dispdec 11430// base address: 0x1ae00 11431#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL 0x36c0 11432#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL_BASE_IDX 2 11433#define regDP_DPHY_SYM320_DP_DPHY_SYM32_STATUS 0x36c1 11434#define regDP_DPHY_SYM320_DP_DPHY_SYM32_STATUS_BASE_IDX 2 11435#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_UPDATE 0x36c4 11436#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_UPDATE_BASE_IDX 2 11437#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL0 0x36c5 11438#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL0_BASE_IDX 2 11439#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL1 0x36c6 11440#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL1_BASE_IDX 2 11441#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL2 0x36c7 11442#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL2_BASE_IDX 2 11443#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL3 0x36c8 11444#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL3_BASE_IDX 2 11445#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC0 0x36cb 11446#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC0_BASE_IDX 2 11447#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC1 0x36cc 11448#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC1_BASE_IDX 2 11449#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC2 0x36cd 11450#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC2_BASE_IDX 2 11451#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC3 0x36ce 11452#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC3_BASE_IDX 2 11453#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS0 0x36d1 11454#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS0_BASE_IDX 2 11455#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS1 0x36d2 11456#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS1_BASE_IDX 2 11457#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS2 0x36d3 11458#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS2_BASE_IDX 2 11459#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS3 0x36d4 11460#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS3_BASE_IDX 2 11461#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG 0x36d7 11462#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG_BASE_IDX 2 11463#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED0 0x36d8 11464#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED0_BASE_IDX 2 11465#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED1 0x36d9 11466#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED1_BASE_IDX 2 11467#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED2 0x36da 11468#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED2_BASE_IDX 2 11469#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED3 0x36db 11470#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED3_BASE_IDX 2 11471#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_SQ_PULSE 0x36dc 11472#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_SQ_PULSE_BASE_IDX 2 11473#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM0 0x36dd 11474#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM0_BASE_IDX 2 11475#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM1 0x36de 11476#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM1_BASE_IDX 2 11477#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM2 0x36df 11478#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM2_BASE_IDX 2 11479#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM3 0x36e0 11480#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM3_BASE_IDX 2 11481#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM4 0x36e1 11482#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM4_BASE_IDX 2 11483#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM5 0x36e2 11484#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM5_BASE_IDX 2 11485#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM6 0x36e3 11486#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM6_BASE_IDX 2 11487#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM7 0x36e4 11488#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM7_BASE_IDX 2 11489#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM8 0x36e5 11490#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM8_BASE_IDX 2 11491#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM9 0x36e6 11492#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM9_BASE_IDX 2 11493#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM10 0x36e7 11494#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM10_BASE_IDX 2 11495#define regDP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS 0x36e8 11496#define regDP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS_BASE_IDX 2 11497#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE 0x36ea 11498#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE_BASE_IDX 2 11499#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS0 0x36eb 11500#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS0_BASE_IDX 2 11501#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS1 0x36ec 11502#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS1_BASE_IDX 2 11503#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL 0x36ed 11504#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL_BASE_IDX 2 11505#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0 0x36ee 11506#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0_BASE_IDX 2 11507#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG1 0x36ef 11508#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG1_BASE_IDX 2 11509#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_STATUS 0x36f0 11510#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_STATUS_BASE_IDX 2 11511#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_COUNT 0x36f1 11512#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_COUNT_BASE_IDX 2 11513 11514 11515// addressBlock: dce_dc_hpo_dp_stream_enc1_dispdec 11516// base address: 0x1aedc 11517#define regDP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL 0x36f7 11518#define regDP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL_BASE_IDX 2 11519#define regDP_STREAM_ENC1_DP_STREAM_ENC_INPUT_MUX_CONTROL 0x36f8 11520#define regDP_STREAM_ENC1_DP_STREAM_ENC_INPUT_MUX_CONTROL_BASE_IDX 2 11521#define regDP_STREAM_ENC1_DP_STREAM_ENC_AUDIO_CONTROL 0x36f9 11522#define regDP_STREAM_ENC1_DP_STREAM_ENC_AUDIO_CONTROL_BASE_IDX 2 11523#define regDP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0 0x36fa 11524#define regDP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0_BASE_IDX 2 11525#define regDP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1 0x36fb 11526#define regDP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1_BASE_IDX 2 11527#define regDP_STREAM_ENC1_DP_STREAM_ENC_SPARE 0x36fc 11528#define regDP_STREAM_ENC1_DP_STREAM_ENC_SPARE_BASE_IDX 2 11529 11530 11531// addressBlock: dce_dc_hpo_dp_stream_enc1_apg_apg_dispdec 11532// base address: 0x1af10 11533#define regAPG1_APG_CONTROL 0x3704 11534#define regAPG1_APG_CONTROL_BASE_IDX 2 11535#define regAPG1_APG_CONTROL2 0x3705 11536#define regAPG1_APG_CONTROL2_BASE_IDX 2 11537#define regAPG1_APG_DBG_GEN_CONTROL 0x3706 11538#define regAPG1_APG_DBG_GEN_CONTROL_BASE_IDX 2 11539#define regAPG1_APG_PACKET_CONTROL 0x3707 11540#define regAPG1_APG_PACKET_CONTROL 0x3707 11541#define regAPG1_APG_PACKET_CONTROL_BASE_IDX 2 11542#define regAPG1_APG_AUDIO_CRC_CONTROL 0x370e 11543#define regAPG1_APG_AUDIO_CRC_CONTROL_BASE_IDX 2 11544#define regAPG1_APG_AUDIO_CRC_CONTROL2 0x370f 11545#define regAPG1_APG_AUDIO_CRC_CONTROL2_BASE_IDX 2 11546#define regAPG1_APG_AUDIO_CRC_RESULT 0x3710 11547#define regAPG1_APG_AUDIO_CRC_RESULT_BASE_IDX 2 11548#define regAPG1_APG_STATUS 0x3715 11549#define regAPG1_APG_STATUS_BASE_IDX 2 11550#define regAPG1_APG_STATUS2 0x3716 11551#define regAPG1_APG_STATUS2_BASE_IDX 2 11552#define regAPG1_APG_MEM_PWR 0x3718 11553#define regAPG1_APG_MEM_PWR_BASE_IDX 2 11554#define regAPG1_APG_SPARE 0x371a 11555#define regAPG1_APG_SPARE_BASE_IDX 2 11556 11557 11558// addressBlock: dce_dc_hpo_dp_stream_enc1_dme_dme_dispdec 11559// base address: 0x1af88 11560#define regDME7_DME_CONTROL 0x3722 11561#define regDME7_DME_CONTROL_BASE_IDX 2 11562#define regDME7_DME_MEMORY_CONTROL 0x3723 11563#define regDME7_DME_MEMORY_CONTROL_BASE_IDX 2 11564 11565 11566// addressBlock: dce_dc_hpo_dp_stream_enc1_vpg_vpg_dispdec 11567// base address: 0x1af94 11568#define regVPG7_VPG_GENERIC_PACKET_ACCESS_CTRL 0x3725 11569#define regVPG7_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2 11570#define regVPG7_VPG_GENERIC_PACKET_DATA 0x3726 11571#define regVPG7_VPG_GENERIC_PACKET_DATA_BASE_IDX 2 11572#define regVPG7_VPG_GSP_FRAME_UPDATE_CTRL 0x3727 11573#define regVPG7_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2 11574#define regVPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x3728 11575#define regVPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2 11576#define regVPG7_VPG_GENERIC_STATUS 0x3729 11577#define regVPG7_VPG_GENERIC_STATUS_BASE_IDX 2 11578#define regVPG7_VPG_MEM_PWR 0x372a 11579#define regVPG7_VPG_MEM_PWR_BASE_IDX 2 11580#define regVPG7_VPG_ISRC1_2_ACCESS_CTRL 0x372b 11581#define regVPG7_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2 11582#define regVPG7_VPG_ISRC1_2_DATA 0x372c 11583#define regVPG7_VPG_ISRC1_2_DATA_BASE_IDX 2 11584#define regVPG7_VPG_MPEG_INFO0 0x372d 11585#define regVPG7_VPG_MPEG_INFO0_BASE_IDX 2 11586#define regVPG7_VPG_MPEG_INFO1 0x372e 11587#define regVPG7_VPG_MPEG_INFO1_BASE_IDX 2 11588 11589 11590// addressBlock: dce_dc_hpo_dp_sym32_enc1_dispdec 11591// base address: 0x1afc4 11592#define regDP_SYM32_ENC1_DP_SYM32_ENC_CONTROL 0x3731 11593#define regDP_SYM32_ENC1_DP_SYM32_ENC_CONTROL_BASE_IDX 2 11594#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_FIFO_CONTROL 0x3732 11595#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_FIFO_CONTROL_BASE_IDX 2 11596#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL 0x3733 11597#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 11598#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL 0x3734 11599#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 11600#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT 0x3735 11601#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT_BASE_IDX 2 11602#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA0 0x3736 11603#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA0_BASE_IDX 2 11604#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA1 0x3737 11605#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA1_BASE_IDX 2 11606#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA2 0x3738 11607#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA2_BASE_IDX 2 11608#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA3 0x3739 11609#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA3_BASE_IDX 2 11610#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA4 0x373a 11611#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA4_BASE_IDX 2 11612#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA5 0x373b 11613#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA5_BASE_IDX 2 11614#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA6 0x373c 11615#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA6_BASE_IDX 2 11616#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA7 0x373d 11617#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA7_BASE_IDX 2 11618#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA8 0x373e 11619#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA8_BASE_IDX 2 11620#define regDP_SYM32_ENC1_DP_SYM32_ENC_HBLANK_CONTROL 0x373f 11621#define regDP_SYM32_ENC1_DP_SYM32_ENC_HBLANK_CONTROL_BASE_IDX 2 11622#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0 0x3740 11623#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0_BASE_IDX 2 11624#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1 0x3741 11625#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1_BASE_IDX 2 11626#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2 0x3742 11627#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2_BASE_IDX 2 11628#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3 0x3743 11629#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3_BASE_IDX 2 11630#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4 0x3744 11631#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4_BASE_IDX 2 11632#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5 0x3745 11633#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5_BASE_IDX 2 11634#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6 0x3746 11635#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6_BASE_IDX 2 11636#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7 0x3747 11637#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7_BASE_IDX 2 11638#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8 0x3748 11639#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8_BASE_IDX 2 11640#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9 0x3749 11641#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9_BASE_IDX 2 11642#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10 0x374a 11643#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10_BASE_IDX 2 11644#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11 0x374b 11645#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11_BASE_IDX 2 11646#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12 0x374c 11647#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12_BASE_IDX 2 11648#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13 0x374d 11649#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13_BASE_IDX 2 11650#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14 0x374e 11651#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14_BASE_IDX 2 11652#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_CONTROL 0x374f 11653#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_CONTROL_BASE_IDX 2 11654#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0 0x3750 11655#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0_BASE_IDX 2 11656#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL1 0x3751 11657#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL1_BASE_IDX 2 11658#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL 0x3752 11659#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL_BASE_IDX 2 11660#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_CONTROL 0x3757 11661#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_CONTROL_BASE_IDX 2 11662#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_VBID_CONTROL 0x3758 11663#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_VBID_CONTROL_BASE_IDX 2 11664#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_STREAM_CONTROL 0x3759 11665#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_STREAM_CONTROL_BASE_IDX 2 11666#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL 0x375a 11667#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL_BASE_IDX 2 11668#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_CONTROL 0x375b 11669#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_CONTROL_BASE_IDX 2 11670#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT0 0x375c 11671#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT0_BASE_IDX 2 11672#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT1 0x375d 11673#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT1_BASE_IDX 2 11674#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_STATUS 0x375e 11675#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_STATUS_BASE_IDX 2 11676#define regDP_SYM32_ENC1_DP_SYM32_ENC_SYMBOL_COUNT_STATUS 0x375f 11677#define regDP_SYM32_ENC1_DP_SYM32_ENC_SYMBOL_COUNT_STATUS_BASE_IDX 2 11678#define regDP_SYM32_ENC1_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL 0x3760 11679#define regDP_SYM32_ENC1_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL_BASE_IDX 2 11680#define regDP_SYM32_ENC1_DP_SYM32_ENC_MEM_POWER_CONTROL 0x3761 11681#define regDP_SYM32_ENC1_DP_SYM32_ENC_MEM_POWER_CONTROL_BASE_IDX 2 11682#define regDP_SYM32_ENC1_DP_SYM32_ENC_SPARE 0x3762 11683#define regDP_SYM32_ENC1_DP_SYM32_ENC_SPARE_BASE_IDX 2 11684 11685 11686// addressBlock: dce_dc_hpo_dp_link_enc1_dispdec 11687// base address: 0x1b0ac 11688#define regDP_LINK_ENC1_DP_LINK_ENC_CLOCK_CONTROL 0x376b 11689#define regDP_LINK_ENC1_DP_LINK_ENC_CLOCK_CONTROL_BASE_IDX 2 11690#define regDP_LINK_ENC1_DP_LINK_ENC_SPARE 0x376c 11691#define regDP_LINK_ENC1_DP_LINK_ENC_SPARE_BASE_IDX 2 11692 11693 11694// addressBlock: dce_dc_hpo_dp_dphy_sym321_dispdec 11695// base address: 0x1b150 11696#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL 0x3794 11697#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL_BASE_IDX 2 11698#define regDP_DPHY_SYM321_DP_DPHY_SYM32_STATUS 0x3795 11699#define regDP_DPHY_SYM321_DP_DPHY_SYM32_STATUS_BASE_IDX 2 11700#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_UPDATE 0x3798 11701#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_UPDATE_BASE_IDX 2 11702#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL0 0x3799 11703#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL0_BASE_IDX 2 11704#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL1 0x379a 11705#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL1_BASE_IDX 2 11706#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL2 0x379b 11707#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL2_BASE_IDX 2 11708#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL3 0x379c 11709#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL3_BASE_IDX 2 11710#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC0 0x379f 11711#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC0_BASE_IDX 2 11712#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC1 0x37a0 11713#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC1_BASE_IDX 2 11714#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC2 0x37a1 11715#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC2_BASE_IDX 2 11716#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC3 0x37a2 11717#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC3_BASE_IDX 2 11718#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS0 0x37a5 11719#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS0_BASE_IDX 2 11720#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS1 0x37a6 11721#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS1_BASE_IDX 2 11722#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS2 0x37a7 11723#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS2_BASE_IDX 2 11724#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS3 0x37a8 11725#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS3_BASE_IDX 2 11726#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG 0x37ab 11727#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG_BASE_IDX 2 11728#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED0 0x37ac 11729#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED0_BASE_IDX 2 11730#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED1 0x37ad 11731#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED1_BASE_IDX 2 11732#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED2 0x37ae 11733#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED2_BASE_IDX 2 11734#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED3 0x37af 11735#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED3_BASE_IDX 2 11736#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_SQ_PULSE 0x37b0 11737#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_SQ_PULSE_BASE_IDX 2 11738#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM0 0x37b1 11739#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM0_BASE_IDX 2 11740#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM1 0x37b2 11741#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM1_BASE_IDX 2 11742#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM2 0x37b3 11743#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM2_BASE_IDX 2 11744#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM3 0x37b4 11745#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM3_BASE_IDX 2 11746#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM4 0x37b5 11747#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM4_BASE_IDX 2 11748#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM5 0x37b6 11749#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM5_BASE_IDX 2 11750#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM6 0x37b7 11751#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM6_BASE_IDX 2 11752#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM7 0x37b8 11753#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM7_BASE_IDX 2 11754#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM8 0x37b9 11755#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM8_BASE_IDX 2 11756#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM9 0x37ba 11757#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM9_BASE_IDX 2 11758#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM10 0x37bb 11759#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM10_BASE_IDX 2 11760#define regDP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS 0x37bc 11761#define regDP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS_BASE_IDX 2 11762#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE 0x37be 11763#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE_BASE_IDX 2 11764#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS0 0x37bf 11765#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS0_BASE_IDX 2 11766#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS1 0x37c0 11767#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS1_BASE_IDX 2 11768#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL 0x37c1 11769#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL_BASE_IDX 2 11770#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0 0x37c2 11771#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0_BASE_IDX 2 11772#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG1 0x37c3 11773#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG1_BASE_IDX 2 11774#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_STATUS 0x37c4 11775#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_STATUS_BASE_IDX 2 11776#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_COUNT 0x37c5 11777#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_COUNT_BASE_IDX 2 11778 11779 11780// addressBlock: dce_dc_hpo_dp_stream_enc2_dispdec 11781// base address: 0x1b22c 11782#define regDP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL 0x37cb 11783#define regDP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL_BASE_IDX 2 11784#define regDP_STREAM_ENC2_DP_STREAM_ENC_INPUT_MUX_CONTROL 0x37cc 11785#define regDP_STREAM_ENC2_DP_STREAM_ENC_INPUT_MUX_CONTROL_BASE_IDX 2 11786#define regDP_STREAM_ENC2_DP_STREAM_ENC_AUDIO_CONTROL 0x37cd 11787#define regDP_STREAM_ENC2_DP_STREAM_ENC_AUDIO_CONTROL_BASE_IDX 2 11788#define regDP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0 0x37ce 11789#define regDP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0_BASE_IDX 2 11790#define regDP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1 0x37cf 11791#define regDP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1_BASE_IDX 2 11792#define regDP_STREAM_ENC2_DP_STREAM_ENC_SPARE 0x37d0 11793#define regDP_STREAM_ENC2_DP_STREAM_ENC_SPARE_BASE_IDX 2 11794 11795 11796// addressBlock: dce_dc_hpo_dp_stream_enc2_apg_apg_dispdec 11797// base address: 0x1b260 11798#define regAPG2_APG_CONTROL 0x37d8 11799#define regAPG2_APG_CONTROL_BASE_IDX 2 11800#define regAPG2_APG_CONTROL2 0x37d9 11801#define regAPG2_APG_CONTROL2_BASE_IDX 2 11802#define regAPG2_APG_DBG_GEN_CONTROL 0x37da 11803#define regAPG2_APG_DBG_GEN_CONTROL_BASE_IDX 2 11804#define regAPG2_APG_PACKET_CONTROL 0x37db 11805#define regAPG2_APG_PACKET_CONTROL_BASE_IDX 2 11806#define regAPG2_APG_AUDIO_CRC_CONTROL 0x37e2 11807#define regAPG2_APG_AUDIO_CRC_CONTROL_BASE_IDX 2 11808#define regAPG2_APG_AUDIO_CRC_CONTROL2 0x37e3 11809#define regAPG2_APG_AUDIO_CRC_CONTROL2_BASE_IDX 2 11810#define regAPG2_APG_AUDIO_CRC_RESULT 0x37e4 11811#define regAPG2_APG_AUDIO_CRC_RESULT_BASE_IDX 2 11812#define regAPG2_APG_STATUS 0x37e9 11813#define regAPG2_APG_STATUS_BASE_IDX 2 11814#define regAPG2_APG_STATUS2 0x37ea 11815#define regAPG2_APG_STATUS2_BASE_IDX 2 11816#define regAPG2_APG_MEM_PWR 0x37ec 11817#define regAPG2_APG_MEM_PWR_BASE_IDX 2 11818#define regAPG2_APG_SPARE 0x37ee 11819#define regAPG2_APG_SPARE_BASE_IDX 2 11820 11821 11822// addressBlock: dce_dc_hpo_dp_stream_enc2_dme_dme_dispdec 11823// base address: 0x1b2d8 11824#define regDME8_DME_CONTROL 0x37f6 11825#define regDME8_DME_CONTROL_BASE_IDX 2 11826#define regDME8_DME_MEMORY_CONTROL 0x37f7 11827#define regDME8_DME_MEMORY_CONTROL_BASE_IDX 2 11828 11829 11830// addressBlock: dce_dc_hpo_dp_stream_enc2_vpg_vpg_dispdec 11831// base address: 0x1b2e4 11832#define regVPG8_VPG_GENERIC_PACKET_ACCESS_CTRL 0x37f9 11833#define regVPG8_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2 11834#define regVPG8_VPG_GENERIC_PACKET_DATA 0x37fa 11835#define regVPG8_VPG_GENERIC_PACKET_DATA_BASE_IDX 2 11836#define regVPG8_VPG_GSP_FRAME_UPDATE_CTRL 0x37fb 11837#define regVPG8_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2 11838#define regVPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x37fc 11839#define regVPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2 11840#define regVPG8_VPG_GENERIC_STATUS 0x37fd 11841#define regVPG8_VPG_GENERIC_STATUS_BASE_IDX 2 11842#define regVPG8_VPG_MEM_PWR 0x37fe 11843#define regVPG8_VPG_MEM_PWR_BASE_IDX 2 11844#define regVPG8_VPG_ISRC1_2_ACCESS_CTRL 0x37ff 11845#define regVPG8_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2 11846#define regVPG8_VPG_ISRC1_2_DATA 0x3800 11847#define regVPG8_VPG_ISRC1_2_DATA_BASE_IDX 2 11848#define regVPG8_VPG_MPEG_INFO0 0x3801 11849#define regVPG8_VPG_MPEG_INFO0_BASE_IDX 2 11850#define regVPG8_VPG_MPEG_INFO1 0x3802 11851#define regVPG8_VPG_MPEG_INFO1_BASE_IDX 2 11852 11853 11854// addressBlock: dce_dc_hpo_dp_sym32_enc2_dispdec 11855// base address: 0x1b314 11856#define regDP_SYM32_ENC2_DP_SYM32_ENC_CONTROL 0x3805 11857#define regDP_SYM32_ENC2_DP_SYM32_ENC_CONTROL_BASE_IDX 2 11858#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_FIFO_CONTROL 0x3806 11859#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_FIFO_CONTROL_BASE_IDX 2 11860#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL 0x3807 11861#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 11862#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL 0x3808 11863#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 11864#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT 0x3809 11865#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT_BASE_IDX 2 11866#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA0 0x380a 11867#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA0_BASE_IDX 2 11868#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA1 0x380b 11869#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA1_BASE_IDX 2 11870#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA2 0x380c 11871#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA2_BASE_IDX 2 11872#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA3 0x380d 11873#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA3_BASE_IDX 2 11874#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA4 0x380e 11875#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA4_BASE_IDX 2 11876#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA5 0x380f 11877#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA5_BASE_IDX 2 11878#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA6 0x3810 11879#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA6_BASE_IDX 2 11880#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA7 0x3811 11881#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA7_BASE_IDX 2 11882#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA8 0x3812 11883#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA8_BASE_IDX 2 11884#define regDP_SYM32_ENC2_DP_SYM32_ENC_HBLANK_CONTROL 0x3813 11885#define regDP_SYM32_ENC2_DP_SYM32_ENC_HBLANK_CONTROL_BASE_IDX 2 11886#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0 0x3814 11887#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0_BASE_IDX 2 11888#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1 0x3815 11889#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1_BASE_IDX 2 11890#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2 0x3816 11891#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2_BASE_IDX 2 11892#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3 0x3817 11893#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3_BASE_IDX 2 11894#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4 0x3818 11895#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4_BASE_IDX 2 11896#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5 0x3819 11897#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5_BASE_IDX 2 11898#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6 0x381a 11899#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6_BASE_IDX 2 11900#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7 0x381b 11901#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7_BASE_IDX 2 11902#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8 0x381c 11903#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8_BASE_IDX 2 11904#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9 0x381d 11905#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9_BASE_IDX 2 11906#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10 0x381e 11907#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10_BASE_IDX 2 11908#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11 0x381f 11909#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11_BASE_IDX 2 11910#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12 0x3820 11911#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12_BASE_IDX 2 11912#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13 0x3821 11913#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13_BASE_IDX 2 11914#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14 0x3822 11915#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14_BASE_IDX 2 11916#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_CONTROL 0x3823 11917#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_CONTROL_BASE_IDX 2 11918#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0 0x3824 11919#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0_BASE_IDX 2 11920#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL1 0x3825 11921#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL1_BASE_IDX 2 11922#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL 0x3826 11923#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL_BASE_IDX 2 11924#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_CONTROL 0x382b 11925#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_CONTROL_BASE_IDX 2 11926#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_VBID_CONTROL 0x382c 11927#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_VBID_CONTROL_BASE_IDX 2 11928#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_STREAM_CONTROL 0x382d 11929#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_STREAM_CONTROL_BASE_IDX 2 11930#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL 0x382e 11931#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL_BASE_IDX 2 11932#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_CONTROL 0x382f 11933#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_CONTROL_BASE_IDX 2 11934#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT0 0x3830 11935#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT0_BASE_IDX 2 11936#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT1 0x3831 11937#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT1_BASE_IDX 2 11938#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_STATUS 0x3832 11939#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_STATUS_BASE_IDX 2 11940#define regDP_SYM32_ENC2_DP_SYM32_ENC_SYMBOL_COUNT_STATUS 0x3833 11941#define regDP_SYM32_ENC2_DP_SYM32_ENC_SYMBOL_COUNT_STATUS_BASE_IDX 2 11942#define regDP_SYM32_ENC2_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL 0x3834 11943#define regDP_SYM32_ENC2_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL_BASE_IDX 2 11944#define regDP_SYM32_ENC2_DP_SYM32_ENC_MEM_POWER_CONTROL 0x3835 11945#define regDP_SYM32_ENC2_DP_SYM32_ENC_MEM_POWER_CONTROL_BASE_IDX 2 11946#define regDP_SYM32_ENC2_DP_SYM32_ENC_SPARE 0x3836 11947#define regDP_SYM32_ENC2_DP_SYM32_ENC_SPARE_BASE_IDX 2 11948 11949 11950// addressBlock: dce_dc_hpo_dp_stream_enc3_dispdec 11951// base address: 0x1b57c 11952#define regDP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL 0x389f 11953#define regDP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL_BASE_IDX 2 11954#define regDP_STREAM_ENC3_DP_STREAM_ENC_INPUT_MUX_CONTROL 0x38a0 11955#define regDP_STREAM_ENC3_DP_STREAM_ENC_INPUT_MUX_CONTROL_BASE_IDX 2 11956#define regDP_STREAM_ENC3_DP_STREAM_ENC_AUDIO_CONTROL 0x38a1 11957#define regDP_STREAM_ENC3_DP_STREAM_ENC_AUDIO_CONTROL_BASE_IDX 2 11958#define regDP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0 0x38a2 11959#define regDP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0_BASE_IDX 2 11960#define regDP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1 0x38a3 11961#define regDP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1_BASE_IDX 2 11962#define regDP_STREAM_ENC3_DP_STREAM_ENC_SPARE 0x38a4 11963#define regDP_STREAM_ENC3_DP_STREAM_ENC_SPARE_BASE_IDX 2 11964 11965 11966// addressBlock: dce_dc_hpo_dp_stream_enc3_apg_apg_dispdec 11967// base address: 0x1b5b0 11968#define regAPG3_APG_CONTROL 0x38ac 11969#define regAPG3_APG_CONTROL_BASE_IDX 2 11970#define regAPG3_APG_CONTROL2 0x38ad 11971#define regAPG3_APG_CONTROL2_BASE_IDX 2 11972#define regAPG3_APG_DBG_GEN_CONTROL 0x38ae 11973#define regAPG3_APG_DBG_GEN_CONTROL_BASE_IDX 2 11974#define regAPG3_APG_PACKET_CONTROL 0x38af 11975#define regAPG3_APG_PACKET_CONTROL_BASE_IDX 2 11976#define regAPG3_APG_AUDIO_CRC_CONTROL 0x38b6 11977#define regAPG3_APG_AUDIO_CRC_CONTROL_BASE_IDX 2 11978#define regAPG3_APG_AUDIO_CRC_CONTROL2 0x38b7 11979#define regAPG3_APG_AUDIO_CRC_CONTROL2_BASE_IDX 2 11980#define regAPG3_APG_AUDIO_CRC_RESULT 0x38b8 11981#define regAPG3_APG_AUDIO_CRC_RESULT_BASE_IDX 2 11982#define regAPG3_APG_STATUS 0x38bd 11983#define regAPG3_APG_STATUS_BASE_IDX 2 11984#define regAPG3_APG_STATUS2 0x38be 11985#define regAPG3_APG_STATUS2_BASE_IDX 2 11986#define regAPG3_APG_MEM_PWR 0x38c0 11987#define regAPG3_APG_MEM_PWR_BASE_IDX 2 11988#define regAPG3_APG_SPARE 0x38c2 11989#define regAPG3_APG_SPARE_BASE_IDX 2 11990 11991 11992// addressBlock: dce_dc_hpo_dp_stream_enc3_dme_dme_dispdec 11993// base address: 0x1b628 11994#define regDME9_DME_CONTROL 0x38ca 11995#define regDME9_DME_CONTROL_BASE_IDX 2 11996#define regDME9_DME_MEMORY_CONTROL 0x38cb 11997#define regDME9_DME_MEMORY_CONTROL_BASE_IDX 2 11998 11999 12000// addressBlock: dce_dc_hpo_dp_stream_enc3_vpg_vpg_dispdec 12001// base address: 0x1b634 12002#define regVPG9_VPG_GENERIC_PACKET_ACCESS_CTRL 0x38cd 12003#define regVPG9_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2 12004#define regVPG9_VPG_GENERIC_PACKET_DATA 0x38ce 12005#define regVPG9_VPG_GENERIC_PACKET_DATA_BASE_IDX 2 12006#define regVPG9_VPG_GSP_FRAME_UPDATE_CTRL 0x38cf 12007#define regVPG9_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2 12008#define regVPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x38d0 12009#define regVPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2 12010#define regVPG9_VPG_GENERIC_STATUS 0x38d1 12011#define regVPG9_VPG_GENERIC_STATUS_BASE_IDX 2 12012#define regVPG9_VPG_MEM_PWR 0x38d2 12013#define regVPG9_VPG_MEM_PWR_BASE_IDX 2 12014#define regVPG9_VPG_ISRC1_2_ACCESS_CTRL 0x38d3 12015#define regVPG9_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2 12016#define regVPG9_VPG_ISRC1_2_DATA 0x38d4 12017#define regVPG9_VPG_ISRC1_2_DATA_BASE_IDX 2 12018#define regVPG9_VPG_MPEG_INFO0 0x38d5 12019#define regVPG9_VPG_MPEG_INFO0_BASE_IDX 2 12020#define regVPG9_VPG_MPEG_INFO1 0x38d6 12021#define regVPG9_VPG_MPEG_INFO1_BASE_IDX 2 12022 12023 12024// addressBlock: dce_dc_hpo_dp_sym32_enc3_dispdec 12025// base address: 0x1b664 12026#define regDP_SYM32_ENC3_DP_SYM32_ENC_CONTROL 0x38d9 12027#define regDP_SYM32_ENC3_DP_SYM32_ENC_CONTROL_BASE_IDX 2 12028#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_FIFO_CONTROL 0x38da 12029#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_FIFO_CONTROL_BASE_IDX 2 12030#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL 0x38db 12031#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 12032#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL 0x38dc 12033#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 12034#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT 0x38dd 12035#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT_BASE_IDX 2 12036#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA0 0x38de 12037#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA0_BASE_IDX 2 12038#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA1 0x38df 12039#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA1_BASE_IDX 2 12040#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA2 0x38e0 12041#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA2_BASE_IDX 2 12042#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA3 0x38e1 12043#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA3_BASE_IDX 2 12044#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA4 0x38e2 12045#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA4_BASE_IDX 2 12046#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA5 0x38e3 12047#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA5_BASE_IDX 2 12048#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA6 0x38e4 12049#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA6_BASE_IDX 2 12050#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA7 0x38e5 12051#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA7_BASE_IDX 2 12052#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA8 0x38e6 12053#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA8_BASE_IDX 2 12054#define regDP_SYM32_ENC3_DP_SYM32_ENC_HBLANK_CONTROL 0x38e7 12055#define regDP_SYM32_ENC3_DP_SYM32_ENC_HBLANK_CONTROL_BASE_IDX 2 12056#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0 0x38e8 12057#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0_BASE_IDX 2 12058#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1 0x38e9 12059#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1_BASE_IDX 2 12060#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2 0x38ea 12061#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2_BASE_IDX 2 12062#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3 0x38eb 12063#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3_BASE_IDX 2 12064#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4 0x38ec 12065#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4_BASE_IDX 2 12066#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5 0x38ed 12067#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5_BASE_IDX 2 12068#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6 0x38ee 12069#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6_BASE_IDX 2 12070#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7 0x38ef 12071#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7_BASE_IDX 2 12072#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8 0x38f0 12073#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8_BASE_IDX 2 12074#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9 0x38f1 12075#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9_BASE_IDX 2 12076#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10 0x38f2 12077#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10_BASE_IDX 2 12078#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11 0x38f3 12079#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11_BASE_IDX 2 12080#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12 0x38f4 12081#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12_BASE_IDX 2 12082#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13 0x38f5 12083#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13_BASE_IDX 2 12084#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14 0x38f6 12085#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14_BASE_IDX 2 12086#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_CONTROL 0x38f7 12087#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_CONTROL_BASE_IDX 2 12088#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0 0x38f8 12089#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0_BASE_IDX 2 12090#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL1 0x38f9 12091#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL1_BASE_IDX 2 12092#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL 0x38fa 12093#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL_BASE_IDX 2 12094#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_CONTROL 0x38ff 12095#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_CONTROL_BASE_IDX 2 12096#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_VBID_CONTROL 0x3900 12097#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_VBID_CONTROL_BASE_IDX 2 12098#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_STREAM_CONTROL 0x3901 12099#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_STREAM_CONTROL_BASE_IDX 2 12100#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL 0x3902 12101#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL_BASE_IDX 2 12102#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_CONTROL 0x3903 12103#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_CONTROL_BASE_IDX 2 12104#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT0 0x3904 12105#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT0_BASE_IDX 2 12106#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT1 0x3905 12107#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT1_BASE_IDX 2 12108#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_STATUS 0x3906 12109#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_STATUS_BASE_IDX 2 12110#define regDP_SYM32_ENC3_DP_SYM32_ENC_SYMBOL_COUNT_STATUS 0x3907 12111#define regDP_SYM32_ENC3_DP_SYM32_ENC_SYMBOL_COUNT_STATUS_BASE_IDX 2 12112#define regDP_SYM32_ENC3_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL 0x3908 12113#define regDP_SYM32_ENC3_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL_BASE_IDX 2 12114#define regDP_SYM32_ENC3_DP_SYM32_ENC_MEM_POWER_CONTROL 0x3909 12115#define regDP_SYM32_ENC3_DP_SYM32_ENC_MEM_POWER_CONTROL_BASE_IDX 2 12116#define regDP_SYM32_ENC3_DP_SYM32_ENC_SPARE 0x390a 12117#define regDP_SYM32_ENC3_DP_SYM32_ENC_SPARE_BASE_IDX 2 12118 12119 12120// addressBlock: dce_dc_mpc_mpcc0_dispdec 12121// base address: 0x0 12122#define regMPCC0_MPCC_TOP_SEL 0x0000 12123#define regMPCC0_MPCC_TOP_SEL_BASE_IDX 3 12124#define regMPCC0_MPCC_BOT_SEL 0x0001 12125#define regMPCC0_MPCC_BOT_SEL_BASE_IDX 3 12126#define regMPCC0_MPCC_OPP_ID 0x0002 12127#define regMPCC0_MPCC_OPP_ID_BASE_IDX 3 12128#define regMPCC0_MPCC_CONTROL 0x0003 12129#define regMPCC0_MPCC_CONTROL_BASE_IDX 3 12130#define regMPCC0_MPCC_SM_CONTROL 0x0004 12131#define regMPCC0_MPCC_SM_CONTROL_BASE_IDX 3 12132#define regMPCC0_MPCC_UPDATE_LOCK_SEL 0x0005 12133#define regMPCC0_MPCC_UPDATE_LOCK_SEL_BASE_IDX 3 12134#define regMPCC0_MPCC_TOP_GAIN 0x0006 12135#define regMPCC0_MPCC_TOP_GAIN_BASE_IDX 3 12136#define regMPCC0_MPCC_BOT_GAIN_INSIDE 0x0007 12137#define regMPCC0_MPCC_BOT_GAIN_INSIDE_BASE_IDX 3 12138#define regMPCC0_MPCC_BOT_GAIN_OUTSIDE 0x0008 12139#define regMPCC0_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX 3 12140#define regMPCC0_MPCC_MOVABLE_CM_LOCATION_CONTROL 0x0009 12141#define regMPCC0_MPCC_MOVABLE_CM_LOCATION_CONTROL_BASE_IDX 3 12142#define regMPCC0_MPCC_BG_R_CR 0x000a 12143#define regMPCC0_MPCC_BG_R_CR_BASE_IDX 3 12144#define regMPCC0_MPCC_BG_G_Y 0x000b 12145#define regMPCC0_MPCC_BG_G_Y_BASE_IDX 3 12146#define regMPCC0_MPCC_BG_B_CB 0x000c 12147#define regMPCC0_MPCC_BG_B_CB_BASE_IDX 3 12148#define regMPCC0_MPCC_MEM_PWR_CTRL 0x000d 12149#define regMPCC0_MPCC_MEM_PWR_CTRL_BASE_IDX 3 12150#define regMPCC0_MPCC_STATUS 0x000e 12151#define regMPCC0_MPCC_STATUS_BASE_IDX 3 12152 12153 12154// addressBlock: dce_dc_mpc_mpcc1_dispdec 12155// base address: 0x54 12156#define regMPCC1_MPCC_TOP_SEL 0x0015 12157#define regMPCC1_MPCC_TOP_SEL_BASE_IDX 3 12158#define regMPCC1_MPCC_BOT_SEL 0x0016 12159#define regMPCC1_MPCC_BOT_SEL_BASE_IDX 3 12160#define regMPCC1_MPCC_OPP_ID 0x0017 12161#define regMPCC1_MPCC_OPP_ID_BASE_IDX 3 12162#define regMPCC1_MPCC_CONTROL 0x0018 12163#define regMPCC1_MPCC_CONTROL_BASE_IDX 3 12164#define regMPCC1_MPCC_SM_CONTROL 0x0019 12165#define regMPCC1_MPCC_SM_CONTROL_BASE_IDX 3 12166#define regMPCC1_MPCC_UPDATE_LOCK_SEL 0x001a 12167#define regMPCC1_MPCC_UPDATE_LOCK_SEL_BASE_IDX 3 12168#define regMPCC1_MPCC_TOP_GAIN 0x001b 12169#define regMPCC1_MPCC_TOP_GAIN_BASE_IDX 3 12170#define regMPCC1_MPCC_BOT_GAIN_INSIDE 0x001c 12171#define regMPCC1_MPCC_BOT_GAIN_INSIDE_BASE_IDX 3 12172#define regMPCC1_MPCC_BOT_GAIN_OUTSIDE 0x001d 12173#define regMPCC1_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX 3 12174#define regMPCC1_MPCC_MOVABLE_CM_LOCATION_CONTROL 0x001e 12175#define regMPCC1_MPCC_MOVABLE_CM_LOCATION_CONTROL_BASE_IDX 3 12176#define regMPCC1_MPCC_BG_R_CR 0x001f 12177#define regMPCC1_MPCC_BG_R_CR_BASE_IDX 3 12178#define regMPCC1_MPCC_BG_G_Y 0x0020 12179#define regMPCC1_MPCC_BG_G_Y_BASE_IDX 3 12180#define regMPCC1_MPCC_BG_B_CB 0x0021 12181#define regMPCC1_MPCC_BG_B_CB_BASE_IDX 3 12182#define regMPCC1_MPCC_MEM_PWR_CTRL 0x0022 12183#define regMPCC1_MPCC_MEM_PWR_CTRL_BASE_IDX 3 12184#define regMPCC1_MPCC_STATUS 0x0023 12185#define regMPCC1_MPCC_STATUS_BASE_IDX 3 12186 12187 12188// addressBlock: dce_dc_mpc_mpcc2_dispdec 12189// base address: 0xa8 12190#define regMPCC2_MPCC_TOP_SEL 0x002a 12191#define regMPCC2_MPCC_TOP_SEL_BASE_IDX 3 12192#define regMPCC2_MPCC_BOT_SEL 0x002b 12193#define regMPCC2_MPCC_BOT_SEL_BASE_IDX 3 12194#define regMPCC2_MPCC_OPP_ID 0x002c 12195#define regMPCC2_MPCC_OPP_ID_BASE_IDX 3 12196#define regMPCC2_MPCC_CONTROL 0x002d 12197#define regMPCC2_MPCC_CONTROL_BASE_IDX 3 12198#define regMPCC2_MPCC_SM_CONTROL 0x002e 12199#define regMPCC2_MPCC_SM_CONTROL_BASE_IDX 3 12200#define regMPCC2_MPCC_UPDATE_LOCK_SEL 0x002f 12201#define regMPCC2_MPCC_UPDATE_LOCK_SEL_BASE_IDX 3 12202#define regMPCC2_MPCC_TOP_GAIN 0x0030 12203#define regMPCC2_MPCC_TOP_GAIN_BASE_IDX 3 12204#define regMPCC2_MPCC_BOT_GAIN_INSIDE 0x0031 12205#define regMPCC2_MPCC_BOT_GAIN_INSIDE_BASE_IDX 3 12206#define regMPCC2_MPCC_BOT_GAIN_OUTSIDE 0x0032 12207#define regMPCC2_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX 3 12208#define regMPCC2_MPCC_MOVABLE_CM_LOCATION_CONTROL 0x0033 12209#define regMPCC2_MPCC_MOVABLE_CM_LOCATION_CONTROL_BASE_IDX 3 12210#define regMPCC2_MPCC_BG_R_CR 0x0034 12211#define regMPCC2_MPCC_BG_R_CR_BASE_IDX 3 12212#define regMPCC2_MPCC_BG_G_Y 0x0035 12213#define regMPCC2_MPCC_BG_G_Y_BASE_IDX 3 12214#define regMPCC2_MPCC_BG_B_CB 0x0036 12215#define regMPCC2_MPCC_BG_B_CB_BASE_IDX 3 12216#define regMPCC2_MPCC_MEM_PWR_CTRL 0x0037 12217#define regMPCC2_MPCC_MEM_PWR_CTRL_BASE_IDX 3 12218#define regMPCC2_MPCC_STATUS 0x0038 12219#define regMPCC2_MPCC_STATUS_BASE_IDX 3 12220 12221 12222// addressBlock: dce_dc_mpc_mpcc3_dispdec 12223// base address: 0xfc 12224#define regMPCC3_MPCC_TOP_SEL 0x003f 12225#define regMPCC3_MPCC_TOP_SEL_BASE_IDX 3 12226#define regMPCC3_MPCC_BOT_SEL 0x0040 12227#define regMPCC3_MPCC_BOT_SEL_BASE_IDX 3 12228#define regMPCC3_MPCC_OPP_ID 0x0041 12229#define regMPCC3_MPCC_OPP_ID_BASE_IDX 3 12230#define regMPCC3_MPCC_CONTROL 0x0042 12231#define regMPCC3_MPCC_CONTROL_BASE_IDX 3 12232#define regMPCC3_MPCC_SM_CONTROL 0x0043 12233#define regMPCC3_MPCC_SM_CONTROL_BASE_IDX 3 12234#define regMPCC3_MPCC_UPDATE_LOCK_SEL 0x0044 12235#define regMPCC3_MPCC_UPDATE_LOCK_SEL_BASE_IDX 3 12236#define regMPCC3_MPCC_TOP_GAIN 0x0045 12237#define regMPCC3_MPCC_TOP_GAIN_BASE_IDX 3 12238#define regMPCC3_MPCC_BOT_GAIN_INSIDE 0x0046 12239#define regMPCC3_MPCC_BOT_GAIN_INSIDE_BASE_IDX 3 12240#define regMPCC3_MPCC_BOT_GAIN_OUTSIDE 0x0047 12241#define regMPCC3_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX 3 12242#define regMPCC3_MPCC_MOVABLE_CM_LOCATION_CONTROL 0x0048 12243#define regMPCC3_MPCC_MOVABLE_CM_LOCATION_CONTROL_BASE_IDX 3 12244#define regMPCC3_MPCC_BG_R_CR 0x0049 12245#define regMPCC3_MPCC_BG_R_CR_BASE_IDX 3 12246#define regMPCC3_MPCC_BG_G_Y 0x004a 12247#define regMPCC3_MPCC_BG_G_Y_BASE_IDX 3 12248#define regMPCC3_MPCC_BG_B_CB 0x004b 12249#define regMPCC3_MPCC_BG_B_CB_BASE_IDX 3 12250#define regMPCC3_MPCC_MEM_PWR_CTRL 0x004c 12251#define regMPCC3_MPCC_MEM_PWR_CTRL_BASE_IDX 3 12252#define regMPCC3_MPCC_STATUS 0x004d 12253#define regMPCC3_MPCC_STATUS_BASE_IDX 3 12254 12255 12256 12257// addressBlock: dce_dc_mpc_mpcc_ogam0_dispdec 12258// base address: 0x0 12259#define regMPCC_OGAM0_MPCC_OGAM_CONTROL 0x00a8 12260#define regMPCC_OGAM0_MPCC_OGAM_CONTROL_BASE_IDX 3 12261#define regMPCC_OGAM0_MPCC_OGAM_LUT_INDEX 0x00a9 12262#define regMPCC_OGAM0_MPCC_OGAM_LUT_INDEX_BASE_IDX 3 12263#define regMPCC_OGAM0_MPCC_OGAM_LUT_DATA 0x00aa 12264#define regMPCC_OGAM0_MPCC_OGAM_LUT_DATA_BASE_IDX 3 12265#define regMPCC_OGAM0_MPCC_OGAM_LUT_CONTROL 0x00ab 12266#define regMPCC_OGAM0_MPCC_OGAM_LUT_CONTROL_BASE_IDX 3 12267#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B 0x00ac 12268#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX 3 12269#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G 0x00ad 12270#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX 3 12271#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R 0x00ae 12272#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX 3 12273#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B 0x00af 12274#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX 3 12275#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G 0x00b0 12276#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 3 12277#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R 0x00b1 12278#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX 3 12279#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_B 0x00b2 12280#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX 3 12281#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_G 0x00b3 12282#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX 3 12283#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_R 0x00b4 12284#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX 3 12285#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B 0x00b5 12286#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX 3 12287#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B 0x00b6 12288#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX 3 12289#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_G 0x00b7 12290#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX 3 12291#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G 0x00b8 12292#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX 3 12293#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_R 0x00b9 12294#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX 3 12295#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R 0x00ba 12296#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX 3 12297#define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_B 0x00bb 12298#define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_B_BASE_IDX 3 12299#define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_G 0x00bc 12300#define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX 3 12301#define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_R 0x00bd 12302#define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_R_BASE_IDX 3 12303#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1 0x00be 12304#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX 3 12305#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3 0x00bf 12306#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX 3 12307#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5 0x00c0 12308#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX 3 12309#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7 0x00c1 12310#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX 3 12311#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9 0x00c2 12312#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX 3 12313#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11 0x00c3 12314#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX 3 12315#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13 0x00c4 12316#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX 3 12317#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15 0x00c5 12318#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX 3 12319#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17 0x00c6 12320#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX 3 12321#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19 0x00c7 12322#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX 3 12323#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21 0x00c8 12324#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX 3 12325#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23 0x00c9 12326#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX 3 12327#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25 0x00ca 12328#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX 3 12329#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27 0x00cb 12330#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX 3 12331#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29 0x00cc 12332#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX 3 12333#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31 0x00cd 12334#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX 3 12335#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33 0x00ce 12336#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX 3 12337#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B 0x00cf 12338#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX 3 12339#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G 0x00d0 12340#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX 3 12341#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R 0x00d1 12342#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX 3 12343#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B 0x00d2 12344#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX 3 12345#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G 0x00d3 12346#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX 3 12347#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R 0x00d4 12348#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX 3 12349#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_B 0x00d5 12350#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX 3 12351#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_G 0x00d6 12352#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX 3 12353#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_R 0x00d7 12354#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX 3 12355#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_B 0x00d8 12356#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX 3 12357#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B 0x00d9 12358#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX 3 12359#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_G 0x00da 12360#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX 3 12361#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G 0x00db 12362#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX 3 12363#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_R 0x00dc 12364#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX 3 12365#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R 0x00dd 12366#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX 3 12367#define regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_B 0x00de 12368#define regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_B_BASE_IDX 3 12369#define regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_G 0x00df 12370#define regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_G_BASE_IDX 3 12371#define regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_R 0x00e0 12372#define regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_R_BASE_IDX 3 12373#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1 0x00e1 12374#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX 3 12375#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3 0x00e2 12376#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX 3 12377#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5 0x00e3 12378#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX 3 12379#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7 0x00e4 12380#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX 3 12381#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9 0x00e5 12382#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX 3 12383#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11 0x00e6 12384#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX 3 12385#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13 0x00e7 12386#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX 3 12387#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15 0x00e8 12388#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX 3 12389#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17 0x00e9 12390#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX 3 12391#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19 0x00ea 12392#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX 3 12393#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21 0x00eb 12394#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX 3 12395#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23 0x00ec 12396#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX 3 12397#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25 0x00ed 12398#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX 3 12399#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27 0x00ee 12400#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX 3 12401#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29 0x00ef 12402#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX 3 12403#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31 0x00f0 12404#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX 3 12405#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33 0x00f1 12406#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX 3 12407#define regMPCC_OGAM0_MPCC_GAMUT_REMAP_COEF_FORMAT 0x00f2 12408#define regMPCC_OGAM0_MPCC_GAMUT_REMAP_COEF_FORMAT_BASE_IDX 3 12409#define regMPCC_OGAM0_MPCC_GAMUT_REMAP_MODE 0x00f3 12410#define regMPCC_OGAM0_MPCC_GAMUT_REMAP_MODE_BASE_IDX 3 12411#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A 0x00f4 12412#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A_BASE_IDX 3 12413#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_A 0x00f5 12414#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_A_BASE_IDX 3 12415#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_A 0x00f6 12416#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_A_BASE_IDX 3 12417#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_A 0x00f7 12418#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_A_BASE_IDX 3 12419#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_A 0x00f8 12420#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_A_BASE_IDX 3 12421#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_A 0x00f9 12422#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_A_BASE_IDX 3 12423#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_B 0x00fa 12424#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_B_BASE_IDX 3 12425#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_B 0x00fb 12426#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_B_BASE_IDX 3 12427#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_B 0x00fc 12428#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_B_BASE_IDX 3 12429#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_B 0x00fd 12430#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_B_BASE_IDX 3 12431#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_B 0x00fe 12432#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_B_BASE_IDX 3 12433#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_B 0x00ff 12434#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_B_BASE_IDX 3 12435 12436 12437// addressBlock: dce_dc_mpc_mpcc_ogam1_dispdec 12438// base address: 0x178 12439#define regMPCC_OGAM1_MPCC_OGAM_CONTROL 0x0106 12440#define regMPCC_OGAM1_MPCC_OGAM_CONTROL_BASE_IDX 3 12441#define regMPCC_OGAM1_MPCC_OGAM_LUT_INDEX 0x0107 12442#define regMPCC_OGAM1_MPCC_OGAM_LUT_INDEX_BASE_IDX 3 12443#define regMPCC_OGAM1_MPCC_OGAM_LUT_DATA 0x0108 12444#define regMPCC_OGAM1_MPCC_OGAM_LUT_DATA_BASE_IDX 3 12445#define regMPCC_OGAM1_MPCC_OGAM_LUT_CONTROL 0x0109 12446#define regMPCC_OGAM1_MPCC_OGAM_LUT_CONTROL_BASE_IDX 3 12447#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B 0x010a 12448#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX 3 12449#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G 0x010b 12450#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX 3 12451#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R 0x010c 12452#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX 3 12453#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B 0x010d 12454#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX 3 12455#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G 0x010e 12456#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 3 12457#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R 0x010f 12458#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX 3 12459#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_B 0x0110 12460#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX 3 12461#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_G 0x0111 12462#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX 3 12463#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_R 0x0112 12464#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX 3 12465#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_B 0x0113 12466#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX 3 12467#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B 0x0114 12468#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX 3 12469#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_G 0x0115 12470#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX 3 12471#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G 0x0116 12472#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX 3 12473#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_R 0x0117 12474#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX 3 12475#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R 0x0118 12476#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX 3 12477#define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_B 0x0119 12478#define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_B_BASE_IDX 3 12479#define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_G 0x011a 12480#define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX 3 12481#define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_R 0x011b 12482#define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_R_BASE_IDX 3 12483#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1 0x011c 12484#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX 3 12485#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3 0x011d 12486#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX 3 12487#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5 0x011e 12488#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX 3 12489#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7 0x011f 12490#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX 3 12491#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9 0x0120 12492#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX 3 12493#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11 0x0121 12494#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX 3 12495#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13 0x0122 12496#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX 3 12497#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15 0x0123 12498#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX 3 12499#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17 0x0124 12500#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX 3 12501#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19 0x0125 12502#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX 3 12503#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21 0x0126 12504#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX 3 12505#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23 0x0127 12506#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX 3 12507#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25 0x0128 12508#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX 3 12509#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27 0x0129 12510#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX 3 12511#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29 0x012a 12512#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX 3 12513#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31 0x012b 12514#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX 3 12515#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33 0x012c 12516#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX 3 12517#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B 0x012d 12518#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX 3 12519#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G 0x012e 12520#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX 3 12521#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R 0x012f 12522#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX 3 12523#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B 0x0130 12524#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX 3 12525#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G 0x0131 12526#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX 3 12527#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R 0x0132 12528#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX 3 12529#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_B 0x0133 12530#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX 3 12531#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_G 0x0134 12532#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX 3 12533#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_R 0x0135 12534#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX 3 12535#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_B 0x0136 12536#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX 3 12537#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B 0x0137 12538#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX 3 12539#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_G 0x0138 12540#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX 3 12541#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G 0x0139 12542#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX 3 12543#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_R 0x013a 12544#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX 3 12545#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R 0x013b 12546#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX 3 12547#define regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_B 0x013c 12548#define regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_B_BASE_IDX 3 12549#define regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_G 0x013d 12550#define regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_G_BASE_IDX 3 12551#define regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_R 0x013e 12552#define regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_R_BASE_IDX 3 12553#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1 0x013f 12554#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX 3 12555#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3 0x0140 12556#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX 3 12557#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5 0x0141 12558#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX 3 12559#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7 0x0142 12560#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX 3 12561#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9 0x0143 12562#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX 3 12563#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11 0x0144 12564#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX 3 12565#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13 0x0145 12566#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX 3 12567#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15 0x0146 12568#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX 3 12569#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17 0x0147 12570#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX 3 12571#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19 0x0148 12572#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX 3 12573#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21 0x0149 12574#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX 3 12575#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23 0x014a 12576#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX 3 12577#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25 0x014b 12578#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX 3 12579#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27 0x014c 12580#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX 3 12581#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29 0x014d 12582#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX 3 12583#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31 0x014e 12584#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX 3 12585#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33 0x014f 12586#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX 3 12587#define regMPCC_OGAM1_MPCC_GAMUT_REMAP_COEF_FORMAT 0x0150 12588#define regMPCC_OGAM1_MPCC_GAMUT_REMAP_COEF_FORMAT_BASE_IDX 3 12589#define regMPCC_OGAM1_MPCC_GAMUT_REMAP_MODE 0x0151 12590#define regMPCC_OGAM1_MPCC_GAMUT_REMAP_MODE_BASE_IDX 3 12591#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_A 0x0152 12592#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_A_BASE_IDX 3 12593#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_A 0x0153 12594#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_A_BASE_IDX 3 12595#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_A 0x0154 12596#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_A_BASE_IDX 3 12597#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_A 0x0155 12598#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_A_BASE_IDX 3 12599#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_A 0x0156 12600#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_A_BASE_IDX 3 12601#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_A 0x0157 12602#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_A_BASE_IDX 3 12603#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_B 0x0158 12604#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_B_BASE_IDX 3 12605#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_B 0x0159 12606#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_B_BASE_IDX 3 12607#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_B 0x015a 12608#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_B_BASE_IDX 3 12609#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_B 0x015b 12610#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_B_BASE_IDX 3 12611#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_B 0x015c 12612#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_B_BASE_IDX 3 12613#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_B 0x015d 12614#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_B_BASE_IDX 3 12615 12616 12617// addressBlock: dce_dc_mpc_mpcc_ogam2_dispdec 12618// base address: 0x2f0 12619#define regMPCC_OGAM2_MPCC_OGAM_CONTROL 0x0164 12620#define regMPCC_OGAM2_MPCC_OGAM_CONTROL_BASE_IDX 3 12621#define regMPCC_OGAM2_MPCC_OGAM_LUT_INDEX 0x0165 12622#define regMPCC_OGAM2_MPCC_OGAM_LUT_INDEX_BASE_IDX 3 12623#define regMPCC_OGAM2_MPCC_OGAM_LUT_DATA 0x0166 12624#define regMPCC_OGAM2_MPCC_OGAM_LUT_DATA_BASE_IDX 3 12625#define regMPCC_OGAM2_MPCC_OGAM_LUT_CONTROL 0x0167 12626#define regMPCC_OGAM2_MPCC_OGAM_LUT_CONTROL_BASE_IDX 3 12627#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B 0x0168 12628#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX 3 12629#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G 0x0169 12630#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX 3 12631#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R 0x016a 12632#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX 3 12633#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B 0x016b 12634#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX 3 12635#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G 0x016c 12636#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 3 12637#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R 0x016d 12638#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX 3 12639#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_B 0x016e 12640#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX 3 12641#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_G 0x016f 12642#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX 3 12643#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_R 0x0170 12644#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX 3 12645#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_B 0x0171 12646#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX 3 12647#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B 0x0172 12648#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX 3 12649#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_G 0x0173 12650#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX 3 12651#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G 0x0174 12652#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX 3 12653#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_R 0x0175 12654#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX 3 12655#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R 0x0176 12656#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX 3 12657#define regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_B 0x0177 12658#define regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_B_BASE_IDX 3 12659#define regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_G 0x0178 12660#define regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX 3 12661#define regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_R 0x0179 12662#define regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_R_BASE_IDX 3 12663#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1 0x017a 12664#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX 3 12665#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3 0x017b 12666#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX 3 12667#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5 0x017c 12668#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX 3 12669#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7 0x017d 12670#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX 3 12671#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9 0x017e 12672#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX 3 12673#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11 0x017f 12674#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX 3 12675#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13 0x0180 12676#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX 3 12677#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15 0x0181 12678#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX 3 12679#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17 0x0182 12680#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX 3 12681#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19 0x0183 12682#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX 3 12683#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21 0x0184 12684#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX 3 12685#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23 0x0185 12686#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX 3 12687#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25 0x0186 12688#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX 3 12689#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27 0x0187 12690#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX 3 12691#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29 0x0188 12692#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX 3 12693#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31 0x0189 12694#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX 3 12695#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33 0x018a 12696#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX 3 12697#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B 0x018b 12698#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX 3 12699#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G 0x018c 12700#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX 3 12701#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R 0x018d 12702#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX 3 12703#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B 0x018e 12704#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX 3 12705#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G 0x018f 12706#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX 3 12707#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R 0x0190 12708#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX 3 12709#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_B 0x0191 12710#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX 3 12711#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_G 0x0192 12712#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX 3 12713#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_R 0x0193 12714#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX 3 12715#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_B 0x0194 12716#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX 3 12717#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B 0x0195 12718#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX 3 12719#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_G 0x0196 12720#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX 3 12721#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G 0x0197 12722#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX 3 12723#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_R 0x0198 12724#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX 3 12725#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R 0x0199 12726#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX 3 12727#define regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_B 0x019a 12728#define regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_B_BASE_IDX 3 12729#define regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_G 0x019b 12730#define regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_G_BASE_IDX 3 12731#define regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_R 0x019c 12732#define regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_R_BASE_IDX 3 12733#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1 0x019d 12734#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX 3 12735#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3 0x019e 12736#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX 3 12737#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5 0x019f 12738#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX 3 12739#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7 0x01a0 12740#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX 3 12741#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9 0x01a1 12742#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX 3 12743#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11 0x01a2 12744#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX 3 12745#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13 0x01a3 12746#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX 3 12747#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15 0x01a4 12748#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX 3 12749#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17 0x01a5 12750#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX 3 12751#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19 0x01a6 12752#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX 3 12753#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21 0x01a7 12754#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX 3 12755#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23 0x01a8 12756#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX 3 12757#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25 0x01a9 12758#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX 3 12759#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27 0x01aa 12760#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX 3 12761#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29 0x01ab 12762#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX 3 12763#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31 0x01ac 12764#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX 3 12765#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33 0x01ad 12766#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX 3 12767#define regMPCC_OGAM2_MPCC_GAMUT_REMAP_COEF_FORMAT 0x01ae 12768#define regMPCC_OGAM2_MPCC_GAMUT_REMAP_COEF_FORMAT_BASE_IDX 3 12769#define regMPCC_OGAM2_MPCC_GAMUT_REMAP_MODE 0x01af 12770#define regMPCC_OGAM2_MPCC_GAMUT_REMAP_MODE_BASE_IDX 3 12771#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_A 0x01b0 12772#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_A_BASE_IDX 3 12773#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_A 0x01b1 12774#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_A_BASE_IDX 3 12775#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_A 0x01b2 12776#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_A_BASE_IDX 3 12777#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_A 0x01b3 12778#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_A_BASE_IDX 3 12779#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_A 0x01b4 12780#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_A_BASE_IDX 3 12781#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_A 0x01b5 12782#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_A_BASE_IDX 3 12783#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_B 0x01b6 12784#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_B_BASE_IDX 3 12785#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_B 0x01b7 12786#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_B_BASE_IDX 3 12787#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_B 0x01b8 12788#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_B_BASE_IDX 3 12789#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_B 0x01b9 12790#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_B_BASE_IDX 3 12791#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_B 0x01ba 12792#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_B_BASE_IDX 3 12793#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_B 0x01bb 12794#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_B_BASE_IDX 3 12795 12796 12797// addressBlock: dce_dc_mpc_mpcc_ogam3_dispdec 12798// base address: 0x468 12799#define regMPCC_OGAM3_MPCC_OGAM_CONTROL 0x01c2 12800#define regMPCC_OGAM3_MPCC_OGAM_CONTROL_BASE_IDX 3 12801#define regMPCC_OGAM3_MPCC_OGAM_LUT_INDEX 0x01c3 12802#define regMPCC_OGAM3_MPCC_OGAM_LUT_INDEX_BASE_IDX 3 12803#define regMPCC_OGAM3_MPCC_OGAM_LUT_DATA 0x01c4 12804#define regMPCC_OGAM3_MPCC_OGAM_LUT_DATA_BASE_IDX 3 12805#define regMPCC_OGAM3_MPCC_OGAM_LUT_CONTROL 0x01c5 12806#define regMPCC_OGAM3_MPCC_OGAM_LUT_CONTROL_BASE_IDX 3 12807#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B 0x01c6 12808#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX 3 12809#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G 0x01c7 12810#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX 3 12811#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R 0x01c8 12812#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX 3 12813#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B 0x01c9 12814#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX 3 12815#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G 0x01ca 12816#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 3 12817#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R 0x01cb 12818#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX 3 12819#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_B 0x01cc 12820#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX 3 12821#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_G 0x01cd 12822#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX 3 12823#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_R 0x01ce 12824#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX 3 12825#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_B 0x01cf 12826#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX 3 12827#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B 0x01d0 12828#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX 3 12829#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_G 0x01d1 12830#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX 3 12831#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G 0x01d2 12832#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX 3 12833#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_R 0x01d3 12834#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX 3 12835#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R 0x01d4 12836#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX 3 12837#define regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_B 0x01d5 12838#define regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_B_BASE_IDX 3 12839#define regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_G 0x01d6 12840#define regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX 3 12841#define regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_R 0x01d7 12842#define regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_R_BASE_IDX 3 12843#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1 0x01d8 12844#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX 3 12845#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3 0x01d9 12846#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX 3 12847#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5 0x01da 12848#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX 3 12849#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7 0x01db 12850#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX 3 12851#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9 0x01dc 12852#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX 3 12853#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11 0x01dd 12854#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX 3 12855#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13 0x01de 12856#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX 3 12857#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15 0x01df 12858#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX 3 12859#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17 0x01e0 12860#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX 3 12861#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19 0x01e1 12862#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX 3 12863#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21 0x01e2 12864#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX 3 12865#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23 0x01e3 12866#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX 3 12867#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25 0x01e4 12868#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX 3 12869#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27 0x01e5 12870#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX 3 12871#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29 0x01e6 12872#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX 3 12873#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31 0x01e7 12874#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX 3 12875#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33 0x01e8 12876#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX 3 12877#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B 0x01e9 12878#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX 3 12879#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G 0x01ea 12880#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX 3 12881#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R 0x01eb 12882#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX 3 12883#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B 0x01ec 12884#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX 3 12885#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G 0x01ed 12886#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX 3 12887#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R 0x01ee 12888#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX 3 12889#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_B 0x01ef 12890#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX 3 12891#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_G 0x01f0 12892#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX 3 12893#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_R 0x01f1 12894#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX 3 12895#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_B 0x01f2 12896#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX 3 12897#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B 0x01f3 12898#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX 3 12899#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_G 0x01f4 12900#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX 3 12901#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G 0x01f5 12902#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX 3 12903#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_R 0x01f6 12904#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX 3 12905#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R 0x01f7 12906#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX 3 12907#define regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_B 0x01f8 12908#define regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_B_BASE_IDX 3 12909#define regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_G 0x01f9 12910#define regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_G_BASE_IDX 3 12911#define regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_R 0x01fa 12912#define regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_R_BASE_IDX 3 12913#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1 0x01fb 12914#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX 3 12915#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3 0x01fc 12916#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX 3 12917#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5 0x01fd 12918#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX 3 12919#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7 0x01fe 12920#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX 3 12921#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9 0x01ff 12922#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX 3 12923#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11 0x0200 12924#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX 3 12925#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13 0x0201 12926#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX 3 12927#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15 0x0202 12928#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX 3 12929#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17 0x0203 12930#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX 3 12931#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19 0x0204 12932#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX 3 12933#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21 0x0205 12934#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX 3 12935#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23 0x0206 12936#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX 3 12937#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25 0x0207 12938#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX 3 12939#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27 0x0208 12940#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX 3 12941#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29 0x0209 12942#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX 3 12943#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31 0x020a 12944#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX 3 12945#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33 0x020b 12946#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX 3 12947#define regMPCC_OGAM3_MPCC_GAMUT_REMAP_COEF_FORMAT 0x020c 12948#define regMPCC_OGAM3_MPCC_GAMUT_REMAP_COEF_FORMAT_BASE_IDX 3 12949#define regMPCC_OGAM3_MPCC_GAMUT_REMAP_MODE 0x020d 12950#define regMPCC_OGAM3_MPCC_GAMUT_REMAP_MODE_BASE_IDX 3 12951#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_A 0x020e 12952#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_A_BASE_IDX 3 12953#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_A 0x020f 12954#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_A_BASE_IDX 3 12955#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_A 0x0210 12956#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_A_BASE_IDX 3 12957#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_A 0x0211 12958#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_A_BASE_IDX 3 12959#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_A 0x0212 12960#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_A_BASE_IDX 3 12961#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_A 0x0213 12962#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_A_BASE_IDX 3 12963#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_B 0x0214 12964#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_B_BASE_IDX 3 12965#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_B 0x0215 12966#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_B_BASE_IDX 3 12967#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_B 0x0216 12968#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_B_BASE_IDX 3 12969#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_B 0x0217 12970#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_B_BASE_IDX 3 12971#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_B 0x0218 12972#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_B_BASE_IDX 3 12973#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_B 0x0219 12974#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_B_BASE_IDX 3 12975 12976 12977// addressBlock: dce_dc_mpc_mpc_cfg_dispdec 12978// base address: 0x0 12979#define regMPC_CLOCK_CONTROL 0x0398 12980#define regMPC_CLOCK_CONTROL_BASE_IDX 3 12981#define regMPC_SOFT_RESET 0x0399 12982#define regMPC_SOFT_RESET_BASE_IDX 3 12983#define regMPC_CRC_CTRL 0x039a 12984#define regMPC_CRC_CTRL_BASE_IDX 3 12985#define regMPC_CRC_SEL_CONTROL 0x039b 12986#define regMPC_CRC_SEL_CONTROL_BASE_IDX 3 12987#define regMPC_CRC_RESULT_AR 0x039c 12988#define regMPC_CRC_RESULT_AR_BASE_IDX 3 12989#define regMPC_CRC_RESULT_GB 0x039d 12990#define regMPC_CRC_RESULT_GB_BASE_IDX 3 12991#define regMPC_CRC_RESULT_C 0x039e 12992#define regMPC_CRC_RESULT_C_BASE_IDX 3 12993#define regMPC_PERFMON_EVENT_CTRL 0x03a1 12994#define regMPC_PERFMON_EVENT_CTRL_BASE_IDX 3 12995#define regMPC_BYPASS_BG_AR 0x03a2 12996#define regMPC_BYPASS_BG_AR_BASE_IDX 3 12997#define regMPC_BYPASS_BG_GB 0x03a3 12998#define regMPC_BYPASS_BG_GB_BASE_IDX 3 12999#define regMPC_HOST_READ_CONTROL 0x03a4 13000#define regMPC_HOST_READ_CONTROL_BASE_IDX 3 13001#define regMPC_DPP_PENDING_STATUS 0x03a5 13002#define regMPC_DPP_PENDING_STATUS_BASE_IDX 3 13003#define regMPC_PENDING_STATUS_MISC 0x03a6 13004#define regMPC_PENDING_STATUS_MISC_BASE_IDX 3 13005#define regADR_CFG_CUR_VUPDATE_LOCK_SET0 0x03a7 13006#define regADR_CFG_CUR_VUPDATE_LOCK_SET0_BASE_IDX 3 13007#define regADR_CFG_VUPDATE_LOCK_SET0 0x03a8 13008#define regADR_CFG_VUPDATE_LOCK_SET0_BASE_IDX 3 13009#define regADR_VUPDATE_LOCK_SET0 0x03a9 13010#define regADR_VUPDATE_LOCK_SET0_BASE_IDX 3 13011#define regCFG_VUPDATE_LOCK_SET0 0x03aa 13012#define regCFG_VUPDATE_LOCK_SET0_BASE_IDX 3 13013#define regCUR_VUPDATE_LOCK_SET0 0x03ab 13014#define regCUR_VUPDATE_LOCK_SET0_BASE_IDX 3 13015#define regADR_CFG_CUR_VUPDATE_LOCK_SET1 0x03ac 13016#define regADR_CFG_CUR_VUPDATE_LOCK_SET1_BASE_IDX 3 13017#define regADR_CFG_VUPDATE_LOCK_SET1 0x03ad 13018#define regADR_CFG_VUPDATE_LOCK_SET1_BASE_IDX 3 13019#define regADR_VUPDATE_LOCK_SET1 0x03ae 13020#define regADR_VUPDATE_LOCK_SET1_BASE_IDX 3 13021#define regCFG_VUPDATE_LOCK_SET1 0x03af 13022#define regCFG_VUPDATE_LOCK_SET1_BASE_IDX 3 13023#define regCUR_VUPDATE_LOCK_SET1 0x03b0 13024#define regCUR_VUPDATE_LOCK_SET1_BASE_IDX 3 13025#define regADR_CFG_CUR_VUPDATE_LOCK_SET2 0x03b1 13026#define regADR_CFG_CUR_VUPDATE_LOCK_SET2_BASE_IDX 3 13027#define regADR_CFG_VUPDATE_LOCK_SET2 0x03b2 13028#define regADR_CFG_VUPDATE_LOCK_SET2_BASE_IDX 3 13029#define regADR_VUPDATE_LOCK_SET2 0x03b3 13030#define regADR_VUPDATE_LOCK_SET2_BASE_IDX 3 13031#define regCFG_VUPDATE_LOCK_SET2 0x03b4 13032#define regCFG_VUPDATE_LOCK_SET2_BASE_IDX 3 13033#define regCUR_VUPDATE_LOCK_SET2 0x03b5 13034#define regCUR_VUPDATE_LOCK_SET2_BASE_IDX 3 13035#define regADR_CFG_CUR_VUPDATE_LOCK_SET3 0x03b6 13036#define regADR_CFG_CUR_VUPDATE_LOCK_SET3_BASE_IDX 3 13037#define regADR_CFG_VUPDATE_LOCK_SET3 0x03b7 13038#define regADR_CFG_VUPDATE_LOCK_SET3_BASE_IDX 3 13039#define regADR_VUPDATE_LOCK_SET3 0x03b8 13040#define regADR_VUPDATE_LOCK_SET3_BASE_IDX 3 13041#define regCFG_VUPDATE_LOCK_SET3 0x03b9 13042#define regCFG_VUPDATE_LOCK_SET3_BASE_IDX 3 13043#define regCUR_VUPDATE_LOCK_SET3 0x03ba 13044#define regCUR_VUPDATE_LOCK_SET3_BASE_IDX 3 13045#define regMPC_DWB0_MUX 0x03c6 13046#define regMPC_DWB0_MUX_BASE_IDX 3 13047 13048 13049// addressBlock: dce_dc_mpc_mpc_ocsc_dispdec 13050// base address: 0x0 13051#define regMPC_OUT0_MUX 0x03d8 13052#define regMPC_OUT0_MUX_BASE_IDX 3 13053#define regMPC_OUT0_DENORM_CONTROL 0x03d9 13054#define regMPC_OUT0_DENORM_CONTROL_BASE_IDX 3 13055#define regMPC_OUT0_DENORM_CLAMP_G_Y 0x03da 13056#define regMPC_OUT0_DENORM_CLAMP_G_Y_BASE_IDX 3 13057#define regMPC_OUT0_DENORM_CLAMP_B_CB 0x03db 13058#define regMPC_OUT0_DENORM_CLAMP_B_CB_BASE_IDX 3 13059#define regMPC_OUT1_MUX 0x03dc 13060#define regMPC_OUT1_MUX_BASE_IDX 3 13061#define regMPC_OUT1_DENORM_CONTROL 0x03dd 13062#define regMPC_OUT1_DENORM_CONTROL_BASE_IDX 3 13063#define regMPC_OUT1_DENORM_CLAMP_G_Y 0x03de 13064#define regMPC_OUT1_DENORM_CLAMP_G_Y_BASE_IDX 3 13065#define regMPC_OUT1_DENORM_CLAMP_B_CB 0x03df 13066#define regMPC_OUT1_DENORM_CLAMP_B_CB_BASE_IDX 3 13067#define regMPC_OUT2_MUX 0x03e0 13068#define regMPC_OUT2_MUX_BASE_IDX 3 13069#define regMPC_OUT2_DENORM_CONTROL 0x03e1 13070#define regMPC_OUT2_DENORM_CONTROL_BASE_IDX 3 13071#define regMPC_OUT2_DENORM_CLAMP_G_Y 0x03e2 13072#define regMPC_OUT2_DENORM_CLAMP_G_Y_BASE_IDX 3 13073#define regMPC_OUT2_DENORM_CLAMP_B_CB 0x03e3 13074#define regMPC_OUT2_DENORM_CLAMP_B_CB_BASE_IDX 3 13075#define regMPC_OUT3_MUX 0x03e4 13076#define regMPC_OUT3_MUX_BASE_IDX 3 13077#define regMPC_OUT3_DENORM_CONTROL 0x03e5 13078#define regMPC_OUT3_DENORM_CONTROL_BASE_IDX 3 13079#define regMPC_OUT3_DENORM_CLAMP_G_Y 0x03e6 13080#define regMPC_OUT3_DENORM_CLAMP_G_Y_BASE_IDX 3 13081#define regMPC_OUT3_DENORM_CLAMP_B_CB 0x03e7 13082#define regMPC_OUT3_DENORM_CLAMP_B_CB_BASE_IDX 3 13083#define regMPC_OUT_CSC_COEF_FORMAT 0x03f0 13084#define regMPC_OUT_CSC_COEF_FORMAT_BASE_IDX 3 13085#define regMPC_OUT0_CSC_MODE 0x03f1 13086#define regMPC_OUT0_CSC_MODE_BASE_IDX 3 13087#define regMPC_OUT0_CSC_C11_C12_A 0x03f2 13088#define regMPC_OUT0_CSC_C11_C12_A_BASE_IDX 3 13089#define regMPC_OUT0_CSC_C13_C14_A 0x03f3 13090#define regMPC_OUT0_CSC_C13_C14_A_BASE_IDX 3 13091#define regMPC_OUT0_CSC_C21_C22_A 0x03f4 13092#define regMPC_OUT0_CSC_C21_C22_A_BASE_IDX 3 13093#define regMPC_OUT0_CSC_C23_C24_A 0x03f5 13094#define regMPC_OUT0_CSC_C23_C24_A_BASE_IDX 3 13095#define regMPC_OUT0_CSC_C31_C32_A 0x03f6 13096#define regMPC_OUT0_CSC_C31_C32_A_BASE_IDX 3 13097#define regMPC_OUT0_CSC_C33_C34_A 0x03f7 13098#define regMPC_OUT0_CSC_C33_C34_A_BASE_IDX 3 13099#define regMPC_OUT0_CSC_C11_C12_B 0x03f8 13100#define regMPC_OUT0_CSC_C11_C12_B_BASE_IDX 3 13101#define regMPC_OUT0_CSC_C13_C14_B 0x03f9 13102#define regMPC_OUT0_CSC_C13_C14_B_BASE_IDX 3 13103#define regMPC_OUT0_CSC_C21_C22_B 0x03fa 13104#define regMPC_OUT0_CSC_C21_C22_B_BASE_IDX 3 13105#define regMPC_OUT0_CSC_C23_C24_B 0x03fb 13106#define regMPC_OUT0_CSC_C23_C24_B_BASE_IDX 3 13107#define regMPC_OUT0_CSC_C31_C32_B 0x03fc 13108#define regMPC_OUT0_CSC_C31_C32_B_BASE_IDX 3 13109#define regMPC_OUT0_CSC_C33_C34_B 0x03fd 13110#define regMPC_OUT0_CSC_C33_C34_B_BASE_IDX 3 13111#define regMPC_OUT1_CSC_MODE 0x03fe 13112#define regMPC_OUT1_CSC_MODE_BASE_IDX 3 13113#define regMPC_OUT1_CSC_C11_C12_A 0x03ff 13114#define regMPC_OUT1_CSC_C11_C12_A_BASE_IDX 3 13115#define regMPC_OUT1_CSC_C13_C14_A 0x0400 13116#define regMPC_OUT1_CSC_C13_C14_A_BASE_IDX 3 13117#define regMPC_OUT1_CSC_C21_C22_A 0x0401 13118#define regMPC_OUT1_CSC_C21_C22_A_BASE_IDX 3 13119#define regMPC_OUT1_CSC_C23_C24_A 0x0402 13120#define regMPC_OUT1_CSC_C23_C24_A_BASE_IDX 3 13121#define regMPC_OUT1_CSC_C31_C32_A 0x0403 13122#define regMPC_OUT1_CSC_C31_C32_A_BASE_IDX 3 13123#define regMPC_OUT1_CSC_C33_C34_A 0x0404 13124#define regMPC_OUT1_CSC_C33_C34_A_BASE_IDX 3 13125#define regMPC_OUT1_CSC_C11_C12_B 0x0405 13126#define regMPC_OUT1_CSC_C11_C12_B_BASE_IDX 3 13127#define regMPC_OUT1_CSC_C13_C14_B 0x0406 13128#define regMPC_OUT1_CSC_C13_C14_B_BASE_IDX 3 13129#define regMPC_OUT1_CSC_C21_C22_B 0x0407 13130#define regMPC_OUT1_CSC_C21_C22_B_BASE_IDX 3 13131#define regMPC_OUT1_CSC_C23_C24_B 0x0408 13132#define regMPC_OUT1_CSC_C23_C24_B_BASE_IDX 3 13133#define regMPC_OUT1_CSC_C31_C32_B 0x0409 13134#define regMPC_OUT1_CSC_C31_C32_B_BASE_IDX 3 13135#define regMPC_OUT1_CSC_C33_C34_B 0x040a 13136#define regMPC_OUT1_CSC_C33_C34_B_BASE_IDX 3 13137#define regMPC_OUT2_CSC_MODE 0x040b 13138#define regMPC_OUT2_CSC_MODE_BASE_IDX 3 13139#define regMPC_OUT2_CSC_C11_C12_A 0x040c 13140#define regMPC_OUT2_CSC_C11_C12_A_BASE_IDX 3 13141#define regMPC_OUT2_CSC_C13_C14_A 0x040d 13142#define regMPC_OUT2_CSC_C13_C14_A_BASE_IDX 3 13143#define regMPC_OUT2_CSC_C21_C22_A 0x040e 13144#define regMPC_OUT2_CSC_C21_C22_A_BASE_IDX 3 13145#define regMPC_OUT2_CSC_C23_C24_A 0x040f 13146#define regMPC_OUT2_CSC_C23_C24_A_BASE_IDX 3 13147#define regMPC_OUT2_CSC_C31_C32_A 0x0410 13148#define regMPC_OUT2_CSC_C31_C32_A_BASE_IDX 3 13149#define regMPC_OUT2_CSC_C33_C34_A 0x0411 13150#define regMPC_OUT2_CSC_C33_C34_A_BASE_IDX 3 13151#define regMPC_OUT2_CSC_C11_C12_B 0x0412 13152#define regMPC_OUT2_CSC_C11_C12_B_BASE_IDX 3 13153#define regMPC_OUT2_CSC_C13_C14_B 0x0413 13154#define regMPC_OUT2_CSC_C13_C14_B_BASE_IDX 3 13155#define regMPC_OUT2_CSC_C21_C22_B 0x0414 13156#define regMPC_OUT2_CSC_C21_C22_B_BASE_IDX 3 13157#define regMPC_OUT2_CSC_C23_C24_B 0x0415 13158#define regMPC_OUT2_CSC_C23_C24_B_BASE_IDX 3 13159#define regMPC_OUT2_CSC_C31_C32_B 0x0416 13160#define regMPC_OUT2_CSC_C31_C32_B_BASE_IDX 3 13161#define regMPC_OUT2_CSC_C33_C34_B 0x0417 13162#define regMPC_OUT2_CSC_C33_C34_B_BASE_IDX 3 13163#define regMPC_OUT3_CSC_MODE 0x0418 13164#define regMPC_OUT3_CSC_MODE_BASE_IDX 3 13165#define regMPC_OUT3_CSC_C11_C12_A 0x0419 13166#define regMPC_OUT3_CSC_C11_C12_A_BASE_IDX 3 13167#define regMPC_OUT3_CSC_C13_C14_A 0x041a 13168#define regMPC_OUT3_CSC_C13_C14_A_BASE_IDX 3 13169#define regMPC_OUT3_CSC_C21_C22_A 0x041b 13170#define regMPC_OUT3_CSC_C21_C22_A_BASE_IDX 3 13171#define regMPC_OUT3_CSC_C23_C24_A 0x041c 13172#define regMPC_OUT3_CSC_C23_C24_A_BASE_IDX 3 13173#define regMPC_OUT3_CSC_C31_C32_A 0x041d 13174#define regMPC_OUT3_CSC_C31_C32_A_BASE_IDX 3 13175#define regMPC_OUT3_CSC_C33_C34_A 0x041e 13176#define regMPC_OUT3_CSC_C33_C34_A_BASE_IDX 3 13177#define regMPC_OUT3_CSC_C11_C12_B 0x041f 13178#define regMPC_OUT3_CSC_C11_C12_B_BASE_IDX 3 13179#define regMPC_OUT3_CSC_C13_C14_B 0x0420 13180#define regMPC_OUT3_CSC_C13_C14_B_BASE_IDX 3 13181#define regMPC_OUT3_CSC_C21_C22_B 0x0421 13182#define regMPC_OUT3_CSC_C21_C22_B_BASE_IDX 3 13183#define regMPC_OUT3_CSC_C23_C24_B 0x0422 13184#define regMPC_OUT3_CSC_C23_C24_B_BASE_IDX 3 13185#define regMPC_OUT3_CSC_C31_C32_B 0x0423 13186#define regMPC_OUT3_CSC_C31_C32_B_BASE_IDX 3 13187#define regMPC_OUT3_CSC_C33_C34_B 0x0424 13188#define regMPC_OUT3_CSC_C33_C34_B_BASE_IDX 3 13189 13190 13191// addressBlock: dce_dc_mpc_mpc_dcperfmon_dc_perfmon_dispdec 13192// base address: 0x17e1c 13193#define regDC_PERFMON15_PERFCOUNTER_CNTL 0x0447 13194#define regDC_PERFMON15_PERFCOUNTER_CNTL_BASE_IDX 3 13195#define regDC_PERFMON15_PERFCOUNTER_CNTL2 0x0448 13196#define regDC_PERFMON15_PERFCOUNTER_CNTL2_BASE_IDX 3 13197#define regDC_PERFMON15_PERFCOUNTER_STATE 0x0449 13198#define regDC_PERFMON15_PERFCOUNTER_STATE_BASE_IDX 3 13199#define regDC_PERFMON15_PERFMON_CNTL 0x044a 13200#define regDC_PERFMON15_PERFMON_CNTL_BASE_IDX 3 13201#define regDC_PERFMON15_PERFMON_CNTL2 0x044b 13202#define regDC_PERFMON15_PERFMON_CNTL2_BASE_IDX 3 13203#define regDC_PERFMON15_PERFMON_CVALUE_INT_MISC 0x044c 13204#define regDC_PERFMON15_PERFMON_CVALUE_INT_MISC_BASE_IDX 3 13205#define regDC_PERFMON15_PERFMON_CVALUE_LOW 0x044d 13206#define regDC_PERFMON15_PERFMON_CVALUE_LOW_BASE_IDX 3 13207#define regDC_PERFMON15_PERFMON_HI 0x044e 13208#define regDC_PERFMON15_PERFMON_HI_BASE_IDX 3 13209#define regDC_PERFMON15_PERFMON_LOW 0x044f 13210#define regDC_PERFMON15_PERFMON_LOW_BASE_IDX 3 13211 13212 13213// addressBlock: dce_dc_hpo_hdmi_stream_enc0_afmt_afmt_dispdec 13214// base address: 0x2646c 13215#define regAFMT5_AFMT_ACP 0x091b 13216#define regAFMT5_AFMT_ACP_BASE_IDX 3 13217#define regAFMT5_AFMT_VBI_PACKET_CONTROL 0x091c 13218#define regAFMT5_AFMT_VBI_PACKET_CONTROL_BASE_IDX 3 13219#define regAFMT5_AFMT_AUDIO_PACKET_CONTROL2 0x091d 13220#define regAFMT5_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 3 13221#define regAFMT5_AFMT_AUDIO_INFO0 0x091e 13222#define regAFMT5_AFMT_AUDIO_INFO0_BASE_IDX 3 13223#define regAFMT5_AFMT_AUDIO_INFO1 0x091f 13224#define regAFMT5_AFMT_AUDIO_INFO1_BASE_IDX 3 13225#define regAFMT5_AFMT_60958_0 0x0920 13226#define regAFMT5_AFMT_60958_0_BASE_IDX 3 13227#define regAFMT5_AFMT_60958_1 0x0921 13228#define regAFMT5_AFMT_60958_1_BASE_IDX 3 13229#define regAFMT5_AFMT_AUDIO_CRC_CONTROL 0x0922 13230#define regAFMT5_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 3 13231#define regAFMT5_AFMT_RAMP_CONTROL0 0x0923 13232#define regAFMT5_AFMT_RAMP_CONTROL0_BASE_IDX 3 13233#define regAFMT5_AFMT_RAMP_CONTROL1 0x0924 13234#define regAFMT5_AFMT_RAMP_CONTROL1_BASE_IDX 3 13235#define regAFMT5_AFMT_RAMP_CONTROL2 0x0925 13236#define regAFMT5_AFMT_RAMP_CONTROL2_BASE_IDX 3 13237#define regAFMT5_AFMT_RAMP_CONTROL3 0x0926 13238#define regAFMT5_AFMT_RAMP_CONTROL3_BASE_IDX 3 13239#define regAFMT5_AFMT_60958_2 0x0927 13240#define regAFMT5_AFMT_60958_2_BASE_IDX 3 13241#define regAFMT5_AFMT_AUDIO_CRC_RESULT 0x0928 13242#define regAFMT5_AFMT_AUDIO_CRC_RESULT_BASE_IDX 3 13243#define regAFMT5_AFMT_STATUS 0x0929 13244#define regAFMT5_AFMT_STATUS_BASE_IDX 3 13245#define regAFMT5_AFMT_AUDIO_PACKET_CONTROL 0x092a 13246#define regAFMT5_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 3 13247#define regAFMT5_AFMT_INFOFRAME_CONTROL0 0x092b 13248#define regAFMT5_AFMT_INFOFRAME_CONTROL0_BASE_IDX 3 13249#define regAFMT5_AFMT_INTERRUPT_STATUS 0x092c 13250#define regAFMT5_AFMT_INTERRUPT_STATUS_BASE_IDX 3 13251#define regAFMT5_AFMT_AUDIO_SRC_CONTROL 0x092d 13252#define regAFMT5_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 3 13253#define regAFMT5_AFMT_MEM_PWR 0x092f 13254#define regAFMT5_AFMT_MEM_PWR_BASE_IDX 3 13255 13256 13257// addressBlock: dce_dc_hpo_hdmi_stream_enc0_vpg_vpg_dispdec 13258// base address: 0x264c4 13259#define regVPG5_VPG_GENERIC_PACKET_ACCESS_CTRL 0x0931 13260#define regVPG5_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 3 13261#define regVPG5_VPG_GENERIC_PACKET_DATA 0x0932 13262#define regVPG5_VPG_GENERIC_PACKET_DATA_BASE_IDX 3 13263#define regVPG5_VPG_GSP_FRAME_UPDATE_CTRL 0x0933 13264#define regVPG5_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 3 13265#define regVPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x0934 13266#define regVPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 3 13267#define regVPG5_VPG_GENERIC_STATUS 0x0935 13268#define regVPG5_VPG_GENERIC_STATUS_BASE_IDX 3 13269#define regVPG5_VPG_MEM_PWR 0x0936 13270#define regVPG5_VPG_MEM_PWR_BASE_IDX 3 13271#define regVPG5_VPG_ISRC1_2_ACCESS_CTRL 0x0937 13272#define regVPG5_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 3 13273#define regVPG5_VPG_ISRC1_2_DATA 0x0938 13274#define regVPG5_VPG_ISRC1_2_DATA_BASE_IDX 3 13275#define regVPG5_VPG_MPEG_INFO0 0x0939 13276#define regVPG5_VPG_MPEG_INFO0_BASE_IDX 3 13277#define regVPG5_VPG_MPEG_INFO1 0x093a 13278#define regVPG5_VPG_MPEG_INFO1_BASE_IDX 3 13279 13280 13281// addressBlock: dce_dc_hpo_hdmi_stream_enc0_dme_dme_dispdec 13282// base address: 0x264f0 13283#define regDME5_DME_CONTROL 0x093c 13284#define regDME5_DME_CONTROL_BASE_IDX 3 13285#define regDME5_DME_MEMORY_CONTROL 0x093d 13286#define regDME5_DME_MEMORY_CONTROL_BASE_IDX 3 13287 13288 13289// addressBlock: dce_dc_hpo_hpo_top_dispdec 13290// base address: 0x2790c 13291#define regHPO_TOP_CLOCK_CONTROL 0x0e43 13292#define regHPO_TOP_CLOCK_CONTROL_BASE_IDX 3 13293#define regHPO_TOP_HW_CONTROL 0x0e4a 13294#define regHPO_TOP_HW_CONTROL_BASE_IDX 3 13295 13296 13297// addressBlock: dce_dc_hpo_dp_stream_mapper_dispdec 13298// base address: 0x27958 13299#define regDP_STREAM_MAPPER_CONTROL0 0x0e56 13300#define regDP_STREAM_MAPPER_CONTROL0_BASE_IDX 3 13301#define regDP_STREAM_MAPPER_CONTROL1 0x0e57 13302#define regDP_STREAM_MAPPER_CONTROL1_BASE_IDX 3 13303#define regDP_STREAM_MAPPER_CONTROL2 0x0e58 13304#define regDP_STREAM_MAPPER_CONTROL2_BASE_IDX 3 13305#define regDP_STREAM_MAPPER_CONTROL3 0x0e59 13306#define regDP_STREAM_MAPPER_CONTROL3_BASE_IDX 3 13307 13308 13309// addressBlock: dce_dc_hpo_hpo_dcperfmon_dc_perfmon_dispdec 13310// base address: 0x1a698 13311#define regDC_PERFMON23_PERFCOUNTER_CNTL 0x0e66 13312#define regDC_PERFMON23_PERFCOUNTER_CNTL_BASE_IDX 3 13313#define regDC_PERFMON23_PERFCOUNTER_CNTL2 0x0e67 13314#define regDC_PERFMON23_PERFCOUNTER_CNTL2_BASE_IDX 3 13315#define regDC_PERFMON23_PERFCOUNTER_STATE 0x0e68 13316#define regDC_PERFMON23_PERFCOUNTER_STATE_BASE_IDX 3 13317#define regDC_PERFMON23_PERFMON_CNTL 0x0e69 13318#define regDC_PERFMON23_PERFMON_CNTL_BASE_IDX 3 13319#define regDC_PERFMON23_PERFMON_CNTL2 0x0e6a 13320#define regDC_PERFMON23_PERFMON_CNTL2_BASE_IDX 3 13321#define regDC_PERFMON23_PERFMON_CVALUE_INT_MISC 0x0e6b 13322#define regDC_PERFMON23_PERFMON_CVALUE_INT_MISC_BASE_IDX 3 13323#define regDC_PERFMON23_PERFMON_CVALUE_LOW 0x0e6c 13324#define regDC_PERFMON23_PERFMON_CVALUE_LOW_BASE_IDX 3 13325#define regDC_PERFMON23_PERFMON_HI 0x0e6d 13326#define regDC_PERFMON23_PERFMON_HI_BASE_IDX 3 13327#define regDC_PERFMON23_PERFMON_LOW 0x0e6e 13328#define regDC_PERFMON23_PERFMON_LOW_BASE_IDX 3 13329 13330 13331 13332// addressBlock: dce_dc_opp_abm0_dispdec 13333// base address: 0x0 13334#define regABM0_BL1_PWM_AMBIENT_LIGHT_LEVEL 0x0e7a 13335#define regABM0_BL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX 3 13336#define regABM0_BL1_PWM_USER_LEVEL 0x0e7b 13337#define regABM0_BL1_PWM_USER_LEVEL_BASE_IDX 3 13338#define regABM0_BL1_PWM_TARGET_ABM_LEVEL 0x0e7c 13339#define regABM0_BL1_PWM_TARGET_ABM_LEVEL_BASE_IDX 3 13340#define regABM0_BL1_PWM_CURRENT_ABM_LEVEL 0x0e7d 13341#define regABM0_BL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX 3 13342#define regABM0_BL1_PWM_FINAL_DUTY_CYCLE 0x0e7e 13343#define regABM0_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX 3 13344#define regABM0_BL1_PWM_MINIMUM_DUTY_CYCLE 0x0e7f 13345#define regABM0_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX 3 13346#define regABM0_BL1_PWM_ABM_CNTL 0x0e80 13347#define regABM0_BL1_PWM_ABM_CNTL_BASE_IDX 3 13348#define regABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE 0x0e81 13349#define regABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX 3 13350#define regABM0_BL1_PWM_GRP2_REG_LOCK 0x0e82 13351#define regABM0_BL1_PWM_GRP2_REG_LOCK_BASE_IDX 3 13352#define regABM0_DC_ABM1_CNTL 0x0e83 13353#define regABM0_DC_ABM1_CNTL_BASE_IDX 3 13354#define regABM0_DC_ABM1_IPCSC_COEFF_SEL 0x0e84 13355#define regABM0_DC_ABM1_IPCSC_COEFF_SEL_BASE_IDX 3 13356#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_0 0x0e85 13357#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_0_BASE_IDX 3 13358#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_1 0x0e86 13359#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_1_BASE_IDX 3 13360#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_2 0x0e87 13361#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_2_BASE_IDX 3 13362#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_3 0x0e88 13363#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_3_BASE_IDX 3 13364#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_4 0x0e89 13365#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_4_BASE_IDX 3 13366#define regABM0_DC_ABM1_ACE_THRES_12 0x0e8a 13367#define regABM0_DC_ABM1_ACE_THRES_12_BASE_IDX 3 13368#define regABM0_DC_ABM1_ACE_THRES_34 0x0e8b 13369#define regABM0_DC_ABM1_ACE_THRES_34_BASE_IDX 3 13370#define regABM0_DC_ABM1_ACE_CNTL_MISC 0x0e8c 13371#define regABM0_DC_ABM1_ACE_CNTL_MISC_BASE_IDX 3 13372#define regABM0_DC_ABM1_HGLS_REG_READ_PROGRESS 0x0e8e 13373#define regABM0_DC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX 3 13374#define regABM0_DC_ABM1_HG_MISC_CTRL 0x0e8f 13375#define regABM0_DC_ABM1_HG_MISC_CTRL_BASE_IDX 3 13376#define regABM0_DC_ABM1_LS_SUM_OF_LUMA 0x0e90 13377#define regABM0_DC_ABM1_LS_SUM_OF_LUMA_BASE_IDX 3 13378#define regABM0_DC_ABM1_LS_MIN_MAX_LUMA 0x0e91 13379#define regABM0_DC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX 3 13380#define regABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA 0x0e92 13381#define regABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX 3 13382#define regABM0_DC_ABM1_LS_PIXEL_COUNT 0x0e93 13383#define regABM0_DC_ABM1_LS_PIXEL_COUNT_BASE_IDX 3 13384#define regABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES 0x0e94 13385#define regABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX 3 13386#define regABM0_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT 0x0e95 13387#define regABM0_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX 3 13388#define regABM0_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT 0x0e96 13389#define regABM0_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX 3 13390#define regABM0_DC_ABM1_HG_SAMPLE_RATE 0x0e97 13391#define regABM0_DC_ABM1_HG_SAMPLE_RATE_BASE_IDX 3 13392#define regABM0_DC_ABM1_LS_SAMPLE_RATE 0x0e98 13393#define regABM0_DC_ABM1_LS_SAMPLE_RATE_BASE_IDX 3 13394#define regABM0_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG 0x0e99 13395#define regABM0_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX 3 13396#define regABM0_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX 0x0e9a 13397#define regABM0_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX 3 13398#define regABM0_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX 0x0e9b 13399#define regABM0_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX 3 13400#define regABM0_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX 0x0e9c 13401#define regABM0_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX 3 13402#define regABM0_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX 0x0e9d 13403#define regABM0_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX 3 13404#define regABM0_DC_ABM1_HG_RESULT_1 0x0e9e 13405#define regABM0_DC_ABM1_HG_RESULT_1_BASE_IDX 3 13406#define regABM0_DC_ABM1_HG_RESULT_2 0x0e9f 13407#define regABM0_DC_ABM1_HG_RESULT_2_BASE_IDX 3 13408#define regABM0_DC_ABM1_HG_RESULT_3 0x0ea0 13409#define regABM0_DC_ABM1_HG_RESULT_3_BASE_IDX 3 13410#define regABM0_DC_ABM1_HG_RESULT_4 0x0ea1 13411#define regABM0_DC_ABM1_HG_RESULT_4_BASE_IDX 3 13412#define regABM0_DC_ABM1_HG_RESULT_5 0x0ea2 13413#define regABM0_DC_ABM1_HG_RESULT_5_BASE_IDX 3 13414#define regABM0_DC_ABM1_HG_RESULT_6 0x0ea3 13415#define regABM0_DC_ABM1_HG_RESULT_6_BASE_IDX 3 13416#define regABM0_DC_ABM1_HG_RESULT_7 0x0ea4 13417#define regABM0_DC_ABM1_HG_RESULT_7_BASE_IDX 3 13418#define regABM0_DC_ABM1_HG_RESULT_8 0x0ea5 13419#define regABM0_DC_ABM1_HG_RESULT_8_BASE_IDX 3 13420#define regABM0_DC_ABM1_HG_RESULT_9 0x0ea6 13421#define regABM0_DC_ABM1_HG_RESULT_9_BASE_IDX 3 13422#define regABM0_DC_ABM1_HG_RESULT_10 0x0ea7 13423#define regABM0_DC_ABM1_HG_RESULT_10_BASE_IDX 3 13424#define regABM0_DC_ABM1_HG_RESULT_11 0x0ea8 13425#define regABM0_DC_ABM1_HG_RESULT_11_BASE_IDX 3 13426#define regABM0_DC_ABM1_HG_RESULT_12 0x0ea9 13427#define regABM0_DC_ABM1_HG_RESULT_12_BASE_IDX 3 13428#define regABM0_DC_ABM1_HG_RESULT_13 0x0eaa 13429#define regABM0_DC_ABM1_HG_RESULT_13_BASE_IDX 3 13430#define regABM0_DC_ABM1_HG_RESULT_14 0x0eab 13431#define regABM0_DC_ABM1_HG_RESULT_14_BASE_IDX 3 13432#define regABM0_DC_ABM1_HG_RESULT_15 0x0eac 13433#define regABM0_DC_ABM1_HG_RESULT_15_BASE_IDX 3 13434#define regABM0_DC_ABM1_HG_RESULT_16 0x0ead 13435#define regABM0_DC_ABM1_HG_RESULT_16_BASE_IDX 3 13436#define regABM0_DC_ABM1_HG_RESULT_17 0x0eae 13437#define regABM0_DC_ABM1_HG_RESULT_17_BASE_IDX 3 13438#define regABM0_DC_ABM1_HG_RESULT_18 0x0eaf 13439#define regABM0_DC_ABM1_HG_RESULT_18_BASE_IDX 3 13440#define regABM0_DC_ABM1_HG_RESULT_19 0x0eb0 13441#define regABM0_DC_ABM1_HG_RESULT_19_BASE_IDX 3 13442#define regABM0_DC_ABM1_HG_RESULT_20 0x0eb1 13443#define regABM0_DC_ABM1_HG_RESULT_20_BASE_IDX 3 13444#define regABM0_DC_ABM1_HG_RESULT_21 0x0eb2 13445#define regABM0_DC_ABM1_HG_RESULT_21_BASE_IDX 3 13446#define regABM0_DC_ABM1_HG_RESULT_22 0x0eb3 13447#define regABM0_DC_ABM1_HG_RESULT_22_BASE_IDX 3 13448#define regABM0_DC_ABM1_HG_RESULT_23 0x0eb4 13449#define regABM0_DC_ABM1_HG_RESULT_23_BASE_IDX 3 13450#define regABM0_DC_ABM1_HG_RESULT_24 0x0eb5 13451#define regABM0_DC_ABM1_HG_RESULT_24_BASE_IDX 3 13452#define regABM0_DC_ABM1_BL_MASTER_LOCK 0x0eb6 13453#define regABM0_DC_ABM1_BL_MASTER_LOCK_BASE_IDX 3 13454 13455 13456// addressBlock: dce_dc_opp_abm1_dispdec 13457// base address: 0x104 13458#define regABM1_BL1_PWM_AMBIENT_LIGHT_LEVEL 0x0ebb 13459#define regABM1_BL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX 3 13460#define regABM1_BL1_PWM_USER_LEVEL 0x0ebc 13461#define regABM1_BL1_PWM_USER_LEVEL_BASE_IDX 3 13462#define regABM1_BL1_PWM_TARGET_ABM_LEVEL 0x0ebd 13463#define regABM1_BL1_PWM_TARGET_ABM_LEVEL_BASE_IDX 3 13464#define regABM1_BL1_PWM_CURRENT_ABM_LEVEL 0x0ebe 13465#define regABM1_BL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX 3 13466#define regABM1_BL1_PWM_FINAL_DUTY_CYCLE 0x0ebf 13467#define regABM1_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX 3 13468#define regABM1_BL1_PWM_MINIMUM_DUTY_CYCLE 0x0ec0 13469#define regABM1_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX 3 13470#define regABM1_BL1_PWM_ABM_CNTL 0x0ec1 13471#define regABM1_BL1_PWM_ABM_CNTL_BASE_IDX 3 13472#define regABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE 0x0ec2 13473#define regABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX 3 13474#define regABM1_BL1_PWM_GRP2_REG_LOCK 0x0ec3 13475#define regABM1_BL1_PWM_GRP2_REG_LOCK_BASE_IDX 3 13476#define regABM1_DC_ABM1_CNTL 0x0ec4 13477#define regABM1_DC_ABM1_CNTL_BASE_IDX 3 13478#define regABM1_DC_ABM1_IPCSC_COEFF_SEL 0x0ec5 13479#define regABM1_DC_ABM1_IPCSC_COEFF_SEL_BASE_IDX 3 13480#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_0 0x0ec6 13481#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_0_BASE_IDX 3 13482#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_1 0x0ec7 13483#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_1_BASE_IDX 3 13484#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_2 0x0ec8 13485#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_2_BASE_IDX 3 13486#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_3 0x0ec9 13487#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_3_BASE_IDX 3 13488#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_4 0x0eca 13489#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_4_BASE_IDX 3 13490#define regABM1_DC_ABM1_ACE_THRES_12 0x0ecb 13491#define regABM1_DC_ABM1_ACE_THRES_12_BASE_IDX 3 13492#define regABM1_DC_ABM1_ACE_THRES_34 0x0ecc 13493#define regABM1_DC_ABM1_ACE_THRES_34_BASE_IDX 3 13494#define regABM1_DC_ABM1_ACE_CNTL_MISC 0x0ecd 13495#define regABM1_DC_ABM1_ACE_CNTL_MISC_BASE_IDX 3 13496#define regABM1_DC_ABM1_HGLS_REG_READ_PROGRESS 0x0ecf 13497#define regABM1_DC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX 3 13498#define regABM1_DC_ABM1_HG_MISC_CTRL 0x0ed0 13499#define regABM1_DC_ABM1_HG_MISC_CTRL_BASE_IDX 3 13500#define regABM1_DC_ABM1_LS_SUM_OF_LUMA 0x0ed1 13501#define regABM1_DC_ABM1_LS_SUM_OF_LUMA_BASE_IDX 3 13502#define regABM1_DC_ABM1_LS_MIN_MAX_LUMA 0x0ed2 13503#define regABM1_DC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX 3 13504#define regABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA 0x0ed3 13505#define regABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX 3 13506#define regABM1_DC_ABM1_LS_PIXEL_COUNT 0x0ed4 13507#define regABM1_DC_ABM1_LS_PIXEL_COUNT_BASE_IDX 3 13508#define regABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES 0x0ed5 13509#define regABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX 3 13510#define regABM1_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT 0x0ed6 13511#define regABM1_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX 3 13512#define regABM1_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT 0x0ed7 13513#define regABM1_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX 3 13514#define regABM1_DC_ABM1_HG_SAMPLE_RATE 0x0ed8 13515#define regABM1_DC_ABM1_HG_SAMPLE_RATE_BASE_IDX 3 13516#define regABM1_DC_ABM1_LS_SAMPLE_RATE 0x0ed9 13517#define regABM1_DC_ABM1_LS_SAMPLE_RATE_BASE_IDX 3 13518#define regABM1_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG 0x0eda 13519#define regABM1_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX 3 13520#define regABM1_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX 0x0edb 13521#define regABM1_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX 3 13522#define regABM1_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX 0x0edc 13523#define regABM1_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX 3 13524#define regABM1_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX 0x0edd 13525#define regABM1_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX 3 13526#define regABM1_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX 0x0ede 13527#define regABM1_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX 3 13528#define regABM1_DC_ABM1_HG_RESULT_1 0x0edf 13529#define regABM1_DC_ABM1_HG_RESULT_1_BASE_IDX 3 13530#define regABM1_DC_ABM1_HG_RESULT_2 0x0ee0 13531#define regABM1_DC_ABM1_HG_RESULT_2_BASE_IDX 3 13532#define regABM1_DC_ABM1_HG_RESULT_3 0x0ee1 13533#define regABM1_DC_ABM1_HG_RESULT_3_BASE_IDX 3 13534#define regABM1_DC_ABM1_HG_RESULT_4 0x0ee2 13535#define regABM1_DC_ABM1_HG_RESULT_4_BASE_IDX 3 13536#define regABM1_DC_ABM1_HG_RESULT_5 0x0ee3 13537#define regABM1_DC_ABM1_HG_RESULT_5_BASE_IDX 3 13538#define regABM1_DC_ABM1_HG_RESULT_6 0x0ee4 13539#define regABM1_DC_ABM1_HG_RESULT_6_BASE_IDX 3 13540#define regABM1_DC_ABM1_HG_RESULT_7 0x0ee5 13541#define regABM1_DC_ABM1_HG_RESULT_7_BASE_IDX 3 13542#define regABM1_DC_ABM1_HG_RESULT_8 0x0ee6 13543#define regABM1_DC_ABM1_HG_RESULT_8_BASE_IDX 3 13544#define regABM1_DC_ABM1_HG_RESULT_9 0x0ee7 13545#define regABM1_DC_ABM1_HG_RESULT_9_BASE_IDX 3 13546#define regABM1_DC_ABM1_HG_RESULT_10 0x0ee8 13547#define regABM1_DC_ABM1_HG_RESULT_10_BASE_IDX 3 13548#define regABM1_DC_ABM1_HG_RESULT_11 0x0ee9 13549#define regABM1_DC_ABM1_HG_RESULT_11_BASE_IDX 3 13550#define regABM1_DC_ABM1_HG_RESULT_12 0x0eea 13551#define regABM1_DC_ABM1_HG_RESULT_12_BASE_IDX 3 13552#define regABM1_DC_ABM1_HG_RESULT_13 0x0eeb 13553#define regABM1_DC_ABM1_HG_RESULT_13_BASE_IDX 3 13554#define regABM1_DC_ABM1_HG_RESULT_14 0x0eec 13555#define regABM1_DC_ABM1_HG_RESULT_14_BASE_IDX 3 13556#define regABM1_DC_ABM1_HG_RESULT_15 0x0eed 13557#define regABM1_DC_ABM1_HG_RESULT_15_BASE_IDX 3 13558#define regABM1_DC_ABM1_HG_RESULT_16 0x0eee 13559#define regABM1_DC_ABM1_HG_RESULT_16_BASE_IDX 3 13560#define regABM1_DC_ABM1_HG_RESULT_17 0x0eef 13561#define regABM1_DC_ABM1_HG_RESULT_17_BASE_IDX 3 13562#define regABM1_DC_ABM1_HG_RESULT_18 0x0ef0 13563#define regABM1_DC_ABM1_HG_RESULT_18_BASE_IDX 3 13564#define regABM1_DC_ABM1_HG_RESULT_19 0x0ef1 13565#define regABM1_DC_ABM1_HG_RESULT_19_BASE_IDX 3 13566#define regABM1_DC_ABM1_HG_RESULT_20 0x0ef2 13567#define regABM1_DC_ABM1_HG_RESULT_20_BASE_IDX 3 13568#define regABM1_DC_ABM1_HG_RESULT_21 0x0ef3 13569#define regABM1_DC_ABM1_HG_RESULT_21_BASE_IDX 3 13570#define regABM1_DC_ABM1_HG_RESULT_22 0x0ef4 13571#define regABM1_DC_ABM1_HG_RESULT_22_BASE_IDX 3 13572#define regABM1_DC_ABM1_HG_RESULT_23 0x0ef5 13573#define regABM1_DC_ABM1_HG_RESULT_23_BASE_IDX 3 13574#define regABM1_DC_ABM1_HG_RESULT_24 0x0ef6 13575#define regABM1_DC_ABM1_HG_RESULT_24_BASE_IDX 3 13576#define regABM1_DC_ABM1_BL_MASTER_LOCK 0x0ef7 13577#define regABM1_DC_ABM1_BL_MASTER_LOCK_BASE_IDX 3 13578 13579 13580// addressBlock: dce_dc_opp_abm2_dispdec 13581// base address: 0x208 13582#define regABM2_BL1_PWM_AMBIENT_LIGHT_LEVEL 0x0efc 13583#define regABM2_BL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX 3 13584#define regABM2_BL1_PWM_USER_LEVEL 0x0efd 13585#define regABM2_BL1_PWM_USER_LEVEL_BASE_IDX 3 13586#define regABM2_BL1_PWM_TARGET_ABM_LEVEL 0x0efe 13587#define regABM2_BL1_PWM_TARGET_ABM_LEVEL_BASE_IDX 3 13588#define regABM2_BL1_PWM_CURRENT_ABM_LEVEL 0x0eff 13589#define regABM2_BL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX 3 13590#define regABM2_BL1_PWM_FINAL_DUTY_CYCLE 0x0f00 13591#define regABM2_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX 3 13592#define regABM2_BL1_PWM_MINIMUM_DUTY_CYCLE 0x0f01 13593#define regABM2_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX 3 13594#define regABM2_BL1_PWM_ABM_CNTL 0x0f02 13595#define regABM2_BL1_PWM_ABM_CNTL_BASE_IDX 3 13596#define regABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE 0x0f03 13597#define regABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX 3 13598#define regABM2_BL1_PWM_GRP2_REG_LOCK 0x0f04 13599#define regABM2_BL1_PWM_GRP2_REG_LOCK_BASE_IDX 3 13600#define regABM2_DC_ABM1_CNTL 0x0f05 13601#define regABM2_DC_ABM1_CNTL_BASE_IDX 3 13602#define regABM2_DC_ABM1_IPCSC_COEFF_SEL 0x0f06 13603#define regABM2_DC_ABM1_IPCSC_COEFF_SEL_BASE_IDX 3 13604#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_0 0x0f07 13605#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_0_BASE_IDX 3 13606#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_1 0x0f08 13607#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_1_BASE_IDX 3 13608#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_2 0x0f09 13609#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_2_BASE_IDX 3 13610#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_3 0x0f0a 13611#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_3_BASE_IDX 3 13612#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_4 0x0f0b 13613#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_4_BASE_IDX 3 13614#define regABM2_DC_ABM1_ACE_THRES_12 0x0f0c 13615#define regABM2_DC_ABM1_ACE_THRES_12_BASE_IDX 3 13616#define regABM2_DC_ABM1_ACE_THRES_34 0x0f0d 13617#define regABM2_DC_ABM1_ACE_THRES_34_BASE_IDX 3 13618#define regABM2_DC_ABM1_ACE_CNTL_MISC 0x0f0e 13619#define regABM2_DC_ABM1_ACE_CNTL_MISC_BASE_IDX 3 13620#define regABM2_DC_ABM1_HGLS_REG_READ_PROGRESS 0x0f10 13621#define regABM2_DC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX 3 13622#define regABM2_DC_ABM1_HG_MISC_CTRL 0x0f11 13623#define regABM2_DC_ABM1_HG_MISC_CTRL_BASE_IDX 3 13624#define regABM2_DC_ABM1_LS_SUM_OF_LUMA 0x0f12 13625#define regABM2_DC_ABM1_LS_SUM_OF_LUMA_BASE_IDX 3 13626#define regABM2_DC_ABM1_LS_MIN_MAX_LUMA 0x0f13 13627#define regABM2_DC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX 3 13628#define regABM2_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA 0x0f14 13629#define regABM2_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX 3 13630#define regABM2_DC_ABM1_LS_PIXEL_COUNT 0x0f15 13631#define regABM2_DC_ABM1_LS_PIXEL_COUNT_BASE_IDX 3 13632#define regABM2_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES 0x0f16 13633#define regABM2_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX 3 13634#define regABM2_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT 0x0f17 13635#define regABM2_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX 3 13636#define regABM2_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT 0x0f18 13637#define regABM2_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX 3 13638#define regABM2_DC_ABM1_HG_SAMPLE_RATE 0x0f19 13639#define regABM2_DC_ABM1_HG_SAMPLE_RATE_BASE_IDX 3 13640#define regABM2_DC_ABM1_LS_SAMPLE_RATE 0x0f1a 13641#define regABM2_DC_ABM1_LS_SAMPLE_RATE_BASE_IDX 3 13642#define regABM2_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG 0x0f1b 13643#define regABM2_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX 3 13644#define regABM2_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX 0x0f1c 13645#define regABM2_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX 3 13646#define regABM2_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX 0x0f1d 13647#define regABM2_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX 3 13648#define regABM2_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX 0x0f1e 13649#define regABM2_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX 3 13650#define regABM2_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX 0x0f1f 13651#define regABM2_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX 3 13652#define regABM2_DC_ABM1_HG_RESULT_1 0x0f20 13653#define regABM2_DC_ABM1_HG_RESULT_1_BASE_IDX 3 13654#define regABM2_DC_ABM1_HG_RESULT_2 0x0f21 13655#define regABM2_DC_ABM1_HG_RESULT_2_BASE_IDX 3 13656#define regABM2_DC_ABM1_HG_RESULT_3 0x0f22 13657#define regABM2_DC_ABM1_HG_RESULT_3_BASE_IDX 3 13658#define regABM2_DC_ABM1_HG_RESULT_4 0x0f23 13659#define regABM2_DC_ABM1_HG_RESULT_4_BASE_IDX 3 13660#define regABM2_DC_ABM1_HG_RESULT_5 0x0f24 13661#define regABM2_DC_ABM1_HG_RESULT_5_BASE_IDX 3 13662#define regABM2_DC_ABM1_HG_RESULT_6 0x0f25 13663#define regABM2_DC_ABM1_HG_RESULT_6_BASE_IDX 3 13664#define regABM2_DC_ABM1_HG_RESULT_7 0x0f26 13665#define regABM2_DC_ABM1_HG_RESULT_7_BASE_IDX 3 13666#define regABM2_DC_ABM1_HG_RESULT_8 0x0f27 13667#define regABM2_DC_ABM1_HG_RESULT_8_BASE_IDX 3 13668#define regABM2_DC_ABM1_HG_RESULT_9 0x0f28 13669#define regABM2_DC_ABM1_HG_RESULT_9_BASE_IDX 3 13670#define regABM2_DC_ABM1_HG_RESULT_10 0x0f29 13671#define regABM2_DC_ABM1_HG_RESULT_10_BASE_IDX 3 13672#define regABM2_DC_ABM1_HG_RESULT_11 0x0f2a 13673#define regABM2_DC_ABM1_HG_RESULT_11_BASE_IDX 3 13674#define regABM2_DC_ABM1_HG_RESULT_12 0x0f2b 13675#define regABM2_DC_ABM1_HG_RESULT_12_BASE_IDX 3 13676#define regABM2_DC_ABM1_HG_RESULT_13 0x0f2c 13677#define regABM2_DC_ABM1_HG_RESULT_13_BASE_IDX 3 13678#define regABM2_DC_ABM1_HG_RESULT_14 0x0f2d 13679#define regABM2_DC_ABM1_HG_RESULT_14_BASE_IDX 3 13680#define regABM2_DC_ABM1_HG_RESULT_15 0x0f2e 13681#define regABM2_DC_ABM1_HG_RESULT_15_BASE_IDX 3 13682#define regABM2_DC_ABM1_HG_RESULT_16 0x0f2f 13683#define regABM2_DC_ABM1_HG_RESULT_16_BASE_IDX 3 13684#define regABM2_DC_ABM1_HG_RESULT_17 0x0f30 13685#define regABM2_DC_ABM1_HG_RESULT_17_BASE_IDX 3 13686#define regABM2_DC_ABM1_HG_RESULT_18 0x0f31 13687#define regABM2_DC_ABM1_HG_RESULT_18_BASE_IDX 3 13688#define regABM2_DC_ABM1_HG_RESULT_19 0x0f32 13689#define regABM2_DC_ABM1_HG_RESULT_19_BASE_IDX 3 13690#define regABM2_DC_ABM1_HG_RESULT_20 0x0f33 13691#define regABM2_DC_ABM1_HG_RESULT_20_BASE_IDX 3 13692#define regABM2_DC_ABM1_HG_RESULT_21 0x0f34 13693#define regABM2_DC_ABM1_HG_RESULT_21_BASE_IDX 3 13694#define regABM2_DC_ABM1_HG_RESULT_22 0x0f35 13695#define regABM2_DC_ABM1_HG_RESULT_22_BASE_IDX 3 13696#define regABM2_DC_ABM1_HG_RESULT_23 0x0f36 13697#define regABM2_DC_ABM1_HG_RESULT_23_BASE_IDX 3 13698#define regABM2_DC_ABM1_HG_RESULT_24 0x0f37 13699#define regABM2_DC_ABM1_HG_RESULT_24_BASE_IDX 3 13700#define regABM2_DC_ABM1_BL_MASTER_LOCK 0x0f38 13701#define regABM2_DC_ABM1_BL_MASTER_LOCK_BASE_IDX 3 13702 13703 13704// addressBlock: dce_dc_opp_abm3_dispdec 13705// base address: 0x30c 13706#define regABM3_BL1_PWM_AMBIENT_LIGHT_LEVEL 0x0f3d 13707#define regABM3_BL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX 3 13708#define regABM3_BL1_PWM_USER_LEVEL 0x0f3e 13709#define regABM3_BL1_PWM_USER_LEVEL_BASE_IDX 3 13710#define regABM3_BL1_PWM_TARGET_ABM_LEVEL 0x0f3f 13711#define regABM3_BL1_PWM_TARGET_ABM_LEVEL_BASE_IDX 3 13712#define regABM3_BL1_PWM_CURRENT_ABM_LEVEL 0x0f40 13713#define regABM3_BL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX 3 13714#define regABM3_BL1_PWM_FINAL_DUTY_CYCLE 0x0f41 13715#define regABM3_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX 3 13716#define regABM3_BL1_PWM_MINIMUM_DUTY_CYCLE 0x0f42 13717#define regABM3_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX 3 13718#define regABM3_BL1_PWM_ABM_CNTL 0x0f43 13719#define regABM3_BL1_PWM_ABM_CNTL_BASE_IDX 3 13720#define regABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE 0x0f44 13721#define regABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX 3 13722#define regABM3_BL1_PWM_GRP2_REG_LOCK 0x0f45 13723#define regABM3_BL1_PWM_GRP2_REG_LOCK_BASE_IDX 3 13724#define regABM3_DC_ABM1_CNTL 0x0f46 13725#define regABM3_DC_ABM1_CNTL_BASE_IDX 3 13726#define regABM3_DC_ABM1_IPCSC_COEFF_SEL 0x0f47 13727#define regABM3_DC_ABM1_IPCSC_COEFF_SEL_BASE_IDX 3 13728#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_0 0x0f48 13729#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_0_BASE_IDX 3 13730#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_1 0x0f49 13731#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_1_BASE_IDX 3 13732#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_2 0x0f4a 13733#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_2_BASE_IDX 3 13734#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_3 0x0f4b 13735#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_3_BASE_IDX 3 13736#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_4 0x0f4c 13737#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_4_BASE_IDX 3 13738#define regABM3_DC_ABM1_ACE_THRES_12 0x0f4d 13739#define regABM3_DC_ABM1_ACE_THRES_12_BASE_IDX 3 13740#define regABM3_DC_ABM1_ACE_THRES_34 0x0f4e 13741#define regABM3_DC_ABM1_ACE_THRES_34_BASE_IDX 3 13742#define regABM3_DC_ABM1_ACE_CNTL_MISC 0x0f4f 13743#define regABM3_DC_ABM1_ACE_CNTL_MISC_BASE_IDX 3 13744#define regABM3_DC_ABM1_HGLS_REG_READ_PROGRESS 0x0f51 13745#define regABM3_DC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX 3 13746#define regABM3_DC_ABM1_HG_MISC_CTRL 0x0f52 13747#define regABM3_DC_ABM1_HG_MISC_CTRL_BASE_IDX 3 13748#define regABM3_DC_ABM1_LS_SUM_OF_LUMA 0x0f53 13749#define regABM3_DC_ABM1_LS_SUM_OF_LUMA_BASE_IDX 3 13750#define regABM3_DC_ABM1_LS_MIN_MAX_LUMA 0x0f54 13751#define regABM3_DC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX 3 13752#define regABM3_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA 0x0f55 13753#define regABM3_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX 3 13754#define regABM3_DC_ABM1_LS_PIXEL_COUNT 0x0f56 13755#define regABM3_DC_ABM1_LS_PIXEL_COUNT_BASE_IDX 3 13756#define regABM3_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES 0x0f57 13757#define regABM3_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX 3 13758#define regABM3_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT 0x0f58 13759#define regABM3_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX 3 13760#define regABM3_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT 0x0f59 13761#define regABM3_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX 3 13762#define regABM3_DC_ABM1_HG_SAMPLE_RATE 0x0f5a 13763#define regABM3_DC_ABM1_HG_SAMPLE_RATE_BASE_IDX 3 13764#define regABM3_DC_ABM1_LS_SAMPLE_RATE 0x0f5b 13765#define regABM3_DC_ABM1_LS_SAMPLE_RATE_BASE_IDX 3 13766#define regABM3_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG 0x0f5c 13767#define regABM3_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX 3 13768#define regABM3_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX 0x0f5d 13769#define regABM3_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX 3 13770#define regABM3_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX 0x0f5e 13771#define regABM3_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX 3 13772#define regABM3_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX 0x0f5f 13773#define regABM3_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX 3 13774#define regABM3_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX 0x0f60 13775#define regABM3_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX 3 13776#define regABM3_DC_ABM1_HG_RESULT_1 0x0f61 13777#define regABM3_DC_ABM1_HG_RESULT_1_BASE_IDX 3 13778#define regABM3_DC_ABM1_HG_RESULT_2 0x0f62 13779#define regABM3_DC_ABM1_HG_RESULT_2_BASE_IDX 3 13780#define regABM3_DC_ABM1_HG_RESULT_3 0x0f63 13781#define regABM3_DC_ABM1_HG_RESULT_3_BASE_IDX 3 13782#define regABM3_DC_ABM1_HG_RESULT_4 0x0f64 13783#define regABM3_DC_ABM1_HG_RESULT_4_BASE_IDX 3 13784#define regABM3_DC_ABM1_HG_RESULT_5 0x0f65 13785#define regABM3_DC_ABM1_HG_RESULT_5_BASE_IDX 3 13786#define regABM3_DC_ABM1_HG_RESULT_6 0x0f66 13787#define regABM3_DC_ABM1_HG_RESULT_6_BASE_IDX 3 13788#define regABM3_DC_ABM1_HG_RESULT_7 0x0f67 13789#define regABM3_DC_ABM1_HG_RESULT_7_BASE_IDX 3 13790#define regABM3_DC_ABM1_HG_RESULT_8 0x0f68 13791#define regABM3_DC_ABM1_HG_RESULT_8_BASE_IDX 3 13792#define regABM3_DC_ABM1_HG_RESULT_9 0x0f69 13793#define regABM3_DC_ABM1_HG_RESULT_9_BASE_IDX 3 13794#define regABM3_DC_ABM1_HG_RESULT_10 0x0f6a 13795#define regABM3_DC_ABM1_HG_RESULT_10_BASE_IDX 3 13796#define regABM3_DC_ABM1_HG_RESULT_11 0x0f6b 13797#define regABM3_DC_ABM1_HG_RESULT_11_BASE_IDX 3 13798#define regABM3_DC_ABM1_HG_RESULT_12 0x0f6c 13799#define regABM3_DC_ABM1_HG_RESULT_12_BASE_IDX 3 13800#define regABM3_DC_ABM1_HG_RESULT_13 0x0f6d 13801#define regABM3_DC_ABM1_HG_RESULT_13_BASE_IDX 3 13802#define regABM3_DC_ABM1_HG_RESULT_14 0x0f6e 13803#define regABM3_DC_ABM1_HG_RESULT_14_BASE_IDX 3 13804#define regABM3_DC_ABM1_HG_RESULT_15 0x0f6f 13805#define regABM3_DC_ABM1_HG_RESULT_15_BASE_IDX 3 13806#define regABM3_DC_ABM1_HG_RESULT_16 0x0f70 13807#define regABM3_DC_ABM1_HG_RESULT_16_BASE_IDX 3 13808#define regABM3_DC_ABM1_HG_RESULT_17 0x0f71 13809#define regABM3_DC_ABM1_HG_RESULT_17_BASE_IDX 3 13810#define regABM3_DC_ABM1_HG_RESULT_18 0x0f72 13811#define regABM3_DC_ABM1_HG_RESULT_18_BASE_IDX 3 13812#define regABM3_DC_ABM1_HG_RESULT_19 0x0f73 13813#define regABM3_DC_ABM1_HG_RESULT_19_BASE_IDX 3 13814#define regABM3_DC_ABM1_HG_RESULT_20 0x0f74 13815#define regABM3_DC_ABM1_HG_RESULT_20_BASE_IDX 3 13816#define regABM3_DC_ABM1_HG_RESULT_21 0x0f75 13817#define regABM3_DC_ABM1_HG_RESULT_21_BASE_IDX 3 13818#define regABM3_DC_ABM1_HG_RESULT_22 0x0f76 13819#define regABM3_DC_ABM1_HG_RESULT_22_BASE_IDX 3 13820#define regABM3_DC_ABM1_HG_RESULT_23 0x0f77 13821#define regABM3_DC_ABM1_HG_RESULT_23_BASE_IDX 3 13822#define regABM3_DC_ABM1_HG_RESULT_24 0x0f78 13823#define regABM3_DC_ABM1_HG_RESULT_24_BASE_IDX 3 13824#define regABM3_DC_ABM1_BL_MASTER_LOCK 0x0f79 13825#define regABM3_DC_ABM1_BL_MASTER_LOCK_BASE_IDX 3 13826 13827 13828// addressBlock: dce_dc_hpo_hdmi_link_enc0_dispdec 13829// base address: 0x2656c 13830#define regHDMI_LINK_ENC_CONTROL 0x095b 13831#define regHDMI_LINK_ENC_CONTROL_BASE_IDX 3 13832#define regHDMI_LINK_ENC_CLK_CTRL 0x095c 13833#define regHDMI_LINK_ENC_CLK_CTRL_BASE_IDX 3 13834 13835 13836// addressBlock: dce_dc_hpo_hdmi_frl_enc0_dispdec 13837// base address: 0x26594 13838#define regHDMI_FRL_ENC_CONFIG 0x0965 13839#define regHDMI_FRL_ENC_CONFIG_BASE_IDX 3 13840#define regHDMI_FRL_ENC_CONFIG2 0x0966 13841#define regHDMI_FRL_ENC_CONFIG2_BASE_IDX 3 13842#define regHDMI_FRL_ENC_METER_BUFFER_STATUS 0x0967 13843#define regHDMI_FRL_ENC_METER_BUFFER_STATUS_BASE_IDX 3 13844#define regHDMI_FRL_ENC_MEM_CTRL 0x0968 13845#define regHDMI_FRL_ENC_MEM_CTRL_BASE_IDX 3 13846 13847 13848// addressBlock: dce_dc_hpo_hdmi_stream_enc0_dispdec 13849// base address: 0x2634c 13850#define regHDMI_STREAM_ENC_CLOCK_CONTROL 0x08d3 13851#define regHDMI_STREAM_ENC_CLOCK_CONTROL_BASE_IDX 3 13852#define regHDMI_STREAM_ENC_INPUT_MUX_CONTROL 0x08d5 13853#define regHDMI_STREAM_ENC_INPUT_MUX_CONTROL_BASE_IDX 3 13854#define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0 0x08d6 13855#define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0_BASE_IDX 3 13856#define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1 0x08d7 13857#define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1_BASE_IDX 3 13858#define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2 0x08d8 13859#define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2_BASE_IDX 3 13860 13861 13862// addressBlock: dce_dc_hpo_hdmi_tb_enc0_dispdec 13863// base address: 0x2637c 13864#define regHDMI_TB_ENC_CONTROL 0x08df 13865#define regHDMI_TB_ENC_CONTROL_BASE_IDX 3 13866#define regHDMI_TB_ENC_PIXEL_FORMAT 0x08e0 13867#define regHDMI_TB_ENC_PIXEL_FORMAT_BASE_IDX 3 13868#define regHDMI_TB_ENC_PACKET_CONTROL 0x08e1 13869#define regHDMI_TB_ENC_PACKET_CONTROL_BASE_IDX 3 13870#define regHDMI_TB_ENC_ACR_PACKET_CONTROL 0x08e2 13871#define regHDMI_TB_ENC_ACR_PACKET_CONTROL_BASE_IDX 3 13872#define regHDMI_TB_ENC_VBI_PACKET_CONTROL1 0x08e3 13873#define regHDMI_TB_ENC_VBI_PACKET_CONTROL1_BASE_IDX 3 13874#define regHDMI_TB_ENC_VBI_PACKET_CONTROL2 0x08e4 13875#define regHDMI_TB_ENC_VBI_PACKET_CONTROL2_BASE_IDX 3 13876#define regHDMI_TB_ENC_GC_CONTROL 0x08e5 13877#define regHDMI_TB_ENC_GC_CONTROL_BASE_IDX 3 13878#define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL0 0x08e6 13879#define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL0_BASE_IDX 3 13880#define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL1 0x08e7 13881#define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL1_BASE_IDX 3 13882#define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL2 0x08e8 13883#define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL2_BASE_IDX 3 13884#define regHDMI_TB_ENC_GENERIC_PACKET0_1_LINE 0x08e9 13885#define regHDMI_TB_ENC_GENERIC_PACKET0_1_LINE_BASE_IDX 3 13886#define regHDMI_TB_ENC_GENERIC_PACKET2_3_LINE 0x08ea 13887#define regHDMI_TB_ENC_GENERIC_PACKET2_3_LINE_BASE_IDX 3 13888#define regHDMI_TB_ENC_GENERIC_PACKET4_5_LINE 0x08eb 13889#define regHDMI_TB_ENC_GENERIC_PACKET4_5_LINE_BASE_IDX 3 13890#define regHDMI_TB_ENC_GENERIC_PACKET6_7_LINE 0x08ec 13891#define regHDMI_TB_ENC_GENERIC_PACKET6_7_LINE_BASE_IDX 3 13892#define regHDMI_TB_ENC_GENERIC_PACKET8_9_LINE 0x08ed 13893#define regHDMI_TB_ENC_GENERIC_PACKET8_9_LINE_BASE_IDX 3 13894#define regHDMI_TB_ENC_GENERIC_PACKET10_11_LINE 0x08ee 13895#define regHDMI_TB_ENC_GENERIC_PACKET10_11_LINE_BASE_IDX 3 13896#define regHDMI_TB_ENC_GENERIC_PACKET12_13_LINE 0x08ef 13897#define regHDMI_TB_ENC_GENERIC_PACKET12_13_LINE_BASE_IDX 3 13898#define regHDMI_TB_ENC_GENERIC_PACKET14_LINE 0x08f0 13899#define regHDMI_TB_ENC_GENERIC_PACKET14_LINE_BASE_IDX 3 13900#define regHDMI_TB_ENC_DB_CONTROL 0x08f1 13901#define regHDMI_TB_ENC_DB_CONTROL_BASE_IDX 3 13902#define regHDMI_TB_ENC_ACR_32_0 0x08f2 13903#define regHDMI_TB_ENC_ACR_32_0_BASE_IDX 3 13904#define regHDMI_TB_ENC_ACR_32_1 0x08f3 13905#define regHDMI_TB_ENC_ACR_32_1_BASE_IDX 3 13906#define regHDMI_TB_ENC_ACR_44_0 0x08f4 13907#define regHDMI_TB_ENC_ACR_44_0_BASE_IDX 3 13908#define regHDMI_TB_ENC_ACR_44_1 0x08f5 13909#define regHDMI_TB_ENC_ACR_44_1_BASE_IDX 3 13910#define regHDMI_TB_ENC_ACR_48_0 0x08f6 13911#define regHDMI_TB_ENC_ACR_48_0_BASE_IDX 3 13912#define regHDMI_TB_ENC_ACR_48_1 0x08f7 13913#define regHDMI_TB_ENC_ACR_48_1_BASE_IDX 3 13914#define regHDMI_TB_ENC_ACR_STATUS_0 0x08f8 13915#define regHDMI_TB_ENC_ACR_STATUS_0_BASE_IDX 3 13916#define regHDMI_TB_ENC_ACR_STATUS_1 0x08f9 13917#define regHDMI_TB_ENC_ACR_STATUS_1_BASE_IDX 3 13918#define regHDMI_TB_ENC_BUFFER_CONTROL 0x08fb 13919#define regHDMI_TB_ENC_BUFFER_CONTROL_BASE_IDX 3 13920#define regHDMI_TB_ENC_MEM_CTRL 0x08fe 13921#define regHDMI_TB_ENC_MEM_CTRL_BASE_IDX 3 13922#define regHDMI_TB_ENC_METADATA_PACKET_CONTROL 0x08ff 13923#define regHDMI_TB_ENC_METADATA_PACKET_CONTROL_BASE_IDX 3 13924#define regHDMI_TB_ENC_H_ACTIVE_BLANK 0x0900 13925#define regHDMI_TB_ENC_H_ACTIVE_BLANK_BASE_IDX 3 13926#define regHDMI_TB_ENC_HC_ACTIVE_BLANK 0x0901 13927#define regHDMI_TB_ENC_HC_ACTIVE_BLANK_BASE_IDX 3 13928#define regHDMI_TB_ENC_CRC_CNTL 0x0903 13929#define regHDMI_TB_ENC_CRC_CNTL_BASE_IDX 3 13930#define regHDMI_TB_ENC_CRC_RESULT_0 0x0904 13931#define regHDMI_TB_ENC_CRC_RESULT_0_BASE_IDX 3 13932#define regHDMI_TB_ENC_ENCRYPTION_CONTROL 0x0907 13933#define regHDMI_TB_ENC_ENCRYPTION_CONTROL_BASE_IDX 3 13934#define regHDMI_TB_ENC_MODE 0x0908 13935#define regHDMI_TB_ENC_MODE_BASE_IDX 3 13936#define regHDMI_TB_ENC_INPUT_FIFO_STATUS 0x0909 13937#define regHDMI_TB_ENC_INPUT_FIFO_STATUS_BASE_IDX 3 13938#define regHDMI_TB_ENC_CRC_RESULT_1 0x090a 13939#define regHDMI_TB_ENC_CRC_RESULT_1_BASE_IDX 3 13940 13941 13942// addressBlock: dce_dc_mpc_mpcc_mcm0_dispdec 13943// base address: 0x0 13944#define regMPCC_MCM0_MPCC_MCM_SHAPER_CONTROL 0x0453 13945#define regMPCC_MCM0_MPCC_MCM_SHAPER_CONTROL_BASE_IDX 3 13946#define regMPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_R 0x0454 13947#define regMPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_R_BASE_IDX 3 13948#define regMPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_G 0x0455 13949#define regMPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_G_BASE_IDX 3 13950#define regMPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_B 0x0456 13951#define regMPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_B_BASE_IDX 3 13952#define regMPCC_MCM0_MPCC_MCM_SHAPER_SCALE_R 0x0457 13953#define regMPCC_MCM0_MPCC_MCM_SHAPER_SCALE_R_BASE_IDX 3 13954#define regMPCC_MCM0_MPCC_MCM_SHAPER_SCALE_G_B 0x0458 13955#define regMPCC_MCM0_MPCC_MCM_SHAPER_SCALE_G_B_BASE_IDX 3 13956#define regMPCC_MCM0_MPCC_MCM_SHAPER_LUT_INDEX 0x0459 13957#define regMPCC_MCM0_MPCC_MCM_SHAPER_LUT_INDEX_BASE_IDX 3 13958#define regMPCC_MCM0_MPCC_MCM_SHAPER_LUT_DATA 0x045a 13959#define regMPCC_MCM0_MPCC_MCM_SHAPER_LUT_DATA_BASE_IDX 3 13960#define regMPCC_MCM0_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK 0x045b 13961#define regMPCC_MCM0_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX 3 13962#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_B 0x045c 13963#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_B_BASE_IDX 3 13964#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_G 0x045d 13965#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_G_BASE_IDX 3 13966#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_R 0x045e 13967#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_R_BASE_IDX 3 13968#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_B 0x045f 13969#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_B_BASE_IDX 3 13970#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_G 0x0460 13971#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_G_BASE_IDX 3 13972#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_R 0x0461 13973#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_R_BASE_IDX 3 13974#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_0_1 0x0462 13975#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_0_1_BASE_IDX 3 13976#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_2_3 0x0463 13977#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_2_3_BASE_IDX 3 13978#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_4_5 0x0464 13979#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_4_5_BASE_IDX 3 13980#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_6_7 0x0465 13981#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_6_7_BASE_IDX 3 13982#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_8_9 0x0466 13983#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_8_9_BASE_IDX 3 13984#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_10_11 0x0467 13985#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_10_11_BASE_IDX 3 13986#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_12_13 0x0468 13987#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_12_13_BASE_IDX 3 13988#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_14_15 0x0469 13989#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_14_15_BASE_IDX 3 13990#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_16_17 0x046a 13991#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_16_17_BASE_IDX 3 13992#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_18_19 0x046b 13993#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_18_19_BASE_IDX 3 13994#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_20_21 0x046c 13995#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_20_21_BASE_IDX 3 13996#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_22_23 0x046d 13997#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_22_23_BASE_IDX 3 13998#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_24_25 0x046e 13999#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_24_25_BASE_IDX 3 14000#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_26_27 0x046f 14001#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_26_27_BASE_IDX 3 14002#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_28_29 0x0470 14003#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_28_29_BASE_IDX 3 14004#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_30_31 0x0471 14005#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_30_31_BASE_IDX 3 14006#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_32_33 0x0472 14007#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_32_33_BASE_IDX 3 14008#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_B 0x0473 14009#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_B_BASE_IDX 3 14010#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_G 0x0474 14011#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_G_BASE_IDX 3 14012#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_R 0x0475 14013#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_R_BASE_IDX 3 14014#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_B 0x0476 14015#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_B_BASE_IDX 3 14016#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_G 0x0477 14017#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_G_BASE_IDX 3 14018#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_R 0x0478 14019#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_R_BASE_IDX 3 14020#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_0_1 0x0479 14021#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_0_1_BASE_IDX 3 14022#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_2_3 0x047a 14023#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_2_3_BASE_IDX 3 14024#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_4_5 0x047b 14025#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_4_5_BASE_IDX 3 14026#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_6_7 0x047c 14027#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_6_7_BASE_IDX 3 14028#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_8_9 0x047d 14029#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_8_9_BASE_IDX 3 14030#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_10_11 0x047e 14031#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_10_11_BASE_IDX 3 14032#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_12_13 0x047f 14033#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_12_13_BASE_IDX 3 14034#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_14_15 0x0480 14035#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_14_15_BASE_IDX 3 14036#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_16_17 0x0481 14037#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_16_17_BASE_IDX 3 14038#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_18_19 0x0482 14039#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_18_19_BASE_IDX 3 14040#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_20_21 0x0483 14041#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_20_21_BASE_IDX 3 14042#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_22_23 0x0484 14043#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_22_23_BASE_IDX 3 14044#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_24_25 0x0485 14045#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_24_25_BASE_IDX 3 14046#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_26_27 0x0486 14047#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_26_27_BASE_IDX 3 14048#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_28_29 0x0487 14049#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_28_29_BASE_IDX 3 14050#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_30_31 0x0488 14051#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_30_31_BASE_IDX 3 14052#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_32_33 0x0489 14053#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_32_33_BASE_IDX 3 14054#define regMPCC_MCM0_MPCC_MCM_3DLUT_MODE 0x048a 14055#define regMPCC_MCM0_MPCC_MCM_3DLUT_MODE_BASE_IDX 3 14056#define regMPCC_MCM0_MPCC_MCM_3DLUT_INDEX 0x048b 14057#define regMPCC_MCM0_MPCC_MCM_3DLUT_INDEX_BASE_IDX 3 14058#define regMPCC_MCM0_MPCC_MCM_3DLUT_DATA 0x048c 14059#define regMPCC_MCM0_MPCC_MCM_3DLUT_DATA_BASE_IDX 3 14060#define regMPCC_MCM0_MPCC_MCM_3DLUT_DATA_30BIT 0x048d 14061#define regMPCC_MCM0_MPCC_MCM_3DLUT_DATA_30BIT_BASE_IDX 3 14062#define regMPCC_MCM0_MPCC_MCM_3DLUT_READ_WRITE_CONTROL 0x048e 14063#define regMPCC_MCM0_MPCC_MCM_3DLUT_READ_WRITE_CONTROL_BASE_IDX 3 14064#define regMPCC_MCM0_MPCC_MCM_3DLUT_OUT_NORM_FACTOR 0x048f 14065#define regMPCC_MCM0_MPCC_MCM_3DLUT_OUT_NORM_FACTOR_BASE_IDX 3 14066#define regMPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_R 0x0490 14067#define regMPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_R_BASE_IDX 3 14068#define regMPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_G 0x0491 14069#define regMPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_G_BASE_IDX 3 14070#define regMPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_B 0x0492 14071#define regMPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_B_BASE_IDX 3 14072#define regMPCC_MCM0_MPCC_MCM_1DLUT_CONTROL 0x0493 14073#define regMPCC_MCM0_MPCC_MCM_1DLUT_CONTROL_BASE_IDX 3 14074#define regMPCC_MCM0_MPCC_MCM_1DLUT_LUT_INDEX 0x0494 14075#define regMPCC_MCM0_MPCC_MCM_1DLUT_LUT_INDEX_BASE_IDX 3 14076#define regMPCC_MCM0_MPCC_MCM_1DLUT_LUT_DATA 0x0495 14077#define regMPCC_MCM0_MPCC_MCM_1DLUT_LUT_DATA_BASE_IDX 3 14078#define regMPCC_MCM0_MPCC_MCM_1DLUT_LUT_CONTROL 0x0496 14079#define regMPCC_MCM0_MPCC_MCM_1DLUT_LUT_CONTROL_BASE_IDX 3 14080#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_B 0x0497 14081#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_B_BASE_IDX 3 14082#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_G 0x0498 14083#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_G_BASE_IDX 3 14084#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_R 0x0499 14085#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_R_BASE_IDX 3 14086#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B 0x049a 14087#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B_BASE_IDX 3 14088#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G 0x049b 14089#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G_BASE_IDX 3 14090#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R 0x049c 14091#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R_BASE_IDX 3 14092#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B 0x049d 14093#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B_BASE_IDX 3 14094#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G 0x049e 14095#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G_BASE_IDX 3 14096#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R 0x049f 14097#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R_BASE_IDX 3 14098#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B 0x04a0 14099#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B_BASE_IDX 3 14100#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B 0x04a1 14101#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B_BASE_IDX 3 14102#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G 0x04a2 14103#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G_BASE_IDX 3 14104#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G 0x04a3 14105#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G_BASE_IDX 3 14106#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R 0x04a4 14107#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R_BASE_IDX 3 14108#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R 0x04a5 14109#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R_BASE_IDX 3 14110#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_B 0x04a6 14111#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_B_BASE_IDX 3 14112#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_G 0x04a7 14113#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_G_BASE_IDX 3 14114#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_R 0x04a8 14115#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_R_BASE_IDX 3 14116#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_0_1 0x04a9 14117#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_0_1_BASE_IDX 3 14118#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_2_3 0x04aa 14119#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_2_3_BASE_IDX 3 14120#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_4_5 0x04ab 14121#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_4_5_BASE_IDX 3 14122#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_6_7 0x04ac 14123#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_6_7_BASE_IDX 3 14124#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_8_9 0x04ad 14125#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_8_9_BASE_IDX 3 14126#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_10_11 0x04ae 14127#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_10_11_BASE_IDX 3 14128#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_12_13 0x04af 14129#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_12_13_BASE_IDX 3 14130#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_14_15 0x04b0 14131#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_14_15_BASE_IDX 3 14132#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_16_17 0x04b1 14133#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_16_17_BASE_IDX 3 14134#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_18_19 0x04b2 14135#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_18_19_BASE_IDX 3 14136#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_20_21 0x04b3 14137#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_20_21_BASE_IDX 3 14138#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_22_23 0x04b4 14139#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_22_23_BASE_IDX 3 14140#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_24_25 0x04b5 14141#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_24_25_BASE_IDX 3 14142#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_26_27 0x04b6 14143#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_26_27_BASE_IDX 3 14144#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_28_29 0x04b7 14145#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_28_29_BASE_IDX 3 14146#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_30_31 0x04b8 14147#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_30_31_BASE_IDX 3 14148#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_32_33 0x04b9 14149#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_32_33_BASE_IDX 3 14150#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_B 0x04ba 14151#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_B_BASE_IDX 3 14152#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_G 0x04bb 14153#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_G_BASE_IDX 3 14154#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_R 0x04bc 14155#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_R_BASE_IDX 3 14156#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B 0x04bd 14157#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B_BASE_IDX 3 14158#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G 0x04be 14159#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G_BASE_IDX 3 14160#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R 0x04bf 14161#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R_BASE_IDX 3 14162#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B 0x04c0 14163#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B_BASE_IDX 3 14164#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G 0x04c1 14165#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G_BASE_IDX 3 14166#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R 0x04c2 14167#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R_BASE_IDX 3 14168#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B 0x04c3 14169#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B_BASE_IDX 3 14170#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B 0x04c4 14171#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B_BASE_IDX 3 14172#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G 0x04c5 14173#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G_BASE_IDX 3 14174#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G 0x04c6 14175#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G_BASE_IDX 3 14176#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R 0x04c7 14177#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R_BASE_IDX 3 14178#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R 0x04c8 14179#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R_BASE_IDX 3 14180#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_B 0x04c9 14181#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_B_BASE_IDX 3 14182#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_G 0x04ca 14183#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_G_BASE_IDX 3 14184#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_R 0x04cb 14185#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_R_BASE_IDX 3 14186#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_0_1 0x04cc 14187#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_0_1_BASE_IDX 3 14188#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_2_3 0x04cd 14189#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_2_3_BASE_IDX 3 14190#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_4_5 0x04ce 14191#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_4_5_BASE_IDX 3 14192#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_6_7 0x04cf 14193#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_6_7_BASE_IDX 3 14194#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_8_9 0x04d0 14195#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_8_9_BASE_IDX 3 14196#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_10_11 0x04d1 14197#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_10_11_BASE_IDX 3 14198#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_12_13 0x04d2 14199#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_12_13_BASE_IDX 3 14200#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_14_15 0x04d3 14201#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_14_15_BASE_IDX 3 14202#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_16_17 0x04d4 14203#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_16_17_BASE_IDX 3 14204#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_18_19 0x04d5 14205#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_18_19_BASE_IDX 3 14206#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_20_21 0x04d6 14207#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_20_21_BASE_IDX 3 14208#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_22_23 0x04d7 14209#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_22_23_BASE_IDX 3 14210#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_24_25 0x04d8 14211#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_24_25_BASE_IDX 3 14212#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_26_27 0x04d9 14213#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_26_27_BASE_IDX 3 14214#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_28_29 0x04da 14215#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_28_29_BASE_IDX 3 14216#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_30_31 0x04db 14217#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_30_31_BASE_IDX 3 14218#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_32_33 0x04dc 14219#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_32_33_BASE_IDX 3 14220#define regMPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL 0x04dd 14221#define regMPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL_BASE_IDX 3 14222 14223 14224// addressBlock: dce_dc_mpc_mpcc_mcm1_dispdec 14225// base address: 0x240 14226#define regMPCC_MCM1_MPCC_MCM_SHAPER_CONTROL 0x04e3 14227#define regMPCC_MCM1_MPCC_MCM_SHAPER_CONTROL_BASE_IDX 3 14228#define regMPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_R 0x04e4 14229#define regMPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_R_BASE_IDX 3 14230#define regMPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_G 0x04e5 14231#define regMPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_G_BASE_IDX 3 14232#define regMPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_B 0x04e6 14233#define regMPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_B_BASE_IDX 3 14234#define regMPCC_MCM1_MPCC_MCM_SHAPER_SCALE_R 0x04e7 14235#define regMPCC_MCM1_MPCC_MCM_SHAPER_SCALE_R_BASE_IDX 3 14236#define regMPCC_MCM1_MPCC_MCM_SHAPER_SCALE_G_B 0x04e8 14237#define regMPCC_MCM1_MPCC_MCM_SHAPER_SCALE_G_B_BASE_IDX 3 14238#define regMPCC_MCM1_MPCC_MCM_SHAPER_LUT_INDEX 0x04e9 14239#define regMPCC_MCM1_MPCC_MCM_SHAPER_LUT_INDEX_BASE_IDX 3 14240#define regMPCC_MCM1_MPCC_MCM_SHAPER_LUT_DATA 0x04ea 14241#define regMPCC_MCM1_MPCC_MCM_SHAPER_LUT_DATA_BASE_IDX 3 14242#define regMPCC_MCM1_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK 0x04eb 14243#define regMPCC_MCM1_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX 3 14244#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_B 0x04ec 14245#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_B_BASE_IDX 3 14246#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_G 0x04ed 14247#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_G_BASE_IDX 3 14248#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_R 0x04ee 14249#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_R_BASE_IDX 3 14250#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_B 0x04ef 14251#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_B_BASE_IDX 3 14252#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_G 0x04f0 14253#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_G_BASE_IDX 3 14254#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_R 0x04f1 14255#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_R_BASE_IDX 3 14256#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_0_1 0x04f2 14257#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_0_1_BASE_IDX 3 14258#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_2_3 0x04f3 14259#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_2_3_BASE_IDX 3 14260#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_4_5 0x04f4 14261#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_4_5_BASE_IDX 3 14262#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_6_7 0x04f5 14263#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_6_7_BASE_IDX 3 14264#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_8_9 0x04f6 14265#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_8_9_BASE_IDX 3 14266#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_10_11 0x04f7 14267#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_10_11_BASE_IDX 3 14268#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_12_13 0x04f8 14269#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_12_13_BASE_IDX 3 14270#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_14_15 0x04f9 14271#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_14_15_BASE_IDX 3 14272#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_16_17 0x04fa 14273#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_16_17_BASE_IDX 3 14274#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_18_19 0x04fb 14275#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_18_19_BASE_IDX 3 14276#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_20_21 0x04fc 14277#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_20_21_BASE_IDX 3 14278#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_22_23 0x04fd 14279#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_22_23_BASE_IDX 3 14280#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_24_25 0x04fe 14281#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_24_25_BASE_IDX 3 14282#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_26_27 0x04ff 14283#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_26_27_BASE_IDX 3 14284#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_28_29 0x0500 14285#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_28_29_BASE_IDX 3 14286#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_30_31 0x0501 14287#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_30_31_BASE_IDX 3 14288#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_32_33 0x0502 14289#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_32_33_BASE_IDX 3 14290#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_B 0x0503 14291#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_B_BASE_IDX 3 14292#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_G 0x0504 14293#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_G_BASE_IDX 3 14294#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_R 0x0505 14295#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_R_BASE_IDX 3 14296#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_B 0x0506 14297#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_B_BASE_IDX 3 14298#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_G 0x0507 14299#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_G_BASE_IDX 3 14300#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_R 0x0508 14301#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_R_BASE_IDX 3 14302#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_0_1 0x0509 14303#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_0_1_BASE_IDX 3 14304#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_2_3 0x050a 14305#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_2_3_BASE_IDX 3 14306#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_4_5 0x050b 14307#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_4_5_BASE_IDX 3 14308#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_6_7 0x050c 14309#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_6_7_BASE_IDX 3 14310#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_8_9 0x050d 14311#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_8_9_BASE_IDX 3 14312#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_10_11 0x050e 14313#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_10_11_BASE_IDX 3 14314#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_12_13 0x050f 14315#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_12_13_BASE_IDX 3 14316#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_14_15 0x0510 14317#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_14_15_BASE_IDX 3 14318#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_16_17 0x0511 14319#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_16_17_BASE_IDX 3 14320#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_18_19 0x0512 14321#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_18_19_BASE_IDX 3 14322#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_20_21 0x0513 14323#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_20_21_BASE_IDX 3 14324#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_22_23 0x0514 14325#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_22_23_BASE_IDX 3 14326#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_24_25 0x0515 14327#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_24_25_BASE_IDX 3 14328#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_26_27 0x0516 14329#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_26_27_BASE_IDX 3 14330#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_28_29 0x0517 14331#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_28_29_BASE_IDX 3 14332#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_30_31 0x0518 14333#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_30_31_BASE_IDX 3 14334#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_32_33 0x0519 14335#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_32_33_BASE_IDX 3 14336#define regMPCC_MCM1_MPCC_MCM_3DLUT_MODE 0x051a 14337#define regMPCC_MCM1_MPCC_MCM_3DLUT_MODE_BASE_IDX 3 14338#define regMPCC_MCM1_MPCC_MCM_3DLUT_INDEX 0x051b 14339#define regMPCC_MCM1_MPCC_MCM_3DLUT_INDEX_BASE_IDX 3 14340#define regMPCC_MCM1_MPCC_MCM_3DLUT_DATA 0x051c 14341#define regMPCC_MCM1_MPCC_MCM_3DLUT_DATA_BASE_IDX 3 14342#define regMPCC_MCM1_MPCC_MCM_3DLUT_DATA_30BIT 0x051d 14343#define regMPCC_MCM1_MPCC_MCM_3DLUT_DATA_30BIT_BASE_IDX 3 14344#define regMPCC_MCM1_MPCC_MCM_3DLUT_READ_WRITE_CONTROL 0x051e 14345#define regMPCC_MCM1_MPCC_MCM_3DLUT_READ_WRITE_CONTROL_BASE_IDX 3 14346#define regMPCC_MCM1_MPCC_MCM_3DLUT_OUT_NORM_FACTOR 0x051f 14347#define regMPCC_MCM1_MPCC_MCM_3DLUT_OUT_NORM_FACTOR_BASE_IDX 3 14348#define regMPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_R 0x0520 14349#define regMPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_R_BASE_IDX 3 14350#define regMPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_G 0x0521 14351#define regMPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_G_BASE_IDX 3 14352#define regMPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_B 0x0522 14353#define regMPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_B_BASE_IDX 3 14354#define regMPCC_MCM1_MPCC_MCM_1DLUT_CONTROL 0x0523 14355#define regMPCC_MCM1_MPCC_MCM_1DLUT_CONTROL_BASE_IDX 3 14356#define regMPCC_MCM1_MPCC_MCM_1DLUT_LUT_INDEX 0x0524 14357#define regMPCC_MCM1_MPCC_MCM_1DLUT_LUT_INDEX_BASE_IDX 3 14358#define regMPCC_MCM1_MPCC_MCM_1DLUT_LUT_DATA 0x0525 14359#define regMPCC_MCM1_MPCC_MCM_1DLUT_LUT_DATA_BASE_IDX 3 14360#define regMPCC_MCM1_MPCC_MCM_1DLUT_LUT_CONTROL 0x0526 14361#define regMPCC_MCM1_MPCC_MCM_1DLUT_LUT_CONTROL_BASE_IDX 3 14362#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_B 0x0527 14363#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_B_BASE_IDX 3 14364#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_G 0x0528 14365#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_G_BASE_IDX 3 14366#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_R 0x0529 14367#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_R_BASE_IDX 3 14368#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B 0x052a 14369#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B_BASE_IDX 3 14370#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G 0x052b 14371#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G_BASE_IDX 3 14372#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R 0x052c 14373#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R_BASE_IDX 3 14374#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B 0x052d 14375#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B_BASE_IDX 3 14376#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G 0x052e 14377#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G_BASE_IDX 3 14378#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R 0x052f 14379#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R_BASE_IDX 3 14380#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B 0x0530 14381#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B_BASE_IDX 3 14382#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B 0x0531 14383#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B_BASE_IDX 3 14384#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G 0x0532 14385#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G_BASE_IDX 3 14386#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G 0x0533 14387#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G_BASE_IDX 3 14388#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R 0x0534 14389#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R_BASE_IDX 3 14390#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R 0x0535 14391#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R_BASE_IDX 3 14392#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_B 0x0536 14393#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_B_BASE_IDX 3 14394#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_G 0x0537 14395#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_G_BASE_IDX 3 14396#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_R 0x0538 14397#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_R_BASE_IDX 3 14398#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_0_1 0x0539 14399#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_0_1_BASE_IDX 3 14400#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_2_3 0x053a 14401#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_2_3_BASE_IDX 3 14402#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_4_5 0x053b 14403#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_4_5_BASE_IDX 3 14404#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_6_7 0x053c 14405#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_6_7_BASE_IDX 3 14406#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_8_9 0x053d 14407#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_8_9_BASE_IDX 3 14408#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_10_11 0x053e 14409#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_10_11_BASE_IDX 3 14410#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_12_13 0x053f 14411#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_12_13_BASE_IDX 3 14412#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_14_15 0x0540 14413#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_14_15_BASE_IDX 3 14414#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_16_17 0x0541 14415#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_16_17_BASE_IDX 3 14416#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_18_19 0x0542 14417#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_18_19_BASE_IDX 3 14418#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_20_21 0x0543 14419#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_20_21_BASE_IDX 3 14420#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_22_23 0x0544 14421#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_22_23_BASE_IDX 3 14422#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_24_25 0x0545 14423#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_24_25_BASE_IDX 3 14424#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_26_27 0x0546 14425#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_26_27_BASE_IDX 3 14426#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_28_29 0x0547 14427#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_28_29_BASE_IDX 3 14428#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_30_31 0x0548 14429#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_30_31_BASE_IDX 3 14430#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_32_33 0x0549 14431#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_32_33_BASE_IDX 3 14432#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_B 0x054a 14433#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_B_BASE_IDX 3 14434#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_G 0x054b 14435#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_G_BASE_IDX 3 14436#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_R 0x054c 14437#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_R_BASE_IDX 3 14438#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B 0x054d 14439#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B_BASE_IDX 3 14440#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G 0x054e 14441#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G_BASE_IDX 3 14442#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R 0x054f 14443#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R_BASE_IDX 3 14444#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B 0x0550 14445#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B_BASE_IDX 3 14446#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G 0x0551 14447#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G_BASE_IDX 3 14448#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R 0x0552 14449#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R_BASE_IDX 3 14450#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B 0x0553 14451#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B_BASE_IDX 3 14452#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B 0x0554 14453#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B_BASE_IDX 3 14454#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G 0x0555 14455#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G_BASE_IDX 3 14456#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G 0x0556 14457#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G_BASE_IDX 3 14458#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R 0x0557 14459#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R_BASE_IDX 3 14460#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R 0x0558 14461#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R_BASE_IDX 3 14462#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_B 0x0559 14463#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_B_BASE_IDX 3 14464#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_G 0x055a 14465#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_G_BASE_IDX 3 14466#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_R 0x055b 14467#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_R_BASE_IDX 3 14468#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_0_1 0x055c 14469#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_0_1_BASE_IDX 3 14470#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_2_3 0x055d 14471#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_2_3_BASE_IDX 3 14472#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_4_5 0x055e 14473#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_4_5_BASE_IDX 3 14474#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_6_7 0x055f 14475#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_6_7_BASE_IDX 3 14476#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_8_9 0x0560 14477#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_8_9_BASE_IDX 3 14478#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_10_11 0x0561 14479#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_10_11_BASE_IDX 3 14480#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_12_13 0x0562 14481#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_12_13_BASE_IDX 3 14482#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_14_15 0x0563 14483#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_14_15_BASE_IDX 3 14484#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_16_17 0x0564 14485#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_16_17_BASE_IDX 3 14486#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_18_19 0x0565 14487#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_18_19_BASE_IDX 3 14488#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_20_21 0x0566 14489#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_20_21_BASE_IDX 3 14490#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_22_23 0x0567 14491#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_22_23_BASE_IDX 3 14492#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_24_25 0x0568 14493#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_24_25_BASE_IDX 3 14494#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_26_27 0x0569 14495#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_26_27_BASE_IDX 3 14496#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_28_29 0x056a 14497#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_28_29_BASE_IDX 3 14498#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_30_31 0x056b 14499#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_30_31_BASE_IDX 3 14500#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_32_33 0x056c 14501#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_32_33_BASE_IDX 3 14502#define regMPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL 0x056d 14503#define regMPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL_BASE_IDX 3 14504 14505 14506// addressBlock: dce_dc_mpc_mpcc_mcm2_dispdec 14507// base address: 0x480 14508#define regMPCC_MCM2_MPCC_MCM_SHAPER_CONTROL 0x0573 14509#define regMPCC_MCM2_MPCC_MCM_SHAPER_CONTROL_BASE_IDX 3 14510#define regMPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_R 0x0574 14511#define regMPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_R_BASE_IDX 3 14512#define regMPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_G 0x0575 14513#define regMPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_G_BASE_IDX 3 14514#define regMPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_B 0x0576 14515#define regMPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_B_BASE_IDX 3 14516#define regMPCC_MCM2_MPCC_MCM_SHAPER_SCALE_R 0x0577 14517#define regMPCC_MCM2_MPCC_MCM_SHAPER_SCALE_R_BASE_IDX 3 14518#define regMPCC_MCM2_MPCC_MCM_SHAPER_SCALE_G_B 0x0578 14519#define regMPCC_MCM2_MPCC_MCM_SHAPER_SCALE_G_B_BASE_IDX 3 14520#define regMPCC_MCM2_MPCC_MCM_SHAPER_LUT_INDEX 0x0579 14521#define regMPCC_MCM2_MPCC_MCM_SHAPER_LUT_INDEX_BASE_IDX 3 14522#define regMPCC_MCM2_MPCC_MCM_SHAPER_LUT_DATA 0x057a 14523#define regMPCC_MCM2_MPCC_MCM_SHAPER_LUT_DATA_BASE_IDX 3 14524#define regMPCC_MCM2_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK 0x057b 14525#define regMPCC_MCM2_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX 3 14526#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_B 0x057c 14527#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_B_BASE_IDX 3 14528#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_G 0x057d 14529#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_G_BASE_IDX 3 14530#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_R 0x057e 14531#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_R_BASE_IDX 3 14532#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_B 0x057f 14533#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_B_BASE_IDX 3 14534#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_G 0x0580 14535#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_G_BASE_IDX 3 14536#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_R 0x0581 14537#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_R_BASE_IDX 3 14538#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_0_1 0x0582 14539#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_0_1_BASE_IDX 3 14540#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_2_3 0x0583 14541#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_2_3_BASE_IDX 3 14542#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_4_5 0x0584 14543#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_4_5_BASE_IDX 3 14544#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_6_7 0x0585 14545#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_6_7_BASE_IDX 3 14546#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_8_9 0x0586 14547#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_8_9_BASE_IDX 3 14548#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_10_11 0x0587 14549#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_10_11_BASE_IDX 3 14550#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_12_13 0x0588 14551#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_12_13_BASE_IDX 3 14552#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_14_15 0x0589 14553#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_14_15_BASE_IDX 3 14554#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_16_17 0x058a 14555#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_16_17_BASE_IDX 3 14556#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_18_19 0x058b 14557#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_18_19_BASE_IDX 3 14558#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_20_21 0x058c 14559#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_20_21_BASE_IDX 3 14560#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_22_23 0x058d 14561#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_22_23_BASE_IDX 3 14562#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_24_25 0x058e 14563#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_24_25_BASE_IDX 3 14564#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_26_27 0x058f 14565#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_26_27_BASE_IDX 3 14566#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_28_29 0x0590 14567#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_28_29_BASE_IDX 3 14568#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_30_31 0x0591 14569#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_30_31_BASE_IDX 3 14570#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_32_33 0x0592 14571#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_32_33_BASE_IDX 3 14572#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_B 0x0593 14573#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_B_BASE_IDX 3 14574#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_G 0x0594 14575#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_G_BASE_IDX 3 14576#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_R 0x0595 14577#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_R_BASE_IDX 3 14578#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_B 0x0596 14579#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_B_BASE_IDX 3 14580#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_G 0x0597 14581#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_G_BASE_IDX 3 14582#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_R 0x0598 14583#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_R_BASE_IDX 3 14584#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_0_1 0x0599 14585#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_0_1_BASE_IDX 3 14586#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_2_3 0x059a 14587#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_2_3_BASE_IDX 3 14588#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_4_5 0x059b 14589#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_4_5_BASE_IDX 3 14590#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_6_7 0x059c 14591#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_6_7_BASE_IDX 3 14592#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_8_9 0x059d 14593#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_8_9_BASE_IDX 3 14594#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_10_11 0x059e 14595#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_10_11_BASE_IDX 3 14596#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_12_13 0x059f 14597#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_12_13_BASE_IDX 3 14598#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_14_15 0x05a0 14599#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_14_15_BASE_IDX 3 14600#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_16_17 0x05a1 14601#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_16_17_BASE_IDX 3 14602#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_18_19 0x05a2 14603#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_18_19_BASE_IDX 3 14604#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_20_21 0x05a3 14605#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_20_21_BASE_IDX 3 14606#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_22_23 0x05a4 14607#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_22_23_BASE_IDX 3 14608#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_24_25 0x05a5 14609#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_24_25_BASE_IDX 3 14610#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_26_27 0x05a6 14611#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_26_27_BASE_IDX 3 14612#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_28_29 0x05a7 14613#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_28_29_BASE_IDX 3 14614#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_30_31 0x05a8 14615#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_30_31_BASE_IDX 3 14616#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_32_33 0x05a9 14617#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_32_33_BASE_IDX 3 14618#define regMPCC_MCM2_MPCC_MCM_3DLUT_MODE 0x05aa 14619#define regMPCC_MCM2_MPCC_MCM_3DLUT_MODE_BASE_IDX 3 14620#define regMPCC_MCM2_MPCC_MCM_3DLUT_INDEX 0x05ab 14621#define regMPCC_MCM2_MPCC_MCM_3DLUT_INDEX_BASE_IDX 3 14622#define regMPCC_MCM2_MPCC_MCM_3DLUT_DATA 0x05ac 14623#define regMPCC_MCM2_MPCC_MCM_3DLUT_DATA_BASE_IDX 3 14624#define regMPCC_MCM2_MPCC_MCM_3DLUT_DATA_30BIT 0x05ad 14625#define regMPCC_MCM2_MPCC_MCM_3DLUT_DATA_30BIT_BASE_IDX 3 14626#define regMPCC_MCM2_MPCC_MCM_3DLUT_READ_WRITE_CONTROL 0x05ae 14627#define regMPCC_MCM2_MPCC_MCM_3DLUT_READ_WRITE_CONTROL_BASE_IDX 3 14628#define regMPCC_MCM2_MPCC_MCM_3DLUT_OUT_NORM_FACTOR 0x05af 14629#define regMPCC_MCM2_MPCC_MCM_3DLUT_OUT_NORM_FACTOR_BASE_IDX 3 14630#define regMPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_R 0x05b0 14631#define regMPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_R_BASE_IDX 3 14632#define regMPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_G 0x05b1 14633#define regMPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_G_BASE_IDX 3 14634#define regMPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_B 0x05b2 14635#define regMPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_B_BASE_IDX 3 14636#define regMPCC_MCM2_MPCC_MCM_1DLUT_CONTROL 0x05b3 14637#define regMPCC_MCM2_MPCC_MCM_1DLUT_CONTROL_BASE_IDX 3 14638#define regMPCC_MCM2_MPCC_MCM_1DLUT_LUT_INDEX 0x05b4 14639#define regMPCC_MCM2_MPCC_MCM_1DLUT_LUT_INDEX_BASE_IDX 3 14640#define regMPCC_MCM2_MPCC_MCM_1DLUT_LUT_DATA 0x05b5 14641#define regMPCC_MCM2_MPCC_MCM_1DLUT_LUT_DATA_BASE_IDX 3 14642#define regMPCC_MCM2_MPCC_MCM_1DLUT_LUT_CONTROL 0x05b6 14643#define regMPCC_MCM2_MPCC_MCM_1DLUT_LUT_CONTROL_BASE_IDX 3 14644#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_B 0x05b7 14645#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_B_BASE_IDX 3 14646#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_G 0x05b8 14647#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_G_BASE_IDX 3 14648#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_R 0x05b9 14649#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_R_BASE_IDX 3 14650#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B 0x05ba 14651#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B_BASE_IDX 3 14652#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G 0x05bb 14653#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G_BASE_IDX 3 14654#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R 0x05bc 14655#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R_BASE_IDX 3 14656#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B 0x05bd 14657#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B_BASE_IDX 3 14658#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G 0x05be 14659#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G_BASE_IDX 3 14660#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R 0x05bf 14661#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R_BASE_IDX 3 14662#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B 0x05c0 14663#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B_BASE_IDX 3 14664#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B 0x05c1 14665#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B_BASE_IDX 3 14666#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G 0x05c2 14667#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G_BASE_IDX 3 14668#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G 0x05c3 14669#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G_BASE_IDX 3 14670#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R 0x05c4 14671#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R_BASE_IDX 3 14672#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R 0x05c5 14673#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R_BASE_IDX 3 14674#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_B 0x05c6 14675#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_B_BASE_IDX 3 14676#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_G 0x05c7 14677#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_G_BASE_IDX 3 14678#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_R 0x05c8 14679#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_R_BASE_IDX 3 14680#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_0_1 0x05c9 14681#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_0_1_BASE_IDX 3 14682#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_2_3 0x05ca 14683#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_2_3_BASE_IDX 3 14684#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_4_5 0x05cb 14685#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_4_5_BASE_IDX 3 14686#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_6_7 0x05cc 14687#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_6_7_BASE_IDX 3 14688#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_8_9 0x05cd 14689#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_8_9_BASE_IDX 3 14690#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_10_11 0x05ce 14691#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_10_11_BASE_IDX 3 14692#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_12_13 0x05cf 14693#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_12_13_BASE_IDX 3 14694#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_14_15 0x05d0 14695#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_14_15_BASE_IDX 3 14696#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_16_17 0x05d1 14697#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_16_17_BASE_IDX 3 14698#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_18_19 0x05d2 14699#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_18_19_BASE_IDX 3 14700#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_20_21 0x05d3 14701#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_20_21_BASE_IDX 3 14702#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_22_23 0x05d4 14703#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_22_23_BASE_IDX 3 14704#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_24_25 0x05d5 14705#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_24_25_BASE_IDX 3 14706#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_26_27 0x05d6 14707#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_26_27_BASE_IDX 3 14708#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_28_29 0x05d7 14709#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_28_29_BASE_IDX 3 14710#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_30_31 0x05d8 14711#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_30_31_BASE_IDX 3 14712#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_32_33 0x05d9 14713#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_32_33_BASE_IDX 3 14714#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_B 0x05da 14715#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_B_BASE_IDX 3 14716#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_G 0x05db 14717#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_G_BASE_IDX 3 14718#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_R 0x05dc 14719#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_R_BASE_IDX 3 14720#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B 0x05dd 14721#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B_BASE_IDX 3 14722#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G 0x05de 14723#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G_BASE_IDX 3 14724#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R 0x05df 14725#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R_BASE_IDX 3 14726#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B 0x05e0 14727#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B_BASE_IDX 3 14728#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G 0x05e1 14729#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G_BASE_IDX 3 14730#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R 0x05e2 14731#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R_BASE_IDX 3 14732#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B 0x05e3 14733#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B_BASE_IDX 3 14734#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B 0x05e4 14735#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B_BASE_IDX 3 14736#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G 0x05e5 14737#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G_BASE_IDX 3 14738#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G 0x05e6 14739#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G_BASE_IDX 3 14740#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R 0x05e7 14741#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R_BASE_IDX 3 14742#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R 0x05e8 14743#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R_BASE_IDX 3 14744#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_B 0x05e9 14745#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_B_BASE_IDX 3 14746#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_G 0x05ea 14747#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_G_BASE_IDX 3 14748#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_R 0x05eb 14749#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_R_BASE_IDX 3 14750#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_0_1 0x05ec 14751#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_0_1_BASE_IDX 3 14752#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_2_3 0x05ed 14753#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_2_3_BASE_IDX 3 14754#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_4_5 0x05ee 14755#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_4_5_BASE_IDX 3 14756#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_6_7 0x05ef 14757#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_6_7_BASE_IDX 3 14758#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_8_9 0x05f0 14759#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_8_9_BASE_IDX 3 14760#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_10_11 0x05f1 14761#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_10_11_BASE_IDX 3 14762#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_12_13 0x05f2 14763#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_12_13_BASE_IDX 3 14764#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_14_15 0x05f3 14765#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_14_15_BASE_IDX 3 14766#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_16_17 0x05f4 14767#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_16_17_BASE_IDX 3 14768#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_18_19 0x05f5 14769#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_18_19_BASE_IDX 3 14770#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_20_21 0x05f6 14771#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_20_21_BASE_IDX 3 14772#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_22_23 0x05f7 14773#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_22_23_BASE_IDX 3 14774#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_24_25 0x05f8 14775#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_24_25_BASE_IDX 3 14776#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_26_27 0x05f9 14777#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_26_27_BASE_IDX 3 14778#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_28_29 0x05fa 14779#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_28_29_BASE_IDX 3 14780#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_30_31 0x05fb 14781#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_30_31_BASE_IDX 3 14782#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_32_33 0x05fc 14783#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_32_33_BASE_IDX 3 14784#define regMPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL 0x05fd 14785#define regMPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL_BASE_IDX 3 14786 14787 14788// addressBlock: dce_dc_mpc_mpcc_mcm3_dispdec 14789// base address: 0x6c0 14790#define regMPCC_MCM3_MPCC_MCM_SHAPER_CONTROL 0x0603 14791#define regMPCC_MCM3_MPCC_MCM_SHAPER_CONTROL_BASE_IDX 3 14792#define regMPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_R 0x0604 14793#define regMPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_R_BASE_IDX 3 14794#define regMPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_G 0x0605 14795#define regMPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_G_BASE_IDX 3 14796#define regMPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_B 0x0606 14797#define regMPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_B_BASE_IDX 3 14798#define regMPCC_MCM3_MPCC_MCM_SHAPER_SCALE_R 0x0607 14799#define regMPCC_MCM3_MPCC_MCM_SHAPER_SCALE_R_BASE_IDX 3 14800#define regMPCC_MCM3_MPCC_MCM_SHAPER_SCALE_G_B 0x0608 14801#define regMPCC_MCM3_MPCC_MCM_SHAPER_SCALE_G_B_BASE_IDX 3 14802#define regMPCC_MCM3_MPCC_MCM_SHAPER_LUT_INDEX 0x0609 14803#define regMPCC_MCM3_MPCC_MCM_SHAPER_LUT_INDEX_BASE_IDX 3 14804#define regMPCC_MCM3_MPCC_MCM_SHAPER_LUT_DATA 0x060a 14805#define regMPCC_MCM3_MPCC_MCM_SHAPER_LUT_DATA_BASE_IDX 3 14806#define regMPCC_MCM3_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK 0x060b 14807#define regMPCC_MCM3_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX 3 14808#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_B 0x060c 14809#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_B_BASE_IDX 3 14810#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_G 0x060d 14811#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_G_BASE_IDX 3 14812#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_R 0x060e 14813#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_R_BASE_IDX 3 14814#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_B 0x060f 14815#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_B_BASE_IDX 3 14816#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_G 0x0610 14817#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_G_BASE_IDX 3 14818#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_R 0x0611 14819#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_R_BASE_IDX 3 14820#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_0_1 0x0612 14821#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_0_1_BASE_IDX 3 14822#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_2_3 0x0613 14823#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_2_3_BASE_IDX 3 14824#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_4_5 0x0614 14825#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_4_5_BASE_IDX 3 14826#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_6_7 0x0615 14827#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_6_7_BASE_IDX 3 14828#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_8_9 0x0616 14829#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_8_9_BASE_IDX 3 14830#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_10_11 0x0617 14831#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_10_11_BASE_IDX 3 14832#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_12_13 0x0618 14833#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_12_13_BASE_IDX 3 14834#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_14_15 0x0619 14835#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_14_15_BASE_IDX 3 14836#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_16_17 0x061a 14837#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_16_17_BASE_IDX 3 14838#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_18_19 0x061b 14839#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_18_19_BASE_IDX 3 14840#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_20_21 0x061c 14841#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_20_21_BASE_IDX 3 14842#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_22_23 0x061d 14843#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_22_23_BASE_IDX 3 14844#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_24_25 0x061e 14845#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_24_25_BASE_IDX 3 14846#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_26_27 0x061f 14847#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_26_27_BASE_IDX 3 14848#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_28_29 0x0620 14849#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_28_29_BASE_IDX 3 14850#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_30_31 0x0621 14851#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_30_31_BASE_IDX 3 14852#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_32_33 0x0622 14853#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_32_33_BASE_IDX 3 14854#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_B 0x0623 14855#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_B_BASE_IDX 3 14856#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_G 0x0624 14857#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_G_BASE_IDX 3 14858#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_R 0x0625 14859#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_R_BASE_IDX 3 14860#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_B 0x0626 14861#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_B_BASE_IDX 3 14862#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_G 0x0627 14863#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_G_BASE_IDX 3 14864#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_R 0x0628 14865#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_R_BASE_IDX 3 14866#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_0_1 0x0629 14867#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_0_1_BASE_IDX 3 14868#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_2_3 0x062a 14869#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_2_3_BASE_IDX 3 14870#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_4_5 0x062b 14871#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_4_5_BASE_IDX 3 14872#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_6_7 0x062c 14873#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_6_7_BASE_IDX 3 14874#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_8_9 0x062d 14875#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_8_9_BASE_IDX 3 14876#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_10_11 0x062e 14877#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_10_11_BASE_IDX 3 14878#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_12_13 0x062f 14879#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_12_13_BASE_IDX 3 14880#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_14_15 0x0630 14881#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_14_15_BASE_IDX 3 14882#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_16_17 0x0631 14883#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_16_17_BASE_IDX 3 14884#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_18_19 0x0632 14885#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_18_19_BASE_IDX 3 14886#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_20_21 0x0633 14887#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_20_21_BASE_IDX 3 14888#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_22_23 0x0634 14889#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_22_23_BASE_IDX 3 14890#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_24_25 0x0635 14891#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_24_25_BASE_IDX 3 14892#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_26_27 0x0636 14893#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_26_27_BASE_IDX 3 14894#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_28_29 0x0637 14895#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_28_29_BASE_IDX 3 14896#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_30_31 0x0638 14897#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_30_31_BASE_IDX 3 14898#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_32_33 0x0639 14899#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_32_33_BASE_IDX 3 14900#define regMPCC_MCM3_MPCC_MCM_3DLUT_MODE 0x063a 14901#define regMPCC_MCM3_MPCC_MCM_3DLUT_MODE_BASE_IDX 3 14902#define regMPCC_MCM3_MPCC_MCM_3DLUT_INDEX 0x063b 14903#define regMPCC_MCM3_MPCC_MCM_3DLUT_INDEX_BASE_IDX 3 14904#define regMPCC_MCM3_MPCC_MCM_3DLUT_DATA 0x063c 14905#define regMPCC_MCM3_MPCC_MCM_3DLUT_DATA_BASE_IDX 3 14906#define regMPCC_MCM3_MPCC_MCM_3DLUT_DATA_30BIT 0x063d 14907#define regMPCC_MCM3_MPCC_MCM_3DLUT_DATA_30BIT_BASE_IDX 3 14908#define regMPCC_MCM3_MPCC_MCM_3DLUT_READ_WRITE_CONTROL 0x063e 14909#define regMPCC_MCM3_MPCC_MCM_3DLUT_READ_WRITE_CONTROL_BASE_IDX 3 14910#define regMPCC_MCM3_MPCC_MCM_3DLUT_OUT_NORM_FACTOR 0x063f 14911#define regMPCC_MCM3_MPCC_MCM_3DLUT_OUT_NORM_FACTOR_BASE_IDX 3 14912#define regMPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_R 0x0640 14913#define regMPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_R_BASE_IDX 3 14914#define regMPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_G 0x0641 14915#define regMPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_G_BASE_IDX 3 14916#define regMPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_B 0x0642 14917#define regMPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_B_BASE_IDX 3 14918#define regMPCC_MCM3_MPCC_MCM_1DLUT_CONTROL 0x0643 14919#define regMPCC_MCM3_MPCC_MCM_1DLUT_CONTROL_BASE_IDX 3 14920#define regMPCC_MCM3_MPCC_MCM_1DLUT_LUT_INDEX 0x0644 14921#define regMPCC_MCM3_MPCC_MCM_1DLUT_LUT_INDEX_BASE_IDX 3 14922#define regMPCC_MCM3_MPCC_MCM_1DLUT_LUT_DATA 0x0645 14923#define regMPCC_MCM3_MPCC_MCM_1DLUT_LUT_DATA_BASE_IDX 3 14924#define regMPCC_MCM3_MPCC_MCM_1DLUT_LUT_CONTROL 0x0646 14925#define regMPCC_MCM3_MPCC_MCM_1DLUT_LUT_CONTROL_BASE_IDX 3 14926#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_B 0x0647 14927#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_B_BASE_IDX 3 14928#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_G 0x0648 14929#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_G_BASE_IDX 3 14930#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_R 0x0649 14931#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_R_BASE_IDX 3 14932#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B 0x064a 14933#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B_BASE_IDX 3 14934#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G 0x064b 14935#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G_BASE_IDX 3 14936#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R 0x064c 14937#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R_BASE_IDX 3 14938#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B 0x064d 14939#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B_BASE_IDX 3 14940#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G 0x064e 14941#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G_BASE_IDX 3 14942#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R 0x064f 14943#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R_BASE_IDX 3 14944#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B 0x0650 14945#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B_BASE_IDX 3 14946#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B 0x0651 14947#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B_BASE_IDX 3 14948#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G 0x0652 14949#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G_BASE_IDX 3 14950#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G 0x0653 14951#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G_BASE_IDX 3 14952#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R 0x0654 14953#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R_BASE_IDX 3 14954#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R 0x0655 14955#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R_BASE_IDX 3 14956#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_B 0x0656 14957#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_B_BASE_IDX 3 14958#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_G 0x0657 14959#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_G_BASE_IDX 3 14960#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_R 0x0658 14961#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_R_BASE_IDX 3 14962#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_0_1 0x0659 14963#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_0_1_BASE_IDX 3 14964#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_2_3 0x065a 14965#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_2_3_BASE_IDX 3 14966#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_4_5 0x065b 14967#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_4_5_BASE_IDX 3 14968#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_6_7 0x065c 14969#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_6_7_BASE_IDX 3 14970#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_8_9 0x065d 14971#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_8_9_BASE_IDX 3 14972#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_10_11 0x065e 14973#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_10_11_BASE_IDX 3 14974#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_12_13 0x065f 14975#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_12_13_BASE_IDX 3 14976#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_14_15 0x0660 14977#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_14_15_BASE_IDX 3 14978#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_16_17 0x0661 14979#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_16_17_BASE_IDX 3 14980#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_18_19 0x0662 14981#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_18_19_BASE_IDX 3 14982#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_20_21 0x0663 14983#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_20_21_BASE_IDX 3 14984#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_22_23 0x0664 14985#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_22_23_BASE_IDX 3 14986#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_24_25 0x0665 14987#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_24_25_BASE_IDX 3 14988#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_26_27 0x0666 14989#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_26_27_BASE_IDX 3 14990#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_28_29 0x0667 14991#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_28_29_BASE_IDX 3 14992#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_30_31 0x0668 14993#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_30_31_BASE_IDX 3 14994#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_32_33 0x0669 14995#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_32_33_BASE_IDX 3 14996#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_B 0x066a 14997#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_B_BASE_IDX 3 14998#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_G 0x066b 14999#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_G_BASE_IDX 3 15000#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_R 0x066c 15001#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_R_BASE_IDX 3 15002#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B 0x066d 15003#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B_BASE_IDX 3 15004#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G 0x066e 15005#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G_BASE_IDX 3 15006#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R 0x066f 15007#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R_BASE_IDX 3 15008#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B 0x0670 15009#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B_BASE_IDX 3 15010#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G 0x0671 15011#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G_BASE_IDX 3 15012#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R 0x0672 15013#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R_BASE_IDX 3 15014#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B 0x0673 15015#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B_BASE_IDX 3 15016#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B 0x0674 15017#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B_BASE_IDX 3 15018#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G 0x0675 15019#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G_BASE_IDX 3 15020#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G 0x0676 15021#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G_BASE_IDX 3 15022#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R 0x0677 15023#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R_BASE_IDX 3 15024#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R 0x0678 15025#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R_BASE_IDX 3 15026#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_B 0x0679 15027#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_B_BASE_IDX 3 15028#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_G 0x067a 15029#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_G_BASE_IDX 3 15030#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_R 0x067b 15031#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_R_BASE_IDX 3 15032#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_0_1 0x067c 15033#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_0_1_BASE_IDX 3 15034#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_2_3 0x067d 15035#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_2_3_BASE_IDX 3 15036#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_4_5 0x067e 15037#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_4_5_BASE_IDX 3 15038#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_6_7 0x067f 15039#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_6_7_BASE_IDX 3 15040#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_8_9 0x0680 15041#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_8_9_BASE_IDX 3 15042#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_10_11 0x0681 15043#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_10_11_BASE_IDX 3 15044#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_12_13 0x0682 15045#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_12_13_BASE_IDX 3 15046#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_14_15 0x0683 15047#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_14_15_BASE_IDX 3 15048#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_16_17 0x0684 15049#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_16_17_BASE_IDX 3 15050#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_18_19 0x0685 15051#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_18_19_BASE_IDX 3 15052#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_20_21 0x0686 15053#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_20_21_BASE_IDX 3 15054#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_22_23 0x0687 15055#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_22_23_BASE_IDX 3 15056#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_24_25 0x0688 15057#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_24_25_BASE_IDX 3 15058#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_26_27 0x0689 15059#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_26_27_BASE_IDX 3 15060#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_28_29 0x068a 15061#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_28_29_BASE_IDX 3 15062#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_30_31 0x068b 15063#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_30_31_BASE_IDX 3 15064#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_32_33 0x068c 15065#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_32_33_BASE_IDX 3 15066#define regMPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL 0x068d 15067#define regMPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL_BASE_IDX 3 15068 15069 15070// addressBlock: dce_dc_dlpc_dlpc_dispdec 15071// base address: 0x0 15072#define regDLPC_ENABLE 0x2fe8 15073#define regDLPC_ENABLE_BASE_IDX 2 15074#define regDLPC_CURRENT_COUNT 0x2fe9 15075#define regDLPC_CURRENT_COUNT_BASE_IDX 2 15076#define regDLPC_OPTC_SNAPSHOT 0x2fea 15077#define regDLPC_OPTC_SNAPSHOT_BASE_IDX 2 15078#define regDLPC_PWRUP 0x2feb 15079#define regDLPC_PWRUP_BASE_IDX 2 15080#define regDLPC_OTG_RESYNC 0x2fec 15081#define regDLPC_OTG_RESYNC_BASE_IDX 2 15082#define regDLPC_DCN_ZSC_LONO_PWRUP 0x2fed 15083#define regDLPC_DCN_ZSC_LONO_PWRUP_BASE_IDX 2 15084#define regDLPC_SPARE 0x2fee 15085#define regDLPC_SPARE_BASE_IDX 2 15086#define regDLPC_COUNTER_INIT_VALUE 0x2fef 15087#define regDLPC_COUNTER_INIT_VALUE_BASE_IDX 2 15088 15089 15090// addressBlock: dce_dpia_dpia_mu0_dpiadec 15091// base address: 0x72000 15092#define regDPIA_MU_CLOCK_CTRL 0x13800 15093#define regDPIA_MU_CLOCK_CTRL_BASE_IDX 3 15094#define regDPIA_MU_CLOCK_CTRL_DPIA_PORT0 0x13801 15095#define regDPIA_MU_CLOCK_CTRL_DPIA_PORT0_BASE_IDX 3 15096#define regDPIA_MU_RESET_CTRL_DPIA_PORT0 0x13802 15097#define regDPIA_MU_RESET_CTRL_DPIA_PORT0_BASE_IDX 3 15098#define regDPIA_MU_CLOCK_CTRL_DPIA_PORT1 0x13803 15099#define regDPIA_MU_CLOCK_CTRL_DPIA_PORT1_BASE_IDX 3 15100#define regDPIA_MU_RESET_CTRL_DPIA_PORT1 0x13804 15101#define regDPIA_MU_RESET_CTRL_DPIA_PORT1_BASE_IDX 3 15102#define regDPIA_MU_CLOCK_CTRL_DPIA_PORT2 0x13805 15103#define regDPIA_MU_CLOCK_CTRL_DPIA_PORT2_BASE_IDX 3 15104#define regDPIA_MU_RESET_CTRL_DPIA_PORT2 0x13806 15105#define regDPIA_MU_RESET_CTRL_DPIA_PORT2_BASE_IDX 3 15106#define regDPIA_MU_CLOCK_CTRL_DPIA_PORT3 0x13807 15107#define regDPIA_MU_CLOCK_CTRL_DPIA_PORT3_BASE_IDX 3 15108#define regDPIA_MU_RESET_CTRL_DPIA_PORT3 0x13808 15109#define regDPIA_MU_RESET_CTRL_DPIA_PORT3_BASE_IDX 3 15110#define regDPIA_MU_TPI_STATUS_DPIA_PORT0 0x13811 15111#define regDPIA_MU_TPI_STATUS_DPIA_PORT0_BASE_IDX 3 15112#define regDPIA_MU_TPI_STATUS_DPIA_PORT1 0x13812 15113#define regDPIA_MU_TPI_STATUS_DPIA_PORT1_BASE_IDX 3 15114#define regDPIA_MU_TPI_STATUS_DPIA_PORT2 0x13813 15115#define regDPIA_MU_TPI_STATUS_DPIA_PORT2_BASE_IDX 3 15116#define regDPIA_MU_TPI_STATUS_DPIA_PORT3 0x13814 15117#define regDPIA_MU_TPI_STATUS_DPIA_PORT3_BASE_IDX 3 15118#define regDPIA_MU_TPI_MAX_CREDIT_COUNT 0x13819 15119#define regDPIA_MU_TPI_MAX_CREDIT_COUNT_BASE_IDX 3 15120#define regDPIA_MU_INTERRUPT_STATUS 0x1381a 15121#define regDPIA_MU_INTERRUPT_STATUS_BASE_IDX 3 15122#define regDPIA_MU_INTERRUPT_CTRL 0x1381b 15123#define regDPIA_MU_INTERRUPT_CTRL_BASE_IDX 3 15124#define regDPIA_MU_LOCAL_INTERRUPT_CTRL 0x1381c 15125#define regDPIA_MU_LOCAL_INTERRUPT_CTRL_BASE_IDX 3 15126#define regDPIA_MU_LOCAL_INTERRUPT_ACK 0x1381d 15127#define regDPIA_MU_LOCAL_INTERRUPT_ACK_BASE_IDX 3 15128#define regDPIA_MU_RBBMIF_TIMEOUT_CTRL 0x1381e 15129#define regDPIA_MU_RBBMIF_TIMEOUT_CTRL_BASE_IDX 3 15130#define regDPIA_MU_RBBMIF_TIMEOUT_CTRL2 0x1381f 15131#define regDPIA_MU_RBBMIF_TIMEOUT_CTRL2_BASE_IDX 3 15132#define regDPIA_MU_RBBMIF_STATUS 0x13820 15133#define regDPIA_MU_RBBMIF_STATUS_BASE_IDX 3 15134#define regDPIA_MU_MICROSECOND_REF_CTRL 0x13821 15135#define regDPIA_MU_MICROSECOND_REF_CTRL_BASE_IDX 3 15136#define regDPIA_MU_PORT_ADP_STATUS 0x13822 15137#define regDPIA_MU_PORT_ADP_STATUS_BASE_IDX 3 15138#define regDPIA_GLUE_CTRL 0x13823 15139#define regDPIA_GLUE_CTRL_BASE_IDX 3 15140#define regDPIA_PERF_COUNT_CONTROL0 0x13825 15141#define regDPIA_PERF_COUNT_CONTROL0_BASE_IDX 3 15142#define regDPIA_PERF_COUNT_CONTROL1 0x13826 15143#define regDPIA_PERF_COUNT_CONTROL1_BASE_IDX 3 15144#define regDPIA_PERF_COUNT_CONTROL2 0x13827 15145#define regDPIA_PERF_COUNT_CONTROL2_BASE_IDX 3 15146#define regDPIA_PERF_COUNT_CONTROL3 0x13828 15147#define regDPIA_PERF_COUNT_CONTROL3_BASE_IDX 3 15148#define regDPIA_PERF_COUNT_CONTROL4 0x13829 15149#define regDPIA_PERF_COUNT_CONTROL4_BASE_IDX 3 15150#define regDPIA_PERF_COUNT_CONTROL5 0x1382a 15151#define regDPIA_PERF_COUNT_CONTROL5_BASE_IDX 3 15152#define regDPIA_PERF_COUNT_INDEX 0x1382b 15153#define regDPIA_PERF_COUNT_INDEX_BASE_IDX 3 15154#define regDPIA_PERF_COUNT_DATA_LO 0x1382c 15155#define regDPIA_PERF_COUNT_DATA_LO_BASE_IDX 3 15156#define regDPIA_MU_SPARE 0x1382d 15157#define regDPIA_MU_SPARE_BASE_IDX 3 15158 15159 15160// addressBlock: dce_dc_hda_azcontroller_azdec 15161// base address: 0x0 15162#define regAZCONTROLLER1_CORB_WRITE_POINTER 0x0000 15163#define regAZCONTROLLER1_CORB_WRITE_POINTER_BASE_IDX 0 15164#define regAZCONTROLLER1_CORB_READ_POINTER 0x0000 15165#define regAZCONTROLLER1_CORB_READ_POINTER_BASE_IDX 0 15166#define regAZCONTROLLER1_CORB_CONTROL 0x0001 15167#define regAZCONTROLLER1_CORB_CONTROL_BASE_IDX 0 15168#define regAZCONTROLLER1_CORB_STATUS 0x0001 15169#define regAZCONTROLLER1_CORB_STATUS_BASE_IDX 0 15170#define regAZCONTROLLER1_CORB_SIZE 0x0001 15171#define regAZCONTROLLER1_CORB_SIZE_BASE_IDX 0 15172#define regAZCONTROLLER1_RIRB_LOWER_BASE_ADDRESS 0x0002 15173#define regAZCONTROLLER1_RIRB_LOWER_BASE_ADDRESS_BASE_IDX 0 15174#define regAZCONTROLLER1_RIRB_UPPER_BASE_ADDRESS 0x0003 15175#define regAZCONTROLLER1_RIRB_UPPER_BASE_ADDRESS_BASE_IDX 0 15176#define regAZCONTROLLER1_RIRB_WRITE_POINTER 0x0004 15177#define regAZCONTROLLER1_RIRB_WRITE_POINTER_BASE_IDX 0 15178#define regAZCONTROLLER1_RESPONSE_INTERRUPT_COUNT 0x0004 15179#define regAZCONTROLLER1_RESPONSE_INTERRUPT_COUNT_BASE_IDX 0 15180#define regAZCONTROLLER1_RIRB_CONTROL 0x0005 15181#define regAZCONTROLLER1_RIRB_CONTROL_BASE_IDX 0 15182#define regAZCONTROLLER1_RIRB_STATUS 0x0005 15183#define regAZCONTROLLER1_RIRB_STATUS_BASE_IDX 0 15184#define regAZCONTROLLER1_RIRB_SIZE 0x0005 15185#define regAZCONTROLLER1_RIRB_SIZE_BASE_IDX 0 15186#define regAZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE 0x0006 15187#define regAZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_BASE_IDX 0 15188#define regAZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x0006 15189#define regAZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX 0 15190#define regAZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x0006 15191#define regAZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX 0 15192#define regAZCONTROLLER1_IMMEDIATE_RESPONSE_INPUT_INTERFACE 0x0007 15193#define regAZCONTROLLER1_IMMEDIATE_RESPONSE_INPUT_INTERFACE_BASE_IDX 0 15194#define regAZCONTROLLER1_IMMEDIATE_COMMAND_STATUS 0x0008 15195#define regAZCONTROLLER1_IMMEDIATE_COMMAND_STATUS_BASE_IDX 0 15196#define regAZCONTROLLER1_DMA_POSITION_LOWER_BASE_ADDRESS 0x000a 15197#define regAZCONTROLLER1_DMA_POSITION_LOWER_BASE_ADDRESS_BASE_IDX 0 15198#define regAZCONTROLLER1_DMA_POSITION_UPPER_BASE_ADDRESS 0x000b 15199#define regAZCONTROLLER1_DMA_POSITION_UPPER_BASE_ADDRESS_BASE_IDX 0 15200#define regAZCONTROLLER1_WALL_CLOCK_COUNTER_ALIAS 0x074c 15201#define regAZCONTROLLER1_WALL_CLOCK_COUNTER_ALIAS_BASE_IDX 1 15202 15203 15204// addressBlock: dce_dc_hda_azendpoint_azdec 15205// base address: 0x0 15206#define regAZENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x0006 15207#define regAZENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX 0 15208#define regAZENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x0006 15209#define regAZENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX 0 15210 15211 15212// addressBlock: dce_dc_hda_azinputendpoint_azdec 15213// base address: 0x0 15214#define regAZINPUTENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA 0x0006 15215#define regAZINPUTENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA_BASE_IDX 0 15216#define regAZINPUTENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX 0x0006 15217#define regAZINPUTENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX_BASE_IDX 0 15218 15219 15220// addressBlock: dce_dc_dio_dio_dpia_mux0_dispdec 15221// base address: 0x14de0 15222#define regDIO_DPIA_MUX0_DIO_DPIA_MUX_CONTROL 0x1eb8 15223#define regDIO_DPIA_MUX0_DIO_DPIA_MUX_CONTROL_BASE_IDX 2 15224 15225 15226// addressBlock: dce_dc_dio_dio_dpia_mux1_dispdec 15227// base address: 0x14de4 15228#define regDIO_DPIA_MUX1_DIO_DPIA_MUX_CONTROL 0x1eb9 15229#define regDIO_DPIA_MUX1_DIO_DPIA_MUX_CONTROL_BASE_IDX 2 15230 15231 15232// addressBlock: dce_dc_dio_dio_dpia_mux2_dispdec 15233// base address: 0x14de8 15234#define regDIO_DPIA_MUX2_DIO_DPIA_MUX_CONTROL 0x1eba 15235#define regDIO_DPIA_MUX2_DIO_DPIA_MUX_CONTROL_BASE_IDX 2 15236 15237 15238// addressBlock: dce_dc_dio_dio_dpia_mux3_dispdec 15239// base address: 0x14dec 15240#define regDIO_DPIA_MUX3_DIO_DPIA_MUX_CONTROL 0x1ebb 15241#define regDIO_DPIA_MUX3_DIO_DPIA_MUX_CONTROL_BASE_IDX 2 15242 15243 15244// addressBlock: dce_dc_dio_dig_stream_mapper_dispdec 15245// base address: 0x0 15246#define regDIG0_STREAM_MAPPER_CONTROL 0x1f0d 15247#define regDIG0_STREAM_MAPPER_CONTROL_BASE_IDX 2 15248#define regDIG1_STREAM_MAPPER_CONTROL 0x1f0e 15249#define regDIG1_STREAM_MAPPER_CONTROL_BASE_IDX 2 15250#define regDIG2_STREAM_MAPPER_CONTROL 0x1f0f 15251#define regDIG2_STREAM_MAPPER_CONTROL_BASE_IDX 2 15252#define regDIG3_STREAM_MAPPER_CONTROL 0x1f10 15253#define regDIG3_STREAM_MAPPER_CONTROL_BASE_IDX 2 15254#define regDIG4_STREAM_MAPPER_CONTROL 0x1f11 15255#define regDIG4_STREAM_MAPPER_CONTROL_BASE_IDX 2 15256 15257 15258#endif 15259 15260