1/* 2 * Copyright (C) 2020 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included 12 * in all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 20 */ 21#ifndef _dcn_3_1_2_OFFSET_HEADER 22#define _dcn_3_1_2_OFFSET_HEADER 23 24 25 26// addressBlock: dce_dc_hda_azcontroller_azdec 27// base address: 0x1300000 28#define regAZCONTROLLER0_GLOBAL_CAPABILITIES 0x4b7000 29#define regAZCONTROLLER0_GLOBAL_CAPABILITIES_BASE_IDX 3 30#define regAZCONTROLLER0_MINOR_VERSION 0x4b7000 31#define regAZCONTROLLER0_MINOR_VERSION_BASE_IDX 3 32#define regAZCONTROLLER0_MAJOR_VERSION 0x4b7000 33#define regAZCONTROLLER0_MAJOR_VERSION_BASE_IDX 3 34#define regAZCONTROLLER0_OUTPUT_PAYLOAD_CAPABILITY 0x4b7001 35#define regAZCONTROLLER0_OUTPUT_PAYLOAD_CAPABILITY_BASE_IDX 3 36#define regAZCONTROLLER0_INPUT_PAYLOAD_CAPABILITY 0x4b7001 37#define regAZCONTROLLER0_INPUT_PAYLOAD_CAPABILITY_BASE_IDX 3 38#define regAZCONTROLLER0_GLOBAL_CONTROL 0x4b7002 39#define regAZCONTROLLER0_GLOBAL_CONTROL_BASE_IDX 3 40#define regAZCONTROLLER0_WAKE_ENABLE 0x4b7003 41#define regAZCONTROLLER0_WAKE_ENABLE_BASE_IDX 3 42#define regAZCONTROLLER0_STATE_CHANGE_STATUS 0x4b7003 43#define regAZCONTROLLER0_STATE_CHANGE_STATUS_BASE_IDX 3 44#define regAZCONTROLLER0_GLOBAL_STATUS 0x4b7004 45#define regAZCONTROLLER0_GLOBAL_STATUS_BASE_IDX 3 46#define regAZCONTROLLER0_OUTPUT_STREAM_PAYLOAD_CAPABILITY 0x4b7006 47#define regAZCONTROLLER0_OUTPUT_STREAM_PAYLOAD_CAPABILITY_BASE_IDX 3 48#define regAZCONTROLLER0_INPUT_STREAM_PAYLOAD_CAPABILITY 0x4b7006 49#define regAZCONTROLLER0_INPUT_STREAM_PAYLOAD_CAPABILITY_BASE_IDX 3 50#define regAZCONTROLLER0_INTERRUPT_CONTROL 0x4b7008 51#define regAZCONTROLLER0_INTERRUPT_CONTROL_BASE_IDX 3 52#define regAZCONTROLLER0_INTERRUPT_STATUS 0x4b7009 53#define regAZCONTROLLER0_INTERRUPT_STATUS_BASE_IDX 3 54#define regAZCONTROLLER0_WALL_CLOCK_COUNTER 0x4b700c 55#define regAZCONTROLLER0_WALL_CLOCK_COUNTER_BASE_IDX 3 56#define regAZCONTROLLER0_STREAM_SYNCHRONIZATION 0x4b700e 57#define regAZCONTROLLER0_STREAM_SYNCHRONIZATION_BASE_IDX 3 58#define regAZCONTROLLER0_CORB_LOWER_BASE_ADDRESS 0x4b7010 59#define regAZCONTROLLER0_CORB_LOWER_BASE_ADDRESS_BASE_IDX 3 60#define regAZCONTROLLER0_CORB_UPPER_BASE_ADDRESS 0x4b7011 61#define regAZCONTROLLER0_CORB_UPPER_BASE_ADDRESS_BASE_IDX 3 62#define regAZCONTROLLER0_CORB_WRITE_POINTER 0x4b7012 63#define regAZCONTROLLER0_CORB_WRITE_POINTER_BASE_IDX 3 64#define regAZCONTROLLER0_CORB_READ_POINTER 0x4b7012 65#define regAZCONTROLLER0_CORB_READ_POINTER_BASE_IDX 3 66#define regAZCONTROLLER0_CORB_CONTROL 0x4b7013 67#define regAZCONTROLLER0_CORB_CONTROL_BASE_IDX 3 68#define regAZCONTROLLER0_CORB_STATUS 0x4b7013 69#define regAZCONTROLLER0_CORB_STATUS_BASE_IDX 3 70#define regAZCONTROLLER0_CORB_SIZE 0x4b7013 71#define regAZCONTROLLER0_CORB_SIZE_BASE_IDX 3 72#define regAZCONTROLLER0_RIRB_LOWER_BASE_ADDRESS 0x4b7014 73#define regAZCONTROLLER0_RIRB_LOWER_BASE_ADDRESS_BASE_IDX 3 74#define regAZCONTROLLER0_RIRB_UPPER_BASE_ADDRESS 0x4b7015 75#define regAZCONTROLLER0_RIRB_UPPER_BASE_ADDRESS_BASE_IDX 3 76#define regAZCONTROLLER0_RIRB_WRITE_POINTER 0x4b7016 77#define regAZCONTROLLER0_RIRB_WRITE_POINTER_BASE_IDX 3 78#define regAZCONTROLLER0_RESPONSE_INTERRUPT_COUNT 0x4b7016 79#define regAZCONTROLLER0_RESPONSE_INTERRUPT_COUNT_BASE_IDX 3 80#define regAZCONTROLLER0_RIRB_CONTROL 0x4b7017 81#define regAZCONTROLLER0_RIRB_CONTROL_BASE_IDX 3 82#define regAZCONTROLLER0_RIRB_STATUS 0x4b7017 83#define regAZCONTROLLER0_RIRB_STATUS_BASE_IDX 3 84#define regAZCONTROLLER0_RIRB_SIZE 0x4b7017 85#define regAZCONTROLLER0_RIRB_SIZE_BASE_IDX 3 86#define regAZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE 0x4b7018 87#define regAZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_BASE_IDX 3 88#define regAZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x4b7018 89#define regAZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX 3 90#define regAZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x4b7018 91#define regAZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX 3 92#define regAZCONTROLLER0_IMMEDIATE_RESPONSE_INPUT_INTERFACE 0x4b7019 93#define regAZCONTROLLER0_IMMEDIATE_RESPONSE_INPUT_INTERFACE_BASE_IDX 3 94#define regAZCONTROLLER0_IMMEDIATE_COMMAND_STATUS 0x4b701a 95#define regAZCONTROLLER0_IMMEDIATE_COMMAND_STATUS_BASE_IDX 3 96#define regAZCONTROLLER0_DMA_POSITION_LOWER_BASE_ADDRESS 0x4b701c 97#define regAZCONTROLLER0_DMA_POSITION_LOWER_BASE_ADDRESS_BASE_IDX 3 98#define regAZCONTROLLER0_DMA_POSITION_UPPER_BASE_ADDRESS 0x4b701d 99#define regAZCONTROLLER0_DMA_POSITION_UPPER_BASE_ADDRESS_BASE_IDX 3 100#define regAZCONTROLLER0_WALL_CLOCK_COUNTER_ALIAS 0x4b780c 101#define regAZCONTROLLER0_WALL_CLOCK_COUNTER_ALIAS_BASE_IDX 3 102 103 104// addressBlock: dce_dc_hda_azendpoint_azdec 105// base address: 0x1300000 106#define regAZENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x4b7018 107#define regAZENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX 3 108#define regAZENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x4b7018 109#define regAZENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX 3 110 111 112// addressBlock: dce_dc_hda_azinputendpoint_azdec 113// base address: 0x1300000 114#define regAZINPUTENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA 0x4b7018 115#define regAZINPUTENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA_BASE_IDX 3 116#define regAZINPUTENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX 0x4b7018 117#define regAZINPUTENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX_BASE_IDX 3 118 119 120// addressBlock: dce_dc_mmhubbub_vga_dispdec[72..76] 121// base address: 0x48 122#define regVGA_MEM_WRITE_PAGE_ADDR 0x0000 123#define regVGA_MEM_WRITE_PAGE_ADDR_BASE_IDX 0 124#define regVGA_MEM_READ_PAGE_ADDR 0x0001 125#define regVGA_MEM_READ_PAGE_ADDR_BASE_IDX 0 126 127 128// addressBlock: dce_dc_mmhubbub_vga_dispdec[948..986] 129// base address: 0x3b4 130#define regCRTC8_IDX 0x002d 131#define regCRTC8_IDX_BASE_IDX 1 132#define regCRTC8_DATA 0x002d 133#define regCRTC8_DATA_BASE_IDX 1 134#define regGENFC_WT 0x002e 135#define regGENFC_WT_BASE_IDX 1 136#define regGENS1 0x002e 137#define regGENS1_BASE_IDX 1 138#define regATTRDW 0x0030 139#define regATTRDW_BASE_IDX 1 140#define regATTRX 0x0030 141#define regATTRX_BASE_IDX 1 142#define regATTRDR 0x0030 143#define regATTRDR_BASE_IDX 1 144#define regGENMO_WT 0x0030 145#define regGENMO_WT_BASE_IDX 1 146#define regGENS0 0x0030 147#define regGENS0_BASE_IDX 1 148#define regGENENB 0x0030 149#define regSEQ8_IDX 0x0031 150#define regSEQ8_IDX_BASE_IDX 1 151#define regSEQ8_DATA 0x0031 152#define regSEQ8_DATA_BASE_IDX 1 153#define regDAC_MASK 0x0031 154#define regDAC_MASK_BASE_IDX 1 155#define regDAC_R_INDEX 0x0031 156#define regDAC_R_INDEX_BASE_IDX 1 157#define regDAC_W_INDEX 0x0032 158#define regDAC_W_INDEX_BASE_IDX 1 159#define regDAC_DATA 0x0032 160#define regDAC_DATA_BASE_IDX 1 161#define regGENFC_RD 0x0032 162#define regGENFC_RD_BASE_IDX 1 163#define regGENMO_RD 0x0033 164#define regGENMO_RD_BASE_IDX 1 165#define regGRPH8_IDX 0x0033 166#define regGRPH8_IDX_BASE_IDX 1 167#define regGRPH8_DATA 0x0033 168#define regGRPH8_DATA_BASE_IDX 1 169#define regCRTC8_IDX_1 0x0035 170#define regCRTC8_IDX_1_BASE_IDX 1 171#define regCRTC8_DATA_1 0x0035 172#define regCRTC8_DATA_1_BASE_IDX 1 173#define regGENFC_WT_1 0x0036 174#define regGENFC_WT_1_BASE_IDX 1 175#define regGENS1_1 0x0036 176#define regGENS1_1_BASE_IDX 1 177 178 179// addressBlock: dce_dc_hda_azcontroller_azdec 180// base address: 0x0 181#define regAZCONTROLLER1_CORB_WRITE_POINTER 0x0000 182#define regAZCONTROLLER1_CORB_WRITE_POINTER_BASE_IDX 0 183#define regAZCONTROLLER1_CORB_READ_POINTER 0x0000 184#define regAZCONTROLLER1_CORB_READ_POINTER_BASE_IDX 0 185#define regAZCONTROLLER1_CORB_CONTROL 0x0001 186#define regAZCONTROLLER1_CORB_CONTROL_BASE_IDX 0 187#define regAZCONTROLLER1_CORB_STATUS 0x0001 188#define regAZCONTROLLER1_CORB_STATUS_BASE_IDX 0 189#define regAZCONTROLLER1_CORB_SIZE 0x0001 190#define regAZCONTROLLER1_CORB_SIZE_BASE_IDX 0 191#define regAZCONTROLLER1_RIRB_LOWER_BASE_ADDRESS 0x0002 192#define regAZCONTROLLER1_RIRB_LOWER_BASE_ADDRESS_BASE_IDX 0 193#define regAZCONTROLLER1_RIRB_UPPER_BASE_ADDRESS 0x0003 194#define regAZCONTROLLER1_RIRB_UPPER_BASE_ADDRESS_BASE_IDX 0 195#define regAZCONTROLLER1_RIRB_WRITE_POINTER 0x0004 196#define regAZCONTROLLER1_RIRB_WRITE_POINTER_BASE_IDX 0 197#define regAZCONTROLLER1_RESPONSE_INTERRUPT_COUNT 0x0004 198#define regAZCONTROLLER1_RESPONSE_INTERRUPT_COUNT_BASE_IDX 0 199#define regAZCONTROLLER1_RIRB_CONTROL 0x0005 200#define regAZCONTROLLER1_RIRB_CONTROL_BASE_IDX 0 201#define regAZCONTROLLER1_RIRB_STATUS 0x0005 202#define regAZCONTROLLER1_RIRB_STATUS_BASE_IDX 0 203#define regAZCONTROLLER1_RIRB_SIZE 0x0005 204#define regAZCONTROLLER1_RIRB_SIZE_BASE_IDX 0 205#define regAZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE 0x0006 206#define regAZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_BASE_IDX 0 207#define regAZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x0006 208#define regAZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX 0 209#define regAZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x0006 210#define regAZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX 0 211#define regAZCONTROLLER1_IMMEDIATE_RESPONSE_INPUT_INTERFACE 0x0007 212#define regAZCONTROLLER1_IMMEDIATE_RESPONSE_INPUT_INTERFACE_BASE_IDX 0 213#define regAZCONTROLLER1_IMMEDIATE_COMMAND_STATUS 0x0008 214#define regAZCONTROLLER1_IMMEDIATE_COMMAND_STATUS_BASE_IDX 0 215#define regAZCONTROLLER1_DMA_POSITION_LOWER_BASE_ADDRESS 0x000a 216#define regAZCONTROLLER1_DMA_POSITION_LOWER_BASE_ADDRESS_BASE_IDX 0 217#define regAZCONTROLLER1_DMA_POSITION_UPPER_BASE_ADDRESS 0x000b 218#define regAZCONTROLLER1_DMA_POSITION_UPPER_BASE_ADDRESS_BASE_IDX 0 219#define regAZCONTROLLER1_WALL_CLOCK_COUNTER_ALIAS 0x074c 220#define regAZCONTROLLER1_WALL_CLOCK_COUNTER_ALIAS_BASE_IDX 1 221 222 223// addressBlock: dce_dc_hda_azendpoint_azdec 224// base address: 0x0 225#define regAZENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x0006 226#define regAZENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX 0 227#define regAZENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x0006 228#define regAZENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX 0 229 230 231// addressBlock: dce_dc_hda_azinputendpoint_azdec 232// base address: 0x0 233#define regAZINPUTENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA 0x0006 234#define regAZINPUTENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA_BASE_IDX 0 235#define regAZINPUTENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX 0x0006 236#define regAZINPUTENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX_BASE_IDX 0 237 238 239// addressBlock: dce_dc_dccg_dccg_dfs_dispdec 240// base address: 0x0 241#define regDENTIST_DISPCLK_CNTL 0x0064 242#define regDENTIST_DISPCLK_CNTL_BASE_IDX 1 243 244 245// addressBlock: dce_dc_dccg_dccg_dispdec 246// base address: 0x0 247#define regPHYPLLA_PIXCLK_RESYNC_CNTL 0x0040 248#define regPHYPLLA_PIXCLK_RESYNC_CNTL_BASE_IDX 1 249#define regPHYPLLB_PIXCLK_RESYNC_CNTL 0x0041 250#define regPHYPLLB_PIXCLK_RESYNC_CNTL_BASE_IDX 1 251#define regPHYPLLC_PIXCLK_RESYNC_CNTL 0x0042 252#define regPHYPLLC_PIXCLK_RESYNC_CNTL_BASE_IDX 1 253#define regPHYPLLD_PIXCLK_RESYNC_CNTL 0x0043 254#define regPHYPLLD_PIXCLK_RESYNC_CNTL_BASE_IDX 1 255#define regDP_DTO_DBUF_EN 0x0044 256#define regDP_DTO_DBUF_EN_BASE_IDX 1 257#define regDPREFCLK_CGTT_BLK_CTRL_REG 0x0048 258#define regDPREFCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1 259#define regDCCG_GATE_DISABLE_CNTL4 0x0049 260#define regDCCG_GATE_DISABLE_CNTL4_BASE_IDX 1 261#define regDPSTREAMCLK_CNTL 0x004a 262#define regDPSTREAMCLK_CNTL_BASE_IDX 1 263#define regREFCLK_CGTT_BLK_CTRL_REG 0x004b 264#define regREFCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1 265#define regPHYPLLE_PIXCLK_RESYNC_CNTL 0x004c 266#define regPHYPLLE_PIXCLK_RESYNC_CNTL_BASE_IDX 1 267#define regDCCG_PERFMON_CNTL2 0x004e 268#define regDCCG_PERFMON_CNTL2_BASE_IDX 1 269#define regDCCG_DS_DTO_INCR 0x0053 270#define regDCCG_DS_DTO_INCR_BASE_IDX 1 271#define regDCCG_DS_DTO_MODULO 0x0054 272#define regDCCG_DS_DTO_MODULO_BASE_IDX 1 273#define regDCCG_DS_CNTL 0x0055 274#define regDCCG_DS_CNTL_BASE_IDX 1 275#define regDCCG_DS_HW_CAL_INTERVAL 0x0056 276#define regDCCG_DS_HW_CAL_INTERVAL_BASE_IDX 1 277#define regDPREFCLK_CNTL 0x0058 278#define regDPREFCLK_CNTL_BASE_IDX 1 279#define regDCE_VERSION 0x005e 280#define regDCE_VERSION_BASE_IDX 1 281#define regDCCG_GTC_CNTL 0x0060 282#define regDCCG_GTC_CNTL_BASE_IDX 1 283#define regDCCG_GTC_DTO_INCR 0x0061 284#define regDCCG_GTC_DTO_INCR_BASE_IDX 1 285#define regDCCG_GTC_DTO_MODULO 0x0062 286#define regDCCG_GTC_DTO_MODULO_BASE_IDX 1 287#define regDCCG_GTC_CURRENT 0x0063 288#define regDCCG_GTC_CURRENT_BASE_IDX 1 289#define regSYMCLK32_SE_CNTL 0x0065 290#define regSYMCLK32_SE_CNTL_BASE_IDX 1 291#define regSYMCLK32_LE_CNTL 0x0066 292#define regSYMCLK32_LE_CNTL_BASE_IDX 1 293#define regDSCCLK0_DTO_PARAM 0x006c 294#define regDSCCLK0_DTO_PARAM_BASE_IDX 1 295#define regDSCCLK1_DTO_PARAM 0x006d 296#define regDSCCLK1_DTO_PARAM_BASE_IDX 1 297#define regDSCCLK2_DTO_PARAM 0x006e 298#define regDSCCLK2_DTO_PARAM_BASE_IDX 1 299#define regMILLISECOND_TIME_BASE_DIV 0x0070 300#define regMILLISECOND_TIME_BASE_DIV_BASE_IDX 1 301#define regDISPCLK_FREQ_CHANGE_CNTL 0x0071 302#define regDISPCLK_FREQ_CHANGE_CNTL_BASE_IDX 1 303#define regDC_MEM_GLOBAL_PWR_REQ_CNTL 0x0072 304#define regDC_MEM_GLOBAL_PWR_REQ_CNTL_BASE_IDX 1 305#define regDCCG_PERFMON_CNTL 0x0073 306#define regDCCG_PERFMON_CNTL_BASE_IDX 1 307#define regDCCG_GATE_DISABLE_CNTL 0x0074 308#define regDCCG_GATE_DISABLE_CNTL_BASE_IDX 1 309#define regDISPCLK_CGTT_BLK_CTRL_REG 0x0075 310#define regDISPCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1 311#define regSOCCLK_CGTT_BLK_CTRL_REG 0x0076 312#define regSOCCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1 313#define regDCCG_CAC_STATUS 0x0077 314#define regDCCG_CAC_STATUS_BASE_IDX 1 315#define regMICROSECOND_TIME_BASE_DIV 0x007b 316#define regMICROSECOND_TIME_BASE_DIV_BASE_IDX 1 317#define regDCCG_GATE_DISABLE_CNTL2 0x007c 318#define regDCCG_GATE_DISABLE_CNTL2_BASE_IDX 1 319#define regSYMCLK_CGTT_BLK_CTRL_REG 0x007d 320#define regSYMCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1 321#define regDCCG_DISP_CNTL_REG 0x007f 322#define regDCCG_DISP_CNTL_REG_BASE_IDX 1 323#define regOTG0_PIXEL_RATE_CNTL 0x0080 324#define regOTG0_PIXEL_RATE_CNTL_BASE_IDX 1 325#define regDP_DTO0_PHASE 0x0081 326#define regDP_DTO0_PHASE_BASE_IDX 1 327#define regDP_DTO0_MODULO 0x0082 328#define regDP_DTO0_MODULO_BASE_IDX 1 329#define regOTG0_PHYPLL_PIXEL_RATE_CNTL 0x0083 330#define regOTG0_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1 331#define regOTG1_PIXEL_RATE_CNTL 0x0084 332#define regOTG1_PIXEL_RATE_CNTL_BASE_IDX 1 333#define regDP_DTO1_PHASE 0x0085 334#define regDP_DTO1_PHASE_BASE_IDX 1 335#define regDP_DTO1_MODULO 0x0086 336#define regDP_DTO1_MODULO_BASE_IDX 1 337#define regOTG1_PHYPLL_PIXEL_RATE_CNTL 0x0087 338#define regOTG1_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1 339#define regOTG2_PIXEL_RATE_CNTL 0x0088 340#define regOTG2_PIXEL_RATE_CNTL_BASE_IDX 1 341#define regDP_DTO2_PHASE 0x0089 342#define regDP_DTO2_PHASE_BASE_IDX 1 343#define regDP_DTO2_MODULO 0x008a 344#define regDP_DTO2_MODULO_BASE_IDX 1 345#define regOTG2_PHYPLL_PIXEL_RATE_CNTL 0x008b 346#define regOTG2_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1 347#define regOTG3_PIXEL_RATE_CNTL 0x008c 348#define regOTG3_PIXEL_RATE_CNTL_BASE_IDX 1 349#define regDP_DTO3_PHASE 0x008d 350#define regDP_DTO3_PHASE_BASE_IDX 1 351#define regDP_DTO3_MODULO 0x008e 352#define regDP_DTO3_MODULO_BASE_IDX 1 353#define regOTG3_PHYPLL_PIXEL_RATE_CNTL 0x008f 354#define regOTG3_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1 355#define regDPPCLK_CGTT_BLK_CTRL_REG 0x0098 356#define regDPPCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1 357#define regDPPCLK0_DTO_PARAM 0x0099 358#define regDPPCLK0_DTO_PARAM_BASE_IDX 1 359#define regDPPCLK1_DTO_PARAM 0x009a 360#define regDPPCLK1_DTO_PARAM_BASE_IDX 1 361#define regDPPCLK2_DTO_PARAM 0x009b 362#define regDPPCLK2_DTO_PARAM_BASE_IDX 1 363#define regDPPCLK3_DTO_PARAM 0x009c 364#define regDPPCLK3_DTO_PARAM_BASE_IDX 1 365#define regDCCG_CAC_STATUS2 0x009f 366#define regDCCG_CAC_STATUS2_BASE_IDX 1 367#define regSYMCLKA_CLOCK_ENABLE 0x00a0 368#define regSYMCLKA_CLOCK_ENABLE_BASE_IDX 1 369#define regSYMCLKB_CLOCK_ENABLE 0x00a1 370#define regSYMCLKB_CLOCK_ENABLE_BASE_IDX 1 371#define regSYMCLKC_CLOCK_ENABLE 0x00a2 372#define regSYMCLKC_CLOCK_ENABLE_BASE_IDX 1 373#define regSYMCLKD_CLOCK_ENABLE 0x00a3 374#define regSYMCLKD_CLOCK_ENABLE_BASE_IDX 1 375#define regSYMCLKE_CLOCK_ENABLE 0x00a4 376#define regSYMCLKE_CLOCK_ENABLE_BASE_IDX 1 377#define regDCCG_SOFT_RESET 0x00a6 378#define regDCCG_SOFT_RESET_BASE_IDX 1 379#define regDSCCLK_DTO_CTRL 0x00a7 380#define regDSCCLK_DTO_CTRL_BASE_IDX 1 381#define regDCCG_AUDIO_DTO_SOURCE 0x00ab 382#define regDCCG_AUDIO_DTO_SOURCE_BASE_IDX 1 383#define regDCCG_AUDIO_DTO0_PHASE 0x00ac 384#define regDCCG_AUDIO_DTO0_PHASE_BASE_IDX 1 385#define regDCCG_AUDIO_DTO0_MODULE 0x00ad 386#define regDCCG_AUDIO_DTO0_MODULE_BASE_IDX 1 387#define regDCCG_AUDIO_DTO1_PHASE 0x00ae 388#define regDCCG_AUDIO_DTO1_PHASE_BASE_IDX 1 389#define regDCCG_AUDIO_DTO1_MODULE 0x00af 390#define regDCCG_AUDIO_DTO1_MODULE_BASE_IDX 1 391#define regDCCG_VSYNC_OTG0_LATCH_VALUE 0x00b0 392#define regDCCG_VSYNC_OTG0_LATCH_VALUE_BASE_IDX 1 393#define regDCCG_VSYNC_OTG1_LATCH_VALUE 0x00b1 394#define regDCCG_VSYNC_OTG1_LATCH_VALUE_BASE_IDX 1 395#define regDCCG_VSYNC_OTG2_LATCH_VALUE 0x00b2 396#define regDCCG_VSYNC_OTG2_LATCH_VALUE_BASE_IDX 1 397#define regDCCG_VSYNC_OTG3_LATCH_VALUE 0x00b3 398#define regDCCG_VSYNC_OTG3_LATCH_VALUE_BASE_IDX 1 399#define regDCCG_VSYNC_OTG4_LATCH_VALUE 0x00b4 400#define regDCCG_VSYNC_OTG4_LATCH_VALUE_BASE_IDX 1 401#define regDCCG_VSYNC_OTG5_LATCH_VALUE 0x00b5 402#define regDCCG_VSYNC_OTG5_LATCH_VALUE_BASE_IDX 1 403#define regDPPCLK_DTO_CTRL 0x00b6 404#define regDPPCLK_DTO_CTRL_BASE_IDX 1 405#define regDCCG_VSYNC_CNT_CTRL 0x00b8 406#define regDCCG_VSYNC_CNT_CTRL_BASE_IDX 1 407#define regDCCG_VSYNC_CNT_INT_CTRL 0x00b9 408#define regDCCG_VSYNC_CNT_INT_CTRL_BASE_IDX 1 409#define regFORCE_SYMCLK_DISABLE 0x00ba 410#define regFORCE_SYMCLK_DISABLE_BASE_IDX 1 411#define regDTBCLK_DTO0_PHASE 0x0018 412#define regDTBCLK_DTO0_PHASE_BASE_IDX 2 413#define regDTBCLK_DTO1_PHASE 0x0019 414#define regDTBCLK_DTO1_PHASE_BASE_IDX 2 415#define regDTBCLK_DTO2_PHASE 0x001a 416#define regDTBCLK_DTO2_PHASE_BASE_IDX 2 417#define regDTBCLK_DTO3_PHASE 0x001b 418#define regDTBCLK_DTO3_PHASE_BASE_IDX 2 419#define regDTBCLK_DTO0_MODULO 0x001f 420#define regDTBCLK_DTO0_MODULO_BASE_IDX 2 421#define regDTBCLK_DTO1_MODULO 0x0020 422#define regDTBCLK_DTO1_MODULO_BASE_IDX 2 423#define regDTBCLK_DTO2_MODULO 0x0021 424#define regDTBCLK_DTO2_MODULO_BASE_IDX 2 425#define regDTBCLK_DTO3_MODULO 0x0022 426#define regDTBCLK_DTO3_MODULO_BASE_IDX 2 427#define regPHYASYMCLK_CLOCK_CNTL 0x0052 428#define regPHYASYMCLK_CLOCK_CNTL_BASE_IDX 2 429#define regPHYBSYMCLK_CLOCK_CNTL 0x0053 430#define regPHYBSYMCLK_CLOCK_CNTL_BASE_IDX 2 431#define regPHYCSYMCLK_CLOCK_CNTL 0x0054 432#define regPHYCSYMCLK_CLOCK_CNTL_BASE_IDX 2 433#define regPHYDSYMCLK_CLOCK_CNTL 0x0055 434#define regPHYDSYMCLK_CLOCK_CNTL_BASE_IDX 2 435#define regPHYESYMCLK_CLOCK_CNTL 0x0056 436#define regPHYESYMCLK_CLOCK_CNTL_BASE_IDX 2 437#define regDCCG_GATE_DISABLE_CNTL3 0x005a 438#define regDCCG_GATE_DISABLE_CNTL3_BASE_IDX 2 439#define regHDMISTREAMCLK0_DTO_PARAM 0x005b 440#define regHDMISTREAMCLK0_DTO_PARAM_BASE_IDX 2 441#define regDCCG_AUDIO_DTBCLK_DTO_PHASE 0x0061 442#define regDCCG_AUDIO_DTBCLK_DTO_PHASE_BASE_IDX 2 443#define regDCCG_AUDIO_DTBCLK_DTO_MODULO 0x0062 444#define regDCCG_AUDIO_DTBCLK_DTO_MODULO_BASE_IDX 2 445#define regDTBCLK_DTO_DBUF_EN 0x0063 446#define regDTBCLK_DTO_DBUF_EN_BASE_IDX 2 447 448 449// addressBlock: dce_dc_dccg_dccg_dcperfmon0_dc_perfmon_dispdec 450// base address: 0x0 451#define regDC_PERFMON0_PERFCOUNTER_CNTL 0x0000 452#define regDC_PERFMON0_PERFCOUNTER_CNTL_BASE_IDX 2 453#define regDC_PERFMON0_PERFCOUNTER_CNTL2 0x0001 454#define regDC_PERFMON0_PERFCOUNTER_CNTL2_BASE_IDX 2 455#define regDC_PERFMON0_PERFCOUNTER_STATE 0x0002 456#define regDC_PERFMON0_PERFCOUNTER_STATE_BASE_IDX 2 457#define regDC_PERFMON0_PERFMON_CNTL 0x0003 458#define regDC_PERFMON0_PERFMON_CNTL_BASE_IDX 2 459#define regDC_PERFMON0_PERFMON_CNTL2 0x0004 460#define regDC_PERFMON0_PERFMON_CNTL2_BASE_IDX 2 461#define regDC_PERFMON0_PERFMON_CVALUE_INT_MISC 0x0005 462#define regDC_PERFMON0_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 463#define regDC_PERFMON0_PERFMON_CVALUE_LOW 0x0006 464#define regDC_PERFMON0_PERFMON_CVALUE_LOW_BASE_IDX 2 465#define regDC_PERFMON0_PERFMON_HI 0x0007 466#define regDC_PERFMON0_PERFMON_HI_BASE_IDX 2 467#define regDC_PERFMON0_PERFMON_LOW 0x0008 468#define regDC_PERFMON0_PERFMON_LOW_BASE_IDX 2 469 470 471// addressBlock: dce_dc_dccg_dccg_dcperfmon1_dc_perfmon_dispdec 472// base address: 0x30 473#define regDC_PERFMON1_PERFCOUNTER_CNTL 0x000c 474#define regDC_PERFMON1_PERFCOUNTER_CNTL_BASE_IDX 2 475#define regDC_PERFMON1_PERFCOUNTER_CNTL2 0x000d 476#define regDC_PERFMON1_PERFCOUNTER_CNTL2_BASE_IDX 2 477#define regDC_PERFMON1_PERFCOUNTER_STATE 0x000e 478#define regDC_PERFMON1_PERFCOUNTER_STATE_BASE_IDX 2 479#define regDC_PERFMON1_PERFMON_CNTL 0x000f 480#define regDC_PERFMON1_PERFMON_CNTL_BASE_IDX 2 481#define regDC_PERFMON1_PERFMON_CNTL2 0x0010 482#define regDC_PERFMON1_PERFMON_CNTL2_BASE_IDX 2 483#define regDC_PERFMON1_PERFMON_CVALUE_INT_MISC 0x0011 484#define regDC_PERFMON1_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 485#define regDC_PERFMON1_PERFMON_CVALUE_LOW 0x0012 486#define regDC_PERFMON1_PERFMON_CVALUE_LOW_BASE_IDX 2 487#define regDC_PERFMON1_PERFMON_HI 0x0013 488#define regDC_PERFMON1_PERFMON_HI_BASE_IDX 2 489#define regDC_PERFMON1_PERFMON_LOW 0x0014 490#define regDC_PERFMON1_PERFMON_LOW_BASE_IDX 2 491 492 493// addressBlock: dce_dc_dmu_dmcu_dispdec 494// base address: 0x0 495#define regDMCU_CTRL 0x00da 496#define regDMCU_CTRL_BASE_IDX 2 497#define regDMCU_STATUS 0x00db 498#define regDMCU_STATUS_BASE_IDX 2 499#define regDMCU_PC_START_ADDR 0x00dc 500#define regDMCU_PC_START_ADDR_BASE_IDX 2 501#define regDMCU_FW_START_ADDR 0x00dd 502#define regDMCU_FW_START_ADDR_BASE_IDX 2 503#define regDMCU_FW_END_ADDR 0x00de 504#define regDMCU_FW_END_ADDR_BASE_IDX 2 505#define regDMCU_FW_ISR_START_ADDR 0x00df 506#define regDMCU_FW_ISR_START_ADDR_BASE_IDX 2 507#define regDMCU_FW_CS_HI 0x00e0 508#define regDMCU_FW_CS_HI_BASE_IDX 2 509#define regDMCU_FW_CS_LO 0x00e1 510#define regDMCU_FW_CS_LO_BASE_IDX 2 511#define regDMCU_RAM_ACCESS_CTRL 0x00e2 512#define regDMCU_RAM_ACCESS_CTRL_BASE_IDX 2 513#define regDMCU_ERAM_WR_CTRL 0x00e3 514#define regDMCU_ERAM_WR_CTRL_BASE_IDX 2 515#define regDMCU_ERAM_WR_DATA 0x00e4 516#define regDMCU_ERAM_WR_DATA_BASE_IDX 2 517#define regDMCU_ERAM_RD_CTRL 0x00e5 518#define regDMCU_ERAM_RD_CTRL_BASE_IDX 2 519#define regDMCU_ERAM_RD_DATA 0x00e6 520#define regDMCU_ERAM_RD_DATA_BASE_IDX 2 521#define regDMCU_IRAM_WR_CTRL 0x00e7 522#define regDMCU_IRAM_WR_CTRL_BASE_IDX 2 523#define regDMCU_IRAM_WR_DATA 0x00e8 524#define regDMCU_IRAM_WR_DATA_BASE_IDX 2 525#define regDMCU_IRAM_RD_CTRL 0x00e9 526#define regDMCU_IRAM_RD_CTRL_BASE_IDX 2 527#define regDMCU_IRAM_RD_DATA 0x00ea 528#define regDMCU_IRAM_RD_DATA_BASE_IDX 2 529#define regDMCU_EVENT_TRIGGER 0x00eb 530#define regDMCU_EVENT_TRIGGER_BASE_IDX 2 531#define regDMCU_UC_INTERNAL_INT_STATUS 0x00ec 532#define regDMCU_UC_INTERNAL_INT_STATUS_BASE_IDX 2 533#define regDMCU_SS_INTERRUPT_CNTL_STATUS 0x00ed 534#define regDMCU_SS_INTERRUPT_CNTL_STATUS_BASE_IDX 2 535#define regDMCU_INTERRUPT_STATUS 0x00ee 536#define regDMCU_INTERRUPT_STATUS_BASE_IDX 2 537#define regDMCU_INTERRUPT_STATUS_1 0x00ef 538#define regDMCU_INTERRUPT_STATUS_1_BASE_IDX 2 539#define regDMCU_INTERRUPT_TO_HOST_EN_MASK 0x00f0 540#define regDMCU_INTERRUPT_TO_HOST_EN_MASK_BASE_IDX 2 541#define regDMCU_INTERRUPT_TO_UC_EN_MASK 0x00f1 542#define regDMCU_INTERRUPT_TO_UC_EN_MASK_BASE_IDX 2 543#define regDMCU_INTERRUPT_TO_UC_EN_MASK_1 0x00f2 544#define regDMCU_INTERRUPT_TO_UC_EN_MASK_1_BASE_IDX 2 545#define regDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL 0x00f3 546#define regDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_BASE_IDX 2 547#define regDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1 0x00f4 548#define regDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1_BASE_IDX 2 549#define regDC_DMCU_SCRATCH 0x00f5 550#define regDC_DMCU_SCRATCH_BASE_IDX 2 551#define regDMCU_INT_CNT 0x00f6 552#define regDMCU_INT_CNT_BASE_IDX 2 553#define regDMCU_FW_CHECKSUM_SMPL_BYTE_POS 0x00f7 554#define regDMCU_FW_CHECKSUM_SMPL_BYTE_POS_BASE_IDX 2 555#define regDMCU_UC_CLK_GATING_CNTL 0x00f8 556#define regDMCU_UC_CLK_GATING_CNTL_BASE_IDX 2 557#define regMASTER_COMM_DATA_REG1 0x00f9 558#define regMASTER_COMM_DATA_REG1_BASE_IDX 2 559#define regMASTER_COMM_DATA_REG2 0x00fa 560#define regMASTER_COMM_DATA_REG2_BASE_IDX 2 561#define regMASTER_COMM_DATA_REG3 0x00fb 562#define regMASTER_COMM_DATA_REG3_BASE_IDX 2 563#define regMASTER_COMM_CMD_REG 0x00fc 564#define regMASTER_COMM_CMD_REG_BASE_IDX 2 565#define regMASTER_COMM_CNTL_REG 0x00fd 566#define regMASTER_COMM_CNTL_REG_BASE_IDX 2 567#define regSLAVE_COMM_DATA_REG1 0x00fe 568#define regSLAVE_COMM_DATA_REG1_BASE_IDX 2 569#define regSLAVE_COMM_DATA_REG2 0x00ff 570#define regSLAVE_COMM_DATA_REG2_BASE_IDX 2 571#define regSLAVE_COMM_DATA_REG3 0x0100 572#define regSLAVE_COMM_DATA_REG3_BASE_IDX 2 573#define regSLAVE_COMM_CMD_REG 0x0101 574#define regSLAVE_COMM_CMD_REG_BASE_IDX 2 575#define regSLAVE_COMM_CNTL_REG 0x0102 576#define regSLAVE_COMM_CNTL_REG_BASE_IDX 2 577#define regDMCU_PERFMON_INTERRUPT_STATUS1 0x0105 578#define regDMCU_PERFMON_INTERRUPT_STATUS1_BASE_IDX 2 579#define regDMCU_PERFMON_INTERRUPT_STATUS2 0x0106 580#define regDMCU_PERFMON_INTERRUPT_STATUS2_BASE_IDX 2 581#define regDMCU_PERFMON_INTERRUPT_STATUS3 0x0107 582#define regDMCU_PERFMON_INTERRUPT_STATUS3_BASE_IDX 2 583#define regDMCU_PERFMON_INTERRUPT_STATUS4 0x0108 584#define regDMCU_PERFMON_INTERRUPT_STATUS4_BASE_IDX 2 585#define regDMCU_PERFMON_INTERRUPT_STATUS5 0x0109 586#define regDMCU_PERFMON_INTERRUPT_STATUS5_BASE_IDX 2 587#define regDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1 0x010a 588#define regDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1_BASE_IDX 2 589#define regDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2 0x010b 590#define regDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2_BASE_IDX 2 591#define regDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3 0x010c 592#define regDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3_BASE_IDX 2 593#define regDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4 0x010d 594#define regDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4_BASE_IDX 2 595#define regDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5 0x010e 596#define regDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5_BASE_IDX 2 597#define regDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1 0x010f 598#define regDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1_BASE_IDX 2 599#define regDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2 0x0110 600#define regDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2_BASE_IDX 2 601#define regDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3 0x0111 602#define regDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3_BASE_IDX 2 603#define regDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4 0x0112 604#define regDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4_BASE_IDX 2 605#define regDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5 0x0113 606#define regDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5_BASE_IDX 2 607#define regDMCU_DPRX_INTERRUPT_STATUS1 0x0114 608#define regDMCU_DPRX_INTERRUPT_STATUS1_BASE_IDX 2 609#define regDMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1 0x0115 610#define regDMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1_BASE_IDX 2 611#define regDMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1 0x0116 612#define regDMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1_BASE_IDX 2 613#define regDMCU_INTERRUPT_STATUS_CONTINUE 0x0119 614#define regDMCU_INTERRUPT_STATUS_CONTINUE_BASE_IDX 2 615#define regDMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE 0x011a 616#define regDMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE_BASE_IDX 2 617#define regDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE 0x011b 618#define regDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE_BASE_IDX 2 619#define regDMCU_INT_CNT_CONTINUE 0x011c 620#define regDMCU_INT_CNT_CONTINUE_BASE_IDX 2 621#define regDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2 0x011d 622#define regDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2_BASE_IDX 2 623#define regDMCU_INTERRUPT_STATUS_2 0x011e 624#define regDMCU_INTERRUPT_STATUS_2_BASE_IDX 2 625#define regDMCU_INTERRUPT_TO_UC_EN_MASK_2 0x011f 626#define regDMCU_INTERRUPT_TO_UC_EN_MASK_2_BASE_IDX 2 627#define regDMCU_INT_CNT_CONT2 0x0120 628#define regDMCU_INT_CNT_CONT2_BASE_IDX 2 629#define regDMCU_INT_CNT_CONT3 0x0121 630#define regDMCU_INT_CNT_CONT3_BASE_IDX 2 631 632 633// addressBlock: dce_dc_dmu_fgsec_dispdec 634// base address: 0x0 635#define regDMCUB_RBBMIF_SEC_CNTL 0x017a 636#define regDMCUB_RBBMIF_SEC_CNTL_BASE_IDX 2 637 638 639// addressBlock: dce_dc_dmu_rbbmif_dispdec 640// base address: 0x0 641#define regRBBMIF_TIMEOUT 0x017f 642#define regRBBMIF_TIMEOUT_BASE_IDX 2 643#define regRBBMIF_STATUS 0x0180 644#define regRBBMIF_STATUS_BASE_IDX 2 645#define regRBBMIF_STATUS_2 0x0181 646#define regRBBMIF_STATUS_2_BASE_IDX 2 647#define regRBBMIF_INT_STATUS 0x0182 648#define regRBBMIF_INT_STATUS_BASE_IDX 2 649#define regRBBMIF_TIMEOUT_DIS 0x0183 650#define regRBBMIF_TIMEOUT_DIS_BASE_IDX 2 651#define regRBBMIF_TIMEOUT_DIS_2 0x0184 652#define regRBBMIF_TIMEOUT_DIS_2_BASE_IDX 2 653#define regRBBMIF_STATUS_FLAG 0x0185 654#define regRBBMIF_STATUS_FLAG_BASE_IDX 2 655 656 657// addressBlock: dce_dc_dmu_dmu_dcperfmon_dc_perfmon_dispdec 658// base address: 0x2f8 659#define regDC_PERFMON2_PERFCOUNTER_CNTL 0x00be 660#define regDC_PERFMON2_PERFCOUNTER_CNTL_BASE_IDX 2 661#define regDC_PERFMON2_PERFCOUNTER_CNTL2 0x00bf 662#define regDC_PERFMON2_PERFCOUNTER_CNTL2_BASE_IDX 2 663#define regDC_PERFMON2_PERFCOUNTER_STATE 0x00c0 664#define regDC_PERFMON2_PERFCOUNTER_STATE_BASE_IDX 2 665#define regDC_PERFMON2_PERFMON_CNTL 0x00c1 666#define regDC_PERFMON2_PERFMON_CNTL_BASE_IDX 2 667#define regDC_PERFMON2_PERFMON_CNTL2 0x00c2 668#define regDC_PERFMON2_PERFMON_CNTL2_BASE_IDX 2 669#define regDC_PERFMON2_PERFMON_CVALUE_INT_MISC 0x00c3 670#define regDC_PERFMON2_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 671#define regDC_PERFMON2_PERFMON_CVALUE_LOW 0x00c4 672#define regDC_PERFMON2_PERFMON_CVALUE_LOW_BASE_IDX 2 673#define regDC_PERFMON2_PERFMON_HI 0x00c5 674#define regDC_PERFMON2_PERFMON_HI_BASE_IDX 2 675#define regDC_PERFMON2_PERFMON_LOW 0x00c6 676#define regDC_PERFMON2_PERFMON_LOW_BASE_IDX 2 677 678 679// addressBlock: dce_dc_dmu_ihc_dispdec 680// base address: 0x0 681#define regDC_GPU_TIMER_START_POSITION_V_UPDATE 0x0126 682#define regDC_GPU_TIMER_START_POSITION_V_UPDATE_BASE_IDX 2 683#define regDC_GPU_TIMER_START_POSITION_VSTARTUP 0x0127 684#define regDC_GPU_TIMER_START_POSITION_VSTARTUP_BASE_IDX 2 685#define regDC_GPU_TIMER_READ 0x0128 686#define regDC_GPU_TIMER_READ_BASE_IDX 2 687#define regDC_GPU_TIMER_READ_CNTL 0x0129 688#define regDC_GPU_TIMER_READ_CNTL_BASE_IDX 2 689#define regDISP_INTERRUPT_STATUS 0x012a 690#define regDISP_INTERRUPT_STATUS_BASE_IDX 2 691#define regDISP_INTERRUPT_STATUS_CONTINUE 0x012b 692#define regDISP_INTERRUPT_STATUS_CONTINUE_BASE_IDX 2 693#define regDISP_INTERRUPT_STATUS_CONTINUE2 0x012c 694#define regDISP_INTERRUPT_STATUS_CONTINUE2_BASE_IDX 2 695#define regDISP_INTERRUPT_STATUS_CONTINUE3 0x012d 696#define regDISP_INTERRUPT_STATUS_CONTINUE3_BASE_IDX 2 697#define regDISP_INTERRUPT_STATUS_CONTINUE4 0x012e 698#define regDISP_INTERRUPT_STATUS_CONTINUE4_BASE_IDX 2 699#define regDISP_INTERRUPT_STATUS_CONTINUE5 0x012f 700#define regDISP_INTERRUPT_STATUS_CONTINUE5_BASE_IDX 2 701#define regDISP_INTERRUPT_STATUS_CONTINUE6 0x0130 702#define regDISP_INTERRUPT_STATUS_CONTINUE6_BASE_IDX 2 703#define regDISP_INTERRUPT_STATUS_CONTINUE7 0x0131 704#define regDISP_INTERRUPT_STATUS_CONTINUE7_BASE_IDX 2 705#define regDISP_INTERRUPT_STATUS_CONTINUE8 0x0132 706#define regDISP_INTERRUPT_STATUS_CONTINUE8_BASE_IDX 2 707#define regDISP_INTERRUPT_STATUS_CONTINUE9 0x0133 708#define regDISP_INTERRUPT_STATUS_CONTINUE9_BASE_IDX 2 709#define regDISP_INTERRUPT_STATUS_CONTINUE10 0x0134 710#define regDISP_INTERRUPT_STATUS_CONTINUE10_BASE_IDX 2 711#define regDISP_INTERRUPT_STATUS_CONTINUE11 0x0135 712#define regDISP_INTERRUPT_STATUS_CONTINUE11_BASE_IDX 2 713#define regDISP_INTERRUPT_STATUS_CONTINUE12 0x0136 714#define regDISP_INTERRUPT_STATUS_CONTINUE12_BASE_IDX 2 715#define regDISP_INTERRUPT_STATUS_CONTINUE13 0x0137 716#define regDISP_INTERRUPT_STATUS_CONTINUE13_BASE_IDX 2 717#define regDISP_INTERRUPT_STATUS_CONTINUE14 0x0138 718#define regDISP_INTERRUPT_STATUS_CONTINUE14_BASE_IDX 2 719#define regDISP_INTERRUPT_STATUS_CONTINUE15 0x0139 720#define regDISP_INTERRUPT_STATUS_CONTINUE15_BASE_IDX 2 721#define regDISP_INTERRUPT_STATUS_CONTINUE16 0x013a 722#define regDISP_INTERRUPT_STATUS_CONTINUE16_BASE_IDX 2 723#define regDISP_INTERRUPT_STATUS_CONTINUE17 0x013b 724#define regDISP_INTERRUPT_STATUS_CONTINUE17_BASE_IDX 2 725#define regDISP_INTERRUPT_STATUS_CONTINUE18 0x013c 726#define regDISP_INTERRUPT_STATUS_CONTINUE18_BASE_IDX 2 727#define regDISP_INTERRUPT_STATUS_CONTINUE19 0x013d 728#define regDISP_INTERRUPT_STATUS_CONTINUE19_BASE_IDX 2 729#define regDISP_INTERRUPT_STATUS_CONTINUE20 0x013e 730#define regDISP_INTERRUPT_STATUS_CONTINUE20_BASE_IDX 2 731#define regDISP_INTERRUPT_STATUS_CONTINUE21 0x013f 732#define regDISP_INTERRUPT_STATUS_CONTINUE21_BASE_IDX 2 733#define regDISP_INTERRUPT_STATUS_CONTINUE22 0x0140 734#define regDISP_INTERRUPT_STATUS_CONTINUE22_BASE_IDX 2 735#define regDC_GPU_TIMER_START_POSITION_VREADY 0x0141 736#define regDC_GPU_TIMER_START_POSITION_VREADY_BASE_IDX 2 737#define regDC_GPU_TIMER_START_POSITION_FLIP 0x0142 738#define regDC_GPU_TIMER_START_POSITION_FLIP_BASE_IDX 2 739#define regDC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK 0x0143 740#define regDC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK_BASE_IDX 2 741#define regDC_GPU_TIMER_START_POSITION_FLIP_AWAY 0x0144 742#define regDC_GPU_TIMER_START_POSITION_FLIP_AWAY_BASE_IDX 2 743#define regDISP_INTERRUPT_STATUS_CONTINUE23 0x0145 744#define regDISP_INTERRUPT_STATUS_CONTINUE23_BASE_IDX 2 745#define regDISP_INTERRUPT_STATUS_CONTINUE24 0x0146 746#define regDISP_INTERRUPT_STATUS_CONTINUE24_BASE_IDX 2 747#define regDISP_INTERRUPT_STATUS_CONTINUE25 0x0147 748#define regDISP_INTERRUPT_STATUS_CONTINUE25_BASE_IDX 2 749#define regDCCG_INTERRUPT_DEST 0x0148 750#define regDCCG_INTERRUPT_DEST_BASE_IDX 2 751#define regDMU_INTERRUPT_DEST 0x0149 752#define regDMU_INTERRUPT_DEST_BASE_IDX 2 753#define regDMU_INTERRUPT_DEST2 0x014a 754#define regDMU_INTERRUPT_DEST2_BASE_IDX 2 755#define regDCPG_INTERRUPT_DEST 0x014b 756#define regDCPG_INTERRUPT_DEST_BASE_IDX 2 757#define regDCPG_INTERRUPT_DEST2 0x014c 758#define regDCPG_INTERRUPT_DEST2_BASE_IDX 2 759#define regMMHUBBUB_INTERRUPT_DEST 0x014d 760#define regMMHUBBUB_INTERRUPT_DEST_BASE_IDX 2 761#define regWB_INTERRUPT_DEST 0x014e 762#define regWB_INTERRUPT_DEST_BASE_IDX 2 763#define regDCHUB_INTERRUPT_DEST 0x014f 764#define regDCHUB_INTERRUPT_DEST_BASE_IDX 2 765#define regDCHUB_PERFCOUNTER_INTERRUPT_DEST 0x0150 766#define regDCHUB_PERFCOUNTER_INTERRUPT_DEST_BASE_IDX 2 767#define regDCHUB_INTERRUPT_DEST2 0x0151 768#define regDCHUB_INTERRUPT_DEST2_BASE_IDX 2 769#define regDPP_PERFCOUNTER_INTERRUPT_DEST 0x0152 770#define regDPP_PERFCOUNTER_INTERRUPT_DEST_BASE_IDX 2 771#define regMPC_INTERRUPT_DEST 0x0153 772#define regMPC_INTERRUPT_DEST_BASE_IDX 2 773#define regOPP_INTERRUPT_DEST 0x0154 774#define regOPP_INTERRUPT_DEST_BASE_IDX 2 775#define regOPTC_INTERRUPT_DEST 0x0155 776#define regOPTC_INTERRUPT_DEST_BASE_IDX 2 777#define regOTG0_INTERRUPT_DEST 0x0156 778#define regOTG0_INTERRUPT_DEST_BASE_IDX 2 779#define regOTG1_INTERRUPT_DEST 0x0157 780#define regOTG1_INTERRUPT_DEST_BASE_IDX 2 781#define regOTG2_INTERRUPT_DEST 0x0158 782#define regOTG2_INTERRUPT_DEST_BASE_IDX 2 783#define regOTG3_INTERRUPT_DEST 0x0159 784#define regOTG3_INTERRUPT_DEST_BASE_IDX 2 785#define regOTG4_INTERRUPT_DEST 0x015a 786#define regOTG4_INTERRUPT_DEST_BASE_IDX 2 787#define regOTG5_INTERRUPT_DEST 0x015b 788#define regOTG5_INTERRUPT_DEST_BASE_IDX 2 789#define regDIG_INTERRUPT_DEST 0x015c 790#define regDIG_INTERRUPT_DEST_BASE_IDX 2 791#define regI2C_DDC_HPD_INTERRUPT_DEST 0x015d 792#define regI2C_DDC_HPD_INTERRUPT_DEST_BASE_IDX 2 793#define regDIO_INTERRUPT_DEST 0x015f 794#define regDIO_INTERRUPT_DEST_BASE_IDX 2 795#define regDCIO_INTERRUPT_DEST 0x0160 796#define regDCIO_INTERRUPT_DEST_BASE_IDX 2 797#define regHPD_INTERRUPT_DEST 0x0161 798#define regHPD_INTERRUPT_DEST_BASE_IDX 2 799#define regAZ_INTERRUPT_DEST 0x0162 800#define regAZ_INTERRUPT_DEST_BASE_IDX 2 801#define regAUX_INTERRUPT_DEST 0x0163 802#define regAUX_INTERRUPT_DEST_BASE_IDX 2 803#define regDSC_INTERRUPT_DEST 0x0164 804#define regDSC_INTERRUPT_DEST_BASE_IDX 2 805#define regHPO_INTERRUPT_DEST 0x0165 806#define regHPO_INTERRUPT_DEST_BASE_IDX 2 807 808 809// addressBlock: dce_dc_dmu_dmu_misc_dispdec 810// base address: 0x0 811#define regCC_DC_PIPE_DIS 0x00ca 812#define regCC_DC_PIPE_DIS_BASE_IDX 2 813#define regDMU_CLK_CNTL 0x00cb 814#define regDMU_CLK_CNTL_BASE_IDX 2 815#define regDMU_MEM_PWR_CNTL 0x00cc 816#define regDMU_MEM_PWR_CNTL_BASE_IDX 2 817#define regDMCU_SMU_INTERRUPT_CNTL 0x00cd 818#define regDMCU_SMU_INTERRUPT_CNTL_BASE_IDX 2 819#define regSMU_INTERRUPT_CONTROL 0x00ce 820#define regSMU_INTERRUPT_CONTROL_BASE_IDX 2 821#define regZSC_CNTL 0x00cf 822#define regZSC_CNTL_BASE_IDX 2 823#define regZSC_CNTL2 0x00d0 824#define regZSC_CNTL2_BASE_IDX 2 825#define regDMU_MISC_ALLOW_DS_FORCE 0x00d6 826#define regDMU_MISC_ALLOW_DS_FORCE_BASE_IDX 2 827#define regZSC_STATUS 0x00d7 828#define regZSC_STATUS_BASE_IDX 2 829 830 831// addressBlock: dce_dc_dmu_dc_pg_dispdec 832// base address: 0x0 833#define regDOMAIN0_PG_CONFIG 0x0080 834#define regDOMAIN0_PG_CONFIG_BASE_IDX 2 835#define regDOMAIN0_PG_STATUS 0x0081 836#define regDOMAIN0_PG_STATUS_BASE_IDX 2 837#define regDOMAIN1_PG_CONFIG 0x0082 838#define regDOMAIN1_PG_CONFIG_BASE_IDX 2 839#define regDOMAIN1_PG_STATUS 0x0083 840#define regDOMAIN1_PG_STATUS_BASE_IDX 2 841#define regDOMAIN2_PG_CONFIG 0x0084 842#define regDOMAIN2_PG_CONFIG_BASE_IDX 2 843#define regDOMAIN2_PG_STATUS 0x0085 844#define regDOMAIN2_PG_STATUS_BASE_IDX 2 845#define regDOMAIN3_PG_CONFIG 0x0086 846#define regDOMAIN3_PG_CONFIG_BASE_IDX 2 847#define regDOMAIN3_PG_STATUS 0x0087 848#define regDOMAIN3_PG_STATUS_BASE_IDX 2 849#define regDOMAIN16_PG_CONFIG 0x0089 850#define regDOMAIN16_PG_CONFIG_BASE_IDX 2 851#define regDOMAIN16_PG_STATUS 0x008a 852#define regDOMAIN16_PG_STATUS_BASE_IDX 2 853#define regDOMAIN17_PG_CONFIG 0x008b 854#define regDOMAIN17_PG_CONFIG_BASE_IDX 2 855#define regDOMAIN17_PG_STATUS 0x008c 856#define regDOMAIN17_PG_STATUS_BASE_IDX 2 857#define regDOMAIN18_PG_CONFIG 0x008d 858#define regDOMAIN18_PG_CONFIG_BASE_IDX 2 859#define regDOMAIN18_PG_STATUS 0x008e 860#define regDOMAIN18_PG_STATUS_BASE_IDX 2 861#define regDCPG_INTERRUPT_STATUS 0x008f 862#define regDCPG_INTERRUPT_STATUS_BASE_IDX 2 863#define regDCPG_INTERRUPT_STATUS_2 0x0090 864#define regDCPG_INTERRUPT_STATUS_2_BASE_IDX 2 865#define regDCPG_INTERRUPT_CONTROL_1 0x0091 866#define regDCPG_INTERRUPT_CONTROL_1_BASE_IDX 2 867#define regDCPG_INTERRUPT_CONTROL_3 0x0092 868#define regDCPG_INTERRUPT_CONTROL_3_BASE_IDX 2 869#define regDC_IP_REQUEST_CNTL 0x0093 870#define regDC_IP_REQUEST_CNTL_BASE_IDX 2 871 872 873// addressBlock: dce_dc_dmu_dmcub_dispdec 874// base address: 0x0 875#define regDMCUB_REGION0_OFFSET 0x018e 876#define regDMCUB_REGION0_OFFSET_BASE_IDX 2 877#define regDMCUB_REGION0_OFFSET_HIGH 0x018f 878#define regDMCUB_REGION0_OFFSET_HIGH_BASE_IDX 2 879#define regDMCUB_REGION1_OFFSET 0x0190 880#define regDMCUB_REGION1_OFFSET_BASE_IDX 2 881#define regDMCUB_REGION1_OFFSET_HIGH 0x0191 882#define regDMCUB_REGION1_OFFSET_HIGH_BASE_IDX 2 883#define regDMCUB_REGION2_OFFSET 0x0192 884#define regDMCUB_REGION2_OFFSET_BASE_IDX 2 885#define regDMCUB_REGION2_OFFSET_HIGH 0x0193 886#define regDMCUB_REGION2_OFFSET_HIGH_BASE_IDX 2 887#define regDMCUB_REGION4_OFFSET 0x0196 888#define regDMCUB_REGION4_OFFSET_BASE_IDX 2 889#define regDMCUB_REGION4_OFFSET_HIGH 0x0197 890#define regDMCUB_REGION4_OFFSET_HIGH_BASE_IDX 2 891#define regDMCUB_REGION5_OFFSET 0x0198 892#define regDMCUB_REGION5_OFFSET_BASE_IDX 2 893#define regDMCUB_REGION5_OFFSET_HIGH 0x0199 894#define regDMCUB_REGION5_OFFSET_HIGH_BASE_IDX 2 895#define regDMCUB_REGION6_OFFSET 0x019a 896#define regDMCUB_REGION6_OFFSET_BASE_IDX 2 897#define regDMCUB_REGION6_OFFSET_HIGH 0x019b 898#define regDMCUB_REGION6_OFFSET_HIGH_BASE_IDX 2 899#define regDMCUB_REGION7_OFFSET 0x019c 900#define regDMCUB_REGION7_OFFSET_BASE_IDX 2 901#define regDMCUB_REGION7_OFFSET_HIGH 0x019d 902#define regDMCUB_REGION7_OFFSET_HIGH_BASE_IDX 2 903#define regDMCUB_REGION0_TOP_ADDRESS 0x019e 904#define regDMCUB_REGION0_TOP_ADDRESS_BASE_IDX 2 905#define regDMCUB_REGION1_TOP_ADDRESS 0x019f 906#define regDMCUB_REGION1_TOP_ADDRESS_BASE_IDX 2 907#define regDMCUB_REGION2_TOP_ADDRESS 0x01a0 908#define regDMCUB_REGION2_TOP_ADDRESS_BASE_IDX 2 909#define regDMCUB_REGION4_TOP_ADDRESS 0x01a1 910#define regDMCUB_REGION4_TOP_ADDRESS_BASE_IDX 2 911#define regDMCUB_REGION5_TOP_ADDRESS 0x01a2 912#define regDMCUB_REGION5_TOP_ADDRESS_BASE_IDX 2 913#define regDMCUB_REGION6_TOP_ADDRESS 0x01a3 914#define regDMCUB_REGION6_TOP_ADDRESS_BASE_IDX 2 915#define regDMCUB_REGION7_TOP_ADDRESS 0x01a4 916#define regDMCUB_REGION7_TOP_ADDRESS_BASE_IDX 2 917#define regDMCUB_REGION3_CW0_BASE_ADDRESS 0x01a5 918#define regDMCUB_REGION3_CW0_BASE_ADDRESS_BASE_IDX 2 919#define regDMCUB_REGION3_CW1_BASE_ADDRESS 0x01a6 920#define regDMCUB_REGION3_CW1_BASE_ADDRESS_BASE_IDX 2 921#define regDMCUB_REGION3_CW2_BASE_ADDRESS 0x01a7 922#define regDMCUB_REGION3_CW2_BASE_ADDRESS_BASE_IDX 2 923#define regDMCUB_REGION3_CW3_BASE_ADDRESS 0x01a8 924#define regDMCUB_REGION3_CW3_BASE_ADDRESS_BASE_IDX 2 925#define regDMCUB_REGION3_CW4_BASE_ADDRESS 0x01a9 926#define regDMCUB_REGION3_CW4_BASE_ADDRESS_BASE_IDX 2 927#define regDMCUB_REGION3_CW5_BASE_ADDRESS 0x01aa 928#define regDMCUB_REGION3_CW5_BASE_ADDRESS_BASE_IDX 2 929#define regDMCUB_REGION3_CW6_BASE_ADDRESS 0x01ab 930#define regDMCUB_REGION3_CW6_BASE_ADDRESS_BASE_IDX 2 931#define regDMCUB_REGION3_CW7_BASE_ADDRESS 0x01ac 932#define regDMCUB_REGION3_CW7_BASE_ADDRESS_BASE_IDX 2 933#define regDMCUB_REGION3_CW0_TOP_ADDRESS 0x01ad 934#define regDMCUB_REGION3_CW0_TOP_ADDRESS_BASE_IDX 2 935#define regDMCUB_REGION3_CW1_TOP_ADDRESS 0x01ae 936#define regDMCUB_REGION3_CW1_TOP_ADDRESS_BASE_IDX 2 937#define regDMCUB_REGION3_CW2_TOP_ADDRESS 0x01af 938#define regDMCUB_REGION3_CW2_TOP_ADDRESS_BASE_IDX 2 939#define regDMCUB_REGION3_CW3_TOP_ADDRESS 0x01b0 940#define regDMCUB_REGION3_CW3_TOP_ADDRESS_BASE_IDX 2 941#define regDMCUB_REGION3_CW4_TOP_ADDRESS 0x01b1 942#define regDMCUB_REGION3_CW4_TOP_ADDRESS_BASE_IDX 2 943#define regDMCUB_REGION3_CW5_TOP_ADDRESS 0x01b2 944#define regDMCUB_REGION3_CW5_TOP_ADDRESS_BASE_IDX 2 945#define regDMCUB_REGION3_CW6_TOP_ADDRESS 0x01b3 946#define regDMCUB_REGION3_CW6_TOP_ADDRESS_BASE_IDX 2 947#define regDMCUB_REGION3_CW7_TOP_ADDRESS 0x01b4 948#define regDMCUB_REGION3_CW7_TOP_ADDRESS_BASE_IDX 2 949#define regDMCUB_REGION3_CW0_OFFSET 0x01b5 950#define regDMCUB_REGION3_CW0_OFFSET_BASE_IDX 2 951#define regDMCUB_REGION3_CW0_OFFSET_HIGH 0x01b6 952#define regDMCUB_REGION3_CW0_OFFSET_HIGH_BASE_IDX 2 953#define regDMCUB_REGION3_CW1_OFFSET 0x01b7 954#define regDMCUB_REGION3_CW1_OFFSET_BASE_IDX 2 955#define regDMCUB_REGION3_CW1_OFFSET_HIGH 0x01b8 956#define regDMCUB_REGION3_CW1_OFFSET_HIGH_BASE_IDX 2 957#define regDMCUB_REGION3_CW2_OFFSET 0x01b9 958#define regDMCUB_REGION3_CW2_OFFSET_BASE_IDX 2 959#define regDMCUB_REGION3_CW2_OFFSET_HIGH 0x01ba 960#define regDMCUB_REGION3_CW2_OFFSET_HIGH_BASE_IDX 2 961#define regDMCUB_REGION3_CW3_OFFSET 0x01bb 962#define regDMCUB_REGION3_CW3_OFFSET_BASE_IDX 2 963#define regDMCUB_REGION3_CW3_OFFSET_HIGH 0x01bc 964#define regDMCUB_REGION3_CW3_OFFSET_HIGH_BASE_IDX 2 965#define regDMCUB_REGION3_CW4_OFFSET 0x01bd 966#define regDMCUB_REGION3_CW4_OFFSET_BASE_IDX 2 967#define regDMCUB_REGION3_CW4_OFFSET_HIGH 0x01be 968#define regDMCUB_REGION3_CW4_OFFSET_HIGH_BASE_IDX 2 969#define regDMCUB_REGION3_CW5_OFFSET 0x01bf 970#define regDMCUB_REGION3_CW5_OFFSET_BASE_IDX 2 971#define regDMCUB_REGION3_CW5_OFFSET_HIGH 0x01c0 972#define regDMCUB_REGION3_CW5_OFFSET_HIGH_BASE_IDX 2 973#define regDMCUB_REGION3_CW6_OFFSET 0x01c1 974#define regDMCUB_REGION3_CW6_OFFSET_BASE_IDX 2 975#define regDMCUB_REGION3_CW6_OFFSET_HIGH 0x01c2 976#define regDMCUB_REGION3_CW6_OFFSET_HIGH_BASE_IDX 2 977#define regDMCUB_REGION3_CW7_OFFSET 0x01c3 978#define regDMCUB_REGION3_CW7_OFFSET_BASE_IDX 2 979#define regDMCUB_REGION3_CW7_OFFSET_HIGH 0x01c4 980#define regDMCUB_REGION3_CW7_OFFSET_HIGH_BASE_IDX 2 981#define regDMCUB_INTERRUPT_ENABLE 0x01c5 982#define regDMCUB_INTERRUPT_ENABLE_BASE_IDX 2 983#define regDMCUB_INTERRUPT_ACK 0x01c6 984#define regDMCUB_INTERRUPT_ACK_BASE_IDX 2 985#define regDMCUB_INTERRUPT_STATUS 0x01c7 986#define regDMCUB_INTERRUPT_STATUS_BASE_IDX 2 987#define regDMCUB_INTERRUPT_TYPE 0x01c8 988#define regDMCUB_INTERRUPT_TYPE_BASE_IDX 2 989#define regDMCUB_EXT_INTERRUPT_STATUS 0x01c9 990#define regDMCUB_EXT_INTERRUPT_STATUS_BASE_IDX 2 991#define regDMCUB_EXT_INTERRUPT_CTXID 0x01ca 992#define regDMCUB_EXT_INTERRUPT_CTXID_BASE_IDX 2 993#define regDMCUB_EXT_INTERRUPT_ACK 0x01cb 994#define regDMCUB_EXT_INTERRUPT_ACK_BASE_IDX 2 995#define regDMCUB_INST_FETCH_FAULT_ADDR 0x01cc 996#define regDMCUB_INST_FETCH_FAULT_ADDR_BASE_IDX 2 997#define regDMCUB_DATA_WRITE_FAULT_ADDR 0x01cd 998#define regDMCUB_DATA_WRITE_FAULT_ADDR_BASE_IDX 2 999#define regDMCUB_SEC_CNTL 0x01ce 1000#define regDMCUB_SEC_CNTL_BASE_IDX 2 1001#define regDMCUB_MEM_CNTL 0x01cf 1002#define regDMCUB_MEM_CNTL_BASE_IDX 2 1003#define regDMCUB_INBOX0_BASE_ADDRESS 0x01d0 1004#define regDMCUB_INBOX0_BASE_ADDRESS_BASE_IDX 2 1005#define regDMCUB_INBOX0_SIZE 0x01d1 1006#define regDMCUB_INBOX0_SIZE_BASE_IDX 2 1007#define regDMCUB_INBOX0_WPTR 0x01d2 1008#define regDMCUB_INBOX0_WPTR_BASE_IDX 2 1009#define regDMCUB_INBOX0_RPTR 0x01d3 1010#define regDMCUB_INBOX0_RPTR_BASE_IDX 2 1011#define regDMCUB_INBOX1_BASE_ADDRESS 0x01d4 1012#define regDMCUB_INBOX1_BASE_ADDRESS_BASE_IDX 2 1013#define regDMCUB_INBOX1_SIZE 0x01d5 1014#define regDMCUB_INBOX1_SIZE_BASE_IDX 2 1015#define regDMCUB_INBOX1_WPTR 0x01d6 1016#define regDMCUB_INBOX1_WPTR_BASE_IDX 2 1017#define regDMCUB_INBOX1_RPTR 0x01d7 1018#define regDMCUB_INBOX1_RPTR_BASE_IDX 2 1019#define regDMCUB_OUTBOX0_BASE_ADDRESS 0x01d8 1020#define regDMCUB_OUTBOX0_BASE_ADDRESS_BASE_IDX 2 1021#define regDMCUB_OUTBOX0_SIZE 0x01d9 1022#define regDMCUB_OUTBOX0_SIZE_BASE_IDX 2 1023#define regDMCUB_OUTBOX0_WPTR 0x01da 1024#define regDMCUB_OUTBOX0_WPTR_BASE_IDX 2 1025#define regDMCUB_OUTBOX0_RPTR 0x01db 1026#define regDMCUB_OUTBOX0_RPTR_BASE_IDX 2 1027#define regDMCUB_OUTBOX1_BASE_ADDRESS 0x01dc 1028#define regDMCUB_OUTBOX1_BASE_ADDRESS_BASE_IDX 2 1029#define regDMCUB_OUTBOX1_SIZE 0x01dd 1030#define regDMCUB_OUTBOX1_SIZE_BASE_IDX 2 1031#define regDMCUB_OUTBOX1_WPTR 0x01de 1032#define regDMCUB_OUTBOX1_WPTR_BASE_IDX 2 1033#define regDMCUB_OUTBOX1_RPTR 0x01df 1034#define regDMCUB_OUTBOX1_RPTR_BASE_IDX 2 1035#define regDMCUB_TIMER_TRIGGER0 0x01e0 1036#define regDMCUB_TIMER_TRIGGER0_BASE_IDX 2 1037#define regDMCUB_TIMER_TRIGGER1 0x01e1 1038#define regDMCUB_TIMER_TRIGGER1_BASE_IDX 2 1039#define regDMCUB_TIMER_WINDOW 0x01e2 1040#define regDMCUB_TIMER_WINDOW_BASE_IDX 2 1041#define regDMCUB_SCRATCH0 0x01e3 1042#define regDMCUB_SCRATCH0_BASE_IDX 2 1043#define regDMCUB_SCRATCH1 0x01e4 1044#define regDMCUB_SCRATCH1_BASE_IDX 2 1045#define regDMCUB_SCRATCH2 0x01e5 1046#define regDMCUB_SCRATCH2_BASE_IDX 2 1047#define regDMCUB_SCRATCH3 0x01e6 1048#define regDMCUB_SCRATCH3_BASE_IDX 2 1049#define regDMCUB_SCRATCH4 0x01e7 1050#define regDMCUB_SCRATCH4_BASE_IDX 2 1051#define regDMCUB_SCRATCH5 0x01e8 1052#define regDMCUB_SCRATCH5_BASE_IDX 2 1053#define regDMCUB_SCRATCH6 0x01e9 1054#define regDMCUB_SCRATCH6_BASE_IDX 2 1055#define regDMCUB_SCRATCH7 0x01ea 1056#define regDMCUB_SCRATCH7_BASE_IDX 2 1057#define regDMCUB_SCRATCH8 0x01eb 1058#define regDMCUB_SCRATCH8_BASE_IDX 2 1059#define regDMCUB_SCRATCH9 0x01ec 1060#define regDMCUB_SCRATCH9_BASE_IDX 2 1061#define regDMCUB_SCRATCH10 0x01ed 1062#define regDMCUB_SCRATCH10_BASE_IDX 2 1063#define regDMCUB_SCRATCH11 0x01ee 1064#define regDMCUB_SCRATCH11_BASE_IDX 2 1065#define regDMCUB_SCRATCH12 0x01ef 1066#define regDMCUB_SCRATCH12_BASE_IDX 2 1067#define regDMCUB_SCRATCH13 0x01f0 1068#define regDMCUB_SCRATCH13_BASE_IDX 2 1069#define regDMCUB_SCRATCH14 0x01f1 1070#define regDMCUB_SCRATCH14_BASE_IDX 2 1071#define regDMCUB_SCRATCH15 0x01f2 1072#define regDMCUB_SCRATCH15_BASE_IDX 2 1073#define regDMCUB_CNTL 0x01f6 1074#define regDMCUB_CNTL_BASE_IDX 2 1075#define regDMCUB_GPINT_DATAIN0 0x01f7 1076#define regDMCUB_GPINT_DATAIN0_BASE_IDX 2 1077#define regDMCUB_GPINT_DATAIN1 0x01f8 1078#define regDMCUB_GPINT_DATAIN1_BASE_IDX 2 1079#define regDMCUB_GPINT_DATAOUT 0x01f9 1080#define regDMCUB_GPINT_DATAOUT_BASE_IDX 2 1081#define regDMCUB_UNDEFINED_ADDRESS_FAULT_ADDR 0x01fa 1082#define regDMCUB_UNDEFINED_ADDRESS_FAULT_ADDR_BASE_IDX 2 1083#define regDMCUB_LS_WAKE_INT_ENABLE 0x01fb 1084#define regDMCUB_LS_WAKE_INT_ENABLE_BASE_IDX 2 1085#define regDMCUB_MEM_PWR_CNTL 0x01fc 1086#define regDMCUB_MEM_PWR_CNTL_BASE_IDX 2 1087#define regDMCUB_TIMER_CURRENT 0x01fd 1088#define regDMCUB_TIMER_CURRENT_BASE_IDX 2 1089#define regDMCUB_PROC_ID 0x01ff 1090#define regDMCUB_PROC_ID_BASE_IDX 2 1091#define regDMCUB_CNTL2 0x0200 1092#define regDMCUB_CNTL2_BASE_IDX 2 1093 1094 1095// addressBlock: dce_dc_wb0_dispdec_dwb_top_dispdec 1096// base address: 0x0 1097#define regDWB_ENABLE_CLK_CTRL 0x3228 1098#define regDWB_ENABLE_CLK_CTRL_BASE_IDX 2 1099#define regDWB_MEM_PWR_CTRL 0x3229 1100#define regDWB_MEM_PWR_CTRL_BASE_IDX 2 1101#define regFC_MODE_CTRL 0x322a 1102#define regFC_MODE_CTRL_BASE_IDX 2 1103#define regFC_FLOW_CTRL 0x322b 1104#define regFC_FLOW_CTRL_BASE_IDX 2 1105#define regFC_WINDOW_START 0x322c 1106#define regFC_WINDOW_START_BASE_IDX 2 1107#define regFC_WINDOW_SIZE 0x322d 1108#define regFC_WINDOW_SIZE_BASE_IDX 2 1109#define regFC_SOURCE_SIZE 0x322e 1110#define regFC_SOURCE_SIZE_BASE_IDX 2 1111#define regDWB_UPDATE_CTRL 0x322f 1112#define regDWB_UPDATE_CTRL_BASE_IDX 2 1113#define regDWB_CRC_CTRL 0x3230 1114#define regDWB_CRC_CTRL_BASE_IDX 2 1115#define regDWB_CRC_MASK_R_G 0x3231 1116#define regDWB_CRC_MASK_R_G_BASE_IDX 2 1117#define regDWB_CRC_MASK_B_A 0x3232 1118#define regDWB_CRC_MASK_B_A_BASE_IDX 2 1119#define regDWB_CRC_VAL_R_G 0x3233 1120#define regDWB_CRC_VAL_R_G_BASE_IDX 2 1121#define regDWB_CRC_VAL_B_A 0x3234 1122#define regDWB_CRC_VAL_B_A_BASE_IDX 2 1123#define regDWB_OUT_CTRL 0x3235 1124#define regDWB_OUT_CTRL_BASE_IDX 2 1125#define regDWB_MMHUBBUB_BACKPRESSURE_CNT_EN 0x3236 1126#define regDWB_MMHUBBUB_BACKPRESSURE_CNT_EN_BASE_IDX 2 1127#define regDWB_MMHUBBUB_BACKPRESSURE_CNT 0x3237 1128#define regDWB_MMHUBBUB_BACKPRESSURE_CNT_BASE_IDX 2 1129#define regDWB_HOST_READ_CONTROL 0x3238 1130#define regDWB_HOST_READ_CONTROL_BASE_IDX 2 1131#define regDWB_OVERFLOW_STATUS 0x3239 1132#define regDWB_OVERFLOW_STATUS_BASE_IDX 2 1133#define regDWB_OVERFLOW_COUNTER 0x323a 1134#define regDWB_OVERFLOW_COUNTER_BASE_IDX 2 1135#define regDWB_SOFT_RESET 0x323b 1136#define regDWB_SOFT_RESET_BASE_IDX 2 1137#define regDWB_DEBUG_CTRL 0x323c 1138#define regDWB_DEBUG_CTRL_BASE_IDX 2 1139 1140 1141// addressBlock: dce_dc_wb0_dispdec_dwbcp_dispdec 1142// base address: 0x0 1143#define regDWB_HDR_MULT_COEF 0x3294 1144#define regDWB_HDR_MULT_COEF_BASE_IDX 2 1145#define regDWB_GAMUT_REMAP_MODE 0x3295 1146#define regDWB_GAMUT_REMAP_MODE_BASE_IDX 2 1147#define regDWB_GAMUT_REMAP_COEF_FORMAT 0x3296 1148#define regDWB_GAMUT_REMAP_COEF_FORMAT_BASE_IDX 2 1149#define regDWB_GAMUT_REMAPA_C11_C12 0x3297 1150#define regDWB_GAMUT_REMAPA_C11_C12_BASE_IDX 2 1151#define regDWB_GAMUT_REMAPA_C13_C14 0x3298 1152#define regDWB_GAMUT_REMAPA_C13_C14_BASE_IDX 2 1153#define regDWB_GAMUT_REMAPA_C21_C22 0x3299 1154#define regDWB_GAMUT_REMAPA_C21_C22_BASE_IDX 2 1155#define regDWB_GAMUT_REMAPA_C23_C24 0x329a 1156#define regDWB_GAMUT_REMAPA_C23_C24_BASE_IDX 2 1157#define regDWB_GAMUT_REMAPA_C31_C32 0x329b 1158#define regDWB_GAMUT_REMAPA_C31_C32_BASE_IDX 2 1159#define regDWB_GAMUT_REMAPA_C33_C34 0x329c 1160#define regDWB_GAMUT_REMAPA_C33_C34_BASE_IDX 2 1161#define regDWB_GAMUT_REMAPB_C11_C12 0x329d 1162#define regDWB_GAMUT_REMAPB_C11_C12_BASE_IDX 2 1163#define regDWB_GAMUT_REMAPB_C13_C14 0x329e 1164#define regDWB_GAMUT_REMAPB_C13_C14_BASE_IDX 2 1165#define regDWB_GAMUT_REMAPB_C21_C22 0x329f 1166#define regDWB_GAMUT_REMAPB_C21_C22_BASE_IDX 2 1167#define regDWB_GAMUT_REMAPB_C23_C24 0x32a0 1168#define regDWB_GAMUT_REMAPB_C23_C24_BASE_IDX 2 1169#define regDWB_GAMUT_REMAPB_C31_C32 0x32a1 1170#define regDWB_GAMUT_REMAPB_C31_C32_BASE_IDX 2 1171#define regDWB_GAMUT_REMAPB_C33_C34 0x32a2 1172#define regDWB_GAMUT_REMAPB_C33_C34_BASE_IDX 2 1173#define regDWB_OGAM_CONTROL 0x32a3 1174#define regDWB_OGAM_CONTROL_BASE_IDX 2 1175#define regDWB_OGAM_LUT_INDEX 0x32a4 1176#define regDWB_OGAM_LUT_INDEX_BASE_IDX 2 1177#define regDWB_OGAM_LUT_DATA 0x32a5 1178#define regDWB_OGAM_LUT_DATA_BASE_IDX 2 1179#define regDWB_OGAM_LUT_CONTROL 0x32a6 1180#define regDWB_OGAM_LUT_CONTROL_BASE_IDX 2 1181#define regDWB_OGAM_RAMA_START_CNTL_B 0x32a7 1182#define regDWB_OGAM_RAMA_START_CNTL_B_BASE_IDX 2 1183#define regDWB_OGAM_RAMA_START_CNTL_G 0x32a8 1184#define regDWB_OGAM_RAMA_START_CNTL_G_BASE_IDX 2 1185#define regDWB_OGAM_RAMA_START_CNTL_R 0x32a9 1186#define regDWB_OGAM_RAMA_START_CNTL_R_BASE_IDX 2 1187#define regDWB_OGAM_RAMA_START_BASE_CNTL_B 0x32aa 1188#define regDWB_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX 2 1189#define regDWB_OGAM_RAMA_START_SLOPE_CNTL_B 0x32ab 1190#define regDWB_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX 2 1191#define regDWB_OGAM_RAMA_START_BASE_CNTL_G 0x32ac 1192#define regDWB_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX 2 1193#define regDWB_OGAM_RAMA_START_SLOPE_CNTL_G 0x32ad 1194#define regDWB_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2 1195#define regDWB_OGAM_RAMA_START_BASE_CNTL_R 0x32ae 1196#define regDWB_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX 2 1197#define regDWB_OGAM_RAMA_START_SLOPE_CNTL_R 0x32af 1198#define regDWB_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX 2 1199#define regDWB_OGAM_RAMA_END_CNTL1_B 0x32b0 1200#define regDWB_OGAM_RAMA_END_CNTL1_B_BASE_IDX 2 1201#define regDWB_OGAM_RAMA_END_CNTL2_B 0x32b1 1202#define regDWB_OGAM_RAMA_END_CNTL2_B_BASE_IDX 2 1203#define regDWB_OGAM_RAMA_END_CNTL1_G 0x32b2 1204#define regDWB_OGAM_RAMA_END_CNTL1_G_BASE_IDX 2 1205#define regDWB_OGAM_RAMA_END_CNTL2_G 0x32b3 1206#define regDWB_OGAM_RAMA_END_CNTL2_G_BASE_IDX 2 1207#define regDWB_OGAM_RAMA_END_CNTL1_R 0x32b4 1208#define regDWB_OGAM_RAMA_END_CNTL1_R_BASE_IDX 2 1209#define regDWB_OGAM_RAMA_END_CNTL2_R 0x32b5 1210#define regDWB_OGAM_RAMA_END_CNTL2_R_BASE_IDX 2 1211#define regDWB_OGAM_RAMA_OFFSET_B 0x32b6 1212#define regDWB_OGAM_RAMA_OFFSET_B_BASE_IDX 2 1213#define regDWB_OGAM_RAMA_OFFSET_G 0x32b7 1214#define regDWB_OGAM_RAMA_OFFSET_G_BASE_IDX 2 1215#define regDWB_OGAM_RAMA_OFFSET_R 0x32b8 1216#define regDWB_OGAM_RAMA_OFFSET_R_BASE_IDX 2 1217#define regDWB_OGAM_RAMA_REGION_0_1 0x32b9 1218#define regDWB_OGAM_RAMA_REGION_0_1_BASE_IDX 2 1219#define regDWB_OGAM_RAMA_REGION_2_3 0x32ba 1220#define regDWB_OGAM_RAMA_REGION_2_3_BASE_IDX 2 1221#define regDWB_OGAM_RAMA_REGION_4_5 0x32bb 1222#define regDWB_OGAM_RAMA_REGION_4_5_BASE_IDX 2 1223#define regDWB_OGAM_RAMA_REGION_6_7 0x32bc 1224#define regDWB_OGAM_RAMA_REGION_6_7_BASE_IDX 2 1225#define regDWB_OGAM_RAMA_REGION_8_9 0x32bd 1226#define regDWB_OGAM_RAMA_REGION_8_9_BASE_IDX 2 1227#define regDWB_OGAM_RAMA_REGION_10_11 0x32be 1228#define regDWB_OGAM_RAMA_REGION_10_11_BASE_IDX 2 1229#define regDWB_OGAM_RAMA_REGION_12_13 0x32bf 1230#define regDWB_OGAM_RAMA_REGION_12_13_BASE_IDX 2 1231#define regDWB_OGAM_RAMA_REGION_14_15 0x32c0 1232#define regDWB_OGAM_RAMA_REGION_14_15_BASE_IDX 2 1233#define regDWB_OGAM_RAMA_REGION_16_17 0x32c1 1234#define regDWB_OGAM_RAMA_REGION_16_17_BASE_IDX 2 1235#define regDWB_OGAM_RAMA_REGION_18_19 0x32c2 1236#define regDWB_OGAM_RAMA_REGION_18_19_BASE_IDX 2 1237#define regDWB_OGAM_RAMA_REGION_20_21 0x32c3 1238#define regDWB_OGAM_RAMA_REGION_20_21_BASE_IDX 2 1239#define regDWB_OGAM_RAMA_REGION_22_23 0x32c4 1240#define regDWB_OGAM_RAMA_REGION_22_23_BASE_IDX 2 1241#define regDWB_OGAM_RAMA_REGION_24_25 0x32c5 1242#define regDWB_OGAM_RAMA_REGION_24_25_BASE_IDX 2 1243#define regDWB_OGAM_RAMA_REGION_26_27 0x32c6 1244#define regDWB_OGAM_RAMA_REGION_26_27_BASE_IDX 2 1245#define regDWB_OGAM_RAMA_REGION_28_29 0x32c7 1246#define regDWB_OGAM_RAMA_REGION_28_29_BASE_IDX 2 1247#define regDWB_OGAM_RAMA_REGION_30_31 0x32c8 1248#define regDWB_OGAM_RAMA_REGION_30_31_BASE_IDX 2 1249#define regDWB_OGAM_RAMA_REGION_32_33 0x32c9 1250#define regDWB_OGAM_RAMA_REGION_32_33_BASE_IDX 2 1251#define regDWB_OGAM_RAMB_START_CNTL_B 0x32ca 1252#define regDWB_OGAM_RAMB_START_CNTL_B_BASE_IDX 2 1253#define regDWB_OGAM_RAMB_START_CNTL_G 0x32cb 1254#define regDWB_OGAM_RAMB_START_CNTL_G_BASE_IDX 2 1255#define regDWB_OGAM_RAMB_START_CNTL_R 0x32cc 1256#define regDWB_OGAM_RAMB_START_CNTL_R_BASE_IDX 2 1257#define regDWB_OGAM_RAMB_START_BASE_CNTL_B 0x32cd 1258#define regDWB_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX 2 1259#define regDWB_OGAM_RAMB_START_SLOPE_CNTL_B 0x32ce 1260#define regDWB_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX 2 1261#define regDWB_OGAM_RAMB_START_BASE_CNTL_G 0x32cf 1262#define regDWB_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX 2 1263#define regDWB_OGAM_RAMB_START_SLOPE_CNTL_G 0x32d0 1264#define regDWB_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX 2 1265#define regDWB_OGAM_RAMB_START_BASE_CNTL_R 0x32d1 1266#define regDWB_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX 2 1267#define regDWB_OGAM_RAMB_START_SLOPE_CNTL_R 0x32d2 1268#define regDWB_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX 2 1269#define regDWB_OGAM_RAMB_END_CNTL1_B 0x32d3 1270#define regDWB_OGAM_RAMB_END_CNTL1_B_BASE_IDX 2 1271#define regDWB_OGAM_RAMB_END_CNTL2_B 0x32d4 1272#define regDWB_OGAM_RAMB_END_CNTL2_B_BASE_IDX 2 1273#define regDWB_OGAM_RAMB_END_CNTL1_G 0x32d5 1274#define regDWB_OGAM_RAMB_END_CNTL1_G_BASE_IDX 2 1275#define regDWB_OGAM_RAMB_END_CNTL2_G 0x32d6 1276#define regDWB_OGAM_RAMB_END_CNTL2_G_BASE_IDX 2 1277#define regDWB_OGAM_RAMB_END_CNTL1_R 0x32d7 1278#define regDWB_OGAM_RAMB_END_CNTL1_R_BASE_IDX 2 1279#define regDWB_OGAM_RAMB_END_CNTL2_R 0x32d8 1280#define regDWB_OGAM_RAMB_END_CNTL2_R_BASE_IDX 2 1281#define regDWB_OGAM_RAMB_OFFSET_B 0x32d9 1282#define regDWB_OGAM_RAMB_OFFSET_B_BASE_IDX 2 1283#define regDWB_OGAM_RAMB_OFFSET_G 0x32da 1284#define regDWB_OGAM_RAMB_OFFSET_G_BASE_IDX 2 1285#define regDWB_OGAM_RAMB_OFFSET_R 0x32db 1286#define regDWB_OGAM_RAMB_OFFSET_R_BASE_IDX 2 1287#define regDWB_OGAM_RAMB_REGION_0_1 0x32dc 1288#define regDWB_OGAM_RAMB_REGION_0_1_BASE_IDX 2 1289#define regDWB_OGAM_RAMB_REGION_2_3 0x32dd 1290#define regDWB_OGAM_RAMB_REGION_2_3_BASE_IDX 2 1291#define regDWB_OGAM_RAMB_REGION_4_5 0x32de 1292#define regDWB_OGAM_RAMB_REGION_4_5_BASE_IDX 2 1293#define regDWB_OGAM_RAMB_REGION_6_7 0x32df 1294#define regDWB_OGAM_RAMB_REGION_6_7_BASE_IDX 2 1295#define regDWB_OGAM_RAMB_REGION_8_9 0x32e0 1296#define regDWB_OGAM_RAMB_REGION_8_9_BASE_IDX 2 1297#define regDWB_OGAM_RAMB_REGION_10_11 0x32e1 1298#define regDWB_OGAM_RAMB_REGION_10_11_BASE_IDX 2 1299#define regDWB_OGAM_RAMB_REGION_12_13 0x32e2 1300#define regDWB_OGAM_RAMB_REGION_12_13_BASE_IDX 2 1301#define regDWB_OGAM_RAMB_REGION_14_15 0x32e3 1302#define regDWB_OGAM_RAMB_REGION_14_15_BASE_IDX 2 1303#define regDWB_OGAM_RAMB_REGION_16_17 0x32e4 1304#define regDWB_OGAM_RAMB_REGION_16_17_BASE_IDX 2 1305#define regDWB_OGAM_RAMB_REGION_18_19 0x32e5 1306#define regDWB_OGAM_RAMB_REGION_18_19_BASE_IDX 2 1307#define regDWB_OGAM_RAMB_REGION_20_21 0x32e6 1308#define regDWB_OGAM_RAMB_REGION_20_21_BASE_IDX 2 1309#define regDWB_OGAM_RAMB_REGION_22_23 0x32e7 1310#define regDWB_OGAM_RAMB_REGION_22_23_BASE_IDX 2 1311#define regDWB_OGAM_RAMB_REGION_24_25 0x32e8 1312#define regDWB_OGAM_RAMB_REGION_24_25_BASE_IDX 2 1313#define regDWB_OGAM_RAMB_REGION_26_27 0x32e9 1314#define regDWB_OGAM_RAMB_REGION_26_27_BASE_IDX 2 1315#define regDWB_OGAM_RAMB_REGION_28_29 0x32ea 1316#define regDWB_OGAM_RAMB_REGION_28_29_BASE_IDX 2 1317#define regDWB_OGAM_RAMB_REGION_30_31 0x32eb 1318#define regDWB_OGAM_RAMB_REGION_30_31_BASE_IDX 2 1319#define regDWB_OGAM_RAMB_REGION_32_33 0x32ec 1320#define regDWB_OGAM_RAMB_REGION_32_33_BASE_IDX 2 1321 1322 1323// addressBlock: dce_dc_wb0_dispdec_wb_dcperfmon_dc_perfmon_dispdec 1324// base address: 0xca20 1325#define regDC_PERFMON3_PERFCOUNTER_CNTL 0x3288 1326#define regDC_PERFMON3_PERFCOUNTER_CNTL_BASE_IDX 2 1327#define regDC_PERFMON3_PERFCOUNTER_CNTL2 0x3289 1328#define regDC_PERFMON3_PERFCOUNTER_CNTL2_BASE_IDX 2 1329#define regDC_PERFMON3_PERFCOUNTER_STATE 0x328a 1330#define regDC_PERFMON3_PERFCOUNTER_STATE_BASE_IDX 2 1331#define regDC_PERFMON3_PERFMON_CNTL 0x328b 1332#define regDC_PERFMON3_PERFMON_CNTL_BASE_IDX 2 1333#define regDC_PERFMON3_PERFMON_CNTL2 0x328c 1334#define regDC_PERFMON3_PERFMON_CNTL2_BASE_IDX 2 1335#define regDC_PERFMON3_PERFMON_CVALUE_INT_MISC 0x328d 1336#define regDC_PERFMON3_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 1337#define regDC_PERFMON3_PERFMON_CVALUE_LOW 0x328e 1338#define regDC_PERFMON3_PERFMON_CVALUE_LOW_BASE_IDX 2 1339#define regDC_PERFMON3_PERFMON_HI 0x328f 1340#define regDC_PERFMON3_PERFMON_HI_BASE_IDX 2 1341#define regDC_PERFMON3_PERFMON_LOW 0x3290 1342#define regDC_PERFMON3_PERFMON_LOW_BASE_IDX 2 1343 1344 1345// addressBlock: dce_dc_mmhubbub_vga_dispdec 1346// base address: 0x0 1347#define regVGA_RENDER_CONTROL 0x0000 1348#define regVGA_RENDER_CONTROL_BASE_IDX 1 1349#define regVGA_SEQUENCER_RESET_CONTROL 0x0001 1350#define regVGA_SEQUENCER_RESET_CONTROL_BASE_IDX 1 1351#define regVGA_MODE_CONTROL 0x0002 1352#define regVGA_MODE_CONTROL_BASE_IDX 1 1353#define regVGA_SURFACE_PITCH_SELECT 0x0003 1354#define regVGA_SURFACE_PITCH_SELECT_BASE_IDX 1 1355#define regVGA_MEMORY_BASE_ADDRESS 0x0004 1356#define regVGA_MEMORY_BASE_ADDRESS_BASE_IDX 1 1357#define regVGA_DISPBUF1_SURFACE_ADDR 0x0006 1358#define regVGA_DISPBUF1_SURFACE_ADDR_BASE_IDX 1 1359#define regVGA_DISPBUF2_SURFACE_ADDR 0x0008 1360#define regVGA_DISPBUF2_SURFACE_ADDR_BASE_IDX 1 1361#define regVGA_MEMORY_BASE_ADDRESS_HIGH 0x0009 1362#define regVGA_MEMORY_BASE_ADDRESS_HIGH_BASE_IDX 1 1363#define regVGA_HDP_CONTROL 0x000a 1364#define regVGA_HDP_CONTROL_BASE_IDX 1 1365#define regVGA_CACHE_CONTROL 0x000b 1366#define regVGA_CACHE_CONTROL_BASE_IDX 1 1367#define regD1VGA_CONTROL 0x000c 1368#define regD1VGA_CONTROL_BASE_IDX 1 1369#define regD2VGA_CONTROL 0x000e 1370#define regD2VGA_CONTROL_BASE_IDX 1 1371#define regVGA_STATUS 0x0010 1372#define regVGA_STATUS_BASE_IDX 1 1373#define regVGA_INTERRUPT_CONTROL 0x0011 1374#define regVGA_INTERRUPT_CONTROL_BASE_IDX 1 1375#define regVGA_STATUS_CLEAR 0x0012 1376#define regVGA_STATUS_CLEAR_BASE_IDX 1 1377#define regVGA_INTERRUPT_STATUS 0x0013 1378#define regVGA_INTERRUPT_STATUS_BASE_IDX 1 1379#define regVGA_MAIN_CONTROL 0x0014 1380#define regVGA_MAIN_CONTROL_BASE_IDX 1 1381#define regVGA_TEST_CONTROL 0x0015 1382#define regVGA_TEST_CONTROL_BASE_IDX 1 1383#define regVGA_QOS_CTRL 0x0018 1384#define regVGA_QOS_CTRL_BASE_IDX 1 1385#define regD3VGA_CONTROL 0x0038 1386#define regD3VGA_CONTROL_BASE_IDX 1 1387#define regD4VGA_CONTROL 0x0039 1388#define regD4VGA_CONTROL_BASE_IDX 1 1389#define regD5VGA_CONTROL 0x003a 1390#define regD5VGA_CONTROL_BASE_IDX 1 1391#define regD6VGA_CONTROL 0x003b 1392#define regD6VGA_CONTROL_BASE_IDX 1 1393#define regVGA_SOURCE_SELECT 0x003c 1394#define regVGA_SOURCE_SELECT_BASE_IDX 1 1395 1396 1397// addressBlock: dce_dc_mmhubbub_vgaif_dispdec 1398// base address: 0x0 1399#define regMCIF_CONTROL 0x034a 1400#define regMCIF_CONTROL_BASE_IDX 2 1401#define regMCIF_WRITE_COMBINE_CONTROL 0x034b 1402#define regMCIF_WRITE_COMBINE_CONTROL_BASE_IDX 2 1403#define regMCIF_PHASE0_OUTSTANDING_COUNTER 0x034e 1404#define regMCIF_PHASE0_OUTSTANDING_COUNTER_BASE_IDX 2 1405#define regMCIF_PHASE1_OUTSTANDING_COUNTER 0x034f 1406#define regMCIF_PHASE1_OUTSTANDING_COUNTER_BASE_IDX 2 1407#define regMCIF_PHASE2_OUTSTANDING_COUNTER 0x0350 1408#define regMCIF_PHASE2_OUTSTANDING_COUNTER_BASE_IDX 2 1409 1410 1411// addressBlock: dce_dc_mmhubbub_mcif_wb0_dispdec 1412// base address: 0x0 1413#define regMCIF_WB_BUFMGR_SW_CONTROL 0x0272 1414#define regMCIF_WB_BUFMGR_SW_CONTROL_BASE_IDX 2 1415#define regMCIF_WB_BUFMGR_STATUS 0x0274 1416#define regMCIF_WB_BUFMGR_STATUS_BASE_IDX 2 1417#define regMCIF_WB_BUF_PITCH 0x0275 1418#define regMCIF_WB_BUF_PITCH_BASE_IDX 2 1419#define regMCIF_WB_BUF_1_STATUS 0x0276 1420#define regMCIF_WB_BUF_1_STATUS_BASE_IDX 2 1421#define regMCIF_WB_BUF_1_STATUS2 0x0277 1422#define regMCIF_WB_BUF_1_STATUS2_BASE_IDX 2 1423#define regMCIF_WB_BUF_2_STATUS 0x0278 1424#define regMCIF_WB_BUF_2_STATUS_BASE_IDX 2 1425#define regMCIF_WB_BUF_2_STATUS2 0x0279 1426#define regMCIF_WB_BUF_2_STATUS2_BASE_IDX 2 1427#define regMCIF_WB_BUF_3_STATUS 0x027a 1428#define regMCIF_WB_BUF_3_STATUS_BASE_IDX 2 1429#define regMCIF_WB_BUF_3_STATUS2 0x027b 1430#define regMCIF_WB_BUF_3_STATUS2_BASE_IDX 2 1431#define regMCIF_WB_BUF_4_STATUS 0x027c 1432#define regMCIF_WB_BUF_4_STATUS_BASE_IDX 2 1433#define regMCIF_WB_BUF_4_STATUS2 0x027d 1434#define regMCIF_WB_BUF_4_STATUS2_BASE_IDX 2 1435#define regMCIF_WB_ARBITRATION_CONTROL 0x027e 1436#define regMCIF_WB_ARBITRATION_CONTROL_BASE_IDX 2 1437#define regMCIF_WB_SCLK_CHANGE 0x027f 1438#define regMCIF_WB_SCLK_CHANGE_BASE_IDX 2 1439#define regMCIF_WB_TEST_DEBUG_INDEX 0x0280 1440#define regMCIF_WB_TEST_DEBUG_INDEX_BASE_IDX 2 1441#define regMCIF_WB_TEST_DEBUG_DATA 0x0281 1442#define regMCIF_WB_TEST_DEBUG_DATA_BASE_IDX 2 1443#define regMCIF_WB_BUF_1_ADDR_Y 0x0282 1444#define regMCIF_WB_BUF_1_ADDR_Y_BASE_IDX 2 1445#define regMCIF_WB_BUF_1_ADDR_C 0x0284 1446#define regMCIF_WB_BUF_1_ADDR_C_BASE_IDX 2 1447#define regMCIF_WB_BUF_2_ADDR_Y 0x0286 1448#define regMCIF_WB_BUF_2_ADDR_Y_BASE_IDX 2 1449#define regMCIF_WB_BUF_2_ADDR_C 0x0288 1450#define regMCIF_WB_BUF_2_ADDR_C_BASE_IDX 2 1451#define regMCIF_WB_BUF_3_ADDR_Y 0x028a 1452#define regMCIF_WB_BUF_3_ADDR_Y_BASE_IDX 2 1453#define regMCIF_WB_BUF_3_ADDR_C 0x028c 1454#define regMCIF_WB_BUF_3_ADDR_C_BASE_IDX 2 1455#define regMCIF_WB_BUF_4_ADDR_Y 0x028e 1456#define regMCIF_WB_BUF_4_ADDR_Y_BASE_IDX 2 1457#define regMCIF_WB_BUF_4_ADDR_C 0x0290 1458#define regMCIF_WB_BUF_4_ADDR_C_BASE_IDX 2 1459#define regMCIF_WB_BUFMGR_VCE_CONTROL 0x0292 1460#define regMCIF_WB_BUFMGR_VCE_CONTROL_BASE_IDX 2 1461#define regMCIF_WB_NB_PSTATE_CONTROL 0x0293 1462#define regMCIF_WB_NB_PSTATE_CONTROL_BASE_IDX 2 1463#define regMCIF_WB_CLOCK_GATER_CONTROL 0x0294 1464#define regMCIF_WB_CLOCK_GATER_CONTROL_BASE_IDX 2 1465#define regMCIF_WB_SELF_REFRESH_CONTROL 0x0296 1466#define regMCIF_WB_SELF_REFRESH_CONTROL_BASE_IDX 2 1467#define regMULTI_LEVEL_QOS_CTRL 0x0297 1468#define regMULTI_LEVEL_QOS_CTRL_BASE_IDX 2 1469#define regMCIF_WB_BUF_LUMA_SIZE 0x0299 1470#define regMCIF_WB_BUF_LUMA_SIZE_BASE_IDX 2 1471#define regMCIF_WB_BUF_CHROMA_SIZE 0x029a 1472#define regMCIF_WB_BUF_CHROMA_SIZE_BASE_IDX 2 1473#define regMCIF_WB_BUF_1_ADDR_Y_HIGH 0x029b 1474#define regMCIF_WB_BUF_1_ADDR_Y_HIGH_BASE_IDX 2 1475#define regMCIF_WB_BUF_1_ADDR_C_HIGH 0x029c 1476#define regMCIF_WB_BUF_1_ADDR_C_HIGH_BASE_IDX 2 1477#define regMCIF_WB_BUF_2_ADDR_Y_HIGH 0x029d 1478#define regMCIF_WB_BUF_2_ADDR_Y_HIGH_BASE_IDX 2 1479#define regMCIF_WB_BUF_2_ADDR_C_HIGH 0x029e 1480#define regMCIF_WB_BUF_2_ADDR_C_HIGH_BASE_IDX 2 1481#define regMCIF_WB_BUF_3_ADDR_Y_HIGH 0x029f 1482#define regMCIF_WB_BUF_3_ADDR_Y_HIGH_BASE_IDX 2 1483#define regMCIF_WB_BUF_3_ADDR_C_HIGH 0x02a0 1484#define regMCIF_WB_BUF_3_ADDR_C_HIGH_BASE_IDX 2 1485#define regMCIF_WB_BUF_4_ADDR_Y_HIGH 0x02a1 1486#define regMCIF_WB_BUF_4_ADDR_Y_HIGH_BASE_IDX 2 1487#define regMCIF_WB_BUF_4_ADDR_C_HIGH 0x02a2 1488#define regMCIF_WB_BUF_4_ADDR_C_HIGH_BASE_IDX 2 1489#define regMCIF_WB_BUF_1_RESOLUTION 0x02a3 1490#define regMCIF_WB_BUF_1_RESOLUTION_BASE_IDX 2 1491#define regMCIF_WB_BUF_2_RESOLUTION 0x02a4 1492#define regMCIF_WB_BUF_2_RESOLUTION_BASE_IDX 2 1493#define regMCIF_WB_BUF_3_RESOLUTION 0x02a5 1494#define regMCIF_WB_BUF_3_RESOLUTION_BASE_IDX 2 1495#define regMCIF_WB_BUF_4_RESOLUTION 0x02a6 1496#define regMCIF_WB_BUF_4_RESOLUTION_BASE_IDX 2 1497#define regMCIF_WB_DRAM_SPEED_CHANGE_DURATION_VBI 0x02a7 1498#define regMCIF_WB_DRAM_SPEED_CHANGE_DURATION_VBI_BASE_IDX 2 1499#define regMCIF_WB_VMID_CONTROL 0x02a8 1500#define regMCIF_WB_VMID_CONTROL_BASE_IDX 2 1501#define regMCIF_WB_MIN_TTO 0x02a9 1502#define regMCIF_WB_MIN_TTO_BASE_IDX 2 1503 1504 1505// addressBlock: dce_dc_mmhubbub_mmhubbub_dcperfmon_dc_perfmon_dispdec 1506// base address: 0xd48 1507#define regDC_PERFMON4_PERFCOUNTER_CNTL 0x0352 1508#define regDC_PERFMON4_PERFCOUNTER_CNTL_BASE_IDX 2 1509#define regDC_PERFMON4_PERFCOUNTER_CNTL2 0x0353 1510#define regDC_PERFMON4_PERFCOUNTER_CNTL2_BASE_IDX 2 1511#define regDC_PERFMON4_PERFCOUNTER_STATE 0x0354 1512#define regDC_PERFMON4_PERFCOUNTER_STATE_BASE_IDX 2 1513#define regDC_PERFMON4_PERFMON_CNTL 0x0355 1514#define regDC_PERFMON4_PERFMON_CNTL_BASE_IDX 2 1515#define regDC_PERFMON4_PERFMON_CNTL2 0x0356 1516#define regDC_PERFMON4_PERFMON_CNTL2_BASE_IDX 2 1517#define regDC_PERFMON4_PERFMON_CVALUE_INT_MISC 0x0357 1518#define regDC_PERFMON4_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 1519#define regDC_PERFMON4_PERFMON_CVALUE_LOW 0x0358 1520#define regDC_PERFMON4_PERFMON_CVALUE_LOW_BASE_IDX 2 1521#define regDC_PERFMON4_PERFMON_HI 0x0359 1522#define regDC_PERFMON4_PERFMON_HI_BASE_IDX 2 1523#define regDC_PERFMON4_PERFMON_LOW 0x035a 1524#define regDC_PERFMON4_PERFMON_LOW_BASE_IDX 2 1525 1526 1527// addressBlock: dce_dc_mmhubbub_mmhubbub_dispdec 1528// base address: 0x0 1529#define regMCIF_WB_NB_PSTATE_LATENCY_WATERMARK 0x02aa 1530#define regMCIF_WB_NB_PSTATE_LATENCY_WATERMARK_BASE_IDX 2 1531#define regMCIF_WB_WATERMARK 0x02ab 1532#define regMCIF_WB_WATERMARK_BASE_IDX 2 1533#define regMMHUBBUB_WARMUP_CONFIG 0x02ac 1534#define regMMHUBBUB_WARMUP_CONFIG_BASE_IDX 2 1535#define regMMHUBBUB_WARMUP_CONTROL_STATUS 0x02ad 1536#define regMMHUBBUB_WARMUP_CONTROL_STATUS_BASE_IDX 2 1537#define regMMHUBBUB_WARMUP_BASE_ADDR_LOW 0x02ae 1538#define regMMHUBBUB_WARMUP_BASE_ADDR_LOW_BASE_IDX 2 1539#define regMMHUBBUB_WARMUP_BASE_ADDR_HIGH 0x02af 1540#define regMMHUBBUB_WARMUP_BASE_ADDR_HIGH_BASE_IDX 2 1541#define regMMHUBBUB_WARMUP_ADDR_REGION 0x02b0 1542#define regMMHUBBUB_WARMUP_ADDR_REGION_BASE_IDX 2 1543#define regMMHUBBUB_MIN_TTO 0x02b1 1544#define regMMHUBBUB_MIN_TTO_BASE_IDX 2 1545#define regMMHUBBUB_CTRL 0x0333 1546#define regMMHUBBUB_CTRL_BASE_IDX 2 1547#define regWBIF_SMU_WM_CONTROL 0x0334 1548#define regWBIF_SMU_WM_CONTROL_BASE_IDX 2 1549#define regWBIF0_MISC_CTRL 0x0335 1550#define regWBIF0_MISC_CTRL_BASE_IDX 2 1551#define regWBIF0_PHASE0_OUTSTANDING_COUNTER 0x0336 1552#define regWBIF0_PHASE0_OUTSTANDING_COUNTER_BASE_IDX 2 1553#define regWBIF0_PHASE1_OUTSTANDING_COUNTER 0x0337 1554#define regWBIF0_PHASE1_OUTSTANDING_COUNTER_BASE_IDX 2 1555#define regVGA_SRC_SPLIT_CNTL 0x033e 1556#define regVGA_SRC_SPLIT_CNTL_BASE_IDX 2 1557#define regMMHUBBUB_MEM_PWR_STATUS 0x033f 1558#define regMMHUBBUB_MEM_PWR_STATUS_BASE_IDX 2 1559#define regMMHUBBUB_MEM_PWR_CNTL 0x0340 1560#define regMMHUBBUB_MEM_PWR_CNTL_BASE_IDX 2 1561#define regMMHUBBUB_CLOCK_CNTL 0x0341 1562#define regMMHUBBUB_CLOCK_CNTL_BASE_IDX 2 1563#define regMMHUBBUB_SOFT_RESET 0x0342 1564#define regMMHUBBUB_SOFT_RESET_BASE_IDX 2 1565#define regDMU_IF_ERR_STATUS 0x0346 1566#define regDMU_IF_ERR_STATUS_BASE_IDX 2 1567#define regMMHUBBUB_CLIENT_UNIT_ID 0x0347 1568#define regMMHUBBUB_CLIENT_UNIT_ID_BASE_IDX 2 1569#define regMMHUBBUB_WARMUP_VMID_CONTROL 0x0349 1570#define regMMHUBBUB_WARMUP_VMID_CONTROL_BASE_IDX 2 1571 1572 1573// addressBlock: dce_dc_hda_azf0controller_dispdec 1574// base address: 0x0 1575#define regAZALIA_CONTROLLER_CLOCK_GATING 0x03c2 1576#define regAZALIA_CONTROLLER_CLOCK_GATING_BASE_IDX 2 1577#define regAZALIA_AUDIO_DTO 0x03c3 1578#define regAZALIA_AUDIO_DTO_BASE_IDX 2 1579#define regAZALIA_AUDIO_DTO_CONTROL 0x03c4 1580#define regAZALIA_AUDIO_DTO_CONTROL_BASE_IDX 2 1581#define regAZALIA_SOCCLK_CONTROL 0x03c5 1582#define regAZALIA_SOCCLK_CONTROL_BASE_IDX 2 1583#define regAZALIA_UNDERFLOW_FILLER_SAMPLE 0x03c6 1584#define regAZALIA_UNDERFLOW_FILLER_SAMPLE_BASE_IDX 2 1585#define regAZALIA_DATA_DMA_CONTROL 0x03c7 1586#define regAZALIA_DATA_DMA_CONTROL_BASE_IDX 2 1587#define regAZALIA_BDL_DMA_CONTROL 0x03c8 1588#define regAZALIA_BDL_DMA_CONTROL_BASE_IDX 2 1589#define regAZALIA_RIRB_AND_DP_CONTROL 0x03c9 1590#define regAZALIA_RIRB_AND_DP_CONTROL_BASE_IDX 2 1591#define regAZALIA_CORB_DMA_CONTROL 0x03ca 1592#define regAZALIA_CORB_DMA_CONTROL_BASE_IDX 2 1593#define regAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER 0x03d1 1594#define regAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER_BASE_IDX 2 1595#define regAZALIA_CYCLIC_BUFFER_SYNC 0x03d2 1596#define regAZALIA_CYCLIC_BUFFER_SYNC_BASE_IDX 2 1597#define regAZALIA_GLOBAL_CAPABILITIES 0x03d3 1598#define regAZALIA_GLOBAL_CAPABILITIES_BASE_IDX 2 1599#define regAZALIA_OUTPUT_PAYLOAD_CAPABILITY 0x03d4 1600#define regAZALIA_OUTPUT_PAYLOAD_CAPABILITY_BASE_IDX 2 1601#define regAZALIA_OUTPUT_STREAM_ARBITER_CONTROL 0x03d5 1602#define regAZALIA_OUTPUT_STREAM_ARBITER_CONTROL_BASE_IDX 2 1603#define regAZALIA_INPUT_PAYLOAD_CAPABILITY 0x03d6 1604#define regAZALIA_INPUT_PAYLOAD_CAPABILITY_BASE_IDX 2 1605#define regAZALIA_INPUT_CRC0_CONTROL0 0x03d9 1606#define regAZALIA_INPUT_CRC0_CONTROL0_BASE_IDX 2 1607#define regAZALIA_INPUT_CRC0_CONTROL1 0x03da 1608#define regAZALIA_INPUT_CRC0_CONTROL1_BASE_IDX 2 1609#define regAZALIA_INPUT_CRC0_CONTROL2 0x03db 1610#define regAZALIA_INPUT_CRC0_CONTROL2_BASE_IDX 2 1611#define regAZALIA_INPUT_CRC0_CONTROL3 0x03dc 1612#define regAZALIA_INPUT_CRC0_CONTROL3_BASE_IDX 2 1613#define regAZALIA_INPUT_CRC0_RESULT 0x03dd 1614#define regAZALIA_INPUT_CRC0_RESULT_BASE_IDX 2 1615#define regAZALIA_INPUT_CRC1_CONTROL0 0x03de 1616#define regAZALIA_INPUT_CRC1_CONTROL0_BASE_IDX 2 1617#define regAZALIA_INPUT_CRC1_CONTROL1 0x03df 1618#define regAZALIA_INPUT_CRC1_CONTROL1_BASE_IDX 2 1619#define regAZALIA_INPUT_CRC1_CONTROL2 0x03e0 1620#define regAZALIA_INPUT_CRC1_CONTROL2_BASE_IDX 2 1621#define regAZALIA_INPUT_CRC1_CONTROL3 0x03e1 1622#define regAZALIA_INPUT_CRC1_CONTROL3_BASE_IDX 2 1623#define regAZALIA_INPUT_CRC1_RESULT 0x03e2 1624#define regAZALIA_INPUT_CRC1_RESULT_BASE_IDX 2 1625#define regAZALIA_CRC0_CONTROL0 0x03e3 1626#define regAZALIA_CRC0_CONTROL0_BASE_IDX 2 1627#define regAZALIA_CRC0_CONTROL1 0x03e4 1628#define regAZALIA_CRC0_CONTROL1_BASE_IDX 2 1629#define regAZALIA_CRC0_CONTROL2 0x03e5 1630#define regAZALIA_CRC0_CONTROL2_BASE_IDX 2 1631#define regAZALIA_CRC0_CONTROL3 0x03e6 1632#define regAZALIA_CRC0_CONTROL3_BASE_IDX 2 1633#define regAZALIA_CRC0_RESULT 0x03e7 1634#define regAZALIA_CRC0_RESULT_BASE_IDX 2 1635#define regAZALIA_CRC1_CONTROL0 0x03e8 1636#define regAZALIA_CRC1_CONTROL0_BASE_IDX 2 1637#define regAZALIA_CRC1_CONTROL1 0x03e9 1638#define regAZALIA_CRC1_CONTROL1_BASE_IDX 2 1639#define regAZALIA_CRC1_CONTROL2 0x03ea 1640#define regAZALIA_CRC1_CONTROL2_BASE_IDX 2 1641#define regAZALIA_CRC1_CONTROL3 0x03eb 1642#define regAZALIA_CRC1_CONTROL3_BASE_IDX 2 1643#define regAZALIA_CRC1_RESULT 0x03ec 1644#define regAZALIA_CRC1_RESULT_BASE_IDX 2 1645#define regAZALIA_MEM_PWR_CTRL 0x03ee 1646#define regAZALIA_MEM_PWR_CTRL_BASE_IDX 2 1647#define regAZALIA_MEM_PWR_STATUS 0x03ef 1648#define regAZALIA_MEM_PWR_STATUS_BASE_IDX 2 1649 1650 1651// addressBlock: dce_dc_hda_azf0root_dispdec 1652// base address: 0x0 1653#define regAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID 0x0406 1654#define regAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_BASE_IDX 2 1655#define regAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID 0x0407 1656#define regAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID_BASE_IDX 2 1657#define regAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL 0x0408 1658#define regAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL_BASE_IDX 2 1659#define regAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL 0x0409 1660#define regAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL_BASE_IDX 2 1661#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE 0x040a 1662#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_BASE_IDX 2 1663#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES 0x040b 1664#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES_BASE_IDX 2 1665#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS 0x040c 1666#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_BASE_IDX 2 1667#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES 0x040d 1668#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES_BASE_IDX 2 1669#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE 0x040e 1670#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE_BASE_IDX 2 1671#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET 0x040f 1672#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET_BASE_IDX 2 1673#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID 0x0410 1674#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_BASE_IDX 2 1675#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION 0x0411 1676#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION_BASE_IDX 2 1677#define regCC_RCU_DC_AUDIO_PORT_CONNECTIVITY 0x0412 1678#define regCC_RCU_DC_AUDIO_PORT_CONNECTIVITY_BASE_IDX 2 1679#define regCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY 0x0413 1680#define regCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_BASE_IDX 2 1681#define regAZALIA_F0_GTC_GROUP_OFFSET0 0x0415 1682#define regAZALIA_F0_GTC_GROUP_OFFSET0_BASE_IDX 2 1683#define regAZALIA_F0_GTC_GROUP_OFFSET1 0x0416 1684#define regAZALIA_F0_GTC_GROUP_OFFSET1_BASE_IDX 2 1685#define regAZALIA_F0_GTC_GROUP_OFFSET2 0x0417 1686#define regAZALIA_F0_GTC_GROUP_OFFSET2_BASE_IDX 2 1687#define regAZALIA_F0_GTC_GROUP_OFFSET3 0x0418 1688#define regAZALIA_F0_GTC_GROUP_OFFSET3_BASE_IDX 2 1689#define regAZALIA_F0_GTC_GROUP_OFFSET4 0x0419 1690#define regAZALIA_F0_GTC_GROUP_OFFSET4_BASE_IDX 2 1691#define regAZALIA_F0_GTC_GROUP_OFFSET5 0x041a 1692#define regAZALIA_F0_GTC_GROUP_OFFSET5_BASE_IDX 2 1693#define regAZALIA_F0_GTC_GROUP_OFFSET6 0x041b 1694#define regAZALIA_F0_GTC_GROUP_OFFSET6_BASE_IDX 2 1695#define regREG_DC_AUDIO_PORT_CONNECTIVITY 0x041c 1696#define regREG_DC_AUDIO_PORT_CONNECTIVITY_BASE_IDX 2 1697#define regREG_DC_AUDIO_INPUT_PORT_CONNECTIVITY 0x041d 1698#define regREG_DC_AUDIO_INPUT_PORT_CONNECTIVITY_BASE_IDX 2 1699 1700 1701// addressBlock: dce_dc_hda_az_misc_dispdec 1702// base address: 0x0 1703#define regAZ_CLOCK_CNTL 0x0372 1704#define regAZ_CLOCK_CNTL_BASE_IDX 2 1705 1706 1707// addressBlock: dce_dc_hda_az_dcperfmon_dc_perfmon_dispdec 1708// base address: 0xde8 1709#define regDC_PERFMON5_PERFCOUNTER_CNTL 0x037a 1710#define regDC_PERFMON5_PERFCOUNTER_CNTL_BASE_IDX 2 1711#define regDC_PERFMON5_PERFCOUNTER_CNTL2 0x037b 1712#define regDC_PERFMON5_PERFCOUNTER_CNTL2_BASE_IDX 2 1713#define regDC_PERFMON5_PERFCOUNTER_STATE 0x037c 1714#define regDC_PERFMON5_PERFCOUNTER_STATE_BASE_IDX 2 1715#define regDC_PERFMON5_PERFMON_CNTL 0x037d 1716#define regDC_PERFMON5_PERFMON_CNTL_BASE_IDX 2 1717#define regDC_PERFMON5_PERFMON_CNTL2 0x037e 1718#define regDC_PERFMON5_PERFMON_CNTL2_BASE_IDX 2 1719#define regDC_PERFMON5_PERFMON_CVALUE_INT_MISC 0x037f 1720#define regDC_PERFMON5_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 1721#define regDC_PERFMON5_PERFMON_CVALUE_LOW 0x0380 1722#define regDC_PERFMON5_PERFMON_CVALUE_LOW_BASE_IDX 2 1723#define regDC_PERFMON5_PERFMON_HI 0x0381 1724#define regDC_PERFMON5_PERFMON_HI_BASE_IDX 2 1725#define regDC_PERFMON5_PERFMON_LOW 0x0382 1726#define regDC_PERFMON5_PERFMON_LOW_BASE_IDX 2 1727 1728 1729// addressBlock: dce_dc_hda_azf0stream0_dispdec 1730// base address: 0x0 1731#define regAZF0STREAM0_AZALIA_STREAM_INDEX 0x035e 1732#define regAZF0STREAM0_AZALIA_STREAM_INDEX_BASE_IDX 2 1733#define regAZF0STREAM0_AZALIA_STREAM_DATA 0x035f 1734#define regAZF0STREAM0_AZALIA_STREAM_DATA_BASE_IDX 2 1735 1736 1737// addressBlock: dce_dc_hda_azf0stream1_dispdec 1738// base address: 0x8 1739#define regAZF0STREAM1_AZALIA_STREAM_INDEX 0x0360 1740#define regAZF0STREAM1_AZALIA_STREAM_INDEX_BASE_IDX 2 1741#define regAZF0STREAM1_AZALIA_STREAM_DATA 0x0361 1742#define regAZF0STREAM1_AZALIA_STREAM_DATA_BASE_IDX 2 1743 1744 1745// addressBlock: dce_dc_hda_azf0stream2_dispdec 1746// base address: 0x10 1747#define regAZF0STREAM2_AZALIA_STREAM_INDEX 0x0362 1748#define regAZF0STREAM2_AZALIA_STREAM_INDEX_BASE_IDX 2 1749#define regAZF0STREAM2_AZALIA_STREAM_DATA 0x0363 1750#define regAZF0STREAM2_AZALIA_STREAM_DATA_BASE_IDX 2 1751 1752 1753// addressBlock: dce_dc_hda_azf0stream3_dispdec 1754// base address: 0x18 1755#define regAZF0STREAM3_AZALIA_STREAM_INDEX 0x0364 1756#define regAZF0STREAM3_AZALIA_STREAM_INDEX_BASE_IDX 2 1757#define regAZF0STREAM3_AZALIA_STREAM_DATA 0x0365 1758#define regAZF0STREAM3_AZALIA_STREAM_DATA_BASE_IDX 2 1759 1760 1761// addressBlock: dce_dc_hda_azf0stream4_dispdec 1762// base address: 0x20 1763#define regAZF0STREAM4_AZALIA_STREAM_INDEX 0x0366 1764#define regAZF0STREAM4_AZALIA_STREAM_INDEX_BASE_IDX 2 1765#define regAZF0STREAM4_AZALIA_STREAM_DATA 0x0367 1766#define regAZF0STREAM4_AZALIA_STREAM_DATA_BASE_IDX 2 1767 1768 1769// addressBlock: dce_dc_hda_azf0stream5_dispdec 1770// base address: 0x28 1771#define regAZF0STREAM5_AZALIA_STREAM_INDEX 0x0368 1772#define regAZF0STREAM5_AZALIA_STREAM_INDEX_BASE_IDX 2 1773#define regAZF0STREAM5_AZALIA_STREAM_DATA 0x0369 1774#define regAZF0STREAM5_AZALIA_STREAM_DATA_BASE_IDX 2 1775 1776 1777// addressBlock: dce_dc_hda_azf0stream6_dispdec 1778// base address: 0x30 1779#define regAZF0STREAM6_AZALIA_STREAM_INDEX 0x036a 1780#define regAZF0STREAM6_AZALIA_STREAM_INDEX_BASE_IDX 2 1781#define regAZF0STREAM6_AZALIA_STREAM_DATA 0x036b 1782#define regAZF0STREAM6_AZALIA_STREAM_DATA_BASE_IDX 2 1783 1784 1785// addressBlock: dce_dc_hda_azf0stream7_dispdec 1786// base address: 0x38 1787#define regAZF0STREAM7_AZALIA_STREAM_INDEX 0x036c 1788#define regAZF0STREAM7_AZALIA_STREAM_INDEX_BASE_IDX 2 1789#define regAZF0STREAM7_AZALIA_STREAM_DATA 0x036d 1790#define regAZF0STREAM7_AZALIA_STREAM_DATA_BASE_IDX 2 1791 1792 1793// addressBlock: dce_dc_hda_azf0stream8_dispdec 1794// base address: 0x320 1795#define regAZF0STREAM8_AZALIA_STREAM_INDEX 0x0426 1796#define regAZF0STREAM8_AZALIA_STREAM_INDEX_BASE_IDX 2 1797#define regAZF0STREAM8_AZALIA_STREAM_DATA 0x0427 1798#define regAZF0STREAM8_AZALIA_STREAM_DATA_BASE_IDX 2 1799 1800 1801// addressBlock: dce_dc_hda_azf0stream9_dispdec 1802// base address: 0x328 1803#define regAZF0STREAM9_AZALIA_STREAM_INDEX 0x0428 1804#define regAZF0STREAM9_AZALIA_STREAM_INDEX_BASE_IDX 2 1805#define regAZF0STREAM9_AZALIA_STREAM_DATA 0x0429 1806#define regAZF0STREAM9_AZALIA_STREAM_DATA_BASE_IDX 2 1807 1808 1809// addressBlock: dce_dc_hda_azf0stream10_dispdec 1810// base address: 0x330 1811#define regAZF0STREAM10_AZALIA_STREAM_INDEX 0x042a 1812#define regAZF0STREAM10_AZALIA_STREAM_INDEX_BASE_IDX 2 1813#define regAZF0STREAM10_AZALIA_STREAM_DATA 0x042b 1814#define regAZF0STREAM10_AZALIA_STREAM_DATA_BASE_IDX 2 1815 1816 1817// addressBlock: dce_dc_hda_azf0stream11_dispdec 1818// base address: 0x338 1819#define regAZF0STREAM11_AZALIA_STREAM_INDEX 0x042c 1820#define regAZF0STREAM11_AZALIA_STREAM_INDEX_BASE_IDX 2 1821#define regAZF0STREAM11_AZALIA_STREAM_DATA 0x042d 1822#define regAZF0STREAM11_AZALIA_STREAM_DATA_BASE_IDX 2 1823 1824 1825// addressBlock: dce_dc_hda_azf0stream12_dispdec 1826// base address: 0x340 1827#define regAZF0STREAM12_AZALIA_STREAM_INDEX 0x042e 1828#define regAZF0STREAM12_AZALIA_STREAM_INDEX_BASE_IDX 2 1829#define regAZF0STREAM12_AZALIA_STREAM_DATA 0x042f 1830#define regAZF0STREAM12_AZALIA_STREAM_DATA_BASE_IDX 2 1831 1832 1833// addressBlock: dce_dc_hda_azf0stream13_dispdec 1834// base address: 0x348 1835#define regAZF0STREAM13_AZALIA_STREAM_INDEX 0x0430 1836#define regAZF0STREAM13_AZALIA_STREAM_INDEX_BASE_IDX 2 1837#define regAZF0STREAM13_AZALIA_STREAM_DATA 0x0431 1838#define regAZF0STREAM13_AZALIA_STREAM_DATA_BASE_IDX 2 1839 1840 1841// addressBlock: dce_dc_hda_azf0stream14_dispdec 1842// base address: 0x350 1843#define regAZF0STREAM14_AZALIA_STREAM_INDEX 0x0432 1844#define regAZF0STREAM14_AZALIA_STREAM_INDEX_BASE_IDX 2 1845#define regAZF0STREAM14_AZALIA_STREAM_DATA 0x0433 1846#define regAZF0STREAM14_AZALIA_STREAM_DATA_BASE_IDX 2 1847 1848 1849// addressBlock: dce_dc_hda_azf0stream15_dispdec 1850// base address: 0x358 1851#define regAZF0STREAM15_AZALIA_STREAM_INDEX 0x0434 1852#define regAZF0STREAM15_AZALIA_STREAM_INDEX_BASE_IDX 2 1853#define regAZF0STREAM15_AZALIA_STREAM_DATA 0x0435 1854#define regAZF0STREAM15_AZALIA_STREAM_DATA_BASE_IDX 2 1855 1856 1857// addressBlock: dce_dc_hda_azf0endpoint0_dispdec 1858// base address: 0x0 1859#define regAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x0386 1860#define regAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 1861#define regAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA 0x0387 1862#define regAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 1863 1864 1865// addressBlock: dce_dc_hda_azf0endpoint1_dispdec 1866// base address: 0x18 1867#define regAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x038c 1868#define regAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 1869#define regAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA 0x038d 1870#define regAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 1871 1872 1873// addressBlock: dce_dc_hda_azf0endpoint2_dispdec 1874// base address: 0x30 1875#define regAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x0392 1876#define regAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 1877#define regAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA 0x0393 1878#define regAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 1879 1880 1881// addressBlock: dce_dc_hda_azf0endpoint3_dispdec 1882// base address: 0x48 1883#define regAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x0398 1884#define regAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 1885#define regAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA 0x0399 1886#define regAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 1887 1888 1889// addressBlock: dce_dc_hda_azf0endpoint4_dispdec 1890// base address: 0x60 1891#define regAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x039e 1892#define regAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 1893#define regAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA 0x039f 1894#define regAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 1895 1896 1897// addressBlock: dce_dc_hda_azf0endpoint5_dispdec 1898// base address: 0x78 1899#define regAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x03a4 1900#define regAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 1901#define regAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA 0x03a5 1902#define regAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 1903 1904 1905// addressBlock: dce_dc_hda_azf0endpoint6_dispdec 1906// base address: 0x90 1907#define regAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x03aa 1908#define regAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 1909#define regAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA 0x03ab 1910#define regAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 1911 1912 1913// addressBlock: dce_dc_hda_azf0endpoint7_dispdec 1914// base address: 0xa8 1915#define regAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x03b0 1916#define regAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 1917#define regAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA 0x03b1 1918#define regAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 1919 1920 1921// addressBlock: dce_dc_hda_azf0inputendpoint0_dispdec 1922// base address: 0x0 1923#define regAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x043a 1924#define regAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 1925#define regAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x043b 1926#define regAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 1927 1928 1929// addressBlock: dce_dc_hda_azf0inputendpoint1_dispdec 1930// base address: 0x10 1931#define regAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x043e 1932#define regAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 1933#define regAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x043f 1934#define regAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 1935 1936 1937// addressBlock: dce_dc_hda_azf0inputendpoint2_dispdec 1938// base address: 0x20 1939#define regAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0442 1940#define regAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 1941#define regAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0443 1942#define regAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 1943 1944 1945// addressBlock: dce_dc_hda_azf0inputendpoint3_dispdec 1946// base address: 0x30 1947#define regAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0446 1948#define regAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 1949#define regAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0447 1950#define regAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 1951 1952 1953// addressBlock: dce_dc_hda_azf0inputendpoint4_dispdec 1954// base address: 0x40 1955#define regAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x044a 1956#define regAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 1957#define regAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x044b 1958#define regAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 1959 1960 1961// addressBlock: dce_dc_hda_azf0inputendpoint5_dispdec 1962// base address: 0x50 1963#define regAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x044e 1964#define regAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 1965#define regAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x044f 1966#define regAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 1967 1968 1969// addressBlock: dce_dc_hda_azf0inputendpoint6_dispdec 1970// base address: 0x60 1971#define regAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0452 1972#define regAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 1973#define regAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0453 1974#define regAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 1975 1976 1977// addressBlock: dce_dc_hda_azf0inputendpoint7_dispdec 1978// base address: 0x70 1979#define regAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0456 1980#define regAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 1981#define regAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0457 1982#define regAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 1983 1984 1985// addressBlock: dce_dc_dchubbubl_hubbub_dispdec 1986// base address: 0x0 1987#define regDCHUBBUB_ARB_DF_REQ_OUTSTAND 0x04f9 1988#define regDCHUBBUB_ARB_DF_REQ_OUTSTAND_BASE_IDX 2 1989#define regDCHUBBUB_ARB_SAT_LEVEL 0x04fa 1990#define regDCHUBBUB_ARB_SAT_LEVEL_BASE_IDX 2 1991#define regDCHUBBUB_ARB_QOS_FORCE 0x04fb 1992#define regDCHUBBUB_ARB_QOS_FORCE_BASE_IDX 2 1993#define regDCHUBBUB_ARB_DRAM_STATE_CNTL 0x04fc 1994#define regDCHUBBUB_ARB_DRAM_STATE_CNTL_BASE_IDX 2 1995#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A 0x04fd 1996#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A_BASE_IDX 2 1997#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A 0x04fe 1998#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A_BASE_IDX 2 1999#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A 0x04ff 2000#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A_BASE_IDX 2 2001#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_A 0x0500 2002#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_A_BASE_IDX 2 2003#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A 0x0501 2004#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A_BASE_IDX 2 2005#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_A 0x0502 2006#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_A_BASE_IDX 2 2007#define regDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A 0x0503 2008#define regDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A_BASE_IDX 2 2009#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_A 0x0504 2010#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_A_BASE_IDX 2 2011#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_A 0x0505 2012#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_A_BASE_IDX 2 2013#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B 0x0506 2014#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B_BASE_IDX 2 2015#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B 0x0507 2016#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B_BASE_IDX 2 2017#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B 0x0508 2018#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B_BASE_IDX 2 2019#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_B 0x0509 2020#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_B_BASE_IDX 2 2021#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B 0x050a 2022#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B_BASE_IDX 2 2023#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_B 0x050b 2024#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_B_BASE_IDX 2 2025#define regDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B 0x050c 2026#define regDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B_BASE_IDX 2 2027#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_B 0x050d 2028#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_B_BASE_IDX 2 2029#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_B 0x050e 2030#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_B_BASE_IDX 2 2031#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C 0x050f 2032#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C_BASE_IDX 2 2033#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C 0x0510 2034#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C_BASE_IDX 2 2035#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C 0x0511 2036#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C_BASE_IDX 2 2037#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_C 0x0512 2038#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_C_BASE_IDX 2 2039#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C 0x0513 2040#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C_BASE_IDX 2 2041#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_C 0x0514 2042#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_C_BASE_IDX 2 2043#define regDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C 0x0515 2044#define regDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C_BASE_IDX 2 2045#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_C 0x0516 2046#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_C_BASE_IDX 2 2047#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_C 0x0517 2048#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_C_BASE_IDX 2 2049#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D 0x0518 2050#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D_BASE_IDX 2 2051#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D 0x0519 2052#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D_BASE_IDX 2 2053#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D 0x051a 2054#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D_BASE_IDX 2 2055#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_D 0x051b 2056#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_D_BASE_IDX 2 2057#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D 0x051c 2058#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D_BASE_IDX 2 2059#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_D 0x051d 2060#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_D_BASE_IDX 2 2061#define regDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D 0x051e 2062#define regDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D_BASE_IDX 2 2063#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_D 0x051f 2064#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_D_BASE_IDX 2 2065#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_D 0x0520 2066#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_D_BASE_IDX 2 2067#define regDCHUBBUB_ARB_HOSTVM_CNTL 0x0521 2068#define regDCHUBBUB_ARB_HOSTVM_CNTL_BASE_IDX 2 2069#define regDCHUBBUB_ARB_WATERMARK_CHANGE_CNTL 0x0522 2070#define regDCHUBBUB_ARB_WATERMARK_CHANGE_CNTL_BASE_IDX 2 2071#define regDCHUBBUB_ARB_TIMEOUT_ENABLE 0x0523 2072#define regDCHUBBUB_ARB_TIMEOUT_ENABLE_BASE_IDX 2 2073#define regDCHUBBUB_GLOBAL_TIMER_CNTL 0x0524 2074#define regDCHUBBUB_GLOBAL_TIMER_CNTL_BASE_IDX 2 2075#define regSURFACE_CHECK0_ADDRESS_LSB 0x0525 2076#define regSURFACE_CHECK0_ADDRESS_LSB_BASE_IDX 2 2077#define regSURFACE_CHECK0_ADDRESS_MSB 0x0526 2078#define regSURFACE_CHECK0_ADDRESS_MSB_BASE_IDX 2 2079#define regSURFACE_CHECK1_ADDRESS_LSB 0x0527 2080#define regSURFACE_CHECK1_ADDRESS_LSB_BASE_IDX 2 2081#define regSURFACE_CHECK1_ADDRESS_MSB 0x0528 2082#define regSURFACE_CHECK1_ADDRESS_MSB_BASE_IDX 2 2083#define regSURFACE_CHECK2_ADDRESS_LSB 0x0529 2084#define regSURFACE_CHECK2_ADDRESS_LSB_BASE_IDX 2 2085#define regSURFACE_CHECK2_ADDRESS_MSB 0x052a 2086#define regSURFACE_CHECK2_ADDRESS_MSB_BASE_IDX 2 2087#define regSURFACE_CHECK3_ADDRESS_LSB 0x052b 2088#define regSURFACE_CHECK3_ADDRESS_LSB_BASE_IDX 2 2089#define regSURFACE_CHECK3_ADDRESS_MSB 0x052c 2090#define regSURFACE_CHECK3_ADDRESS_MSB_BASE_IDX 2 2091#define regVTG0_CONTROL 0x052d 2092#define regVTG0_CONTROL_BASE_IDX 2 2093#define regVTG1_CONTROL 0x052e 2094#define regVTG1_CONTROL_BASE_IDX 2 2095#define regVTG2_CONTROL 0x052f 2096#define regVTG2_CONTROL_BASE_IDX 2 2097#define regVTG3_CONTROL 0x0530 2098#define regVTG3_CONTROL_BASE_IDX 2 2099#define regDCHUBBUB_SOFT_RESET 0x0531 2100#define regDCHUBBUB_SOFT_RESET_BASE_IDX 2 2101#define regDCHUBBUB_CLOCK_CNTL 0x0532 2102#define regDCHUBBUB_CLOCK_CNTL_BASE_IDX 2 2103#define regDCFCLK_CNTL 0x0533 2104#define regDCFCLK_CNTL_BASE_IDX 2 2105#define regDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL 0x0534 2106#define regDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL_BASE_IDX 2 2107#define regDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2 0x0535 2108#define regDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2_BASE_IDX 2 2109#define regDCHUBBUB_VLINE_SNAPSHOT 0x0536 2110#define regDCHUBBUB_VLINE_SNAPSHOT_BASE_IDX 2 2111#define regDCHUBBUB_CTRL_STATUS 0x0537 2112#define regDCHUBBUB_CTRL_STATUS_BASE_IDX 2 2113#define regDCHUBBUB_TIMEOUT_DETECTION_CTRL1 0x053d 2114#define regDCHUBBUB_TIMEOUT_DETECTION_CTRL1_BASE_IDX 2 2115#define regDCHUBBUB_TIMEOUT_DETECTION_CTRL2 0x053e 2116#define regDCHUBBUB_TIMEOUT_DETECTION_CTRL2_BASE_IDX 2 2117#define regDCHUBBUB_TIMEOUT_INTERRUPT_STATUS 0x053f 2118#define regDCHUBBUB_TIMEOUT_INTERRUPT_STATUS_BASE_IDX 2 2119#define regFMON_CTRL 0x0540 2120#define regFMON_CTRL_BASE_IDX 2 2121#define regDCHUBBUB_TEST_DEBUG_INDEX 0x0541 2122#define regDCHUBBUB_TEST_DEBUG_INDEX_BASE_IDX 2 2123#define regDCHUBBUB_TEST_DEBUG_DATA 0x0542 2124#define regDCHUBBUB_TEST_DEBUG_DATA_BASE_IDX 2 2125 2126 2127// addressBlock: dce_dc_dchubbubl_hubbub_sdpif_dispdec 2128// base address: 0x0 2129#define regDCHUBBUB_SDPIF_CFG0 0x046f 2130#define regDCHUBBUB_SDPIF_CFG0_BASE_IDX 2 2131#define regDCHUBBUB_SDPIF_CFG1 0x0470 2132#define regDCHUBBUB_SDPIF_CFG1_BASE_IDX 2 2133#define regDCHUBBUB_SDPIF_CFG2 0x0471 2134#define regDCHUBBUB_SDPIF_CFG2_BASE_IDX 2 2135#define regVM_REQUEST_PHYSICAL 0x0472 2136#define regVM_REQUEST_PHYSICAL_BASE_IDX 2 2137#define regDCHUBBUB_FORCE_IO_STATUS_0 0x0473 2138#define regDCHUBBUB_FORCE_IO_STATUS_0_BASE_IDX 2 2139#define regDCHUBBUB_FORCE_IO_STATUS_1 0x0474 2140#define regDCHUBBUB_FORCE_IO_STATUS_1_BASE_IDX 2 2141#define regDCN_VM_FB_LOCATION_BASE 0x0475 2142#define regDCN_VM_FB_LOCATION_BASE_BASE_IDX 2 2143#define regDCN_VM_FB_LOCATION_TOP 0x0476 2144#define regDCN_VM_FB_LOCATION_TOP_BASE_IDX 2 2145#define regDCN_VM_FB_OFFSET 0x0477 2146#define regDCN_VM_FB_OFFSET_BASE_IDX 2 2147#define regDCN_VM_AGP_BOT 0x0478 2148#define regDCN_VM_AGP_BOT_BASE_IDX 2 2149#define regDCN_VM_AGP_TOP 0x0479 2150#define regDCN_VM_AGP_TOP_BASE_IDX 2 2151#define regDCN_VM_AGP_BASE 0x047a 2152#define regDCN_VM_AGP_BASE_BASE_IDX 2 2153#define regDCN_VM_LOCAL_HBM_ADDRESS_START 0x047b 2154#define regDCN_VM_LOCAL_HBM_ADDRESS_START_BASE_IDX 2 2155#define regDCN_VM_LOCAL_HBM_ADDRESS_END 0x047c 2156#define regDCN_VM_LOCAL_HBM_ADDRESS_END_BASE_IDX 2 2157#define regDCN_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL 0x047d 2158#define regDCN_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL_BASE_IDX 2 2159#define regDCHUBBUB_SDPIF_MEM_PWR_CTRL 0x0483 2160#define regDCHUBBUB_SDPIF_MEM_PWR_CTRL_BASE_IDX 2 2161#define regDCHUBBUB_SDPIF_MEM_PWR_STATUS 0x0484 2162#define regDCHUBBUB_SDPIF_MEM_PWR_STATUS_BASE_IDX 2 2163 2164 2165// addressBlock: dce_dc_dchubbubl_hubbub_ret_path_dispdec 2166// base address: 0x0 2167#define regDCHUBBUB_RET_PATH_DCC_CFG 0x04af 2168#define regDCHUBBUB_RET_PATH_DCC_CFG_BASE_IDX 2 2169#define regDCHUBBUB_RET_PATH_DCC_CFG0_0 0x04b0 2170#define regDCHUBBUB_RET_PATH_DCC_CFG0_0_BASE_IDX 2 2171#define regDCHUBBUB_RET_PATH_DCC_CFG0_1 0x04b1 2172#define regDCHUBBUB_RET_PATH_DCC_CFG0_1_BASE_IDX 2 2173#define regDCHUBBUB_RET_PATH_DCC_CFG1_0 0x04b2 2174#define regDCHUBBUB_RET_PATH_DCC_CFG1_0_BASE_IDX 2 2175#define regDCHUBBUB_RET_PATH_DCC_CFG1_1 0x04b3 2176#define regDCHUBBUB_RET_PATH_DCC_CFG1_1_BASE_IDX 2 2177#define regDCHUBBUB_RET_PATH_DCC_CFG2_0 0x04b4 2178#define regDCHUBBUB_RET_PATH_DCC_CFG2_0_BASE_IDX 2 2179#define regDCHUBBUB_RET_PATH_DCC_CFG2_1 0x04b5 2180#define regDCHUBBUB_RET_PATH_DCC_CFG2_1_BASE_IDX 2 2181#define regDCHUBBUB_RET_PATH_DCC_CFG3_0 0x04b6 2182#define regDCHUBBUB_RET_PATH_DCC_CFG3_0_BASE_IDX 2 2183#define regDCHUBBUB_RET_PATH_DCC_CFG3_1 0x04b7 2184#define regDCHUBBUB_RET_PATH_DCC_CFG3_1_BASE_IDX 2 2185#define regDCHUBBUB_RET_PATH_DCC_CFG4_0 0x04b8 2186#define regDCHUBBUB_RET_PATH_DCC_CFG4_0_BASE_IDX 2 2187#define regDCHUBBUB_RET_PATH_DCC_CFG4_1 0x04b9 2188#define regDCHUBBUB_RET_PATH_DCC_CFG4_1_BASE_IDX 2 2189#define regDCHUBBUB_RET_PATH_DCC_CFG5_0 0x04ba 2190#define regDCHUBBUB_RET_PATH_DCC_CFG5_0_BASE_IDX 2 2191#define regDCHUBBUB_RET_PATH_DCC_CFG5_1 0x04bb 2192#define regDCHUBBUB_RET_PATH_DCC_CFG5_1_BASE_IDX 2 2193#define regDCHUBBUB_RET_PATH_DCC_CFG6_0 0x04bc 2194#define regDCHUBBUB_RET_PATH_DCC_CFG6_0_BASE_IDX 2 2195#define regDCHUBBUB_RET_PATH_DCC_CFG6_1 0x04bd 2196#define regDCHUBBUB_RET_PATH_DCC_CFG6_1_BASE_IDX 2 2197#define regDCHUBBUB_RET_PATH_DCC_CFG7_0 0x04be 2198#define regDCHUBBUB_RET_PATH_DCC_CFG7_0_BASE_IDX 2 2199#define regDCHUBBUB_RET_PATH_DCC_CFG7_1 0x04bf 2200#define regDCHUBBUB_RET_PATH_DCC_CFG7_1_BASE_IDX 2 2201#define regDCHUBBUB_RET_PATH_MEM_PWR_CTRL 0x04c0 2202#define regDCHUBBUB_RET_PATH_MEM_PWR_CTRL_BASE_IDX 2 2203#define regDCHUBBUB_RET_PATH_MEM_PWR_STATUS 0x04c1 2204#define regDCHUBBUB_RET_PATH_MEM_PWR_STATUS_BASE_IDX 2 2205#define regDCHUBBUB_CRC_CTRL 0x04c2 2206#define regDCHUBBUB_CRC_CTRL_BASE_IDX 2 2207#define regDCHUBBUB_CRC0_VAL_R_G 0x04c3 2208#define regDCHUBBUB_CRC0_VAL_R_G_BASE_IDX 2 2209#define regDCHUBBUB_CRC0_VAL_B_A 0x04c4 2210#define regDCHUBBUB_CRC0_VAL_B_A_BASE_IDX 2 2211#define regDCHUBBUB_CRC1_VAL_R_G 0x04c5 2212#define regDCHUBBUB_CRC1_VAL_R_G_BASE_IDX 2 2213#define regDCHUBBUB_CRC1_VAL_B_A 0x04c6 2214#define regDCHUBBUB_CRC1_VAL_B_A_BASE_IDX 2 2215#define regDCHUBBUB_DCC_STAT_CNTL 0x04c7 2216#define regDCHUBBUB_DCC_STAT_CNTL_BASE_IDX 2 2217#define regDCHUBBUB_DCC_STAT0 0x04c8 2218#define regDCHUBBUB_DCC_STAT0_BASE_IDX 2 2219#define regDCHUBBUB_DCC_STAT1 0x04c9 2220#define regDCHUBBUB_DCC_STAT1_BASE_IDX 2 2221#define regDCHUBBUB_DCC_STAT2 0x04ca 2222#define regDCHUBBUB_DCC_STAT2_BASE_IDX 2 2223#define regDCHUBBUB_COMPBUF_CTRL 0x04cb 2224#define regDCHUBBUB_COMPBUF_CTRL_BASE_IDX 2 2225#define regDCHUBBUB_DET0_CTRL 0x04cc 2226#define regDCHUBBUB_DET0_CTRL_BASE_IDX 2 2227#define regDCHUBBUB_DET1_CTRL 0x04cd 2228#define regDCHUBBUB_DET1_CTRL_BASE_IDX 2 2229#define regDCHUBBUB_DET2_CTRL 0x04ce 2230#define regDCHUBBUB_DET2_CTRL_BASE_IDX 2 2231#define regDCHUBBUB_DET3_CTRL 0x04cf 2232#define regDCHUBBUB_DET3_CTRL_BASE_IDX 2 2233#define regDCHUBBUB_MEM_PWR_MODE_CTRL 0x04d1 2234#define regDCHUBBUB_MEM_PWR_MODE_CTRL_BASE_IDX 2 2235#define regCOMPBUF_MEM_PWR_CTRL_1 0x04d2 2236#define regCOMPBUF_MEM_PWR_CTRL_1_BASE_IDX 2 2237#define regCOMPBUF_MEM_PWR_CTRL_2 0x04d3 2238#define regCOMPBUF_MEM_PWR_CTRL_2_BASE_IDX 2 2239#define regDCHUBBUB_MEM_PWR_STATUS 0x04d4 2240#define regDCHUBBUB_MEM_PWR_STATUS_BASE_IDX 2 2241#define regCOMPBUF_RESERVED_SPACE 0x04d5 2242#define regCOMPBUF_RESERVED_SPACE_BASE_IDX 2 2243 2244 2245// addressBlock: dce_dc_dchubbubl_hubbub_vmrq_if_dispdec 2246// base address: 0x0 2247#define regDCN_VM_CONTEXT0_CNTL 0x0559 2248#define regDCN_VM_CONTEXT0_CNTL_BASE_IDX 2 2249#define regDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 0x055a 2250#define regDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 2251#define regDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 0x055b 2252#define regDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 2253#define regDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 0x055c 2254#define regDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 2255#define regDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 0x055d 2256#define regDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 2257#define regDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 0x055e 2258#define regDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 2259#define regDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 0x055f 2260#define regDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 2261#define regDCN_VM_CONTEXT1_CNTL 0x0560 2262#define regDCN_VM_CONTEXT1_CNTL_BASE_IDX 2 2263#define regDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32 0x0561 2264#define regDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 2265#define regDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 0x0562 2266#define regDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 2267#define regDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32 0x0563 2268#define regDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 2269#define regDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32 0x0564 2270#define regDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 2271#define regDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32 0x0565 2272#define regDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 2273#define regDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32 0x0566 2274#define regDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 2275#define regDCN_VM_CONTEXT2_CNTL 0x0567 2276#define regDCN_VM_CONTEXT2_CNTL_BASE_IDX 2 2277#define regDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32 0x0568 2278#define regDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 2279#define regDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32 0x0569 2280#define regDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 2281#define regDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32 0x056a 2282#define regDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 2283#define regDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32 0x056b 2284#define regDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 2285#define regDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32 0x056c 2286#define regDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 2287#define regDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32 0x056d 2288#define regDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 2289#define regDCN_VM_CONTEXT3_CNTL 0x056e 2290#define regDCN_VM_CONTEXT3_CNTL_BASE_IDX 2 2291#define regDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32 0x056f 2292#define regDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 2293#define regDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32 0x0570 2294#define regDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 2295#define regDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32 0x0571 2296#define regDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 2297#define regDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32 0x0572 2298#define regDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 2299#define regDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32 0x0573 2300#define regDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 2301#define regDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32 0x0574 2302#define regDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 2303#define regDCN_VM_CONTEXT4_CNTL 0x0575 2304#define regDCN_VM_CONTEXT4_CNTL_BASE_IDX 2 2305#define regDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32 0x0576 2306#define regDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 2307#define regDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32 0x0577 2308#define regDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 2309#define regDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32 0x0578 2310#define regDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 2311#define regDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32 0x0579 2312#define regDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 2313#define regDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32 0x057a 2314#define regDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 2315#define regDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32 0x057b 2316#define regDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 2317#define regDCN_VM_CONTEXT5_CNTL 0x057c 2318#define regDCN_VM_CONTEXT5_CNTL_BASE_IDX 2 2319#define regDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32 0x057d 2320#define regDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 2321#define regDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32 0x057e 2322#define regDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 2323#define regDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32 0x057f 2324#define regDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 2325#define regDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32 0x0580 2326#define regDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 2327#define regDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32 0x0581 2328#define regDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 2329#define regDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32 0x0582 2330#define regDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 2331#define regDCN_VM_CONTEXT6_CNTL 0x0583 2332#define regDCN_VM_CONTEXT6_CNTL_BASE_IDX 2 2333#define regDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32 0x0584 2334#define regDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 2335#define regDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32 0x0585 2336#define regDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 2337#define regDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32 0x0586 2338#define regDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 2339#define regDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32 0x0587 2340#define regDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 2341#define regDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32 0x0588 2342#define regDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 2343#define regDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32 0x0589 2344#define regDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 2345#define regDCN_VM_CONTEXT7_CNTL 0x058a 2346#define regDCN_VM_CONTEXT7_CNTL_BASE_IDX 2 2347#define regDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32 0x058b 2348#define regDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 2349#define regDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32 0x058c 2350#define regDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 2351#define regDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32 0x058d 2352#define regDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 2353#define regDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32 0x058e 2354#define regDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 2355#define regDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32 0x058f 2356#define regDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 2357#define regDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32 0x0590 2358#define regDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 2359#define regDCN_VM_CONTEXT8_CNTL 0x0591 2360#define regDCN_VM_CONTEXT8_CNTL_BASE_IDX 2 2361#define regDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32 0x0592 2362#define regDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 2363#define regDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32 0x0593 2364#define regDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 2365#define regDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32 0x0594 2366#define regDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 2367#define regDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32 0x0595 2368#define regDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 2369#define regDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32 0x0596 2370#define regDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 2371#define regDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32 0x0597 2372#define regDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 2373#define regDCN_VM_CONTEXT9_CNTL 0x0598 2374#define regDCN_VM_CONTEXT9_CNTL_BASE_IDX 2 2375#define regDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32 0x0599 2376#define regDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 2377#define regDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32 0x059a 2378#define regDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 2379#define regDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32 0x059b 2380#define regDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 2381#define regDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32 0x059c 2382#define regDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 2383#define regDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32 0x059d 2384#define regDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 2385#define regDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32 0x059e 2386#define regDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 2387#define regDCN_VM_CONTEXT10_CNTL 0x059f 2388#define regDCN_VM_CONTEXT10_CNTL_BASE_IDX 2 2389#define regDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32 0x05a0 2390#define regDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 2391#define regDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32 0x05a1 2392#define regDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 2393#define regDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32 0x05a2 2394#define regDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 2395#define regDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32 0x05a3 2396#define regDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 2397#define regDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32 0x05a4 2398#define regDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 2399#define regDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32 0x05a5 2400#define regDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 2401#define regDCN_VM_CONTEXT11_CNTL 0x05a6 2402#define regDCN_VM_CONTEXT11_CNTL_BASE_IDX 2 2403#define regDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32 0x05a7 2404#define regDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 2405#define regDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32 0x05a8 2406#define regDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 2407#define regDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32 0x05a9 2408#define regDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 2409#define regDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32 0x05aa 2410#define regDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 2411#define regDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32 0x05ab 2412#define regDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 2413#define regDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32 0x05ac 2414#define regDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 2415#define regDCN_VM_CONTEXT12_CNTL 0x05ad 2416#define regDCN_VM_CONTEXT12_CNTL_BASE_IDX 2 2417#define regDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32 0x05ae 2418#define regDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 2419#define regDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32 0x05af 2420#define regDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 2421#define regDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32 0x05b0 2422#define regDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 2423#define regDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32 0x05b1 2424#define regDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 2425#define regDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32 0x05b2 2426#define regDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 2427#define regDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32 0x05b3 2428#define regDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 2429#define regDCN_VM_CONTEXT13_CNTL 0x05b4 2430#define regDCN_VM_CONTEXT13_CNTL_BASE_IDX 2 2431#define regDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32 0x05b5 2432#define regDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 2433#define regDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32 0x05b6 2434#define regDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 2435#define regDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32 0x05b7 2436#define regDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 2437#define regDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32 0x05b8 2438#define regDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 2439#define regDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32 0x05b9 2440#define regDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 2441#define regDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32 0x05ba 2442#define regDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 2443#define regDCN_VM_CONTEXT14_CNTL 0x05bb 2444#define regDCN_VM_CONTEXT14_CNTL_BASE_IDX 2 2445#define regDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32 0x05bc 2446#define regDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 2447#define regDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32 0x05bd 2448#define regDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 2449#define regDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32 0x05be 2450#define regDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 2451#define regDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32 0x05bf 2452#define regDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 2453#define regDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32 0x05c0 2454#define regDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 2455#define regDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32 0x05c1 2456#define regDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 2457#define regDCN_VM_CONTEXT15_CNTL 0x05c2 2458#define regDCN_VM_CONTEXT15_CNTL_BASE_IDX 2 2459#define regDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32 0x05c3 2460#define regDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 2461#define regDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32 0x05c4 2462#define regDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 2463#define regDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32 0x05c5 2464#define regDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 2465#define regDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32 0x05c6 2466#define regDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 2467#define regDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32 0x05c7 2468#define regDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 2469#define regDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32 0x05c8 2470#define regDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 2471#define regDCN_VM_DEFAULT_ADDR_MSB 0x05c9 2472#define regDCN_VM_DEFAULT_ADDR_MSB_BASE_IDX 2 2473#define regDCN_VM_DEFAULT_ADDR_LSB 0x05ca 2474#define regDCN_VM_DEFAULT_ADDR_LSB_BASE_IDX 2 2475#define regDCN_VM_FAULT_CNTL 0x05cb 2476#define regDCN_VM_FAULT_CNTL_BASE_IDX 2 2477#define regDCN_VM_FAULT_STATUS 0x05cc 2478#define regDCN_VM_FAULT_STATUS_BASE_IDX 2 2479#define regDCN_VM_FAULT_ADDR_MSB 0x05cd 2480#define regDCN_VM_FAULT_ADDR_MSB_BASE_IDX 2 2481#define regDCN_VM_FAULT_ADDR_LSB 0x05ce 2482#define regDCN_VM_FAULT_ADDR_LSB_BASE_IDX 2 2483 2484 2485// addressBlock: dce_dc_dchubbubl_dchubbub_dcperfmon_dc_perfmon_dispdec 2486// base address: 0x1534 2487#define regDC_PERFMON6_PERFCOUNTER_CNTL 0x054d 2488#define regDC_PERFMON6_PERFCOUNTER_CNTL_BASE_IDX 2 2489#define regDC_PERFMON6_PERFCOUNTER_CNTL2 0x054e 2490#define regDC_PERFMON6_PERFCOUNTER_CNTL2_BASE_IDX 2 2491#define regDC_PERFMON6_PERFCOUNTER_STATE 0x054f 2492#define regDC_PERFMON6_PERFCOUNTER_STATE_BASE_IDX 2 2493#define regDC_PERFMON6_PERFMON_CNTL 0x0550 2494#define regDC_PERFMON6_PERFMON_CNTL_BASE_IDX 2 2495#define regDC_PERFMON6_PERFMON_CNTL2 0x0551 2496#define regDC_PERFMON6_PERFMON_CNTL2_BASE_IDX 2 2497#define regDC_PERFMON6_PERFMON_CVALUE_INT_MISC 0x0552 2498#define regDC_PERFMON6_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 2499#define regDC_PERFMON6_PERFMON_CVALUE_LOW 0x0553 2500#define regDC_PERFMON6_PERFMON_CVALUE_LOW_BASE_IDX 2 2501#define regDC_PERFMON6_PERFMON_HI 0x0554 2502#define regDC_PERFMON6_PERFMON_HI_BASE_IDX 2 2503#define regDC_PERFMON6_PERFMON_LOW 0x0555 2504#define regDC_PERFMON6_PERFMON_LOW_BASE_IDX 2 2505 2506 2507// addressBlock: dce_dc_dcbubp0_dispdec_hubp_dispdec 2508// base address: 0x0 2509#define regHUBP0_DCSURF_SURFACE_CONFIG 0x05e5 2510#define regHUBP0_DCSURF_SURFACE_CONFIG_BASE_IDX 2 2511#define regHUBP0_DCSURF_ADDR_CONFIG 0x05e6 2512#define regHUBP0_DCSURF_ADDR_CONFIG_BASE_IDX 2 2513#define regHUBP0_DCSURF_TILING_CONFIG 0x05e7 2514#define regHUBP0_DCSURF_TILING_CONFIG_BASE_IDX 2 2515#define regHUBP0_DCSURF_PRI_VIEWPORT_START 0x05e9 2516#define regHUBP0_DCSURF_PRI_VIEWPORT_START_BASE_IDX 2 2517#define regHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION 0x05ea 2518#define regHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2 2519#define regHUBP0_DCSURF_PRI_VIEWPORT_START_C 0x05eb 2520#define regHUBP0_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX 2 2521#define regHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C 0x05ec 2522#define regHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX 2 2523#define regHUBP0_DCSURF_SEC_VIEWPORT_START 0x05ed 2524#define regHUBP0_DCSURF_SEC_VIEWPORT_START_BASE_IDX 2 2525#define regHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION 0x05ee 2526#define regHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX 2 2527#define regHUBP0_DCSURF_SEC_VIEWPORT_START_C 0x05ef 2528#define regHUBP0_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX 2 2529#define regHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C 0x05f0 2530#define regHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX 2 2531#define regHUBP0_DCHUBP_REQ_SIZE_CONFIG 0x05f1 2532#define regHUBP0_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX 2 2533#define regHUBP0_DCHUBP_REQ_SIZE_CONFIG_C 0x05f2 2534#define regHUBP0_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX 2 2535#define regHUBP0_DCHUBP_CNTL 0x05f3 2536#define regHUBP0_DCHUBP_CNTL_BASE_IDX 2 2537#define regHUBP0_HUBP_CLK_CNTL 0x05f4 2538#define regHUBP0_HUBP_CLK_CNTL_BASE_IDX 2 2539#define regHUBP0_DCHUBP_VMPG_CONFIG 0x05f5 2540#define regHUBP0_DCHUBP_VMPG_CONFIG_BASE_IDX 2 2541#define regHUBP0_HUBPREQ_DEBUG_DB 0x05f6 2542#define regHUBP0_HUBPREQ_DEBUG_DB_BASE_IDX 2 2543#define regHUBP0_HUBPREQ_DEBUG 0x05f7 2544#define regHUBP0_HUBPREQ_DEBUG_BASE_IDX 2 2545#define regHUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK 0x05fb 2546#define regHUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX 2 2547#define regHUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK 0x05fc 2548#define regHUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX 2 2549 2550 2551// addressBlock: dce_dc_dcbubp0_dispdec_hubpreq_dispdec 2552// base address: 0x0 2553#define regHUBPREQ0_DCSURF_SURFACE_PITCH 0x0607 2554#define regHUBPREQ0_DCSURF_SURFACE_PITCH_BASE_IDX 2 2555#define regHUBPREQ0_DCSURF_SURFACE_PITCH_C 0x0608 2556#define regHUBPREQ0_DCSURF_SURFACE_PITCH_C_BASE_IDX 2 2557#define regHUBPREQ0_VMID_SETTINGS_0 0x0609 2558#define regHUBPREQ0_VMID_SETTINGS_0_BASE_IDX 2 2559#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS 0x060a 2560#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2 2561#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH 0x060b 2562#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 2563#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C 0x060c 2564#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX 2 2565#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x060d 2566#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 2567#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS 0x060e 2568#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2 2569#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH 0x060f 2570#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 2571#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C 0x0610 2572#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX 2 2573#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x0611 2574#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 2575#define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS 0x0612 2576#define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX 2 2577#define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH 0x0613 2578#define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 2579#define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C 0x0614 2580#define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 2581#define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C 0x0615 2582#define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 2583#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS 0x0616 2584#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX 2 2585#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH 0x0617 2586#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 2587#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C 0x0618 2588#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 2589#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C 0x0619 2590#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 2591#define regHUBPREQ0_DCSURF_SURFACE_CONTROL 0x061a 2592#define regHUBPREQ0_DCSURF_SURFACE_CONTROL_BASE_IDX 2 2593#define regHUBPREQ0_DCSURF_FLIP_CONTROL 0x061b 2594#define regHUBPREQ0_DCSURF_FLIP_CONTROL_BASE_IDX 2 2595#define regHUBPREQ0_DCSURF_FLIP_CONTROL2 0x061c 2596#define regHUBPREQ0_DCSURF_FLIP_CONTROL2_BASE_IDX 2 2597#define regHUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT 0x0620 2598#define regHUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX 2 2599#define regHUBPREQ0_DCSURF_SURFACE_INUSE 0x0621 2600#define regHUBPREQ0_DCSURF_SURFACE_INUSE_BASE_IDX 2 2601#define regHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH 0x0622 2602#define regHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX 2 2603#define regHUBPREQ0_DCSURF_SURFACE_INUSE_C 0x0623 2604#define regHUBPREQ0_DCSURF_SURFACE_INUSE_C_BASE_IDX 2 2605#define regHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C 0x0624 2606#define regHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX 2 2607#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE 0x0625 2608#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX 2 2609#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH 0x0626 2610#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX 2 2611#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C 0x0627 2612#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX 2 2613#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C 0x0628 2614#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX 2 2615#define regHUBPREQ0_DCN_EXPANSION_MODE 0x0629 2616#define regHUBPREQ0_DCN_EXPANSION_MODE_BASE_IDX 2 2617#define regHUBPREQ0_DCN_TTU_QOS_WM 0x062a 2618#define regHUBPREQ0_DCN_TTU_QOS_WM_BASE_IDX 2 2619#define regHUBPREQ0_DCN_GLOBAL_TTU_CNTL 0x062b 2620#define regHUBPREQ0_DCN_GLOBAL_TTU_CNTL_BASE_IDX 2 2621#define regHUBPREQ0_DCN_SURF0_TTU_CNTL0 0x062c 2622#define regHUBPREQ0_DCN_SURF0_TTU_CNTL0_BASE_IDX 2 2623#define regHUBPREQ0_DCN_SURF0_TTU_CNTL1 0x062d 2624#define regHUBPREQ0_DCN_SURF0_TTU_CNTL1_BASE_IDX 2 2625#define regHUBPREQ0_DCN_SURF1_TTU_CNTL0 0x062e 2626#define regHUBPREQ0_DCN_SURF1_TTU_CNTL0_BASE_IDX 2 2627#define regHUBPREQ0_DCN_SURF1_TTU_CNTL1 0x062f 2628#define regHUBPREQ0_DCN_SURF1_TTU_CNTL1_BASE_IDX 2 2629#define regHUBPREQ0_DCN_CUR0_TTU_CNTL0 0x0630 2630#define regHUBPREQ0_DCN_CUR0_TTU_CNTL0_BASE_IDX 2 2631#define regHUBPREQ0_DCN_CUR0_TTU_CNTL1 0x0631 2632#define regHUBPREQ0_DCN_CUR0_TTU_CNTL1_BASE_IDX 2 2633#define regHUBPREQ0_DCN_CUR1_TTU_CNTL0 0x0632 2634#define regHUBPREQ0_DCN_CUR1_TTU_CNTL0_BASE_IDX 2 2635#define regHUBPREQ0_DCN_CUR1_TTU_CNTL1 0x0633 2636#define regHUBPREQ0_DCN_CUR1_TTU_CNTL1_BASE_IDX 2 2637#define regHUBPREQ0_DCN_DMDATA_VM_CNTL 0x0634 2638#define regHUBPREQ0_DCN_DMDATA_VM_CNTL_BASE_IDX 2 2639#define regHUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR 0x0635 2640#define regHUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 2 2641#define regHUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR 0x0636 2642#define regHUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 2 2643#define regHUBPREQ0_DCN_VM_MX_L1_TLB_CNTL 0x0643 2644#define regHUBPREQ0_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX 2 2645#define regHUBPREQ0_BLANK_OFFSET_0 0x0644 2646#define regHUBPREQ0_BLANK_OFFSET_0_BASE_IDX 2 2647#define regHUBPREQ0_BLANK_OFFSET_1 0x0645 2648#define regHUBPREQ0_BLANK_OFFSET_1_BASE_IDX 2 2649#define regHUBPREQ0_DST_DIMENSIONS 0x0646 2650#define regHUBPREQ0_DST_DIMENSIONS_BASE_IDX 2 2651#define regHUBPREQ0_DST_AFTER_SCALER 0x0647 2652#define regHUBPREQ0_DST_AFTER_SCALER_BASE_IDX 2 2653#define regHUBPREQ0_PREFETCH_SETTINGS 0x0648 2654#define regHUBPREQ0_PREFETCH_SETTINGS_BASE_IDX 2 2655#define regHUBPREQ0_PREFETCH_SETTINGS_C 0x0649 2656#define regHUBPREQ0_PREFETCH_SETTINGS_C_BASE_IDX 2 2657#define regHUBPREQ0_VBLANK_PARAMETERS_0 0x064a 2658#define regHUBPREQ0_VBLANK_PARAMETERS_0_BASE_IDX 2 2659#define regHUBPREQ0_VBLANK_PARAMETERS_1 0x064b 2660#define regHUBPREQ0_VBLANK_PARAMETERS_1_BASE_IDX 2 2661#define regHUBPREQ0_VBLANK_PARAMETERS_2 0x064c 2662#define regHUBPREQ0_VBLANK_PARAMETERS_2_BASE_IDX 2 2663#define regHUBPREQ0_VBLANK_PARAMETERS_3 0x064d 2664#define regHUBPREQ0_VBLANK_PARAMETERS_3_BASE_IDX 2 2665#define regHUBPREQ0_VBLANK_PARAMETERS_4 0x064e 2666#define regHUBPREQ0_VBLANK_PARAMETERS_4_BASE_IDX 2 2667#define regHUBPREQ0_FLIP_PARAMETERS_0 0x064f 2668#define regHUBPREQ0_FLIP_PARAMETERS_0_BASE_IDX 2 2669#define regHUBPREQ0_FLIP_PARAMETERS_1 0x0650 2670#define regHUBPREQ0_FLIP_PARAMETERS_1_BASE_IDX 2 2671#define regHUBPREQ0_FLIP_PARAMETERS_2 0x0651 2672#define regHUBPREQ0_FLIP_PARAMETERS_2_BASE_IDX 2 2673#define regHUBPREQ0_NOM_PARAMETERS_0 0x0652 2674#define regHUBPREQ0_NOM_PARAMETERS_0_BASE_IDX 2 2675#define regHUBPREQ0_NOM_PARAMETERS_1 0x0653 2676#define regHUBPREQ0_NOM_PARAMETERS_1_BASE_IDX 2 2677#define regHUBPREQ0_NOM_PARAMETERS_2 0x0654 2678#define regHUBPREQ0_NOM_PARAMETERS_2_BASE_IDX 2 2679#define regHUBPREQ0_NOM_PARAMETERS_3 0x0655 2680#define regHUBPREQ0_NOM_PARAMETERS_3_BASE_IDX 2 2681#define regHUBPREQ0_NOM_PARAMETERS_4 0x0656 2682#define regHUBPREQ0_NOM_PARAMETERS_4_BASE_IDX 2 2683#define regHUBPREQ0_NOM_PARAMETERS_5 0x0657 2684#define regHUBPREQ0_NOM_PARAMETERS_5_BASE_IDX 2 2685#define regHUBPREQ0_NOM_PARAMETERS_6 0x0658 2686#define regHUBPREQ0_NOM_PARAMETERS_6_BASE_IDX 2 2687#define regHUBPREQ0_NOM_PARAMETERS_7 0x0659 2688#define regHUBPREQ0_NOM_PARAMETERS_7_BASE_IDX 2 2689#define regHUBPREQ0_PER_LINE_DELIVERY_PRE 0x065a 2690#define regHUBPREQ0_PER_LINE_DELIVERY_PRE_BASE_IDX 2 2691#define regHUBPREQ0_PER_LINE_DELIVERY 0x065b 2692#define regHUBPREQ0_PER_LINE_DELIVERY_BASE_IDX 2 2693#define regHUBPREQ0_CURSOR_SETTINGS 0x065c 2694#define regHUBPREQ0_CURSOR_SETTINGS_BASE_IDX 2 2695#define regHUBPREQ0_REF_FREQ_TO_PIX_FREQ 0x065d 2696#define regHUBPREQ0_REF_FREQ_TO_PIX_FREQ_BASE_IDX 2 2697#define regHUBPREQ0_DST_Y_DELTA_DRQ_LIMIT 0x065e 2698#define regHUBPREQ0_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX 2 2699#define regHUBPREQ0_HUBPREQ_MEM_PWR_CTRL 0x065f 2700#define regHUBPREQ0_HUBPREQ_MEM_PWR_CTRL_BASE_IDX 2 2701#define regHUBPREQ0_HUBPREQ_MEM_PWR_STATUS 0x0660 2702#define regHUBPREQ0_HUBPREQ_MEM_PWR_STATUS_BASE_IDX 2 2703#define regHUBPREQ0_VBLANK_PARAMETERS_5 0x0663 2704#define regHUBPREQ0_VBLANK_PARAMETERS_5_BASE_IDX 2 2705#define regHUBPREQ0_VBLANK_PARAMETERS_6 0x0664 2706#define regHUBPREQ0_VBLANK_PARAMETERS_6_BASE_IDX 2 2707#define regHUBPREQ0_FLIP_PARAMETERS_3 0x0665 2708#define regHUBPREQ0_FLIP_PARAMETERS_3_BASE_IDX 2 2709#define regHUBPREQ0_FLIP_PARAMETERS_4 0x0666 2710#define regHUBPREQ0_FLIP_PARAMETERS_4_BASE_IDX 2 2711#define regHUBPREQ0_FLIP_PARAMETERS_5 0x0667 2712#define regHUBPREQ0_FLIP_PARAMETERS_5_BASE_IDX 2 2713#define regHUBPREQ0_FLIP_PARAMETERS_6 0x0668 2714#define regHUBPREQ0_FLIP_PARAMETERS_6_BASE_IDX 2 2715 2716 2717// addressBlock: dce_dc_dcbubp0_dispdec_hubpret_dispdec 2718// base address: 0x0 2719#define regHUBPRET0_HUBPRET_CONTROL 0x066c 2720#define regHUBPRET0_HUBPRET_CONTROL_BASE_IDX 2 2721#define regHUBPRET0_HUBPRET_MEM_PWR_CTRL 0x066d 2722#define regHUBPRET0_HUBPRET_MEM_PWR_CTRL_BASE_IDX 2 2723#define regHUBPRET0_HUBPRET_MEM_PWR_STATUS 0x066e 2724#define regHUBPRET0_HUBPRET_MEM_PWR_STATUS_BASE_IDX 2 2725#define regHUBPRET0_HUBPRET_READ_LINE_CTRL0 0x066f 2726#define regHUBPRET0_HUBPRET_READ_LINE_CTRL0_BASE_IDX 2 2727#define regHUBPRET0_HUBPRET_READ_LINE_CTRL1 0x0670 2728#define regHUBPRET0_HUBPRET_READ_LINE_CTRL1_BASE_IDX 2 2729#define regHUBPRET0_HUBPRET_READ_LINE0 0x0671 2730#define regHUBPRET0_HUBPRET_READ_LINE0_BASE_IDX 2 2731#define regHUBPRET0_HUBPRET_READ_LINE1 0x0672 2732#define regHUBPRET0_HUBPRET_READ_LINE1_BASE_IDX 2 2733#define regHUBPRET0_HUBPRET_INTERRUPT 0x0673 2734#define regHUBPRET0_HUBPRET_INTERRUPT_BASE_IDX 2 2735#define regHUBPRET0_HUBPRET_READ_LINE_VALUE 0x0674 2736#define regHUBPRET0_HUBPRET_READ_LINE_VALUE_BASE_IDX 2 2737#define regHUBPRET0_HUBPRET_READ_LINE_STATUS 0x0675 2738#define regHUBPRET0_HUBPRET_READ_LINE_STATUS_BASE_IDX 2 2739 2740 2741// addressBlock: dce_dc_dcbubp0_dispdec_cursor0_dispdec 2742// base address: 0x0 2743#define regCURSOR0_0_CURSOR_CONTROL 0x0678 2744#define regCURSOR0_0_CURSOR_CONTROL_BASE_IDX 2 2745#define regCURSOR0_0_CURSOR_SURFACE_ADDRESS 0x0679 2746#define regCURSOR0_0_CURSOR_SURFACE_ADDRESS_BASE_IDX 2 2747#define regCURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH 0x067a 2748#define regCURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX 2 2749#define regCURSOR0_0_CURSOR_SIZE 0x067b 2750#define regCURSOR0_0_CURSOR_SIZE_BASE_IDX 2 2751#define regCURSOR0_0_CURSOR_POSITION 0x067c 2752#define regCURSOR0_0_CURSOR_POSITION_BASE_IDX 2 2753#define regCURSOR0_0_CURSOR_HOT_SPOT 0x067d 2754#define regCURSOR0_0_CURSOR_HOT_SPOT_BASE_IDX 2 2755#define regCURSOR0_0_CURSOR_STEREO_CONTROL 0x067e 2756#define regCURSOR0_0_CURSOR_STEREO_CONTROL_BASE_IDX 2 2757#define regCURSOR0_0_CURSOR_DST_OFFSET 0x067f 2758#define regCURSOR0_0_CURSOR_DST_OFFSET_BASE_IDX 2 2759#define regCURSOR0_0_CURSOR_MEM_PWR_CTRL 0x0680 2760#define regCURSOR0_0_CURSOR_MEM_PWR_CTRL_BASE_IDX 2 2761#define regCURSOR0_0_CURSOR_MEM_PWR_STATUS 0x0681 2762#define regCURSOR0_0_CURSOR_MEM_PWR_STATUS_BASE_IDX 2 2763#define regCURSOR0_0_DMDATA_ADDRESS_HIGH 0x0682 2764#define regCURSOR0_0_DMDATA_ADDRESS_HIGH_BASE_IDX 2 2765#define regCURSOR0_0_DMDATA_ADDRESS_LOW 0x0683 2766#define regCURSOR0_0_DMDATA_ADDRESS_LOW_BASE_IDX 2 2767#define regCURSOR0_0_DMDATA_CNTL 0x0684 2768#define regCURSOR0_0_DMDATA_CNTL_BASE_IDX 2 2769#define regCURSOR0_0_DMDATA_QOS_CNTL 0x0685 2770#define regCURSOR0_0_DMDATA_QOS_CNTL_BASE_IDX 2 2771#define regCURSOR0_0_DMDATA_STATUS 0x0686 2772#define regCURSOR0_0_DMDATA_STATUS_BASE_IDX 2 2773#define regCURSOR0_0_DMDATA_SW_CNTL 0x0687 2774#define regCURSOR0_0_DMDATA_SW_CNTL_BASE_IDX 2 2775#define regCURSOR0_0_DMDATA_SW_DATA 0x0688 2776#define regCURSOR0_0_DMDATA_SW_DATA_BASE_IDX 2 2777 2778 2779// addressBlock: dce_dc_dcbubp0_dispdec_hubp_dcperfmon_dc_perfmon_dispdec 2780// base address: 0x1a74 2781#define regDC_PERFMON7_PERFCOUNTER_CNTL 0x069d 2782#define regDC_PERFMON7_PERFCOUNTER_CNTL_BASE_IDX 2 2783#define regDC_PERFMON7_PERFCOUNTER_CNTL2 0x069e 2784#define regDC_PERFMON7_PERFCOUNTER_CNTL2_BASE_IDX 2 2785#define regDC_PERFMON7_PERFCOUNTER_STATE 0x069f 2786#define regDC_PERFMON7_PERFCOUNTER_STATE_BASE_IDX 2 2787#define regDC_PERFMON7_PERFMON_CNTL 0x06a0 2788#define regDC_PERFMON7_PERFMON_CNTL_BASE_IDX 2 2789#define regDC_PERFMON7_PERFMON_CNTL2 0x06a1 2790#define regDC_PERFMON7_PERFMON_CNTL2_BASE_IDX 2 2791#define regDC_PERFMON7_PERFMON_CVALUE_INT_MISC 0x06a2 2792#define regDC_PERFMON7_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 2793#define regDC_PERFMON7_PERFMON_CVALUE_LOW 0x06a3 2794#define regDC_PERFMON7_PERFMON_CVALUE_LOW_BASE_IDX 2 2795#define regDC_PERFMON7_PERFMON_HI 0x06a4 2796#define regDC_PERFMON7_PERFMON_HI_BASE_IDX 2 2797#define regDC_PERFMON7_PERFMON_LOW 0x06a5 2798#define regDC_PERFMON7_PERFMON_LOW_BASE_IDX 2 2799 2800 2801// addressBlock: dce_dc_dcbubp1_dispdec_hubp_dispdec 2802// base address: 0x370 2803#define regHUBP1_DCSURF_SURFACE_CONFIG 0x06c1 2804#define regHUBP1_DCSURF_SURFACE_CONFIG_BASE_IDX 2 2805#define regHUBP1_DCSURF_ADDR_CONFIG 0x06c2 2806#define regHUBP1_DCSURF_ADDR_CONFIG_BASE_IDX 2 2807#define regHUBP1_DCSURF_TILING_CONFIG 0x06c3 2808#define regHUBP1_DCSURF_TILING_CONFIG_BASE_IDX 2 2809#define regHUBP1_DCSURF_PRI_VIEWPORT_START 0x06c5 2810#define regHUBP1_DCSURF_PRI_VIEWPORT_START_BASE_IDX 2 2811#define regHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION 0x06c6 2812#define regHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2 2813#define regHUBP1_DCSURF_PRI_VIEWPORT_START_C 0x06c7 2814#define regHUBP1_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX 2 2815#define regHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C 0x06c8 2816#define regHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX 2 2817#define regHUBP1_DCSURF_SEC_VIEWPORT_START 0x06c9 2818#define regHUBP1_DCSURF_SEC_VIEWPORT_START_BASE_IDX 2 2819#define regHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION 0x06ca 2820#define regHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX 2 2821#define regHUBP1_DCSURF_SEC_VIEWPORT_START_C 0x06cb 2822#define regHUBP1_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX 2 2823#define regHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C 0x06cc 2824#define regHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX 2 2825#define regHUBP1_DCHUBP_REQ_SIZE_CONFIG 0x06cd 2826#define regHUBP1_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX 2 2827#define regHUBP1_DCHUBP_REQ_SIZE_CONFIG_C 0x06ce 2828#define regHUBP1_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX 2 2829#define regHUBP1_DCHUBP_CNTL 0x06cf 2830#define regHUBP1_DCHUBP_CNTL_BASE_IDX 2 2831#define regHUBP1_HUBP_CLK_CNTL 0x06d0 2832#define regHUBP1_HUBP_CLK_CNTL_BASE_IDX 2 2833#define regHUBP1_DCHUBP_VMPG_CONFIG 0x06d1 2834#define regHUBP1_DCHUBP_VMPG_CONFIG_BASE_IDX 2 2835#define regHUBP1_HUBPREQ_DEBUG_DB 0x06d2 2836#define regHUBP1_HUBPREQ_DEBUG_DB_BASE_IDX 2 2837#define regHUBP1_HUBPREQ_DEBUG 0x06d3 2838#define regHUBP1_HUBPREQ_DEBUG_BASE_IDX 2 2839#define regHUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK 0x06d7 2840#define regHUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX 2 2841#define regHUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK 0x06d8 2842#define regHUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX 2 2843 2844 2845// addressBlock: dce_dc_dcbubp1_dispdec_hubpreq_dispdec 2846// base address: 0x370 2847#define regHUBPREQ1_DCSURF_SURFACE_PITCH 0x06e3 2848#define regHUBPREQ1_DCSURF_SURFACE_PITCH_BASE_IDX 2 2849#define regHUBPREQ1_DCSURF_SURFACE_PITCH_C 0x06e4 2850#define regHUBPREQ1_DCSURF_SURFACE_PITCH_C_BASE_IDX 2 2851#define regHUBPREQ1_VMID_SETTINGS_0 0x06e5 2852#define regHUBPREQ1_VMID_SETTINGS_0_BASE_IDX 2 2853#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS 0x06e6 2854#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2 2855#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH 0x06e7 2856#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 2857#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C 0x06e8 2858#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX 2 2859#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x06e9 2860#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 2861#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS 0x06ea 2862#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2 2863#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH 0x06eb 2864#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 2865#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C 0x06ec 2866#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX 2 2867#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x06ed 2868#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 2869#define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS 0x06ee 2870#define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX 2 2871#define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH 0x06ef 2872#define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 2873#define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C 0x06f0 2874#define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 2875#define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C 0x06f1 2876#define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 2877#define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS 0x06f2 2878#define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX 2 2879#define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH 0x06f3 2880#define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 2881#define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C 0x06f4 2882#define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 2883#define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C 0x06f5 2884#define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 2885#define regHUBPREQ1_DCSURF_SURFACE_CONTROL 0x06f6 2886#define regHUBPREQ1_DCSURF_SURFACE_CONTROL_BASE_IDX 2 2887#define regHUBPREQ1_DCSURF_FLIP_CONTROL 0x06f7 2888#define regHUBPREQ1_DCSURF_FLIP_CONTROL_BASE_IDX 2 2889#define regHUBPREQ1_DCSURF_FLIP_CONTROL2 0x06f8 2890#define regHUBPREQ1_DCSURF_FLIP_CONTROL2_BASE_IDX 2 2891#define regHUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT 0x06fc 2892#define regHUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX 2 2893#define regHUBPREQ1_DCSURF_SURFACE_INUSE 0x06fd 2894#define regHUBPREQ1_DCSURF_SURFACE_INUSE_BASE_IDX 2 2895#define regHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH 0x06fe 2896#define regHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX 2 2897#define regHUBPREQ1_DCSURF_SURFACE_INUSE_C 0x06ff 2898#define regHUBPREQ1_DCSURF_SURFACE_INUSE_C_BASE_IDX 2 2899#define regHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C 0x0700 2900#define regHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX 2 2901#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE 0x0701 2902#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX 2 2903#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH 0x0702 2904#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX 2 2905#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C 0x0703 2906#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX 2 2907#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C 0x0704 2908#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX 2 2909#define regHUBPREQ1_DCN_EXPANSION_MODE 0x0705 2910#define regHUBPREQ1_DCN_EXPANSION_MODE_BASE_IDX 2 2911#define regHUBPREQ1_DCN_TTU_QOS_WM 0x0706 2912#define regHUBPREQ1_DCN_TTU_QOS_WM_BASE_IDX 2 2913#define regHUBPREQ1_DCN_GLOBAL_TTU_CNTL 0x0707 2914#define regHUBPREQ1_DCN_GLOBAL_TTU_CNTL_BASE_IDX 2 2915#define regHUBPREQ1_DCN_SURF0_TTU_CNTL0 0x0708 2916#define regHUBPREQ1_DCN_SURF0_TTU_CNTL0_BASE_IDX 2 2917#define regHUBPREQ1_DCN_SURF0_TTU_CNTL1 0x0709 2918#define regHUBPREQ1_DCN_SURF0_TTU_CNTL1_BASE_IDX 2 2919#define regHUBPREQ1_DCN_SURF1_TTU_CNTL0 0x070a 2920#define regHUBPREQ1_DCN_SURF1_TTU_CNTL0_BASE_IDX 2 2921#define regHUBPREQ1_DCN_SURF1_TTU_CNTL1 0x070b 2922#define regHUBPREQ1_DCN_SURF1_TTU_CNTL1_BASE_IDX 2 2923#define regHUBPREQ1_DCN_CUR0_TTU_CNTL0 0x070c 2924#define regHUBPREQ1_DCN_CUR0_TTU_CNTL0_BASE_IDX 2 2925#define regHUBPREQ1_DCN_CUR0_TTU_CNTL1 0x070d 2926#define regHUBPREQ1_DCN_CUR0_TTU_CNTL1_BASE_IDX 2 2927#define regHUBPREQ1_DCN_CUR1_TTU_CNTL0 0x070e 2928#define regHUBPREQ1_DCN_CUR1_TTU_CNTL0_BASE_IDX 2 2929#define regHUBPREQ1_DCN_CUR1_TTU_CNTL1 0x070f 2930#define regHUBPREQ1_DCN_CUR1_TTU_CNTL1_BASE_IDX 2 2931#define regHUBPREQ1_DCN_DMDATA_VM_CNTL 0x0710 2932#define regHUBPREQ1_DCN_DMDATA_VM_CNTL_BASE_IDX 2 2933#define regHUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR 0x0711 2934#define regHUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 2 2935#define regHUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR 0x0712 2936#define regHUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 2 2937#define regHUBPREQ1_DCN_VM_MX_L1_TLB_CNTL 0x071f 2938#define regHUBPREQ1_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX 2 2939#define regHUBPREQ1_BLANK_OFFSET_0 0x0720 2940#define regHUBPREQ1_BLANK_OFFSET_0_BASE_IDX 2 2941#define regHUBPREQ1_BLANK_OFFSET_1 0x0721 2942#define regHUBPREQ1_BLANK_OFFSET_1_BASE_IDX 2 2943#define regHUBPREQ1_DST_DIMENSIONS 0x0722 2944#define regHUBPREQ1_DST_DIMENSIONS_BASE_IDX 2 2945#define regHUBPREQ1_DST_AFTER_SCALER 0x0723 2946#define regHUBPREQ1_DST_AFTER_SCALER_BASE_IDX 2 2947#define regHUBPREQ1_PREFETCH_SETTINGS 0x0724 2948#define regHUBPREQ1_PREFETCH_SETTINGS_BASE_IDX 2 2949#define regHUBPREQ1_PREFETCH_SETTINGS_C 0x0725 2950#define regHUBPREQ1_PREFETCH_SETTINGS_C_BASE_IDX 2 2951#define regHUBPREQ1_VBLANK_PARAMETERS_0 0x0726 2952#define regHUBPREQ1_VBLANK_PARAMETERS_0_BASE_IDX 2 2953#define regHUBPREQ1_VBLANK_PARAMETERS_1 0x0727 2954#define regHUBPREQ1_VBLANK_PARAMETERS_1_BASE_IDX 2 2955#define regHUBPREQ1_VBLANK_PARAMETERS_2 0x0728 2956#define regHUBPREQ1_VBLANK_PARAMETERS_2_BASE_IDX 2 2957#define regHUBPREQ1_VBLANK_PARAMETERS_3 0x0729 2958#define regHUBPREQ1_VBLANK_PARAMETERS_3_BASE_IDX 2 2959#define regHUBPREQ1_VBLANK_PARAMETERS_4 0x072a 2960#define regHUBPREQ1_VBLANK_PARAMETERS_4_BASE_IDX 2 2961#define regHUBPREQ1_FLIP_PARAMETERS_0 0x072b 2962#define regHUBPREQ1_FLIP_PARAMETERS_0_BASE_IDX 2 2963#define regHUBPREQ1_FLIP_PARAMETERS_1 0x072c 2964#define regHUBPREQ1_FLIP_PARAMETERS_1_BASE_IDX 2 2965#define regHUBPREQ1_FLIP_PARAMETERS_2 0x072d 2966#define regHUBPREQ1_FLIP_PARAMETERS_2_BASE_IDX 2 2967#define regHUBPREQ1_NOM_PARAMETERS_0 0x072e 2968#define regHUBPREQ1_NOM_PARAMETERS_0_BASE_IDX 2 2969#define regHUBPREQ1_NOM_PARAMETERS_1 0x072f 2970#define regHUBPREQ1_NOM_PARAMETERS_1_BASE_IDX 2 2971#define regHUBPREQ1_NOM_PARAMETERS_2 0x0730 2972#define regHUBPREQ1_NOM_PARAMETERS_2_BASE_IDX 2 2973#define regHUBPREQ1_NOM_PARAMETERS_3 0x0731 2974#define regHUBPREQ1_NOM_PARAMETERS_3_BASE_IDX 2 2975#define regHUBPREQ1_NOM_PARAMETERS_4 0x0732 2976#define regHUBPREQ1_NOM_PARAMETERS_4_BASE_IDX 2 2977#define regHUBPREQ1_NOM_PARAMETERS_5 0x0733 2978#define regHUBPREQ1_NOM_PARAMETERS_5_BASE_IDX 2 2979#define regHUBPREQ1_NOM_PARAMETERS_6 0x0734 2980#define regHUBPREQ1_NOM_PARAMETERS_6_BASE_IDX 2 2981#define regHUBPREQ1_NOM_PARAMETERS_7 0x0735 2982#define regHUBPREQ1_NOM_PARAMETERS_7_BASE_IDX 2 2983#define regHUBPREQ1_PER_LINE_DELIVERY_PRE 0x0736 2984#define regHUBPREQ1_PER_LINE_DELIVERY_PRE_BASE_IDX 2 2985#define regHUBPREQ1_PER_LINE_DELIVERY 0x0737 2986#define regHUBPREQ1_PER_LINE_DELIVERY_BASE_IDX 2 2987#define regHUBPREQ1_CURSOR_SETTINGS 0x0738 2988#define regHUBPREQ1_CURSOR_SETTINGS_BASE_IDX 2 2989#define regHUBPREQ1_REF_FREQ_TO_PIX_FREQ 0x0739 2990#define regHUBPREQ1_REF_FREQ_TO_PIX_FREQ_BASE_IDX 2 2991#define regHUBPREQ1_DST_Y_DELTA_DRQ_LIMIT 0x073a 2992#define regHUBPREQ1_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX 2 2993#define regHUBPREQ1_HUBPREQ_MEM_PWR_CTRL 0x073b 2994#define regHUBPREQ1_HUBPREQ_MEM_PWR_CTRL_BASE_IDX 2 2995#define regHUBPREQ1_HUBPREQ_MEM_PWR_STATUS 0x073c 2996#define regHUBPREQ1_HUBPREQ_MEM_PWR_STATUS_BASE_IDX 2 2997#define regHUBPREQ1_VBLANK_PARAMETERS_5 0x073f 2998#define regHUBPREQ1_VBLANK_PARAMETERS_5_BASE_IDX 2 2999#define regHUBPREQ1_VBLANK_PARAMETERS_6 0x0740 3000#define regHUBPREQ1_VBLANK_PARAMETERS_6_BASE_IDX 2 3001#define regHUBPREQ1_FLIP_PARAMETERS_3 0x0741 3002#define regHUBPREQ1_FLIP_PARAMETERS_3_BASE_IDX 2 3003#define regHUBPREQ1_FLIP_PARAMETERS_4 0x0742 3004#define regHUBPREQ1_FLIP_PARAMETERS_4_BASE_IDX 2 3005#define regHUBPREQ1_FLIP_PARAMETERS_5 0x0743 3006#define regHUBPREQ1_FLIP_PARAMETERS_5_BASE_IDX 2 3007#define regHUBPREQ1_FLIP_PARAMETERS_6 0x0744 3008#define regHUBPREQ1_FLIP_PARAMETERS_6_BASE_IDX 2 3009 3010 3011// addressBlock: dce_dc_dcbubp1_dispdec_hubpret_dispdec 3012// base address: 0x370 3013#define regHUBPRET1_HUBPRET_CONTROL 0x0748 3014#define regHUBPRET1_HUBPRET_CONTROL_BASE_IDX 2 3015#define regHUBPRET1_HUBPRET_MEM_PWR_CTRL 0x0749 3016#define regHUBPRET1_HUBPRET_MEM_PWR_CTRL_BASE_IDX 2 3017#define regHUBPRET1_HUBPRET_MEM_PWR_STATUS 0x074a 3018#define regHUBPRET1_HUBPRET_MEM_PWR_STATUS_BASE_IDX 2 3019#define regHUBPRET1_HUBPRET_READ_LINE_CTRL0 0x074b 3020#define regHUBPRET1_HUBPRET_READ_LINE_CTRL0_BASE_IDX 2 3021#define regHUBPRET1_HUBPRET_READ_LINE_CTRL1 0x074c 3022#define regHUBPRET1_HUBPRET_READ_LINE_CTRL1_BASE_IDX 2 3023#define regHUBPRET1_HUBPRET_READ_LINE0 0x074d 3024#define regHUBPRET1_HUBPRET_READ_LINE0_BASE_IDX 2 3025#define regHUBPRET1_HUBPRET_READ_LINE1 0x074e 3026#define regHUBPRET1_HUBPRET_READ_LINE1_BASE_IDX 2 3027#define regHUBPRET1_HUBPRET_INTERRUPT 0x074f 3028#define regHUBPRET1_HUBPRET_INTERRUPT_BASE_IDX 2 3029#define regHUBPRET1_HUBPRET_READ_LINE_VALUE 0x0750 3030#define regHUBPRET1_HUBPRET_READ_LINE_VALUE_BASE_IDX 2 3031#define regHUBPRET1_HUBPRET_READ_LINE_STATUS 0x0751 3032#define regHUBPRET1_HUBPRET_READ_LINE_STATUS_BASE_IDX 2 3033 3034 3035// addressBlock: dce_dc_dcbubp1_dispdec_cursor0_dispdec 3036// base address: 0x370 3037#define regCURSOR0_1_CURSOR_CONTROL 0x0754 3038#define regCURSOR0_1_CURSOR_CONTROL_BASE_IDX 2 3039#define regCURSOR0_1_CURSOR_SURFACE_ADDRESS 0x0755 3040#define regCURSOR0_1_CURSOR_SURFACE_ADDRESS_BASE_IDX 2 3041#define regCURSOR0_1_CURSOR_SURFACE_ADDRESS_HIGH 0x0756 3042#define regCURSOR0_1_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX 2 3043#define regCURSOR0_1_CURSOR_SIZE 0x0757 3044#define regCURSOR0_1_CURSOR_SIZE_BASE_IDX 2 3045#define regCURSOR0_1_CURSOR_POSITION 0x0758 3046#define regCURSOR0_1_CURSOR_POSITION_BASE_IDX 2 3047#define regCURSOR0_1_CURSOR_HOT_SPOT 0x0759 3048#define regCURSOR0_1_CURSOR_HOT_SPOT_BASE_IDX 2 3049#define regCURSOR0_1_CURSOR_STEREO_CONTROL 0x075a 3050#define regCURSOR0_1_CURSOR_STEREO_CONTROL_BASE_IDX 2 3051#define regCURSOR0_1_CURSOR_DST_OFFSET 0x075b 3052#define regCURSOR0_1_CURSOR_DST_OFFSET_BASE_IDX 2 3053#define regCURSOR0_1_CURSOR_MEM_PWR_CTRL 0x075c 3054#define regCURSOR0_1_CURSOR_MEM_PWR_CTRL_BASE_IDX 2 3055#define regCURSOR0_1_CURSOR_MEM_PWR_STATUS 0x075d 3056#define regCURSOR0_1_CURSOR_MEM_PWR_STATUS_BASE_IDX 2 3057#define regCURSOR0_1_DMDATA_ADDRESS_HIGH 0x075e 3058#define regCURSOR0_1_DMDATA_ADDRESS_HIGH_BASE_IDX 2 3059#define regCURSOR0_1_DMDATA_ADDRESS_LOW 0x075f 3060#define regCURSOR0_1_DMDATA_ADDRESS_LOW_BASE_IDX 2 3061#define regCURSOR0_1_DMDATA_CNTL 0x0760 3062#define regCURSOR0_1_DMDATA_CNTL_BASE_IDX 2 3063#define regCURSOR0_1_DMDATA_QOS_CNTL 0x0761 3064#define regCURSOR0_1_DMDATA_QOS_CNTL_BASE_IDX 2 3065#define regCURSOR0_1_DMDATA_STATUS 0x0762 3066#define regCURSOR0_1_DMDATA_STATUS_BASE_IDX 2 3067#define regCURSOR0_1_DMDATA_SW_CNTL 0x0763 3068#define regCURSOR0_1_DMDATA_SW_CNTL_BASE_IDX 2 3069#define regCURSOR0_1_DMDATA_SW_DATA 0x0764 3070#define regCURSOR0_1_DMDATA_SW_DATA_BASE_IDX 2 3071 3072 3073// addressBlock: dce_dc_dcbubp1_dispdec_hubp_dcperfmon_dc_perfmon_dispdec 3074// base address: 0x1de4 3075#define regDC_PERFMON8_PERFCOUNTER_CNTL 0x0779 3076#define regDC_PERFMON8_PERFCOUNTER_CNTL_BASE_IDX 2 3077#define regDC_PERFMON8_PERFCOUNTER_CNTL2 0x077a 3078#define regDC_PERFMON8_PERFCOUNTER_CNTL2_BASE_IDX 2 3079#define regDC_PERFMON8_PERFCOUNTER_STATE 0x077b 3080#define regDC_PERFMON8_PERFCOUNTER_STATE_BASE_IDX 2 3081#define regDC_PERFMON8_PERFMON_CNTL 0x077c 3082#define regDC_PERFMON8_PERFMON_CNTL_BASE_IDX 2 3083#define regDC_PERFMON8_PERFMON_CNTL2 0x077d 3084#define regDC_PERFMON8_PERFMON_CNTL2_BASE_IDX 2 3085#define regDC_PERFMON8_PERFMON_CVALUE_INT_MISC 0x077e 3086#define regDC_PERFMON8_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 3087#define regDC_PERFMON8_PERFMON_CVALUE_LOW 0x077f 3088#define regDC_PERFMON8_PERFMON_CVALUE_LOW_BASE_IDX 2 3089#define regDC_PERFMON8_PERFMON_HI 0x0780 3090#define regDC_PERFMON8_PERFMON_HI_BASE_IDX 2 3091#define regDC_PERFMON8_PERFMON_LOW 0x0781 3092#define regDC_PERFMON8_PERFMON_LOW_BASE_IDX 2 3093 3094 3095// addressBlock: dce_dc_dcbubp2_dispdec_hubp_dispdec 3096// base address: 0x6e0 3097#define regHUBP2_DCSURF_SURFACE_CONFIG 0x079d 3098#define regHUBP2_DCSURF_SURFACE_CONFIG_BASE_IDX 2 3099#define regHUBP2_DCSURF_ADDR_CONFIG 0x079e 3100#define regHUBP2_DCSURF_ADDR_CONFIG_BASE_IDX 2 3101#define regHUBP2_DCSURF_TILING_CONFIG 0x079f 3102#define regHUBP2_DCSURF_TILING_CONFIG_BASE_IDX 2 3103#define regHUBP2_DCSURF_PRI_VIEWPORT_START 0x07a1 3104#define regHUBP2_DCSURF_PRI_VIEWPORT_START_BASE_IDX 2 3105#define regHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION 0x07a2 3106#define regHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2 3107#define regHUBP2_DCSURF_PRI_VIEWPORT_START_C 0x07a3 3108#define regHUBP2_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX 2 3109#define regHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C 0x07a4 3110#define regHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX 2 3111#define regHUBP2_DCSURF_SEC_VIEWPORT_START 0x07a5 3112#define regHUBP2_DCSURF_SEC_VIEWPORT_START_BASE_IDX 2 3113#define regHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION 0x07a6 3114#define regHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX 2 3115#define regHUBP2_DCSURF_SEC_VIEWPORT_START_C 0x07a7 3116#define regHUBP2_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX 2 3117#define regHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C 0x07a8 3118#define regHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX 2 3119#define regHUBP2_DCHUBP_REQ_SIZE_CONFIG 0x07a9 3120#define regHUBP2_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX 2 3121#define regHUBP2_DCHUBP_REQ_SIZE_CONFIG_C 0x07aa 3122#define regHUBP2_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX 2 3123#define regHUBP2_DCHUBP_CNTL 0x07ab 3124#define regHUBP2_DCHUBP_CNTL_BASE_IDX 2 3125#define regHUBP2_HUBP_CLK_CNTL 0x07ac 3126#define regHUBP2_HUBP_CLK_CNTL_BASE_IDX 2 3127#define regHUBP2_DCHUBP_VMPG_CONFIG 0x07ad 3128#define regHUBP2_DCHUBP_VMPG_CONFIG_BASE_IDX 2 3129#define regHUBP2_HUBPREQ_DEBUG_DB 0x07ae 3130#define regHUBP2_HUBPREQ_DEBUG_DB_BASE_IDX 2 3131#define regHUBP2_HUBPREQ_DEBUG 0x07af 3132#define regHUBP2_HUBPREQ_DEBUG_BASE_IDX 2 3133#define regHUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK 0x07b3 3134#define regHUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX 2 3135#define regHUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK 0x07b4 3136#define regHUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX 2 3137 3138 3139// addressBlock: dce_dc_dcbubp2_dispdec_hubpreq_dispdec 3140// base address: 0x6e0 3141#define regHUBPREQ2_DCSURF_SURFACE_PITCH 0x07bf 3142#define regHUBPREQ2_DCSURF_SURFACE_PITCH_BASE_IDX 2 3143#define regHUBPREQ2_DCSURF_SURFACE_PITCH_C 0x07c0 3144#define regHUBPREQ2_DCSURF_SURFACE_PITCH_C_BASE_IDX 2 3145#define regHUBPREQ2_VMID_SETTINGS_0 0x07c1 3146#define regHUBPREQ2_VMID_SETTINGS_0_BASE_IDX 2 3147#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS 0x07c2 3148#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2 3149#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH 0x07c3 3150#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 3151#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C 0x07c4 3152#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX 2 3153#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x07c5 3154#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 3155#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS 0x07c6 3156#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2 3157#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH 0x07c7 3158#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 3159#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C 0x07c8 3160#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX 2 3161#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x07c9 3162#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 3163#define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS 0x07ca 3164#define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX 2 3165#define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH 0x07cb 3166#define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 3167#define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C 0x07cc 3168#define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 3169#define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C 0x07cd 3170#define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 3171#define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS 0x07ce 3172#define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX 2 3173#define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH 0x07cf 3174#define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 3175#define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C 0x07d0 3176#define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 3177#define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C 0x07d1 3178#define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 3179#define regHUBPREQ2_DCSURF_SURFACE_CONTROL 0x07d2 3180#define regHUBPREQ2_DCSURF_SURFACE_CONTROL_BASE_IDX 2 3181#define regHUBPREQ2_DCSURF_FLIP_CONTROL 0x07d3 3182#define regHUBPREQ2_DCSURF_FLIP_CONTROL_BASE_IDX 2 3183#define regHUBPREQ2_DCSURF_FLIP_CONTROL2 0x07d4 3184#define regHUBPREQ2_DCSURF_FLIP_CONTROL2_BASE_IDX 2 3185#define regHUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT 0x07d8 3186#define regHUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX 2 3187#define regHUBPREQ2_DCSURF_SURFACE_INUSE 0x07d9 3188#define regHUBPREQ2_DCSURF_SURFACE_INUSE_BASE_IDX 2 3189#define regHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH 0x07da 3190#define regHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX 2 3191#define regHUBPREQ2_DCSURF_SURFACE_INUSE_C 0x07db 3192#define regHUBPREQ2_DCSURF_SURFACE_INUSE_C_BASE_IDX 2 3193#define regHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C 0x07dc 3194#define regHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX 2 3195#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE 0x07dd 3196#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX 2 3197#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH 0x07de 3198#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX 2 3199#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C 0x07df 3200#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX 2 3201#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C 0x07e0 3202#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX 2 3203#define regHUBPREQ2_DCN_EXPANSION_MODE 0x07e1 3204#define regHUBPREQ2_DCN_EXPANSION_MODE_BASE_IDX 2 3205#define regHUBPREQ2_DCN_TTU_QOS_WM 0x07e2 3206#define regHUBPREQ2_DCN_TTU_QOS_WM_BASE_IDX 2 3207#define regHUBPREQ2_DCN_GLOBAL_TTU_CNTL 0x07e3 3208#define regHUBPREQ2_DCN_GLOBAL_TTU_CNTL_BASE_IDX 2 3209#define regHUBPREQ2_DCN_SURF0_TTU_CNTL0 0x07e4 3210#define regHUBPREQ2_DCN_SURF0_TTU_CNTL0_BASE_IDX 2 3211#define regHUBPREQ2_DCN_SURF0_TTU_CNTL1 0x07e5 3212#define regHUBPREQ2_DCN_SURF0_TTU_CNTL1_BASE_IDX 2 3213#define regHUBPREQ2_DCN_SURF1_TTU_CNTL0 0x07e6 3214#define regHUBPREQ2_DCN_SURF1_TTU_CNTL0_BASE_IDX 2 3215#define regHUBPREQ2_DCN_SURF1_TTU_CNTL1 0x07e7 3216#define regHUBPREQ2_DCN_SURF1_TTU_CNTL1_BASE_IDX 2 3217#define regHUBPREQ2_DCN_CUR0_TTU_CNTL0 0x07e8 3218#define regHUBPREQ2_DCN_CUR0_TTU_CNTL0_BASE_IDX 2 3219#define regHUBPREQ2_DCN_CUR0_TTU_CNTL1 0x07e9 3220#define regHUBPREQ2_DCN_CUR0_TTU_CNTL1_BASE_IDX 2 3221#define regHUBPREQ2_DCN_CUR1_TTU_CNTL0 0x07ea 3222#define regHUBPREQ2_DCN_CUR1_TTU_CNTL0_BASE_IDX 2 3223#define regHUBPREQ2_DCN_CUR1_TTU_CNTL1 0x07eb 3224#define regHUBPREQ2_DCN_CUR1_TTU_CNTL1_BASE_IDX 2 3225#define regHUBPREQ2_DCN_DMDATA_VM_CNTL 0x07ec 3226#define regHUBPREQ2_DCN_DMDATA_VM_CNTL_BASE_IDX 2 3227#define regHUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR 0x07ed 3228#define regHUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 2 3229#define regHUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR 0x07ee 3230#define regHUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 2 3231#define regHUBPREQ2_DCN_VM_MX_L1_TLB_CNTL 0x07fb 3232#define regHUBPREQ2_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX 2 3233#define regHUBPREQ2_BLANK_OFFSET_0 0x07fc 3234#define regHUBPREQ2_BLANK_OFFSET_0_BASE_IDX 2 3235#define regHUBPREQ2_BLANK_OFFSET_1 0x07fd 3236#define regHUBPREQ2_BLANK_OFFSET_1_BASE_IDX 2 3237#define regHUBPREQ2_DST_DIMENSIONS 0x07fe 3238#define regHUBPREQ2_DST_DIMENSIONS_BASE_IDX 2 3239#define regHUBPREQ2_DST_AFTER_SCALER 0x07ff 3240#define regHUBPREQ2_DST_AFTER_SCALER_BASE_IDX 2 3241#define regHUBPREQ2_PREFETCH_SETTINGS 0x0800 3242#define regHUBPREQ2_PREFETCH_SETTINGS_BASE_IDX 2 3243#define regHUBPREQ2_PREFETCH_SETTINGS_C 0x0801 3244#define regHUBPREQ2_PREFETCH_SETTINGS_C_BASE_IDX 2 3245#define regHUBPREQ2_VBLANK_PARAMETERS_0 0x0802 3246#define regHUBPREQ2_VBLANK_PARAMETERS_0_BASE_IDX 2 3247#define regHUBPREQ2_VBLANK_PARAMETERS_1 0x0803 3248#define regHUBPREQ2_VBLANK_PARAMETERS_1_BASE_IDX 2 3249#define regHUBPREQ2_VBLANK_PARAMETERS_2 0x0804 3250#define regHUBPREQ2_VBLANK_PARAMETERS_2_BASE_IDX 2 3251#define regHUBPREQ2_VBLANK_PARAMETERS_3 0x0805 3252#define regHUBPREQ2_VBLANK_PARAMETERS_3_BASE_IDX 2 3253#define regHUBPREQ2_VBLANK_PARAMETERS_4 0x0806 3254#define regHUBPREQ2_VBLANK_PARAMETERS_4_BASE_IDX 2 3255#define regHUBPREQ2_FLIP_PARAMETERS_0 0x0807 3256#define regHUBPREQ2_FLIP_PARAMETERS_0_BASE_IDX 2 3257#define regHUBPREQ2_FLIP_PARAMETERS_1 0x0808 3258#define regHUBPREQ2_FLIP_PARAMETERS_1_BASE_IDX 2 3259#define regHUBPREQ2_FLIP_PARAMETERS_2 0x0809 3260#define regHUBPREQ2_FLIP_PARAMETERS_2_BASE_IDX 2 3261#define regHUBPREQ2_NOM_PARAMETERS_0 0x080a 3262#define regHUBPREQ2_NOM_PARAMETERS_0_BASE_IDX 2 3263#define regHUBPREQ2_NOM_PARAMETERS_1 0x080b 3264#define regHUBPREQ2_NOM_PARAMETERS_1_BASE_IDX 2 3265#define regHUBPREQ2_NOM_PARAMETERS_2 0x080c 3266#define regHUBPREQ2_NOM_PARAMETERS_2_BASE_IDX 2 3267#define regHUBPREQ2_NOM_PARAMETERS_3 0x080d 3268#define regHUBPREQ2_NOM_PARAMETERS_3_BASE_IDX 2 3269#define regHUBPREQ2_NOM_PARAMETERS_4 0x080e 3270#define regHUBPREQ2_NOM_PARAMETERS_4_BASE_IDX 2 3271#define regHUBPREQ2_NOM_PARAMETERS_5 0x080f 3272#define regHUBPREQ2_NOM_PARAMETERS_5_BASE_IDX 2 3273#define regHUBPREQ2_NOM_PARAMETERS_6 0x0810 3274#define regHUBPREQ2_NOM_PARAMETERS_6_BASE_IDX 2 3275#define regHUBPREQ2_NOM_PARAMETERS_7 0x0811 3276#define regHUBPREQ2_NOM_PARAMETERS_7_BASE_IDX 2 3277#define regHUBPREQ2_PER_LINE_DELIVERY_PRE 0x0812 3278#define regHUBPREQ2_PER_LINE_DELIVERY_PRE_BASE_IDX 2 3279#define regHUBPREQ2_PER_LINE_DELIVERY 0x0813 3280#define regHUBPREQ2_PER_LINE_DELIVERY_BASE_IDX 2 3281#define regHUBPREQ2_CURSOR_SETTINGS 0x0814 3282#define regHUBPREQ2_CURSOR_SETTINGS_BASE_IDX 2 3283#define regHUBPREQ2_REF_FREQ_TO_PIX_FREQ 0x0815 3284#define regHUBPREQ2_REF_FREQ_TO_PIX_FREQ_BASE_IDX 2 3285#define regHUBPREQ2_DST_Y_DELTA_DRQ_LIMIT 0x0816 3286#define regHUBPREQ2_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX 2 3287#define regHUBPREQ2_HUBPREQ_MEM_PWR_CTRL 0x0817 3288#define regHUBPREQ2_HUBPREQ_MEM_PWR_CTRL_BASE_IDX 2 3289#define regHUBPREQ2_HUBPREQ_MEM_PWR_STATUS 0x0818 3290#define regHUBPREQ2_HUBPREQ_MEM_PWR_STATUS_BASE_IDX 2 3291#define regHUBPREQ2_VBLANK_PARAMETERS_5 0x081b 3292#define regHUBPREQ2_VBLANK_PARAMETERS_5_BASE_IDX 2 3293#define regHUBPREQ2_VBLANK_PARAMETERS_6 0x081c 3294#define regHUBPREQ2_VBLANK_PARAMETERS_6_BASE_IDX 2 3295#define regHUBPREQ2_FLIP_PARAMETERS_3 0x081d 3296#define regHUBPREQ2_FLIP_PARAMETERS_3_BASE_IDX 2 3297#define regHUBPREQ2_FLIP_PARAMETERS_4 0x081e 3298#define regHUBPREQ2_FLIP_PARAMETERS_4_BASE_IDX 2 3299#define regHUBPREQ2_FLIP_PARAMETERS_5 0x081f 3300#define regHUBPREQ2_FLIP_PARAMETERS_5_BASE_IDX 2 3301#define regHUBPREQ2_FLIP_PARAMETERS_6 0x0820 3302#define regHUBPREQ2_FLIP_PARAMETERS_6_BASE_IDX 2 3303 3304 3305// addressBlock: dce_dc_dcbubp2_dispdec_hubpret_dispdec 3306// base address: 0x6e0 3307#define regHUBPRET2_HUBPRET_CONTROL 0x0824 3308#define regHUBPRET2_HUBPRET_CONTROL_BASE_IDX 2 3309#define regHUBPRET2_HUBPRET_MEM_PWR_CTRL 0x0825 3310#define regHUBPRET2_HUBPRET_MEM_PWR_CTRL_BASE_IDX 2 3311#define regHUBPRET2_HUBPRET_MEM_PWR_STATUS 0x0826 3312#define regHUBPRET2_HUBPRET_MEM_PWR_STATUS_BASE_IDX 2 3313#define regHUBPRET2_HUBPRET_READ_LINE_CTRL0 0x0827 3314#define regHUBPRET2_HUBPRET_READ_LINE_CTRL0_BASE_IDX 2 3315#define regHUBPRET2_HUBPRET_READ_LINE_CTRL1 0x0828 3316#define regHUBPRET2_HUBPRET_READ_LINE_CTRL1_BASE_IDX 2 3317#define regHUBPRET2_HUBPRET_READ_LINE0 0x0829 3318#define regHUBPRET2_HUBPRET_READ_LINE0_BASE_IDX 2 3319#define regHUBPRET2_HUBPRET_READ_LINE1 0x082a 3320#define regHUBPRET2_HUBPRET_READ_LINE1_BASE_IDX 2 3321#define regHUBPRET2_HUBPRET_INTERRUPT 0x082b 3322#define regHUBPRET2_HUBPRET_INTERRUPT_BASE_IDX 2 3323#define regHUBPRET2_HUBPRET_READ_LINE_VALUE 0x082c 3324#define regHUBPRET2_HUBPRET_READ_LINE_VALUE_BASE_IDX 2 3325#define regHUBPRET2_HUBPRET_READ_LINE_STATUS 0x082d 3326#define regHUBPRET2_HUBPRET_READ_LINE_STATUS_BASE_IDX 2 3327 3328 3329// addressBlock: dce_dc_dcbubp2_dispdec_cursor0_dispdec 3330// base address: 0x6e0 3331#define regCURSOR0_2_CURSOR_CONTROL 0x0830 3332#define regCURSOR0_2_CURSOR_CONTROL_BASE_IDX 2 3333#define regCURSOR0_2_CURSOR_SURFACE_ADDRESS 0x0831 3334#define regCURSOR0_2_CURSOR_SURFACE_ADDRESS_BASE_IDX 2 3335#define regCURSOR0_2_CURSOR_SURFACE_ADDRESS_HIGH 0x0832 3336#define regCURSOR0_2_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX 2 3337#define regCURSOR0_2_CURSOR_SIZE 0x0833 3338#define regCURSOR0_2_CURSOR_SIZE_BASE_IDX 2 3339#define regCURSOR0_2_CURSOR_POSITION 0x0834 3340#define regCURSOR0_2_CURSOR_POSITION_BASE_IDX 2 3341#define regCURSOR0_2_CURSOR_HOT_SPOT 0x0835 3342#define regCURSOR0_2_CURSOR_HOT_SPOT_BASE_IDX 2 3343#define regCURSOR0_2_CURSOR_STEREO_CONTROL 0x0836 3344#define regCURSOR0_2_CURSOR_STEREO_CONTROL_BASE_IDX 2 3345#define regCURSOR0_2_CURSOR_DST_OFFSET 0x0837 3346#define regCURSOR0_2_CURSOR_DST_OFFSET_BASE_IDX 2 3347#define regCURSOR0_2_CURSOR_MEM_PWR_CTRL 0x0838 3348#define regCURSOR0_2_CURSOR_MEM_PWR_CTRL_BASE_IDX 2 3349#define regCURSOR0_2_CURSOR_MEM_PWR_STATUS 0x0839 3350#define regCURSOR0_2_CURSOR_MEM_PWR_STATUS_BASE_IDX 2 3351#define regCURSOR0_2_DMDATA_ADDRESS_HIGH 0x083a 3352#define regCURSOR0_2_DMDATA_ADDRESS_HIGH_BASE_IDX 2 3353#define regCURSOR0_2_DMDATA_ADDRESS_LOW 0x083b 3354#define regCURSOR0_2_DMDATA_ADDRESS_LOW_BASE_IDX 2 3355#define regCURSOR0_2_DMDATA_CNTL 0x083c 3356#define regCURSOR0_2_DMDATA_CNTL_BASE_IDX 2 3357#define regCURSOR0_2_DMDATA_QOS_CNTL 0x083d 3358#define regCURSOR0_2_DMDATA_QOS_CNTL_BASE_IDX 2 3359#define regCURSOR0_2_DMDATA_STATUS 0x083e 3360#define regCURSOR0_2_DMDATA_STATUS_BASE_IDX 2 3361#define regCURSOR0_2_DMDATA_SW_CNTL 0x083f 3362#define regCURSOR0_2_DMDATA_SW_CNTL_BASE_IDX 2 3363#define regCURSOR0_2_DMDATA_SW_DATA 0x0840 3364#define regCURSOR0_2_DMDATA_SW_DATA_BASE_IDX 2 3365 3366 3367// addressBlock: dce_dc_dcbubp2_dispdec_hubp_dcperfmon_dc_perfmon_dispdec 3368// base address: 0x2154 3369#define regDC_PERFMON9_PERFCOUNTER_CNTL 0x0855 3370#define regDC_PERFMON9_PERFCOUNTER_CNTL_BASE_IDX 2 3371#define regDC_PERFMON9_PERFCOUNTER_CNTL2 0x0856 3372#define regDC_PERFMON9_PERFCOUNTER_CNTL2_BASE_IDX 2 3373#define regDC_PERFMON9_PERFCOUNTER_STATE 0x0857 3374#define regDC_PERFMON9_PERFCOUNTER_STATE_BASE_IDX 2 3375#define regDC_PERFMON9_PERFMON_CNTL 0x0858 3376#define regDC_PERFMON9_PERFMON_CNTL_BASE_IDX 2 3377#define regDC_PERFMON9_PERFMON_CNTL2 0x0859 3378#define regDC_PERFMON9_PERFMON_CNTL2_BASE_IDX 2 3379#define regDC_PERFMON9_PERFMON_CVALUE_INT_MISC 0x085a 3380#define regDC_PERFMON9_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 3381#define regDC_PERFMON9_PERFMON_CVALUE_LOW 0x085b 3382#define regDC_PERFMON9_PERFMON_CVALUE_LOW_BASE_IDX 2 3383#define regDC_PERFMON9_PERFMON_HI 0x085c 3384#define regDC_PERFMON9_PERFMON_HI_BASE_IDX 2 3385#define regDC_PERFMON9_PERFMON_LOW 0x085d 3386#define regDC_PERFMON9_PERFMON_LOW_BASE_IDX 2 3387 3388 3389// addressBlock: dce_dc_dcbubp3_dispdec_hubp_dispdec 3390// base address: 0xa50 3391#define regHUBP3_DCSURF_SURFACE_CONFIG 0x0879 3392#define regHUBP3_DCSURF_SURFACE_CONFIG_BASE_IDX 2 3393#define regHUBP3_DCSURF_ADDR_CONFIG 0x087a 3394#define regHUBP3_DCSURF_ADDR_CONFIG_BASE_IDX 2 3395#define regHUBP3_DCSURF_TILING_CONFIG 0x087b 3396#define regHUBP3_DCSURF_TILING_CONFIG_BASE_IDX 2 3397#define regHUBP3_DCSURF_PRI_VIEWPORT_START 0x087d 3398#define regHUBP3_DCSURF_PRI_VIEWPORT_START_BASE_IDX 2 3399#define regHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION 0x087e 3400#define regHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2 3401#define regHUBP3_DCSURF_PRI_VIEWPORT_START_C 0x087f 3402#define regHUBP3_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX 2 3403#define regHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C 0x0880 3404#define regHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX 2 3405#define regHUBP3_DCSURF_SEC_VIEWPORT_START 0x0881 3406#define regHUBP3_DCSURF_SEC_VIEWPORT_START_BASE_IDX 2 3407#define regHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION 0x0882 3408#define regHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX 2 3409#define regHUBP3_DCSURF_SEC_VIEWPORT_START_C 0x0883 3410#define regHUBP3_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX 2 3411#define regHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C 0x0884 3412#define regHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX 2 3413#define regHUBP3_DCHUBP_REQ_SIZE_CONFIG 0x0885 3414#define regHUBP3_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX 2 3415#define regHUBP3_DCHUBP_REQ_SIZE_CONFIG_C 0x0886 3416#define regHUBP3_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX 2 3417#define regHUBP3_DCHUBP_CNTL 0x0887 3418#define regHUBP3_DCHUBP_CNTL_BASE_IDX 2 3419#define regHUBP3_HUBP_CLK_CNTL 0x0888 3420#define regHUBP3_HUBP_CLK_CNTL_BASE_IDX 2 3421#define regHUBP3_DCHUBP_VMPG_CONFIG 0x0889 3422#define regHUBP3_DCHUBP_VMPG_CONFIG_BASE_IDX 2 3423#define regHUBP3_HUBPREQ_DEBUG_DB 0x088a 3424#define regHUBP3_HUBPREQ_DEBUG_DB_BASE_IDX 2 3425#define regHUBP3_HUBPREQ_DEBUG 0x088b 3426#define regHUBP3_HUBPREQ_DEBUG_BASE_IDX 2 3427#define regHUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK 0x088f 3428#define regHUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX 2 3429#define regHUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK 0x0890 3430#define regHUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX 2 3431 3432 3433// addressBlock: dce_dc_dcbubp3_dispdec_hubpreq_dispdec 3434// base address: 0xa50 3435#define regHUBPREQ3_DCSURF_SURFACE_PITCH 0x089b 3436#define regHUBPREQ3_DCSURF_SURFACE_PITCH_BASE_IDX 2 3437#define regHUBPREQ3_DCSURF_SURFACE_PITCH_C 0x089c 3438#define regHUBPREQ3_DCSURF_SURFACE_PITCH_C_BASE_IDX 2 3439#define regHUBPREQ3_VMID_SETTINGS_0 0x089d 3440#define regHUBPREQ3_VMID_SETTINGS_0_BASE_IDX 2 3441#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS 0x089e 3442#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2 3443#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH 0x089f 3444#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 3445#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C 0x08a0 3446#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX 2 3447#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x08a1 3448#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 3449#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS 0x08a2 3450#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2 3451#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH 0x08a3 3452#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 3453#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C 0x08a4 3454#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX 2 3455#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x08a5 3456#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 3457#define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS 0x08a6 3458#define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX 2 3459#define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH 0x08a7 3460#define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 3461#define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C 0x08a8 3462#define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 3463#define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C 0x08a9 3464#define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 3465#define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS 0x08aa 3466#define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX 2 3467#define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH 0x08ab 3468#define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 3469#define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C 0x08ac 3470#define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 3471#define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C 0x08ad 3472#define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 3473#define regHUBPREQ3_DCSURF_SURFACE_CONTROL 0x08ae 3474#define regHUBPREQ3_DCSURF_SURFACE_CONTROL_BASE_IDX 2 3475#define regHUBPREQ3_DCSURF_FLIP_CONTROL 0x08af 3476#define regHUBPREQ3_DCSURF_FLIP_CONTROL_BASE_IDX 2 3477#define regHUBPREQ3_DCSURF_FLIP_CONTROL2 0x08b0 3478#define regHUBPREQ3_DCSURF_FLIP_CONTROL2_BASE_IDX 2 3479#define regHUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT 0x08b4 3480#define regHUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX 2 3481#define regHUBPREQ3_DCSURF_SURFACE_INUSE 0x08b5 3482#define regHUBPREQ3_DCSURF_SURFACE_INUSE_BASE_IDX 2 3483#define regHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH 0x08b6 3484#define regHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX 2 3485#define regHUBPREQ3_DCSURF_SURFACE_INUSE_C 0x08b7 3486#define regHUBPREQ3_DCSURF_SURFACE_INUSE_C_BASE_IDX 2 3487#define regHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C 0x08b8 3488#define regHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX 2 3489#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE 0x08b9 3490#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX 2 3491#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH 0x08ba 3492#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX 2 3493#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C 0x08bb 3494#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX 2 3495#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C 0x08bc 3496#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX 2 3497#define regHUBPREQ3_DCN_EXPANSION_MODE 0x08bd 3498#define regHUBPREQ3_DCN_EXPANSION_MODE_BASE_IDX 2 3499#define regHUBPREQ3_DCN_TTU_QOS_WM 0x08be 3500#define regHUBPREQ3_DCN_TTU_QOS_WM_BASE_IDX 2 3501#define regHUBPREQ3_DCN_GLOBAL_TTU_CNTL 0x08bf 3502#define regHUBPREQ3_DCN_GLOBAL_TTU_CNTL_BASE_IDX 2 3503#define regHUBPREQ3_DCN_SURF0_TTU_CNTL0 0x08c0 3504#define regHUBPREQ3_DCN_SURF0_TTU_CNTL0_BASE_IDX 2 3505#define regHUBPREQ3_DCN_SURF0_TTU_CNTL1 0x08c1 3506#define regHUBPREQ3_DCN_SURF0_TTU_CNTL1_BASE_IDX 2 3507#define regHUBPREQ3_DCN_SURF1_TTU_CNTL0 0x08c2 3508#define regHUBPREQ3_DCN_SURF1_TTU_CNTL0_BASE_IDX 2 3509#define regHUBPREQ3_DCN_SURF1_TTU_CNTL1 0x08c3 3510#define regHUBPREQ3_DCN_SURF1_TTU_CNTL1_BASE_IDX 2 3511#define regHUBPREQ3_DCN_CUR0_TTU_CNTL0 0x08c4 3512#define regHUBPREQ3_DCN_CUR0_TTU_CNTL0_BASE_IDX 2 3513#define regHUBPREQ3_DCN_CUR0_TTU_CNTL1 0x08c5 3514#define regHUBPREQ3_DCN_CUR0_TTU_CNTL1_BASE_IDX 2 3515#define regHUBPREQ3_DCN_CUR1_TTU_CNTL0 0x08c6 3516#define regHUBPREQ3_DCN_CUR1_TTU_CNTL0_BASE_IDX 2 3517#define regHUBPREQ3_DCN_CUR1_TTU_CNTL1 0x08c7 3518#define regHUBPREQ3_DCN_CUR1_TTU_CNTL1_BASE_IDX 2 3519#define regHUBPREQ3_DCN_DMDATA_VM_CNTL 0x08c8 3520#define regHUBPREQ3_DCN_DMDATA_VM_CNTL_BASE_IDX 2 3521#define regHUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR 0x08c9 3522#define regHUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 2 3523#define regHUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR 0x08ca 3524#define regHUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 2 3525#define regHUBPREQ3_DCN_VM_MX_L1_TLB_CNTL 0x08d7 3526#define regHUBPREQ3_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX 2 3527#define regHUBPREQ3_BLANK_OFFSET_0 0x08d8 3528#define regHUBPREQ3_BLANK_OFFSET_0_BASE_IDX 2 3529#define regHUBPREQ3_BLANK_OFFSET_1 0x08d9 3530#define regHUBPREQ3_BLANK_OFFSET_1_BASE_IDX 2 3531#define regHUBPREQ3_DST_DIMENSIONS 0x08da 3532#define regHUBPREQ3_DST_DIMENSIONS_BASE_IDX 2 3533#define regHUBPREQ3_DST_AFTER_SCALER 0x08db 3534#define regHUBPREQ3_DST_AFTER_SCALER_BASE_IDX 2 3535#define regHUBPREQ3_PREFETCH_SETTINGS 0x08dc 3536#define regHUBPREQ3_PREFETCH_SETTINGS_BASE_IDX 2 3537#define regHUBPREQ3_PREFETCH_SETTINGS_C 0x08dd 3538#define regHUBPREQ3_PREFETCH_SETTINGS_C_BASE_IDX 2 3539#define regHUBPREQ3_VBLANK_PARAMETERS_0 0x08de 3540#define regHUBPREQ3_VBLANK_PARAMETERS_0_BASE_IDX 2 3541#define regHUBPREQ3_VBLANK_PARAMETERS_1 0x08df 3542#define regHUBPREQ3_VBLANK_PARAMETERS_1_BASE_IDX 2 3543#define regHUBPREQ3_VBLANK_PARAMETERS_2 0x08e0 3544#define regHUBPREQ3_VBLANK_PARAMETERS_2_BASE_IDX 2 3545#define regHUBPREQ3_VBLANK_PARAMETERS_3 0x08e1 3546#define regHUBPREQ3_VBLANK_PARAMETERS_3_BASE_IDX 2 3547#define regHUBPREQ3_VBLANK_PARAMETERS_4 0x08e2 3548#define regHUBPREQ3_VBLANK_PARAMETERS_4_BASE_IDX 2 3549#define regHUBPREQ3_FLIP_PARAMETERS_0 0x08e3 3550#define regHUBPREQ3_FLIP_PARAMETERS_0_BASE_IDX 2 3551#define regHUBPREQ3_FLIP_PARAMETERS_1 0x08e4 3552#define regHUBPREQ3_FLIP_PARAMETERS_1_BASE_IDX 2 3553#define regHUBPREQ3_FLIP_PARAMETERS_2 0x08e5 3554#define regHUBPREQ3_FLIP_PARAMETERS_2_BASE_IDX 2 3555#define regHUBPREQ3_NOM_PARAMETERS_0 0x08e6 3556#define regHUBPREQ3_NOM_PARAMETERS_0_BASE_IDX 2 3557#define regHUBPREQ3_NOM_PARAMETERS_1 0x08e7 3558#define regHUBPREQ3_NOM_PARAMETERS_1_BASE_IDX 2 3559#define regHUBPREQ3_NOM_PARAMETERS_2 0x08e8 3560#define regHUBPREQ3_NOM_PARAMETERS_2_BASE_IDX 2 3561#define regHUBPREQ3_NOM_PARAMETERS_3 0x08e9 3562#define regHUBPREQ3_NOM_PARAMETERS_3_BASE_IDX 2 3563#define regHUBPREQ3_NOM_PARAMETERS_4 0x08ea 3564#define regHUBPREQ3_NOM_PARAMETERS_4_BASE_IDX 2 3565#define regHUBPREQ3_NOM_PARAMETERS_5 0x08eb 3566#define regHUBPREQ3_NOM_PARAMETERS_5_BASE_IDX 2 3567#define regHUBPREQ3_NOM_PARAMETERS_6 0x08ec 3568#define regHUBPREQ3_NOM_PARAMETERS_6_BASE_IDX 2 3569#define regHUBPREQ3_NOM_PARAMETERS_7 0x08ed 3570#define regHUBPREQ3_NOM_PARAMETERS_7_BASE_IDX 2 3571#define regHUBPREQ3_PER_LINE_DELIVERY_PRE 0x08ee 3572#define regHUBPREQ3_PER_LINE_DELIVERY_PRE_BASE_IDX 2 3573#define regHUBPREQ3_PER_LINE_DELIVERY 0x08ef 3574#define regHUBPREQ3_PER_LINE_DELIVERY_BASE_IDX 2 3575#define regHUBPREQ3_CURSOR_SETTINGS 0x08f0 3576#define regHUBPREQ3_CURSOR_SETTINGS_BASE_IDX 2 3577#define regHUBPREQ3_REF_FREQ_TO_PIX_FREQ 0x08f1 3578#define regHUBPREQ3_REF_FREQ_TO_PIX_FREQ_BASE_IDX 2 3579#define regHUBPREQ3_DST_Y_DELTA_DRQ_LIMIT 0x08f2 3580#define regHUBPREQ3_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX 2 3581#define regHUBPREQ3_HUBPREQ_MEM_PWR_CTRL 0x08f3 3582#define regHUBPREQ3_HUBPREQ_MEM_PWR_CTRL_BASE_IDX 2 3583#define regHUBPREQ3_HUBPREQ_MEM_PWR_STATUS 0x08f4 3584#define regHUBPREQ3_HUBPREQ_MEM_PWR_STATUS_BASE_IDX 2 3585#define regHUBPREQ3_VBLANK_PARAMETERS_5 0x08f7 3586#define regHUBPREQ3_VBLANK_PARAMETERS_5_BASE_IDX 2 3587#define regHUBPREQ3_VBLANK_PARAMETERS_6 0x08f8 3588#define regHUBPREQ3_VBLANK_PARAMETERS_6_BASE_IDX 2 3589#define regHUBPREQ3_FLIP_PARAMETERS_3 0x08f9 3590#define regHUBPREQ3_FLIP_PARAMETERS_3_BASE_IDX 2 3591#define regHUBPREQ3_FLIP_PARAMETERS_4 0x08fa 3592#define regHUBPREQ3_FLIP_PARAMETERS_4_BASE_IDX 2 3593#define regHUBPREQ3_FLIP_PARAMETERS_5 0x08fb 3594#define regHUBPREQ3_FLIP_PARAMETERS_5_BASE_IDX 2 3595#define regHUBPREQ3_FLIP_PARAMETERS_6 0x08fc 3596#define regHUBPREQ3_FLIP_PARAMETERS_6_BASE_IDX 2 3597 3598 3599// addressBlock: dce_dc_dcbubp3_dispdec_hubpret_dispdec 3600// base address: 0xa50 3601#define regHUBPRET3_HUBPRET_CONTROL 0x0900 3602#define regHUBPRET3_HUBPRET_CONTROL_BASE_IDX 2 3603#define regHUBPRET3_HUBPRET_MEM_PWR_CTRL 0x0901 3604#define regHUBPRET3_HUBPRET_MEM_PWR_CTRL_BASE_IDX 2 3605#define regHUBPRET3_HUBPRET_MEM_PWR_STATUS 0x0902 3606#define regHUBPRET3_HUBPRET_MEM_PWR_STATUS_BASE_IDX 2 3607#define regHUBPRET3_HUBPRET_READ_LINE_CTRL0 0x0903 3608#define regHUBPRET3_HUBPRET_READ_LINE_CTRL0_BASE_IDX 2 3609#define regHUBPRET3_HUBPRET_READ_LINE_CTRL1 0x0904 3610#define regHUBPRET3_HUBPRET_READ_LINE_CTRL1_BASE_IDX 2 3611#define regHUBPRET3_HUBPRET_READ_LINE0 0x0905 3612#define regHUBPRET3_HUBPRET_READ_LINE0_BASE_IDX 2 3613#define regHUBPRET3_HUBPRET_READ_LINE1 0x0906 3614#define regHUBPRET3_HUBPRET_READ_LINE1_BASE_IDX 2 3615#define regHUBPRET3_HUBPRET_INTERRUPT 0x0907 3616#define regHUBPRET3_HUBPRET_INTERRUPT_BASE_IDX 2 3617#define regHUBPRET3_HUBPRET_READ_LINE_VALUE 0x0908 3618#define regHUBPRET3_HUBPRET_READ_LINE_VALUE_BASE_IDX 2 3619#define regHUBPRET3_HUBPRET_READ_LINE_STATUS 0x0909 3620#define regHUBPRET3_HUBPRET_READ_LINE_STATUS_BASE_IDX 2 3621 3622 3623// addressBlock: dce_dc_dcbubp3_dispdec_cursor0_dispdec 3624// base address: 0xa50 3625#define regCURSOR0_3_CURSOR_CONTROL 0x090c 3626#define regCURSOR0_3_CURSOR_CONTROL_BASE_IDX 2 3627#define regCURSOR0_3_CURSOR_SURFACE_ADDRESS 0x090d 3628#define regCURSOR0_3_CURSOR_SURFACE_ADDRESS_BASE_IDX 2 3629#define regCURSOR0_3_CURSOR_SURFACE_ADDRESS_HIGH 0x090e 3630#define regCURSOR0_3_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX 2 3631#define regCURSOR0_3_CURSOR_SIZE 0x090f 3632#define regCURSOR0_3_CURSOR_SIZE_BASE_IDX 2 3633#define regCURSOR0_3_CURSOR_POSITION 0x0910 3634#define regCURSOR0_3_CURSOR_POSITION_BASE_IDX 2 3635#define regCURSOR0_3_CURSOR_HOT_SPOT 0x0911 3636#define regCURSOR0_3_CURSOR_HOT_SPOT_BASE_IDX 2 3637#define regCURSOR0_3_CURSOR_STEREO_CONTROL 0x0912 3638#define regCURSOR0_3_CURSOR_STEREO_CONTROL_BASE_IDX 2 3639#define regCURSOR0_3_CURSOR_DST_OFFSET 0x0913 3640#define regCURSOR0_3_CURSOR_DST_OFFSET_BASE_IDX 2 3641#define regCURSOR0_3_CURSOR_MEM_PWR_CTRL 0x0914 3642#define regCURSOR0_3_CURSOR_MEM_PWR_CTRL_BASE_IDX 2 3643#define regCURSOR0_3_CURSOR_MEM_PWR_STATUS 0x0915 3644#define regCURSOR0_3_CURSOR_MEM_PWR_STATUS_BASE_IDX 2 3645#define regCURSOR0_3_DMDATA_ADDRESS_HIGH 0x0916 3646#define regCURSOR0_3_DMDATA_ADDRESS_HIGH_BASE_IDX 2 3647#define regCURSOR0_3_DMDATA_ADDRESS_LOW 0x0917 3648#define regCURSOR0_3_DMDATA_ADDRESS_LOW_BASE_IDX 2 3649#define regCURSOR0_3_DMDATA_CNTL 0x0918 3650#define regCURSOR0_3_DMDATA_CNTL_BASE_IDX 2 3651#define regCURSOR0_3_DMDATA_QOS_CNTL 0x0919 3652#define regCURSOR0_3_DMDATA_QOS_CNTL_BASE_IDX 2 3653#define regCURSOR0_3_DMDATA_STATUS 0x091a 3654#define regCURSOR0_3_DMDATA_STATUS_BASE_IDX 2 3655#define regCURSOR0_3_DMDATA_SW_CNTL 0x091b 3656#define regCURSOR0_3_DMDATA_SW_CNTL_BASE_IDX 2 3657#define regCURSOR0_3_DMDATA_SW_DATA 0x091c 3658#define regCURSOR0_3_DMDATA_SW_DATA_BASE_IDX 2 3659 3660 3661// addressBlock: dce_dc_dcbubp3_dispdec_hubp_dcperfmon_dc_perfmon_dispdec 3662// base address: 0x24c4 3663#define regDC_PERFMON10_PERFCOUNTER_CNTL 0x0931 3664#define regDC_PERFMON10_PERFCOUNTER_CNTL_BASE_IDX 2 3665#define regDC_PERFMON10_PERFCOUNTER_CNTL2 0x0932 3666#define regDC_PERFMON10_PERFCOUNTER_CNTL2_BASE_IDX 2 3667#define regDC_PERFMON10_PERFCOUNTER_STATE 0x0933 3668#define regDC_PERFMON10_PERFCOUNTER_STATE_BASE_IDX 2 3669#define regDC_PERFMON10_PERFMON_CNTL 0x0934 3670#define regDC_PERFMON10_PERFMON_CNTL_BASE_IDX 2 3671#define regDC_PERFMON10_PERFMON_CNTL2 0x0935 3672#define regDC_PERFMON10_PERFMON_CNTL2_BASE_IDX 2 3673#define regDC_PERFMON10_PERFMON_CVALUE_INT_MISC 0x0936 3674#define regDC_PERFMON10_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 3675#define regDC_PERFMON10_PERFMON_CVALUE_LOW 0x0937 3676#define regDC_PERFMON10_PERFMON_CVALUE_LOW_BASE_IDX 2 3677#define regDC_PERFMON10_PERFMON_HI 0x0938 3678#define regDC_PERFMON10_PERFMON_HI_BASE_IDX 2 3679#define regDC_PERFMON10_PERFMON_LOW 0x0939 3680#define regDC_PERFMON10_PERFMON_LOW_BASE_IDX 2 3681 3682 3683// addressBlock: dce_dc_dpp0_dispdec_cnvc_cfg_dispdec 3684// base address: 0x0 3685#define regCNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT 0x0ccf 3686#define regCNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX 2 3687#define regCNVC_CFG0_FORMAT_CONTROL 0x0cd0 3688#define regCNVC_CFG0_FORMAT_CONTROL_BASE_IDX 2 3689#define regCNVC_CFG0_FCNV_FP_BIAS_R 0x0cd1 3690#define regCNVC_CFG0_FCNV_FP_BIAS_R_BASE_IDX 2 3691#define regCNVC_CFG0_FCNV_FP_BIAS_G 0x0cd2 3692#define regCNVC_CFG0_FCNV_FP_BIAS_G_BASE_IDX 2 3693#define regCNVC_CFG0_FCNV_FP_BIAS_B 0x0cd3 3694#define regCNVC_CFG0_FCNV_FP_BIAS_B_BASE_IDX 2 3695#define regCNVC_CFG0_FCNV_FP_SCALE_R 0x0cd4 3696#define regCNVC_CFG0_FCNV_FP_SCALE_R_BASE_IDX 2 3697#define regCNVC_CFG0_FCNV_FP_SCALE_G 0x0cd5 3698#define regCNVC_CFG0_FCNV_FP_SCALE_G_BASE_IDX 2 3699#define regCNVC_CFG0_FCNV_FP_SCALE_B 0x0cd6 3700#define regCNVC_CFG0_FCNV_FP_SCALE_B_BASE_IDX 2 3701#define regCNVC_CFG0_COLOR_KEYER_CONTROL 0x0cd7 3702#define regCNVC_CFG0_COLOR_KEYER_CONTROL_BASE_IDX 2 3703#define regCNVC_CFG0_COLOR_KEYER_ALPHA 0x0cd8 3704#define regCNVC_CFG0_COLOR_KEYER_ALPHA_BASE_IDX 2 3705#define regCNVC_CFG0_COLOR_KEYER_RED 0x0cd9 3706#define regCNVC_CFG0_COLOR_KEYER_RED_BASE_IDX 2 3707#define regCNVC_CFG0_COLOR_KEYER_GREEN 0x0cda 3708#define regCNVC_CFG0_COLOR_KEYER_GREEN_BASE_IDX 2 3709#define regCNVC_CFG0_COLOR_KEYER_BLUE 0x0cdb 3710#define regCNVC_CFG0_COLOR_KEYER_BLUE_BASE_IDX 2 3711#define regCNVC_CFG0_ALPHA_2BIT_LUT 0x0cdd 3712#define regCNVC_CFG0_ALPHA_2BIT_LUT_BASE_IDX 2 3713#define regCNVC_CFG0_PRE_DEALPHA 0x0cde 3714#define regCNVC_CFG0_PRE_DEALPHA_BASE_IDX 2 3715#define regCNVC_CFG0_PRE_CSC_MODE 0x0cdf 3716#define regCNVC_CFG0_PRE_CSC_MODE_BASE_IDX 2 3717#define regCNVC_CFG0_PRE_CSC_C11_C12 0x0ce0 3718#define regCNVC_CFG0_PRE_CSC_C11_C12_BASE_IDX 2 3719#define regCNVC_CFG0_PRE_CSC_C13_C14 0x0ce1 3720#define regCNVC_CFG0_PRE_CSC_C13_C14_BASE_IDX 2 3721#define regCNVC_CFG0_PRE_CSC_C21_C22 0x0ce2 3722#define regCNVC_CFG0_PRE_CSC_C21_C22_BASE_IDX 2 3723#define regCNVC_CFG0_PRE_CSC_C23_C24 0x0ce3 3724#define regCNVC_CFG0_PRE_CSC_C23_C24_BASE_IDX 2 3725#define regCNVC_CFG0_PRE_CSC_C31_C32 0x0ce4 3726#define regCNVC_CFG0_PRE_CSC_C31_C32_BASE_IDX 2 3727#define regCNVC_CFG0_PRE_CSC_C33_C34 0x0ce5 3728#define regCNVC_CFG0_PRE_CSC_C33_C34_BASE_IDX 2 3729#define regCNVC_CFG0_PRE_CSC_B_C11_C12 0x0ce6 3730#define regCNVC_CFG0_PRE_CSC_B_C11_C12_BASE_IDX 2 3731#define regCNVC_CFG0_PRE_CSC_B_C13_C14 0x0ce7 3732#define regCNVC_CFG0_PRE_CSC_B_C13_C14_BASE_IDX 2 3733#define regCNVC_CFG0_PRE_CSC_B_C21_C22 0x0ce8 3734#define regCNVC_CFG0_PRE_CSC_B_C21_C22_BASE_IDX 2 3735#define regCNVC_CFG0_PRE_CSC_B_C23_C24 0x0ce9 3736#define regCNVC_CFG0_PRE_CSC_B_C23_C24_BASE_IDX 2 3737#define regCNVC_CFG0_PRE_CSC_B_C31_C32 0x0cea 3738#define regCNVC_CFG0_PRE_CSC_B_C31_C32_BASE_IDX 2 3739#define regCNVC_CFG0_PRE_CSC_B_C33_C34 0x0ceb 3740#define regCNVC_CFG0_PRE_CSC_B_C33_C34_BASE_IDX 2 3741#define regCNVC_CFG0_CNVC_COEF_FORMAT 0x0cec 3742#define regCNVC_CFG0_CNVC_COEF_FORMAT_BASE_IDX 2 3743#define regCNVC_CFG0_PRE_DEGAM 0x0ced 3744#define regCNVC_CFG0_PRE_DEGAM_BASE_IDX 2 3745#define regCNVC_CFG0_PRE_REALPHA 0x0cee 3746#define regCNVC_CFG0_PRE_REALPHA_BASE_IDX 2 3747 3748 3749// addressBlock: dce_dc_dpp0_dispdec_cnvc_cur_dispdec 3750// base address: 0x0 3751#define regCNVC_CUR0_CURSOR0_CONTROL 0x0cf1 3752#define regCNVC_CUR0_CURSOR0_CONTROL_BASE_IDX 2 3753#define regCNVC_CUR0_CURSOR0_COLOR0 0x0cf2 3754#define regCNVC_CUR0_CURSOR0_COLOR0_BASE_IDX 2 3755#define regCNVC_CUR0_CURSOR0_COLOR1 0x0cf3 3756#define regCNVC_CUR0_CURSOR0_COLOR1_BASE_IDX 2 3757#define regCNVC_CUR0_CURSOR0_FP_SCALE_BIAS 0x0cf4 3758#define regCNVC_CUR0_CURSOR0_FP_SCALE_BIAS_BASE_IDX 2 3759 3760 3761// addressBlock: dce_dc_dpp0_dispdec_dscl_dispdec 3762// base address: 0x0 3763#define regDSCL0_SCL_COEF_RAM_TAP_SELECT 0x0cf9 3764#define regDSCL0_SCL_COEF_RAM_TAP_SELECT_BASE_IDX 2 3765#define regDSCL0_SCL_COEF_RAM_TAP_DATA 0x0cfa 3766#define regDSCL0_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2 3767#define regDSCL0_SCL_MODE 0x0cfb 3768#define regDSCL0_SCL_MODE_BASE_IDX 2 3769#define regDSCL0_SCL_TAP_CONTROL 0x0cfc 3770#define regDSCL0_SCL_TAP_CONTROL_BASE_IDX 2 3771#define regDSCL0_DSCL_CONTROL 0x0cfd 3772#define regDSCL0_DSCL_CONTROL_BASE_IDX 2 3773#define regDSCL0_DSCL_2TAP_CONTROL 0x0cfe 3774#define regDSCL0_DSCL_2TAP_CONTROL_BASE_IDX 2 3775#define regDSCL0_SCL_MANUAL_REPLICATE_CONTROL 0x0cff 3776#define regDSCL0_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2 3777#define regDSCL0_SCL_HORZ_FILTER_SCALE_RATIO 0x0d00 3778#define regDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2 3779#define regDSCL0_SCL_HORZ_FILTER_INIT 0x0d01 3780#define regDSCL0_SCL_HORZ_FILTER_INIT_BASE_IDX 2 3781#define regDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C 0x0d02 3782#define regDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX 2 3783#define regDSCL0_SCL_HORZ_FILTER_INIT_C 0x0d03 3784#define regDSCL0_SCL_HORZ_FILTER_INIT_C_BASE_IDX 2 3785#define regDSCL0_SCL_VERT_FILTER_SCALE_RATIO 0x0d04 3786#define regDSCL0_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2 3787#define regDSCL0_SCL_VERT_FILTER_INIT 0x0d05 3788#define regDSCL0_SCL_VERT_FILTER_INIT_BASE_IDX 2 3789#define regDSCL0_SCL_VERT_FILTER_INIT_BOT 0x0d06 3790#define regDSCL0_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2 3791#define regDSCL0_SCL_VERT_FILTER_SCALE_RATIO_C 0x0d07 3792#define regDSCL0_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX 2 3793#define regDSCL0_SCL_VERT_FILTER_INIT_C 0x0d08 3794#define regDSCL0_SCL_VERT_FILTER_INIT_C_BASE_IDX 2 3795#define regDSCL0_SCL_VERT_FILTER_INIT_BOT_C 0x0d09 3796#define regDSCL0_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX 2 3797#define regDSCL0_SCL_BLACK_COLOR 0x0d0a 3798#define regDSCL0_SCL_BLACK_COLOR_BASE_IDX 2 3799#define regDSCL0_DSCL_UPDATE 0x0d0b 3800#define regDSCL0_DSCL_UPDATE_BASE_IDX 2 3801#define regDSCL0_DSCL_AUTOCAL 0x0d0c 3802#define regDSCL0_DSCL_AUTOCAL_BASE_IDX 2 3803#define regDSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT 0x0d0d 3804#define regDSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2 3805#define regDSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM 0x0d0e 3806#define regDSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2 3807#define regDSCL0_OTG_H_BLANK 0x0d0f 3808#define regDSCL0_OTG_H_BLANK_BASE_IDX 2 3809#define regDSCL0_OTG_V_BLANK 0x0d10 3810#define regDSCL0_OTG_V_BLANK_BASE_IDX 2 3811#define regDSCL0_RECOUT_START 0x0d11 3812#define regDSCL0_RECOUT_START_BASE_IDX 2 3813#define regDSCL0_RECOUT_SIZE 0x0d12 3814#define regDSCL0_RECOUT_SIZE_BASE_IDX 2 3815#define regDSCL0_MPC_SIZE 0x0d13 3816#define regDSCL0_MPC_SIZE_BASE_IDX 2 3817#define regDSCL0_LB_DATA_FORMAT 0x0d14 3818#define regDSCL0_LB_DATA_FORMAT_BASE_IDX 2 3819#define regDSCL0_LB_MEMORY_CTRL 0x0d15 3820#define regDSCL0_LB_MEMORY_CTRL_BASE_IDX 2 3821#define regDSCL0_LB_V_COUNTER 0x0d16 3822#define regDSCL0_LB_V_COUNTER_BASE_IDX 2 3823#define regDSCL0_DSCL_MEM_PWR_CTRL 0x0d17 3824#define regDSCL0_DSCL_MEM_PWR_CTRL_BASE_IDX 2 3825#define regDSCL0_DSCL_MEM_PWR_STATUS 0x0d18 3826#define regDSCL0_DSCL_MEM_PWR_STATUS_BASE_IDX 2 3827#define regDSCL0_OBUF_CONTROL 0x0d19 3828#define regDSCL0_OBUF_CONTROL_BASE_IDX 2 3829#define regDSCL0_OBUF_MEM_PWR_CTRL 0x0d1a 3830#define regDSCL0_OBUF_MEM_PWR_CTRL_BASE_IDX 2 3831 3832 3833// addressBlock: dce_dc_dpp0_dispdec_cm_dispdec 3834// base address: 0x0 3835#define regCM0_CM_CONTROL 0x0d20 3836#define regCM0_CM_CONTROL_BASE_IDX 2 3837#define regCM0_CM_POST_CSC_CONTROL 0x0d21 3838#define regCM0_CM_POST_CSC_CONTROL_BASE_IDX 2 3839#define regCM0_CM_POST_CSC_C11_C12 0x0d22 3840#define regCM0_CM_POST_CSC_C11_C12_BASE_IDX 2 3841#define regCM0_CM_POST_CSC_C13_C14 0x0d23 3842#define regCM0_CM_POST_CSC_C13_C14_BASE_IDX 2 3843#define regCM0_CM_POST_CSC_C21_C22 0x0d24 3844#define regCM0_CM_POST_CSC_C21_C22_BASE_IDX 2 3845#define regCM0_CM_POST_CSC_C23_C24 0x0d25 3846#define regCM0_CM_POST_CSC_C23_C24_BASE_IDX 2 3847#define regCM0_CM_POST_CSC_C31_C32 0x0d26 3848#define regCM0_CM_POST_CSC_C31_C32_BASE_IDX 2 3849#define regCM0_CM_POST_CSC_C33_C34 0x0d27 3850#define regCM0_CM_POST_CSC_C33_C34_BASE_IDX 2 3851#define regCM0_CM_POST_CSC_B_C11_C12 0x0d28 3852#define regCM0_CM_POST_CSC_B_C11_C12_BASE_IDX 2 3853#define regCM0_CM_POST_CSC_B_C13_C14 0x0d29 3854#define regCM0_CM_POST_CSC_B_C13_C14_BASE_IDX 2 3855#define regCM0_CM_POST_CSC_B_C21_C22 0x0d2a 3856#define regCM0_CM_POST_CSC_B_C21_C22_BASE_IDX 2 3857#define regCM0_CM_POST_CSC_B_C23_C24 0x0d2b 3858#define regCM0_CM_POST_CSC_B_C23_C24_BASE_IDX 2 3859#define regCM0_CM_POST_CSC_B_C31_C32 0x0d2c 3860#define regCM0_CM_POST_CSC_B_C31_C32_BASE_IDX 2 3861#define regCM0_CM_POST_CSC_B_C33_C34 0x0d2d 3862#define regCM0_CM_POST_CSC_B_C33_C34_BASE_IDX 2 3863#define regCM0_CM_GAMUT_REMAP_CONTROL 0x0d2e 3864#define regCM0_CM_GAMUT_REMAP_CONTROL_BASE_IDX 2 3865#define regCM0_CM_GAMUT_REMAP_C11_C12 0x0d2f 3866#define regCM0_CM_GAMUT_REMAP_C11_C12_BASE_IDX 2 3867#define regCM0_CM_GAMUT_REMAP_C13_C14 0x0d30 3868#define regCM0_CM_GAMUT_REMAP_C13_C14_BASE_IDX 2 3869#define regCM0_CM_GAMUT_REMAP_C21_C22 0x0d31 3870#define regCM0_CM_GAMUT_REMAP_C21_C22_BASE_IDX 2 3871#define regCM0_CM_GAMUT_REMAP_C23_C24 0x0d32 3872#define regCM0_CM_GAMUT_REMAP_C23_C24_BASE_IDX 2 3873#define regCM0_CM_GAMUT_REMAP_C31_C32 0x0d33 3874#define regCM0_CM_GAMUT_REMAP_C31_C32_BASE_IDX 2 3875#define regCM0_CM_GAMUT_REMAP_C33_C34 0x0d34 3876#define regCM0_CM_GAMUT_REMAP_C33_C34_BASE_IDX 2 3877#define regCM0_CM_GAMUT_REMAP_B_C11_C12 0x0d35 3878#define regCM0_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX 2 3879#define regCM0_CM_GAMUT_REMAP_B_C13_C14 0x0d36 3880#define regCM0_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX 2 3881#define regCM0_CM_GAMUT_REMAP_B_C21_C22 0x0d37 3882#define regCM0_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX 2 3883#define regCM0_CM_GAMUT_REMAP_B_C23_C24 0x0d38 3884#define regCM0_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX 2 3885#define regCM0_CM_GAMUT_REMAP_B_C31_C32 0x0d39 3886#define regCM0_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX 2 3887#define regCM0_CM_GAMUT_REMAP_B_C33_C34 0x0d3a 3888#define regCM0_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX 2 3889#define regCM0_CM_BIAS_CR_R 0x0d3b 3890#define regCM0_CM_BIAS_CR_R_BASE_IDX 2 3891#define regCM0_CM_BIAS_Y_G_CB_B 0x0d3c 3892#define regCM0_CM_BIAS_Y_G_CB_B_BASE_IDX 2 3893#define regCM0_CM_GAMCOR_CONTROL 0x0d3d 3894#define regCM0_CM_GAMCOR_CONTROL_BASE_IDX 2 3895#define regCM0_CM_GAMCOR_LUT_INDEX 0x0d3e 3896#define regCM0_CM_GAMCOR_LUT_INDEX_BASE_IDX 2 3897#define regCM0_CM_GAMCOR_LUT_DATA 0x0d3f 3898#define regCM0_CM_GAMCOR_LUT_DATA_BASE_IDX 2 3899#define regCM0_CM_GAMCOR_LUT_CONTROL 0x0d40 3900#define regCM0_CM_GAMCOR_LUT_CONTROL_BASE_IDX 2 3901#define regCM0_CM_GAMCOR_RAMA_START_CNTL_B 0x0d41 3902#define regCM0_CM_GAMCOR_RAMA_START_CNTL_B_BASE_IDX 2 3903#define regCM0_CM_GAMCOR_RAMA_START_CNTL_G 0x0d42 3904#define regCM0_CM_GAMCOR_RAMA_START_CNTL_G_BASE_IDX 2 3905#define regCM0_CM_GAMCOR_RAMA_START_CNTL_R 0x0d43 3906#define regCM0_CM_GAMCOR_RAMA_START_CNTL_R_BASE_IDX 2 3907#define regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B 0x0d44 3908#define regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B_BASE_IDX 2 3909#define regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G 0x0d45 3910#define regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2 3911#define regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R 0x0d46 3912#define regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R_BASE_IDX 2 3913#define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_B 0x0d47 3914#define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_B_BASE_IDX 2 3915#define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_G 0x0d48 3916#define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_G_BASE_IDX 2 3917#define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_R 0x0d49 3918#define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_R_BASE_IDX 2 3919#define regCM0_CM_GAMCOR_RAMA_END_CNTL1_B 0x0d4a 3920#define regCM0_CM_GAMCOR_RAMA_END_CNTL1_B_BASE_IDX 2 3921#define regCM0_CM_GAMCOR_RAMA_END_CNTL2_B 0x0d4b 3922#define regCM0_CM_GAMCOR_RAMA_END_CNTL2_B_BASE_IDX 2 3923#define regCM0_CM_GAMCOR_RAMA_END_CNTL1_G 0x0d4c 3924#define regCM0_CM_GAMCOR_RAMA_END_CNTL1_G_BASE_IDX 2 3925#define regCM0_CM_GAMCOR_RAMA_END_CNTL2_G 0x0d4d 3926#define regCM0_CM_GAMCOR_RAMA_END_CNTL2_G_BASE_IDX 2 3927#define regCM0_CM_GAMCOR_RAMA_END_CNTL1_R 0x0d4e 3928#define regCM0_CM_GAMCOR_RAMA_END_CNTL1_R_BASE_IDX 2 3929#define regCM0_CM_GAMCOR_RAMA_END_CNTL2_R 0x0d4f 3930#define regCM0_CM_GAMCOR_RAMA_END_CNTL2_R_BASE_IDX 2 3931#define regCM0_CM_GAMCOR_RAMA_OFFSET_B 0x0d50 3932#define regCM0_CM_GAMCOR_RAMA_OFFSET_B_BASE_IDX 2 3933#define regCM0_CM_GAMCOR_RAMA_OFFSET_G 0x0d51 3934#define regCM0_CM_GAMCOR_RAMA_OFFSET_G_BASE_IDX 2 3935#define regCM0_CM_GAMCOR_RAMA_OFFSET_R 0x0d52 3936#define regCM0_CM_GAMCOR_RAMA_OFFSET_R_BASE_IDX 2 3937#define regCM0_CM_GAMCOR_RAMA_REGION_0_1 0x0d53 3938#define regCM0_CM_GAMCOR_RAMA_REGION_0_1_BASE_IDX 2 3939#define regCM0_CM_GAMCOR_RAMA_REGION_2_3 0x0d54 3940#define regCM0_CM_GAMCOR_RAMA_REGION_2_3_BASE_IDX 2 3941#define regCM0_CM_GAMCOR_RAMA_REGION_4_5 0x0d55 3942#define regCM0_CM_GAMCOR_RAMA_REGION_4_5_BASE_IDX 2 3943#define regCM0_CM_GAMCOR_RAMA_REGION_6_7 0x0d56 3944#define regCM0_CM_GAMCOR_RAMA_REGION_6_7_BASE_IDX 2 3945#define regCM0_CM_GAMCOR_RAMA_REGION_8_9 0x0d57 3946#define regCM0_CM_GAMCOR_RAMA_REGION_8_9_BASE_IDX 2 3947#define regCM0_CM_GAMCOR_RAMA_REGION_10_11 0x0d58 3948#define regCM0_CM_GAMCOR_RAMA_REGION_10_11_BASE_IDX 2 3949#define regCM0_CM_GAMCOR_RAMA_REGION_12_13 0x0d59 3950#define regCM0_CM_GAMCOR_RAMA_REGION_12_13_BASE_IDX 2 3951#define regCM0_CM_GAMCOR_RAMA_REGION_14_15 0x0d5a 3952#define regCM0_CM_GAMCOR_RAMA_REGION_14_15_BASE_IDX 2 3953#define regCM0_CM_GAMCOR_RAMA_REGION_16_17 0x0d5b 3954#define regCM0_CM_GAMCOR_RAMA_REGION_16_17_BASE_IDX 2 3955#define regCM0_CM_GAMCOR_RAMA_REGION_18_19 0x0d5c 3956#define regCM0_CM_GAMCOR_RAMA_REGION_18_19_BASE_IDX 2 3957#define regCM0_CM_GAMCOR_RAMA_REGION_20_21 0x0d5d 3958#define regCM0_CM_GAMCOR_RAMA_REGION_20_21_BASE_IDX 2 3959#define regCM0_CM_GAMCOR_RAMA_REGION_22_23 0x0d5e 3960#define regCM0_CM_GAMCOR_RAMA_REGION_22_23_BASE_IDX 2 3961#define regCM0_CM_GAMCOR_RAMA_REGION_24_25 0x0d5f 3962#define regCM0_CM_GAMCOR_RAMA_REGION_24_25_BASE_IDX 2 3963#define regCM0_CM_GAMCOR_RAMA_REGION_26_27 0x0d60 3964#define regCM0_CM_GAMCOR_RAMA_REGION_26_27_BASE_IDX 2 3965#define regCM0_CM_GAMCOR_RAMA_REGION_28_29 0x0d61 3966#define regCM0_CM_GAMCOR_RAMA_REGION_28_29_BASE_IDX 2 3967#define regCM0_CM_GAMCOR_RAMA_REGION_30_31 0x0d62 3968#define regCM0_CM_GAMCOR_RAMA_REGION_30_31_BASE_IDX 2 3969#define regCM0_CM_GAMCOR_RAMA_REGION_32_33 0x0d63 3970#define regCM0_CM_GAMCOR_RAMA_REGION_32_33_BASE_IDX 2 3971#define regCM0_CM_GAMCOR_RAMB_START_CNTL_B 0x0d64 3972#define regCM0_CM_GAMCOR_RAMB_START_CNTL_B_BASE_IDX 2 3973#define regCM0_CM_GAMCOR_RAMB_START_CNTL_G 0x0d65 3974#define regCM0_CM_GAMCOR_RAMB_START_CNTL_G_BASE_IDX 2 3975#define regCM0_CM_GAMCOR_RAMB_START_CNTL_R 0x0d66 3976#define regCM0_CM_GAMCOR_RAMB_START_CNTL_R_BASE_IDX 2 3977#define regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B 0x0d67 3978#define regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B_BASE_IDX 2 3979#define regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G 0x0d68 3980#define regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G_BASE_IDX 2 3981#define regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R 0x0d69 3982#define regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R_BASE_IDX 2 3983#define regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_B 0x0d6a 3984#define regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_B_BASE_IDX 2 3985#define regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_G 0x0d6b 3986#define regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_G_BASE_IDX 2 3987#define regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_R 0x0d6c 3988#define regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_R_BASE_IDX 2 3989#define regCM0_CM_GAMCOR_RAMB_END_CNTL1_B 0x0d6d 3990#define regCM0_CM_GAMCOR_RAMB_END_CNTL1_B_BASE_IDX 2 3991#define regCM0_CM_GAMCOR_RAMB_END_CNTL2_B 0x0d6e 3992#define regCM0_CM_GAMCOR_RAMB_END_CNTL2_B_BASE_IDX 2 3993#define regCM0_CM_GAMCOR_RAMB_END_CNTL1_G 0x0d6f 3994#define regCM0_CM_GAMCOR_RAMB_END_CNTL1_G_BASE_IDX 2 3995#define regCM0_CM_GAMCOR_RAMB_END_CNTL2_G 0x0d70 3996#define regCM0_CM_GAMCOR_RAMB_END_CNTL2_G_BASE_IDX 2 3997#define regCM0_CM_GAMCOR_RAMB_END_CNTL1_R 0x0d71 3998#define regCM0_CM_GAMCOR_RAMB_END_CNTL1_R_BASE_IDX 2 3999#define regCM0_CM_GAMCOR_RAMB_END_CNTL2_R 0x0d72 4000#define regCM0_CM_GAMCOR_RAMB_END_CNTL2_R_BASE_IDX 2 4001#define regCM0_CM_GAMCOR_RAMB_OFFSET_B 0x0d73 4002#define regCM0_CM_GAMCOR_RAMB_OFFSET_B_BASE_IDX 2 4003#define regCM0_CM_GAMCOR_RAMB_OFFSET_G 0x0d74 4004#define regCM0_CM_GAMCOR_RAMB_OFFSET_G_BASE_IDX 2 4005#define regCM0_CM_GAMCOR_RAMB_OFFSET_R 0x0d75 4006#define regCM0_CM_GAMCOR_RAMB_OFFSET_R_BASE_IDX 2 4007#define regCM0_CM_GAMCOR_RAMB_REGION_0_1 0x0d76 4008#define regCM0_CM_GAMCOR_RAMB_REGION_0_1_BASE_IDX 2 4009#define regCM0_CM_GAMCOR_RAMB_REGION_2_3 0x0d77 4010#define regCM0_CM_GAMCOR_RAMB_REGION_2_3_BASE_IDX 2 4011#define regCM0_CM_GAMCOR_RAMB_REGION_4_5 0x0d78 4012#define regCM0_CM_GAMCOR_RAMB_REGION_4_5_BASE_IDX 2 4013#define regCM0_CM_GAMCOR_RAMB_REGION_6_7 0x0d79 4014#define regCM0_CM_GAMCOR_RAMB_REGION_6_7_BASE_IDX 2 4015#define regCM0_CM_GAMCOR_RAMB_REGION_8_9 0x0d7a 4016#define regCM0_CM_GAMCOR_RAMB_REGION_8_9_BASE_IDX 2 4017#define regCM0_CM_GAMCOR_RAMB_REGION_10_11 0x0d7b 4018#define regCM0_CM_GAMCOR_RAMB_REGION_10_11_BASE_IDX 2 4019#define regCM0_CM_GAMCOR_RAMB_REGION_12_13 0x0d7c 4020#define regCM0_CM_GAMCOR_RAMB_REGION_12_13_BASE_IDX 2 4021#define regCM0_CM_GAMCOR_RAMB_REGION_14_15 0x0d7d 4022#define regCM0_CM_GAMCOR_RAMB_REGION_14_15_BASE_IDX 2 4023#define regCM0_CM_GAMCOR_RAMB_REGION_16_17 0x0d7e 4024#define regCM0_CM_GAMCOR_RAMB_REGION_16_17_BASE_IDX 2 4025#define regCM0_CM_GAMCOR_RAMB_REGION_18_19 0x0d7f 4026#define regCM0_CM_GAMCOR_RAMB_REGION_18_19_BASE_IDX 2 4027#define regCM0_CM_GAMCOR_RAMB_REGION_20_21 0x0d80 4028#define regCM0_CM_GAMCOR_RAMB_REGION_20_21_BASE_IDX 2 4029#define regCM0_CM_GAMCOR_RAMB_REGION_22_23 0x0d81 4030#define regCM0_CM_GAMCOR_RAMB_REGION_22_23_BASE_IDX 2 4031#define regCM0_CM_GAMCOR_RAMB_REGION_24_25 0x0d82 4032#define regCM0_CM_GAMCOR_RAMB_REGION_24_25_BASE_IDX 2 4033#define regCM0_CM_GAMCOR_RAMB_REGION_26_27 0x0d83 4034#define regCM0_CM_GAMCOR_RAMB_REGION_26_27_BASE_IDX 2 4035#define regCM0_CM_GAMCOR_RAMB_REGION_28_29 0x0d84 4036#define regCM0_CM_GAMCOR_RAMB_REGION_28_29_BASE_IDX 2 4037#define regCM0_CM_GAMCOR_RAMB_REGION_30_31 0x0d85 4038#define regCM0_CM_GAMCOR_RAMB_REGION_30_31_BASE_IDX 2 4039#define regCM0_CM_GAMCOR_RAMB_REGION_32_33 0x0d86 4040#define regCM0_CM_GAMCOR_RAMB_REGION_32_33_BASE_IDX 2 4041#define regCM0_CM_BLNDGAM_CONTROL 0x0d87 4042#define regCM0_CM_BLNDGAM_CONTROL_BASE_IDX 2 4043#define regCM0_CM_BLNDGAM_LUT_INDEX 0x0d88 4044#define regCM0_CM_BLNDGAM_LUT_INDEX_BASE_IDX 2 4045#define regCM0_CM_BLNDGAM_LUT_DATA 0x0d89 4046#define regCM0_CM_BLNDGAM_LUT_DATA_BASE_IDX 2 4047#define regCM0_CM_BLNDGAM_LUT_CONTROL 0x0d8a 4048#define regCM0_CM_BLNDGAM_LUT_CONTROL_BASE_IDX 2 4049#define regCM0_CM_BLNDGAM_RAMA_START_CNTL_B 0x0d8b 4050#define regCM0_CM_BLNDGAM_RAMA_START_CNTL_B_BASE_IDX 2 4051#define regCM0_CM_BLNDGAM_RAMA_START_CNTL_G 0x0d8c 4052#define regCM0_CM_BLNDGAM_RAMA_START_CNTL_G_BASE_IDX 2 4053#define regCM0_CM_BLNDGAM_RAMA_START_CNTL_R 0x0d8d 4054#define regCM0_CM_BLNDGAM_RAMA_START_CNTL_R_BASE_IDX 2 4055#define regCM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B 0x0d8e 4056#define regCM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX 2 4057#define regCM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G 0x0d8f 4058#define regCM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2 4059#define regCM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R 0x0d90 4060#define regCM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX 2 4061#define regCM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_B 0x0d91 4062#define regCM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_B_BASE_IDX 2 4063#define regCM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_G 0x0d92 4064#define regCM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_G_BASE_IDX 2 4065#define regCM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_R 0x0d93 4066#define regCM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_R_BASE_IDX 2 4067#define regCM0_CM_BLNDGAM_RAMA_END_CNTL1_B 0x0d94 4068#define regCM0_CM_BLNDGAM_RAMA_END_CNTL1_B_BASE_IDX 2 4069#define regCM0_CM_BLNDGAM_RAMA_END_CNTL2_B 0x0d95 4070#define regCM0_CM_BLNDGAM_RAMA_END_CNTL2_B_BASE_IDX 2 4071#define regCM0_CM_BLNDGAM_RAMA_END_CNTL1_G 0x0d96 4072#define regCM0_CM_BLNDGAM_RAMA_END_CNTL1_G_BASE_IDX 2 4073#define regCM0_CM_BLNDGAM_RAMA_END_CNTL2_G 0x0d97 4074#define regCM0_CM_BLNDGAM_RAMA_END_CNTL2_G_BASE_IDX 2 4075#define regCM0_CM_BLNDGAM_RAMA_END_CNTL1_R 0x0d98 4076#define regCM0_CM_BLNDGAM_RAMA_END_CNTL1_R_BASE_IDX 2 4077#define regCM0_CM_BLNDGAM_RAMA_END_CNTL2_R 0x0d99 4078#define regCM0_CM_BLNDGAM_RAMA_END_CNTL2_R_BASE_IDX 2 4079#define regCM0_CM_BLNDGAM_RAMA_OFFSET_B 0x0d9a 4080#define regCM0_CM_BLNDGAM_RAMA_OFFSET_B_BASE_IDX 2 4081#define regCM0_CM_BLNDGAM_RAMA_OFFSET_G 0x0d9b 4082#define regCM0_CM_BLNDGAM_RAMA_OFFSET_G_BASE_IDX 2 4083#define regCM0_CM_BLNDGAM_RAMA_OFFSET_R 0x0d9c 4084#define regCM0_CM_BLNDGAM_RAMA_OFFSET_R_BASE_IDX 2 4085#define regCM0_CM_BLNDGAM_RAMA_REGION_0_1 0x0d9d 4086#define regCM0_CM_BLNDGAM_RAMA_REGION_0_1_BASE_IDX 2 4087#define regCM0_CM_BLNDGAM_RAMA_REGION_2_3 0x0d9e 4088#define regCM0_CM_BLNDGAM_RAMA_REGION_2_3_BASE_IDX 2 4089#define regCM0_CM_BLNDGAM_RAMA_REGION_4_5 0x0d9f 4090#define regCM0_CM_BLNDGAM_RAMA_REGION_4_5_BASE_IDX 2 4091#define regCM0_CM_BLNDGAM_RAMA_REGION_6_7 0x0da0 4092#define regCM0_CM_BLNDGAM_RAMA_REGION_6_7_BASE_IDX 2 4093#define regCM0_CM_BLNDGAM_RAMA_REGION_8_9 0x0da1 4094#define regCM0_CM_BLNDGAM_RAMA_REGION_8_9_BASE_IDX 2 4095#define regCM0_CM_BLNDGAM_RAMA_REGION_10_11 0x0da2 4096#define regCM0_CM_BLNDGAM_RAMA_REGION_10_11_BASE_IDX 2 4097#define regCM0_CM_BLNDGAM_RAMA_REGION_12_13 0x0da3 4098#define regCM0_CM_BLNDGAM_RAMA_REGION_12_13_BASE_IDX 2 4099#define regCM0_CM_BLNDGAM_RAMA_REGION_14_15 0x0da4 4100#define regCM0_CM_BLNDGAM_RAMA_REGION_14_15_BASE_IDX 2 4101#define regCM0_CM_BLNDGAM_RAMA_REGION_16_17 0x0da5 4102#define regCM0_CM_BLNDGAM_RAMA_REGION_16_17_BASE_IDX 2 4103#define regCM0_CM_BLNDGAM_RAMA_REGION_18_19 0x0da6 4104#define regCM0_CM_BLNDGAM_RAMA_REGION_18_19_BASE_IDX 2 4105#define regCM0_CM_BLNDGAM_RAMA_REGION_20_21 0x0da7 4106#define regCM0_CM_BLNDGAM_RAMA_REGION_20_21_BASE_IDX 2 4107#define regCM0_CM_BLNDGAM_RAMA_REGION_22_23 0x0da8 4108#define regCM0_CM_BLNDGAM_RAMA_REGION_22_23_BASE_IDX 2 4109#define regCM0_CM_BLNDGAM_RAMA_REGION_24_25 0x0da9 4110#define regCM0_CM_BLNDGAM_RAMA_REGION_24_25_BASE_IDX 2 4111#define regCM0_CM_BLNDGAM_RAMA_REGION_26_27 0x0daa 4112#define regCM0_CM_BLNDGAM_RAMA_REGION_26_27_BASE_IDX 2 4113#define regCM0_CM_BLNDGAM_RAMA_REGION_28_29 0x0dab 4114#define regCM0_CM_BLNDGAM_RAMA_REGION_28_29_BASE_IDX 2 4115#define regCM0_CM_BLNDGAM_RAMA_REGION_30_31 0x0dac 4116#define regCM0_CM_BLNDGAM_RAMA_REGION_30_31_BASE_IDX 2 4117#define regCM0_CM_BLNDGAM_RAMA_REGION_32_33 0x0dad 4118#define regCM0_CM_BLNDGAM_RAMA_REGION_32_33_BASE_IDX 2 4119#define regCM0_CM_BLNDGAM_RAMB_START_CNTL_B 0x0dae 4120#define regCM0_CM_BLNDGAM_RAMB_START_CNTL_B_BASE_IDX 2 4121#define regCM0_CM_BLNDGAM_RAMB_START_CNTL_G 0x0daf 4122#define regCM0_CM_BLNDGAM_RAMB_START_CNTL_G_BASE_IDX 2 4123#define regCM0_CM_BLNDGAM_RAMB_START_CNTL_R 0x0db0 4124#define regCM0_CM_BLNDGAM_RAMB_START_CNTL_R_BASE_IDX 2 4125#define regCM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B 0x0db1 4126#define regCM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX 2 4127#define regCM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G 0x0db2 4128#define regCM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX 2 4129#define regCM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R 0x0db3 4130#define regCM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX 2 4131#define regCM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_B 0x0db4 4132#define regCM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_B_BASE_IDX 2 4133#define regCM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_G 0x0db5 4134#define regCM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_G_BASE_IDX 2 4135#define regCM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_R 0x0db6 4136#define regCM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_R_BASE_IDX 2 4137#define regCM0_CM_BLNDGAM_RAMB_END_CNTL1_B 0x0db7 4138#define regCM0_CM_BLNDGAM_RAMB_END_CNTL1_B_BASE_IDX 2 4139#define regCM0_CM_BLNDGAM_RAMB_END_CNTL2_B 0x0db8 4140#define regCM0_CM_BLNDGAM_RAMB_END_CNTL2_B_BASE_IDX 2 4141#define regCM0_CM_BLNDGAM_RAMB_END_CNTL1_G 0x0db9 4142#define regCM0_CM_BLNDGAM_RAMB_END_CNTL1_G_BASE_IDX 2 4143#define regCM0_CM_BLNDGAM_RAMB_END_CNTL2_G 0x0dba 4144#define regCM0_CM_BLNDGAM_RAMB_END_CNTL2_G_BASE_IDX 2 4145#define regCM0_CM_BLNDGAM_RAMB_END_CNTL1_R 0x0dbb 4146#define regCM0_CM_BLNDGAM_RAMB_END_CNTL1_R_BASE_IDX 2 4147#define regCM0_CM_BLNDGAM_RAMB_END_CNTL2_R 0x0dbc 4148#define regCM0_CM_BLNDGAM_RAMB_END_CNTL2_R_BASE_IDX 2 4149#define regCM0_CM_BLNDGAM_RAMB_OFFSET_B 0x0dbd 4150#define regCM0_CM_BLNDGAM_RAMB_OFFSET_B_BASE_IDX 2 4151#define regCM0_CM_BLNDGAM_RAMB_OFFSET_G 0x0dbe 4152#define regCM0_CM_BLNDGAM_RAMB_OFFSET_G_BASE_IDX 2 4153#define regCM0_CM_BLNDGAM_RAMB_OFFSET_R 0x0dbf 4154#define regCM0_CM_BLNDGAM_RAMB_OFFSET_R_BASE_IDX 2 4155#define regCM0_CM_BLNDGAM_RAMB_REGION_0_1 0x0dc0 4156#define regCM0_CM_BLNDGAM_RAMB_REGION_0_1_BASE_IDX 2 4157#define regCM0_CM_BLNDGAM_RAMB_REGION_2_3 0x0dc1 4158#define regCM0_CM_BLNDGAM_RAMB_REGION_2_3_BASE_IDX 2 4159#define regCM0_CM_BLNDGAM_RAMB_REGION_4_5 0x0dc2 4160#define regCM0_CM_BLNDGAM_RAMB_REGION_4_5_BASE_IDX 2 4161#define regCM0_CM_BLNDGAM_RAMB_REGION_6_7 0x0dc3 4162#define regCM0_CM_BLNDGAM_RAMB_REGION_6_7_BASE_IDX 2 4163#define regCM0_CM_BLNDGAM_RAMB_REGION_8_9 0x0dc4 4164#define regCM0_CM_BLNDGAM_RAMB_REGION_8_9_BASE_IDX 2 4165#define regCM0_CM_BLNDGAM_RAMB_REGION_10_11 0x0dc5 4166#define regCM0_CM_BLNDGAM_RAMB_REGION_10_11_BASE_IDX 2 4167#define regCM0_CM_BLNDGAM_RAMB_REGION_12_13 0x0dc6 4168#define regCM0_CM_BLNDGAM_RAMB_REGION_12_13_BASE_IDX 2 4169#define regCM0_CM_BLNDGAM_RAMB_REGION_14_15 0x0dc7 4170#define regCM0_CM_BLNDGAM_RAMB_REGION_14_15_BASE_IDX 2 4171#define regCM0_CM_BLNDGAM_RAMB_REGION_16_17 0x0dc8 4172#define regCM0_CM_BLNDGAM_RAMB_REGION_16_17_BASE_IDX 2 4173#define regCM0_CM_BLNDGAM_RAMB_REGION_18_19 0x0dc9 4174#define regCM0_CM_BLNDGAM_RAMB_REGION_18_19_BASE_IDX 2 4175#define regCM0_CM_BLNDGAM_RAMB_REGION_20_21 0x0dca 4176#define regCM0_CM_BLNDGAM_RAMB_REGION_20_21_BASE_IDX 2 4177#define regCM0_CM_BLNDGAM_RAMB_REGION_22_23 0x0dcb 4178#define regCM0_CM_BLNDGAM_RAMB_REGION_22_23_BASE_IDX 2 4179#define regCM0_CM_BLNDGAM_RAMB_REGION_24_25 0x0dcc 4180#define regCM0_CM_BLNDGAM_RAMB_REGION_24_25_BASE_IDX 2 4181#define regCM0_CM_BLNDGAM_RAMB_REGION_26_27 0x0dcd 4182#define regCM0_CM_BLNDGAM_RAMB_REGION_26_27_BASE_IDX 2 4183#define regCM0_CM_BLNDGAM_RAMB_REGION_28_29 0x0dce 4184#define regCM0_CM_BLNDGAM_RAMB_REGION_28_29_BASE_IDX 2 4185#define regCM0_CM_BLNDGAM_RAMB_REGION_30_31 0x0dcf 4186#define regCM0_CM_BLNDGAM_RAMB_REGION_30_31_BASE_IDX 2 4187#define regCM0_CM_BLNDGAM_RAMB_REGION_32_33 0x0dd0 4188#define regCM0_CM_BLNDGAM_RAMB_REGION_32_33_BASE_IDX 2 4189#define regCM0_CM_HDR_MULT_COEF 0x0dd1 4190#define regCM0_CM_HDR_MULT_COEF_BASE_IDX 2 4191#define regCM0_CM_MEM_PWR_CTRL 0x0dd2 4192#define regCM0_CM_MEM_PWR_CTRL_BASE_IDX 2 4193#define regCM0_CM_MEM_PWR_STATUS 0x0dd3 4194#define regCM0_CM_MEM_PWR_STATUS_BASE_IDX 2 4195#define regCM0_CM_DEALPHA 0x0dd5 4196#define regCM0_CM_DEALPHA_BASE_IDX 2 4197#define regCM0_CM_COEF_FORMAT 0x0dd6 4198#define regCM0_CM_COEF_FORMAT_BASE_IDX 2 4199#define regCM0_CM_SHAPER_CONTROL 0x0dd7 4200#define regCM0_CM_SHAPER_CONTROL_BASE_IDX 2 4201#define regCM0_CM_SHAPER_OFFSET_R 0x0dd8 4202#define regCM0_CM_SHAPER_OFFSET_R_BASE_IDX 2 4203#define regCM0_CM_SHAPER_OFFSET_G 0x0dd9 4204#define regCM0_CM_SHAPER_OFFSET_G_BASE_IDX 2 4205#define regCM0_CM_SHAPER_OFFSET_B 0x0dda 4206#define regCM0_CM_SHAPER_OFFSET_B_BASE_IDX 2 4207#define regCM0_CM_SHAPER_SCALE_R 0x0ddb 4208#define regCM0_CM_SHAPER_SCALE_R_BASE_IDX 2 4209#define regCM0_CM_SHAPER_SCALE_G_B 0x0ddc 4210#define regCM0_CM_SHAPER_SCALE_G_B_BASE_IDX 2 4211#define regCM0_CM_SHAPER_LUT_INDEX 0x0ddd 4212#define regCM0_CM_SHAPER_LUT_INDEX_BASE_IDX 2 4213#define regCM0_CM_SHAPER_LUT_DATA 0x0dde 4214#define regCM0_CM_SHAPER_LUT_DATA_BASE_IDX 2 4215#define regCM0_CM_SHAPER_LUT_WRITE_EN_MASK 0x0ddf 4216#define regCM0_CM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX 2 4217#define regCM0_CM_SHAPER_RAMA_START_CNTL_B 0x0de0 4218#define regCM0_CM_SHAPER_RAMA_START_CNTL_B_BASE_IDX 2 4219#define regCM0_CM_SHAPER_RAMA_START_CNTL_G 0x0de1 4220#define regCM0_CM_SHAPER_RAMA_START_CNTL_G_BASE_IDX 2 4221#define regCM0_CM_SHAPER_RAMA_START_CNTL_R 0x0de2 4222#define regCM0_CM_SHAPER_RAMA_START_CNTL_R_BASE_IDX 2 4223#define regCM0_CM_SHAPER_RAMA_END_CNTL_B 0x0de3 4224#define regCM0_CM_SHAPER_RAMA_END_CNTL_B_BASE_IDX 2 4225#define regCM0_CM_SHAPER_RAMA_END_CNTL_G 0x0de4 4226#define regCM0_CM_SHAPER_RAMA_END_CNTL_G_BASE_IDX 2 4227#define regCM0_CM_SHAPER_RAMA_END_CNTL_R 0x0de5 4228#define regCM0_CM_SHAPER_RAMA_END_CNTL_R_BASE_IDX 2 4229#define regCM0_CM_SHAPER_RAMA_REGION_0_1 0x0de6 4230#define regCM0_CM_SHAPER_RAMA_REGION_0_1_BASE_IDX 2 4231#define regCM0_CM_SHAPER_RAMA_REGION_2_3 0x0de7 4232#define regCM0_CM_SHAPER_RAMA_REGION_2_3_BASE_IDX 2 4233#define regCM0_CM_SHAPER_RAMA_REGION_4_5 0x0de8 4234#define regCM0_CM_SHAPER_RAMA_REGION_4_5_BASE_IDX 2 4235#define regCM0_CM_SHAPER_RAMA_REGION_6_7 0x0de9 4236#define regCM0_CM_SHAPER_RAMA_REGION_6_7_BASE_IDX 2 4237#define regCM0_CM_SHAPER_RAMA_REGION_8_9 0x0dea 4238#define regCM0_CM_SHAPER_RAMA_REGION_8_9_BASE_IDX 2 4239#define regCM0_CM_SHAPER_RAMA_REGION_10_11 0x0deb 4240#define regCM0_CM_SHAPER_RAMA_REGION_10_11_BASE_IDX 2 4241#define regCM0_CM_SHAPER_RAMA_REGION_12_13 0x0dec 4242#define regCM0_CM_SHAPER_RAMA_REGION_12_13_BASE_IDX 2 4243#define regCM0_CM_SHAPER_RAMA_REGION_14_15 0x0ded 4244#define regCM0_CM_SHAPER_RAMA_REGION_14_15_BASE_IDX 2 4245#define regCM0_CM_SHAPER_RAMA_REGION_16_17 0x0dee 4246#define regCM0_CM_SHAPER_RAMA_REGION_16_17_BASE_IDX 2 4247#define regCM0_CM_SHAPER_RAMA_REGION_18_19 0x0def 4248#define regCM0_CM_SHAPER_RAMA_REGION_18_19_BASE_IDX 2 4249#define regCM0_CM_SHAPER_RAMA_REGION_20_21 0x0df0 4250#define regCM0_CM_SHAPER_RAMA_REGION_20_21_BASE_IDX 2 4251#define regCM0_CM_SHAPER_RAMA_REGION_22_23 0x0df1 4252#define regCM0_CM_SHAPER_RAMA_REGION_22_23_BASE_IDX 2 4253#define regCM0_CM_SHAPER_RAMA_REGION_24_25 0x0df2 4254#define regCM0_CM_SHAPER_RAMA_REGION_24_25_BASE_IDX 2 4255#define regCM0_CM_SHAPER_RAMA_REGION_26_27 0x0df3 4256#define regCM0_CM_SHAPER_RAMA_REGION_26_27_BASE_IDX 2 4257#define regCM0_CM_SHAPER_RAMA_REGION_28_29 0x0df4 4258#define regCM0_CM_SHAPER_RAMA_REGION_28_29_BASE_IDX 2 4259#define regCM0_CM_SHAPER_RAMA_REGION_30_31 0x0df5 4260#define regCM0_CM_SHAPER_RAMA_REGION_30_31_BASE_IDX 2 4261#define regCM0_CM_SHAPER_RAMA_REGION_32_33 0x0df6 4262#define regCM0_CM_SHAPER_RAMA_REGION_32_33_BASE_IDX 2 4263#define regCM0_CM_SHAPER_RAMB_START_CNTL_B 0x0df7 4264#define regCM0_CM_SHAPER_RAMB_START_CNTL_B_BASE_IDX 2 4265#define regCM0_CM_SHAPER_RAMB_START_CNTL_G 0x0df8 4266#define regCM0_CM_SHAPER_RAMB_START_CNTL_G_BASE_IDX 2 4267#define regCM0_CM_SHAPER_RAMB_START_CNTL_R 0x0df9 4268#define regCM0_CM_SHAPER_RAMB_START_CNTL_R_BASE_IDX 2 4269#define regCM0_CM_SHAPER_RAMB_END_CNTL_B 0x0dfa 4270#define regCM0_CM_SHAPER_RAMB_END_CNTL_B_BASE_IDX 2 4271#define regCM0_CM_SHAPER_RAMB_END_CNTL_G 0x0dfb 4272#define regCM0_CM_SHAPER_RAMB_END_CNTL_G_BASE_IDX 2 4273#define regCM0_CM_SHAPER_RAMB_END_CNTL_R 0x0dfc 4274#define regCM0_CM_SHAPER_RAMB_END_CNTL_R_BASE_IDX 2 4275#define regCM0_CM_SHAPER_RAMB_REGION_0_1 0x0dfd 4276#define regCM0_CM_SHAPER_RAMB_REGION_0_1_BASE_IDX 2 4277#define regCM0_CM_SHAPER_RAMB_REGION_2_3 0x0dfe 4278#define regCM0_CM_SHAPER_RAMB_REGION_2_3_BASE_IDX 2 4279#define regCM0_CM_SHAPER_RAMB_REGION_4_5 0x0dff 4280#define regCM0_CM_SHAPER_RAMB_REGION_4_5_BASE_IDX 2 4281#define regCM0_CM_SHAPER_RAMB_REGION_6_7 0x0e00 4282#define regCM0_CM_SHAPER_RAMB_REGION_6_7_BASE_IDX 2 4283#define regCM0_CM_SHAPER_RAMB_REGION_8_9 0x0e01 4284#define regCM0_CM_SHAPER_RAMB_REGION_8_9_BASE_IDX 2 4285#define regCM0_CM_SHAPER_RAMB_REGION_10_11 0x0e02 4286#define regCM0_CM_SHAPER_RAMB_REGION_10_11_BASE_IDX 2 4287#define regCM0_CM_SHAPER_RAMB_REGION_12_13 0x0e03 4288#define regCM0_CM_SHAPER_RAMB_REGION_12_13_BASE_IDX 2 4289#define regCM0_CM_SHAPER_RAMB_REGION_14_15 0x0e04 4290#define regCM0_CM_SHAPER_RAMB_REGION_14_15_BASE_IDX 2 4291#define regCM0_CM_SHAPER_RAMB_REGION_16_17 0x0e05 4292#define regCM0_CM_SHAPER_RAMB_REGION_16_17_BASE_IDX 2 4293#define regCM0_CM_SHAPER_RAMB_REGION_18_19 0x0e06 4294#define regCM0_CM_SHAPER_RAMB_REGION_18_19_BASE_IDX 2 4295#define regCM0_CM_SHAPER_RAMB_REGION_20_21 0x0e07 4296#define regCM0_CM_SHAPER_RAMB_REGION_20_21_BASE_IDX 2 4297#define regCM0_CM_SHAPER_RAMB_REGION_22_23 0x0e08 4298#define regCM0_CM_SHAPER_RAMB_REGION_22_23_BASE_IDX 2 4299#define regCM0_CM_SHAPER_RAMB_REGION_24_25 0x0e09 4300#define regCM0_CM_SHAPER_RAMB_REGION_24_25_BASE_IDX 2 4301#define regCM0_CM_SHAPER_RAMB_REGION_26_27 0x0e0a 4302#define regCM0_CM_SHAPER_RAMB_REGION_26_27_BASE_IDX 2 4303#define regCM0_CM_SHAPER_RAMB_REGION_28_29 0x0e0b 4304#define regCM0_CM_SHAPER_RAMB_REGION_28_29_BASE_IDX 2 4305#define regCM0_CM_SHAPER_RAMB_REGION_30_31 0x0e0c 4306#define regCM0_CM_SHAPER_RAMB_REGION_30_31_BASE_IDX 2 4307#define regCM0_CM_SHAPER_RAMB_REGION_32_33 0x0e0d 4308#define regCM0_CM_SHAPER_RAMB_REGION_32_33_BASE_IDX 2 4309#define regCM0_CM_MEM_PWR_CTRL2 0x0e0e 4310#define regCM0_CM_MEM_PWR_CTRL2_BASE_IDX 2 4311#define regCM0_CM_MEM_PWR_STATUS2 0x0e0f 4312#define regCM0_CM_MEM_PWR_STATUS2_BASE_IDX 2 4313#define regCM0_CM_3DLUT_MODE 0x0e10 4314#define regCM0_CM_3DLUT_MODE_BASE_IDX 2 4315#define regCM0_CM_3DLUT_INDEX 0x0e11 4316#define regCM0_CM_3DLUT_INDEX_BASE_IDX 2 4317#define regCM0_CM_3DLUT_DATA 0x0e12 4318#define regCM0_CM_3DLUT_DATA_BASE_IDX 2 4319#define regCM0_CM_3DLUT_DATA_30BIT 0x0e13 4320#define regCM0_CM_3DLUT_DATA_30BIT_BASE_IDX 2 4321#define regCM0_CM_3DLUT_READ_WRITE_CONTROL 0x0e14 4322#define regCM0_CM_3DLUT_READ_WRITE_CONTROL_BASE_IDX 2 4323#define regCM0_CM_3DLUT_OUT_NORM_FACTOR 0x0e15 4324#define regCM0_CM_3DLUT_OUT_NORM_FACTOR_BASE_IDX 2 4325#define regCM0_CM_3DLUT_OUT_OFFSET_R 0x0e16 4326#define regCM0_CM_3DLUT_OUT_OFFSET_R_BASE_IDX 2 4327#define regCM0_CM_3DLUT_OUT_OFFSET_G 0x0e17 4328#define regCM0_CM_3DLUT_OUT_OFFSET_G_BASE_IDX 2 4329#define regCM0_CM_3DLUT_OUT_OFFSET_B 0x0e18 4330#define regCM0_CM_3DLUT_OUT_OFFSET_B_BASE_IDX 2 4331#define regCM0_CM_TEST_DEBUG_INDEX 0x0e19 4332#define regCM0_CM_TEST_DEBUG_INDEX_BASE_IDX 2 4333#define regCM0_CM_TEST_DEBUG_DATA 0x0e1a 4334#define regCM0_CM_TEST_DEBUG_DATA_BASE_IDX 2 4335 4336 4337// addressBlock: dce_dc_dpp0_dispdec_dpp_top_dispdec 4338// base address: 0x0 4339#define regDPP_TOP0_DPP_CONTROL 0x0cc5 4340#define regDPP_TOP0_DPP_CONTROL_BASE_IDX 2 4341#define regDPP_TOP0_DPP_SOFT_RESET 0x0cc6 4342#define regDPP_TOP0_DPP_SOFT_RESET_BASE_IDX 2 4343#define regDPP_TOP0_DPP_CRC_VAL_R_G 0x0cc7 4344#define regDPP_TOP0_DPP_CRC_VAL_R_G_BASE_IDX 2 4345#define regDPP_TOP0_DPP_CRC_VAL_B_A 0x0cc8 4346#define regDPP_TOP0_DPP_CRC_VAL_B_A_BASE_IDX 2 4347#define regDPP_TOP0_DPP_CRC_CTRL 0x0cc9 4348#define regDPP_TOP0_DPP_CRC_CTRL_BASE_IDX 2 4349#define regDPP_TOP0_HOST_READ_CONTROL 0x0cca 4350#define regDPP_TOP0_HOST_READ_CONTROL_BASE_IDX 2 4351 4352 4353// addressBlock: dce_dc_dpp0_dispdec_dpp_dcperfmon_dc_perfmon_dispdec 4354// base address: 0x3890 4355#define regDC_PERFMON11_PERFCOUNTER_CNTL 0x0e24 4356#define regDC_PERFMON11_PERFCOUNTER_CNTL_BASE_IDX 2 4357#define regDC_PERFMON11_PERFCOUNTER_CNTL2 0x0e25 4358#define regDC_PERFMON11_PERFCOUNTER_CNTL2_BASE_IDX 2 4359#define regDC_PERFMON11_PERFCOUNTER_STATE 0x0e26 4360#define regDC_PERFMON11_PERFCOUNTER_STATE_BASE_IDX 2 4361#define regDC_PERFMON11_PERFMON_CNTL 0x0e27 4362#define regDC_PERFMON11_PERFMON_CNTL_BASE_IDX 2 4363#define regDC_PERFMON11_PERFMON_CNTL2 0x0e28 4364#define regDC_PERFMON11_PERFMON_CNTL2_BASE_IDX 2 4365#define regDC_PERFMON11_PERFMON_CVALUE_INT_MISC 0x0e29 4366#define regDC_PERFMON11_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 4367#define regDC_PERFMON11_PERFMON_CVALUE_LOW 0x0e2a 4368#define regDC_PERFMON11_PERFMON_CVALUE_LOW_BASE_IDX 2 4369#define regDC_PERFMON11_PERFMON_HI 0x0e2b 4370#define regDC_PERFMON11_PERFMON_HI_BASE_IDX 2 4371#define regDC_PERFMON11_PERFMON_LOW 0x0e2c 4372#define regDC_PERFMON11_PERFMON_LOW_BASE_IDX 2 4373 4374 4375// addressBlock: dce_dc_dpp1_dispdec_cnvc_cfg_dispdec 4376// base address: 0x5ac 4377#define regCNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT 0x0e3a 4378#define regCNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX 2 4379#define regCNVC_CFG1_FORMAT_CONTROL 0x0e3b 4380#define regCNVC_CFG1_FORMAT_CONTROL_BASE_IDX 2 4381#define regCNVC_CFG1_FCNV_FP_BIAS_R 0x0e3c 4382#define regCNVC_CFG1_FCNV_FP_BIAS_R_BASE_IDX 2 4383#define regCNVC_CFG1_FCNV_FP_BIAS_G 0x0e3d 4384#define regCNVC_CFG1_FCNV_FP_BIAS_G_BASE_IDX 2 4385#define regCNVC_CFG1_FCNV_FP_BIAS_B 0x0e3e 4386#define regCNVC_CFG1_FCNV_FP_BIAS_B_BASE_IDX 2 4387#define regCNVC_CFG1_FCNV_FP_SCALE_R 0x0e3f 4388#define regCNVC_CFG1_FCNV_FP_SCALE_R_BASE_IDX 2 4389#define regCNVC_CFG1_FCNV_FP_SCALE_G 0x0e40 4390#define regCNVC_CFG1_FCNV_FP_SCALE_G_BASE_IDX 2 4391#define regCNVC_CFG1_FCNV_FP_SCALE_B 0x0e41 4392#define regCNVC_CFG1_FCNV_FP_SCALE_B_BASE_IDX 2 4393#define regCNVC_CFG1_COLOR_KEYER_CONTROL 0x0e42 4394#define regCNVC_CFG1_COLOR_KEYER_CONTROL_BASE_IDX 2 4395#define regCNVC_CFG1_COLOR_KEYER_ALPHA 0x0e43 4396#define regCNVC_CFG1_COLOR_KEYER_ALPHA_BASE_IDX 2 4397#define regCNVC_CFG1_COLOR_KEYER_RED 0x0e44 4398#define regCNVC_CFG1_COLOR_KEYER_RED_BASE_IDX 2 4399#define regCNVC_CFG1_COLOR_KEYER_GREEN 0x0e45 4400#define regCNVC_CFG1_COLOR_KEYER_GREEN_BASE_IDX 2 4401#define regCNVC_CFG1_COLOR_KEYER_BLUE 0x0e46 4402#define regCNVC_CFG1_COLOR_KEYER_BLUE_BASE_IDX 2 4403#define regCNVC_CFG1_ALPHA_2BIT_LUT 0x0e48 4404#define regCNVC_CFG1_ALPHA_2BIT_LUT_BASE_IDX 2 4405#define regCNVC_CFG1_PRE_DEALPHA 0x0e49 4406#define regCNVC_CFG1_PRE_DEALPHA_BASE_IDX 2 4407#define regCNVC_CFG1_PRE_CSC_MODE 0x0e4a 4408#define regCNVC_CFG1_PRE_CSC_MODE_BASE_IDX 2 4409#define regCNVC_CFG1_PRE_CSC_C11_C12 0x0e4b 4410#define regCNVC_CFG1_PRE_CSC_C11_C12_BASE_IDX 2 4411#define regCNVC_CFG1_PRE_CSC_C13_C14 0x0e4c 4412#define regCNVC_CFG1_PRE_CSC_C13_C14_BASE_IDX 2 4413#define regCNVC_CFG1_PRE_CSC_C21_C22 0x0e4d 4414#define regCNVC_CFG1_PRE_CSC_C21_C22_BASE_IDX 2 4415#define regCNVC_CFG1_PRE_CSC_C23_C24 0x0e4e 4416#define regCNVC_CFG1_PRE_CSC_C23_C24_BASE_IDX 2 4417#define regCNVC_CFG1_PRE_CSC_C31_C32 0x0e4f 4418#define regCNVC_CFG1_PRE_CSC_C31_C32_BASE_IDX 2 4419#define regCNVC_CFG1_PRE_CSC_C33_C34 0x0e50 4420#define regCNVC_CFG1_PRE_CSC_C33_C34_BASE_IDX 2 4421#define regCNVC_CFG1_PRE_CSC_B_C11_C12 0x0e51 4422#define regCNVC_CFG1_PRE_CSC_B_C11_C12_BASE_IDX 2 4423#define regCNVC_CFG1_PRE_CSC_B_C13_C14 0x0e52 4424#define regCNVC_CFG1_PRE_CSC_B_C13_C14_BASE_IDX 2 4425#define regCNVC_CFG1_PRE_CSC_B_C21_C22 0x0e53 4426#define regCNVC_CFG1_PRE_CSC_B_C21_C22_BASE_IDX 2 4427#define regCNVC_CFG1_PRE_CSC_B_C23_C24 0x0e54 4428#define regCNVC_CFG1_PRE_CSC_B_C23_C24_BASE_IDX 2 4429#define regCNVC_CFG1_PRE_CSC_B_C31_C32 0x0e55 4430#define regCNVC_CFG1_PRE_CSC_B_C31_C32_BASE_IDX 2 4431#define regCNVC_CFG1_PRE_CSC_B_C33_C34 0x0e56 4432#define regCNVC_CFG1_PRE_CSC_B_C33_C34_BASE_IDX 2 4433#define regCNVC_CFG1_CNVC_COEF_FORMAT 0x0e57 4434#define regCNVC_CFG1_CNVC_COEF_FORMAT_BASE_IDX 2 4435#define regCNVC_CFG1_PRE_DEGAM 0x0e58 4436#define regCNVC_CFG1_PRE_DEGAM_BASE_IDX 2 4437#define regCNVC_CFG1_PRE_REALPHA 0x0e59 4438#define regCNVC_CFG1_PRE_REALPHA_BASE_IDX 2 4439 4440 4441// addressBlock: dce_dc_dpp1_dispdec_cnvc_cur_dispdec 4442// base address: 0x5ac 4443#define regCNVC_CUR1_CURSOR0_CONTROL 0x0e5c 4444#define regCNVC_CUR1_CURSOR0_CONTROL_BASE_IDX 2 4445#define regCNVC_CUR1_CURSOR0_COLOR0 0x0e5d 4446#define regCNVC_CUR1_CURSOR0_COLOR0_BASE_IDX 2 4447#define regCNVC_CUR1_CURSOR0_COLOR1 0x0e5e 4448#define regCNVC_CUR1_CURSOR0_COLOR1_BASE_IDX 2 4449#define regCNVC_CUR1_CURSOR0_FP_SCALE_BIAS 0x0e5f 4450#define regCNVC_CUR1_CURSOR0_FP_SCALE_BIAS_BASE_IDX 2 4451 4452 4453// addressBlock: dce_dc_dpp1_dispdec_dscl_dispdec 4454// base address: 0x5ac 4455#define regDSCL1_SCL_COEF_RAM_TAP_SELECT 0x0e64 4456#define regDSCL1_SCL_COEF_RAM_TAP_SELECT_BASE_IDX 2 4457#define regDSCL1_SCL_COEF_RAM_TAP_DATA 0x0e65 4458#define regDSCL1_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2 4459#define regDSCL1_SCL_MODE 0x0e66 4460#define regDSCL1_SCL_MODE_BASE_IDX 2 4461#define regDSCL1_SCL_TAP_CONTROL 0x0e67 4462#define regDSCL1_SCL_TAP_CONTROL_BASE_IDX 2 4463#define regDSCL1_DSCL_CONTROL 0x0e68 4464#define regDSCL1_DSCL_CONTROL_BASE_IDX 2 4465#define regDSCL1_DSCL_2TAP_CONTROL 0x0e69 4466#define regDSCL1_DSCL_2TAP_CONTROL_BASE_IDX 2 4467#define regDSCL1_SCL_MANUAL_REPLICATE_CONTROL 0x0e6a 4468#define regDSCL1_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2 4469#define regDSCL1_SCL_HORZ_FILTER_SCALE_RATIO 0x0e6b 4470#define regDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2 4471#define regDSCL1_SCL_HORZ_FILTER_INIT 0x0e6c 4472#define regDSCL1_SCL_HORZ_FILTER_INIT_BASE_IDX 2 4473#define regDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C 0x0e6d 4474#define regDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX 2 4475#define regDSCL1_SCL_HORZ_FILTER_INIT_C 0x0e6e 4476#define regDSCL1_SCL_HORZ_FILTER_INIT_C_BASE_IDX 2 4477#define regDSCL1_SCL_VERT_FILTER_SCALE_RATIO 0x0e6f 4478#define regDSCL1_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2 4479#define regDSCL1_SCL_VERT_FILTER_INIT 0x0e70 4480#define regDSCL1_SCL_VERT_FILTER_INIT_BASE_IDX 2 4481#define regDSCL1_SCL_VERT_FILTER_INIT_BOT 0x0e71 4482#define regDSCL1_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2 4483#define regDSCL1_SCL_VERT_FILTER_SCALE_RATIO_C 0x0e72 4484#define regDSCL1_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX 2 4485#define regDSCL1_SCL_VERT_FILTER_INIT_C 0x0e73 4486#define regDSCL1_SCL_VERT_FILTER_INIT_C_BASE_IDX 2 4487#define regDSCL1_SCL_VERT_FILTER_INIT_BOT_C 0x0e74 4488#define regDSCL1_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX 2 4489#define regDSCL1_SCL_BLACK_COLOR 0x0e75 4490#define regDSCL1_SCL_BLACK_COLOR_BASE_IDX 2 4491#define regDSCL1_DSCL_UPDATE 0x0e76 4492#define regDSCL1_DSCL_UPDATE_BASE_IDX 2 4493#define regDSCL1_DSCL_AUTOCAL 0x0e77 4494#define regDSCL1_DSCL_AUTOCAL_BASE_IDX 2 4495#define regDSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT 0x0e78 4496#define regDSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2 4497#define regDSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM 0x0e79 4498#define regDSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2 4499#define regDSCL1_OTG_H_BLANK 0x0e7a 4500#define regDSCL1_OTG_H_BLANK_BASE_IDX 2 4501#define regDSCL1_OTG_V_BLANK 0x0e7b 4502#define regDSCL1_OTG_V_BLANK_BASE_IDX 2 4503#define regDSCL1_RECOUT_START 0x0e7c 4504#define regDSCL1_RECOUT_START_BASE_IDX 2 4505#define regDSCL1_RECOUT_SIZE 0x0e7d 4506#define regDSCL1_RECOUT_SIZE_BASE_IDX 2 4507#define regDSCL1_MPC_SIZE 0x0e7e 4508#define regDSCL1_MPC_SIZE_BASE_IDX 2 4509#define regDSCL1_LB_DATA_FORMAT 0x0e7f 4510#define regDSCL1_LB_DATA_FORMAT_BASE_IDX 2 4511#define regDSCL1_LB_MEMORY_CTRL 0x0e80 4512#define regDSCL1_LB_MEMORY_CTRL_BASE_IDX 2 4513#define regDSCL1_LB_V_COUNTER 0x0e81 4514#define regDSCL1_LB_V_COUNTER_BASE_IDX 2 4515#define regDSCL1_DSCL_MEM_PWR_CTRL 0x0e82 4516#define regDSCL1_DSCL_MEM_PWR_CTRL_BASE_IDX 2 4517#define regDSCL1_DSCL_MEM_PWR_STATUS 0x0e83 4518#define regDSCL1_DSCL_MEM_PWR_STATUS_BASE_IDX 2 4519#define regDSCL1_OBUF_CONTROL 0x0e84 4520#define regDSCL1_OBUF_CONTROL_BASE_IDX 2 4521#define regDSCL1_OBUF_MEM_PWR_CTRL 0x0e85 4522#define regDSCL1_OBUF_MEM_PWR_CTRL_BASE_IDX 2 4523 4524 4525// addressBlock: dce_dc_dpp1_dispdec_cm_dispdec 4526// base address: 0x5ac 4527#define regCM1_CM_CONTROL 0x0e8b 4528#define regCM1_CM_CONTROL_BASE_IDX 2 4529#define regCM1_CM_POST_CSC_CONTROL 0x0e8c 4530#define regCM1_CM_POST_CSC_CONTROL_BASE_IDX 2 4531#define regCM1_CM_POST_CSC_C11_C12 0x0e8d 4532#define regCM1_CM_POST_CSC_C11_C12_BASE_IDX 2 4533#define regCM1_CM_POST_CSC_C13_C14 0x0e8e 4534#define regCM1_CM_POST_CSC_C13_C14_BASE_IDX 2 4535#define regCM1_CM_POST_CSC_C21_C22 0x0e8f 4536#define regCM1_CM_POST_CSC_C21_C22_BASE_IDX 2 4537#define regCM1_CM_POST_CSC_C23_C24 0x0e90 4538#define regCM1_CM_POST_CSC_C23_C24_BASE_IDX 2 4539#define regCM1_CM_POST_CSC_C31_C32 0x0e91 4540#define regCM1_CM_POST_CSC_C31_C32_BASE_IDX 2 4541#define regCM1_CM_POST_CSC_C33_C34 0x0e92 4542#define regCM1_CM_POST_CSC_C33_C34_BASE_IDX 2 4543#define regCM1_CM_POST_CSC_B_C11_C12 0x0e93 4544#define regCM1_CM_POST_CSC_B_C11_C12_BASE_IDX 2 4545#define regCM1_CM_POST_CSC_B_C13_C14 0x0e94 4546#define regCM1_CM_POST_CSC_B_C13_C14_BASE_IDX 2 4547#define regCM1_CM_POST_CSC_B_C21_C22 0x0e95 4548#define regCM1_CM_POST_CSC_B_C21_C22_BASE_IDX 2 4549#define regCM1_CM_POST_CSC_B_C23_C24 0x0e96 4550#define regCM1_CM_POST_CSC_B_C23_C24_BASE_IDX 2 4551#define regCM1_CM_POST_CSC_B_C31_C32 0x0e97 4552#define regCM1_CM_POST_CSC_B_C31_C32_BASE_IDX 2 4553#define regCM1_CM_POST_CSC_B_C33_C34 0x0e98 4554#define regCM1_CM_POST_CSC_B_C33_C34_BASE_IDX 2 4555#define regCM1_CM_GAMUT_REMAP_CONTROL 0x0e99 4556#define regCM1_CM_GAMUT_REMAP_CONTROL_BASE_IDX 2 4557#define regCM1_CM_GAMUT_REMAP_C11_C12 0x0e9a 4558#define regCM1_CM_GAMUT_REMAP_C11_C12_BASE_IDX 2 4559#define regCM1_CM_GAMUT_REMAP_C13_C14 0x0e9b 4560#define regCM1_CM_GAMUT_REMAP_C13_C14_BASE_IDX 2 4561#define regCM1_CM_GAMUT_REMAP_C21_C22 0x0e9c 4562#define regCM1_CM_GAMUT_REMAP_C21_C22_BASE_IDX 2 4563#define regCM1_CM_GAMUT_REMAP_C23_C24 0x0e9d 4564#define regCM1_CM_GAMUT_REMAP_C23_C24_BASE_IDX 2 4565#define regCM1_CM_GAMUT_REMAP_C31_C32 0x0e9e 4566#define regCM1_CM_GAMUT_REMAP_C31_C32_BASE_IDX 2 4567#define regCM1_CM_GAMUT_REMAP_C33_C34 0x0e9f 4568#define regCM1_CM_GAMUT_REMAP_C33_C34_BASE_IDX 2 4569#define regCM1_CM_GAMUT_REMAP_B_C11_C12 0x0ea0 4570#define regCM1_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX 2 4571#define regCM1_CM_GAMUT_REMAP_B_C13_C14 0x0ea1 4572#define regCM1_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX 2 4573#define regCM1_CM_GAMUT_REMAP_B_C21_C22 0x0ea2 4574#define regCM1_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX 2 4575#define regCM1_CM_GAMUT_REMAP_B_C23_C24 0x0ea3 4576#define regCM1_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX 2 4577#define regCM1_CM_GAMUT_REMAP_B_C31_C32 0x0ea4 4578#define regCM1_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX 2 4579#define regCM1_CM_GAMUT_REMAP_B_C33_C34 0x0ea5 4580#define regCM1_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX 2 4581#define regCM1_CM_BIAS_CR_R 0x0ea6 4582#define regCM1_CM_BIAS_CR_R_BASE_IDX 2 4583#define regCM1_CM_BIAS_Y_G_CB_B 0x0ea7 4584#define regCM1_CM_BIAS_Y_G_CB_B_BASE_IDX 2 4585#define regCM1_CM_GAMCOR_CONTROL 0x0ea8 4586#define regCM1_CM_GAMCOR_CONTROL_BASE_IDX 2 4587#define regCM1_CM_GAMCOR_LUT_INDEX 0x0ea9 4588#define regCM1_CM_GAMCOR_LUT_INDEX_BASE_IDX 2 4589#define regCM1_CM_GAMCOR_LUT_DATA 0x0eaa 4590#define regCM1_CM_GAMCOR_LUT_DATA_BASE_IDX 2 4591#define regCM1_CM_GAMCOR_LUT_CONTROL 0x0eab 4592#define regCM1_CM_GAMCOR_LUT_CONTROL_BASE_IDX 2 4593#define regCM1_CM_GAMCOR_RAMA_START_CNTL_B 0x0eac 4594#define regCM1_CM_GAMCOR_RAMA_START_CNTL_B_BASE_IDX 2 4595#define regCM1_CM_GAMCOR_RAMA_START_CNTL_G 0x0ead 4596#define regCM1_CM_GAMCOR_RAMA_START_CNTL_G_BASE_IDX 2 4597#define regCM1_CM_GAMCOR_RAMA_START_CNTL_R 0x0eae 4598#define regCM1_CM_GAMCOR_RAMA_START_CNTL_R_BASE_IDX 2 4599#define regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B 0x0eaf 4600#define regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B_BASE_IDX 2 4601#define regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G 0x0eb0 4602#define regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2 4603#define regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R 0x0eb1 4604#define regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R_BASE_IDX 2 4605#define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_B 0x0eb2 4606#define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_B_BASE_IDX 2 4607#define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_G 0x0eb3 4608#define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_G_BASE_IDX 2 4609#define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_R 0x0eb4 4610#define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_R_BASE_IDX 2 4611#define regCM1_CM_GAMCOR_RAMA_END_CNTL1_B 0x0eb5 4612#define regCM1_CM_GAMCOR_RAMA_END_CNTL1_B_BASE_IDX 2 4613#define regCM1_CM_GAMCOR_RAMA_END_CNTL2_B 0x0eb6 4614#define regCM1_CM_GAMCOR_RAMA_END_CNTL2_B_BASE_IDX 2 4615#define regCM1_CM_GAMCOR_RAMA_END_CNTL1_G 0x0eb7 4616#define regCM1_CM_GAMCOR_RAMA_END_CNTL1_G_BASE_IDX 2 4617#define regCM1_CM_GAMCOR_RAMA_END_CNTL2_G 0x0eb8 4618#define regCM1_CM_GAMCOR_RAMA_END_CNTL2_G_BASE_IDX 2 4619#define regCM1_CM_GAMCOR_RAMA_END_CNTL1_R 0x0eb9 4620#define regCM1_CM_GAMCOR_RAMA_END_CNTL1_R_BASE_IDX 2 4621#define regCM1_CM_GAMCOR_RAMA_END_CNTL2_R 0x0eba 4622#define regCM1_CM_GAMCOR_RAMA_END_CNTL2_R_BASE_IDX 2 4623#define regCM1_CM_GAMCOR_RAMA_OFFSET_B 0x0ebb 4624#define regCM1_CM_GAMCOR_RAMA_OFFSET_B_BASE_IDX 2 4625#define regCM1_CM_GAMCOR_RAMA_OFFSET_G 0x0ebc 4626#define regCM1_CM_GAMCOR_RAMA_OFFSET_G_BASE_IDX 2 4627#define regCM1_CM_GAMCOR_RAMA_OFFSET_R 0x0ebd 4628#define regCM1_CM_GAMCOR_RAMA_OFFSET_R_BASE_IDX 2 4629#define regCM1_CM_GAMCOR_RAMA_REGION_0_1 0x0ebe 4630#define regCM1_CM_GAMCOR_RAMA_REGION_0_1_BASE_IDX 2 4631#define regCM1_CM_GAMCOR_RAMA_REGION_2_3 0x0ebf 4632#define regCM1_CM_GAMCOR_RAMA_REGION_2_3_BASE_IDX 2 4633#define regCM1_CM_GAMCOR_RAMA_REGION_4_5 0x0ec0 4634#define regCM1_CM_GAMCOR_RAMA_REGION_4_5_BASE_IDX 2 4635#define regCM1_CM_GAMCOR_RAMA_REGION_6_7 0x0ec1 4636#define regCM1_CM_GAMCOR_RAMA_REGION_6_7_BASE_IDX 2 4637#define regCM1_CM_GAMCOR_RAMA_REGION_8_9 0x0ec2 4638#define regCM1_CM_GAMCOR_RAMA_REGION_8_9_BASE_IDX 2 4639#define regCM1_CM_GAMCOR_RAMA_REGION_10_11 0x0ec3 4640#define regCM1_CM_GAMCOR_RAMA_REGION_10_11_BASE_IDX 2 4641#define regCM1_CM_GAMCOR_RAMA_REGION_12_13 0x0ec4 4642#define regCM1_CM_GAMCOR_RAMA_REGION_12_13_BASE_IDX 2 4643#define regCM1_CM_GAMCOR_RAMA_REGION_14_15 0x0ec5 4644#define regCM1_CM_GAMCOR_RAMA_REGION_14_15_BASE_IDX 2 4645#define regCM1_CM_GAMCOR_RAMA_REGION_16_17 0x0ec6 4646#define regCM1_CM_GAMCOR_RAMA_REGION_16_17_BASE_IDX 2 4647#define regCM1_CM_GAMCOR_RAMA_REGION_18_19 0x0ec7 4648#define regCM1_CM_GAMCOR_RAMA_REGION_18_19_BASE_IDX 2 4649#define regCM1_CM_GAMCOR_RAMA_REGION_20_21 0x0ec8 4650#define regCM1_CM_GAMCOR_RAMA_REGION_20_21_BASE_IDX 2 4651#define regCM1_CM_GAMCOR_RAMA_REGION_22_23 0x0ec9 4652#define regCM1_CM_GAMCOR_RAMA_REGION_22_23_BASE_IDX 2 4653#define regCM1_CM_GAMCOR_RAMA_REGION_24_25 0x0eca 4654#define regCM1_CM_GAMCOR_RAMA_REGION_24_25_BASE_IDX 2 4655#define regCM1_CM_GAMCOR_RAMA_REGION_26_27 0x0ecb 4656#define regCM1_CM_GAMCOR_RAMA_REGION_26_27_BASE_IDX 2 4657#define regCM1_CM_GAMCOR_RAMA_REGION_28_29 0x0ecc 4658#define regCM1_CM_GAMCOR_RAMA_REGION_28_29_BASE_IDX 2 4659#define regCM1_CM_GAMCOR_RAMA_REGION_30_31 0x0ecd 4660#define regCM1_CM_GAMCOR_RAMA_REGION_30_31_BASE_IDX 2 4661#define regCM1_CM_GAMCOR_RAMA_REGION_32_33 0x0ece 4662#define regCM1_CM_GAMCOR_RAMA_REGION_32_33_BASE_IDX 2 4663#define regCM1_CM_GAMCOR_RAMB_START_CNTL_B 0x0ecf 4664#define regCM1_CM_GAMCOR_RAMB_START_CNTL_B_BASE_IDX 2 4665#define regCM1_CM_GAMCOR_RAMB_START_CNTL_G 0x0ed0 4666#define regCM1_CM_GAMCOR_RAMB_START_CNTL_G_BASE_IDX 2 4667#define regCM1_CM_GAMCOR_RAMB_START_CNTL_R 0x0ed1 4668#define regCM1_CM_GAMCOR_RAMB_START_CNTL_R_BASE_IDX 2 4669#define regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B 0x0ed2 4670#define regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B_BASE_IDX 2 4671#define regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G 0x0ed3 4672#define regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G_BASE_IDX 2 4673#define regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R 0x0ed4 4674#define regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R_BASE_IDX 2 4675#define regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_B 0x0ed5 4676#define regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_B_BASE_IDX 2 4677#define regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_G 0x0ed6 4678#define regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_G_BASE_IDX 2 4679#define regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_R 0x0ed7 4680#define regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_R_BASE_IDX 2 4681#define regCM1_CM_GAMCOR_RAMB_END_CNTL1_B 0x0ed8 4682#define regCM1_CM_GAMCOR_RAMB_END_CNTL1_B_BASE_IDX 2 4683#define regCM1_CM_GAMCOR_RAMB_END_CNTL2_B 0x0ed9 4684#define regCM1_CM_GAMCOR_RAMB_END_CNTL2_B_BASE_IDX 2 4685#define regCM1_CM_GAMCOR_RAMB_END_CNTL1_G 0x0eda 4686#define regCM1_CM_GAMCOR_RAMB_END_CNTL1_G_BASE_IDX 2 4687#define regCM1_CM_GAMCOR_RAMB_END_CNTL2_G 0x0edb 4688#define regCM1_CM_GAMCOR_RAMB_END_CNTL2_G_BASE_IDX 2 4689#define regCM1_CM_GAMCOR_RAMB_END_CNTL1_R 0x0edc 4690#define regCM1_CM_GAMCOR_RAMB_END_CNTL1_R_BASE_IDX 2 4691#define regCM1_CM_GAMCOR_RAMB_END_CNTL2_R 0x0edd 4692#define regCM1_CM_GAMCOR_RAMB_END_CNTL2_R_BASE_IDX 2 4693#define regCM1_CM_GAMCOR_RAMB_OFFSET_B 0x0ede 4694#define regCM1_CM_GAMCOR_RAMB_OFFSET_B_BASE_IDX 2 4695#define regCM1_CM_GAMCOR_RAMB_OFFSET_G 0x0edf 4696#define regCM1_CM_GAMCOR_RAMB_OFFSET_G_BASE_IDX 2 4697#define regCM1_CM_GAMCOR_RAMB_OFFSET_R 0x0ee0 4698#define regCM1_CM_GAMCOR_RAMB_OFFSET_R_BASE_IDX 2 4699#define regCM1_CM_GAMCOR_RAMB_REGION_0_1 0x0ee1 4700#define regCM1_CM_GAMCOR_RAMB_REGION_0_1_BASE_IDX 2 4701#define regCM1_CM_GAMCOR_RAMB_REGION_2_3 0x0ee2 4702#define regCM1_CM_GAMCOR_RAMB_REGION_2_3_BASE_IDX 2 4703#define regCM1_CM_GAMCOR_RAMB_REGION_4_5 0x0ee3 4704#define regCM1_CM_GAMCOR_RAMB_REGION_4_5_BASE_IDX 2 4705#define regCM1_CM_GAMCOR_RAMB_REGION_6_7 0x0ee4 4706#define regCM1_CM_GAMCOR_RAMB_REGION_6_7_BASE_IDX 2 4707#define regCM1_CM_GAMCOR_RAMB_REGION_8_9 0x0ee5 4708#define regCM1_CM_GAMCOR_RAMB_REGION_8_9_BASE_IDX 2 4709#define regCM1_CM_GAMCOR_RAMB_REGION_10_11 0x0ee6 4710#define regCM1_CM_GAMCOR_RAMB_REGION_10_11_BASE_IDX 2 4711#define regCM1_CM_GAMCOR_RAMB_REGION_12_13 0x0ee7 4712#define regCM1_CM_GAMCOR_RAMB_REGION_12_13_BASE_IDX 2 4713#define regCM1_CM_GAMCOR_RAMB_REGION_14_15 0x0ee8 4714#define regCM1_CM_GAMCOR_RAMB_REGION_14_15_BASE_IDX 2 4715#define regCM1_CM_GAMCOR_RAMB_REGION_16_17 0x0ee9 4716#define regCM1_CM_GAMCOR_RAMB_REGION_16_17_BASE_IDX 2 4717#define regCM1_CM_GAMCOR_RAMB_REGION_18_19 0x0eea 4718#define regCM1_CM_GAMCOR_RAMB_REGION_18_19_BASE_IDX 2 4719#define regCM1_CM_GAMCOR_RAMB_REGION_20_21 0x0eeb 4720#define regCM1_CM_GAMCOR_RAMB_REGION_20_21_BASE_IDX 2 4721#define regCM1_CM_GAMCOR_RAMB_REGION_22_23 0x0eec 4722#define regCM1_CM_GAMCOR_RAMB_REGION_22_23_BASE_IDX 2 4723#define regCM1_CM_GAMCOR_RAMB_REGION_24_25 0x0eed 4724#define regCM1_CM_GAMCOR_RAMB_REGION_24_25_BASE_IDX 2 4725#define regCM1_CM_GAMCOR_RAMB_REGION_26_27 0x0eee 4726#define regCM1_CM_GAMCOR_RAMB_REGION_26_27_BASE_IDX 2 4727#define regCM1_CM_GAMCOR_RAMB_REGION_28_29 0x0eef 4728#define regCM1_CM_GAMCOR_RAMB_REGION_28_29_BASE_IDX 2 4729#define regCM1_CM_GAMCOR_RAMB_REGION_30_31 0x0ef0 4730#define regCM1_CM_GAMCOR_RAMB_REGION_30_31_BASE_IDX 2 4731#define regCM1_CM_GAMCOR_RAMB_REGION_32_33 0x0ef1 4732#define regCM1_CM_GAMCOR_RAMB_REGION_32_33_BASE_IDX 2 4733#define regCM1_CM_BLNDGAM_CONTROL 0x0ef2 4734#define regCM1_CM_BLNDGAM_CONTROL_BASE_IDX 2 4735#define regCM1_CM_BLNDGAM_LUT_INDEX 0x0ef3 4736#define regCM1_CM_BLNDGAM_LUT_INDEX_BASE_IDX 2 4737#define regCM1_CM_BLNDGAM_LUT_DATA 0x0ef4 4738#define regCM1_CM_BLNDGAM_LUT_DATA_BASE_IDX 2 4739#define regCM1_CM_BLNDGAM_LUT_CONTROL 0x0ef5 4740#define regCM1_CM_BLNDGAM_LUT_CONTROL_BASE_IDX 2 4741#define regCM1_CM_BLNDGAM_RAMA_START_CNTL_B 0x0ef6 4742#define regCM1_CM_BLNDGAM_RAMA_START_CNTL_B_BASE_IDX 2 4743#define regCM1_CM_BLNDGAM_RAMA_START_CNTL_G 0x0ef7 4744#define regCM1_CM_BLNDGAM_RAMA_START_CNTL_G_BASE_IDX 2 4745#define regCM1_CM_BLNDGAM_RAMA_START_CNTL_R 0x0ef8 4746#define regCM1_CM_BLNDGAM_RAMA_START_CNTL_R_BASE_IDX 2 4747#define regCM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B 0x0ef9 4748#define regCM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX 2 4749#define regCM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G 0x0efa 4750#define regCM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2 4751#define regCM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R 0x0efb 4752#define regCM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX 2 4753#define regCM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_B 0x0efc 4754#define regCM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_B_BASE_IDX 2 4755#define regCM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_G 0x0efd 4756#define regCM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_G_BASE_IDX 2 4757#define regCM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_R 0x0efe 4758#define regCM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_R_BASE_IDX 2 4759#define regCM1_CM_BLNDGAM_RAMA_END_CNTL1_B 0x0eff 4760#define regCM1_CM_BLNDGAM_RAMA_END_CNTL1_B_BASE_IDX 2 4761#define regCM1_CM_BLNDGAM_RAMA_END_CNTL2_B 0x0f00 4762#define regCM1_CM_BLNDGAM_RAMA_END_CNTL2_B_BASE_IDX 2 4763#define regCM1_CM_BLNDGAM_RAMA_END_CNTL1_G 0x0f01 4764#define regCM1_CM_BLNDGAM_RAMA_END_CNTL1_G_BASE_IDX 2 4765#define regCM1_CM_BLNDGAM_RAMA_END_CNTL2_G 0x0f02 4766#define regCM1_CM_BLNDGAM_RAMA_END_CNTL2_G_BASE_IDX 2 4767#define regCM1_CM_BLNDGAM_RAMA_END_CNTL1_R 0x0f03 4768#define regCM1_CM_BLNDGAM_RAMA_END_CNTL1_R_BASE_IDX 2 4769#define regCM1_CM_BLNDGAM_RAMA_END_CNTL2_R 0x0f04 4770#define regCM1_CM_BLNDGAM_RAMA_END_CNTL2_R_BASE_IDX 2 4771#define regCM1_CM_BLNDGAM_RAMA_OFFSET_B 0x0f05 4772#define regCM1_CM_BLNDGAM_RAMA_OFFSET_B_BASE_IDX 2 4773#define regCM1_CM_BLNDGAM_RAMA_OFFSET_G 0x0f06 4774#define regCM1_CM_BLNDGAM_RAMA_OFFSET_G_BASE_IDX 2 4775#define regCM1_CM_BLNDGAM_RAMA_OFFSET_R 0x0f07 4776#define regCM1_CM_BLNDGAM_RAMA_OFFSET_R_BASE_IDX 2 4777#define regCM1_CM_BLNDGAM_RAMA_REGION_0_1 0x0f08 4778#define regCM1_CM_BLNDGAM_RAMA_REGION_0_1_BASE_IDX 2 4779#define regCM1_CM_BLNDGAM_RAMA_REGION_2_3 0x0f09 4780#define regCM1_CM_BLNDGAM_RAMA_REGION_2_3_BASE_IDX 2 4781#define regCM1_CM_BLNDGAM_RAMA_REGION_4_5 0x0f0a 4782#define regCM1_CM_BLNDGAM_RAMA_REGION_4_5_BASE_IDX 2 4783#define regCM1_CM_BLNDGAM_RAMA_REGION_6_7 0x0f0b 4784#define regCM1_CM_BLNDGAM_RAMA_REGION_6_7_BASE_IDX 2 4785#define regCM1_CM_BLNDGAM_RAMA_REGION_8_9 0x0f0c 4786#define regCM1_CM_BLNDGAM_RAMA_REGION_8_9_BASE_IDX 2 4787#define regCM1_CM_BLNDGAM_RAMA_REGION_10_11 0x0f0d 4788#define regCM1_CM_BLNDGAM_RAMA_REGION_10_11_BASE_IDX 2 4789#define regCM1_CM_BLNDGAM_RAMA_REGION_12_13 0x0f0e 4790#define regCM1_CM_BLNDGAM_RAMA_REGION_12_13_BASE_IDX 2 4791#define regCM1_CM_BLNDGAM_RAMA_REGION_14_15 0x0f0f 4792#define regCM1_CM_BLNDGAM_RAMA_REGION_14_15_BASE_IDX 2 4793#define regCM1_CM_BLNDGAM_RAMA_REGION_16_17 0x0f10 4794#define regCM1_CM_BLNDGAM_RAMA_REGION_16_17_BASE_IDX 2 4795#define regCM1_CM_BLNDGAM_RAMA_REGION_18_19 0x0f11 4796#define regCM1_CM_BLNDGAM_RAMA_REGION_18_19_BASE_IDX 2 4797#define regCM1_CM_BLNDGAM_RAMA_REGION_20_21 0x0f12 4798#define regCM1_CM_BLNDGAM_RAMA_REGION_20_21_BASE_IDX 2 4799#define regCM1_CM_BLNDGAM_RAMA_REGION_22_23 0x0f13 4800#define regCM1_CM_BLNDGAM_RAMA_REGION_22_23_BASE_IDX 2 4801#define regCM1_CM_BLNDGAM_RAMA_REGION_24_25 0x0f14 4802#define regCM1_CM_BLNDGAM_RAMA_REGION_24_25_BASE_IDX 2 4803#define regCM1_CM_BLNDGAM_RAMA_REGION_26_27 0x0f15 4804#define regCM1_CM_BLNDGAM_RAMA_REGION_26_27_BASE_IDX 2 4805#define regCM1_CM_BLNDGAM_RAMA_REGION_28_29 0x0f16 4806#define regCM1_CM_BLNDGAM_RAMA_REGION_28_29_BASE_IDX 2 4807#define regCM1_CM_BLNDGAM_RAMA_REGION_30_31 0x0f17 4808#define regCM1_CM_BLNDGAM_RAMA_REGION_30_31_BASE_IDX 2 4809#define regCM1_CM_BLNDGAM_RAMA_REGION_32_33 0x0f18 4810#define regCM1_CM_BLNDGAM_RAMA_REGION_32_33_BASE_IDX 2 4811#define regCM1_CM_BLNDGAM_RAMB_START_CNTL_B 0x0f19 4812#define regCM1_CM_BLNDGAM_RAMB_START_CNTL_B_BASE_IDX 2 4813#define regCM1_CM_BLNDGAM_RAMB_START_CNTL_G 0x0f1a 4814#define regCM1_CM_BLNDGAM_RAMB_START_CNTL_G_BASE_IDX 2 4815#define regCM1_CM_BLNDGAM_RAMB_START_CNTL_R 0x0f1b 4816#define regCM1_CM_BLNDGAM_RAMB_START_CNTL_R_BASE_IDX 2 4817#define regCM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B 0x0f1c 4818#define regCM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX 2 4819#define regCM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G 0x0f1d 4820#define regCM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX 2 4821#define regCM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R 0x0f1e 4822#define regCM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX 2 4823#define regCM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_B 0x0f1f 4824#define regCM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_B_BASE_IDX 2 4825#define regCM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_G 0x0f20 4826#define regCM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_G_BASE_IDX 2 4827#define regCM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_R 0x0f21 4828#define regCM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_R_BASE_IDX 2 4829#define regCM1_CM_BLNDGAM_RAMB_END_CNTL1_B 0x0f22 4830#define regCM1_CM_BLNDGAM_RAMB_END_CNTL1_B_BASE_IDX 2 4831#define regCM1_CM_BLNDGAM_RAMB_END_CNTL2_B 0x0f23 4832#define regCM1_CM_BLNDGAM_RAMB_END_CNTL2_B_BASE_IDX 2 4833#define regCM1_CM_BLNDGAM_RAMB_END_CNTL1_G 0x0f24 4834#define regCM1_CM_BLNDGAM_RAMB_END_CNTL1_G_BASE_IDX 2 4835#define regCM1_CM_BLNDGAM_RAMB_END_CNTL2_G 0x0f25 4836#define regCM1_CM_BLNDGAM_RAMB_END_CNTL2_G_BASE_IDX 2 4837#define regCM1_CM_BLNDGAM_RAMB_END_CNTL1_R 0x0f26 4838#define regCM1_CM_BLNDGAM_RAMB_END_CNTL1_R_BASE_IDX 2 4839#define regCM1_CM_BLNDGAM_RAMB_END_CNTL2_R 0x0f27 4840#define regCM1_CM_BLNDGAM_RAMB_END_CNTL2_R_BASE_IDX 2 4841#define regCM1_CM_BLNDGAM_RAMB_OFFSET_B 0x0f28 4842#define regCM1_CM_BLNDGAM_RAMB_OFFSET_B_BASE_IDX 2 4843#define regCM1_CM_BLNDGAM_RAMB_OFFSET_G 0x0f29 4844#define regCM1_CM_BLNDGAM_RAMB_OFFSET_G_BASE_IDX 2 4845#define regCM1_CM_BLNDGAM_RAMB_OFFSET_R 0x0f2a 4846#define regCM1_CM_BLNDGAM_RAMB_OFFSET_R_BASE_IDX 2 4847#define regCM1_CM_BLNDGAM_RAMB_REGION_0_1 0x0f2b 4848#define regCM1_CM_BLNDGAM_RAMB_REGION_0_1_BASE_IDX 2 4849#define regCM1_CM_BLNDGAM_RAMB_REGION_2_3 0x0f2c 4850#define regCM1_CM_BLNDGAM_RAMB_REGION_2_3_BASE_IDX 2 4851#define regCM1_CM_BLNDGAM_RAMB_REGION_4_5 0x0f2d 4852#define regCM1_CM_BLNDGAM_RAMB_REGION_4_5_BASE_IDX 2 4853#define regCM1_CM_BLNDGAM_RAMB_REGION_6_7 0x0f2e 4854#define regCM1_CM_BLNDGAM_RAMB_REGION_6_7_BASE_IDX 2 4855#define regCM1_CM_BLNDGAM_RAMB_REGION_8_9 0x0f2f 4856#define regCM1_CM_BLNDGAM_RAMB_REGION_8_9_BASE_IDX 2 4857#define regCM1_CM_BLNDGAM_RAMB_REGION_10_11 0x0f30 4858#define regCM1_CM_BLNDGAM_RAMB_REGION_10_11_BASE_IDX 2 4859#define regCM1_CM_BLNDGAM_RAMB_REGION_12_13 0x0f31 4860#define regCM1_CM_BLNDGAM_RAMB_REGION_12_13_BASE_IDX 2 4861#define regCM1_CM_BLNDGAM_RAMB_REGION_14_15 0x0f32 4862#define regCM1_CM_BLNDGAM_RAMB_REGION_14_15_BASE_IDX 2 4863#define regCM1_CM_BLNDGAM_RAMB_REGION_16_17 0x0f33 4864#define regCM1_CM_BLNDGAM_RAMB_REGION_16_17_BASE_IDX 2 4865#define regCM1_CM_BLNDGAM_RAMB_REGION_18_19 0x0f34 4866#define regCM1_CM_BLNDGAM_RAMB_REGION_18_19_BASE_IDX 2 4867#define regCM1_CM_BLNDGAM_RAMB_REGION_20_21 0x0f35 4868#define regCM1_CM_BLNDGAM_RAMB_REGION_20_21_BASE_IDX 2 4869#define regCM1_CM_BLNDGAM_RAMB_REGION_22_23 0x0f36 4870#define regCM1_CM_BLNDGAM_RAMB_REGION_22_23_BASE_IDX 2 4871#define regCM1_CM_BLNDGAM_RAMB_REGION_24_25 0x0f37 4872#define regCM1_CM_BLNDGAM_RAMB_REGION_24_25_BASE_IDX 2 4873#define regCM1_CM_BLNDGAM_RAMB_REGION_26_27 0x0f38 4874#define regCM1_CM_BLNDGAM_RAMB_REGION_26_27_BASE_IDX 2 4875#define regCM1_CM_BLNDGAM_RAMB_REGION_28_29 0x0f39 4876#define regCM1_CM_BLNDGAM_RAMB_REGION_28_29_BASE_IDX 2 4877#define regCM1_CM_BLNDGAM_RAMB_REGION_30_31 0x0f3a 4878#define regCM1_CM_BLNDGAM_RAMB_REGION_30_31_BASE_IDX 2 4879#define regCM1_CM_BLNDGAM_RAMB_REGION_32_33 0x0f3b 4880#define regCM1_CM_BLNDGAM_RAMB_REGION_32_33_BASE_IDX 2 4881#define regCM1_CM_HDR_MULT_COEF 0x0f3c 4882#define regCM1_CM_HDR_MULT_COEF_BASE_IDX 2 4883#define regCM1_CM_MEM_PWR_CTRL 0x0f3d 4884#define regCM1_CM_MEM_PWR_CTRL_BASE_IDX 2 4885#define regCM1_CM_MEM_PWR_STATUS 0x0f3e 4886#define regCM1_CM_MEM_PWR_STATUS_BASE_IDX 2 4887#define regCM1_CM_DEALPHA 0x0f40 4888#define regCM1_CM_DEALPHA_BASE_IDX 2 4889#define regCM1_CM_COEF_FORMAT 0x0f41 4890#define regCM1_CM_COEF_FORMAT_BASE_IDX 2 4891#define regCM1_CM_SHAPER_CONTROL 0x0f42 4892#define regCM1_CM_SHAPER_CONTROL_BASE_IDX 2 4893#define regCM1_CM_SHAPER_OFFSET_R 0x0f43 4894#define regCM1_CM_SHAPER_OFFSET_R_BASE_IDX 2 4895#define regCM1_CM_SHAPER_OFFSET_G 0x0f44 4896#define regCM1_CM_SHAPER_OFFSET_G_BASE_IDX 2 4897#define regCM1_CM_SHAPER_OFFSET_B 0x0f45 4898#define regCM1_CM_SHAPER_OFFSET_B_BASE_IDX 2 4899#define regCM1_CM_SHAPER_SCALE_R 0x0f46 4900#define regCM1_CM_SHAPER_SCALE_R_BASE_IDX 2 4901#define regCM1_CM_SHAPER_SCALE_G_B 0x0f47 4902#define regCM1_CM_SHAPER_SCALE_G_B_BASE_IDX 2 4903#define regCM1_CM_SHAPER_LUT_INDEX 0x0f48 4904#define regCM1_CM_SHAPER_LUT_INDEX_BASE_IDX 2 4905#define regCM1_CM_SHAPER_LUT_DATA 0x0f49 4906#define regCM1_CM_SHAPER_LUT_DATA_BASE_IDX 2 4907#define regCM1_CM_SHAPER_LUT_WRITE_EN_MASK 0x0f4a 4908#define regCM1_CM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX 2 4909#define regCM1_CM_SHAPER_RAMA_START_CNTL_B 0x0f4b 4910#define regCM1_CM_SHAPER_RAMA_START_CNTL_B_BASE_IDX 2 4911#define regCM1_CM_SHAPER_RAMA_START_CNTL_G 0x0f4c 4912#define regCM1_CM_SHAPER_RAMA_START_CNTL_G_BASE_IDX 2 4913#define regCM1_CM_SHAPER_RAMA_START_CNTL_R 0x0f4d 4914#define regCM1_CM_SHAPER_RAMA_START_CNTL_R_BASE_IDX 2 4915#define regCM1_CM_SHAPER_RAMA_END_CNTL_B 0x0f4e 4916#define regCM1_CM_SHAPER_RAMA_END_CNTL_B_BASE_IDX 2 4917#define regCM1_CM_SHAPER_RAMA_END_CNTL_G 0x0f4f 4918#define regCM1_CM_SHAPER_RAMA_END_CNTL_G_BASE_IDX 2 4919#define regCM1_CM_SHAPER_RAMA_END_CNTL_R 0x0f50 4920#define regCM1_CM_SHAPER_RAMA_END_CNTL_R_BASE_IDX 2 4921#define regCM1_CM_SHAPER_RAMA_REGION_0_1 0x0f51 4922#define regCM1_CM_SHAPER_RAMA_REGION_0_1_BASE_IDX 2 4923#define regCM1_CM_SHAPER_RAMA_REGION_2_3 0x0f52 4924#define regCM1_CM_SHAPER_RAMA_REGION_2_3_BASE_IDX 2 4925#define regCM1_CM_SHAPER_RAMA_REGION_4_5 0x0f53 4926#define regCM1_CM_SHAPER_RAMA_REGION_4_5_BASE_IDX 2 4927#define regCM1_CM_SHAPER_RAMA_REGION_6_7 0x0f54 4928#define regCM1_CM_SHAPER_RAMA_REGION_6_7_BASE_IDX 2 4929#define regCM1_CM_SHAPER_RAMA_REGION_8_9 0x0f55 4930#define regCM1_CM_SHAPER_RAMA_REGION_8_9_BASE_IDX 2 4931#define regCM1_CM_SHAPER_RAMA_REGION_10_11 0x0f56 4932#define regCM1_CM_SHAPER_RAMA_REGION_10_11_BASE_IDX 2 4933#define regCM1_CM_SHAPER_RAMA_REGION_12_13 0x0f57 4934#define regCM1_CM_SHAPER_RAMA_REGION_12_13_BASE_IDX 2 4935#define regCM1_CM_SHAPER_RAMA_REGION_14_15 0x0f58 4936#define regCM1_CM_SHAPER_RAMA_REGION_14_15_BASE_IDX 2 4937#define regCM1_CM_SHAPER_RAMA_REGION_16_17 0x0f59 4938#define regCM1_CM_SHAPER_RAMA_REGION_16_17_BASE_IDX 2 4939#define regCM1_CM_SHAPER_RAMA_REGION_18_19 0x0f5a 4940#define regCM1_CM_SHAPER_RAMA_REGION_18_19_BASE_IDX 2 4941#define regCM1_CM_SHAPER_RAMA_REGION_20_21 0x0f5b 4942#define regCM1_CM_SHAPER_RAMA_REGION_20_21_BASE_IDX 2 4943#define regCM1_CM_SHAPER_RAMA_REGION_22_23 0x0f5c 4944#define regCM1_CM_SHAPER_RAMA_REGION_22_23_BASE_IDX 2 4945#define regCM1_CM_SHAPER_RAMA_REGION_24_25 0x0f5d 4946#define regCM1_CM_SHAPER_RAMA_REGION_24_25_BASE_IDX 2 4947#define regCM1_CM_SHAPER_RAMA_REGION_26_27 0x0f5e 4948#define regCM1_CM_SHAPER_RAMA_REGION_26_27_BASE_IDX 2 4949#define regCM1_CM_SHAPER_RAMA_REGION_28_29 0x0f5f 4950#define regCM1_CM_SHAPER_RAMA_REGION_28_29_BASE_IDX 2 4951#define regCM1_CM_SHAPER_RAMA_REGION_30_31 0x0f60 4952#define regCM1_CM_SHAPER_RAMA_REGION_30_31_BASE_IDX 2 4953#define regCM1_CM_SHAPER_RAMA_REGION_32_33 0x0f61 4954#define regCM1_CM_SHAPER_RAMA_REGION_32_33_BASE_IDX 2 4955#define regCM1_CM_SHAPER_RAMB_START_CNTL_B 0x0f62 4956#define regCM1_CM_SHAPER_RAMB_START_CNTL_B_BASE_IDX 2 4957#define regCM1_CM_SHAPER_RAMB_START_CNTL_G 0x0f63 4958#define regCM1_CM_SHAPER_RAMB_START_CNTL_G_BASE_IDX 2 4959#define regCM1_CM_SHAPER_RAMB_START_CNTL_R 0x0f64 4960#define regCM1_CM_SHAPER_RAMB_START_CNTL_R_BASE_IDX 2 4961#define regCM1_CM_SHAPER_RAMB_END_CNTL_B 0x0f65 4962#define regCM1_CM_SHAPER_RAMB_END_CNTL_B_BASE_IDX 2 4963#define regCM1_CM_SHAPER_RAMB_END_CNTL_G 0x0f66 4964#define regCM1_CM_SHAPER_RAMB_END_CNTL_G_BASE_IDX 2 4965#define regCM1_CM_SHAPER_RAMB_END_CNTL_R 0x0f67 4966#define regCM1_CM_SHAPER_RAMB_END_CNTL_R_BASE_IDX 2 4967#define regCM1_CM_SHAPER_RAMB_REGION_0_1 0x0f68 4968#define regCM1_CM_SHAPER_RAMB_REGION_0_1_BASE_IDX 2 4969#define regCM1_CM_SHAPER_RAMB_REGION_2_3 0x0f69 4970#define regCM1_CM_SHAPER_RAMB_REGION_2_3_BASE_IDX 2 4971#define regCM1_CM_SHAPER_RAMB_REGION_4_5 0x0f6a 4972#define regCM1_CM_SHAPER_RAMB_REGION_4_5_BASE_IDX 2 4973#define regCM1_CM_SHAPER_RAMB_REGION_6_7 0x0f6b 4974#define regCM1_CM_SHAPER_RAMB_REGION_6_7_BASE_IDX 2 4975#define regCM1_CM_SHAPER_RAMB_REGION_8_9 0x0f6c 4976#define regCM1_CM_SHAPER_RAMB_REGION_8_9_BASE_IDX 2 4977#define regCM1_CM_SHAPER_RAMB_REGION_10_11 0x0f6d 4978#define regCM1_CM_SHAPER_RAMB_REGION_10_11_BASE_IDX 2 4979#define regCM1_CM_SHAPER_RAMB_REGION_12_13 0x0f6e 4980#define regCM1_CM_SHAPER_RAMB_REGION_12_13_BASE_IDX 2 4981#define regCM1_CM_SHAPER_RAMB_REGION_14_15 0x0f6f 4982#define regCM1_CM_SHAPER_RAMB_REGION_14_15_BASE_IDX 2 4983#define regCM1_CM_SHAPER_RAMB_REGION_16_17 0x0f70 4984#define regCM1_CM_SHAPER_RAMB_REGION_16_17_BASE_IDX 2 4985#define regCM1_CM_SHAPER_RAMB_REGION_18_19 0x0f71 4986#define regCM1_CM_SHAPER_RAMB_REGION_18_19_BASE_IDX 2 4987#define regCM1_CM_SHAPER_RAMB_REGION_20_21 0x0f72 4988#define regCM1_CM_SHAPER_RAMB_REGION_20_21_BASE_IDX 2 4989#define regCM1_CM_SHAPER_RAMB_REGION_22_23 0x0f73 4990#define regCM1_CM_SHAPER_RAMB_REGION_22_23_BASE_IDX 2 4991#define regCM1_CM_SHAPER_RAMB_REGION_24_25 0x0f74 4992#define regCM1_CM_SHAPER_RAMB_REGION_24_25_BASE_IDX 2 4993#define regCM1_CM_SHAPER_RAMB_REGION_26_27 0x0f75 4994#define regCM1_CM_SHAPER_RAMB_REGION_26_27_BASE_IDX 2 4995#define regCM1_CM_SHAPER_RAMB_REGION_28_29 0x0f76 4996#define regCM1_CM_SHAPER_RAMB_REGION_28_29_BASE_IDX 2 4997#define regCM1_CM_SHAPER_RAMB_REGION_30_31 0x0f77 4998#define regCM1_CM_SHAPER_RAMB_REGION_30_31_BASE_IDX 2 4999#define regCM1_CM_SHAPER_RAMB_REGION_32_33 0x0f78 5000#define regCM1_CM_SHAPER_RAMB_REGION_32_33_BASE_IDX 2 5001#define regCM1_CM_MEM_PWR_CTRL2 0x0f79 5002#define regCM1_CM_MEM_PWR_CTRL2_BASE_IDX 2 5003#define regCM1_CM_MEM_PWR_STATUS2 0x0f7a 5004#define regCM1_CM_MEM_PWR_STATUS2_BASE_IDX 2 5005#define regCM1_CM_3DLUT_MODE 0x0f7b 5006#define regCM1_CM_3DLUT_MODE_BASE_IDX 2 5007#define regCM1_CM_3DLUT_INDEX 0x0f7c 5008#define regCM1_CM_3DLUT_INDEX_BASE_IDX 2 5009#define regCM1_CM_3DLUT_DATA 0x0f7d 5010#define regCM1_CM_3DLUT_DATA_BASE_IDX 2 5011#define regCM1_CM_3DLUT_DATA_30BIT 0x0f7e 5012#define regCM1_CM_3DLUT_DATA_30BIT_BASE_IDX 2 5013#define regCM1_CM_3DLUT_READ_WRITE_CONTROL 0x0f7f 5014#define regCM1_CM_3DLUT_READ_WRITE_CONTROL_BASE_IDX 2 5015#define regCM1_CM_3DLUT_OUT_NORM_FACTOR 0x0f80 5016#define regCM1_CM_3DLUT_OUT_NORM_FACTOR_BASE_IDX 2 5017#define regCM1_CM_3DLUT_OUT_OFFSET_R 0x0f81 5018#define regCM1_CM_3DLUT_OUT_OFFSET_R_BASE_IDX 2 5019#define regCM1_CM_3DLUT_OUT_OFFSET_G 0x0f82 5020#define regCM1_CM_3DLUT_OUT_OFFSET_G_BASE_IDX 2 5021#define regCM1_CM_3DLUT_OUT_OFFSET_B 0x0f83 5022#define regCM1_CM_3DLUT_OUT_OFFSET_B_BASE_IDX 2 5023#define regCM1_CM_TEST_DEBUG_INDEX 0x0f84 5024#define regCM1_CM_TEST_DEBUG_INDEX_BASE_IDX 2 5025#define regCM1_CM_TEST_DEBUG_DATA 0x0f85 5026#define regCM1_CM_TEST_DEBUG_DATA_BASE_IDX 2 5027 5028 5029// addressBlock: dce_dc_dpp1_dispdec_dpp_top_dispdec 5030// base address: 0x5ac 5031#define regDPP_TOP1_DPP_CONTROL 0x0e30 5032#define regDPP_TOP1_DPP_CONTROL_BASE_IDX 2 5033#define regDPP_TOP1_DPP_SOFT_RESET 0x0e31 5034#define regDPP_TOP1_DPP_SOFT_RESET_BASE_IDX 2 5035#define regDPP_TOP1_DPP_CRC_VAL_R_G 0x0e32 5036#define regDPP_TOP1_DPP_CRC_VAL_R_G_BASE_IDX 2 5037#define regDPP_TOP1_DPP_CRC_VAL_B_A 0x0e33 5038#define regDPP_TOP1_DPP_CRC_VAL_B_A_BASE_IDX 2 5039#define regDPP_TOP1_DPP_CRC_CTRL 0x0e34 5040#define regDPP_TOP1_DPP_CRC_CTRL_BASE_IDX 2 5041#define regDPP_TOP1_HOST_READ_CONTROL 0x0e35 5042#define regDPP_TOP1_HOST_READ_CONTROL_BASE_IDX 2 5043 5044 5045// addressBlock: dce_dc_dpp1_dispdec_dpp_dcperfmon_dc_perfmon_dispdec 5046// base address: 0x3e3c 5047#define regDC_PERFMON12_PERFCOUNTER_CNTL 0x0f8f 5048#define regDC_PERFMON12_PERFCOUNTER_CNTL_BASE_IDX 2 5049#define regDC_PERFMON12_PERFCOUNTER_CNTL2 0x0f90 5050#define regDC_PERFMON12_PERFCOUNTER_CNTL2_BASE_IDX 2 5051#define regDC_PERFMON12_PERFCOUNTER_STATE 0x0f91 5052#define regDC_PERFMON12_PERFCOUNTER_STATE_BASE_IDX 2 5053#define regDC_PERFMON12_PERFMON_CNTL 0x0f92 5054#define regDC_PERFMON12_PERFMON_CNTL_BASE_IDX 2 5055#define regDC_PERFMON12_PERFMON_CNTL2 0x0f93 5056#define regDC_PERFMON12_PERFMON_CNTL2_BASE_IDX 2 5057#define regDC_PERFMON12_PERFMON_CVALUE_INT_MISC 0x0f94 5058#define regDC_PERFMON12_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 5059#define regDC_PERFMON12_PERFMON_CVALUE_LOW 0x0f95 5060#define regDC_PERFMON12_PERFMON_CVALUE_LOW_BASE_IDX 2 5061#define regDC_PERFMON12_PERFMON_HI 0x0f96 5062#define regDC_PERFMON12_PERFMON_HI_BASE_IDX 2 5063#define regDC_PERFMON12_PERFMON_LOW 0x0f97 5064#define regDC_PERFMON12_PERFMON_LOW_BASE_IDX 2 5065 5066 5067// addressBlock: dce_dc_dpp2_dispdec_cnvc_cfg_dispdec 5068// base address: 0xb58 5069#define regCNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT 0x0fa5 5070#define regCNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX 2 5071#define regCNVC_CFG2_FORMAT_CONTROL 0x0fa6 5072#define regCNVC_CFG2_FORMAT_CONTROL_BASE_IDX 2 5073#define regCNVC_CFG2_FCNV_FP_BIAS_R 0x0fa7 5074#define regCNVC_CFG2_FCNV_FP_BIAS_R_BASE_IDX 2 5075#define regCNVC_CFG2_FCNV_FP_BIAS_G 0x0fa8 5076#define regCNVC_CFG2_FCNV_FP_BIAS_G_BASE_IDX 2 5077#define regCNVC_CFG2_FCNV_FP_BIAS_B 0x0fa9 5078#define regCNVC_CFG2_FCNV_FP_BIAS_B_BASE_IDX 2 5079#define regCNVC_CFG2_FCNV_FP_SCALE_R 0x0faa 5080#define regCNVC_CFG2_FCNV_FP_SCALE_R_BASE_IDX 2 5081#define regCNVC_CFG2_FCNV_FP_SCALE_G 0x0fab 5082#define regCNVC_CFG2_FCNV_FP_SCALE_G_BASE_IDX 2 5083#define regCNVC_CFG2_FCNV_FP_SCALE_B 0x0fac 5084#define regCNVC_CFG2_FCNV_FP_SCALE_B_BASE_IDX 2 5085#define regCNVC_CFG2_COLOR_KEYER_CONTROL 0x0fad 5086#define regCNVC_CFG2_COLOR_KEYER_CONTROL_BASE_IDX 2 5087#define regCNVC_CFG2_COLOR_KEYER_ALPHA 0x0fae 5088#define regCNVC_CFG2_COLOR_KEYER_ALPHA_BASE_IDX 2 5089#define regCNVC_CFG2_COLOR_KEYER_RED 0x0faf 5090#define regCNVC_CFG2_COLOR_KEYER_RED_BASE_IDX 2 5091#define regCNVC_CFG2_COLOR_KEYER_GREEN 0x0fb0 5092#define regCNVC_CFG2_COLOR_KEYER_GREEN_BASE_IDX 2 5093#define regCNVC_CFG2_COLOR_KEYER_BLUE 0x0fb1 5094#define regCNVC_CFG2_COLOR_KEYER_BLUE_BASE_IDX 2 5095#define regCNVC_CFG2_ALPHA_2BIT_LUT 0x0fb3 5096#define regCNVC_CFG2_ALPHA_2BIT_LUT_BASE_IDX 2 5097#define regCNVC_CFG2_PRE_DEALPHA 0x0fb4 5098#define regCNVC_CFG2_PRE_DEALPHA_BASE_IDX 2 5099#define regCNVC_CFG2_PRE_CSC_MODE 0x0fb5 5100#define regCNVC_CFG2_PRE_CSC_MODE_BASE_IDX 2 5101#define regCNVC_CFG2_PRE_CSC_C11_C12 0x0fb6 5102#define regCNVC_CFG2_PRE_CSC_C11_C12_BASE_IDX 2 5103#define regCNVC_CFG2_PRE_CSC_C13_C14 0x0fb7 5104#define regCNVC_CFG2_PRE_CSC_C13_C14_BASE_IDX 2 5105#define regCNVC_CFG2_PRE_CSC_C21_C22 0x0fb8 5106#define regCNVC_CFG2_PRE_CSC_C21_C22_BASE_IDX 2 5107#define regCNVC_CFG2_PRE_CSC_C23_C24 0x0fb9 5108#define regCNVC_CFG2_PRE_CSC_C23_C24_BASE_IDX 2 5109#define regCNVC_CFG2_PRE_CSC_C31_C32 0x0fba 5110#define regCNVC_CFG2_PRE_CSC_C31_C32_BASE_IDX 2 5111#define regCNVC_CFG2_PRE_CSC_C33_C34 0x0fbb 5112#define regCNVC_CFG2_PRE_CSC_C33_C34_BASE_IDX 2 5113#define regCNVC_CFG2_PRE_CSC_B_C11_C12 0x0fbc 5114#define regCNVC_CFG2_PRE_CSC_B_C11_C12_BASE_IDX 2 5115#define regCNVC_CFG2_PRE_CSC_B_C13_C14 0x0fbd 5116#define regCNVC_CFG2_PRE_CSC_B_C13_C14_BASE_IDX 2 5117#define regCNVC_CFG2_PRE_CSC_B_C21_C22 0x0fbe 5118#define regCNVC_CFG2_PRE_CSC_B_C21_C22_BASE_IDX 2 5119#define regCNVC_CFG2_PRE_CSC_B_C23_C24 0x0fbf 5120#define regCNVC_CFG2_PRE_CSC_B_C23_C24_BASE_IDX 2 5121#define regCNVC_CFG2_PRE_CSC_B_C31_C32 0x0fc0 5122#define regCNVC_CFG2_PRE_CSC_B_C31_C32_BASE_IDX 2 5123#define regCNVC_CFG2_PRE_CSC_B_C33_C34 0x0fc1 5124#define regCNVC_CFG2_PRE_CSC_B_C33_C34_BASE_IDX 2 5125#define regCNVC_CFG2_CNVC_COEF_FORMAT 0x0fc2 5126#define regCNVC_CFG2_CNVC_COEF_FORMAT_BASE_IDX 2 5127#define regCNVC_CFG2_PRE_DEGAM 0x0fc3 5128#define regCNVC_CFG2_PRE_DEGAM_BASE_IDX 2 5129#define regCNVC_CFG2_PRE_REALPHA 0x0fc4 5130#define regCNVC_CFG2_PRE_REALPHA_BASE_IDX 2 5131 5132 5133// addressBlock: dce_dc_dpp2_dispdec_cnvc_cur_dispdec 5134// base address: 0xb58 5135#define regCNVC_CUR2_CURSOR0_CONTROL 0x0fc7 5136#define regCNVC_CUR2_CURSOR0_CONTROL_BASE_IDX 2 5137#define regCNVC_CUR2_CURSOR0_COLOR0 0x0fc8 5138#define regCNVC_CUR2_CURSOR0_COLOR0_BASE_IDX 2 5139#define regCNVC_CUR2_CURSOR0_COLOR1 0x0fc9 5140#define regCNVC_CUR2_CURSOR0_COLOR1_BASE_IDX 2 5141#define regCNVC_CUR2_CURSOR0_FP_SCALE_BIAS 0x0fca 5142#define regCNVC_CUR2_CURSOR0_FP_SCALE_BIAS_BASE_IDX 2 5143 5144 5145// addressBlock: dce_dc_dpp2_dispdec_dscl_dispdec 5146// base address: 0xb58 5147#define regDSCL2_SCL_COEF_RAM_TAP_SELECT 0x0fcf 5148#define regDSCL2_SCL_COEF_RAM_TAP_SELECT_BASE_IDX 2 5149#define regDSCL2_SCL_COEF_RAM_TAP_DATA 0x0fd0 5150#define regDSCL2_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2 5151#define regDSCL2_SCL_MODE 0x0fd1 5152#define regDSCL2_SCL_MODE_BASE_IDX 2 5153#define regDSCL2_SCL_TAP_CONTROL 0x0fd2 5154#define regDSCL2_SCL_TAP_CONTROL_BASE_IDX 2 5155#define regDSCL2_DSCL_CONTROL 0x0fd3 5156#define regDSCL2_DSCL_CONTROL_BASE_IDX 2 5157#define regDSCL2_DSCL_2TAP_CONTROL 0x0fd4 5158#define regDSCL2_DSCL_2TAP_CONTROL_BASE_IDX 2 5159#define regDSCL2_SCL_MANUAL_REPLICATE_CONTROL 0x0fd5 5160#define regDSCL2_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2 5161#define regDSCL2_SCL_HORZ_FILTER_SCALE_RATIO 0x0fd6 5162#define regDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2 5163#define regDSCL2_SCL_HORZ_FILTER_INIT 0x0fd7 5164#define regDSCL2_SCL_HORZ_FILTER_INIT_BASE_IDX 2 5165#define regDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C 0x0fd8 5166#define regDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX 2 5167#define regDSCL2_SCL_HORZ_FILTER_INIT_C 0x0fd9 5168#define regDSCL2_SCL_HORZ_FILTER_INIT_C_BASE_IDX 2 5169#define regDSCL2_SCL_VERT_FILTER_SCALE_RATIO 0x0fda 5170#define regDSCL2_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2 5171#define regDSCL2_SCL_VERT_FILTER_INIT 0x0fdb 5172#define regDSCL2_SCL_VERT_FILTER_INIT_BASE_IDX 2 5173#define regDSCL2_SCL_VERT_FILTER_INIT_BOT 0x0fdc 5174#define regDSCL2_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2 5175#define regDSCL2_SCL_VERT_FILTER_SCALE_RATIO_C 0x0fdd 5176#define regDSCL2_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX 2 5177#define regDSCL2_SCL_VERT_FILTER_INIT_C 0x0fde 5178#define regDSCL2_SCL_VERT_FILTER_INIT_C_BASE_IDX 2 5179#define regDSCL2_SCL_VERT_FILTER_INIT_BOT_C 0x0fdf 5180#define regDSCL2_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX 2 5181#define regDSCL2_SCL_BLACK_COLOR 0x0fe0 5182#define regDSCL2_SCL_BLACK_COLOR_BASE_IDX 2 5183#define regDSCL2_DSCL_UPDATE 0x0fe1 5184#define regDSCL2_DSCL_UPDATE_BASE_IDX 2 5185#define regDSCL2_DSCL_AUTOCAL 0x0fe2 5186#define regDSCL2_DSCL_AUTOCAL_BASE_IDX 2 5187#define regDSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT 0x0fe3 5188#define regDSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2 5189#define regDSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM 0x0fe4 5190#define regDSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2 5191#define regDSCL2_OTG_H_BLANK 0x0fe5 5192#define regDSCL2_OTG_H_BLANK_BASE_IDX 2 5193#define regDSCL2_OTG_V_BLANK 0x0fe6 5194#define regDSCL2_OTG_V_BLANK_BASE_IDX 2 5195#define regDSCL2_RECOUT_START 0x0fe7 5196#define regDSCL2_RECOUT_START_BASE_IDX 2 5197#define regDSCL2_RECOUT_SIZE 0x0fe8 5198#define regDSCL2_RECOUT_SIZE_BASE_IDX 2 5199#define regDSCL2_MPC_SIZE 0x0fe9 5200#define regDSCL2_MPC_SIZE_BASE_IDX 2 5201#define regDSCL2_LB_DATA_FORMAT 0x0fea 5202#define regDSCL2_LB_DATA_FORMAT_BASE_IDX 2 5203#define regDSCL2_LB_MEMORY_CTRL 0x0feb 5204#define regDSCL2_LB_MEMORY_CTRL_BASE_IDX 2 5205#define regDSCL2_LB_V_COUNTER 0x0fec 5206#define regDSCL2_LB_V_COUNTER_BASE_IDX 2 5207#define regDSCL2_DSCL_MEM_PWR_CTRL 0x0fed 5208#define regDSCL2_DSCL_MEM_PWR_CTRL_BASE_IDX 2 5209#define regDSCL2_DSCL_MEM_PWR_STATUS 0x0fee 5210#define regDSCL2_DSCL_MEM_PWR_STATUS_BASE_IDX 2 5211#define regDSCL2_OBUF_CONTROL 0x0fef 5212#define regDSCL2_OBUF_CONTROL_BASE_IDX 2 5213#define regDSCL2_OBUF_MEM_PWR_CTRL 0x0ff0 5214#define regDSCL2_OBUF_MEM_PWR_CTRL_BASE_IDX 2 5215 5216 5217// addressBlock: dce_dc_dpp2_dispdec_cm_dispdec 5218// base address: 0xb58 5219#define regCM2_CM_CONTROL 0x0ff6 5220#define regCM2_CM_CONTROL_BASE_IDX 2 5221#define regCM2_CM_POST_CSC_CONTROL 0x0ff7 5222#define regCM2_CM_POST_CSC_CONTROL_BASE_IDX 2 5223#define regCM2_CM_POST_CSC_C11_C12 0x0ff8 5224#define regCM2_CM_POST_CSC_C11_C12_BASE_IDX 2 5225#define regCM2_CM_POST_CSC_C13_C14 0x0ff9 5226#define regCM2_CM_POST_CSC_C13_C14_BASE_IDX 2 5227#define regCM2_CM_POST_CSC_C21_C22 0x0ffa 5228#define regCM2_CM_POST_CSC_C21_C22_BASE_IDX 2 5229#define regCM2_CM_POST_CSC_C23_C24 0x0ffb 5230#define regCM2_CM_POST_CSC_C23_C24_BASE_IDX 2 5231#define regCM2_CM_POST_CSC_C31_C32 0x0ffc 5232#define regCM2_CM_POST_CSC_C31_C32_BASE_IDX 2 5233#define regCM2_CM_POST_CSC_C33_C34 0x0ffd 5234#define regCM2_CM_POST_CSC_C33_C34_BASE_IDX 2 5235#define regCM2_CM_POST_CSC_B_C11_C12 0x0ffe 5236#define regCM2_CM_POST_CSC_B_C11_C12_BASE_IDX 2 5237#define regCM2_CM_POST_CSC_B_C13_C14 0x0fff 5238#define regCM2_CM_POST_CSC_B_C13_C14_BASE_IDX 2 5239#define regCM2_CM_POST_CSC_B_C21_C22 0x1000 5240#define regCM2_CM_POST_CSC_B_C21_C22_BASE_IDX 2 5241#define regCM2_CM_POST_CSC_B_C23_C24 0x1001 5242#define regCM2_CM_POST_CSC_B_C23_C24_BASE_IDX 2 5243#define regCM2_CM_POST_CSC_B_C31_C32 0x1002 5244#define regCM2_CM_POST_CSC_B_C31_C32_BASE_IDX 2 5245#define regCM2_CM_POST_CSC_B_C33_C34 0x1003 5246#define regCM2_CM_POST_CSC_B_C33_C34_BASE_IDX 2 5247#define regCM2_CM_GAMUT_REMAP_CONTROL 0x1004 5248#define regCM2_CM_GAMUT_REMAP_CONTROL_BASE_IDX 2 5249#define regCM2_CM_GAMUT_REMAP_C11_C12 0x1005 5250#define regCM2_CM_GAMUT_REMAP_C11_C12_BASE_IDX 2 5251#define regCM2_CM_GAMUT_REMAP_C13_C14 0x1006 5252#define regCM2_CM_GAMUT_REMAP_C13_C14_BASE_IDX 2 5253#define regCM2_CM_GAMUT_REMAP_C21_C22 0x1007 5254#define regCM2_CM_GAMUT_REMAP_C21_C22_BASE_IDX 2 5255#define regCM2_CM_GAMUT_REMAP_C23_C24 0x1008 5256#define regCM2_CM_GAMUT_REMAP_C23_C24_BASE_IDX 2 5257#define regCM2_CM_GAMUT_REMAP_C31_C32 0x1009 5258#define regCM2_CM_GAMUT_REMAP_C31_C32_BASE_IDX 2 5259#define regCM2_CM_GAMUT_REMAP_C33_C34 0x100a 5260#define regCM2_CM_GAMUT_REMAP_C33_C34_BASE_IDX 2 5261#define regCM2_CM_GAMUT_REMAP_B_C11_C12 0x100b 5262#define regCM2_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX 2 5263#define regCM2_CM_GAMUT_REMAP_B_C13_C14 0x100c 5264#define regCM2_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX 2 5265#define regCM2_CM_GAMUT_REMAP_B_C21_C22 0x100d 5266#define regCM2_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX 2 5267#define regCM2_CM_GAMUT_REMAP_B_C23_C24 0x100e 5268#define regCM2_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX 2 5269#define regCM2_CM_GAMUT_REMAP_B_C31_C32 0x100f 5270#define regCM2_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX 2 5271#define regCM2_CM_GAMUT_REMAP_B_C33_C34 0x1010 5272#define regCM2_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX 2 5273#define regCM2_CM_BIAS_CR_R 0x1011 5274#define regCM2_CM_BIAS_CR_R_BASE_IDX 2 5275#define regCM2_CM_BIAS_Y_G_CB_B 0x1012 5276#define regCM2_CM_BIAS_Y_G_CB_B_BASE_IDX 2 5277#define regCM2_CM_GAMCOR_CONTROL 0x1013 5278#define regCM2_CM_GAMCOR_CONTROL_BASE_IDX 2 5279#define regCM2_CM_GAMCOR_LUT_INDEX 0x1014 5280#define regCM2_CM_GAMCOR_LUT_INDEX_BASE_IDX 2 5281#define regCM2_CM_GAMCOR_LUT_DATA 0x1015 5282#define regCM2_CM_GAMCOR_LUT_DATA_BASE_IDX 2 5283#define regCM2_CM_GAMCOR_LUT_CONTROL 0x1016 5284#define regCM2_CM_GAMCOR_LUT_CONTROL_BASE_IDX 2 5285#define regCM2_CM_GAMCOR_RAMA_START_CNTL_B 0x1017 5286#define regCM2_CM_GAMCOR_RAMA_START_CNTL_B_BASE_IDX 2 5287#define regCM2_CM_GAMCOR_RAMA_START_CNTL_G 0x1018 5288#define regCM2_CM_GAMCOR_RAMA_START_CNTL_G_BASE_IDX 2 5289#define regCM2_CM_GAMCOR_RAMA_START_CNTL_R 0x1019 5290#define regCM2_CM_GAMCOR_RAMA_START_CNTL_R_BASE_IDX 2 5291#define regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B 0x101a 5292#define regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B_BASE_IDX 2 5293#define regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G 0x101b 5294#define regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2 5295#define regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R 0x101c 5296#define regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R_BASE_IDX 2 5297#define regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_B 0x101d 5298#define regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_B_BASE_IDX 2 5299#define regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_G 0x101e 5300#define regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_G_BASE_IDX 2 5301#define regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_R 0x101f 5302#define regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_R_BASE_IDX 2 5303#define regCM2_CM_GAMCOR_RAMA_END_CNTL1_B 0x1020 5304#define regCM2_CM_GAMCOR_RAMA_END_CNTL1_B_BASE_IDX 2 5305#define regCM2_CM_GAMCOR_RAMA_END_CNTL2_B 0x1021 5306#define regCM2_CM_GAMCOR_RAMA_END_CNTL2_B_BASE_IDX 2 5307#define regCM2_CM_GAMCOR_RAMA_END_CNTL1_G 0x1022 5308#define regCM2_CM_GAMCOR_RAMA_END_CNTL1_G_BASE_IDX 2 5309#define regCM2_CM_GAMCOR_RAMA_END_CNTL2_G 0x1023 5310#define regCM2_CM_GAMCOR_RAMA_END_CNTL2_G_BASE_IDX 2 5311#define regCM2_CM_GAMCOR_RAMA_END_CNTL1_R 0x1024 5312#define regCM2_CM_GAMCOR_RAMA_END_CNTL1_R_BASE_IDX 2 5313#define regCM2_CM_GAMCOR_RAMA_END_CNTL2_R 0x1025 5314#define regCM2_CM_GAMCOR_RAMA_END_CNTL2_R_BASE_IDX 2 5315#define regCM2_CM_GAMCOR_RAMA_OFFSET_B 0x1026 5316#define regCM2_CM_GAMCOR_RAMA_OFFSET_B_BASE_IDX 2 5317#define regCM2_CM_GAMCOR_RAMA_OFFSET_G 0x1027 5318#define regCM2_CM_GAMCOR_RAMA_OFFSET_G_BASE_IDX 2 5319#define regCM2_CM_GAMCOR_RAMA_OFFSET_R 0x1028 5320#define regCM2_CM_GAMCOR_RAMA_OFFSET_R_BASE_IDX 2 5321#define regCM2_CM_GAMCOR_RAMA_REGION_0_1 0x1029 5322#define regCM2_CM_GAMCOR_RAMA_REGION_0_1_BASE_IDX 2 5323#define regCM2_CM_GAMCOR_RAMA_REGION_2_3 0x102a 5324#define regCM2_CM_GAMCOR_RAMA_REGION_2_3_BASE_IDX 2 5325#define regCM2_CM_GAMCOR_RAMA_REGION_4_5 0x102b 5326#define regCM2_CM_GAMCOR_RAMA_REGION_4_5_BASE_IDX 2 5327#define regCM2_CM_GAMCOR_RAMA_REGION_6_7 0x102c 5328#define regCM2_CM_GAMCOR_RAMA_REGION_6_7_BASE_IDX 2 5329#define regCM2_CM_GAMCOR_RAMA_REGION_8_9 0x102d 5330#define regCM2_CM_GAMCOR_RAMA_REGION_8_9_BASE_IDX 2 5331#define regCM2_CM_GAMCOR_RAMA_REGION_10_11 0x102e 5332#define regCM2_CM_GAMCOR_RAMA_REGION_10_11_BASE_IDX 2 5333#define regCM2_CM_GAMCOR_RAMA_REGION_12_13 0x102f 5334#define regCM2_CM_GAMCOR_RAMA_REGION_12_13_BASE_IDX 2 5335#define regCM2_CM_GAMCOR_RAMA_REGION_14_15 0x1030 5336#define regCM2_CM_GAMCOR_RAMA_REGION_14_15_BASE_IDX 2 5337#define regCM2_CM_GAMCOR_RAMA_REGION_16_17 0x1031 5338#define regCM2_CM_GAMCOR_RAMA_REGION_16_17_BASE_IDX 2 5339#define regCM2_CM_GAMCOR_RAMA_REGION_18_19 0x1032 5340#define regCM2_CM_GAMCOR_RAMA_REGION_18_19_BASE_IDX 2 5341#define regCM2_CM_GAMCOR_RAMA_REGION_20_21 0x1033 5342#define regCM2_CM_GAMCOR_RAMA_REGION_20_21_BASE_IDX 2 5343#define regCM2_CM_GAMCOR_RAMA_REGION_22_23 0x1034 5344#define regCM2_CM_GAMCOR_RAMA_REGION_22_23_BASE_IDX 2 5345#define regCM2_CM_GAMCOR_RAMA_REGION_24_25 0x1035 5346#define regCM2_CM_GAMCOR_RAMA_REGION_24_25_BASE_IDX 2 5347#define regCM2_CM_GAMCOR_RAMA_REGION_26_27 0x1036 5348#define regCM2_CM_GAMCOR_RAMA_REGION_26_27_BASE_IDX 2 5349#define regCM2_CM_GAMCOR_RAMA_REGION_28_29 0x1037 5350#define regCM2_CM_GAMCOR_RAMA_REGION_28_29_BASE_IDX 2 5351#define regCM2_CM_GAMCOR_RAMA_REGION_30_31 0x1038 5352#define regCM2_CM_GAMCOR_RAMA_REGION_30_31_BASE_IDX 2 5353#define regCM2_CM_GAMCOR_RAMA_REGION_32_33 0x1039 5354#define regCM2_CM_GAMCOR_RAMA_REGION_32_33_BASE_IDX 2 5355#define regCM2_CM_GAMCOR_RAMB_START_CNTL_B 0x103a 5356#define regCM2_CM_GAMCOR_RAMB_START_CNTL_B_BASE_IDX 2 5357#define regCM2_CM_GAMCOR_RAMB_START_CNTL_G 0x103b 5358#define regCM2_CM_GAMCOR_RAMB_START_CNTL_G_BASE_IDX 2 5359#define regCM2_CM_GAMCOR_RAMB_START_CNTL_R 0x103c 5360#define regCM2_CM_GAMCOR_RAMB_START_CNTL_R_BASE_IDX 2 5361#define regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B 0x103d 5362#define regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B_BASE_IDX 2 5363#define regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G 0x103e 5364#define regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G_BASE_IDX 2 5365#define regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R 0x103f 5366#define regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R_BASE_IDX 2 5367#define regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_B 0x1040 5368#define regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_B_BASE_IDX 2 5369#define regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_G 0x1041 5370#define regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_G_BASE_IDX 2 5371#define regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_R 0x1042 5372#define regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_R_BASE_IDX 2 5373#define regCM2_CM_GAMCOR_RAMB_END_CNTL1_B 0x1043 5374#define regCM2_CM_GAMCOR_RAMB_END_CNTL1_B_BASE_IDX 2 5375#define regCM2_CM_GAMCOR_RAMB_END_CNTL2_B 0x1044 5376#define regCM2_CM_GAMCOR_RAMB_END_CNTL2_B_BASE_IDX 2 5377#define regCM2_CM_GAMCOR_RAMB_END_CNTL1_G 0x1045 5378#define regCM2_CM_GAMCOR_RAMB_END_CNTL1_G_BASE_IDX 2 5379#define regCM2_CM_GAMCOR_RAMB_END_CNTL2_G 0x1046 5380#define regCM2_CM_GAMCOR_RAMB_END_CNTL2_G_BASE_IDX 2 5381#define regCM2_CM_GAMCOR_RAMB_END_CNTL1_R 0x1047 5382#define regCM2_CM_GAMCOR_RAMB_END_CNTL1_R_BASE_IDX 2 5383#define regCM2_CM_GAMCOR_RAMB_END_CNTL2_R 0x1048 5384#define regCM2_CM_GAMCOR_RAMB_END_CNTL2_R_BASE_IDX 2 5385#define regCM2_CM_GAMCOR_RAMB_OFFSET_B 0x1049 5386#define regCM2_CM_GAMCOR_RAMB_OFFSET_B_BASE_IDX 2 5387#define regCM2_CM_GAMCOR_RAMB_OFFSET_G 0x104a 5388#define regCM2_CM_GAMCOR_RAMB_OFFSET_G_BASE_IDX 2 5389#define regCM2_CM_GAMCOR_RAMB_OFFSET_R 0x104b 5390#define regCM2_CM_GAMCOR_RAMB_OFFSET_R_BASE_IDX 2 5391#define regCM2_CM_GAMCOR_RAMB_REGION_0_1 0x104c 5392#define regCM2_CM_GAMCOR_RAMB_REGION_0_1_BASE_IDX 2 5393#define regCM2_CM_GAMCOR_RAMB_REGION_2_3 0x104d 5394#define regCM2_CM_GAMCOR_RAMB_REGION_2_3_BASE_IDX 2 5395#define regCM2_CM_GAMCOR_RAMB_REGION_4_5 0x104e 5396#define regCM2_CM_GAMCOR_RAMB_REGION_4_5_BASE_IDX 2 5397#define regCM2_CM_GAMCOR_RAMB_REGION_6_7 0x104f 5398#define regCM2_CM_GAMCOR_RAMB_REGION_6_7_BASE_IDX 2 5399#define regCM2_CM_GAMCOR_RAMB_REGION_8_9 0x1050 5400#define regCM2_CM_GAMCOR_RAMB_REGION_8_9_BASE_IDX 2 5401#define regCM2_CM_GAMCOR_RAMB_REGION_10_11 0x1051 5402#define regCM2_CM_GAMCOR_RAMB_REGION_10_11_BASE_IDX 2 5403#define regCM2_CM_GAMCOR_RAMB_REGION_12_13 0x1052 5404#define regCM2_CM_GAMCOR_RAMB_REGION_12_13_BASE_IDX 2 5405#define regCM2_CM_GAMCOR_RAMB_REGION_14_15 0x1053 5406#define regCM2_CM_GAMCOR_RAMB_REGION_14_15_BASE_IDX 2 5407#define regCM2_CM_GAMCOR_RAMB_REGION_16_17 0x1054 5408#define regCM2_CM_GAMCOR_RAMB_REGION_16_17_BASE_IDX 2 5409#define regCM2_CM_GAMCOR_RAMB_REGION_18_19 0x1055 5410#define regCM2_CM_GAMCOR_RAMB_REGION_18_19_BASE_IDX 2 5411#define regCM2_CM_GAMCOR_RAMB_REGION_20_21 0x1056 5412#define regCM2_CM_GAMCOR_RAMB_REGION_20_21_BASE_IDX 2 5413#define regCM2_CM_GAMCOR_RAMB_REGION_22_23 0x1057 5414#define regCM2_CM_GAMCOR_RAMB_REGION_22_23_BASE_IDX 2 5415#define regCM2_CM_GAMCOR_RAMB_REGION_24_25 0x1058 5416#define regCM2_CM_GAMCOR_RAMB_REGION_24_25_BASE_IDX 2 5417#define regCM2_CM_GAMCOR_RAMB_REGION_26_27 0x1059 5418#define regCM2_CM_GAMCOR_RAMB_REGION_26_27_BASE_IDX 2 5419#define regCM2_CM_GAMCOR_RAMB_REGION_28_29 0x105a 5420#define regCM2_CM_GAMCOR_RAMB_REGION_28_29_BASE_IDX 2 5421#define regCM2_CM_GAMCOR_RAMB_REGION_30_31 0x105b 5422#define regCM2_CM_GAMCOR_RAMB_REGION_30_31_BASE_IDX 2 5423#define regCM2_CM_GAMCOR_RAMB_REGION_32_33 0x105c 5424#define regCM2_CM_GAMCOR_RAMB_REGION_32_33_BASE_IDX 2 5425#define regCM2_CM_BLNDGAM_CONTROL 0x105d 5426#define regCM2_CM_BLNDGAM_CONTROL_BASE_IDX 2 5427#define regCM2_CM_BLNDGAM_LUT_INDEX 0x105e 5428#define regCM2_CM_BLNDGAM_LUT_INDEX_BASE_IDX 2 5429#define regCM2_CM_BLNDGAM_LUT_DATA 0x105f 5430#define regCM2_CM_BLNDGAM_LUT_DATA_BASE_IDX 2 5431#define regCM2_CM_BLNDGAM_LUT_CONTROL 0x1060 5432#define regCM2_CM_BLNDGAM_LUT_CONTROL_BASE_IDX 2 5433#define regCM2_CM_BLNDGAM_RAMA_START_CNTL_B 0x1061 5434#define regCM2_CM_BLNDGAM_RAMA_START_CNTL_B_BASE_IDX 2 5435#define regCM2_CM_BLNDGAM_RAMA_START_CNTL_G 0x1062 5436#define regCM2_CM_BLNDGAM_RAMA_START_CNTL_G_BASE_IDX 2 5437#define regCM2_CM_BLNDGAM_RAMA_START_CNTL_R 0x1063 5438#define regCM2_CM_BLNDGAM_RAMA_START_CNTL_R_BASE_IDX 2 5439#define regCM2_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B 0x1064 5440#define regCM2_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX 2 5441#define regCM2_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G 0x1065 5442#define regCM2_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2 5443#define regCM2_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R 0x1066 5444#define regCM2_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX 2 5445#define regCM2_CM_BLNDGAM_RAMA_START_BASE_CNTL_B 0x1067 5446#define regCM2_CM_BLNDGAM_RAMA_START_BASE_CNTL_B_BASE_IDX 2 5447#define regCM2_CM_BLNDGAM_RAMA_START_BASE_CNTL_G 0x1068 5448#define regCM2_CM_BLNDGAM_RAMA_START_BASE_CNTL_G_BASE_IDX 2 5449#define regCM2_CM_BLNDGAM_RAMA_START_BASE_CNTL_R 0x1069 5450#define regCM2_CM_BLNDGAM_RAMA_START_BASE_CNTL_R_BASE_IDX 2 5451#define regCM2_CM_BLNDGAM_RAMA_END_CNTL1_B 0x106a 5452#define regCM2_CM_BLNDGAM_RAMA_END_CNTL1_B_BASE_IDX 2 5453#define regCM2_CM_BLNDGAM_RAMA_END_CNTL2_B 0x106b 5454#define regCM2_CM_BLNDGAM_RAMA_END_CNTL2_B_BASE_IDX 2 5455#define regCM2_CM_BLNDGAM_RAMA_END_CNTL1_G 0x106c 5456#define regCM2_CM_BLNDGAM_RAMA_END_CNTL1_G_BASE_IDX 2 5457#define regCM2_CM_BLNDGAM_RAMA_END_CNTL2_G 0x106d 5458#define regCM2_CM_BLNDGAM_RAMA_END_CNTL2_G_BASE_IDX 2 5459#define regCM2_CM_BLNDGAM_RAMA_END_CNTL1_R 0x106e 5460#define regCM2_CM_BLNDGAM_RAMA_END_CNTL1_R_BASE_IDX 2 5461#define regCM2_CM_BLNDGAM_RAMA_END_CNTL2_R 0x106f 5462#define regCM2_CM_BLNDGAM_RAMA_END_CNTL2_R_BASE_IDX 2 5463#define regCM2_CM_BLNDGAM_RAMA_OFFSET_B 0x1070 5464#define regCM2_CM_BLNDGAM_RAMA_OFFSET_B_BASE_IDX 2 5465#define regCM2_CM_BLNDGAM_RAMA_OFFSET_G 0x1071 5466#define regCM2_CM_BLNDGAM_RAMA_OFFSET_G_BASE_IDX 2 5467#define regCM2_CM_BLNDGAM_RAMA_OFFSET_R 0x1072 5468#define regCM2_CM_BLNDGAM_RAMA_OFFSET_R_BASE_IDX 2 5469#define regCM2_CM_BLNDGAM_RAMA_REGION_0_1 0x1073 5470#define regCM2_CM_BLNDGAM_RAMA_REGION_0_1_BASE_IDX 2 5471#define regCM2_CM_BLNDGAM_RAMA_REGION_2_3 0x1074 5472#define regCM2_CM_BLNDGAM_RAMA_REGION_2_3_BASE_IDX 2 5473#define regCM2_CM_BLNDGAM_RAMA_REGION_4_5 0x1075 5474#define regCM2_CM_BLNDGAM_RAMA_REGION_4_5_BASE_IDX 2 5475#define regCM2_CM_BLNDGAM_RAMA_REGION_6_7 0x1076 5476#define regCM2_CM_BLNDGAM_RAMA_REGION_6_7_BASE_IDX 2 5477#define regCM2_CM_BLNDGAM_RAMA_REGION_8_9 0x1077 5478#define regCM2_CM_BLNDGAM_RAMA_REGION_8_9_BASE_IDX 2 5479#define regCM2_CM_BLNDGAM_RAMA_REGION_10_11 0x1078 5480#define regCM2_CM_BLNDGAM_RAMA_REGION_10_11_BASE_IDX 2 5481#define regCM2_CM_BLNDGAM_RAMA_REGION_12_13 0x1079 5482#define regCM2_CM_BLNDGAM_RAMA_REGION_12_13_BASE_IDX 2 5483#define regCM2_CM_BLNDGAM_RAMA_REGION_14_15 0x107a 5484#define regCM2_CM_BLNDGAM_RAMA_REGION_14_15_BASE_IDX 2 5485#define regCM2_CM_BLNDGAM_RAMA_REGION_16_17 0x107b 5486#define regCM2_CM_BLNDGAM_RAMA_REGION_16_17_BASE_IDX 2 5487#define regCM2_CM_BLNDGAM_RAMA_REGION_18_19 0x107c 5488#define regCM2_CM_BLNDGAM_RAMA_REGION_18_19_BASE_IDX 2 5489#define regCM2_CM_BLNDGAM_RAMA_REGION_20_21 0x107d 5490#define regCM2_CM_BLNDGAM_RAMA_REGION_20_21_BASE_IDX 2 5491#define regCM2_CM_BLNDGAM_RAMA_REGION_22_23 0x107e 5492#define regCM2_CM_BLNDGAM_RAMA_REGION_22_23_BASE_IDX 2 5493#define regCM2_CM_BLNDGAM_RAMA_REGION_24_25 0x107f 5494#define regCM2_CM_BLNDGAM_RAMA_REGION_24_25_BASE_IDX 2 5495#define regCM2_CM_BLNDGAM_RAMA_REGION_26_27 0x1080 5496#define regCM2_CM_BLNDGAM_RAMA_REGION_26_27_BASE_IDX 2 5497#define regCM2_CM_BLNDGAM_RAMA_REGION_28_29 0x1081 5498#define regCM2_CM_BLNDGAM_RAMA_REGION_28_29_BASE_IDX 2 5499#define regCM2_CM_BLNDGAM_RAMA_REGION_30_31 0x1082 5500#define regCM2_CM_BLNDGAM_RAMA_REGION_30_31_BASE_IDX 2 5501#define regCM2_CM_BLNDGAM_RAMA_REGION_32_33 0x1083 5502#define regCM2_CM_BLNDGAM_RAMA_REGION_32_33_BASE_IDX 2 5503#define regCM2_CM_BLNDGAM_RAMB_START_CNTL_B 0x1084 5504#define regCM2_CM_BLNDGAM_RAMB_START_CNTL_B_BASE_IDX 2 5505#define regCM2_CM_BLNDGAM_RAMB_START_CNTL_G 0x1085 5506#define regCM2_CM_BLNDGAM_RAMB_START_CNTL_G_BASE_IDX 2 5507#define regCM2_CM_BLNDGAM_RAMB_START_CNTL_R 0x1086 5508#define regCM2_CM_BLNDGAM_RAMB_START_CNTL_R_BASE_IDX 2 5509#define regCM2_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B 0x1087 5510#define regCM2_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX 2 5511#define regCM2_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G 0x1088 5512#define regCM2_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX 2 5513#define regCM2_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R 0x1089 5514#define regCM2_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX 2 5515#define regCM2_CM_BLNDGAM_RAMB_START_BASE_CNTL_B 0x108a 5516#define regCM2_CM_BLNDGAM_RAMB_START_BASE_CNTL_B_BASE_IDX 2 5517#define regCM2_CM_BLNDGAM_RAMB_START_BASE_CNTL_G 0x108b 5518#define regCM2_CM_BLNDGAM_RAMB_START_BASE_CNTL_G_BASE_IDX 2 5519#define regCM2_CM_BLNDGAM_RAMB_START_BASE_CNTL_R 0x108c 5520#define regCM2_CM_BLNDGAM_RAMB_START_BASE_CNTL_R_BASE_IDX 2 5521#define regCM2_CM_BLNDGAM_RAMB_END_CNTL1_B 0x108d 5522#define regCM2_CM_BLNDGAM_RAMB_END_CNTL1_B_BASE_IDX 2 5523#define regCM2_CM_BLNDGAM_RAMB_END_CNTL2_B 0x108e 5524#define regCM2_CM_BLNDGAM_RAMB_END_CNTL2_B_BASE_IDX 2 5525#define regCM2_CM_BLNDGAM_RAMB_END_CNTL1_G 0x108f 5526#define regCM2_CM_BLNDGAM_RAMB_END_CNTL1_G_BASE_IDX 2 5527#define regCM2_CM_BLNDGAM_RAMB_END_CNTL2_G 0x1090 5528#define regCM2_CM_BLNDGAM_RAMB_END_CNTL2_G_BASE_IDX 2 5529#define regCM2_CM_BLNDGAM_RAMB_END_CNTL1_R 0x1091 5530#define regCM2_CM_BLNDGAM_RAMB_END_CNTL1_R_BASE_IDX 2 5531#define regCM2_CM_BLNDGAM_RAMB_END_CNTL2_R 0x1092 5532#define regCM2_CM_BLNDGAM_RAMB_END_CNTL2_R_BASE_IDX 2 5533#define regCM2_CM_BLNDGAM_RAMB_OFFSET_B 0x1093 5534#define regCM2_CM_BLNDGAM_RAMB_OFFSET_B_BASE_IDX 2 5535#define regCM2_CM_BLNDGAM_RAMB_OFFSET_G 0x1094 5536#define regCM2_CM_BLNDGAM_RAMB_OFFSET_G_BASE_IDX 2 5537#define regCM2_CM_BLNDGAM_RAMB_OFFSET_R 0x1095 5538#define regCM2_CM_BLNDGAM_RAMB_OFFSET_R_BASE_IDX 2 5539#define regCM2_CM_BLNDGAM_RAMB_REGION_0_1 0x1096 5540#define regCM2_CM_BLNDGAM_RAMB_REGION_0_1_BASE_IDX 2 5541#define regCM2_CM_BLNDGAM_RAMB_REGION_2_3 0x1097 5542#define regCM2_CM_BLNDGAM_RAMB_REGION_2_3_BASE_IDX 2 5543#define regCM2_CM_BLNDGAM_RAMB_REGION_4_5 0x1098 5544#define regCM2_CM_BLNDGAM_RAMB_REGION_4_5_BASE_IDX 2 5545#define regCM2_CM_BLNDGAM_RAMB_REGION_6_7 0x1099 5546#define regCM2_CM_BLNDGAM_RAMB_REGION_6_7_BASE_IDX 2 5547#define regCM2_CM_BLNDGAM_RAMB_REGION_8_9 0x109a 5548#define regCM2_CM_BLNDGAM_RAMB_REGION_8_9_BASE_IDX 2 5549#define regCM2_CM_BLNDGAM_RAMB_REGION_10_11 0x109b 5550#define regCM2_CM_BLNDGAM_RAMB_REGION_10_11_BASE_IDX 2 5551#define regCM2_CM_BLNDGAM_RAMB_REGION_12_13 0x109c 5552#define regCM2_CM_BLNDGAM_RAMB_REGION_12_13_BASE_IDX 2 5553#define regCM2_CM_BLNDGAM_RAMB_REGION_14_15 0x109d 5554#define regCM2_CM_BLNDGAM_RAMB_REGION_14_15_BASE_IDX 2 5555#define regCM2_CM_BLNDGAM_RAMB_REGION_16_17 0x109e 5556#define regCM2_CM_BLNDGAM_RAMB_REGION_16_17_BASE_IDX 2 5557#define regCM2_CM_BLNDGAM_RAMB_REGION_18_19 0x109f 5558#define regCM2_CM_BLNDGAM_RAMB_REGION_18_19_BASE_IDX 2 5559#define regCM2_CM_BLNDGAM_RAMB_REGION_20_21 0x10a0 5560#define regCM2_CM_BLNDGAM_RAMB_REGION_20_21_BASE_IDX 2 5561#define regCM2_CM_BLNDGAM_RAMB_REGION_22_23 0x10a1 5562#define regCM2_CM_BLNDGAM_RAMB_REGION_22_23_BASE_IDX 2 5563#define regCM2_CM_BLNDGAM_RAMB_REGION_24_25 0x10a2 5564#define regCM2_CM_BLNDGAM_RAMB_REGION_24_25_BASE_IDX 2 5565#define regCM2_CM_BLNDGAM_RAMB_REGION_26_27 0x10a3 5566#define regCM2_CM_BLNDGAM_RAMB_REGION_26_27_BASE_IDX 2 5567#define regCM2_CM_BLNDGAM_RAMB_REGION_28_29 0x10a4 5568#define regCM2_CM_BLNDGAM_RAMB_REGION_28_29_BASE_IDX 2 5569#define regCM2_CM_BLNDGAM_RAMB_REGION_30_31 0x10a5 5570#define regCM2_CM_BLNDGAM_RAMB_REGION_30_31_BASE_IDX 2 5571#define regCM2_CM_BLNDGAM_RAMB_REGION_32_33 0x10a6 5572#define regCM2_CM_BLNDGAM_RAMB_REGION_32_33_BASE_IDX 2 5573#define regCM2_CM_HDR_MULT_COEF 0x10a7 5574#define regCM2_CM_HDR_MULT_COEF_BASE_IDX 2 5575#define regCM2_CM_MEM_PWR_CTRL 0x10a8 5576#define regCM2_CM_MEM_PWR_CTRL_BASE_IDX 2 5577#define regCM2_CM_MEM_PWR_STATUS 0x10a9 5578#define regCM2_CM_MEM_PWR_STATUS_BASE_IDX 2 5579#define regCM2_CM_DEALPHA 0x10ab 5580#define regCM2_CM_DEALPHA_BASE_IDX 2 5581#define regCM2_CM_COEF_FORMAT 0x10ac 5582#define regCM2_CM_COEF_FORMAT_BASE_IDX 2 5583#define regCM2_CM_SHAPER_CONTROL 0x10ad 5584#define regCM2_CM_SHAPER_CONTROL_BASE_IDX 2 5585#define regCM2_CM_SHAPER_OFFSET_R 0x10ae 5586#define regCM2_CM_SHAPER_OFFSET_R_BASE_IDX 2 5587#define regCM2_CM_SHAPER_OFFSET_G 0x10af 5588#define regCM2_CM_SHAPER_OFFSET_G_BASE_IDX 2 5589#define regCM2_CM_SHAPER_OFFSET_B 0x10b0 5590#define regCM2_CM_SHAPER_OFFSET_B_BASE_IDX 2 5591#define regCM2_CM_SHAPER_SCALE_R 0x10b1 5592#define regCM2_CM_SHAPER_SCALE_R_BASE_IDX 2 5593#define regCM2_CM_SHAPER_SCALE_G_B 0x10b2 5594#define regCM2_CM_SHAPER_SCALE_G_B_BASE_IDX 2 5595#define regCM2_CM_SHAPER_LUT_INDEX 0x10b3 5596#define regCM2_CM_SHAPER_LUT_INDEX_BASE_IDX 2 5597#define regCM2_CM_SHAPER_LUT_DATA 0x10b4 5598#define regCM2_CM_SHAPER_LUT_DATA_BASE_IDX 2 5599#define regCM2_CM_SHAPER_LUT_WRITE_EN_MASK 0x10b5 5600#define regCM2_CM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX 2 5601#define regCM2_CM_SHAPER_RAMA_START_CNTL_B 0x10b6 5602#define regCM2_CM_SHAPER_RAMA_START_CNTL_B_BASE_IDX 2 5603#define regCM2_CM_SHAPER_RAMA_START_CNTL_G 0x10b7 5604#define regCM2_CM_SHAPER_RAMA_START_CNTL_G_BASE_IDX 2 5605#define regCM2_CM_SHAPER_RAMA_START_CNTL_R 0x10b8 5606#define regCM2_CM_SHAPER_RAMA_START_CNTL_R_BASE_IDX 2 5607#define regCM2_CM_SHAPER_RAMA_END_CNTL_B 0x10b9 5608#define regCM2_CM_SHAPER_RAMA_END_CNTL_B_BASE_IDX 2 5609#define regCM2_CM_SHAPER_RAMA_END_CNTL_G 0x10ba 5610#define regCM2_CM_SHAPER_RAMA_END_CNTL_G_BASE_IDX 2 5611#define regCM2_CM_SHAPER_RAMA_END_CNTL_R 0x10bb 5612#define regCM2_CM_SHAPER_RAMA_END_CNTL_R_BASE_IDX 2 5613#define regCM2_CM_SHAPER_RAMA_REGION_0_1 0x10bc 5614#define regCM2_CM_SHAPER_RAMA_REGION_0_1_BASE_IDX 2 5615#define regCM2_CM_SHAPER_RAMA_REGION_2_3 0x10bd 5616#define regCM2_CM_SHAPER_RAMA_REGION_2_3_BASE_IDX 2 5617#define regCM2_CM_SHAPER_RAMA_REGION_4_5 0x10be 5618#define regCM2_CM_SHAPER_RAMA_REGION_4_5_BASE_IDX 2 5619#define regCM2_CM_SHAPER_RAMA_REGION_6_7 0x10bf 5620#define regCM2_CM_SHAPER_RAMA_REGION_6_7_BASE_IDX 2 5621#define regCM2_CM_SHAPER_RAMA_REGION_8_9 0x10c0 5622#define regCM2_CM_SHAPER_RAMA_REGION_8_9_BASE_IDX 2 5623#define regCM2_CM_SHAPER_RAMA_REGION_10_11 0x10c1 5624#define regCM2_CM_SHAPER_RAMA_REGION_10_11_BASE_IDX 2 5625#define regCM2_CM_SHAPER_RAMA_REGION_12_13 0x10c2 5626#define regCM2_CM_SHAPER_RAMA_REGION_12_13_BASE_IDX 2 5627#define regCM2_CM_SHAPER_RAMA_REGION_14_15 0x10c3 5628#define regCM2_CM_SHAPER_RAMA_REGION_14_15_BASE_IDX 2 5629#define regCM2_CM_SHAPER_RAMA_REGION_16_17 0x10c4 5630#define regCM2_CM_SHAPER_RAMA_REGION_16_17_BASE_IDX 2 5631#define regCM2_CM_SHAPER_RAMA_REGION_18_19 0x10c5 5632#define regCM2_CM_SHAPER_RAMA_REGION_18_19_BASE_IDX 2 5633#define regCM2_CM_SHAPER_RAMA_REGION_20_21 0x10c6 5634#define regCM2_CM_SHAPER_RAMA_REGION_20_21_BASE_IDX 2 5635#define regCM2_CM_SHAPER_RAMA_REGION_22_23 0x10c7 5636#define regCM2_CM_SHAPER_RAMA_REGION_22_23_BASE_IDX 2 5637#define regCM2_CM_SHAPER_RAMA_REGION_24_25 0x10c8 5638#define regCM2_CM_SHAPER_RAMA_REGION_24_25_BASE_IDX 2 5639#define regCM2_CM_SHAPER_RAMA_REGION_26_27 0x10c9 5640#define regCM2_CM_SHAPER_RAMA_REGION_26_27_BASE_IDX 2 5641#define regCM2_CM_SHAPER_RAMA_REGION_28_29 0x10ca 5642#define regCM2_CM_SHAPER_RAMA_REGION_28_29_BASE_IDX 2 5643#define regCM2_CM_SHAPER_RAMA_REGION_30_31 0x10cb 5644#define regCM2_CM_SHAPER_RAMA_REGION_30_31_BASE_IDX 2 5645#define regCM2_CM_SHAPER_RAMA_REGION_32_33 0x10cc 5646#define regCM2_CM_SHAPER_RAMA_REGION_32_33_BASE_IDX 2 5647#define regCM2_CM_SHAPER_RAMB_START_CNTL_B 0x10cd 5648#define regCM2_CM_SHAPER_RAMB_START_CNTL_B_BASE_IDX 2 5649#define regCM2_CM_SHAPER_RAMB_START_CNTL_G 0x10ce 5650#define regCM2_CM_SHAPER_RAMB_START_CNTL_G_BASE_IDX 2 5651#define regCM2_CM_SHAPER_RAMB_START_CNTL_R 0x10cf 5652#define regCM2_CM_SHAPER_RAMB_START_CNTL_R_BASE_IDX 2 5653#define regCM2_CM_SHAPER_RAMB_END_CNTL_B 0x10d0 5654#define regCM2_CM_SHAPER_RAMB_END_CNTL_B_BASE_IDX 2 5655#define regCM2_CM_SHAPER_RAMB_END_CNTL_G 0x10d1 5656#define regCM2_CM_SHAPER_RAMB_END_CNTL_G_BASE_IDX 2 5657#define regCM2_CM_SHAPER_RAMB_END_CNTL_R 0x10d2 5658#define regCM2_CM_SHAPER_RAMB_END_CNTL_R_BASE_IDX 2 5659#define regCM2_CM_SHAPER_RAMB_REGION_0_1 0x10d3 5660#define regCM2_CM_SHAPER_RAMB_REGION_0_1_BASE_IDX 2 5661#define regCM2_CM_SHAPER_RAMB_REGION_2_3 0x10d4 5662#define regCM2_CM_SHAPER_RAMB_REGION_2_3_BASE_IDX 2 5663#define regCM2_CM_SHAPER_RAMB_REGION_4_5 0x10d5 5664#define regCM2_CM_SHAPER_RAMB_REGION_4_5_BASE_IDX 2 5665#define regCM2_CM_SHAPER_RAMB_REGION_6_7 0x10d6 5666#define regCM2_CM_SHAPER_RAMB_REGION_6_7_BASE_IDX 2 5667#define regCM2_CM_SHAPER_RAMB_REGION_8_9 0x10d7 5668#define regCM2_CM_SHAPER_RAMB_REGION_8_9_BASE_IDX 2 5669#define regCM2_CM_SHAPER_RAMB_REGION_10_11 0x10d8 5670#define regCM2_CM_SHAPER_RAMB_REGION_10_11_BASE_IDX 2 5671#define regCM2_CM_SHAPER_RAMB_REGION_12_13 0x10d9 5672#define regCM2_CM_SHAPER_RAMB_REGION_12_13_BASE_IDX 2 5673#define regCM2_CM_SHAPER_RAMB_REGION_14_15 0x10da 5674#define regCM2_CM_SHAPER_RAMB_REGION_14_15_BASE_IDX 2 5675#define regCM2_CM_SHAPER_RAMB_REGION_16_17 0x10db 5676#define regCM2_CM_SHAPER_RAMB_REGION_16_17_BASE_IDX 2 5677#define regCM2_CM_SHAPER_RAMB_REGION_18_19 0x10dc 5678#define regCM2_CM_SHAPER_RAMB_REGION_18_19_BASE_IDX 2 5679#define regCM2_CM_SHAPER_RAMB_REGION_20_21 0x10dd 5680#define regCM2_CM_SHAPER_RAMB_REGION_20_21_BASE_IDX 2 5681#define regCM2_CM_SHAPER_RAMB_REGION_22_23 0x10de 5682#define regCM2_CM_SHAPER_RAMB_REGION_22_23_BASE_IDX 2 5683#define regCM2_CM_SHAPER_RAMB_REGION_24_25 0x10df 5684#define regCM2_CM_SHAPER_RAMB_REGION_24_25_BASE_IDX 2 5685#define regCM2_CM_SHAPER_RAMB_REGION_26_27 0x10e0 5686#define regCM2_CM_SHAPER_RAMB_REGION_26_27_BASE_IDX 2 5687#define regCM2_CM_SHAPER_RAMB_REGION_28_29 0x10e1 5688#define regCM2_CM_SHAPER_RAMB_REGION_28_29_BASE_IDX 2 5689#define regCM2_CM_SHAPER_RAMB_REGION_30_31 0x10e2 5690#define regCM2_CM_SHAPER_RAMB_REGION_30_31_BASE_IDX 2 5691#define regCM2_CM_SHAPER_RAMB_REGION_32_33 0x10e3 5692#define regCM2_CM_SHAPER_RAMB_REGION_32_33_BASE_IDX 2 5693#define regCM2_CM_MEM_PWR_CTRL2 0x10e4 5694#define regCM2_CM_MEM_PWR_CTRL2_BASE_IDX 2 5695#define regCM2_CM_MEM_PWR_STATUS2 0x10e5 5696#define regCM2_CM_MEM_PWR_STATUS2_BASE_IDX 2 5697#define regCM2_CM_3DLUT_MODE 0x10e6 5698#define regCM2_CM_3DLUT_MODE_BASE_IDX 2 5699#define regCM2_CM_3DLUT_INDEX 0x10e7 5700#define regCM2_CM_3DLUT_INDEX_BASE_IDX 2 5701#define regCM2_CM_3DLUT_DATA 0x10e8 5702#define regCM2_CM_3DLUT_DATA_BASE_IDX 2 5703#define regCM2_CM_3DLUT_DATA_30BIT 0x10e9 5704#define regCM2_CM_3DLUT_DATA_30BIT_BASE_IDX 2 5705#define regCM2_CM_3DLUT_READ_WRITE_CONTROL 0x10ea 5706#define regCM2_CM_3DLUT_READ_WRITE_CONTROL_BASE_IDX 2 5707#define regCM2_CM_3DLUT_OUT_NORM_FACTOR 0x10eb 5708#define regCM2_CM_3DLUT_OUT_NORM_FACTOR_BASE_IDX 2 5709#define regCM2_CM_3DLUT_OUT_OFFSET_R 0x10ec 5710#define regCM2_CM_3DLUT_OUT_OFFSET_R_BASE_IDX 2 5711#define regCM2_CM_3DLUT_OUT_OFFSET_G 0x10ed 5712#define regCM2_CM_3DLUT_OUT_OFFSET_G_BASE_IDX 2 5713#define regCM2_CM_3DLUT_OUT_OFFSET_B 0x10ee 5714#define regCM2_CM_3DLUT_OUT_OFFSET_B_BASE_IDX 2 5715#define regCM2_CM_TEST_DEBUG_INDEX 0x10ef 5716#define regCM2_CM_TEST_DEBUG_INDEX_BASE_IDX 2 5717#define regCM2_CM_TEST_DEBUG_DATA 0x10f0 5718#define regCM2_CM_TEST_DEBUG_DATA_BASE_IDX 2 5719 5720 5721// addressBlock: dce_dc_dpp2_dispdec_dpp_top_dispdec 5722// base address: 0xb58 5723#define regDPP_TOP2_DPP_CONTROL 0x0f9b 5724#define regDPP_TOP2_DPP_CONTROL_BASE_IDX 2 5725#define regDPP_TOP2_DPP_SOFT_RESET 0x0f9c 5726#define regDPP_TOP2_DPP_SOFT_RESET_BASE_IDX 2 5727#define regDPP_TOP2_DPP_CRC_VAL_R_G 0x0f9d 5728#define regDPP_TOP2_DPP_CRC_VAL_R_G_BASE_IDX 2 5729#define regDPP_TOP2_DPP_CRC_VAL_B_A 0x0f9e 5730#define regDPP_TOP2_DPP_CRC_VAL_B_A_BASE_IDX 2 5731#define regDPP_TOP2_DPP_CRC_CTRL 0x0f9f 5732#define regDPP_TOP2_DPP_CRC_CTRL_BASE_IDX 2 5733#define regDPP_TOP2_HOST_READ_CONTROL 0x0fa0 5734#define regDPP_TOP2_HOST_READ_CONTROL_BASE_IDX 2 5735 5736 5737// addressBlock: dce_dc_dpp2_dispdec_dpp_dcperfmon_dc_perfmon_dispdec 5738// base address: 0x43e8 5739#define regDC_PERFMON13_PERFCOUNTER_CNTL 0x10fa 5740#define regDC_PERFMON13_PERFCOUNTER_CNTL_BASE_IDX 2 5741#define regDC_PERFMON13_PERFCOUNTER_CNTL2 0x10fb 5742#define regDC_PERFMON13_PERFCOUNTER_CNTL2_BASE_IDX 2 5743#define regDC_PERFMON13_PERFCOUNTER_STATE 0x10fc 5744#define regDC_PERFMON13_PERFCOUNTER_STATE_BASE_IDX 2 5745#define regDC_PERFMON13_PERFMON_CNTL 0x10fd 5746#define regDC_PERFMON13_PERFMON_CNTL_BASE_IDX 2 5747#define regDC_PERFMON13_PERFMON_CNTL2 0x10fe 5748#define regDC_PERFMON13_PERFMON_CNTL2_BASE_IDX 2 5749#define regDC_PERFMON13_PERFMON_CVALUE_INT_MISC 0x10ff 5750#define regDC_PERFMON13_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 5751#define regDC_PERFMON13_PERFMON_CVALUE_LOW 0x1100 5752#define regDC_PERFMON13_PERFMON_CVALUE_LOW_BASE_IDX 2 5753#define regDC_PERFMON13_PERFMON_HI 0x1101 5754#define regDC_PERFMON13_PERFMON_HI_BASE_IDX 2 5755#define regDC_PERFMON13_PERFMON_LOW 0x1102 5756#define regDC_PERFMON13_PERFMON_LOW_BASE_IDX 2 5757 5758 5759// addressBlock: dce_dc_dpp3_dispdec_cnvc_cfg_dispdec 5760// base address: 0x1104 5761#define regCNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT 0x1110 5762#define regCNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX 2 5763#define regCNVC_CFG3_FORMAT_CONTROL 0x1111 5764#define regCNVC_CFG3_FORMAT_CONTROL_BASE_IDX 2 5765#define regCNVC_CFG3_FCNV_FP_BIAS_R 0x1112 5766#define regCNVC_CFG3_FCNV_FP_BIAS_R_BASE_IDX 2 5767#define regCNVC_CFG3_FCNV_FP_BIAS_G 0x1113 5768#define regCNVC_CFG3_FCNV_FP_BIAS_G_BASE_IDX 2 5769#define regCNVC_CFG3_FCNV_FP_BIAS_B 0x1114 5770#define regCNVC_CFG3_FCNV_FP_BIAS_B_BASE_IDX 2 5771#define regCNVC_CFG3_FCNV_FP_SCALE_R 0x1115 5772#define regCNVC_CFG3_FCNV_FP_SCALE_R_BASE_IDX 2 5773#define regCNVC_CFG3_FCNV_FP_SCALE_G 0x1116 5774#define regCNVC_CFG3_FCNV_FP_SCALE_G_BASE_IDX 2 5775#define regCNVC_CFG3_FCNV_FP_SCALE_B 0x1117 5776#define regCNVC_CFG3_FCNV_FP_SCALE_B_BASE_IDX 2 5777#define regCNVC_CFG3_COLOR_KEYER_CONTROL 0x1118 5778#define regCNVC_CFG3_COLOR_KEYER_CONTROL_BASE_IDX 2 5779#define regCNVC_CFG3_COLOR_KEYER_ALPHA 0x1119 5780#define regCNVC_CFG3_COLOR_KEYER_ALPHA_BASE_IDX 2 5781#define regCNVC_CFG3_COLOR_KEYER_RED 0x111a 5782#define regCNVC_CFG3_COLOR_KEYER_RED_BASE_IDX 2 5783#define regCNVC_CFG3_COLOR_KEYER_GREEN 0x111b 5784#define regCNVC_CFG3_COLOR_KEYER_GREEN_BASE_IDX 2 5785#define regCNVC_CFG3_COLOR_KEYER_BLUE 0x111c 5786#define regCNVC_CFG3_COLOR_KEYER_BLUE_BASE_IDX 2 5787#define regCNVC_CFG3_ALPHA_2BIT_LUT 0x111e 5788#define regCNVC_CFG3_ALPHA_2BIT_LUT_BASE_IDX 2 5789#define regCNVC_CFG3_PRE_DEALPHA 0x111f 5790#define regCNVC_CFG3_PRE_DEALPHA_BASE_IDX 2 5791#define regCNVC_CFG3_PRE_CSC_MODE 0x1120 5792#define regCNVC_CFG3_PRE_CSC_MODE_BASE_IDX 2 5793#define regCNVC_CFG3_PRE_CSC_C11_C12 0x1121 5794#define regCNVC_CFG3_PRE_CSC_C11_C12_BASE_IDX 2 5795#define regCNVC_CFG3_PRE_CSC_C13_C14 0x1122 5796#define regCNVC_CFG3_PRE_CSC_C13_C14_BASE_IDX 2 5797#define regCNVC_CFG3_PRE_CSC_C21_C22 0x1123 5798#define regCNVC_CFG3_PRE_CSC_C21_C22_BASE_IDX 2 5799#define regCNVC_CFG3_PRE_CSC_C23_C24 0x1124 5800#define regCNVC_CFG3_PRE_CSC_C23_C24_BASE_IDX 2 5801#define regCNVC_CFG3_PRE_CSC_C31_C32 0x1125 5802#define regCNVC_CFG3_PRE_CSC_C31_C32_BASE_IDX 2 5803#define regCNVC_CFG3_PRE_CSC_C33_C34 0x1126 5804#define regCNVC_CFG3_PRE_CSC_C33_C34_BASE_IDX 2 5805#define regCNVC_CFG3_PRE_CSC_B_C11_C12 0x1127 5806#define regCNVC_CFG3_PRE_CSC_B_C11_C12_BASE_IDX 2 5807#define regCNVC_CFG3_PRE_CSC_B_C13_C14 0x1128 5808#define regCNVC_CFG3_PRE_CSC_B_C13_C14_BASE_IDX 2 5809#define regCNVC_CFG3_PRE_CSC_B_C21_C22 0x1129 5810#define regCNVC_CFG3_PRE_CSC_B_C21_C22_BASE_IDX 2 5811#define regCNVC_CFG3_PRE_CSC_B_C23_C24 0x112a 5812#define regCNVC_CFG3_PRE_CSC_B_C23_C24_BASE_IDX 2 5813#define regCNVC_CFG3_PRE_CSC_B_C31_C32 0x112b 5814#define regCNVC_CFG3_PRE_CSC_B_C31_C32_BASE_IDX 2 5815#define regCNVC_CFG3_PRE_CSC_B_C33_C34 0x112c 5816#define regCNVC_CFG3_PRE_CSC_B_C33_C34_BASE_IDX 2 5817#define regCNVC_CFG3_CNVC_COEF_FORMAT 0x112d 5818#define regCNVC_CFG3_CNVC_COEF_FORMAT_BASE_IDX 2 5819#define regCNVC_CFG3_PRE_DEGAM 0x112e 5820#define regCNVC_CFG3_PRE_DEGAM_BASE_IDX 2 5821#define regCNVC_CFG3_PRE_REALPHA 0x112f 5822#define regCNVC_CFG3_PRE_REALPHA_BASE_IDX 2 5823 5824 5825// addressBlock: dce_dc_dpp3_dispdec_cnvc_cur_dispdec 5826// base address: 0x1104 5827#define regCNVC_CUR3_CURSOR0_CONTROL 0x1132 5828#define regCNVC_CUR3_CURSOR0_CONTROL_BASE_IDX 2 5829#define regCNVC_CUR3_CURSOR0_COLOR0 0x1133 5830#define regCNVC_CUR3_CURSOR0_COLOR0_BASE_IDX 2 5831#define regCNVC_CUR3_CURSOR0_COLOR1 0x1134 5832#define regCNVC_CUR3_CURSOR0_COLOR1_BASE_IDX 2 5833#define regCNVC_CUR3_CURSOR0_FP_SCALE_BIAS 0x1135 5834#define regCNVC_CUR3_CURSOR0_FP_SCALE_BIAS_BASE_IDX 2 5835 5836 5837// addressBlock: dce_dc_dpp3_dispdec_dscl_dispdec 5838// base address: 0x1104 5839#define regDSCL3_SCL_COEF_RAM_TAP_SELECT 0x113a 5840#define regDSCL3_SCL_COEF_RAM_TAP_SELECT_BASE_IDX 2 5841#define regDSCL3_SCL_COEF_RAM_TAP_DATA 0x113b 5842#define regDSCL3_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2 5843#define regDSCL3_SCL_MODE 0x113c 5844#define regDSCL3_SCL_MODE_BASE_IDX 2 5845#define regDSCL3_SCL_TAP_CONTROL 0x113d 5846#define regDSCL3_SCL_TAP_CONTROL_BASE_IDX 2 5847#define regDSCL3_DSCL_CONTROL 0x113e 5848#define regDSCL3_DSCL_CONTROL_BASE_IDX 2 5849#define regDSCL3_DSCL_2TAP_CONTROL 0x113f 5850#define regDSCL3_DSCL_2TAP_CONTROL_BASE_IDX 2 5851#define regDSCL3_SCL_MANUAL_REPLICATE_CONTROL 0x1140 5852#define regDSCL3_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2 5853#define regDSCL3_SCL_HORZ_FILTER_SCALE_RATIO 0x1141 5854#define regDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2 5855#define regDSCL3_SCL_HORZ_FILTER_INIT 0x1142 5856#define regDSCL3_SCL_HORZ_FILTER_INIT_BASE_IDX 2 5857#define regDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C 0x1143 5858#define regDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX 2 5859#define regDSCL3_SCL_HORZ_FILTER_INIT_C 0x1144 5860#define regDSCL3_SCL_HORZ_FILTER_INIT_C_BASE_IDX 2 5861#define regDSCL3_SCL_VERT_FILTER_SCALE_RATIO 0x1145 5862#define regDSCL3_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2 5863#define regDSCL3_SCL_VERT_FILTER_INIT 0x1146 5864#define regDSCL3_SCL_VERT_FILTER_INIT_BASE_IDX 2 5865#define regDSCL3_SCL_VERT_FILTER_INIT_BOT 0x1147 5866#define regDSCL3_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2 5867#define regDSCL3_SCL_VERT_FILTER_SCALE_RATIO_C 0x1148 5868#define regDSCL3_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX 2 5869#define regDSCL3_SCL_VERT_FILTER_INIT_C 0x1149 5870#define regDSCL3_SCL_VERT_FILTER_INIT_C_BASE_IDX 2 5871#define regDSCL3_SCL_VERT_FILTER_INIT_BOT_C 0x114a 5872#define regDSCL3_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX 2 5873#define regDSCL3_SCL_BLACK_COLOR 0x114b 5874#define regDSCL3_SCL_BLACK_COLOR_BASE_IDX 2 5875#define regDSCL3_DSCL_UPDATE 0x114c 5876#define regDSCL3_DSCL_UPDATE_BASE_IDX 2 5877#define regDSCL3_DSCL_AUTOCAL 0x114d 5878#define regDSCL3_DSCL_AUTOCAL_BASE_IDX 2 5879#define regDSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT 0x114e 5880#define regDSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2 5881#define regDSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM 0x114f 5882#define regDSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2 5883#define regDSCL3_OTG_H_BLANK 0x1150 5884#define regDSCL3_OTG_H_BLANK_BASE_IDX 2 5885#define regDSCL3_OTG_V_BLANK 0x1151 5886#define regDSCL3_OTG_V_BLANK_BASE_IDX 2 5887#define regDSCL3_RECOUT_START 0x1152 5888#define regDSCL3_RECOUT_START_BASE_IDX 2 5889#define regDSCL3_RECOUT_SIZE 0x1153 5890#define regDSCL3_RECOUT_SIZE_BASE_IDX 2 5891#define regDSCL3_MPC_SIZE 0x1154 5892#define regDSCL3_MPC_SIZE_BASE_IDX 2 5893#define regDSCL3_LB_DATA_FORMAT 0x1155 5894#define regDSCL3_LB_DATA_FORMAT_BASE_IDX 2 5895#define regDSCL3_LB_MEMORY_CTRL 0x1156 5896#define regDSCL3_LB_MEMORY_CTRL_BASE_IDX 2 5897#define regDSCL3_LB_V_COUNTER 0x1157 5898#define regDSCL3_LB_V_COUNTER_BASE_IDX 2 5899#define regDSCL3_DSCL_MEM_PWR_CTRL 0x1158 5900#define regDSCL3_DSCL_MEM_PWR_CTRL_BASE_IDX 2 5901#define regDSCL3_DSCL_MEM_PWR_STATUS 0x1159 5902#define regDSCL3_DSCL_MEM_PWR_STATUS_BASE_IDX 2 5903#define regDSCL3_OBUF_CONTROL 0x115a 5904#define regDSCL3_OBUF_CONTROL_BASE_IDX 2 5905#define regDSCL3_OBUF_MEM_PWR_CTRL 0x115b 5906#define regDSCL3_OBUF_MEM_PWR_CTRL_BASE_IDX 2 5907 5908 5909// addressBlock: dce_dc_dpp3_dispdec_cm_dispdec 5910// base address: 0x1104 5911#define regCM3_CM_CONTROL 0x1161 5912#define regCM3_CM_CONTROL_BASE_IDX 2 5913#define regCM3_CM_POST_CSC_CONTROL 0x1162 5914#define regCM3_CM_POST_CSC_CONTROL_BASE_IDX 2 5915#define regCM3_CM_POST_CSC_C11_C12 0x1163 5916#define regCM3_CM_POST_CSC_C11_C12_BASE_IDX 2 5917#define regCM3_CM_POST_CSC_C13_C14 0x1164 5918#define regCM3_CM_POST_CSC_C13_C14_BASE_IDX 2 5919#define regCM3_CM_POST_CSC_C21_C22 0x1165 5920#define regCM3_CM_POST_CSC_C21_C22_BASE_IDX 2 5921#define regCM3_CM_POST_CSC_C23_C24 0x1166 5922#define regCM3_CM_POST_CSC_C23_C24_BASE_IDX 2 5923#define regCM3_CM_POST_CSC_C31_C32 0x1167 5924#define regCM3_CM_POST_CSC_C31_C32_BASE_IDX 2 5925#define regCM3_CM_POST_CSC_C33_C34 0x1168 5926#define regCM3_CM_POST_CSC_C33_C34_BASE_IDX 2 5927#define regCM3_CM_POST_CSC_B_C11_C12 0x1169 5928#define regCM3_CM_POST_CSC_B_C11_C12_BASE_IDX 2 5929#define regCM3_CM_POST_CSC_B_C13_C14 0x116a 5930#define regCM3_CM_POST_CSC_B_C13_C14_BASE_IDX 2 5931#define regCM3_CM_POST_CSC_B_C21_C22 0x116b 5932#define regCM3_CM_POST_CSC_B_C21_C22_BASE_IDX 2 5933#define regCM3_CM_POST_CSC_B_C23_C24 0x116c 5934#define regCM3_CM_POST_CSC_B_C23_C24_BASE_IDX 2 5935#define regCM3_CM_POST_CSC_B_C31_C32 0x116d 5936#define regCM3_CM_POST_CSC_B_C31_C32_BASE_IDX 2 5937#define regCM3_CM_POST_CSC_B_C33_C34 0x116e 5938#define regCM3_CM_POST_CSC_B_C33_C34_BASE_IDX 2 5939#define regCM3_CM_GAMUT_REMAP_CONTROL 0x116f 5940#define regCM3_CM_GAMUT_REMAP_CONTROL_BASE_IDX 2 5941#define regCM3_CM_GAMUT_REMAP_C11_C12 0x1170 5942#define regCM3_CM_GAMUT_REMAP_C11_C12_BASE_IDX 2 5943#define regCM3_CM_GAMUT_REMAP_C13_C14 0x1171 5944#define regCM3_CM_GAMUT_REMAP_C13_C14_BASE_IDX 2 5945#define regCM3_CM_GAMUT_REMAP_C21_C22 0x1172 5946#define regCM3_CM_GAMUT_REMAP_C21_C22_BASE_IDX 2 5947#define regCM3_CM_GAMUT_REMAP_C23_C24 0x1173 5948#define regCM3_CM_GAMUT_REMAP_C23_C24_BASE_IDX 2 5949#define regCM3_CM_GAMUT_REMAP_C31_C32 0x1174 5950#define regCM3_CM_GAMUT_REMAP_C31_C32_BASE_IDX 2 5951#define regCM3_CM_GAMUT_REMAP_C33_C34 0x1175 5952#define regCM3_CM_GAMUT_REMAP_C33_C34_BASE_IDX 2 5953#define regCM3_CM_GAMUT_REMAP_B_C11_C12 0x1176 5954#define regCM3_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX 2 5955#define regCM3_CM_GAMUT_REMAP_B_C13_C14 0x1177 5956#define regCM3_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX 2 5957#define regCM3_CM_GAMUT_REMAP_B_C21_C22 0x1178 5958#define regCM3_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX 2 5959#define regCM3_CM_GAMUT_REMAP_B_C23_C24 0x1179 5960#define regCM3_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX 2 5961#define regCM3_CM_GAMUT_REMAP_B_C31_C32 0x117a 5962#define regCM3_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX 2 5963#define regCM3_CM_GAMUT_REMAP_B_C33_C34 0x117b 5964#define regCM3_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX 2 5965#define regCM3_CM_BIAS_CR_R 0x117c 5966#define regCM3_CM_BIAS_CR_R_BASE_IDX 2 5967#define regCM3_CM_BIAS_Y_G_CB_B 0x117d 5968#define regCM3_CM_BIAS_Y_G_CB_B_BASE_IDX 2 5969#define regCM3_CM_GAMCOR_CONTROL 0x117e 5970#define regCM3_CM_GAMCOR_CONTROL_BASE_IDX 2 5971#define regCM3_CM_GAMCOR_LUT_INDEX 0x117f 5972#define regCM3_CM_GAMCOR_LUT_INDEX_BASE_IDX 2 5973#define regCM3_CM_GAMCOR_LUT_DATA 0x1180 5974#define regCM3_CM_GAMCOR_LUT_DATA_BASE_IDX 2 5975#define regCM3_CM_GAMCOR_LUT_CONTROL 0x1181 5976#define regCM3_CM_GAMCOR_LUT_CONTROL_BASE_IDX 2 5977#define regCM3_CM_GAMCOR_RAMA_START_CNTL_B 0x1182 5978#define regCM3_CM_GAMCOR_RAMA_START_CNTL_B_BASE_IDX 2 5979#define regCM3_CM_GAMCOR_RAMA_START_CNTL_G 0x1183 5980#define regCM3_CM_GAMCOR_RAMA_START_CNTL_G_BASE_IDX 2 5981#define regCM3_CM_GAMCOR_RAMA_START_CNTL_R 0x1184 5982#define regCM3_CM_GAMCOR_RAMA_START_CNTL_R_BASE_IDX 2 5983#define regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B 0x1185 5984#define regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B_BASE_IDX 2 5985#define regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G 0x1186 5986#define regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2 5987#define regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R 0x1187 5988#define regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R_BASE_IDX 2 5989#define regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_B 0x1188 5990#define regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_B_BASE_IDX 2 5991#define regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_G 0x1189 5992#define regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_G_BASE_IDX 2 5993#define regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_R 0x118a 5994#define regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_R_BASE_IDX 2 5995#define regCM3_CM_GAMCOR_RAMA_END_CNTL1_B 0x118b 5996#define regCM3_CM_GAMCOR_RAMA_END_CNTL1_B_BASE_IDX 2 5997#define regCM3_CM_GAMCOR_RAMA_END_CNTL2_B 0x118c 5998#define regCM3_CM_GAMCOR_RAMA_END_CNTL2_B_BASE_IDX 2 5999#define regCM3_CM_GAMCOR_RAMA_END_CNTL1_G 0x118d 6000#define regCM3_CM_GAMCOR_RAMA_END_CNTL1_G_BASE_IDX 2 6001#define regCM3_CM_GAMCOR_RAMA_END_CNTL2_G 0x118e 6002#define regCM3_CM_GAMCOR_RAMA_END_CNTL2_G_BASE_IDX 2 6003#define regCM3_CM_GAMCOR_RAMA_END_CNTL1_R 0x118f 6004#define regCM3_CM_GAMCOR_RAMA_END_CNTL1_R_BASE_IDX 2 6005#define regCM3_CM_GAMCOR_RAMA_END_CNTL2_R 0x1190 6006#define regCM3_CM_GAMCOR_RAMA_END_CNTL2_R_BASE_IDX 2 6007#define regCM3_CM_GAMCOR_RAMA_OFFSET_B 0x1191 6008#define regCM3_CM_GAMCOR_RAMA_OFFSET_B_BASE_IDX 2 6009#define regCM3_CM_GAMCOR_RAMA_OFFSET_G 0x1192 6010#define regCM3_CM_GAMCOR_RAMA_OFFSET_G_BASE_IDX 2 6011#define regCM3_CM_GAMCOR_RAMA_OFFSET_R 0x1193 6012#define regCM3_CM_GAMCOR_RAMA_OFFSET_R_BASE_IDX 2 6013#define regCM3_CM_GAMCOR_RAMA_REGION_0_1 0x1194 6014#define regCM3_CM_GAMCOR_RAMA_REGION_0_1_BASE_IDX 2 6015#define regCM3_CM_GAMCOR_RAMA_REGION_2_3 0x1195 6016#define regCM3_CM_GAMCOR_RAMA_REGION_2_3_BASE_IDX 2 6017#define regCM3_CM_GAMCOR_RAMA_REGION_4_5 0x1196 6018#define regCM3_CM_GAMCOR_RAMA_REGION_4_5_BASE_IDX 2 6019#define regCM3_CM_GAMCOR_RAMA_REGION_6_7 0x1197 6020#define regCM3_CM_GAMCOR_RAMA_REGION_6_7_BASE_IDX 2 6021#define regCM3_CM_GAMCOR_RAMA_REGION_8_9 0x1198 6022#define regCM3_CM_GAMCOR_RAMA_REGION_8_9_BASE_IDX 2 6023#define regCM3_CM_GAMCOR_RAMA_REGION_10_11 0x1199 6024#define regCM3_CM_GAMCOR_RAMA_REGION_10_11_BASE_IDX 2 6025#define regCM3_CM_GAMCOR_RAMA_REGION_12_13 0x119a 6026#define regCM3_CM_GAMCOR_RAMA_REGION_12_13_BASE_IDX 2 6027#define regCM3_CM_GAMCOR_RAMA_REGION_14_15 0x119b 6028#define regCM3_CM_GAMCOR_RAMA_REGION_14_15_BASE_IDX 2 6029#define regCM3_CM_GAMCOR_RAMA_REGION_16_17 0x119c 6030#define regCM3_CM_GAMCOR_RAMA_REGION_16_17_BASE_IDX 2 6031#define regCM3_CM_GAMCOR_RAMA_REGION_18_19 0x119d 6032#define regCM3_CM_GAMCOR_RAMA_REGION_18_19_BASE_IDX 2 6033#define regCM3_CM_GAMCOR_RAMA_REGION_20_21 0x119e 6034#define regCM3_CM_GAMCOR_RAMA_REGION_20_21_BASE_IDX 2 6035#define regCM3_CM_GAMCOR_RAMA_REGION_22_23 0x119f 6036#define regCM3_CM_GAMCOR_RAMA_REGION_22_23_BASE_IDX 2 6037#define regCM3_CM_GAMCOR_RAMA_REGION_24_25 0x11a0 6038#define regCM3_CM_GAMCOR_RAMA_REGION_24_25_BASE_IDX 2 6039#define regCM3_CM_GAMCOR_RAMA_REGION_26_27 0x11a1 6040#define regCM3_CM_GAMCOR_RAMA_REGION_26_27_BASE_IDX 2 6041#define regCM3_CM_GAMCOR_RAMA_REGION_28_29 0x11a2 6042#define regCM3_CM_GAMCOR_RAMA_REGION_28_29_BASE_IDX 2 6043#define regCM3_CM_GAMCOR_RAMA_REGION_30_31 0x11a3 6044#define regCM3_CM_GAMCOR_RAMA_REGION_30_31_BASE_IDX 2 6045#define regCM3_CM_GAMCOR_RAMA_REGION_32_33 0x11a4 6046#define regCM3_CM_GAMCOR_RAMA_REGION_32_33_BASE_IDX 2 6047#define regCM3_CM_GAMCOR_RAMB_START_CNTL_B 0x11a5 6048#define regCM3_CM_GAMCOR_RAMB_START_CNTL_B_BASE_IDX 2 6049#define regCM3_CM_GAMCOR_RAMB_START_CNTL_G 0x11a6 6050#define regCM3_CM_GAMCOR_RAMB_START_CNTL_G_BASE_IDX 2 6051#define regCM3_CM_GAMCOR_RAMB_START_CNTL_R 0x11a7 6052#define regCM3_CM_GAMCOR_RAMB_START_CNTL_R_BASE_IDX 2 6053#define regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B 0x11a8 6054#define regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B_BASE_IDX 2 6055#define regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G 0x11a9 6056#define regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G_BASE_IDX 2 6057#define regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R 0x11aa 6058#define regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R_BASE_IDX 2 6059#define regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_B 0x11ab 6060#define regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_B_BASE_IDX 2 6061#define regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_G 0x11ac 6062#define regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_G_BASE_IDX 2 6063#define regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_R 0x11ad 6064#define regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_R_BASE_IDX 2 6065#define regCM3_CM_GAMCOR_RAMB_END_CNTL1_B 0x11ae 6066#define regCM3_CM_GAMCOR_RAMB_END_CNTL1_B_BASE_IDX 2 6067#define regCM3_CM_GAMCOR_RAMB_END_CNTL2_B 0x11af 6068#define regCM3_CM_GAMCOR_RAMB_END_CNTL2_B_BASE_IDX 2 6069#define regCM3_CM_GAMCOR_RAMB_END_CNTL1_G 0x11b0 6070#define regCM3_CM_GAMCOR_RAMB_END_CNTL1_G_BASE_IDX 2 6071#define regCM3_CM_GAMCOR_RAMB_END_CNTL2_G 0x11b1 6072#define regCM3_CM_GAMCOR_RAMB_END_CNTL2_G_BASE_IDX 2 6073#define regCM3_CM_GAMCOR_RAMB_END_CNTL1_R 0x11b2 6074#define regCM3_CM_GAMCOR_RAMB_END_CNTL1_R_BASE_IDX 2 6075#define regCM3_CM_GAMCOR_RAMB_END_CNTL2_R 0x11b3 6076#define regCM3_CM_GAMCOR_RAMB_END_CNTL2_R_BASE_IDX 2 6077#define regCM3_CM_GAMCOR_RAMB_OFFSET_B 0x11b4 6078#define regCM3_CM_GAMCOR_RAMB_OFFSET_B_BASE_IDX 2 6079#define regCM3_CM_GAMCOR_RAMB_OFFSET_G 0x11b5 6080#define regCM3_CM_GAMCOR_RAMB_OFFSET_G_BASE_IDX 2 6081#define regCM3_CM_GAMCOR_RAMB_OFFSET_R 0x11b6 6082#define regCM3_CM_GAMCOR_RAMB_OFFSET_R_BASE_IDX 2 6083#define regCM3_CM_GAMCOR_RAMB_REGION_0_1 0x11b7 6084#define regCM3_CM_GAMCOR_RAMB_REGION_0_1_BASE_IDX 2 6085#define regCM3_CM_GAMCOR_RAMB_REGION_2_3 0x11b8 6086#define regCM3_CM_GAMCOR_RAMB_REGION_2_3_BASE_IDX 2 6087#define regCM3_CM_GAMCOR_RAMB_REGION_4_5 0x11b9 6088#define regCM3_CM_GAMCOR_RAMB_REGION_4_5_BASE_IDX 2 6089#define regCM3_CM_GAMCOR_RAMB_REGION_6_7 0x11ba 6090#define regCM3_CM_GAMCOR_RAMB_REGION_6_7_BASE_IDX 2 6091#define regCM3_CM_GAMCOR_RAMB_REGION_8_9 0x11bb 6092#define regCM3_CM_GAMCOR_RAMB_REGION_8_9_BASE_IDX 2 6093#define regCM3_CM_GAMCOR_RAMB_REGION_10_11 0x11bc 6094#define regCM3_CM_GAMCOR_RAMB_REGION_10_11_BASE_IDX 2 6095#define regCM3_CM_GAMCOR_RAMB_REGION_12_13 0x11bd 6096#define regCM3_CM_GAMCOR_RAMB_REGION_12_13_BASE_IDX 2 6097#define regCM3_CM_GAMCOR_RAMB_REGION_14_15 0x11be 6098#define regCM3_CM_GAMCOR_RAMB_REGION_14_15_BASE_IDX 2 6099#define regCM3_CM_GAMCOR_RAMB_REGION_16_17 0x11bf 6100#define regCM3_CM_GAMCOR_RAMB_REGION_16_17_BASE_IDX 2 6101#define regCM3_CM_GAMCOR_RAMB_REGION_18_19 0x11c0 6102#define regCM3_CM_GAMCOR_RAMB_REGION_18_19_BASE_IDX 2 6103#define regCM3_CM_GAMCOR_RAMB_REGION_20_21 0x11c1 6104#define regCM3_CM_GAMCOR_RAMB_REGION_20_21_BASE_IDX 2 6105#define regCM3_CM_GAMCOR_RAMB_REGION_22_23 0x11c2 6106#define regCM3_CM_GAMCOR_RAMB_REGION_22_23_BASE_IDX 2 6107#define regCM3_CM_GAMCOR_RAMB_REGION_24_25 0x11c3 6108#define regCM3_CM_GAMCOR_RAMB_REGION_24_25_BASE_IDX 2 6109#define regCM3_CM_GAMCOR_RAMB_REGION_26_27 0x11c4 6110#define regCM3_CM_GAMCOR_RAMB_REGION_26_27_BASE_IDX 2 6111#define regCM3_CM_GAMCOR_RAMB_REGION_28_29 0x11c5 6112#define regCM3_CM_GAMCOR_RAMB_REGION_28_29_BASE_IDX 2 6113#define regCM3_CM_GAMCOR_RAMB_REGION_30_31 0x11c6 6114#define regCM3_CM_GAMCOR_RAMB_REGION_30_31_BASE_IDX 2 6115#define regCM3_CM_GAMCOR_RAMB_REGION_32_33 0x11c7 6116#define regCM3_CM_GAMCOR_RAMB_REGION_32_33_BASE_IDX 2 6117#define regCM3_CM_BLNDGAM_CONTROL 0x11c8 6118#define regCM3_CM_BLNDGAM_CONTROL_BASE_IDX 2 6119#define regCM3_CM_BLNDGAM_LUT_INDEX 0x11c9 6120#define regCM3_CM_BLNDGAM_LUT_INDEX_BASE_IDX 2 6121#define regCM3_CM_BLNDGAM_LUT_DATA 0x11ca 6122#define regCM3_CM_BLNDGAM_LUT_DATA_BASE_IDX 2 6123#define regCM3_CM_BLNDGAM_LUT_CONTROL 0x11cb 6124#define regCM3_CM_BLNDGAM_LUT_CONTROL_BASE_IDX 2 6125#define regCM3_CM_BLNDGAM_RAMA_START_CNTL_B 0x11cc 6126#define regCM3_CM_BLNDGAM_RAMA_START_CNTL_B_BASE_IDX 2 6127#define regCM3_CM_BLNDGAM_RAMA_START_CNTL_G 0x11cd 6128#define regCM3_CM_BLNDGAM_RAMA_START_CNTL_G_BASE_IDX 2 6129#define regCM3_CM_BLNDGAM_RAMA_START_CNTL_R 0x11ce 6130#define regCM3_CM_BLNDGAM_RAMA_START_CNTL_R_BASE_IDX 2 6131#define regCM3_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B 0x11cf 6132#define regCM3_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX 2 6133#define regCM3_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G 0x11d0 6134#define regCM3_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2 6135#define regCM3_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R 0x11d1 6136#define regCM3_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX 2 6137#define regCM3_CM_BLNDGAM_RAMA_START_BASE_CNTL_B 0x11d2 6138#define regCM3_CM_BLNDGAM_RAMA_START_BASE_CNTL_B_BASE_IDX 2 6139#define regCM3_CM_BLNDGAM_RAMA_START_BASE_CNTL_G 0x11d3 6140#define regCM3_CM_BLNDGAM_RAMA_START_BASE_CNTL_G_BASE_IDX 2 6141#define regCM3_CM_BLNDGAM_RAMA_START_BASE_CNTL_R 0x11d4 6142#define regCM3_CM_BLNDGAM_RAMA_START_BASE_CNTL_R_BASE_IDX 2 6143#define regCM3_CM_BLNDGAM_RAMA_END_CNTL1_B 0x11d5 6144#define regCM3_CM_BLNDGAM_RAMA_END_CNTL1_B_BASE_IDX 2 6145#define regCM3_CM_BLNDGAM_RAMA_END_CNTL2_B 0x11d6 6146#define regCM3_CM_BLNDGAM_RAMA_END_CNTL2_B_BASE_IDX 2 6147#define regCM3_CM_BLNDGAM_RAMA_END_CNTL1_G 0x11d7 6148#define regCM3_CM_BLNDGAM_RAMA_END_CNTL1_G_BASE_IDX 2 6149#define regCM3_CM_BLNDGAM_RAMA_END_CNTL2_G 0x11d8 6150#define regCM3_CM_BLNDGAM_RAMA_END_CNTL2_G_BASE_IDX 2 6151#define regCM3_CM_BLNDGAM_RAMA_END_CNTL1_R 0x11d9 6152#define regCM3_CM_BLNDGAM_RAMA_END_CNTL1_R_BASE_IDX 2 6153#define regCM3_CM_BLNDGAM_RAMA_END_CNTL2_R 0x11da 6154#define regCM3_CM_BLNDGAM_RAMA_END_CNTL2_R_BASE_IDX 2 6155#define regCM3_CM_BLNDGAM_RAMA_OFFSET_B 0x11db 6156#define regCM3_CM_BLNDGAM_RAMA_OFFSET_B_BASE_IDX 2 6157#define regCM3_CM_BLNDGAM_RAMA_OFFSET_G 0x11dc 6158#define regCM3_CM_BLNDGAM_RAMA_OFFSET_G_BASE_IDX 2 6159#define regCM3_CM_BLNDGAM_RAMA_OFFSET_R 0x11dd 6160#define regCM3_CM_BLNDGAM_RAMA_OFFSET_R_BASE_IDX 2 6161#define regCM3_CM_BLNDGAM_RAMA_REGION_0_1 0x11de 6162#define regCM3_CM_BLNDGAM_RAMA_REGION_0_1_BASE_IDX 2 6163#define regCM3_CM_BLNDGAM_RAMA_REGION_2_3 0x11df 6164#define regCM3_CM_BLNDGAM_RAMA_REGION_2_3_BASE_IDX 2 6165#define regCM3_CM_BLNDGAM_RAMA_REGION_4_5 0x11e0 6166#define regCM3_CM_BLNDGAM_RAMA_REGION_4_5_BASE_IDX 2 6167#define regCM3_CM_BLNDGAM_RAMA_REGION_6_7 0x11e1 6168#define regCM3_CM_BLNDGAM_RAMA_REGION_6_7_BASE_IDX 2 6169#define regCM3_CM_BLNDGAM_RAMA_REGION_8_9 0x11e2 6170#define regCM3_CM_BLNDGAM_RAMA_REGION_8_9_BASE_IDX 2 6171#define regCM3_CM_BLNDGAM_RAMA_REGION_10_11 0x11e3 6172#define regCM3_CM_BLNDGAM_RAMA_REGION_10_11_BASE_IDX 2 6173#define regCM3_CM_BLNDGAM_RAMA_REGION_12_13 0x11e4 6174#define regCM3_CM_BLNDGAM_RAMA_REGION_12_13_BASE_IDX 2 6175#define regCM3_CM_BLNDGAM_RAMA_REGION_14_15 0x11e5 6176#define regCM3_CM_BLNDGAM_RAMA_REGION_14_15_BASE_IDX 2 6177#define regCM3_CM_BLNDGAM_RAMA_REGION_16_17 0x11e6 6178#define regCM3_CM_BLNDGAM_RAMA_REGION_16_17_BASE_IDX 2 6179#define regCM3_CM_BLNDGAM_RAMA_REGION_18_19 0x11e7 6180#define regCM3_CM_BLNDGAM_RAMA_REGION_18_19_BASE_IDX 2 6181#define regCM3_CM_BLNDGAM_RAMA_REGION_20_21 0x11e8 6182#define regCM3_CM_BLNDGAM_RAMA_REGION_20_21_BASE_IDX 2 6183#define regCM3_CM_BLNDGAM_RAMA_REGION_22_23 0x11e9 6184#define regCM3_CM_BLNDGAM_RAMA_REGION_22_23_BASE_IDX 2 6185#define regCM3_CM_BLNDGAM_RAMA_REGION_24_25 0x11ea 6186#define regCM3_CM_BLNDGAM_RAMA_REGION_24_25_BASE_IDX 2 6187#define regCM3_CM_BLNDGAM_RAMA_REGION_26_27 0x11eb 6188#define regCM3_CM_BLNDGAM_RAMA_REGION_26_27_BASE_IDX 2 6189#define regCM3_CM_BLNDGAM_RAMA_REGION_28_29 0x11ec 6190#define regCM3_CM_BLNDGAM_RAMA_REGION_28_29_BASE_IDX 2 6191#define regCM3_CM_BLNDGAM_RAMA_REGION_30_31 0x11ed 6192#define regCM3_CM_BLNDGAM_RAMA_REGION_30_31_BASE_IDX 2 6193#define regCM3_CM_BLNDGAM_RAMA_REGION_32_33 0x11ee 6194#define regCM3_CM_BLNDGAM_RAMA_REGION_32_33_BASE_IDX 2 6195#define regCM3_CM_BLNDGAM_RAMB_START_CNTL_B 0x11ef 6196#define regCM3_CM_BLNDGAM_RAMB_START_CNTL_B_BASE_IDX 2 6197#define regCM3_CM_BLNDGAM_RAMB_START_CNTL_G 0x11f0 6198#define regCM3_CM_BLNDGAM_RAMB_START_CNTL_G_BASE_IDX 2 6199#define regCM3_CM_BLNDGAM_RAMB_START_CNTL_R 0x11f1 6200#define regCM3_CM_BLNDGAM_RAMB_START_CNTL_R_BASE_IDX 2 6201#define regCM3_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B 0x11f2 6202#define regCM3_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX 2 6203#define regCM3_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G 0x11f3 6204#define regCM3_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX 2 6205#define regCM3_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R 0x11f4 6206#define regCM3_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX 2 6207#define regCM3_CM_BLNDGAM_RAMB_START_BASE_CNTL_B 0x11f5 6208#define regCM3_CM_BLNDGAM_RAMB_START_BASE_CNTL_B_BASE_IDX 2 6209#define regCM3_CM_BLNDGAM_RAMB_START_BASE_CNTL_G 0x11f6 6210#define regCM3_CM_BLNDGAM_RAMB_START_BASE_CNTL_G_BASE_IDX 2 6211#define regCM3_CM_BLNDGAM_RAMB_START_BASE_CNTL_R 0x11f7 6212#define regCM3_CM_BLNDGAM_RAMB_START_BASE_CNTL_R_BASE_IDX 2 6213#define regCM3_CM_BLNDGAM_RAMB_END_CNTL1_B 0x11f8 6214#define regCM3_CM_BLNDGAM_RAMB_END_CNTL1_B_BASE_IDX 2 6215#define regCM3_CM_BLNDGAM_RAMB_END_CNTL2_B 0x11f9 6216#define regCM3_CM_BLNDGAM_RAMB_END_CNTL2_B_BASE_IDX 2 6217#define regCM3_CM_BLNDGAM_RAMB_END_CNTL1_G 0x11fa 6218#define regCM3_CM_BLNDGAM_RAMB_END_CNTL1_G_BASE_IDX 2 6219#define regCM3_CM_BLNDGAM_RAMB_END_CNTL2_G 0x11fb 6220#define regCM3_CM_BLNDGAM_RAMB_END_CNTL2_G_BASE_IDX 2 6221#define regCM3_CM_BLNDGAM_RAMB_END_CNTL1_R 0x11fc 6222#define regCM3_CM_BLNDGAM_RAMB_END_CNTL1_R_BASE_IDX 2 6223#define regCM3_CM_BLNDGAM_RAMB_END_CNTL2_R 0x11fd 6224#define regCM3_CM_BLNDGAM_RAMB_END_CNTL2_R_BASE_IDX 2 6225#define regCM3_CM_BLNDGAM_RAMB_OFFSET_B 0x11fe 6226#define regCM3_CM_BLNDGAM_RAMB_OFFSET_B_BASE_IDX 2 6227#define regCM3_CM_BLNDGAM_RAMB_OFFSET_G 0x11ff 6228#define regCM3_CM_BLNDGAM_RAMB_OFFSET_G_BASE_IDX 2 6229#define regCM3_CM_BLNDGAM_RAMB_OFFSET_R 0x1200 6230#define regCM3_CM_BLNDGAM_RAMB_OFFSET_R_BASE_IDX 2 6231#define regCM3_CM_BLNDGAM_RAMB_REGION_0_1 0x1201 6232#define regCM3_CM_BLNDGAM_RAMB_REGION_0_1_BASE_IDX 2 6233#define regCM3_CM_BLNDGAM_RAMB_REGION_2_3 0x1202 6234#define regCM3_CM_BLNDGAM_RAMB_REGION_2_3_BASE_IDX 2 6235#define regCM3_CM_BLNDGAM_RAMB_REGION_4_5 0x1203 6236#define regCM3_CM_BLNDGAM_RAMB_REGION_4_5_BASE_IDX 2 6237#define regCM3_CM_BLNDGAM_RAMB_REGION_6_7 0x1204 6238#define regCM3_CM_BLNDGAM_RAMB_REGION_6_7_BASE_IDX 2 6239#define regCM3_CM_BLNDGAM_RAMB_REGION_8_9 0x1205 6240#define regCM3_CM_BLNDGAM_RAMB_REGION_8_9_BASE_IDX 2 6241#define regCM3_CM_BLNDGAM_RAMB_REGION_10_11 0x1206 6242#define regCM3_CM_BLNDGAM_RAMB_REGION_10_11_BASE_IDX 2 6243#define regCM3_CM_BLNDGAM_RAMB_REGION_12_13 0x1207 6244#define regCM3_CM_BLNDGAM_RAMB_REGION_12_13_BASE_IDX 2 6245#define regCM3_CM_BLNDGAM_RAMB_REGION_14_15 0x1208 6246#define regCM3_CM_BLNDGAM_RAMB_REGION_14_15_BASE_IDX 2 6247#define regCM3_CM_BLNDGAM_RAMB_REGION_16_17 0x1209 6248#define regCM3_CM_BLNDGAM_RAMB_REGION_16_17_BASE_IDX 2 6249#define regCM3_CM_BLNDGAM_RAMB_REGION_18_19 0x120a 6250#define regCM3_CM_BLNDGAM_RAMB_REGION_18_19_BASE_IDX 2 6251#define regCM3_CM_BLNDGAM_RAMB_REGION_20_21 0x120b 6252#define regCM3_CM_BLNDGAM_RAMB_REGION_20_21_BASE_IDX 2 6253#define regCM3_CM_BLNDGAM_RAMB_REGION_22_23 0x120c 6254#define regCM3_CM_BLNDGAM_RAMB_REGION_22_23_BASE_IDX 2 6255#define regCM3_CM_BLNDGAM_RAMB_REGION_24_25 0x120d 6256#define regCM3_CM_BLNDGAM_RAMB_REGION_24_25_BASE_IDX 2 6257#define regCM3_CM_BLNDGAM_RAMB_REGION_26_27 0x120e 6258#define regCM3_CM_BLNDGAM_RAMB_REGION_26_27_BASE_IDX 2 6259#define regCM3_CM_BLNDGAM_RAMB_REGION_28_29 0x120f 6260#define regCM3_CM_BLNDGAM_RAMB_REGION_28_29_BASE_IDX 2 6261#define regCM3_CM_BLNDGAM_RAMB_REGION_30_31 0x1210 6262#define regCM3_CM_BLNDGAM_RAMB_REGION_30_31_BASE_IDX 2 6263#define regCM3_CM_BLNDGAM_RAMB_REGION_32_33 0x1211 6264#define regCM3_CM_BLNDGAM_RAMB_REGION_32_33_BASE_IDX 2 6265#define regCM3_CM_HDR_MULT_COEF 0x1212 6266#define regCM3_CM_HDR_MULT_COEF_BASE_IDX 2 6267#define regCM3_CM_MEM_PWR_CTRL 0x1213 6268#define regCM3_CM_MEM_PWR_CTRL_BASE_IDX 2 6269#define regCM3_CM_MEM_PWR_STATUS 0x1214 6270#define regCM3_CM_MEM_PWR_STATUS_BASE_IDX 2 6271#define regCM3_CM_DEALPHA 0x1216 6272#define regCM3_CM_DEALPHA_BASE_IDX 2 6273#define regCM3_CM_COEF_FORMAT 0x1217 6274#define regCM3_CM_COEF_FORMAT_BASE_IDX 2 6275#define regCM3_CM_SHAPER_CONTROL 0x1218 6276#define regCM3_CM_SHAPER_CONTROL_BASE_IDX 2 6277#define regCM3_CM_SHAPER_OFFSET_R 0x1219 6278#define regCM3_CM_SHAPER_OFFSET_R_BASE_IDX 2 6279#define regCM3_CM_SHAPER_OFFSET_G 0x121a 6280#define regCM3_CM_SHAPER_OFFSET_G_BASE_IDX 2 6281#define regCM3_CM_SHAPER_OFFSET_B 0x121b 6282#define regCM3_CM_SHAPER_OFFSET_B_BASE_IDX 2 6283#define regCM3_CM_SHAPER_SCALE_R 0x121c 6284#define regCM3_CM_SHAPER_SCALE_R_BASE_IDX 2 6285#define regCM3_CM_SHAPER_SCALE_G_B 0x121d 6286#define regCM3_CM_SHAPER_SCALE_G_B_BASE_IDX 2 6287#define regCM3_CM_SHAPER_LUT_INDEX 0x121e 6288#define regCM3_CM_SHAPER_LUT_INDEX_BASE_IDX 2 6289#define regCM3_CM_SHAPER_LUT_DATA 0x121f 6290#define regCM3_CM_SHAPER_LUT_DATA_BASE_IDX 2 6291#define regCM3_CM_SHAPER_LUT_WRITE_EN_MASK 0x1220 6292#define regCM3_CM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX 2 6293#define regCM3_CM_SHAPER_RAMA_START_CNTL_B 0x1221 6294#define regCM3_CM_SHAPER_RAMA_START_CNTL_B_BASE_IDX 2 6295#define regCM3_CM_SHAPER_RAMA_START_CNTL_G 0x1222 6296#define regCM3_CM_SHAPER_RAMA_START_CNTL_G_BASE_IDX 2 6297#define regCM3_CM_SHAPER_RAMA_START_CNTL_R 0x1223 6298#define regCM3_CM_SHAPER_RAMA_START_CNTL_R_BASE_IDX 2 6299#define regCM3_CM_SHAPER_RAMA_END_CNTL_B 0x1224 6300#define regCM3_CM_SHAPER_RAMA_END_CNTL_B_BASE_IDX 2 6301#define regCM3_CM_SHAPER_RAMA_END_CNTL_G 0x1225 6302#define regCM3_CM_SHAPER_RAMA_END_CNTL_G_BASE_IDX 2 6303#define regCM3_CM_SHAPER_RAMA_END_CNTL_R 0x1226 6304#define regCM3_CM_SHAPER_RAMA_END_CNTL_R_BASE_IDX 2 6305#define regCM3_CM_SHAPER_RAMA_REGION_0_1 0x1227 6306#define regCM3_CM_SHAPER_RAMA_REGION_0_1_BASE_IDX 2 6307#define regCM3_CM_SHAPER_RAMA_REGION_2_3 0x1228 6308#define regCM3_CM_SHAPER_RAMA_REGION_2_3_BASE_IDX 2 6309#define regCM3_CM_SHAPER_RAMA_REGION_4_5 0x1229 6310#define regCM3_CM_SHAPER_RAMA_REGION_4_5_BASE_IDX 2 6311#define regCM3_CM_SHAPER_RAMA_REGION_6_7 0x122a 6312#define regCM3_CM_SHAPER_RAMA_REGION_6_7_BASE_IDX 2 6313#define regCM3_CM_SHAPER_RAMA_REGION_8_9 0x122b 6314#define regCM3_CM_SHAPER_RAMA_REGION_8_9_BASE_IDX 2 6315#define regCM3_CM_SHAPER_RAMA_REGION_10_11 0x122c 6316#define regCM3_CM_SHAPER_RAMA_REGION_10_11_BASE_IDX 2 6317#define regCM3_CM_SHAPER_RAMA_REGION_12_13 0x122d 6318#define regCM3_CM_SHAPER_RAMA_REGION_12_13_BASE_IDX 2 6319#define regCM3_CM_SHAPER_RAMA_REGION_14_15 0x122e 6320#define regCM3_CM_SHAPER_RAMA_REGION_14_15_BASE_IDX 2 6321#define regCM3_CM_SHAPER_RAMA_REGION_16_17 0x122f 6322#define regCM3_CM_SHAPER_RAMA_REGION_16_17_BASE_IDX 2 6323#define regCM3_CM_SHAPER_RAMA_REGION_18_19 0x1230 6324#define regCM3_CM_SHAPER_RAMA_REGION_18_19_BASE_IDX 2 6325#define regCM3_CM_SHAPER_RAMA_REGION_20_21 0x1231 6326#define regCM3_CM_SHAPER_RAMA_REGION_20_21_BASE_IDX 2 6327#define regCM3_CM_SHAPER_RAMA_REGION_22_23 0x1232 6328#define regCM3_CM_SHAPER_RAMA_REGION_22_23_BASE_IDX 2 6329#define regCM3_CM_SHAPER_RAMA_REGION_24_25 0x1233 6330#define regCM3_CM_SHAPER_RAMA_REGION_24_25_BASE_IDX 2 6331#define regCM3_CM_SHAPER_RAMA_REGION_26_27 0x1234 6332#define regCM3_CM_SHAPER_RAMA_REGION_26_27_BASE_IDX 2 6333#define regCM3_CM_SHAPER_RAMA_REGION_28_29 0x1235 6334#define regCM3_CM_SHAPER_RAMA_REGION_28_29_BASE_IDX 2 6335#define regCM3_CM_SHAPER_RAMA_REGION_30_31 0x1236 6336#define regCM3_CM_SHAPER_RAMA_REGION_30_31_BASE_IDX 2 6337#define regCM3_CM_SHAPER_RAMA_REGION_32_33 0x1237 6338#define regCM3_CM_SHAPER_RAMA_REGION_32_33_BASE_IDX 2 6339#define regCM3_CM_SHAPER_RAMB_START_CNTL_B 0x1238 6340#define regCM3_CM_SHAPER_RAMB_START_CNTL_B_BASE_IDX 2 6341#define regCM3_CM_SHAPER_RAMB_START_CNTL_G 0x1239 6342#define regCM3_CM_SHAPER_RAMB_START_CNTL_G_BASE_IDX 2 6343#define regCM3_CM_SHAPER_RAMB_START_CNTL_R 0x123a 6344#define regCM3_CM_SHAPER_RAMB_START_CNTL_R_BASE_IDX 2 6345#define regCM3_CM_SHAPER_RAMB_END_CNTL_B 0x123b 6346#define regCM3_CM_SHAPER_RAMB_END_CNTL_B_BASE_IDX 2 6347#define regCM3_CM_SHAPER_RAMB_END_CNTL_G 0x123c 6348#define regCM3_CM_SHAPER_RAMB_END_CNTL_G_BASE_IDX 2 6349#define regCM3_CM_SHAPER_RAMB_END_CNTL_R 0x123d 6350#define regCM3_CM_SHAPER_RAMB_END_CNTL_R_BASE_IDX 2 6351#define regCM3_CM_SHAPER_RAMB_REGION_0_1 0x123e 6352#define regCM3_CM_SHAPER_RAMB_REGION_0_1_BASE_IDX 2 6353#define regCM3_CM_SHAPER_RAMB_REGION_2_3 0x123f 6354#define regCM3_CM_SHAPER_RAMB_REGION_2_3_BASE_IDX 2 6355#define regCM3_CM_SHAPER_RAMB_REGION_4_5 0x1240 6356#define regCM3_CM_SHAPER_RAMB_REGION_4_5_BASE_IDX 2 6357#define regCM3_CM_SHAPER_RAMB_REGION_6_7 0x1241 6358#define regCM3_CM_SHAPER_RAMB_REGION_6_7_BASE_IDX 2 6359#define regCM3_CM_SHAPER_RAMB_REGION_8_9 0x1242 6360#define regCM3_CM_SHAPER_RAMB_REGION_8_9_BASE_IDX 2 6361#define regCM3_CM_SHAPER_RAMB_REGION_10_11 0x1243 6362#define regCM3_CM_SHAPER_RAMB_REGION_10_11_BASE_IDX 2 6363#define regCM3_CM_SHAPER_RAMB_REGION_12_13 0x1244 6364#define regCM3_CM_SHAPER_RAMB_REGION_12_13_BASE_IDX 2 6365#define regCM3_CM_SHAPER_RAMB_REGION_14_15 0x1245 6366#define regCM3_CM_SHAPER_RAMB_REGION_14_15_BASE_IDX 2 6367#define regCM3_CM_SHAPER_RAMB_REGION_16_17 0x1246 6368#define regCM3_CM_SHAPER_RAMB_REGION_16_17_BASE_IDX 2 6369#define regCM3_CM_SHAPER_RAMB_REGION_18_19 0x1247 6370#define regCM3_CM_SHAPER_RAMB_REGION_18_19_BASE_IDX 2 6371#define regCM3_CM_SHAPER_RAMB_REGION_20_21 0x1248 6372#define regCM3_CM_SHAPER_RAMB_REGION_20_21_BASE_IDX 2 6373#define regCM3_CM_SHAPER_RAMB_REGION_22_23 0x1249 6374#define regCM3_CM_SHAPER_RAMB_REGION_22_23_BASE_IDX 2 6375#define regCM3_CM_SHAPER_RAMB_REGION_24_25 0x124a 6376#define regCM3_CM_SHAPER_RAMB_REGION_24_25_BASE_IDX 2 6377#define regCM3_CM_SHAPER_RAMB_REGION_26_27 0x124b 6378#define regCM3_CM_SHAPER_RAMB_REGION_26_27_BASE_IDX 2 6379#define regCM3_CM_SHAPER_RAMB_REGION_28_29 0x124c 6380#define regCM3_CM_SHAPER_RAMB_REGION_28_29_BASE_IDX 2 6381#define regCM3_CM_SHAPER_RAMB_REGION_30_31 0x124d 6382#define regCM3_CM_SHAPER_RAMB_REGION_30_31_BASE_IDX 2 6383#define regCM3_CM_SHAPER_RAMB_REGION_32_33 0x124e 6384#define regCM3_CM_SHAPER_RAMB_REGION_32_33_BASE_IDX 2 6385#define regCM3_CM_MEM_PWR_CTRL2 0x124f 6386#define regCM3_CM_MEM_PWR_CTRL2_BASE_IDX 2 6387#define regCM3_CM_MEM_PWR_STATUS2 0x1250 6388#define regCM3_CM_MEM_PWR_STATUS2_BASE_IDX 2 6389#define regCM3_CM_3DLUT_MODE 0x1251 6390#define regCM3_CM_3DLUT_MODE_BASE_IDX 2 6391#define regCM3_CM_3DLUT_INDEX 0x1252 6392#define regCM3_CM_3DLUT_INDEX_BASE_IDX 2 6393#define regCM3_CM_3DLUT_DATA 0x1253 6394#define regCM3_CM_3DLUT_DATA_BASE_IDX 2 6395#define regCM3_CM_3DLUT_DATA_30BIT 0x1254 6396#define regCM3_CM_3DLUT_DATA_30BIT_BASE_IDX 2 6397#define regCM3_CM_3DLUT_READ_WRITE_CONTROL 0x1255 6398#define regCM3_CM_3DLUT_READ_WRITE_CONTROL_BASE_IDX 2 6399#define regCM3_CM_3DLUT_OUT_NORM_FACTOR 0x1256 6400#define regCM3_CM_3DLUT_OUT_NORM_FACTOR_BASE_IDX 2 6401#define regCM3_CM_3DLUT_OUT_OFFSET_R 0x1257 6402#define regCM3_CM_3DLUT_OUT_OFFSET_R_BASE_IDX 2 6403#define regCM3_CM_3DLUT_OUT_OFFSET_G 0x1258 6404#define regCM3_CM_3DLUT_OUT_OFFSET_G_BASE_IDX 2 6405#define regCM3_CM_3DLUT_OUT_OFFSET_B 0x1259 6406#define regCM3_CM_3DLUT_OUT_OFFSET_B_BASE_IDX 2 6407#define regCM3_CM_TEST_DEBUG_INDEX 0x125a 6408#define regCM3_CM_TEST_DEBUG_INDEX_BASE_IDX 2 6409#define regCM3_CM_TEST_DEBUG_DATA 0x125b 6410#define regCM3_CM_TEST_DEBUG_DATA_BASE_IDX 2 6411 6412 6413// addressBlock: dce_dc_dpp3_dispdec_dpp_top_dispdec 6414// base address: 0x1104 6415#define regDPP_TOP3_DPP_CONTROL 0x1106 6416#define regDPP_TOP3_DPP_CONTROL_BASE_IDX 2 6417#define regDPP_TOP3_DPP_SOFT_RESET 0x1107 6418#define regDPP_TOP3_DPP_SOFT_RESET_BASE_IDX 2 6419#define regDPP_TOP3_DPP_CRC_VAL_R_G 0x1108 6420#define regDPP_TOP3_DPP_CRC_VAL_R_G_BASE_IDX 2 6421#define regDPP_TOP3_DPP_CRC_VAL_B_A 0x1109 6422#define regDPP_TOP3_DPP_CRC_VAL_B_A_BASE_IDX 2 6423#define regDPP_TOP3_DPP_CRC_CTRL 0x110a 6424#define regDPP_TOP3_DPP_CRC_CTRL_BASE_IDX 2 6425#define regDPP_TOP3_HOST_READ_CONTROL 0x110b 6426#define regDPP_TOP3_HOST_READ_CONTROL_BASE_IDX 2 6427 6428 6429// addressBlock: dce_dc_dpp3_dispdec_dpp_dcperfmon_dc_perfmon_dispdec 6430// base address: 0x4994 6431#define regDC_PERFMON14_PERFCOUNTER_CNTL 0x1265 6432#define regDC_PERFMON14_PERFCOUNTER_CNTL_BASE_IDX 2 6433#define regDC_PERFMON14_PERFCOUNTER_CNTL2 0x1266 6434#define regDC_PERFMON14_PERFCOUNTER_CNTL2_BASE_IDX 2 6435#define regDC_PERFMON14_PERFCOUNTER_STATE 0x1267 6436#define regDC_PERFMON14_PERFCOUNTER_STATE_BASE_IDX 2 6437#define regDC_PERFMON14_PERFMON_CNTL 0x1268 6438#define regDC_PERFMON14_PERFMON_CNTL_BASE_IDX 2 6439#define regDC_PERFMON14_PERFMON_CNTL2 0x1269 6440#define regDC_PERFMON14_PERFMON_CNTL2_BASE_IDX 2 6441#define regDC_PERFMON14_PERFMON_CVALUE_INT_MISC 0x126a 6442#define regDC_PERFMON14_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 6443#define regDC_PERFMON14_PERFMON_CVALUE_LOW 0x126b 6444#define regDC_PERFMON14_PERFMON_CVALUE_LOW_BASE_IDX 2 6445#define regDC_PERFMON14_PERFMON_HI 0x126c 6446#define regDC_PERFMON14_PERFMON_HI_BASE_IDX 2 6447#define regDC_PERFMON14_PERFMON_LOW 0x126d 6448#define regDC_PERFMON14_PERFMON_LOW_BASE_IDX 2 6449 6450 6451// addressBlock: dce_dc_mpc_mpcc0_dispdec 6452// base address: 0x0 6453#define regMPCC0_MPCC_TOP_SEL 0x0000 6454#define regMPCC0_MPCC_TOP_SEL_BASE_IDX 3 6455#define regMPCC0_MPCC_BOT_SEL 0x0001 6456#define regMPCC0_MPCC_BOT_SEL_BASE_IDX 3 6457#define regMPCC0_MPCC_OPP_ID 0x0002 6458#define regMPCC0_MPCC_OPP_ID_BASE_IDX 3 6459#define regMPCC0_MPCC_CONTROL 0x0003 6460#define regMPCC0_MPCC_CONTROL_BASE_IDX 3 6461#define regMPCC0_MPCC_SM_CONTROL 0x0004 6462#define regMPCC0_MPCC_SM_CONTROL_BASE_IDX 3 6463#define regMPCC0_MPCC_UPDATE_LOCK_SEL 0x0005 6464#define regMPCC0_MPCC_UPDATE_LOCK_SEL_BASE_IDX 3 6465#define regMPCC0_MPCC_TOP_GAIN 0x0006 6466#define regMPCC0_MPCC_TOP_GAIN_BASE_IDX 3 6467#define regMPCC0_MPCC_BOT_GAIN_INSIDE 0x0007 6468#define regMPCC0_MPCC_BOT_GAIN_INSIDE_BASE_IDX 3 6469#define regMPCC0_MPCC_BOT_GAIN_OUTSIDE 0x0008 6470#define regMPCC0_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX 3 6471#define regMPCC0_MPCC_BG_R_CR 0x0009 6472#define regMPCC0_MPCC_BG_R_CR_BASE_IDX 3 6473#define regMPCC0_MPCC_BG_G_Y 0x000a 6474#define regMPCC0_MPCC_BG_G_Y_BASE_IDX 3 6475#define regMPCC0_MPCC_BG_B_CB 0x000b 6476#define regMPCC0_MPCC_BG_B_CB_BASE_IDX 3 6477#define regMPCC0_MPCC_MEM_PWR_CTRL 0x000c 6478#define regMPCC0_MPCC_MEM_PWR_CTRL_BASE_IDX 3 6479#define regMPCC0_MPCC_STATUS 0x000d 6480#define regMPCC0_MPCC_STATUS_BASE_IDX 3 6481 6482 6483// addressBlock: dce_dc_mpc_mpcc1_dispdec 6484// base address: 0x80 6485#define regMPCC1_MPCC_TOP_SEL 0x0020 6486#define regMPCC1_MPCC_TOP_SEL_BASE_IDX 3 6487#define regMPCC1_MPCC_BOT_SEL 0x0021 6488#define regMPCC1_MPCC_BOT_SEL_BASE_IDX 3 6489#define regMPCC1_MPCC_OPP_ID 0x0022 6490#define regMPCC1_MPCC_OPP_ID_BASE_IDX 3 6491#define regMPCC1_MPCC_CONTROL 0x0023 6492#define regMPCC1_MPCC_CONTROL_BASE_IDX 3 6493#define regMPCC1_MPCC_SM_CONTROL 0x0024 6494#define regMPCC1_MPCC_SM_CONTROL_BASE_IDX 3 6495#define regMPCC1_MPCC_UPDATE_LOCK_SEL 0x0025 6496#define regMPCC1_MPCC_UPDATE_LOCK_SEL_BASE_IDX 3 6497#define regMPCC1_MPCC_TOP_GAIN 0x0026 6498#define regMPCC1_MPCC_TOP_GAIN_BASE_IDX 3 6499#define regMPCC1_MPCC_BOT_GAIN_INSIDE 0x0027 6500#define regMPCC1_MPCC_BOT_GAIN_INSIDE_BASE_IDX 3 6501#define regMPCC1_MPCC_BOT_GAIN_OUTSIDE 0x0028 6502#define regMPCC1_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX 3 6503#define regMPCC1_MPCC_BG_R_CR 0x0029 6504#define regMPCC1_MPCC_BG_R_CR_BASE_IDX 3 6505#define regMPCC1_MPCC_BG_G_Y 0x002a 6506#define regMPCC1_MPCC_BG_G_Y_BASE_IDX 3 6507#define regMPCC1_MPCC_BG_B_CB 0x002b 6508#define regMPCC1_MPCC_BG_B_CB_BASE_IDX 3 6509#define regMPCC1_MPCC_MEM_PWR_CTRL 0x002c 6510#define regMPCC1_MPCC_MEM_PWR_CTRL_BASE_IDX 3 6511#define regMPCC1_MPCC_STATUS 0x002d 6512#define regMPCC1_MPCC_STATUS_BASE_IDX 3 6513 6514 6515// addressBlock: dce_dc_mpc_mpcc2_dispdec 6516// base address: 0x100 6517#define regMPCC2_MPCC_TOP_SEL 0x0040 6518#define regMPCC2_MPCC_TOP_SEL_BASE_IDX 3 6519#define regMPCC2_MPCC_BOT_SEL 0x0041 6520#define regMPCC2_MPCC_BOT_SEL_BASE_IDX 3 6521#define regMPCC2_MPCC_OPP_ID 0x0042 6522#define regMPCC2_MPCC_OPP_ID_BASE_IDX 3 6523#define regMPCC2_MPCC_CONTROL 0x0043 6524#define regMPCC2_MPCC_CONTROL_BASE_IDX 3 6525#define regMPCC2_MPCC_SM_CONTROL 0x0044 6526#define regMPCC2_MPCC_SM_CONTROL_BASE_IDX 3 6527#define regMPCC2_MPCC_UPDATE_LOCK_SEL 0x0045 6528#define regMPCC2_MPCC_UPDATE_LOCK_SEL_BASE_IDX 3 6529#define regMPCC2_MPCC_TOP_GAIN 0x0046 6530#define regMPCC2_MPCC_TOP_GAIN_BASE_IDX 3 6531#define regMPCC2_MPCC_BOT_GAIN_INSIDE 0x0047 6532#define regMPCC2_MPCC_BOT_GAIN_INSIDE_BASE_IDX 3 6533#define regMPCC2_MPCC_BOT_GAIN_OUTSIDE 0x0048 6534#define regMPCC2_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX 3 6535#define regMPCC2_MPCC_BG_R_CR 0x0049 6536#define regMPCC2_MPCC_BG_R_CR_BASE_IDX 3 6537#define regMPCC2_MPCC_BG_G_Y 0x004a 6538#define regMPCC2_MPCC_BG_G_Y_BASE_IDX 3 6539#define regMPCC2_MPCC_BG_B_CB 0x004b 6540#define regMPCC2_MPCC_BG_B_CB_BASE_IDX 3 6541#define regMPCC2_MPCC_MEM_PWR_CTRL 0x004c 6542#define regMPCC2_MPCC_MEM_PWR_CTRL_BASE_IDX 3 6543#define regMPCC2_MPCC_STATUS 0x004d 6544#define regMPCC2_MPCC_STATUS_BASE_IDX 3 6545 6546 6547// addressBlock: dce_dc_mpc_mpcc3_dispdec 6548// base address: 0x180 6549#define regMPCC3_MPCC_TOP_SEL 0x0060 6550#define regMPCC3_MPCC_TOP_SEL_BASE_IDX 3 6551#define regMPCC3_MPCC_BOT_SEL 0x0061 6552#define regMPCC3_MPCC_BOT_SEL_BASE_IDX 3 6553#define regMPCC3_MPCC_OPP_ID 0x0062 6554#define regMPCC3_MPCC_OPP_ID_BASE_IDX 3 6555#define regMPCC3_MPCC_CONTROL 0x0063 6556#define regMPCC3_MPCC_CONTROL_BASE_IDX 3 6557#define regMPCC3_MPCC_SM_CONTROL 0x0064 6558#define regMPCC3_MPCC_SM_CONTROL_BASE_IDX 3 6559#define regMPCC3_MPCC_UPDATE_LOCK_SEL 0x0065 6560#define regMPCC3_MPCC_UPDATE_LOCK_SEL_BASE_IDX 3 6561#define regMPCC3_MPCC_TOP_GAIN 0x0066 6562#define regMPCC3_MPCC_TOP_GAIN_BASE_IDX 3 6563#define regMPCC3_MPCC_BOT_GAIN_INSIDE 0x0067 6564#define regMPCC3_MPCC_BOT_GAIN_INSIDE_BASE_IDX 3 6565#define regMPCC3_MPCC_BOT_GAIN_OUTSIDE 0x0068 6566#define regMPCC3_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX 3 6567#define regMPCC3_MPCC_BG_R_CR 0x0069 6568#define regMPCC3_MPCC_BG_R_CR_BASE_IDX 3 6569#define regMPCC3_MPCC_BG_G_Y 0x006a 6570#define regMPCC3_MPCC_BG_G_Y_BASE_IDX 3 6571#define regMPCC3_MPCC_BG_B_CB 0x006b 6572#define regMPCC3_MPCC_BG_B_CB_BASE_IDX 3 6573#define regMPCC3_MPCC_MEM_PWR_CTRL 0x006c 6574#define regMPCC3_MPCC_MEM_PWR_CTRL_BASE_IDX 3 6575#define regMPCC3_MPCC_STATUS 0x006d 6576#define regMPCC3_MPCC_STATUS_BASE_IDX 3 6577 6578 6579// addressBlock: dce_dc_mpc_mpc_cfg_dispdec 6580// base address: 0x0 6581#define regMPC_CLOCK_CONTROL 0x0500 6582#define regMPC_CLOCK_CONTROL_BASE_IDX 3 6583#define regMPC_SOFT_RESET 0x0501 6584#define regMPC_SOFT_RESET_BASE_IDX 3 6585#define regMPC_CRC_CTRL 0x0502 6586#define regMPC_CRC_CTRL_BASE_IDX 3 6587#define regMPC_CRC_SEL_CONTROL 0x0503 6588#define regMPC_CRC_SEL_CONTROL_BASE_IDX 3 6589#define regMPC_CRC_RESULT_AR 0x0504 6590#define regMPC_CRC_RESULT_AR_BASE_IDX 3 6591#define regMPC_CRC_RESULT_GB 0x0505 6592#define regMPC_CRC_RESULT_GB_BASE_IDX 3 6593#define regMPC_CRC_RESULT_C 0x0506 6594#define regMPC_CRC_RESULT_C_BASE_IDX 3 6595#define regMPC_PERFMON_EVENT_CTRL 0x0509 6596#define regMPC_PERFMON_EVENT_CTRL_BASE_IDX 3 6597#define regMPC_BYPASS_BG_AR 0x050a 6598#define regMPC_BYPASS_BG_AR_BASE_IDX 3 6599#define regMPC_BYPASS_BG_GB 0x050b 6600#define regMPC_BYPASS_BG_GB_BASE_IDX 3 6601#define regMPC_HOST_READ_CONTROL 0x050c 6602#define regMPC_HOST_READ_CONTROL_BASE_IDX 3 6603#define regMPC_DPP_PENDING_STATUS 0x050d 6604#define regMPC_DPP_PENDING_STATUS_BASE_IDX 3 6605#define regMPC_PENDING_STATUS_MISC 0x050e 6606#define regMPC_PENDING_STATUS_MISC_BASE_IDX 3 6607#define regADR_CFG_CUR_VUPDATE_LOCK_SET0 0x050f 6608#define regADR_CFG_CUR_VUPDATE_LOCK_SET0_BASE_IDX 3 6609#define regADR_CFG_VUPDATE_LOCK_SET0 0x0510 6610#define regADR_CFG_VUPDATE_LOCK_SET0_BASE_IDX 3 6611#define regADR_VUPDATE_LOCK_SET0 0x0511 6612#define regADR_VUPDATE_LOCK_SET0_BASE_IDX 3 6613#define regCFG_VUPDATE_LOCK_SET0 0x0512 6614#define regCFG_VUPDATE_LOCK_SET0_BASE_IDX 3 6615#define regCUR_VUPDATE_LOCK_SET0 0x0513 6616#define regCUR_VUPDATE_LOCK_SET0_BASE_IDX 3 6617#define regADR_CFG_CUR_VUPDATE_LOCK_SET1 0x0514 6618#define regADR_CFG_CUR_VUPDATE_LOCK_SET1_BASE_IDX 3 6619#define regADR_CFG_VUPDATE_LOCK_SET1 0x0515 6620#define regADR_CFG_VUPDATE_LOCK_SET1_BASE_IDX 3 6621#define regADR_VUPDATE_LOCK_SET1 0x0516 6622#define regADR_VUPDATE_LOCK_SET1_BASE_IDX 3 6623#define regCFG_VUPDATE_LOCK_SET1 0x0517 6624#define regCFG_VUPDATE_LOCK_SET1_BASE_IDX 3 6625#define regCUR_VUPDATE_LOCK_SET1 0x0518 6626#define regCUR_VUPDATE_LOCK_SET1_BASE_IDX 3 6627#define regADR_CFG_CUR_VUPDATE_LOCK_SET2 0x0519 6628#define regADR_CFG_CUR_VUPDATE_LOCK_SET2_BASE_IDX 3 6629#define regADR_CFG_VUPDATE_LOCK_SET2 0x051a 6630#define regADR_CFG_VUPDATE_LOCK_SET2_BASE_IDX 3 6631#define regADR_VUPDATE_LOCK_SET2 0x051b 6632#define regADR_VUPDATE_LOCK_SET2_BASE_IDX 3 6633#define regCFG_VUPDATE_LOCK_SET2 0x051c 6634#define regCFG_VUPDATE_LOCK_SET2_BASE_IDX 3 6635#define regCUR_VUPDATE_LOCK_SET2 0x051d 6636#define regCUR_VUPDATE_LOCK_SET2_BASE_IDX 3 6637#define regADR_CFG_CUR_VUPDATE_LOCK_SET3 0x051e 6638#define regADR_CFG_CUR_VUPDATE_LOCK_SET3_BASE_IDX 3 6639#define regADR_CFG_VUPDATE_LOCK_SET3 0x051f 6640#define regADR_CFG_VUPDATE_LOCK_SET3_BASE_IDX 3 6641#define regADR_VUPDATE_LOCK_SET3 0x0520 6642#define regADR_VUPDATE_LOCK_SET3_BASE_IDX 3 6643#define regCFG_VUPDATE_LOCK_SET3 0x0521 6644#define regCFG_VUPDATE_LOCK_SET3_BASE_IDX 3 6645#define regCUR_VUPDATE_LOCK_SET3 0x0522 6646#define regCUR_VUPDATE_LOCK_SET3_BASE_IDX 3 6647#define regMPC_DWB0_MUX 0x055c 6648#define regMPC_DWB0_MUX_BASE_IDX 3 6649 6650 6651// addressBlock: dce_dc_mpc_mpc_dcperfmon_dc_perfmon_dispdec 6652// base address: 0x1901c 6653#define regDC_PERFMON15_PERFCOUNTER_CNTL 0x08c7 6654#define regDC_PERFMON15_PERFCOUNTER_CNTL_BASE_IDX 3 6655#define regDC_PERFMON15_PERFCOUNTER_CNTL2 0x08c8 6656#define regDC_PERFMON15_PERFCOUNTER_CNTL2_BASE_IDX 3 6657#define regDC_PERFMON15_PERFCOUNTER_STATE 0x08c9 6658#define regDC_PERFMON15_PERFCOUNTER_STATE_BASE_IDX 3 6659#define regDC_PERFMON15_PERFMON_CNTL 0x08ca 6660#define regDC_PERFMON15_PERFMON_CNTL_BASE_IDX 3 6661#define regDC_PERFMON15_PERFMON_CNTL2 0x08cb 6662#define regDC_PERFMON15_PERFMON_CNTL2_BASE_IDX 3 6663#define regDC_PERFMON15_PERFMON_CVALUE_INT_MISC 0x08cc 6664#define regDC_PERFMON15_PERFMON_CVALUE_INT_MISC_BASE_IDX 3 6665#define regDC_PERFMON15_PERFMON_CVALUE_LOW 0x08cd 6666#define regDC_PERFMON15_PERFMON_CVALUE_LOW_BASE_IDX 3 6667#define regDC_PERFMON15_PERFMON_HI 0x08ce 6668#define regDC_PERFMON15_PERFMON_HI_BASE_IDX 3 6669#define regDC_PERFMON15_PERFMON_LOW 0x08cf 6670#define regDC_PERFMON15_PERFMON_LOW_BASE_IDX 3 6671 6672 6673// addressBlock: dce_dc_mpc_mpcc_ogam0_dispdec 6674// base address: 0x0 6675#define regMPCC_OGAM0_MPCC_OGAM_CONTROL 0x0100 6676#define regMPCC_OGAM0_MPCC_OGAM_CONTROL_BASE_IDX 3 6677#define regMPCC_OGAM0_MPCC_OGAM_LUT_INDEX 0x0101 6678#define regMPCC_OGAM0_MPCC_OGAM_LUT_INDEX_BASE_IDX 3 6679#define regMPCC_OGAM0_MPCC_OGAM_LUT_DATA 0x0102 6680#define regMPCC_OGAM0_MPCC_OGAM_LUT_DATA_BASE_IDX 3 6681#define regMPCC_OGAM0_MPCC_OGAM_LUT_CONTROL 0x0103 6682#define regMPCC_OGAM0_MPCC_OGAM_LUT_CONTROL_BASE_IDX 3 6683#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B 0x0104 6684#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX 3 6685#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G 0x0105 6686#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX 3 6687#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R 0x0106 6688#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX 3 6689#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B 0x0107 6690#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX 3 6691#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G 0x0108 6692#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 3 6693#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R 0x0109 6694#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX 3 6695#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_B 0x010a 6696#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX 3 6697#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_G 0x010b 6698#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX 3 6699#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_R 0x010c 6700#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX 3 6701#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B 0x010d 6702#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX 3 6703#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B 0x010e 6704#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX 3 6705#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_G 0x010f 6706#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX 3 6707#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G 0x0110 6708#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX 3 6709#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_R 0x0111 6710#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX 3 6711#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R 0x0112 6712#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX 3 6713#define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_B 0x0113 6714#define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_B_BASE_IDX 3 6715#define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_G 0x0114 6716#define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX 3 6717#define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_R 0x0115 6718#define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_R_BASE_IDX 3 6719#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1 0x0116 6720#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX 3 6721#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3 0x0117 6722#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX 3 6723#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5 0x0118 6724#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX 3 6725#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7 0x0119 6726#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX 3 6727#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9 0x011a 6728#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX 3 6729#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11 0x011b 6730#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX 3 6731#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13 0x011c 6732#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX 3 6733#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15 0x011d 6734#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX 3 6735#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17 0x011e 6736#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX 3 6737#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19 0x011f 6738#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX 3 6739#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21 0x0120 6740#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX 3 6741#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23 0x0121 6742#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX 3 6743#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25 0x0122 6744#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX 3 6745#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27 0x0123 6746#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX 3 6747#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29 0x0124 6748#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX 3 6749#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31 0x0125 6750#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX 3 6751#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33 0x0126 6752#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX 3 6753#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B 0x0127 6754#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX 3 6755#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G 0x0128 6756#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX 3 6757#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R 0x0129 6758#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX 3 6759#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B 0x012a 6760#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX 3 6761#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G 0x012b 6762#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX 3 6763#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R 0x012c 6764#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX 3 6765#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_B 0x012d 6766#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX 3 6767#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_G 0x012e 6768#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX 3 6769#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_R 0x012f 6770#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX 3 6771#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_B 0x0130 6772#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX 3 6773#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B 0x0131 6774#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX 3 6775#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_G 0x0132 6776#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX 3 6777#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G 0x0133 6778#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX 3 6779#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_R 0x0134 6780#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX 3 6781#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R 0x0135 6782#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX 3 6783#define regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_B 0x0136 6784#define regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_B_BASE_IDX 3 6785#define regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_G 0x0137 6786#define regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_G_BASE_IDX 3 6787#define regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_R 0x0138 6788#define regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_R_BASE_IDX 3 6789#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1 0x0139 6790#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX 3 6791#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3 0x013a 6792#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX 3 6793#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5 0x013b 6794#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX 3 6795#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7 0x013c 6796#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX 3 6797#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9 0x013d 6798#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX 3 6799#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11 0x013e 6800#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX 3 6801#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13 0x013f 6802#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX 3 6803#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15 0x0140 6804#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX 3 6805#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17 0x0141 6806#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX 3 6807#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19 0x0142 6808#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX 3 6809#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21 0x0143 6810#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX 3 6811#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23 0x0144 6812#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX 3 6813#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25 0x0145 6814#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX 3 6815#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27 0x0146 6816#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX 3 6817#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29 0x0147 6818#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX 3 6819#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31 0x0148 6820#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX 3 6821#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33 0x0149 6822#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX 3 6823#define regMPCC_OGAM0_MPCC_GAMUT_REMAP_COEF_FORMAT 0x014a 6824#define regMPCC_OGAM0_MPCC_GAMUT_REMAP_COEF_FORMAT_BASE_IDX 3 6825#define regMPCC_OGAM0_MPCC_GAMUT_REMAP_MODE 0x014b 6826#define regMPCC_OGAM0_MPCC_GAMUT_REMAP_MODE_BASE_IDX 3 6827#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A 0x014c 6828#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A_BASE_IDX 3 6829#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_A 0x014d 6830#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_A_BASE_IDX 3 6831#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_A 0x014e 6832#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_A_BASE_IDX 3 6833#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_A 0x014f 6834#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_A_BASE_IDX 3 6835#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_A 0x0150 6836#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_A_BASE_IDX 3 6837#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_A 0x0151 6838#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_A_BASE_IDX 3 6839#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_B 0x0152 6840#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_B_BASE_IDX 3 6841#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_B 0x0153 6842#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_B_BASE_IDX 3 6843#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_B 0x0154 6844#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_B_BASE_IDX 3 6845#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_B 0x0155 6846#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_B_BASE_IDX 3 6847#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_B 0x0156 6848#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_B_BASE_IDX 3 6849#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_B 0x0157 6850#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_B_BASE_IDX 3 6851 6852 6853// addressBlock: dce_dc_mpc_mpcc_ogam1_dispdec 6854// base address: 0x200 6855#define regMPCC_OGAM1_MPCC_OGAM_CONTROL 0x0180 6856#define regMPCC_OGAM1_MPCC_OGAM_CONTROL_BASE_IDX 3 6857#define regMPCC_OGAM1_MPCC_OGAM_LUT_INDEX 0x0181 6858#define regMPCC_OGAM1_MPCC_OGAM_LUT_INDEX_BASE_IDX 3 6859#define regMPCC_OGAM1_MPCC_OGAM_LUT_DATA 0x0182 6860#define regMPCC_OGAM1_MPCC_OGAM_LUT_DATA_BASE_IDX 3 6861#define regMPCC_OGAM1_MPCC_OGAM_LUT_CONTROL 0x0183 6862#define regMPCC_OGAM1_MPCC_OGAM_LUT_CONTROL_BASE_IDX 3 6863#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B 0x0184 6864#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX 3 6865#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G 0x0185 6866#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX 3 6867#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R 0x0186 6868#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX 3 6869#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B 0x0187 6870#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX 3 6871#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G 0x0188 6872#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 3 6873#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R 0x0189 6874#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX 3 6875#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_B 0x018a 6876#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX 3 6877#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_G 0x018b 6878#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX 3 6879#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_R 0x018c 6880#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX 3 6881#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_B 0x018d 6882#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX 3 6883#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B 0x018e 6884#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX 3 6885#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_G 0x018f 6886#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX 3 6887#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G 0x0190 6888#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX 3 6889#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_R 0x0191 6890#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX 3 6891#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R 0x0192 6892#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX 3 6893#define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_B 0x0193 6894#define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_B_BASE_IDX 3 6895#define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_G 0x0194 6896#define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX 3 6897#define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_R 0x0195 6898#define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_R_BASE_IDX 3 6899#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1 0x0196 6900#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX 3 6901#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3 0x0197 6902#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX 3 6903#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5 0x0198 6904#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX 3 6905#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7 0x0199 6906#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX 3 6907#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9 0x019a 6908#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX 3 6909#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11 0x019b 6910#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX 3 6911#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13 0x019c 6912#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX 3 6913#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15 0x019d 6914#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX 3 6915#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17 0x019e 6916#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX 3 6917#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19 0x019f 6918#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX 3 6919#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21 0x01a0 6920#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX 3 6921#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23 0x01a1 6922#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX 3 6923#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25 0x01a2 6924#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX 3 6925#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27 0x01a3 6926#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX 3 6927#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29 0x01a4 6928#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX 3 6929#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31 0x01a5 6930#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX 3 6931#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33 0x01a6 6932#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX 3 6933#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B 0x01a7 6934#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX 3 6935#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G 0x01a8 6936#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX 3 6937#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R 0x01a9 6938#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX 3 6939#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B 0x01aa 6940#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX 3 6941#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G 0x01ab 6942#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX 3 6943#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R 0x01ac 6944#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX 3 6945#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_B 0x01ad 6946#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX 3 6947#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_G 0x01ae 6948#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX 3 6949#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_R 0x01af 6950#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX 3 6951#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_B 0x01b0 6952#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX 3 6953#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B 0x01b1 6954#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX 3 6955#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_G 0x01b2 6956#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX 3 6957#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G 0x01b3 6958#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX 3 6959#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_R 0x01b4 6960#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX 3 6961#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R 0x01b5 6962#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX 3 6963#define regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_B 0x01b6 6964#define regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_B_BASE_IDX 3 6965#define regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_G 0x01b7 6966#define regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_G_BASE_IDX 3 6967#define regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_R 0x01b8 6968#define regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_R_BASE_IDX 3 6969#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1 0x01b9 6970#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX 3 6971#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3 0x01ba 6972#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX 3 6973#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5 0x01bb 6974#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX 3 6975#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7 0x01bc 6976#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX 3 6977#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9 0x01bd 6978#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX 3 6979#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11 0x01be 6980#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX 3 6981#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13 0x01bf 6982#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX 3 6983#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15 0x01c0 6984#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX 3 6985#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17 0x01c1 6986#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX 3 6987#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19 0x01c2 6988#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX 3 6989#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21 0x01c3 6990#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX 3 6991#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23 0x01c4 6992#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX 3 6993#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25 0x01c5 6994#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX 3 6995#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27 0x01c6 6996#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX 3 6997#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29 0x01c7 6998#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX 3 6999#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31 0x01c8 7000#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX 3 7001#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33 0x01c9 7002#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX 3 7003#define regMPCC_OGAM1_MPCC_GAMUT_REMAP_COEF_FORMAT 0x01ca 7004#define regMPCC_OGAM1_MPCC_GAMUT_REMAP_COEF_FORMAT_BASE_IDX 3 7005#define regMPCC_OGAM1_MPCC_GAMUT_REMAP_MODE 0x01cb 7006#define regMPCC_OGAM1_MPCC_GAMUT_REMAP_MODE_BASE_IDX 3 7007#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_A 0x01cc 7008#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_A_BASE_IDX 3 7009#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_A 0x01cd 7010#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_A_BASE_IDX 3 7011#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_A 0x01ce 7012#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_A_BASE_IDX 3 7013#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_A 0x01cf 7014#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_A_BASE_IDX 3 7015#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_A 0x01d0 7016#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_A_BASE_IDX 3 7017#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_A 0x01d1 7018#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_A_BASE_IDX 3 7019#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_B 0x01d2 7020#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_B_BASE_IDX 3 7021#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_B 0x01d3 7022#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_B_BASE_IDX 3 7023#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_B 0x01d4 7024#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_B_BASE_IDX 3 7025#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_B 0x01d5 7026#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_B_BASE_IDX 3 7027#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_B 0x01d6 7028#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_B_BASE_IDX 3 7029#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_B 0x01d7 7030#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_B_BASE_IDX 3 7031 7032 7033// addressBlock: dce_dc_mpc_mpcc_ogam2_dispdec 7034// base address: 0x400 7035#define regMPCC_OGAM2_MPCC_OGAM_CONTROL 0x0200 7036#define regMPCC_OGAM2_MPCC_OGAM_CONTROL_BASE_IDX 3 7037#define regMPCC_OGAM2_MPCC_OGAM_LUT_INDEX 0x0201 7038#define regMPCC_OGAM2_MPCC_OGAM_LUT_INDEX_BASE_IDX 3 7039#define regMPCC_OGAM2_MPCC_OGAM_LUT_DATA 0x0202 7040#define regMPCC_OGAM2_MPCC_OGAM_LUT_DATA_BASE_IDX 3 7041#define regMPCC_OGAM2_MPCC_OGAM_LUT_CONTROL 0x0203 7042#define regMPCC_OGAM2_MPCC_OGAM_LUT_CONTROL_BASE_IDX 3 7043#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B 0x0204 7044#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX 3 7045#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G 0x0205 7046#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX 3 7047#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R 0x0206 7048#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX 3 7049#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B 0x0207 7050#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX 3 7051#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G 0x0208 7052#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 3 7053#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R 0x0209 7054#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX 3 7055#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_B 0x020a 7056#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX 3 7057#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_G 0x020b 7058#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX 3 7059#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_R 0x020c 7060#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX 3 7061#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_B 0x020d 7062#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX 3 7063#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B 0x020e 7064#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX 3 7065#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_G 0x020f 7066#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX 3 7067#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G 0x0210 7068#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX 3 7069#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_R 0x0211 7070#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX 3 7071#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R 0x0212 7072#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX 3 7073#define regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_B 0x0213 7074#define regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_B_BASE_IDX 3 7075#define regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_G 0x0214 7076#define regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX 3 7077#define regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_R 0x0215 7078#define regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_R_BASE_IDX 3 7079#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1 0x0216 7080#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX 3 7081#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3 0x0217 7082#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX 3 7083#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5 0x0218 7084#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX 3 7085#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7 0x0219 7086#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX 3 7087#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9 0x021a 7088#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX 3 7089#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11 0x021b 7090#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX 3 7091#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13 0x021c 7092#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX 3 7093#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15 0x021d 7094#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX 3 7095#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17 0x021e 7096#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX 3 7097#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19 0x021f 7098#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX 3 7099#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21 0x0220 7100#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX 3 7101#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23 0x0221 7102#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX 3 7103#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25 0x0222 7104#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX 3 7105#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27 0x0223 7106#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX 3 7107#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29 0x0224 7108#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX 3 7109#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31 0x0225 7110#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX 3 7111#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33 0x0226 7112#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX 3 7113#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B 0x0227 7114#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX 3 7115#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G 0x0228 7116#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX 3 7117#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R 0x0229 7118#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX 3 7119#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B 0x022a 7120#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX 3 7121#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G 0x022b 7122#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX 3 7123#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R 0x022c 7124#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX 3 7125#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_B 0x022d 7126#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX 3 7127#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_G 0x022e 7128#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX 3 7129#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_R 0x022f 7130#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX 3 7131#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_B 0x0230 7132#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX 3 7133#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B 0x0231 7134#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX 3 7135#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_G 0x0232 7136#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX 3 7137#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G 0x0233 7138#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX 3 7139#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_R 0x0234 7140#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX 3 7141#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R 0x0235 7142#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX 3 7143#define regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_B 0x0236 7144#define regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_B_BASE_IDX 3 7145#define regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_G 0x0237 7146#define regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_G_BASE_IDX 3 7147#define regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_R 0x0238 7148#define regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_R_BASE_IDX 3 7149#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1 0x0239 7150#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX 3 7151#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3 0x023a 7152#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX 3 7153#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5 0x023b 7154#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX 3 7155#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7 0x023c 7156#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX 3 7157#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9 0x023d 7158#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX 3 7159#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11 0x023e 7160#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX 3 7161#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13 0x023f 7162#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX 3 7163#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15 0x0240 7164#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX 3 7165#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17 0x0241 7166#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX 3 7167#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19 0x0242 7168#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX 3 7169#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21 0x0243 7170#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX 3 7171#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23 0x0244 7172#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX 3 7173#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25 0x0245 7174#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX 3 7175#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27 0x0246 7176#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX 3 7177#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29 0x0247 7178#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX 3 7179#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31 0x0248 7180#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX 3 7181#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33 0x0249 7182#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX 3 7183#define regMPCC_OGAM2_MPCC_GAMUT_REMAP_COEF_FORMAT 0x024a 7184#define regMPCC_OGAM2_MPCC_GAMUT_REMAP_COEF_FORMAT_BASE_IDX 3 7185#define regMPCC_OGAM2_MPCC_GAMUT_REMAP_MODE 0x024b 7186#define regMPCC_OGAM2_MPCC_GAMUT_REMAP_MODE_BASE_IDX 3 7187#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_A 0x024c 7188#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_A_BASE_IDX 3 7189#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_A 0x024d 7190#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_A_BASE_IDX 3 7191#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_A 0x024e 7192#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_A_BASE_IDX 3 7193#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_A 0x024f 7194#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_A_BASE_IDX 3 7195#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_A 0x0250 7196#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_A_BASE_IDX 3 7197#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_A 0x0251 7198#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_A_BASE_IDX 3 7199#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_B 0x0252 7200#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_B_BASE_IDX 3 7201#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_B 0x0253 7202#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_B_BASE_IDX 3 7203#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_B 0x0254 7204#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_B_BASE_IDX 3 7205#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_B 0x0255 7206#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_B_BASE_IDX 3 7207#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_B 0x0256 7208#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_B_BASE_IDX 3 7209#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_B 0x0257 7210#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_B_BASE_IDX 3 7211 7212 7213// addressBlock: dce_dc_mpc_mpcc_ogam3_dispdec 7214// base address: 0x600 7215#define regMPCC_OGAM3_MPCC_OGAM_CONTROL 0x0280 7216#define regMPCC_OGAM3_MPCC_OGAM_CONTROL_BASE_IDX 3 7217#define regMPCC_OGAM3_MPCC_OGAM_LUT_INDEX 0x0281 7218#define regMPCC_OGAM3_MPCC_OGAM_LUT_INDEX_BASE_IDX 3 7219#define regMPCC_OGAM3_MPCC_OGAM_LUT_DATA 0x0282 7220#define regMPCC_OGAM3_MPCC_OGAM_LUT_DATA_BASE_IDX 3 7221#define regMPCC_OGAM3_MPCC_OGAM_LUT_CONTROL 0x0283 7222#define regMPCC_OGAM3_MPCC_OGAM_LUT_CONTROL_BASE_IDX 3 7223#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B 0x0284 7224#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX 3 7225#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G 0x0285 7226#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX 3 7227#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R 0x0286 7228#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX 3 7229#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B 0x0287 7230#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX 3 7231#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G 0x0288 7232#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 3 7233#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R 0x0289 7234#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX 3 7235#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_B 0x028a 7236#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX 3 7237#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_G 0x028b 7238#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX 3 7239#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_R 0x028c 7240#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX 3 7241#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_B 0x028d 7242#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX 3 7243#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B 0x028e 7244#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX 3 7245#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_G 0x028f 7246#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX 3 7247#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G 0x0290 7248#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX 3 7249#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_R 0x0291 7250#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX 3 7251#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R 0x0292 7252#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX 3 7253#define regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_B 0x0293 7254#define regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_B_BASE_IDX 3 7255#define regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_G 0x0294 7256#define regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX 3 7257#define regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_R 0x0295 7258#define regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_R_BASE_IDX 3 7259#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1 0x0296 7260#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX 3 7261#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3 0x0297 7262#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX 3 7263#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5 0x0298 7264#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX 3 7265#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7 0x0299 7266#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX 3 7267#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9 0x029a 7268#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX 3 7269#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11 0x029b 7270#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX 3 7271#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13 0x029c 7272#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX 3 7273#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15 0x029d 7274#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX 3 7275#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17 0x029e 7276#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX 3 7277#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19 0x029f 7278#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX 3 7279#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21 0x02a0 7280#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX 3 7281#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23 0x02a1 7282#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX 3 7283#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25 0x02a2 7284#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX 3 7285#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27 0x02a3 7286#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX 3 7287#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29 0x02a4 7288#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX 3 7289#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31 0x02a5 7290#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX 3 7291#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33 0x02a6 7292#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX 3 7293#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B 0x02a7 7294#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX 3 7295#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G 0x02a8 7296#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX 3 7297#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R 0x02a9 7298#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX 3 7299#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B 0x02aa 7300#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX 3 7301#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G 0x02ab 7302#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX 3 7303#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R 0x02ac 7304#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX 3 7305#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_B 0x02ad 7306#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX 3 7307#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_G 0x02ae 7308#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX 3 7309#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_R 0x02af 7310#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX 3 7311#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_B 0x02b0 7312#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX 3 7313#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B 0x02b1 7314#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX 3 7315#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_G 0x02b2 7316#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX 3 7317#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G 0x02b3 7318#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX 3 7319#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_R 0x02b4 7320#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX 3 7321#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R 0x02b5 7322#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX 3 7323#define regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_B 0x02b6 7324#define regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_B_BASE_IDX 3 7325#define regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_G 0x02b7 7326#define regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_G_BASE_IDX 3 7327#define regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_R 0x02b8 7328#define regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_R_BASE_IDX 3 7329#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1 0x02b9 7330#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX 3 7331#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3 0x02ba 7332#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX 3 7333#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5 0x02bb 7334#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX 3 7335#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7 0x02bc 7336#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX 3 7337#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9 0x02bd 7338#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX 3 7339#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11 0x02be 7340#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX 3 7341#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13 0x02bf 7342#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX 3 7343#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15 0x02c0 7344#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX 3 7345#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17 0x02c1 7346#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX 3 7347#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19 0x02c2 7348#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX 3 7349#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21 0x02c3 7350#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX 3 7351#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23 0x02c4 7352#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX 3 7353#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25 0x02c5 7354#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX 3 7355#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27 0x02c6 7356#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX 3 7357#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29 0x02c7 7358#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX 3 7359#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31 0x02c8 7360#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX 3 7361#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33 0x02c9 7362#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX 3 7363#define regMPCC_OGAM3_MPCC_GAMUT_REMAP_COEF_FORMAT 0x02ca 7364#define regMPCC_OGAM3_MPCC_GAMUT_REMAP_COEF_FORMAT_BASE_IDX 3 7365#define regMPCC_OGAM3_MPCC_GAMUT_REMAP_MODE 0x02cb 7366#define regMPCC_OGAM3_MPCC_GAMUT_REMAP_MODE_BASE_IDX 3 7367#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_A 0x02cc 7368#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_A_BASE_IDX 3 7369#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_A 0x02cd 7370#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_A_BASE_IDX 3 7371#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_A 0x02ce 7372#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_A_BASE_IDX 3 7373#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_A 0x02cf 7374#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_A_BASE_IDX 3 7375#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_A 0x02d0 7376#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_A_BASE_IDX 3 7377#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_A 0x02d1 7378#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_A_BASE_IDX 3 7379#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_B 0x02d2 7380#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_B_BASE_IDX 3 7381#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_B 0x02d3 7382#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_B_BASE_IDX 3 7383#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_B 0x02d4 7384#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_B_BASE_IDX 3 7385#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_B 0x02d5 7386#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_B_BASE_IDX 3 7387#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_B 0x02d6 7388#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_B_BASE_IDX 3 7389#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_B 0x02d7 7390#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_B_BASE_IDX 3 7391 7392 7393// addressBlock: dce_dc_mpc_mpc_ocsc_dispdec 7394// base address: 0x0 7395#define regMPC_OUT0_MUX 0x0580 7396#define regMPC_OUT0_MUX_BASE_IDX 3 7397#define regMPC_OUT0_DENORM_CONTROL 0x0581 7398#define regMPC_OUT0_DENORM_CONTROL_BASE_IDX 3 7399#define regMPC_OUT0_DENORM_CLAMP_G_Y 0x0582 7400#define regMPC_OUT0_DENORM_CLAMP_G_Y_BASE_IDX 3 7401#define regMPC_OUT0_DENORM_CLAMP_B_CB 0x0583 7402#define regMPC_OUT0_DENORM_CLAMP_B_CB_BASE_IDX 3 7403#define regMPC_OUT1_MUX 0x0584 7404#define regMPC_OUT1_MUX_BASE_IDX 3 7405#define regMPC_OUT1_DENORM_CONTROL 0x0585 7406#define regMPC_OUT1_DENORM_CONTROL_BASE_IDX 3 7407#define regMPC_OUT1_DENORM_CLAMP_G_Y 0x0586 7408#define regMPC_OUT1_DENORM_CLAMP_G_Y_BASE_IDX 3 7409#define regMPC_OUT1_DENORM_CLAMP_B_CB 0x0587 7410#define regMPC_OUT1_DENORM_CLAMP_B_CB_BASE_IDX 3 7411#define regMPC_OUT2_MUX 0x0588 7412#define regMPC_OUT2_MUX_BASE_IDX 3 7413#define regMPC_OUT2_DENORM_CONTROL 0x0589 7414#define regMPC_OUT2_DENORM_CONTROL_BASE_IDX 3 7415#define regMPC_OUT2_DENORM_CLAMP_G_Y 0x058a 7416#define regMPC_OUT2_DENORM_CLAMP_G_Y_BASE_IDX 3 7417#define regMPC_OUT2_DENORM_CLAMP_B_CB 0x058b 7418#define regMPC_OUT2_DENORM_CLAMP_B_CB_BASE_IDX 3 7419#define regMPC_OUT3_MUX 0x058c 7420#define regMPC_OUT3_MUX_BASE_IDX 3 7421#define regMPC_OUT3_DENORM_CONTROL 0x058d 7422#define regMPC_OUT3_DENORM_CONTROL_BASE_IDX 3 7423#define regMPC_OUT3_DENORM_CLAMP_G_Y 0x058e 7424#define regMPC_OUT3_DENORM_CLAMP_G_Y_BASE_IDX 3 7425#define regMPC_OUT3_DENORM_CLAMP_B_CB 0x058f 7426#define regMPC_OUT3_DENORM_CLAMP_B_CB_BASE_IDX 3 7427#define regMPC_OUT_CSC_COEF_FORMAT 0x05a0 7428#define regMPC_OUT_CSC_COEF_FORMAT_BASE_IDX 3 7429#define regMPC_OUT0_CSC_MODE 0x05a1 7430#define regMPC_OUT0_CSC_MODE_BASE_IDX 3 7431#define regMPC_OUT0_CSC_C11_C12_A 0x05a2 7432#define regMPC_OUT0_CSC_C11_C12_A_BASE_IDX 3 7433#define regMPC_OUT0_CSC_C13_C14_A 0x05a3 7434#define regMPC_OUT0_CSC_C13_C14_A_BASE_IDX 3 7435#define regMPC_OUT0_CSC_C21_C22_A 0x05a4 7436#define regMPC_OUT0_CSC_C21_C22_A_BASE_IDX 3 7437#define regMPC_OUT0_CSC_C23_C24_A 0x05a5 7438#define regMPC_OUT0_CSC_C23_C24_A_BASE_IDX 3 7439#define regMPC_OUT0_CSC_C31_C32_A 0x05a6 7440#define regMPC_OUT0_CSC_C31_C32_A_BASE_IDX 3 7441#define regMPC_OUT0_CSC_C33_C34_A 0x05a7 7442#define regMPC_OUT0_CSC_C33_C34_A_BASE_IDX 3 7443#define regMPC_OUT0_CSC_C11_C12_B 0x05a8 7444#define regMPC_OUT0_CSC_C11_C12_B_BASE_IDX 3 7445#define regMPC_OUT0_CSC_C13_C14_B 0x05a9 7446#define regMPC_OUT0_CSC_C13_C14_B_BASE_IDX 3 7447#define regMPC_OUT0_CSC_C21_C22_B 0x05aa 7448#define regMPC_OUT0_CSC_C21_C22_B_BASE_IDX 3 7449#define regMPC_OUT0_CSC_C23_C24_B 0x05ab 7450#define regMPC_OUT0_CSC_C23_C24_B_BASE_IDX 3 7451#define regMPC_OUT0_CSC_C31_C32_B 0x05ac 7452#define regMPC_OUT0_CSC_C31_C32_B_BASE_IDX 3 7453#define regMPC_OUT0_CSC_C33_C34_B 0x05ad 7454#define regMPC_OUT0_CSC_C33_C34_B_BASE_IDX 3 7455#define regMPC_OUT1_CSC_MODE 0x05ae 7456#define regMPC_OUT1_CSC_MODE_BASE_IDX 3 7457#define regMPC_OUT1_CSC_C11_C12_A 0x05af 7458#define regMPC_OUT1_CSC_C11_C12_A_BASE_IDX 3 7459#define regMPC_OUT1_CSC_C13_C14_A 0x05b0 7460#define regMPC_OUT1_CSC_C13_C14_A_BASE_IDX 3 7461#define regMPC_OUT1_CSC_C21_C22_A 0x05b1 7462#define regMPC_OUT1_CSC_C21_C22_A_BASE_IDX 3 7463#define regMPC_OUT1_CSC_C23_C24_A 0x05b2 7464#define regMPC_OUT1_CSC_C23_C24_A_BASE_IDX 3 7465#define regMPC_OUT1_CSC_C31_C32_A 0x05b3 7466#define regMPC_OUT1_CSC_C31_C32_A_BASE_IDX 3 7467#define regMPC_OUT1_CSC_C33_C34_A 0x05b4 7468#define regMPC_OUT1_CSC_C33_C34_A_BASE_IDX 3 7469#define regMPC_OUT1_CSC_C11_C12_B 0x05b5 7470#define regMPC_OUT1_CSC_C11_C12_B_BASE_IDX 3 7471#define regMPC_OUT1_CSC_C13_C14_B 0x05b6 7472#define regMPC_OUT1_CSC_C13_C14_B_BASE_IDX 3 7473#define regMPC_OUT1_CSC_C21_C22_B 0x05b7 7474#define regMPC_OUT1_CSC_C21_C22_B_BASE_IDX 3 7475#define regMPC_OUT1_CSC_C23_C24_B 0x05b8 7476#define regMPC_OUT1_CSC_C23_C24_B_BASE_IDX 3 7477#define regMPC_OUT1_CSC_C31_C32_B 0x05b9 7478#define regMPC_OUT1_CSC_C31_C32_B_BASE_IDX 3 7479#define regMPC_OUT1_CSC_C33_C34_B 0x05ba 7480#define regMPC_OUT1_CSC_C33_C34_B_BASE_IDX 3 7481#define regMPC_OUT2_CSC_MODE 0x05bb 7482#define regMPC_OUT2_CSC_MODE_BASE_IDX 3 7483#define regMPC_OUT2_CSC_C11_C12_A 0x05bc 7484#define regMPC_OUT2_CSC_C11_C12_A_BASE_IDX 3 7485#define regMPC_OUT2_CSC_C13_C14_A 0x05bd 7486#define regMPC_OUT2_CSC_C13_C14_A_BASE_IDX 3 7487#define regMPC_OUT2_CSC_C21_C22_A 0x05be 7488#define regMPC_OUT2_CSC_C21_C22_A_BASE_IDX 3 7489#define regMPC_OUT2_CSC_C23_C24_A 0x05bf 7490#define regMPC_OUT2_CSC_C23_C24_A_BASE_IDX 3 7491#define regMPC_OUT2_CSC_C31_C32_A 0x05c0 7492#define regMPC_OUT2_CSC_C31_C32_A_BASE_IDX 3 7493#define regMPC_OUT2_CSC_C33_C34_A 0x05c1 7494#define regMPC_OUT2_CSC_C33_C34_A_BASE_IDX 3 7495#define regMPC_OUT2_CSC_C11_C12_B 0x05c2 7496#define regMPC_OUT2_CSC_C11_C12_B_BASE_IDX 3 7497#define regMPC_OUT2_CSC_C13_C14_B 0x05c3 7498#define regMPC_OUT2_CSC_C13_C14_B_BASE_IDX 3 7499#define regMPC_OUT2_CSC_C21_C22_B 0x05c4 7500#define regMPC_OUT2_CSC_C21_C22_B_BASE_IDX 3 7501#define regMPC_OUT2_CSC_C23_C24_B 0x05c5 7502#define regMPC_OUT2_CSC_C23_C24_B_BASE_IDX 3 7503#define regMPC_OUT2_CSC_C31_C32_B 0x05c6 7504#define regMPC_OUT2_CSC_C31_C32_B_BASE_IDX 3 7505#define regMPC_OUT2_CSC_C33_C34_B 0x05c7 7506#define regMPC_OUT2_CSC_C33_C34_B_BASE_IDX 3 7507#define regMPC_OUT3_CSC_MODE 0x05c8 7508#define regMPC_OUT3_CSC_MODE_BASE_IDX 3 7509#define regMPC_OUT3_CSC_C11_C12_A 0x05c9 7510#define regMPC_OUT3_CSC_C11_C12_A_BASE_IDX 3 7511#define regMPC_OUT3_CSC_C13_C14_A 0x05ca 7512#define regMPC_OUT3_CSC_C13_C14_A_BASE_IDX 3 7513#define regMPC_OUT3_CSC_C21_C22_A 0x05cb 7514#define regMPC_OUT3_CSC_C21_C22_A_BASE_IDX 3 7515#define regMPC_OUT3_CSC_C23_C24_A 0x05cc 7516#define regMPC_OUT3_CSC_C23_C24_A_BASE_IDX 3 7517#define regMPC_OUT3_CSC_C31_C32_A 0x05cd 7518#define regMPC_OUT3_CSC_C31_C32_A_BASE_IDX 3 7519#define regMPC_OUT3_CSC_C33_C34_A 0x05ce 7520#define regMPC_OUT3_CSC_C33_C34_A_BASE_IDX 3 7521#define regMPC_OUT3_CSC_C11_C12_B 0x05cf 7522#define regMPC_OUT3_CSC_C11_C12_B_BASE_IDX 3 7523#define regMPC_OUT3_CSC_C13_C14_B 0x05d0 7524#define regMPC_OUT3_CSC_C13_C14_B_BASE_IDX 3 7525#define regMPC_OUT3_CSC_C21_C22_B 0x05d1 7526#define regMPC_OUT3_CSC_C21_C22_B_BASE_IDX 3 7527#define regMPC_OUT3_CSC_C23_C24_B 0x05d2 7528#define regMPC_OUT3_CSC_C23_C24_B_BASE_IDX 3 7529#define regMPC_OUT3_CSC_C31_C32_B 0x05d3 7530#define regMPC_OUT3_CSC_C31_C32_B_BASE_IDX 3 7531#define regMPC_OUT3_CSC_C33_C34_B 0x05d4 7532#define regMPC_OUT3_CSC_C33_C34_B_BASE_IDX 3 7533 7534 7535// addressBlock: dce_dc_mpc_mpc_rmu_dispdec 7536// base address: 0x0 7537#define regMPC_RMU_CONTROL 0x0680 7538#define regMPC_RMU_CONTROL_BASE_IDX 3 7539#define regMPC_RMU_MEM_PWR_CTRL 0x0681 7540#define regMPC_RMU_MEM_PWR_CTRL_BASE_IDX 3 7541#define regMPC_RMU0_SHAPER_CONTROL 0x0682 7542#define regMPC_RMU0_SHAPER_CONTROL_BASE_IDX 3 7543#define regMPC_RMU0_SHAPER_OFFSET_R 0x0683 7544#define regMPC_RMU0_SHAPER_OFFSET_R_BASE_IDX 3 7545#define regMPC_RMU0_SHAPER_OFFSET_G 0x0684 7546#define regMPC_RMU0_SHAPER_OFFSET_G_BASE_IDX 3 7547#define regMPC_RMU0_SHAPER_OFFSET_B 0x0685 7548#define regMPC_RMU0_SHAPER_OFFSET_B_BASE_IDX 3 7549#define regMPC_RMU0_SHAPER_SCALE_R 0x0686 7550#define regMPC_RMU0_SHAPER_SCALE_R_BASE_IDX 3 7551#define regMPC_RMU0_SHAPER_SCALE_G_B 0x0687 7552#define regMPC_RMU0_SHAPER_SCALE_G_B_BASE_IDX 3 7553#define regMPC_RMU0_SHAPER_LUT_INDEX 0x0688 7554#define regMPC_RMU0_SHAPER_LUT_INDEX_BASE_IDX 3 7555#define regMPC_RMU0_SHAPER_LUT_DATA 0x0689 7556#define regMPC_RMU0_SHAPER_LUT_DATA_BASE_IDX 3 7557#define regMPC_RMU0_SHAPER_LUT_WRITE_EN_MASK 0x068a 7558#define regMPC_RMU0_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX 3 7559#define regMPC_RMU0_SHAPER_RAMA_START_CNTL_B 0x068b 7560#define regMPC_RMU0_SHAPER_RAMA_START_CNTL_B_BASE_IDX 3 7561#define regMPC_RMU0_SHAPER_RAMA_START_CNTL_G 0x068c 7562#define regMPC_RMU0_SHAPER_RAMA_START_CNTL_G_BASE_IDX 3 7563#define regMPC_RMU0_SHAPER_RAMA_START_CNTL_R 0x068d 7564#define regMPC_RMU0_SHAPER_RAMA_START_CNTL_R_BASE_IDX 3 7565#define regMPC_RMU0_SHAPER_RAMA_END_CNTL_B 0x068e 7566#define regMPC_RMU0_SHAPER_RAMA_END_CNTL_B_BASE_IDX 3 7567#define regMPC_RMU0_SHAPER_RAMA_END_CNTL_G 0x068f 7568#define regMPC_RMU0_SHAPER_RAMA_END_CNTL_G_BASE_IDX 3 7569#define regMPC_RMU0_SHAPER_RAMA_END_CNTL_R 0x0690 7570#define regMPC_RMU0_SHAPER_RAMA_END_CNTL_R_BASE_IDX 3 7571#define regMPC_RMU0_SHAPER_RAMA_REGION_0_1 0x0691 7572#define regMPC_RMU0_SHAPER_RAMA_REGION_0_1_BASE_IDX 3 7573#define regMPC_RMU0_SHAPER_RAMA_REGION_2_3 0x0692 7574#define regMPC_RMU0_SHAPER_RAMA_REGION_2_3_BASE_IDX 3 7575#define regMPC_RMU0_SHAPER_RAMA_REGION_4_5 0x0693 7576#define regMPC_RMU0_SHAPER_RAMA_REGION_4_5_BASE_IDX 3 7577#define regMPC_RMU0_SHAPER_RAMA_REGION_6_7 0x0694 7578#define regMPC_RMU0_SHAPER_RAMA_REGION_6_7_BASE_IDX 3 7579#define regMPC_RMU0_SHAPER_RAMA_REGION_8_9 0x0695 7580#define regMPC_RMU0_SHAPER_RAMA_REGION_8_9_BASE_IDX 3 7581#define regMPC_RMU0_SHAPER_RAMA_REGION_10_11 0x0696 7582#define regMPC_RMU0_SHAPER_RAMA_REGION_10_11_BASE_IDX 3 7583#define regMPC_RMU0_SHAPER_RAMA_REGION_12_13 0x0697 7584#define regMPC_RMU0_SHAPER_RAMA_REGION_12_13_BASE_IDX 3 7585#define regMPC_RMU0_SHAPER_RAMA_REGION_14_15 0x0698 7586#define regMPC_RMU0_SHAPER_RAMA_REGION_14_15_BASE_IDX 3 7587#define regMPC_RMU0_SHAPER_RAMA_REGION_16_17 0x0699 7588#define regMPC_RMU0_SHAPER_RAMA_REGION_16_17_BASE_IDX 3 7589#define regMPC_RMU0_SHAPER_RAMA_REGION_18_19 0x069a 7590#define regMPC_RMU0_SHAPER_RAMA_REGION_18_19_BASE_IDX 3 7591#define regMPC_RMU0_SHAPER_RAMA_REGION_20_21 0x069b 7592#define regMPC_RMU0_SHAPER_RAMA_REGION_20_21_BASE_IDX 3 7593#define regMPC_RMU0_SHAPER_RAMA_REGION_22_23 0x069c 7594#define regMPC_RMU0_SHAPER_RAMA_REGION_22_23_BASE_IDX 3 7595#define regMPC_RMU0_SHAPER_RAMA_REGION_24_25 0x069d 7596#define regMPC_RMU0_SHAPER_RAMA_REGION_24_25_BASE_IDX 3 7597#define regMPC_RMU0_SHAPER_RAMA_REGION_26_27 0x069e 7598#define regMPC_RMU0_SHAPER_RAMA_REGION_26_27_BASE_IDX 3 7599#define regMPC_RMU0_SHAPER_RAMA_REGION_28_29 0x069f 7600#define regMPC_RMU0_SHAPER_RAMA_REGION_28_29_BASE_IDX 3 7601#define regMPC_RMU0_SHAPER_RAMA_REGION_30_31 0x06a0 7602#define regMPC_RMU0_SHAPER_RAMA_REGION_30_31_BASE_IDX 3 7603#define regMPC_RMU0_SHAPER_RAMA_REGION_32_33 0x06a1 7604#define regMPC_RMU0_SHAPER_RAMA_REGION_32_33_BASE_IDX 3 7605#define regMPC_RMU0_SHAPER_RAMB_START_CNTL_B 0x06a2 7606#define regMPC_RMU0_SHAPER_RAMB_START_CNTL_B_BASE_IDX 3 7607#define regMPC_RMU0_SHAPER_RAMB_START_CNTL_G 0x06a3 7608#define regMPC_RMU0_SHAPER_RAMB_START_CNTL_G_BASE_IDX 3 7609#define regMPC_RMU0_SHAPER_RAMB_START_CNTL_R 0x06a4 7610#define regMPC_RMU0_SHAPER_RAMB_START_CNTL_R_BASE_IDX 3 7611#define regMPC_RMU0_SHAPER_RAMB_END_CNTL_B 0x06a5 7612#define regMPC_RMU0_SHAPER_RAMB_END_CNTL_B_BASE_IDX 3 7613#define regMPC_RMU0_SHAPER_RAMB_END_CNTL_G 0x06a6 7614#define regMPC_RMU0_SHAPER_RAMB_END_CNTL_G_BASE_IDX 3 7615#define regMPC_RMU0_SHAPER_RAMB_END_CNTL_R 0x06a7 7616#define regMPC_RMU0_SHAPER_RAMB_END_CNTL_R_BASE_IDX 3 7617#define regMPC_RMU0_SHAPER_RAMB_REGION_0_1 0x06a8 7618#define regMPC_RMU0_SHAPER_RAMB_REGION_0_1_BASE_IDX 3 7619#define regMPC_RMU0_SHAPER_RAMB_REGION_2_3 0x06a9 7620#define regMPC_RMU0_SHAPER_RAMB_REGION_2_3_BASE_IDX 3 7621#define regMPC_RMU0_SHAPER_RAMB_REGION_4_5 0x06aa 7622#define regMPC_RMU0_SHAPER_RAMB_REGION_4_5_BASE_IDX 3 7623#define regMPC_RMU0_SHAPER_RAMB_REGION_6_7 0x06ab 7624#define regMPC_RMU0_SHAPER_RAMB_REGION_6_7_BASE_IDX 3 7625#define regMPC_RMU0_SHAPER_RAMB_REGION_8_9 0x06ac 7626#define regMPC_RMU0_SHAPER_RAMB_REGION_8_9_BASE_IDX 3 7627#define regMPC_RMU0_SHAPER_RAMB_REGION_10_11 0x06ad 7628#define regMPC_RMU0_SHAPER_RAMB_REGION_10_11_BASE_IDX 3 7629#define regMPC_RMU0_SHAPER_RAMB_REGION_12_13 0x06ae 7630#define regMPC_RMU0_SHAPER_RAMB_REGION_12_13_BASE_IDX 3 7631#define regMPC_RMU0_SHAPER_RAMB_REGION_14_15 0x06af 7632#define regMPC_RMU0_SHAPER_RAMB_REGION_14_15_BASE_IDX 3 7633#define regMPC_RMU0_SHAPER_RAMB_REGION_16_17 0x06b0 7634#define regMPC_RMU0_SHAPER_RAMB_REGION_16_17_BASE_IDX 3 7635#define regMPC_RMU0_SHAPER_RAMB_REGION_18_19 0x06b1 7636#define regMPC_RMU0_SHAPER_RAMB_REGION_18_19_BASE_IDX 3 7637#define regMPC_RMU0_SHAPER_RAMB_REGION_20_21 0x06b2 7638#define regMPC_RMU0_SHAPER_RAMB_REGION_20_21_BASE_IDX 3 7639#define regMPC_RMU0_SHAPER_RAMB_REGION_22_23 0x06b3 7640#define regMPC_RMU0_SHAPER_RAMB_REGION_22_23_BASE_IDX 3 7641#define regMPC_RMU0_SHAPER_RAMB_REGION_24_25 0x06b4 7642#define regMPC_RMU0_SHAPER_RAMB_REGION_24_25_BASE_IDX 3 7643#define regMPC_RMU0_SHAPER_RAMB_REGION_26_27 0x06b5 7644#define regMPC_RMU0_SHAPER_RAMB_REGION_26_27_BASE_IDX 3 7645#define regMPC_RMU0_SHAPER_RAMB_REGION_28_29 0x06b6 7646#define regMPC_RMU0_SHAPER_RAMB_REGION_28_29_BASE_IDX 3 7647#define regMPC_RMU0_SHAPER_RAMB_REGION_30_31 0x06b7 7648#define regMPC_RMU0_SHAPER_RAMB_REGION_30_31_BASE_IDX 3 7649#define regMPC_RMU0_SHAPER_RAMB_REGION_32_33 0x06b8 7650#define regMPC_RMU0_SHAPER_RAMB_REGION_32_33_BASE_IDX 3 7651#define regMPC_RMU0_3DLUT_MODE 0x06b9 7652#define regMPC_RMU0_3DLUT_MODE_BASE_IDX 3 7653#define regMPC_RMU0_3DLUT_INDEX 0x06ba 7654#define regMPC_RMU0_3DLUT_INDEX_BASE_IDX 3 7655#define regMPC_RMU0_3DLUT_DATA 0x06bb 7656#define regMPC_RMU0_3DLUT_DATA_BASE_IDX 3 7657#define regMPC_RMU0_3DLUT_DATA_30BIT 0x06bc 7658#define regMPC_RMU0_3DLUT_DATA_30BIT_BASE_IDX 3 7659#define regMPC_RMU0_3DLUT_READ_WRITE_CONTROL 0x06bd 7660#define regMPC_RMU0_3DLUT_READ_WRITE_CONTROL_BASE_IDX 3 7661#define regMPC_RMU0_3DLUT_OUT_NORM_FACTOR 0x06be 7662#define regMPC_RMU0_3DLUT_OUT_NORM_FACTOR_BASE_IDX 3 7663#define regMPC_RMU0_3DLUT_OUT_OFFSET_R 0x06bf 7664#define regMPC_RMU0_3DLUT_OUT_OFFSET_R_BASE_IDX 3 7665#define regMPC_RMU0_3DLUT_OUT_OFFSET_G 0x06c0 7666#define regMPC_RMU0_3DLUT_OUT_OFFSET_G_BASE_IDX 3 7667#define regMPC_RMU0_3DLUT_OUT_OFFSET_B 0x06c1 7668#define regMPC_RMU0_3DLUT_OUT_OFFSET_B_BASE_IDX 3 7669#define regMPC_RMU1_SHAPER_CONTROL 0x06c2 7670#define regMPC_RMU1_SHAPER_CONTROL_BASE_IDX 3 7671#define regMPC_RMU1_SHAPER_OFFSET_R 0x06c3 7672#define regMPC_RMU1_SHAPER_OFFSET_R_BASE_IDX 3 7673#define regMPC_RMU1_SHAPER_OFFSET_G 0x06c4 7674#define regMPC_RMU1_SHAPER_OFFSET_G_BASE_IDX 3 7675#define regMPC_RMU1_SHAPER_OFFSET_B 0x06c5 7676#define regMPC_RMU1_SHAPER_OFFSET_B_BASE_IDX 3 7677#define regMPC_RMU1_SHAPER_SCALE_R 0x06c6 7678#define regMPC_RMU1_SHAPER_SCALE_R_BASE_IDX 3 7679#define regMPC_RMU1_SHAPER_SCALE_G_B 0x06c7 7680#define regMPC_RMU1_SHAPER_SCALE_G_B_BASE_IDX 3 7681#define regMPC_RMU1_SHAPER_LUT_INDEX 0x06c8 7682#define regMPC_RMU1_SHAPER_LUT_INDEX_BASE_IDX 3 7683#define regMPC_RMU1_SHAPER_LUT_DATA 0x06c9 7684#define regMPC_RMU1_SHAPER_LUT_DATA_BASE_IDX 3 7685#define regMPC_RMU1_SHAPER_LUT_WRITE_EN_MASK 0x06ca 7686#define regMPC_RMU1_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX 3 7687#define regMPC_RMU1_SHAPER_RAMA_START_CNTL_B 0x06cb 7688#define regMPC_RMU1_SHAPER_RAMA_START_CNTL_B_BASE_IDX 3 7689#define regMPC_RMU1_SHAPER_RAMA_START_CNTL_G 0x06cc 7690#define regMPC_RMU1_SHAPER_RAMA_START_CNTL_G_BASE_IDX 3 7691#define regMPC_RMU1_SHAPER_RAMA_START_CNTL_R 0x06cd 7692#define regMPC_RMU1_SHAPER_RAMA_START_CNTL_R_BASE_IDX 3 7693#define regMPC_RMU1_SHAPER_RAMA_END_CNTL_B 0x06ce 7694#define regMPC_RMU1_SHAPER_RAMA_END_CNTL_B_BASE_IDX 3 7695#define regMPC_RMU1_SHAPER_RAMA_END_CNTL_G 0x06cf 7696#define regMPC_RMU1_SHAPER_RAMA_END_CNTL_G_BASE_IDX 3 7697#define regMPC_RMU1_SHAPER_RAMA_END_CNTL_R 0x06d0 7698#define regMPC_RMU1_SHAPER_RAMA_END_CNTL_R_BASE_IDX 3 7699#define regMPC_RMU1_SHAPER_RAMA_REGION_0_1 0x06d1 7700#define regMPC_RMU1_SHAPER_RAMA_REGION_0_1_BASE_IDX 3 7701#define regMPC_RMU1_SHAPER_RAMA_REGION_2_3 0x06d2 7702#define regMPC_RMU1_SHAPER_RAMA_REGION_2_3_BASE_IDX 3 7703#define regMPC_RMU1_SHAPER_RAMA_REGION_4_5 0x06d3 7704#define regMPC_RMU1_SHAPER_RAMA_REGION_4_5_BASE_IDX 3 7705#define regMPC_RMU1_SHAPER_RAMA_REGION_6_7 0x06d4 7706#define regMPC_RMU1_SHAPER_RAMA_REGION_6_7_BASE_IDX 3 7707#define regMPC_RMU1_SHAPER_RAMA_REGION_8_9 0x06d5 7708#define regMPC_RMU1_SHAPER_RAMA_REGION_8_9_BASE_IDX 3 7709#define regMPC_RMU1_SHAPER_RAMA_REGION_10_11 0x06d6 7710#define regMPC_RMU1_SHAPER_RAMA_REGION_10_11_BASE_IDX 3 7711#define regMPC_RMU1_SHAPER_RAMA_REGION_12_13 0x06d7 7712#define regMPC_RMU1_SHAPER_RAMA_REGION_12_13_BASE_IDX 3 7713#define regMPC_RMU1_SHAPER_RAMA_REGION_14_15 0x06d8 7714#define regMPC_RMU1_SHAPER_RAMA_REGION_14_15_BASE_IDX 3 7715#define regMPC_RMU1_SHAPER_RAMA_REGION_16_17 0x06d9 7716#define regMPC_RMU1_SHAPER_RAMA_REGION_16_17_BASE_IDX 3 7717#define regMPC_RMU1_SHAPER_RAMA_REGION_18_19 0x06da 7718#define regMPC_RMU1_SHAPER_RAMA_REGION_18_19_BASE_IDX 3 7719#define regMPC_RMU1_SHAPER_RAMA_REGION_20_21 0x06db 7720#define regMPC_RMU1_SHAPER_RAMA_REGION_20_21_BASE_IDX 3 7721#define regMPC_RMU1_SHAPER_RAMA_REGION_22_23 0x06dc 7722#define regMPC_RMU1_SHAPER_RAMA_REGION_22_23_BASE_IDX 3 7723#define regMPC_RMU1_SHAPER_RAMA_REGION_24_25 0x06dd 7724#define regMPC_RMU1_SHAPER_RAMA_REGION_24_25_BASE_IDX 3 7725#define regMPC_RMU1_SHAPER_RAMA_REGION_26_27 0x06de 7726#define regMPC_RMU1_SHAPER_RAMA_REGION_26_27_BASE_IDX 3 7727#define regMPC_RMU1_SHAPER_RAMA_REGION_28_29 0x06df 7728#define regMPC_RMU1_SHAPER_RAMA_REGION_28_29_BASE_IDX 3 7729#define regMPC_RMU1_SHAPER_RAMA_REGION_30_31 0x06e0 7730#define regMPC_RMU1_SHAPER_RAMA_REGION_30_31_BASE_IDX 3 7731#define regMPC_RMU1_SHAPER_RAMA_REGION_32_33 0x06e1 7732#define regMPC_RMU1_SHAPER_RAMA_REGION_32_33_BASE_IDX 3 7733#define regMPC_RMU1_SHAPER_RAMB_START_CNTL_B 0x06e2 7734#define regMPC_RMU1_SHAPER_RAMB_START_CNTL_B_BASE_IDX 3 7735#define regMPC_RMU1_SHAPER_RAMB_START_CNTL_G 0x06e3 7736#define regMPC_RMU1_SHAPER_RAMB_START_CNTL_G_BASE_IDX 3 7737#define regMPC_RMU1_SHAPER_RAMB_START_CNTL_R 0x06e4 7738#define regMPC_RMU1_SHAPER_RAMB_START_CNTL_R_BASE_IDX 3 7739#define regMPC_RMU1_SHAPER_RAMB_END_CNTL_B 0x06e5 7740#define regMPC_RMU1_SHAPER_RAMB_END_CNTL_B_BASE_IDX 3 7741#define regMPC_RMU1_SHAPER_RAMB_END_CNTL_G 0x06e6 7742#define regMPC_RMU1_SHAPER_RAMB_END_CNTL_G_BASE_IDX 3 7743#define regMPC_RMU1_SHAPER_RAMB_END_CNTL_R 0x06e7 7744#define regMPC_RMU1_SHAPER_RAMB_END_CNTL_R_BASE_IDX 3 7745#define regMPC_RMU1_SHAPER_RAMB_REGION_0_1 0x06e8 7746#define regMPC_RMU1_SHAPER_RAMB_REGION_0_1_BASE_IDX 3 7747#define regMPC_RMU1_SHAPER_RAMB_REGION_2_3 0x06e9 7748#define regMPC_RMU1_SHAPER_RAMB_REGION_2_3_BASE_IDX 3 7749#define regMPC_RMU1_SHAPER_RAMB_REGION_4_5 0x06ea 7750#define regMPC_RMU1_SHAPER_RAMB_REGION_4_5_BASE_IDX 3 7751#define regMPC_RMU1_SHAPER_RAMB_REGION_6_7 0x06eb 7752#define regMPC_RMU1_SHAPER_RAMB_REGION_6_7_BASE_IDX 3 7753#define regMPC_RMU1_SHAPER_RAMB_REGION_8_9 0x06ec 7754#define regMPC_RMU1_SHAPER_RAMB_REGION_8_9_BASE_IDX 3 7755#define regMPC_RMU1_SHAPER_RAMB_REGION_10_11 0x06ed 7756#define regMPC_RMU1_SHAPER_RAMB_REGION_10_11_BASE_IDX 3 7757#define regMPC_RMU1_SHAPER_RAMB_REGION_12_13 0x06ee 7758#define regMPC_RMU1_SHAPER_RAMB_REGION_12_13_BASE_IDX 3 7759#define regMPC_RMU1_SHAPER_RAMB_REGION_14_15 0x06ef 7760#define regMPC_RMU1_SHAPER_RAMB_REGION_14_15_BASE_IDX 3 7761#define regMPC_RMU1_SHAPER_RAMB_REGION_16_17 0x06f0 7762#define regMPC_RMU1_SHAPER_RAMB_REGION_16_17_BASE_IDX 3 7763#define regMPC_RMU1_SHAPER_RAMB_REGION_18_19 0x06f1 7764#define regMPC_RMU1_SHAPER_RAMB_REGION_18_19_BASE_IDX 3 7765#define regMPC_RMU1_SHAPER_RAMB_REGION_20_21 0x06f2 7766#define regMPC_RMU1_SHAPER_RAMB_REGION_20_21_BASE_IDX 3 7767#define regMPC_RMU1_SHAPER_RAMB_REGION_22_23 0x06f3 7768#define regMPC_RMU1_SHAPER_RAMB_REGION_22_23_BASE_IDX 3 7769#define regMPC_RMU1_SHAPER_RAMB_REGION_24_25 0x06f4 7770#define regMPC_RMU1_SHAPER_RAMB_REGION_24_25_BASE_IDX 3 7771#define regMPC_RMU1_SHAPER_RAMB_REGION_26_27 0x06f5 7772#define regMPC_RMU1_SHAPER_RAMB_REGION_26_27_BASE_IDX 3 7773#define regMPC_RMU1_SHAPER_RAMB_REGION_28_29 0x06f6 7774#define regMPC_RMU1_SHAPER_RAMB_REGION_28_29_BASE_IDX 3 7775#define regMPC_RMU1_SHAPER_RAMB_REGION_30_31 0x06f7 7776#define regMPC_RMU1_SHAPER_RAMB_REGION_30_31_BASE_IDX 3 7777#define regMPC_RMU1_SHAPER_RAMB_REGION_32_33 0x06f8 7778#define regMPC_RMU1_SHAPER_RAMB_REGION_32_33_BASE_IDX 3 7779#define regMPC_RMU1_3DLUT_MODE 0x06f9 7780#define regMPC_RMU1_3DLUT_MODE_BASE_IDX 3 7781#define regMPC_RMU1_3DLUT_INDEX 0x06fa 7782#define regMPC_RMU1_3DLUT_INDEX_BASE_IDX 3 7783#define regMPC_RMU1_3DLUT_DATA 0x06fb 7784#define regMPC_RMU1_3DLUT_DATA_BASE_IDX 3 7785#define regMPC_RMU1_3DLUT_DATA_30BIT 0x06fc 7786#define regMPC_RMU1_3DLUT_DATA_30BIT_BASE_IDX 3 7787#define regMPC_RMU1_3DLUT_READ_WRITE_CONTROL 0x06fd 7788#define regMPC_RMU1_3DLUT_READ_WRITE_CONTROL_BASE_IDX 3 7789#define regMPC_RMU1_3DLUT_OUT_NORM_FACTOR 0x06fe 7790#define regMPC_RMU1_3DLUT_OUT_NORM_FACTOR_BASE_IDX 3 7791#define regMPC_RMU1_3DLUT_OUT_OFFSET_R 0x06ff 7792#define regMPC_RMU1_3DLUT_OUT_OFFSET_R_BASE_IDX 3 7793#define regMPC_RMU1_3DLUT_OUT_OFFSET_G 0x0700 7794#define regMPC_RMU1_3DLUT_OUT_OFFSET_G_BASE_IDX 3 7795#define regMPC_RMU1_3DLUT_OUT_OFFSET_B 0x0701 7796#define regMPC_RMU1_3DLUT_OUT_OFFSET_B_BASE_IDX 3 7797 7798 7799// addressBlock: dce_dc_opp_abm0_dispdec 7800// base address: 0x0 7801#define regABM0_BL1_PWM_AMBIENT_LIGHT_LEVEL 0x0e7a 7802#define regABM0_BL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX 3 7803#define regABM0_BL1_PWM_USER_LEVEL 0x0e7b 7804#define regABM0_BL1_PWM_USER_LEVEL_BASE_IDX 3 7805#define regABM0_BL1_PWM_TARGET_ABM_LEVEL 0x0e7c 7806#define regABM0_BL1_PWM_TARGET_ABM_LEVEL_BASE_IDX 3 7807#define regABM0_BL1_PWM_CURRENT_ABM_LEVEL 0x0e7d 7808#define regABM0_BL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX 3 7809#define regABM0_BL1_PWM_FINAL_DUTY_CYCLE 0x0e7e 7810#define regABM0_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX 3 7811#define regABM0_BL1_PWM_MINIMUM_DUTY_CYCLE 0x0e7f 7812#define regABM0_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX 3 7813#define regABM0_BL1_PWM_ABM_CNTL 0x0e80 7814#define regABM0_BL1_PWM_ABM_CNTL_BASE_IDX 3 7815#define regABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE 0x0e81 7816#define regABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX 3 7817#define regABM0_BL1_PWM_GRP2_REG_LOCK 0x0e82 7818#define regABM0_BL1_PWM_GRP2_REG_LOCK_BASE_IDX 3 7819#define regABM0_DC_ABM1_CNTL 0x0e83 7820#define regABM0_DC_ABM1_CNTL_BASE_IDX 3 7821#define regABM0_DC_ABM1_IPCSC_COEFF_SEL 0x0e84 7822#define regABM0_DC_ABM1_IPCSC_COEFF_SEL_BASE_IDX 3 7823#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_0 0x0e85 7824#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_0_BASE_IDX 3 7825#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_1 0x0e86 7826#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_1_BASE_IDX 3 7827#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_2 0x0e87 7828#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_2_BASE_IDX 3 7829#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_3 0x0e88 7830#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_3_BASE_IDX 3 7831#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_4 0x0e89 7832#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_4_BASE_IDX 3 7833#define regABM0_DC_ABM1_ACE_THRES_12 0x0e8a 7834#define regABM0_DC_ABM1_ACE_THRES_12_BASE_IDX 3 7835#define regABM0_DC_ABM1_ACE_THRES_34 0x0e8b 7836#define regABM0_DC_ABM1_ACE_THRES_34_BASE_IDX 3 7837#define regABM0_DC_ABM1_ACE_CNTL_MISC 0x0e8c 7838#define regABM0_DC_ABM1_ACE_CNTL_MISC_BASE_IDX 3 7839#define regABM0_DC_ABM1_HGLS_REG_READ_PROGRESS 0x0e8e 7840#define regABM0_DC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX 3 7841#define regABM0_DC_ABM1_HG_MISC_CTRL 0x0e8f 7842#define regABM0_DC_ABM1_HG_MISC_CTRL_BASE_IDX 3 7843#define regABM0_DC_ABM1_LS_SUM_OF_LUMA 0x0e90 7844#define regABM0_DC_ABM1_LS_SUM_OF_LUMA_BASE_IDX 3 7845#define regABM0_DC_ABM1_LS_MIN_MAX_LUMA 0x0e91 7846#define regABM0_DC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX 3 7847#define regABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA 0x0e92 7848#define regABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX 3 7849#define regABM0_DC_ABM1_LS_PIXEL_COUNT 0x0e93 7850#define regABM0_DC_ABM1_LS_PIXEL_COUNT_BASE_IDX 3 7851#define regABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES 0x0e94 7852#define regABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX 3 7853#define regABM0_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT 0x0e95 7854#define regABM0_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX 3 7855#define regABM0_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT 0x0e96 7856#define regABM0_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX 3 7857#define regABM0_DC_ABM1_HG_SAMPLE_RATE 0x0e97 7858#define regABM0_DC_ABM1_HG_SAMPLE_RATE_BASE_IDX 3 7859#define regABM0_DC_ABM1_LS_SAMPLE_RATE 0x0e98 7860#define regABM0_DC_ABM1_LS_SAMPLE_RATE_BASE_IDX 3 7861#define regABM0_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG 0x0e99 7862#define regABM0_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX 3 7863#define regABM0_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX 0x0e9a 7864#define regABM0_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX 3 7865#define regABM0_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX 0x0e9b 7866#define regABM0_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX 3 7867#define regABM0_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX 0x0e9c 7868#define regABM0_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX 3 7869#define regABM0_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX 0x0e9d 7870#define regABM0_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX 3 7871#define regABM0_DC_ABM1_HG_RESULT_1 0x0e9e 7872#define regABM0_DC_ABM1_HG_RESULT_1_BASE_IDX 3 7873#define regABM0_DC_ABM1_HG_RESULT_2 0x0e9f 7874#define regABM0_DC_ABM1_HG_RESULT_2_BASE_IDX 3 7875#define regABM0_DC_ABM1_HG_RESULT_3 0x0ea0 7876#define regABM0_DC_ABM1_HG_RESULT_3_BASE_IDX 3 7877#define regABM0_DC_ABM1_HG_RESULT_4 0x0ea1 7878#define regABM0_DC_ABM1_HG_RESULT_4_BASE_IDX 3 7879#define regABM0_DC_ABM1_HG_RESULT_5 0x0ea2 7880#define regABM0_DC_ABM1_HG_RESULT_5_BASE_IDX 3 7881#define regABM0_DC_ABM1_HG_RESULT_6 0x0ea3 7882#define regABM0_DC_ABM1_HG_RESULT_6_BASE_IDX 3 7883#define regABM0_DC_ABM1_HG_RESULT_7 0x0ea4 7884#define regABM0_DC_ABM1_HG_RESULT_7_BASE_IDX 3 7885#define regABM0_DC_ABM1_HG_RESULT_8 0x0ea5 7886#define regABM0_DC_ABM1_HG_RESULT_8_BASE_IDX 3 7887#define regABM0_DC_ABM1_HG_RESULT_9 0x0ea6 7888#define regABM0_DC_ABM1_HG_RESULT_9_BASE_IDX 3 7889#define regABM0_DC_ABM1_HG_RESULT_10 0x0ea7 7890#define regABM0_DC_ABM1_HG_RESULT_10_BASE_IDX 3 7891#define regABM0_DC_ABM1_HG_RESULT_11 0x0ea8 7892#define regABM0_DC_ABM1_HG_RESULT_11_BASE_IDX 3 7893#define regABM0_DC_ABM1_HG_RESULT_12 0x0ea9 7894#define regABM0_DC_ABM1_HG_RESULT_12_BASE_IDX 3 7895#define regABM0_DC_ABM1_HG_RESULT_13 0x0eaa 7896#define regABM0_DC_ABM1_HG_RESULT_13_BASE_IDX 3 7897#define regABM0_DC_ABM1_HG_RESULT_14 0x0eab 7898#define regABM0_DC_ABM1_HG_RESULT_14_BASE_IDX 3 7899#define regABM0_DC_ABM1_HG_RESULT_15 0x0eac 7900#define regABM0_DC_ABM1_HG_RESULT_15_BASE_IDX 3 7901#define regABM0_DC_ABM1_HG_RESULT_16 0x0ead 7902#define regABM0_DC_ABM1_HG_RESULT_16_BASE_IDX 3 7903#define regABM0_DC_ABM1_HG_RESULT_17 0x0eae 7904#define regABM0_DC_ABM1_HG_RESULT_17_BASE_IDX 3 7905#define regABM0_DC_ABM1_HG_RESULT_18 0x0eaf 7906#define regABM0_DC_ABM1_HG_RESULT_18_BASE_IDX 3 7907#define regABM0_DC_ABM1_HG_RESULT_19 0x0eb0 7908#define regABM0_DC_ABM1_HG_RESULT_19_BASE_IDX 3 7909#define regABM0_DC_ABM1_HG_RESULT_20 0x0eb1 7910#define regABM0_DC_ABM1_HG_RESULT_20_BASE_IDX 3 7911#define regABM0_DC_ABM1_HG_RESULT_21 0x0eb2 7912#define regABM0_DC_ABM1_HG_RESULT_21_BASE_IDX 3 7913#define regABM0_DC_ABM1_HG_RESULT_22 0x0eb3 7914#define regABM0_DC_ABM1_HG_RESULT_22_BASE_IDX 3 7915#define regABM0_DC_ABM1_HG_RESULT_23 0x0eb4 7916#define regABM0_DC_ABM1_HG_RESULT_23_BASE_IDX 3 7917#define regABM0_DC_ABM1_HG_RESULT_24 0x0eb5 7918#define regABM0_DC_ABM1_HG_RESULT_24_BASE_IDX 3 7919#define regABM0_DC_ABM1_BL_MASTER_LOCK 0x0eb6 7920#define regABM0_DC_ABM1_BL_MASTER_LOCK_BASE_IDX 3 7921 7922 7923// addressBlock: dce_dc_opp_abm1_dispdec 7924// base address: 0x104 7925#define regABM1_BL1_PWM_AMBIENT_LIGHT_LEVEL 0x0ebb 7926#define regABM1_BL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX 3 7927#define regABM1_BL1_PWM_USER_LEVEL 0x0ebc 7928#define regABM1_BL1_PWM_USER_LEVEL_BASE_IDX 3 7929#define regABM1_BL1_PWM_TARGET_ABM_LEVEL 0x0ebd 7930#define regABM1_BL1_PWM_TARGET_ABM_LEVEL_BASE_IDX 3 7931#define regABM1_BL1_PWM_CURRENT_ABM_LEVEL 0x0ebe 7932#define regABM1_BL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX 3 7933#define regABM1_BL1_PWM_FINAL_DUTY_CYCLE 0x0ebf 7934#define regABM1_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX 3 7935#define regABM1_BL1_PWM_MINIMUM_DUTY_CYCLE 0x0ec0 7936#define regABM1_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX 3 7937#define regABM1_BL1_PWM_ABM_CNTL 0x0ec1 7938#define regABM1_BL1_PWM_ABM_CNTL_BASE_IDX 3 7939#define regABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE 0x0ec2 7940#define regABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX 3 7941#define regABM1_BL1_PWM_GRP2_REG_LOCK 0x0ec3 7942#define regABM1_BL1_PWM_GRP2_REG_LOCK_BASE_IDX 3 7943#define regABM1_DC_ABM1_CNTL 0x0ec4 7944#define regABM1_DC_ABM1_CNTL_BASE_IDX 3 7945#define regABM1_DC_ABM1_IPCSC_COEFF_SEL 0x0ec5 7946#define regABM1_DC_ABM1_IPCSC_COEFF_SEL_BASE_IDX 3 7947#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_0 0x0ec6 7948#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_0_BASE_IDX 3 7949#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_1 0x0ec7 7950#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_1_BASE_IDX 3 7951#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_2 0x0ec8 7952#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_2_BASE_IDX 3 7953#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_3 0x0ec9 7954#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_3_BASE_IDX 3 7955#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_4 0x0eca 7956#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_4_BASE_IDX 3 7957#define regABM1_DC_ABM1_ACE_THRES_12 0x0ecb 7958#define regABM1_DC_ABM1_ACE_THRES_12_BASE_IDX 3 7959#define regABM1_DC_ABM1_ACE_THRES_34 0x0ecc 7960#define regABM1_DC_ABM1_ACE_THRES_34_BASE_IDX 3 7961#define regABM1_DC_ABM1_ACE_CNTL_MISC 0x0ecd 7962#define regABM1_DC_ABM1_ACE_CNTL_MISC_BASE_IDX 3 7963#define regABM1_DC_ABM1_HGLS_REG_READ_PROGRESS 0x0ecf 7964#define regABM1_DC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX 3 7965#define regABM1_DC_ABM1_HG_MISC_CTRL 0x0ed0 7966#define regABM1_DC_ABM1_HG_MISC_CTRL_BASE_IDX 3 7967#define regABM1_DC_ABM1_LS_SUM_OF_LUMA 0x0ed1 7968#define regABM1_DC_ABM1_LS_SUM_OF_LUMA_BASE_IDX 3 7969#define regABM1_DC_ABM1_LS_MIN_MAX_LUMA 0x0ed2 7970#define regABM1_DC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX 3 7971#define regABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA 0x0ed3 7972#define regABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX 3 7973#define regABM1_DC_ABM1_LS_PIXEL_COUNT 0x0ed4 7974#define regABM1_DC_ABM1_LS_PIXEL_COUNT_BASE_IDX 3 7975#define regABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES 0x0ed5 7976#define regABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX 3 7977#define regABM1_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT 0x0ed6 7978#define regABM1_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX 3 7979#define regABM1_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT 0x0ed7 7980#define regABM1_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX 3 7981#define regABM1_DC_ABM1_HG_SAMPLE_RATE 0x0ed8 7982#define regABM1_DC_ABM1_HG_SAMPLE_RATE_BASE_IDX 3 7983#define regABM1_DC_ABM1_LS_SAMPLE_RATE 0x0ed9 7984#define regABM1_DC_ABM1_LS_SAMPLE_RATE_BASE_IDX 3 7985#define regABM1_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG 0x0eda 7986#define regABM1_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX 3 7987#define regABM1_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX 0x0edb 7988#define regABM1_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX 3 7989#define regABM1_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX 0x0edc 7990#define regABM1_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX 3 7991#define regABM1_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX 0x0edd 7992#define regABM1_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX 3 7993#define regABM1_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX 0x0ede 7994#define regABM1_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX 3 7995#define regABM1_DC_ABM1_HG_RESULT_1 0x0edf 7996#define regABM1_DC_ABM1_HG_RESULT_1_BASE_IDX 3 7997#define regABM1_DC_ABM1_HG_RESULT_2 0x0ee0 7998#define regABM1_DC_ABM1_HG_RESULT_2_BASE_IDX 3 7999#define regABM1_DC_ABM1_HG_RESULT_3 0x0ee1 8000#define regABM1_DC_ABM1_HG_RESULT_3_BASE_IDX 3 8001#define regABM1_DC_ABM1_HG_RESULT_4 0x0ee2 8002#define regABM1_DC_ABM1_HG_RESULT_4_BASE_IDX 3 8003#define regABM1_DC_ABM1_HG_RESULT_5 0x0ee3 8004#define regABM1_DC_ABM1_HG_RESULT_5_BASE_IDX 3 8005#define regABM1_DC_ABM1_HG_RESULT_6 0x0ee4 8006#define regABM1_DC_ABM1_HG_RESULT_6_BASE_IDX 3 8007#define regABM1_DC_ABM1_HG_RESULT_7 0x0ee5 8008#define regABM1_DC_ABM1_HG_RESULT_7_BASE_IDX 3 8009#define regABM1_DC_ABM1_HG_RESULT_8 0x0ee6 8010#define regABM1_DC_ABM1_HG_RESULT_8_BASE_IDX 3 8011#define regABM1_DC_ABM1_HG_RESULT_9 0x0ee7 8012#define regABM1_DC_ABM1_HG_RESULT_9_BASE_IDX 3 8013#define regABM1_DC_ABM1_HG_RESULT_10 0x0ee8 8014#define regABM1_DC_ABM1_HG_RESULT_10_BASE_IDX 3 8015#define regABM1_DC_ABM1_HG_RESULT_11 0x0ee9 8016#define regABM1_DC_ABM1_HG_RESULT_11_BASE_IDX 3 8017#define regABM1_DC_ABM1_HG_RESULT_12 0x0eea 8018#define regABM1_DC_ABM1_HG_RESULT_12_BASE_IDX 3 8019#define regABM1_DC_ABM1_HG_RESULT_13 0x0eeb 8020#define regABM1_DC_ABM1_HG_RESULT_13_BASE_IDX 3 8021#define regABM1_DC_ABM1_HG_RESULT_14 0x0eec 8022#define regABM1_DC_ABM1_HG_RESULT_14_BASE_IDX 3 8023#define regABM1_DC_ABM1_HG_RESULT_15 0x0eed 8024#define regABM1_DC_ABM1_HG_RESULT_15_BASE_IDX 3 8025#define regABM1_DC_ABM1_HG_RESULT_16 0x0eee 8026#define regABM1_DC_ABM1_HG_RESULT_16_BASE_IDX 3 8027#define regABM1_DC_ABM1_HG_RESULT_17 0x0eef 8028#define regABM1_DC_ABM1_HG_RESULT_17_BASE_IDX 3 8029#define regABM1_DC_ABM1_HG_RESULT_18 0x0ef0 8030#define regABM1_DC_ABM1_HG_RESULT_18_BASE_IDX 3 8031#define regABM1_DC_ABM1_HG_RESULT_19 0x0ef1 8032#define regABM1_DC_ABM1_HG_RESULT_19_BASE_IDX 3 8033#define regABM1_DC_ABM1_HG_RESULT_20 0x0ef2 8034#define regABM1_DC_ABM1_HG_RESULT_20_BASE_IDX 3 8035#define regABM1_DC_ABM1_HG_RESULT_21 0x0ef3 8036#define regABM1_DC_ABM1_HG_RESULT_21_BASE_IDX 3 8037#define regABM1_DC_ABM1_HG_RESULT_22 0x0ef4 8038#define regABM1_DC_ABM1_HG_RESULT_22_BASE_IDX 3 8039#define regABM1_DC_ABM1_HG_RESULT_23 0x0ef5 8040#define regABM1_DC_ABM1_HG_RESULT_23_BASE_IDX 3 8041#define regABM1_DC_ABM1_HG_RESULT_24 0x0ef6 8042#define regABM1_DC_ABM1_HG_RESULT_24_BASE_IDX 3 8043#define regABM1_DC_ABM1_BL_MASTER_LOCK 0x0ef7 8044#define regABM1_DC_ABM1_BL_MASTER_LOCK_BASE_IDX 3 8045 8046 8047// addressBlock: dce_dc_opp_abm2_dispdec 8048// base address: 0x208 8049#define regABM2_BL1_PWM_AMBIENT_LIGHT_LEVEL 0x0efc 8050#define regABM2_BL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX 3 8051#define regABM2_BL1_PWM_USER_LEVEL 0x0efd 8052#define regABM2_BL1_PWM_USER_LEVEL_BASE_IDX 3 8053#define regABM2_BL1_PWM_TARGET_ABM_LEVEL 0x0efe 8054#define regABM2_BL1_PWM_TARGET_ABM_LEVEL_BASE_IDX 3 8055#define regABM2_BL1_PWM_CURRENT_ABM_LEVEL 0x0eff 8056#define regABM2_BL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX 3 8057#define regABM2_BL1_PWM_FINAL_DUTY_CYCLE 0x0f00 8058#define regABM2_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX 3 8059#define regABM2_BL1_PWM_MINIMUM_DUTY_CYCLE 0x0f01 8060#define regABM2_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX 3 8061#define regABM2_BL1_PWM_ABM_CNTL 0x0f02 8062#define regABM2_BL1_PWM_ABM_CNTL_BASE_IDX 3 8063#define regABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE 0x0f03 8064#define regABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX 3 8065#define regABM2_BL1_PWM_GRP2_REG_LOCK 0x0f04 8066#define regABM2_BL1_PWM_GRP2_REG_LOCK_BASE_IDX 3 8067#define regABM2_DC_ABM1_CNTL 0x0f05 8068#define regABM2_DC_ABM1_CNTL_BASE_IDX 3 8069#define regABM2_DC_ABM1_IPCSC_COEFF_SEL 0x0f06 8070#define regABM2_DC_ABM1_IPCSC_COEFF_SEL_BASE_IDX 3 8071#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_0 0x0f07 8072#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_0_BASE_IDX 3 8073#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_1 0x0f08 8074#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_1_BASE_IDX 3 8075#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_2 0x0f09 8076#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_2_BASE_IDX 3 8077#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_3 0x0f0a 8078#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_3_BASE_IDX 3 8079#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_4 0x0f0b 8080#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_4_BASE_IDX 3 8081#define regABM2_DC_ABM1_ACE_THRES_12 0x0f0c 8082#define regABM2_DC_ABM1_ACE_THRES_12_BASE_IDX 3 8083#define regABM2_DC_ABM1_ACE_THRES_34 0x0f0d 8084#define regABM2_DC_ABM1_ACE_THRES_34_BASE_IDX 3 8085#define regABM2_DC_ABM1_ACE_CNTL_MISC 0x0f0e 8086#define regABM2_DC_ABM1_ACE_CNTL_MISC_BASE_IDX 3 8087#define regABM2_DC_ABM1_HGLS_REG_READ_PROGRESS 0x0f10 8088#define regABM2_DC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX 3 8089#define regABM2_DC_ABM1_HG_MISC_CTRL 0x0f11 8090#define regABM2_DC_ABM1_HG_MISC_CTRL_BASE_IDX 3 8091#define regABM2_DC_ABM1_LS_SUM_OF_LUMA 0x0f12 8092#define regABM2_DC_ABM1_LS_SUM_OF_LUMA_BASE_IDX 3 8093#define regABM2_DC_ABM1_LS_MIN_MAX_LUMA 0x0f13 8094#define regABM2_DC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX 3 8095#define regABM2_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA 0x0f14 8096#define regABM2_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX 3 8097#define regABM2_DC_ABM1_LS_PIXEL_COUNT 0x0f15 8098#define regABM2_DC_ABM1_LS_PIXEL_COUNT_BASE_IDX 3 8099#define regABM2_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES 0x0f16 8100#define regABM2_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX 3 8101#define regABM2_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT 0x0f17 8102#define regABM2_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX 3 8103#define regABM2_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT 0x0f18 8104#define regABM2_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX 3 8105#define regABM2_DC_ABM1_HG_SAMPLE_RATE 0x0f19 8106#define regABM2_DC_ABM1_HG_SAMPLE_RATE_BASE_IDX 3 8107#define regABM2_DC_ABM1_LS_SAMPLE_RATE 0x0f1a 8108#define regABM2_DC_ABM1_LS_SAMPLE_RATE_BASE_IDX 3 8109#define regABM2_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG 0x0f1b 8110#define regABM2_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX 3 8111#define regABM2_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX 0x0f1c 8112#define regABM2_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX 3 8113#define regABM2_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX 0x0f1d 8114#define regABM2_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX 3 8115#define regABM2_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX 0x0f1e 8116#define regABM2_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX 3 8117#define regABM2_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX 0x0f1f 8118#define regABM2_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX 3 8119#define regABM2_DC_ABM1_HG_RESULT_1 0x0f20 8120#define regABM2_DC_ABM1_HG_RESULT_1_BASE_IDX 3 8121#define regABM2_DC_ABM1_HG_RESULT_2 0x0f21 8122#define regABM2_DC_ABM1_HG_RESULT_2_BASE_IDX 3 8123#define regABM2_DC_ABM1_HG_RESULT_3 0x0f22 8124#define regABM2_DC_ABM1_HG_RESULT_3_BASE_IDX 3 8125#define regABM2_DC_ABM1_HG_RESULT_4 0x0f23 8126#define regABM2_DC_ABM1_HG_RESULT_4_BASE_IDX 3 8127#define regABM2_DC_ABM1_HG_RESULT_5 0x0f24 8128#define regABM2_DC_ABM1_HG_RESULT_5_BASE_IDX 3 8129#define regABM2_DC_ABM1_HG_RESULT_6 0x0f25 8130#define regABM2_DC_ABM1_HG_RESULT_6_BASE_IDX 3 8131#define regABM2_DC_ABM1_HG_RESULT_7 0x0f26 8132#define regABM2_DC_ABM1_HG_RESULT_7_BASE_IDX 3 8133#define regABM2_DC_ABM1_HG_RESULT_8 0x0f27 8134#define regABM2_DC_ABM1_HG_RESULT_8_BASE_IDX 3 8135#define regABM2_DC_ABM1_HG_RESULT_9 0x0f28 8136#define regABM2_DC_ABM1_HG_RESULT_9_BASE_IDX 3 8137#define regABM2_DC_ABM1_HG_RESULT_10 0x0f29 8138#define regABM2_DC_ABM1_HG_RESULT_10_BASE_IDX 3 8139#define regABM2_DC_ABM1_HG_RESULT_11 0x0f2a 8140#define regABM2_DC_ABM1_HG_RESULT_11_BASE_IDX 3 8141#define regABM2_DC_ABM1_HG_RESULT_12 0x0f2b 8142#define regABM2_DC_ABM1_HG_RESULT_12_BASE_IDX 3 8143#define regABM2_DC_ABM1_HG_RESULT_13 0x0f2c 8144#define regABM2_DC_ABM1_HG_RESULT_13_BASE_IDX 3 8145#define regABM2_DC_ABM1_HG_RESULT_14 0x0f2d 8146#define regABM2_DC_ABM1_HG_RESULT_14_BASE_IDX 3 8147#define regABM2_DC_ABM1_HG_RESULT_15 0x0f2e 8148#define regABM2_DC_ABM1_HG_RESULT_15_BASE_IDX 3 8149#define regABM2_DC_ABM1_HG_RESULT_16 0x0f2f 8150#define regABM2_DC_ABM1_HG_RESULT_16_BASE_IDX 3 8151#define regABM2_DC_ABM1_HG_RESULT_17 0x0f30 8152#define regABM2_DC_ABM1_HG_RESULT_17_BASE_IDX 3 8153#define regABM2_DC_ABM1_HG_RESULT_18 0x0f31 8154#define regABM2_DC_ABM1_HG_RESULT_18_BASE_IDX 3 8155#define regABM2_DC_ABM1_HG_RESULT_19 0x0f32 8156#define regABM2_DC_ABM1_HG_RESULT_19_BASE_IDX 3 8157#define regABM2_DC_ABM1_HG_RESULT_20 0x0f33 8158#define regABM2_DC_ABM1_HG_RESULT_20_BASE_IDX 3 8159#define regABM2_DC_ABM1_HG_RESULT_21 0x0f34 8160#define regABM2_DC_ABM1_HG_RESULT_21_BASE_IDX 3 8161#define regABM2_DC_ABM1_HG_RESULT_22 0x0f35 8162#define regABM2_DC_ABM1_HG_RESULT_22_BASE_IDX 3 8163#define regABM2_DC_ABM1_HG_RESULT_23 0x0f36 8164#define regABM2_DC_ABM1_HG_RESULT_23_BASE_IDX 3 8165#define regABM2_DC_ABM1_HG_RESULT_24 0x0f37 8166#define regABM2_DC_ABM1_HG_RESULT_24_BASE_IDX 3 8167#define regABM2_DC_ABM1_BL_MASTER_LOCK 0x0f38 8168#define regABM2_DC_ABM1_BL_MASTER_LOCK_BASE_IDX 3 8169 8170 8171// addressBlock: dce_dc_opp_abm3_dispdec 8172// base address: 0x30c 8173#define regABM3_BL1_PWM_AMBIENT_LIGHT_LEVEL 0x0f3d 8174#define regABM3_BL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX 3 8175#define regABM3_BL1_PWM_USER_LEVEL 0x0f3e 8176#define regABM3_BL1_PWM_USER_LEVEL_BASE_IDX 3 8177#define regABM3_BL1_PWM_TARGET_ABM_LEVEL 0x0f3f 8178#define regABM3_BL1_PWM_TARGET_ABM_LEVEL_BASE_IDX 3 8179#define regABM3_BL1_PWM_CURRENT_ABM_LEVEL 0x0f40 8180#define regABM3_BL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX 3 8181#define regABM3_BL1_PWM_FINAL_DUTY_CYCLE 0x0f41 8182#define regABM3_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX 3 8183#define regABM3_BL1_PWM_MINIMUM_DUTY_CYCLE 0x0f42 8184#define regABM3_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX 3 8185#define regABM3_BL1_PWM_ABM_CNTL 0x0f43 8186#define regABM3_BL1_PWM_ABM_CNTL_BASE_IDX 3 8187#define regABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE 0x0f44 8188#define regABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX 3 8189#define regABM3_BL1_PWM_GRP2_REG_LOCK 0x0f45 8190#define regABM3_BL1_PWM_GRP2_REG_LOCK_BASE_IDX 3 8191#define regABM3_DC_ABM1_CNTL 0x0f46 8192#define regABM3_DC_ABM1_CNTL_BASE_IDX 3 8193#define regABM3_DC_ABM1_IPCSC_COEFF_SEL 0x0f47 8194#define regABM3_DC_ABM1_IPCSC_COEFF_SEL_BASE_IDX 3 8195#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_0 0x0f48 8196#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_0_BASE_IDX 3 8197#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_1 0x0f49 8198#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_1_BASE_IDX 3 8199#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_2 0x0f4a 8200#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_2_BASE_IDX 3 8201#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_3 0x0f4b 8202#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_3_BASE_IDX 3 8203#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_4 0x0f4c 8204#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_4_BASE_IDX 3 8205#define regABM3_DC_ABM1_ACE_THRES_12 0x0f4d 8206#define regABM3_DC_ABM1_ACE_THRES_12_BASE_IDX 3 8207#define regABM3_DC_ABM1_ACE_THRES_34 0x0f4e 8208#define regABM3_DC_ABM1_ACE_THRES_34_BASE_IDX 3 8209#define regABM3_DC_ABM1_ACE_CNTL_MISC 0x0f4f 8210#define regABM3_DC_ABM1_ACE_CNTL_MISC_BASE_IDX 3 8211#define regABM3_DC_ABM1_HGLS_REG_READ_PROGRESS 0x0f51 8212#define regABM3_DC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX 3 8213#define regABM3_DC_ABM1_HG_MISC_CTRL 0x0f52 8214#define regABM3_DC_ABM1_HG_MISC_CTRL_BASE_IDX 3 8215#define regABM3_DC_ABM1_LS_SUM_OF_LUMA 0x0f53 8216#define regABM3_DC_ABM1_LS_SUM_OF_LUMA_BASE_IDX 3 8217#define regABM3_DC_ABM1_LS_MIN_MAX_LUMA 0x0f54 8218#define regABM3_DC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX 3 8219#define regABM3_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA 0x0f55 8220#define regABM3_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX 3 8221#define regABM3_DC_ABM1_LS_PIXEL_COUNT 0x0f56 8222#define regABM3_DC_ABM1_LS_PIXEL_COUNT_BASE_IDX 3 8223#define regABM3_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES 0x0f57 8224#define regABM3_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX 3 8225#define regABM3_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT 0x0f58 8226#define regABM3_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX 3 8227#define regABM3_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT 0x0f59 8228#define regABM3_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX 3 8229#define regABM3_DC_ABM1_HG_SAMPLE_RATE 0x0f5a 8230#define regABM3_DC_ABM1_HG_SAMPLE_RATE_BASE_IDX 3 8231#define regABM3_DC_ABM1_LS_SAMPLE_RATE 0x0f5b 8232#define regABM3_DC_ABM1_LS_SAMPLE_RATE_BASE_IDX 3 8233#define regABM3_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG 0x0f5c 8234#define regABM3_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX 3 8235#define regABM3_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX 0x0f5d 8236#define regABM3_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX 3 8237#define regABM3_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX 0x0f5e 8238#define regABM3_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX 3 8239#define regABM3_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX 0x0f5f 8240#define regABM3_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX 3 8241#define regABM3_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX 0x0f60 8242#define regABM3_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX 3 8243#define regABM3_DC_ABM1_HG_RESULT_1 0x0f61 8244#define regABM3_DC_ABM1_HG_RESULT_1_BASE_IDX 3 8245#define regABM3_DC_ABM1_HG_RESULT_2 0x0f62 8246#define regABM3_DC_ABM1_HG_RESULT_2_BASE_IDX 3 8247#define regABM3_DC_ABM1_HG_RESULT_3 0x0f63 8248#define regABM3_DC_ABM1_HG_RESULT_3_BASE_IDX 3 8249#define regABM3_DC_ABM1_HG_RESULT_4 0x0f64 8250#define regABM3_DC_ABM1_HG_RESULT_4_BASE_IDX 3 8251#define regABM3_DC_ABM1_HG_RESULT_5 0x0f65 8252#define regABM3_DC_ABM1_HG_RESULT_5_BASE_IDX 3 8253#define regABM3_DC_ABM1_HG_RESULT_6 0x0f66 8254#define regABM3_DC_ABM1_HG_RESULT_6_BASE_IDX 3 8255#define regABM3_DC_ABM1_HG_RESULT_7 0x0f67 8256#define regABM3_DC_ABM1_HG_RESULT_7_BASE_IDX 3 8257#define regABM3_DC_ABM1_HG_RESULT_8 0x0f68 8258#define regABM3_DC_ABM1_HG_RESULT_8_BASE_IDX 3 8259#define regABM3_DC_ABM1_HG_RESULT_9 0x0f69 8260#define regABM3_DC_ABM1_HG_RESULT_9_BASE_IDX 3 8261#define regABM3_DC_ABM1_HG_RESULT_10 0x0f6a 8262#define regABM3_DC_ABM1_HG_RESULT_10_BASE_IDX 3 8263#define regABM3_DC_ABM1_HG_RESULT_11 0x0f6b 8264#define regABM3_DC_ABM1_HG_RESULT_11_BASE_IDX 3 8265#define regABM3_DC_ABM1_HG_RESULT_12 0x0f6c 8266#define regABM3_DC_ABM1_HG_RESULT_12_BASE_IDX 3 8267#define regABM3_DC_ABM1_HG_RESULT_13 0x0f6d 8268#define regABM3_DC_ABM1_HG_RESULT_13_BASE_IDX 3 8269#define regABM3_DC_ABM1_HG_RESULT_14 0x0f6e 8270#define regABM3_DC_ABM1_HG_RESULT_14_BASE_IDX 3 8271#define regABM3_DC_ABM1_HG_RESULT_15 0x0f6f 8272#define regABM3_DC_ABM1_HG_RESULT_15_BASE_IDX 3 8273#define regABM3_DC_ABM1_HG_RESULT_16 0x0f70 8274#define regABM3_DC_ABM1_HG_RESULT_16_BASE_IDX 3 8275#define regABM3_DC_ABM1_HG_RESULT_17 0x0f71 8276#define regABM3_DC_ABM1_HG_RESULT_17_BASE_IDX 3 8277#define regABM3_DC_ABM1_HG_RESULT_18 0x0f72 8278#define regABM3_DC_ABM1_HG_RESULT_18_BASE_IDX 3 8279#define regABM3_DC_ABM1_HG_RESULT_19 0x0f73 8280#define regABM3_DC_ABM1_HG_RESULT_19_BASE_IDX 3 8281#define regABM3_DC_ABM1_HG_RESULT_20 0x0f74 8282#define regABM3_DC_ABM1_HG_RESULT_20_BASE_IDX 3 8283#define regABM3_DC_ABM1_HG_RESULT_21 0x0f75 8284#define regABM3_DC_ABM1_HG_RESULT_21_BASE_IDX 3 8285#define regABM3_DC_ABM1_HG_RESULT_22 0x0f76 8286#define regABM3_DC_ABM1_HG_RESULT_22_BASE_IDX 3 8287#define regABM3_DC_ABM1_HG_RESULT_23 0x0f77 8288#define regABM3_DC_ABM1_HG_RESULT_23_BASE_IDX 3 8289#define regABM3_DC_ABM1_HG_RESULT_24 0x0f78 8290#define regABM3_DC_ABM1_HG_RESULT_24_BASE_IDX 3 8291#define regABM3_DC_ABM1_BL_MASTER_LOCK 0x0f79 8292#define regABM3_DC_ABM1_BL_MASTER_LOCK_BASE_IDX 3 8293 8294 8295// addressBlock: dce_dc_opp_dpg0_dispdec 8296// base address: 0x0 8297#define regDPG0_DPG_CONTROL 0x1854 8298#define regDPG0_DPG_CONTROL_BASE_IDX 2 8299#define regDPG0_DPG_RAMP_CONTROL 0x1855 8300#define regDPG0_DPG_RAMP_CONTROL_BASE_IDX 2 8301#define regDPG0_DPG_DIMENSIONS 0x1856 8302#define regDPG0_DPG_DIMENSIONS_BASE_IDX 2 8303#define regDPG0_DPG_COLOUR_R_CR 0x1857 8304#define regDPG0_DPG_COLOUR_R_CR_BASE_IDX 2 8305#define regDPG0_DPG_COLOUR_G_Y 0x1858 8306#define regDPG0_DPG_COLOUR_G_Y_BASE_IDX 2 8307#define regDPG0_DPG_COLOUR_B_CB 0x1859 8308#define regDPG0_DPG_COLOUR_B_CB_BASE_IDX 2 8309#define regDPG0_DPG_OFFSET_SEGMENT 0x185a 8310#define regDPG0_DPG_OFFSET_SEGMENT_BASE_IDX 2 8311#define regDPG0_DPG_STATUS 0x185b 8312#define regDPG0_DPG_STATUS_BASE_IDX 2 8313 8314 8315// addressBlock: dce_dc_opp_fmt0_dispdec 8316// base address: 0x0 8317#define regFMT0_FMT_CLAMP_COMPONENT_R 0x183c 8318#define regFMT0_FMT_CLAMP_COMPONENT_R_BASE_IDX 2 8319#define regFMT0_FMT_CLAMP_COMPONENT_G 0x183d 8320#define regFMT0_FMT_CLAMP_COMPONENT_G_BASE_IDX 2 8321#define regFMT0_FMT_CLAMP_COMPONENT_B 0x183e 8322#define regFMT0_FMT_CLAMP_COMPONENT_B_BASE_IDX 2 8323#define regFMT0_FMT_DYNAMIC_EXP_CNTL 0x183f 8324#define regFMT0_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2 8325#define regFMT0_FMT_CONTROL 0x1840 8326#define regFMT0_FMT_CONTROL_BASE_IDX 2 8327#define regFMT0_FMT_BIT_DEPTH_CONTROL 0x1841 8328#define regFMT0_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2 8329#define regFMT0_FMT_DITHER_RAND_R_SEED 0x1842 8330#define regFMT0_FMT_DITHER_RAND_R_SEED_BASE_IDX 2 8331#define regFMT0_FMT_DITHER_RAND_G_SEED 0x1843 8332#define regFMT0_FMT_DITHER_RAND_G_SEED_BASE_IDX 2 8333#define regFMT0_FMT_DITHER_RAND_B_SEED 0x1844 8334#define regFMT0_FMT_DITHER_RAND_B_SEED_BASE_IDX 2 8335#define regFMT0_FMT_CLAMP_CNTL 0x1845 8336#define regFMT0_FMT_CLAMP_CNTL_BASE_IDX 2 8337#define regFMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x1846 8338#define regFMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2 8339#define regFMT0_FMT_MAP420_MEMORY_CONTROL 0x1847 8340#define regFMT0_FMT_MAP420_MEMORY_CONTROL_BASE_IDX 2 8341#define regFMT0_FMT_422_CONTROL 0x1849 8342#define regFMT0_FMT_422_CONTROL_BASE_IDX 2 8343 8344 8345// addressBlock: dce_dc_opp_oppbuf0_dispdec 8346// base address: 0x0 8347#define regOPPBUF0_OPPBUF_CONTROL 0x1884 8348#define regOPPBUF0_OPPBUF_CONTROL_BASE_IDX 2 8349#define regOPPBUF0_OPPBUF_3D_PARAMETERS_0 0x1885 8350#define regOPPBUF0_OPPBUF_3D_PARAMETERS_0_BASE_IDX 2 8351#define regOPPBUF0_OPPBUF_3D_PARAMETERS_1 0x1886 8352#define regOPPBUF0_OPPBUF_3D_PARAMETERS_1_BASE_IDX 2 8353#define regOPPBUF0_OPPBUF_CONTROL1 0x1889 8354#define regOPPBUF0_OPPBUF_CONTROL1_BASE_IDX 2 8355 8356 8357// addressBlock: dce_dc_opp_opp_pipe0_dispdec 8358// base address: 0x0 8359#define regOPP_PIPE0_OPP_PIPE_CONTROL 0x188c 8360#define regOPP_PIPE0_OPP_PIPE_CONTROL_BASE_IDX 2 8361 8362 8363// addressBlock: dce_dc_opp_opp_pipe_crc0_dispdec 8364// base address: 0x0 8365#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL 0x1891 8366#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL_BASE_IDX 2 8367#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_MASK 0x1892 8368#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_MASK_BASE_IDX 2 8369#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0 0x1893 8370#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0_BASE_IDX 2 8371#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1 0x1894 8372#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1_BASE_IDX 2 8373#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2 0x1895 8374#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2_BASE_IDX 2 8375 8376 8377// addressBlock: dce_dc_opp_dpg1_dispdec 8378// base address: 0x168 8379#define regDPG1_DPG_CONTROL 0x18ae 8380#define regDPG1_DPG_CONTROL_BASE_IDX 2 8381#define regDPG1_DPG_RAMP_CONTROL 0x18af 8382#define regDPG1_DPG_RAMP_CONTROL_BASE_IDX 2 8383#define regDPG1_DPG_DIMENSIONS 0x18b0 8384#define regDPG1_DPG_DIMENSIONS_BASE_IDX 2 8385#define regDPG1_DPG_COLOUR_R_CR 0x18b1 8386#define regDPG1_DPG_COLOUR_R_CR_BASE_IDX 2 8387#define regDPG1_DPG_COLOUR_G_Y 0x18b2 8388#define regDPG1_DPG_COLOUR_G_Y_BASE_IDX 2 8389#define regDPG1_DPG_COLOUR_B_CB 0x18b3 8390#define regDPG1_DPG_COLOUR_B_CB_BASE_IDX 2 8391#define regDPG1_DPG_OFFSET_SEGMENT 0x18b4 8392#define regDPG1_DPG_OFFSET_SEGMENT_BASE_IDX 2 8393#define regDPG1_DPG_STATUS 0x18b5 8394#define regDPG1_DPG_STATUS_BASE_IDX 2 8395 8396 8397// addressBlock: dce_dc_opp_fmt1_dispdec 8398// base address: 0x168 8399#define regFMT1_FMT_CLAMP_COMPONENT_R 0x1896 8400#define regFMT1_FMT_CLAMP_COMPONENT_R_BASE_IDX 2 8401#define regFMT1_FMT_CLAMP_COMPONENT_G 0x1897 8402#define regFMT1_FMT_CLAMP_COMPONENT_G_BASE_IDX 2 8403#define regFMT1_FMT_CLAMP_COMPONENT_B 0x1898 8404#define regFMT1_FMT_CLAMP_COMPONENT_B_BASE_IDX 2 8405#define regFMT1_FMT_DYNAMIC_EXP_CNTL 0x1899 8406#define regFMT1_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2 8407#define regFMT1_FMT_CONTROL 0x189a 8408#define regFMT1_FMT_CONTROL_BASE_IDX 2 8409#define regFMT1_FMT_BIT_DEPTH_CONTROL 0x189b 8410#define regFMT1_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2 8411#define regFMT1_FMT_DITHER_RAND_R_SEED 0x189c 8412#define regFMT1_FMT_DITHER_RAND_R_SEED_BASE_IDX 2 8413#define regFMT1_FMT_DITHER_RAND_G_SEED 0x189d 8414#define regFMT1_FMT_DITHER_RAND_G_SEED_BASE_IDX 2 8415#define regFMT1_FMT_DITHER_RAND_B_SEED 0x189e 8416#define regFMT1_FMT_DITHER_RAND_B_SEED_BASE_IDX 2 8417#define regFMT1_FMT_CLAMP_CNTL 0x189f 8418#define regFMT1_FMT_CLAMP_CNTL_BASE_IDX 2 8419#define regFMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x18a0 8420#define regFMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2 8421#define regFMT1_FMT_MAP420_MEMORY_CONTROL 0x18a1 8422#define regFMT1_FMT_MAP420_MEMORY_CONTROL_BASE_IDX 2 8423#define regFMT1_FMT_422_CONTROL 0x18a3 8424#define regFMT1_FMT_422_CONTROL_BASE_IDX 2 8425 8426 8427// addressBlock: dce_dc_opp_oppbuf1_dispdec 8428// base address: 0x168 8429#define regOPPBUF1_OPPBUF_CONTROL 0x18de 8430#define regOPPBUF1_OPPBUF_CONTROL_BASE_IDX 2 8431#define regOPPBUF1_OPPBUF_3D_PARAMETERS_0 0x18df 8432#define regOPPBUF1_OPPBUF_3D_PARAMETERS_0_BASE_IDX 2 8433#define regOPPBUF1_OPPBUF_3D_PARAMETERS_1 0x18e0 8434#define regOPPBUF1_OPPBUF_3D_PARAMETERS_1_BASE_IDX 2 8435#define regOPPBUF1_OPPBUF_CONTROL1 0x18e3 8436#define regOPPBUF1_OPPBUF_CONTROL1_BASE_IDX 2 8437 8438 8439// addressBlock: dce_dc_opp_opp_pipe1_dispdec 8440// base address: 0x168 8441#define regOPP_PIPE1_OPP_PIPE_CONTROL 0x18e6 8442#define regOPP_PIPE1_OPP_PIPE_CONTROL_BASE_IDX 2 8443 8444 8445// addressBlock: dce_dc_opp_opp_pipe_crc1_dispdec 8446// base address: 0x168 8447#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL 0x18eb 8448#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL_BASE_IDX 2 8449#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_MASK 0x18ec 8450#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_MASK_BASE_IDX 2 8451#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0 0x18ed 8452#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0_BASE_IDX 2 8453#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1 0x18ee 8454#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1_BASE_IDX 2 8455#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2 0x18ef 8456#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2_BASE_IDX 2 8457 8458 8459// addressBlock: dce_dc_opp_dpg2_dispdec 8460// base address: 0x2d0 8461#define regDPG2_DPG_CONTROL 0x1908 8462#define regDPG2_DPG_CONTROL_BASE_IDX 2 8463#define regDPG2_DPG_RAMP_CONTROL 0x1909 8464#define regDPG2_DPG_RAMP_CONTROL_BASE_IDX 2 8465#define regDPG2_DPG_DIMENSIONS 0x190a 8466#define regDPG2_DPG_DIMENSIONS_BASE_IDX 2 8467#define regDPG2_DPG_COLOUR_R_CR 0x190b 8468#define regDPG2_DPG_COLOUR_R_CR_BASE_IDX 2 8469#define regDPG2_DPG_COLOUR_G_Y 0x190c 8470#define regDPG2_DPG_COLOUR_G_Y_BASE_IDX 2 8471#define regDPG2_DPG_COLOUR_B_CB 0x190d 8472#define regDPG2_DPG_COLOUR_B_CB_BASE_IDX 2 8473#define regDPG2_DPG_OFFSET_SEGMENT 0x190e 8474#define regDPG2_DPG_OFFSET_SEGMENT_BASE_IDX 2 8475#define regDPG2_DPG_STATUS 0x190f 8476#define regDPG2_DPG_STATUS_BASE_IDX 2 8477 8478 8479// addressBlock: dce_dc_opp_fmt2_dispdec 8480// base address: 0x2d0 8481#define regFMT2_FMT_CLAMP_COMPONENT_R 0x18f0 8482#define regFMT2_FMT_CLAMP_COMPONENT_R_BASE_IDX 2 8483#define regFMT2_FMT_CLAMP_COMPONENT_G 0x18f1 8484#define regFMT2_FMT_CLAMP_COMPONENT_G_BASE_IDX 2 8485#define regFMT2_FMT_CLAMP_COMPONENT_B 0x18f2 8486#define regFMT2_FMT_CLAMP_COMPONENT_B_BASE_IDX 2 8487#define regFMT2_FMT_DYNAMIC_EXP_CNTL 0x18f3 8488#define regFMT2_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2 8489#define regFMT2_FMT_CONTROL 0x18f4 8490#define regFMT2_FMT_CONTROL_BASE_IDX 2 8491#define regFMT2_FMT_BIT_DEPTH_CONTROL 0x18f5 8492#define regFMT2_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2 8493#define regFMT2_FMT_DITHER_RAND_R_SEED 0x18f6 8494#define regFMT2_FMT_DITHER_RAND_R_SEED_BASE_IDX 2 8495#define regFMT2_FMT_DITHER_RAND_G_SEED 0x18f7 8496#define regFMT2_FMT_DITHER_RAND_G_SEED_BASE_IDX 2 8497#define regFMT2_FMT_DITHER_RAND_B_SEED 0x18f8 8498#define regFMT2_FMT_DITHER_RAND_B_SEED_BASE_IDX 2 8499#define regFMT2_FMT_CLAMP_CNTL 0x18f9 8500#define regFMT2_FMT_CLAMP_CNTL_BASE_IDX 2 8501#define regFMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x18fa 8502#define regFMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2 8503#define regFMT2_FMT_MAP420_MEMORY_CONTROL 0x18fb 8504#define regFMT2_FMT_MAP420_MEMORY_CONTROL_BASE_IDX 2 8505#define regFMT2_FMT_422_CONTROL 0x18fd 8506#define regFMT2_FMT_422_CONTROL_BASE_IDX 2 8507 8508 8509// addressBlock: dce_dc_opp_oppbuf2_dispdec 8510// base address: 0x2d0 8511#define regOPPBUF2_OPPBUF_CONTROL 0x1938 8512#define regOPPBUF2_OPPBUF_CONTROL_BASE_IDX 2 8513#define regOPPBUF2_OPPBUF_3D_PARAMETERS_0 0x1939 8514#define regOPPBUF2_OPPBUF_3D_PARAMETERS_0_BASE_IDX 2 8515#define regOPPBUF2_OPPBUF_3D_PARAMETERS_1 0x193a 8516#define regOPPBUF2_OPPBUF_3D_PARAMETERS_1_BASE_IDX 2 8517#define regOPPBUF2_OPPBUF_CONTROL1 0x193d 8518#define regOPPBUF2_OPPBUF_CONTROL1_BASE_IDX 2 8519 8520 8521// addressBlock: dce_dc_opp_opp_pipe2_dispdec 8522// base address: 0x2d0 8523#define regOPP_PIPE2_OPP_PIPE_CONTROL 0x1940 8524#define regOPP_PIPE2_OPP_PIPE_CONTROL_BASE_IDX 2 8525 8526 8527// addressBlock: dce_dc_opp_opp_pipe_crc2_dispdec 8528// base address: 0x2d0 8529#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL 0x1945 8530#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL_BASE_IDX 2 8531#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_MASK 0x1946 8532#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_MASK_BASE_IDX 2 8533#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0 0x1947 8534#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0_BASE_IDX 2 8535#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1 0x1948 8536#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1_BASE_IDX 2 8537#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT2 0x1949 8538#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT2_BASE_IDX 2 8539 8540 8541// addressBlock: dce_dc_opp_dpg3_dispdec 8542// base address: 0x438 8543#define regDPG3_DPG_CONTROL 0x1962 8544#define regDPG3_DPG_CONTROL_BASE_IDX 2 8545#define regDPG3_DPG_RAMP_CONTROL 0x1963 8546#define regDPG3_DPG_RAMP_CONTROL_BASE_IDX 2 8547#define regDPG3_DPG_DIMENSIONS 0x1964 8548#define regDPG3_DPG_DIMENSIONS_BASE_IDX 2 8549#define regDPG3_DPG_COLOUR_R_CR 0x1965 8550#define regDPG3_DPG_COLOUR_R_CR_BASE_IDX 2 8551#define regDPG3_DPG_COLOUR_G_Y 0x1966 8552#define regDPG3_DPG_COLOUR_G_Y_BASE_IDX 2 8553#define regDPG3_DPG_COLOUR_B_CB 0x1967 8554#define regDPG3_DPG_COLOUR_B_CB_BASE_IDX 2 8555#define regDPG3_DPG_OFFSET_SEGMENT 0x1968 8556#define regDPG3_DPG_OFFSET_SEGMENT_BASE_IDX 2 8557#define regDPG3_DPG_STATUS 0x1969 8558#define regDPG3_DPG_STATUS_BASE_IDX 2 8559 8560 8561// addressBlock: dce_dc_opp_fmt3_dispdec 8562// base address: 0x438 8563#define regFMT3_FMT_CLAMP_COMPONENT_R 0x194a 8564#define regFMT3_FMT_CLAMP_COMPONENT_R_BASE_IDX 2 8565#define regFMT3_FMT_CLAMP_COMPONENT_G 0x194b 8566#define regFMT3_FMT_CLAMP_COMPONENT_G_BASE_IDX 2 8567#define regFMT3_FMT_CLAMP_COMPONENT_B 0x194c 8568#define regFMT3_FMT_CLAMP_COMPONENT_B_BASE_IDX 2 8569#define regFMT3_FMT_DYNAMIC_EXP_CNTL 0x194d 8570#define regFMT3_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2 8571#define regFMT3_FMT_CONTROL 0x194e 8572#define regFMT3_FMT_CONTROL_BASE_IDX 2 8573#define regFMT3_FMT_BIT_DEPTH_CONTROL 0x194f 8574#define regFMT3_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2 8575#define regFMT3_FMT_DITHER_RAND_R_SEED 0x1950 8576#define regFMT3_FMT_DITHER_RAND_R_SEED_BASE_IDX 2 8577#define regFMT3_FMT_DITHER_RAND_G_SEED 0x1951 8578#define regFMT3_FMT_DITHER_RAND_G_SEED_BASE_IDX 2 8579#define regFMT3_FMT_DITHER_RAND_B_SEED 0x1952 8580#define regFMT3_FMT_DITHER_RAND_B_SEED_BASE_IDX 2 8581#define regFMT3_FMT_CLAMP_CNTL 0x1953 8582#define regFMT3_FMT_CLAMP_CNTL_BASE_IDX 2 8583#define regFMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x1954 8584#define regFMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2 8585#define regFMT3_FMT_MAP420_MEMORY_CONTROL 0x1955 8586#define regFMT3_FMT_MAP420_MEMORY_CONTROL_BASE_IDX 2 8587#define regFMT3_FMT_422_CONTROL 0x1957 8588#define regFMT3_FMT_422_CONTROL_BASE_IDX 2 8589 8590 8591// addressBlock: dce_dc_opp_oppbuf3_dispdec 8592// base address: 0x438 8593#define regOPPBUF3_OPPBUF_CONTROL 0x1992 8594#define regOPPBUF3_OPPBUF_CONTROL_BASE_IDX 2 8595#define regOPPBUF3_OPPBUF_3D_PARAMETERS_0 0x1993 8596#define regOPPBUF3_OPPBUF_3D_PARAMETERS_0_BASE_IDX 2 8597#define regOPPBUF3_OPPBUF_3D_PARAMETERS_1 0x1994 8598#define regOPPBUF3_OPPBUF_3D_PARAMETERS_1_BASE_IDX 2 8599#define regOPPBUF3_OPPBUF_CONTROL1 0x1997 8600#define regOPPBUF3_OPPBUF_CONTROL1_BASE_IDX 2 8601 8602 8603// addressBlock: dce_dc_opp_opp_pipe3_dispdec 8604// base address: 0x438 8605#define regOPP_PIPE3_OPP_PIPE_CONTROL 0x199a 8606#define regOPP_PIPE3_OPP_PIPE_CONTROL_BASE_IDX 2 8607 8608 8609// addressBlock: dce_dc_opp_opp_pipe_crc3_dispdec 8610// base address: 0x438 8611#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL 0x199f 8612#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL_BASE_IDX 2 8613#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_MASK 0x19a0 8614#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_MASK_BASE_IDX 2 8615#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0 0x19a1 8616#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0_BASE_IDX 2 8617#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1 0x19a2 8618#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1_BASE_IDX 2 8619#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT2 0x19a3 8620#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT2_BASE_IDX 2 8621 8622 8623// addressBlock: dce_dc_opp_dscrm0_dispdec 8624// base address: 0x0 8625#define regDSCRM0_DSCRM_DSC_FORWARD_CONFIG 0x1a64 8626#define regDSCRM0_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX 2 8627 8628 8629// addressBlock: dce_dc_opp_dscrm1_dispdec 8630// base address: 0x4 8631#define regDSCRM1_DSCRM_DSC_FORWARD_CONFIG 0x1a65 8632#define regDSCRM1_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX 2 8633 8634 8635// addressBlock: dce_dc_opp_dscrm2_dispdec 8636// base address: 0x8 8637#define regDSCRM2_DSCRM_DSC_FORWARD_CONFIG 0x1a66 8638#define regDSCRM2_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX 2 8639 8640 8641// addressBlock: dce_dc_opp_opp_top_dispdec 8642// base address: 0x0 8643#define regOPP_TOP_CLK_CONTROL 0x1a5e 8644#define regOPP_TOP_CLK_CONTROL_BASE_IDX 2 8645#define regOPP_ABM_CONTROL 0x1a60 8646#define regOPP_ABM_CONTROL_BASE_IDX 2 8647 8648 8649// addressBlock: dce_dc_opp_opp_dcperfmon_dc_perfmon_dispdec 8650// base address: 0x6af8 8651#define regDC_PERFMON16_PERFCOUNTER_CNTL 0x1abe 8652#define regDC_PERFMON16_PERFCOUNTER_CNTL_BASE_IDX 2 8653#define regDC_PERFMON16_PERFCOUNTER_CNTL2 0x1abf 8654#define regDC_PERFMON16_PERFCOUNTER_CNTL2_BASE_IDX 2 8655#define regDC_PERFMON16_PERFCOUNTER_STATE 0x1ac0 8656#define regDC_PERFMON16_PERFCOUNTER_STATE_BASE_IDX 2 8657#define regDC_PERFMON16_PERFMON_CNTL 0x1ac1 8658#define regDC_PERFMON16_PERFMON_CNTL_BASE_IDX 2 8659#define regDC_PERFMON16_PERFMON_CNTL2 0x1ac2 8660#define regDC_PERFMON16_PERFMON_CNTL2_BASE_IDX 2 8661#define regDC_PERFMON16_PERFMON_CVALUE_INT_MISC 0x1ac3 8662#define regDC_PERFMON16_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 8663#define regDC_PERFMON16_PERFMON_CVALUE_LOW 0x1ac4 8664#define regDC_PERFMON16_PERFMON_CVALUE_LOW_BASE_IDX 2 8665#define regDC_PERFMON16_PERFMON_HI 0x1ac5 8666#define regDC_PERFMON16_PERFMON_HI_BASE_IDX 2 8667#define regDC_PERFMON16_PERFMON_LOW 0x1ac6 8668#define regDC_PERFMON16_PERFMON_LOW_BASE_IDX 2 8669 8670 8671// addressBlock: dce_dc_optc_odm0_dispdec 8672// base address: 0x0 8673#define regODM0_OPTC_INPUT_GLOBAL_CONTROL 0x1aca 8674#define regODM0_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX 2 8675#define regODM0_OPTC_DATA_SOURCE_SELECT 0x1acb 8676#define regODM0_OPTC_DATA_SOURCE_SELECT_BASE_IDX 2 8677#define regODM0_OPTC_DATA_FORMAT_CONTROL 0x1acc 8678#define regODM0_OPTC_DATA_FORMAT_CONTROL_BASE_IDX 2 8679#define regODM0_OPTC_BYTES_PER_PIXEL 0x1acd 8680#define regODM0_OPTC_BYTES_PER_PIXEL_BASE_IDX 2 8681#define regODM0_OPTC_WIDTH_CONTROL 0x1ace 8682#define regODM0_OPTC_WIDTH_CONTROL_BASE_IDX 2 8683#define regODM0_OPTC_INPUT_CLOCK_CONTROL 0x1acf 8684#define regODM0_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX 2 8685#define regODM0_OPTC_MEMORY_CONFIG 0x1ad0 8686#define regODM0_OPTC_MEMORY_CONFIG_BASE_IDX 2 8687#define regODM0_OPTC_INPUT_SPARE_REGISTER 0x1ad1 8688#define regODM0_OPTC_INPUT_SPARE_REGISTER_BASE_IDX 2 8689 8690 8691// addressBlock: dce_dc_optc_odm1_dispdec 8692// base address: 0x40 8693#define regODM1_OPTC_INPUT_GLOBAL_CONTROL 0x1ada 8694#define regODM1_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX 2 8695#define regODM1_OPTC_DATA_SOURCE_SELECT 0x1adb 8696#define regODM1_OPTC_DATA_SOURCE_SELECT_BASE_IDX 2 8697#define regODM1_OPTC_DATA_FORMAT_CONTROL 0x1adc 8698#define regODM1_OPTC_DATA_FORMAT_CONTROL_BASE_IDX 2 8699#define regODM1_OPTC_BYTES_PER_PIXEL 0x1add 8700#define regODM1_OPTC_BYTES_PER_PIXEL_BASE_IDX 2 8701#define regODM1_OPTC_WIDTH_CONTROL 0x1ade 8702#define regODM1_OPTC_WIDTH_CONTROL_BASE_IDX 2 8703#define regODM1_OPTC_INPUT_CLOCK_CONTROL 0x1adf 8704#define regODM1_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX 2 8705#define regODM1_OPTC_MEMORY_CONFIG 0x1ae0 8706#define regODM1_OPTC_MEMORY_CONFIG_BASE_IDX 2 8707#define regODM1_OPTC_INPUT_SPARE_REGISTER 0x1ae1 8708#define regODM1_OPTC_INPUT_SPARE_REGISTER_BASE_IDX 2 8709 8710 8711// addressBlock: dce_dc_optc_odm2_dispdec 8712// base address: 0x80 8713#define regODM2_OPTC_INPUT_GLOBAL_CONTROL 0x1aea 8714#define regODM2_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX 2 8715#define regODM2_OPTC_DATA_SOURCE_SELECT 0x1aeb 8716#define regODM2_OPTC_DATA_SOURCE_SELECT_BASE_IDX 2 8717#define regODM2_OPTC_DATA_FORMAT_CONTROL 0x1aec 8718#define regODM2_OPTC_DATA_FORMAT_CONTROL_BASE_IDX 2 8719#define regODM2_OPTC_BYTES_PER_PIXEL 0x1aed 8720#define regODM2_OPTC_BYTES_PER_PIXEL_BASE_IDX 2 8721#define regODM2_OPTC_WIDTH_CONTROL 0x1aee 8722#define regODM2_OPTC_WIDTH_CONTROL_BASE_IDX 2 8723#define regODM2_OPTC_INPUT_CLOCK_CONTROL 0x1aef 8724#define regODM2_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX 2 8725#define regODM2_OPTC_MEMORY_CONFIG 0x1af0 8726#define regODM2_OPTC_MEMORY_CONFIG_BASE_IDX 2 8727#define regODM2_OPTC_INPUT_SPARE_REGISTER 0x1af1 8728#define regODM2_OPTC_INPUT_SPARE_REGISTER_BASE_IDX 2 8729 8730 8731// addressBlock: dce_dc_optc_odm3_dispdec 8732// base address: 0xc0 8733#define regODM3_OPTC_INPUT_GLOBAL_CONTROL 0x1afa 8734#define regODM3_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX 2 8735#define regODM3_OPTC_DATA_SOURCE_SELECT 0x1afb 8736#define regODM3_OPTC_DATA_SOURCE_SELECT_BASE_IDX 2 8737#define regODM3_OPTC_DATA_FORMAT_CONTROL 0x1afc 8738#define regODM3_OPTC_DATA_FORMAT_CONTROL_BASE_IDX 2 8739#define regODM3_OPTC_BYTES_PER_PIXEL 0x1afd 8740#define regODM3_OPTC_BYTES_PER_PIXEL_BASE_IDX 2 8741#define regODM3_OPTC_WIDTH_CONTROL 0x1afe 8742#define regODM3_OPTC_WIDTH_CONTROL_BASE_IDX 2 8743#define regODM3_OPTC_INPUT_CLOCK_CONTROL 0x1aff 8744#define regODM3_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX 2 8745#define regODM3_OPTC_MEMORY_CONFIG 0x1b00 8746#define regODM3_OPTC_MEMORY_CONFIG_BASE_IDX 2 8747#define regODM3_OPTC_INPUT_SPARE_REGISTER 0x1b01 8748#define regODM3_OPTC_INPUT_SPARE_REGISTER_BASE_IDX 2 8749 8750 8751// addressBlock: dce_dc_optc_otg0_dispdec 8752// base address: 0x0 8753#define regOTG0_OTG_H_TOTAL 0x1b2a 8754#define regOTG0_OTG_H_TOTAL_BASE_IDX 2 8755#define regOTG0_OTG_H_BLANK_START_END 0x1b2b 8756#define regOTG0_OTG_H_BLANK_START_END_BASE_IDX 2 8757#define regOTG0_OTG_H_SYNC_A 0x1b2c 8758#define regOTG0_OTG_H_SYNC_A_BASE_IDX 2 8759#define regOTG0_OTG_H_SYNC_A_CNTL 0x1b2d 8760#define regOTG0_OTG_H_SYNC_A_CNTL_BASE_IDX 2 8761#define regOTG0_OTG_H_TIMING_CNTL 0x1b2e 8762#define regOTG0_OTG_H_TIMING_CNTL_BASE_IDX 2 8763#define regOTG0_OTG_V_TOTAL 0x1b2f 8764#define regOTG0_OTG_V_TOTAL_BASE_IDX 2 8765#define regOTG0_OTG_V_TOTAL_MIN 0x1b30 8766#define regOTG0_OTG_V_TOTAL_MIN_BASE_IDX 2 8767#define regOTG0_OTG_V_TOTAL_MAX 0x1b31 8768#define regOTG0_OTG_V_TOTAL_MAX_BASE_IDX 2 8769#define regOTG0_OTG_V_TOTAL_MID 0x1b32 8770#define regOTG0_OTG_V_TOTAL_MID_BASE_IDX 2 8771#define regOTG0_OTG_V_TOTAL_CONTROL 0x1b33 8772#define regOTG0_OTG_V_TOTAL_CONTROL_BASE_IDX 2 8773#define regOTG0_OTG_V_TOTAL_INT_STATUS 0x1b34 8774#define regOTG0_OTG_V_TOTAL_INT_STATUS_BASE_IDX 2 8775#define regOTG0_OTG_VSYNC_NOM_INT_STATUS 0x1b35 8776#define regOTG0_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX 2 8777#define regOTG0_OTG_V_BLANK_START_END 0x1b36 8778#define regOTG0_OTG_V_BLANK_START_END_BASE_IDX 2 8779#define regOTG0_OTG_V_SYNC_A 0x1b37 8780#define regOTG0_OTG_V_SYNC_A_BASE_IDX 2 8781#define regOTG0_OTG_V_SYNC_A_CNTL 0x1b38 8782#define regOTG0_OTG_V_SYNC_A_CNTL_BASE_IDX 2 8783#define regOTG0_OTG_TRIGA_CNTL 0x1b39 8784#define regOTG0_OTG_TRIGA_CNTL_BASE_IDX 2 8785#define regOTG0_OTG_TRIGA_MANUAL_TRIG 0x1b3a 8786#define regOTG0_OTG_TRIGA_MANUAL_TRIG_BASE_IDX 2 8787#define regOTG0_OTG_TRIGB_CNTL 0x1b3b 8788#define regOTG0_OTG_TRIGB_CNTL_BASE_IDX 2 8789#define regOTG0_OTG_TRIGB_MANUAL_TRIG 0x1b3c 8790#define regOTG0_OTG_TRIGB_MANUAL_TRIG_BASE_IDX 2 8791#define regOTG0_OTG_FORCE_COUNT_NOW_CNTL 0x1b3d 8792#define regOTG0_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX 2 8793#define regOTG0_OTG_FLOW_CONTROL 0x1b3e 8794#define regOTG0_OTG_FLOW_CONTROL_BASE_IDX 2 8795#define regOTG0_OTG_STEREO_FORCE_NEXT_EYE 0x1b3f 8796#define regOTG0_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX 2 8797#define regOTG0_OTG_CONTROL 0x1b41 8798#define regOTG0_OTG_CONTROL_BASE_IDX 2 8799#define regOTG0_OTG_INTERLACE_CONTROL 0x1b44 8800#define regOTG0_OTG_INTERLACE_CONTROL_BASE_IDX 2 8801#define regOTG0_OTG_INTERLACE_STATUS 0x1b45 8802#define regOTG0_OTG_INTERLACE_STATUS_BASE_IDX 2 8803#define regOTG0_OTG_PIXEL_DATA_READBACK0 0x1b47 8804#define regOTG0_OTG_PIXEL_DATA_READBACK0_BASE_IDX 2 8805#define regOTG0_OTG_PIXEL_DATA_READBACK1 0x1b48 8806#define regOTG0_OTG_PIXEL_DATA_READBACK1_BASE_IDX 2 8807#define regOTG0_OTG_STATUS 0x1b49 8808#define regOTG0_OTG_STATUS_BASE_IDX 2 8809#define regOTG0_OTG_STATUS_POSITION 0x1b4a 8810#define regOTG0_OTG_STATUS_POSITION_BASE_IDX 2 8811#define regOTG0_OTG_NOM_VERT_POSITION 0x1b4b 8812#define regOTG0_OTG_NOM_VERT_POSITION_BASE_IDX 2 8813#define regOTG0_OTG_STATUS_FRAME_COUNT 0x1b4c 8814#define regOTG0_OTG_STATUS_FRAME_COUNT_BASE_IDX 2 8815#define regOTG0_OTG_STATUS_VF_COUNT 0x1b4d 8816#define regOTG0_OTG_STATUS_VF_COUNT_BASE_IDX 2 8817#define regOTG0_OTG_STATUS_HV_COUNT 0x1b4e 8818#define regOTG0_OTG_STATUS_HV_COUNT_BASE_IDX 2 8819#define regOTG0_OTG_COUNT_CONTROL 0x1b4f 8820#define regOTG0_OTG_COUNT_CONTROL_BASE_IDX 2 8821#define regOTG0_OTG_COUNT_RESET 0x1b50 8822#define regOTG0_OTG_COUNT_RESET_BASE_IDX 2 8823#define regOTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1b51 8824#define regOTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2 8825#define regOTG0_OTG_VERT_SYNC_CONTROL 0x1b52 8826#define regOTG0_OTG_VERT_SYNC_CONTROL_BASE_IDX 2 8827#define regOTG0_OTG_STEREO_STATUS 0x1b53 8828#define regOTG0_OTG_STEREO_STATUS_BASE_IDX 2 8829#define regOTG0_OTG_STEREO_CONTROL 0x1b54 8830#define regOTG0_OTG_STEREO_CONTROL_BASE_IDX 2 8831#define regOTG0_OTG_SNAPSHOT_STATUS 0x1b55 8832#define regOTG0_OTG_SNAPSHOT_STATUS_BASE_IDX 2 8833#define regOTG0_OTG_SNAPSHOT_CONTROL 0x1b56 8834#define regOTG0_OTG_SNAPSHOT_CONTROL_BASE_IDX 2 8835#define regOTG0_OTG_SNAPSHOT_POSITION 0x1b57 8836#define regOTG0_OTG_SNAPSHOT_POSITION_BASE_IDX 2 8837#define regOTG0_OTG_SNAPSHOT_FRAME 0x1b58 8838#define regOTG0_OTG_SNAPSHOT_FRAME_BASE_IDX 2 8839#define regOTG0_OTG_INTERRUPT_CONTROL 0x1b59 8840#define regOTG0_OTG_INTERRUPT_CONTROL_BASE_IDX 2 8841#define regOTG0_OTG_UPDATE_LOCK 0x1b5a 8842#define regOTG0_OTG_UPDATE_LOCK_BASE_IDX 2 8843#define regOTG0_OTG_DOUBLE_BUFFER_CONTROL 0x1b5b 8844#define regOTG0_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 8845#define regOTG0_OTG_MASTER_EN 0x1b5c 8846#define regOTG0_OTG_MASTER_EN_BASE_IDX 2 8847#define regOTG0_OTG_VERTICAL_INTERRUPT0_POSITION 0x1b62 8848#define regOTG0_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2 8849#define regOTG0_OTG_VERTICAL_INTERRUPT0_CONTROL 0x1b63 8850#define regOTG0_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2 8851#define regOTG0_OTG_VERTICAL_INTERRUPT1_POSITION 0x1b64 8852#define regOTG0_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2 8853#define regOTG0_OTG_VERTICAL_INTERRUPT1_CONTROL 0x1b65 8854#define regOTG0_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2 8855#define regOTG0_OTG_VERTICAL_INTERRUPT2_POSITION 0x1b66 8856#define regOTG0_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2 8857#define regOTG0_OTG_VERTICAL_INTERRUPT2_CONTROL 0x1b67 8858#define regOTG0_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2 8859#define regOTG0_OTG_CRC_CNTL 0x1b68 8860#define regOTG0_OTG_CRC_CNTL_BASE_IDX 2 8861#define regOTG0_OTG_CRC_CNTL2 0x1b69 8862#define regOTG0_OTG_CRC_CNTL2_BASE_IDX 2 8863#define regOTG0_OTG_CRC0_WINDOWA_X_CONTROL 0x1b6a 8864#define regOTG0_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2 8865#define regOTG0_OTG_CRC0_WINDOWA_Y_CONTROL 0x1b6b 8866#define regOTG0_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2 8867#define regOTG0_OTG_CRC0_WINDOWB_X_CONTROL 0x1b6c 8868#define regOTG0_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2 8869#define regOTG0_OTG_CRC0_WINDOWB_Y_CONTROL 0x1b6d 8870#define regOTG0_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2 8871#define regOTG0_OTG_CRC0_DATA_RG 0x1b6e 8872#define regOTG0_OTG_CRC0_DATA_RG_BASE_IDX 2 8873#define regOTG0_OTG_CRC0_DATA_B 0x1b6f 8874#define regOTG0_OTG_CRC0_DATA_B_BASE_IDX 2 8875#define regOTG0_OTG_CRC1_WINDOWA_X_CONTROL 0x1b70 8876#define regOTG0_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2 8877#define regOTG0_OTG_CRC1_WINDOWA_Y_CONTROL 0x1b71 8878#define regOTG0_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2 8879#define regOTG0_OTG_CRC1_WINDOWB_X_CONTROL 0x1b72 8880#define regOTG0_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2 8881#define regOTG0_OTG_CRC1_WINDOWB_Y_CONTROL 0x1b73 8882#define regOTG0_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2 8883#define regOTG0_OTG_CRC1_DATA_RG 0x1b74 8884#define regOTG0_OTG_CRC1_DATA_RG_BASE_IDX 2 8885#define regOTG0_OTG_CRC1_DATA_B 0x1b75 8886#define regOTG0_OTG_CRC1_DATA_B_BASE_IDX 2 8887#define regOTG0_OTG_CRC2_DATA_RG 0x1b76 8888#define regOTG0_OTG_CRC2_DATA_RG_BASE_IDX 2 8889#define regOTG0_OTG_CRC2_DATA_B 0x1b77 8890#define regOTG0_OTG_CRC2_DATA_B_BASE_IDX 2 8891#define regOTG0_OTG_CRC3_DATA_RG 0x1b78 8892#define regOTG0_OTG_CRC3_DATA_RG_BASE_IDX 2 8893#define regOTG0_OTG_CRC3_DATA_B 0x1b79 8894#define regOTG0_OTG_CRC3_DATA_B_BASE_IDX 2 8895#define regOTG0_OTG_CRC_SIG_RED_GREEN_MASK 0x1b7a 8896#define regOTG0_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2 8897#define regOTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK 0x1b7b 8898#define regOTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2 8899#define regOTG0_OTG_STATIC_SCREEN_CONTROL 0x1b82 8900#define regOTG0_OTG_STATIC_SCREEN_CONTROL_BASE_IDX 2 8901#define regOTG0_OTG_3D_STRUCTURE_CONTROL 0x1b83 8902#define regOTG0_OTG_3D_STRUCTURE_CONTROL_BASE_IDX 2 8903#define regOTG0_OTG_GSL_VSYNC_GAP 0x1b84 8904#define regOTG0_OTG_GSL_VSYNC_GAP_BASE_IDX 2 8905#define regOTG0_OTG_MASTER_UPDATE_MODE 0x1b85 8906#define regOTG0_OTG_MASTER_UPDATE_MODE_BASE_IDX 2 8907#define regOTG0_OTG_CLOCK_CONTROL 0x1b86 8908#define regOTG0_OTG_CLOCK_CONTROL_BASE_IDX 2 8909#define regOTG0_OTG_VSTARTUP_PARAM 0x1b87 8910#define regOTG0_OTG_VSTARTUP_PARAM_BASE_IDX 2 8911#define regOTG0_OTG_VUPDATE_PARAM 0x1b88 8912#define regOTG0_OTG_VUPDATE_PARAM_BASE_IDX 2 8913#define regOTG0_OTG_VREADY_PARAM 0x1b89 8914#define regOTG0_OTG_VREADY_PARAM_BASE_IDX 2 8915#define regOTG0_OTG_GLOBAL_SYNC_STATUS 0x1b8a 8916#define regOTG0_OTG_GLOBAL_SYNC_STATUS_BASE_IDX 2 8917#define regOTG0_OTG_MASTER_UPDATE_LOCK 0x1b8b 8918#define regOTG0_OTG_MASTER_UPDATE_LOCK_BASE_IDX 2 8919#define regOTG0_OTG_GSL_CONTROL 0x1b8c 8920#define regOTG0_OTG_GSL_CONTROL_BASE_IDX 2 8921#define regOTG0_OTG_GSL_WINDOW_X 0x1b8d 8922#define regOTG0_OTG_GSL_WINDOW_X_BASE_IDX 2 8923#define regOTG0_OTG_GSL_WINDOW_Y 0x1b8e 8924#define regOTG0_OTG_GSL_WINDOW_Y_BASE_IDX 2 8925#define regOTG0_OTG_VUPDATE_KEEPOUT 0x1b8f 8926#define regOTG0_OTG_VUPDATE_KEEPOUT_BASE_IDX 2 8927#define regOTG0_OTG_GLOBAL_CONTROL0 0x1b90 8928#define regOTG0_OTG_GLOBAL_CONTROL0_BASE_IDX 2 8929#define regOTG0_OTG_GLOBAL_CONTROL1 0x1b91 8930#define regOTG0_OTG_GLOBAL_CONTROL1_BASE_IDX 2 8931#define regOTG0_OTG_GLOBAL_CONTROL2 0x1b92 8932#define regOTG0_OTG_GLOBAL_CONTROL2_BASE_IDX 2 8933#define regOTG0_OTG_GLOBAL_CONTROL3 0x1b93 8934#define regOTG0_OTG_GLOBAL_CONTROL3_BASE_IDX 2 8935#define regOTG0_OTG_GLOBAL_CONTROL4 0x1b94 8936#define regOTG0_OTG_GLOBAL_CONTROL4_BASE_IDX 2 8937#define regOTG0_OTG_TRIG_MANUAL_CONTROL 0x1b95 8938#define regOTG0_OTG_TRIG_MANUAL_CONTROL_BASE_IDX 2 8939#define regOTG0_OTG_MANUAL_FLOW_CONTROL 0x1b96 8940#define regOTG0_OTG_MANUAL_FLOW_CONTROL_BASE_IDX 2 8941#define regOTG0_OTG_DRR_TIMING_INT_STATUS 0x1b97 8942#define regOTG0_OTG_DRR_TIMING_INT_STATUS_BASE_IDX 2 8943#define regOTG0_OTG_DRR_V_TOTAL_REACH_RANGE 0x1b98 8944#define regOTG0_OTG_DRR_V_TOTAL_REACH_RANGE_BASE_IDX 2 8945#define regOTG0_OTG_DRR_V_TOTAL_CHANGE 0x1b99 8946#define regOTG0_OTG_DRR_V_TOTAL_CHANGE_BASE_IDX 2 8947#define regOTG0_OTG_DRR_TRIGGER_WINDOW 0x1b9a 8948#define regOTG0_OTG_DRR_TRIGGER_WINDOW_BASE_IDX 2 8949#define regOTG0_OTG_DRR_CONTROL 0x1b9b 8950#define regOTG0_OTG_DRR_CONTROL_BASE_IDX 2 8951#define regOTG0_OTG_M_CONST_DTO0 0x1b9c 8952#define regOTG0_OTG_M_CONST_DTO0_BASE_IDX 2 8953#define regOTG0_OTG_M_CONST_DTO1 0x1b9d 8954#define regOTG0_OTG_M_CONST_DTO1_BASE_IDX 2 8955#define regOTG0_OTG_REQUEST_CONTROL 0x1b9e 8956#define regOTG0_OTG_REQUEST_CONTROL_BASE_IDX 2 8957#define regOTG0_OTG_DSC_START_POSITION 0x1b9f 8958#define regOTG0_OTG_DSC_START_POSITION_BASE_IDX 2 8959#define regOTG0_OTG_PIPE_UPDATE_STATUS 0x1ba0 8960#define regOTG0_OTG_PIPE_UPDATE_STATUS_BASE_IDX 2 8961#define regOTG0_OTG_SPARE_REGISTER 0x1ba2 8962#define regOTG0_OTG_SPARE_REGISTER_BASE_IDX 2 8963 8964 8965// addressBlock: dce_dc_optc_otg1_dispdec 8966// base address: 0x200 8967#define regOTG1_OTG_H_TOTAL 0x1baa 8968#define regOTG1_OTG_H_TOTAL_BASE_IDX 2 8969#define regOTG1_OTG_H_BLANK_START_END 0x1bab 8970#define regOTG1_OTG_H_BLANK_START_END_BASE_IDX 2 8971#define regOTG1_OTG_H_SYNC_A 0x1bac 8972#define regOTG1_OTG_H_SYNC_A_BASE_IDX 2 8973#define regOTG1_OTG_H_SYNC_A_CNTL 0x1bad 8974#define regOTG1_OTG_H_SYNC_A_CNTL_BASE_IDX 2 8975#define regOTG1_OTG_H_TIMING_CNTL 0x1bae 8976#define regOTG1_OTG_H_TIMING_CNTL_BASE_IDX 2 8977#define regOTG1_OTG_V_TOTAL 0x1baf 8978#define regOTG1_OTG_V_TOTAL_BASE_IDX 2 8979#define regOTG1_OTG_V_TOTAL_MIN 0x1bb0 8980#define regOTG1_OTG_V_TOTAL_MIN_BASE_IDX 2 8981#define regOTG1_OTG_V_TOTAL_MAX 0x1bb1 8982#define regOTG1_OTG_V_TOTAL_MAX_BASE_IDX 2 8983#define regOTG1_OTG_V_TOTAL_MID 0x1bb2 8984#define regOTG1_OTG_V_TOTAL_MID_BASE_IDX 2 8985#define regOTG1_OTG_V_TOTAL_CONTROL 0x1bb3 8986#define regOTG1_OTG_V_TOTAL_CONTROL_BASE_IDX 2 8987#define regOTG1_OTG_V_TOTAL_INT_STATUS 0x1bb4 8988#define regOTG1_OTG_V_TOTAL_INT_STATUS_BASE_IDX 2 8989#define regOTG1_OTG_VSYNC_NOM_INT_STATUS 0x1bb5 8990#define regOTG1_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX 2 8991#define regOTG1_OTG_V_BLANK_START_END 0x1bb6 8992#define regOTG1_OTG_V_BLANK_START_END_BASE_IDX 2 8993#define regOTG1_OTG_V_SYNC_A 0x1bb7 8994#define regOTG1_OTG_V_SYNC_A_BASE_IDX 2 8995#define regOTG1_OTG_V_SYNC_A_CNTL 0x1bb8 8996#define regOTG1_OTG_V_SYNC_A_CNTL_BASE_IDX 2 8997#define regOTG1_OTG_TRIGA_CNTL 0x1bb9 8998#define regOTG1_OTG_TRIGA_CNTL_BASE_IDX 2 8999#define regOTG1_OTG_TRIGA_MANUAL_TRIG 0x1bba 9000#define regOTG1_OTG_TRIGA_MANUAL_TRIG_BASE_IDX 2 9001#define regOTG1_OTG_TRIGB_CNTL 0x1bbb 9002#define regOTG1_OTG_TRIGB_CNTL_BASE_IDX 2 9003#define regOTG1_OTG_TRIGB_MANUAL_TRIG 0x1bbc 9004#define regOTG1_OTG_TRIGB_MANUAL_TRIG_BASE_IDX 2 9005#define regOTG1_OTG_FORCE_COUNT_NOW_CNTL 0x1bbd 9006#define regOTG1_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX 2 9007#define regOTG1_OTG_FLOW_CONTROL 0x1bbe 9008#define regOTG1_OTG_FLOW_CONTROL_BASE_IDX 2 9009#define regOTG1_OTG_STEREO_FORCE_NEXT_EYE 0x1bbf 9010#define regOTG1_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX 2 9011#define regOTG1_OTG_CONTROL 0x1bc1 9012#define regOTG1_OTG_CONTROL_BASE_IDX 2 9013#define regOTG1_OTG_INTERLACE_CONTROL 0x1bc4 9014#define regOTG1_OTG_INTERLACE_CONTROL_BASE_IDX 2 9015#define regOTG1_OTG_INTERLACE_STATUS 0x1bc5 9016#define regOTG1_OTG_INTERLACE_STATUS_BASE_IDX 2 9017#define regOTG1_OTG_PIXEL_DATA_READBACK0 0x1bc7 9018#define regOTG1_OTG_PIXEL_DATA_READBACK0_BASE_IDX 2 9019#define regOTG1_OTG_PIXEL_DATA_READBACK1 0x1bc8 9020#define regOTG1_OTG_PIXEL_DATA_READBACK1_BASE_IDX 2 9021#define regOTG1_OTG_STATUS 0x1bc9 9022#define regOTG1_OTG_STATUS_BASE_IDX 2 9023#define regOTG1_OTG_STATUS_POSITION 0x1bca 9024#define regOTG1_OTG_STATUS_POSITION_BASE_IDX 2 9025#define regOTG1_OTG_NOM_VERT_POSITION 0x1bcb 9026#define regOTG1_OTG_NOM_VERT_POSITION_BASE_IDX 2 9027#define regOTG1_OTG_STATUS_FRAME_COUNT 0x1bcc 9028#define regOTG1_OTG_STATUS_FRAME_COUNT_BASE_IDX 2 9029#define regOTG1_OTG_STATUS_VF_COUNT 0x1bcd 9030#define regOTG1_OTG_STATUS_VF_COUNT_BASE_IDX 2 9031#define regOTG1_OTG_STATUS_HV_COUNT 0x1bce 9032#define regOTG1_OTG_STATUS_HV_COUNT_BASE_IDX 2 9033#define regOTG1_OTG_COUNT_CONTROL 0x1bcf 9034#define regOTG1_OTG_COUNT_CONTROL_BASE_IDX 2 9035#define regOTG1_OTG_COUNT_RESET 0x1bd0 9036#define regOTG1_OTG_COUNT_RESET_BASE_IDX 2 9037#define regOTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1bd1 9038#define regOTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2 9039#define regOTG1_OTG_VERT_SYNC_CONTROL 0x1bd2 9040#define regOTG1_OTG_VERT_SYNC_CONTROL_BASE_IDX 2 9041#define regOTG1_OTG_STEREO_STATUS 0x1bd3 9042#define regOTG1_OTG_STEREO_STATUS_BASE_IDX 2 9043#define regOTG1_OTG_STEREO_CONTROL 0x1bd4 9044#define regOTG1_OTG_STEREO_CONTROL_BASE_IDX 2 9045#define regOTG1_OTG_SNAPSHOT_STATUS 0x1bd5 9046#define regOTG1_OTG_SNAPSHOT_STATUS_BASE_IDX 2 9047#define regOTG1_OTG_SNAPSHOT_CONTROL 0x1bd6 9048#define regOTG1_OTG_SNAPSHOT_CONTROL_BASE_IDX 2 9049#define regOTG1_OTG_SNAPSHOT_POSITION 0x1bd7 9050#define regOTG1_OTG_SNAPSHOT_POSITION_BASE_IDX 2 9051#define regOTG1_OTG_SNAPSHOT_FRAME 0x1bd8 9052#define regOTG1_OTG_SNAPSHOT_FRAME_BASE_IDX 2 9053#define regOTG1_OTG_INTERRUPT_CONTROL 0x1bd9 9054#define regOTG1_OTG_INTERRUPT_CONTROL_BASE_IDX 2 9055#define regOTG1_OTG_UPDATE_LOCK 0x1bda 9056#define regOTG1_OTG_UPDATE_LOCK_BASE_IDX 2 9057#define regOTG1_OTG_DOUBLE_BUFFER_CONTROL 0x1bdb 9058#define regOTG1_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 9059#define regOTG1_OTG_MASTER_EN 0x1bdc 9060#define regOTG1_OTG_MASTER_EN_BASE_IDX 2 9061#define regOTG1_OTG_VERTICAL_INTERRUPT0_POSITION 0x1be2 9062#define regOTG1_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2 9063#define regOTG1_OTG_VERTICAL_INTERRUPT0_CONTROL 0x1be3 9064#define regOTG1_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2 9065#define regOTG1_OTG_VERTICAL_INTERRUPT1_POSITION 0x1be4 9066#define regOTG1_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2 9067#define regOTG1_OTG_VERTICAL_INTERRUPT1_CONTROL 0x1be5 9068#define regOTG1_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2 9069#define regOTG1_OTG_VERTICAL_INTERRUPT2_POSITION 0x1be6 9070#define regOTG1_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2 9071#define regOTG1_OTG_VERTICAL_INTERRUPT2_CONTROL 0x1be7 9072#define regOTG1_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2 9073#define regOTG1_OTG_CRC_CNTL 0x1be8 9074#define regOTG1_OTG_CRC_CNTL_BASE_IDX 2 9075#define regOTG1_OTG_CRC_CNTL2 0x1be9 9076#define regOTG1_OTG_CRC_CNTL2_BASE_IDX 2 9077#define regOTG1_OTG_CRC0_WINDOWA_X_CONTROL 0x1bea 9078#define regOTG1_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2 9079#define regOTG1_OTG_CRC0_WINDOWA_Y_CONTROL 0x1beb 9080#define regOTG1_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2 9081#define regOTG1_OTG_CRC0_WINDOWB_X_CONTROL 0x1bec 9082#define regOTG1_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2 9083#define regOTG1_OTG_CRC0_WINDOWB_Y_CONTROL 0x1bed 9084#define regOTG1_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2 9085#define regOTG1_OTG_CRC0_DATA_RG 0x1bee 9086#define regOTG1_OTG_CRC0_DATA_RG_BASE_IDX 2 9087#define regOTG1_OTG_CRC0_DATA_B 0x1bef 9088#define regOTG1_OTG_CRC0_DATA_B_BASE_IDX 2 9089#define regOTG1_OTG_CRC1_WINDOWA_X_CONTROL 0x1bf0 9090#define regOTG1_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2 9091#define regOTG1_OTG_CRC1_WINDOWA_Y_CONTROL 0x1bf1 9092#define regOTG1_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2 9093#define regOTG1_OTG_CRC1_WINDOWB_X_CONTROL 0x1bf2 9094#define regOTG1_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2 9095#define regOTG1_OTG_CRC1_WINDOWB_Y_CONTROL 0x1bf3 9096#define regOTG1_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2 9097#define regOTG1_OTG_CRC1_DATA_RG 0x1bf4 9098#define regOTG1_OTG_CRC1_DATA_RG_BASE_IDX 2 9099#define regOTG1_OTG_CRC1_DATA_B 0x1bf5 9100#define regOTG1_OTG_CRC1_DATA_B_BASE_IDX 2 9101#define regOTG1_OTG_CRC2_DATA_RG 0x1bf6 9102#define regOTG1_OTG_CRC2_DATA_RG_BASE_IDX 2 9103#define regOTG1_OTG_CRC2_DATA_B 0x1bf7 9104#define regOTG1_OTG_CRC2_DATA_B_BASE_IDX 2 9105#define regOTG1_OTG_CRC3_DATA_RG 0x1bf8 9106#define regOTG1_OTG_CRC3_DATA_RG_BASE_IDX 2 9107#define regOTG1_OTG_CRC3_DATA_B 0x1bf9 9108#define regOTG1_OTG_CRC3_DATA_B_BASE_IDX 2 9109#define regOTG1_OTG_CRC_SIG_RED_GREEN_MASK 0x1bfa 9110#define regOTG1_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2 9111#define regOTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK 0x1bfb 9112#define regOTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2 9113#define regOTG1_OTG_STATIC_SCREEN_CONTROL 0x1c02 9114#define regOTG1_OTG_STATIC_SCREEN_CONTROL_BASE_IDX 2 9115#define regOTG1_OTG_3D_STRUCTURE_CONTROL 0x1c03 9116#define regOTG1_OTG_3D_STRUCTURE_CONTROL_BASE_IDX 2 9117#define regOTG1_OTG_GSL_VSYNC_GAP 0x1c04 9118#define regOTG1_OTG_GSL_VSYNC_GAP_BASE_IDX 2 9119#define regOTG1_OTG_MASTER_UPDATE_MODE 0x1c05 9120#define regOTG1_OTG_MASTER_UPDATE_MODE_BASE_IDX 2 9121#define regOTG1_OTG_CLOCK_CONTROL 0x1c06 9122#define regOTG1_OTG_CLOCK_CONTROL_BASE_IDX 2 9123#define regOTG1_OTG_VSTARTUP_PARAM 0x1c07 9124#define regOTG1_OTG_VSTARTUP_PARAM_BASE_IDX 2 9125#define regOTG1_OTG_VUPDATE_PARAM 0x1c08 9126#define regOTG1_OTG_VUPDATE_PARAM_BASE_IDX 2 9127#define regOTG1_OTG_VREADY_PARAM 0x1c09 9128#define regOTG1_OTG_VREADY_PARAM_BASE_IDX 2 9129#define regOTG1_OTG_GLOBAL_SYNC_STATUS 0x1c0a 9130#define regOTG1_OTG_GLOBAL_SYNC_STATUS_BASE_IDX 2 9131#define regOTG1_OTG_MASTER_UPDATE_LOCK 0x1c0b 9132#define regOTG1_OTG_MASTER_UPDATE_LOCK_BASE_IDX 2 9133#define regOTG1_OTG_GSL_CONTROL 0x1c0c 9134#define regOTG1_OTG_GSL_CONTROL_BASE_IDX 2 9135#define regOTG1_OTG_GSL_WINDOW_X 0x1c0d 9136#define regOTG1_OTG_GSL_WINDOW_X_BASE_IDX 2 9137#define regOTG1_OTG_GSL_WINDOW_Y 0x1c0e 9138#define regOTG1_OTG_GSL_WINDOW_Y_BASE_IDX 2 9139#define regOTG1_OTG_VUPDATE_KEEPOUT 0x1c0f 9140#define regOTG1_OTG_VUPDATE_KEEPOUT_BASE_IDX 2 9141#define regOTG1_OTG_GLOBAL_CONTROL0 0x1c10 9142#define regOTG1_OTG_GLOBAL_CONTROL0_BASE_IDX 2 9143#define regOTG1_OTG_GLOBAL_CONTROL1 0x1c11 9144#define regOTG1_OTG_GLOBAL_CONTROL1_BASE_IDX 2 9145#define regOTG1_OTG_GLOBAL_CONTROL2 0x1c12 9146#define regOTG1_OTG_GLOBAL_CONTROL2_BASE_IDX 2 9147#define regOTG1_OTG_GLOBAL_CONTROL3 0x1c13 9148#define regOTG1_OTG_GLOBAL_CONTROL3_BASE_IDX 2 9149#define regOTG1_OTG_GLOBAL_CONTROL4 0x1c14 9150#define regOTG1_OTG_GLOBAL_CONTROL4_BASE_IDX 2 9151#define regOTG1_OTG_TRIG_MANUAL_CONTROL 0x1c15 9152#define regOTG1_OTG_TRIG_MANUAL_CONTROL_BASE_IDX 2 9153#define regOTG1_OTG_MANUAL_FLOW_CONTROL 0x1c16 9154#define regOTG1_OTG_MANUAL_FLOW_CONTROL_BASE_IDX 2 9155#define regOTG1_OTG_DRR_TIMING_INT_STATUS 0x1c17 9156#define regOTG1_OTG_DRR_TIMING_INT_STATUS_BASE_IDX 2 9157#define regOTG1_OTG_DRR_V_TOTAL_REACH_RANGE 0x1c18 9158#define regOTG1_OTG_DRR_V_TOTAL_REACH_RANGE_BASE_IDX 2 9159#define regOTG1_OTG_DRR_V_TOTAL_CHANGE 0x1c19 9160#define regOTG1_OTG_DRR_V_TOTAL_CHANGE_BASE_IDX 2 9161#define regOTG1_OTG_DRR_TRIGGER_WINDOW 0x1c1a 9162#define regOTG1_OTG_DRR_TRIGGER_WINDOW_BASE_IDX 2 9163#define regOTG1_OTG_DRR_CONTROL 0x1c1b 9164#define regOTG1_OTG_DRR_CONTROL_BASE_IDX 2 9165#define regOTG1_OTG_M_CONST_DTO0 0x1c1c 9166#define regOTG1_OTG_M_CONST_DTO0_BASE_IDX 2 9167#define regOTG1_OTG_M_CONST_DTO1 0x1c1d 9168#define regOTG1_OTG_M_CONST_DTO1_BASE_IDX 2 9169#define regOTG1_OTG_REQUEST_CONTROL 0x1c1e 9170#define regOTG1_OTG_REQUEST_CONTROL_BASE_IDX 2 9171#define regOTG1_OTG_DSC_START_POSITION 0x1c1f 9172#define regOTG1_OTG_DSC_START_POSITION_BASE_IDX 2 9173#define regOTG1_OTG_PIPE_UPDATE_STATUS 0x1c20 9174#define regOTG1_OTG_PIPE_UPDATE_STATUS_BASE_IDX 2 9175#define regOTG1_OTG_SPARE_REGISTER 0x1c22 9176#define regOTG1_OTG_SPARE_REGISTER_BASE_IDX 2 9177 9178 9179// addressBlock: dce_dc_optc_otg2_dispdec 9180// base address: 0x400 9181#define regOTG2_OTG_H_TOTAL 0x1c2a 9182#define regOTG2_OTG_H_TOTAL_BASE_IDX 2 9183#define regOTG2_OTG_H_BLANK_START_END 0x1c2b 9184#define regOTG2_OTG_H_BLANK_START_END_BASE_IDX 2 9185#define regOTG2_OTG_H_SYNC_A 0x1c2c 9186#define regOTG2_OTG_H_SYNC_A_BASE_IDX 2 9187#define regOTG2_OTG_H_SYNC_A_CNTL 0x1c2d 9188#define regOTG2_OTG_H_SYNC_A_CNTL_BASE_IDX 2 9189#define regOTG2_OTG_H_TIMING_CNTL 0x1c2e 9190#define regOTG2_OTG_H_TIMING_CNTL_BASE_IDX 2 9191#define regOTG2_OTG_V_TOTAL 0x1c2f 9192#define regOTG2_OTG_V_TOTAL_BASE_IDX 2 9193#define regOTG2_OTG_V_TOTAL_MIN 0x1c30 9194#define regOTG2_OTG_V_TOTAL_MIN_BASE_IDX 2 9195#define regOTG2_OTG_V_TOTAL_MAX 0x1c31 9196#define regOTG2_OTG_V_TOTAL_MAX_BASE_IDX 2 9197#define regOTG2_OTG_V_TOTAL_MID 0x1c32 9198#define regOTG2_OTG_V_TOTAL_MID_BASE_IDX 2 9199#define regOTG2_OTG_V_TOTAL_CONTROL 0x1c33 9200#define regOTG2_OTG_V_TOTAL_CONTROL_BASE_IDX 2 9201#define regOTG2_OTG_V_TOTAL_INT_STATUS 0x1c34 9202#define regOTG2_OTG_V_TOTAL_INT_STATUS_BASE_IDX 2 9203#define regOTG2_OTG_VSYNC_NOM_INT_STATUS 0x1c35 9204#define regOTG2_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX 2 9205#define regOTG2_OTG_V_BLANK_START_END 0x1c36 9206#define regOTG2_OTG_V_BLANK_START_END_BASE_IDX 2 9207#define regOTG2_OTG_V_SYNC_A 0x1c37 9208#define regOTG2_OTG_V_SYNC_A_BASE_IDX 2 9209#define regOTG2_OTG_V_SYNC_A_CNTL 0x1c38 9210#define regOTG2_OTG_V_SYNC_A_CNTL_BASE_IDX 2 9211#define regOTG2_OTG_TRIGA_CNTL 0x1c39 9212#define regOTG2_OTG_TRIGA_CNTL_BASE_IDX 2 9213#define regOTG2_OTG_TRIGA_MANUAL_TRIG 0x1c3a 9214#define regOTG2_OTG_TRIGA_MANUAL_TRIG_BASE_IDX 2 9215#define regOTG2_OTG_TRIGB_CNTL 0x1c3b 9216#define regOTG2_OTG_TRIGB_CNTL_BASE_IDX 2 9217#define regOTG2_OTG_TRIGB_MANUAL_TRIG 0x1c3c 9218#define regOTG2_OTG_TRIGB_MANUAL_TRIG_BASE_IDX 2 9219#define regOTG2_OTG_FORCE_COUNT_NOW_CNTL 0x1c3d 9220#define regOTG2_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX 2 9221#define regOTG2_OTG_FLOW_CONTROL 0x1c3e 9222#define regOTG2_OTG_FLOW_CONTROL_BASE_IDX 2 9223#define regOTG2_OTG_STEREO_FORCE_NEXT_EYE 0x1c3f 9224#define regOTG2_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX 2 9225#define regOTG2_OTG_CONTROL 0x1c41 9226#define regOTG2_OTG_CONTROL_BASE_IDX 2 9227#define regOTG2_OTG_INTERLACE_CONTROL 0x1c44 9228#define regOTG2_OTG_INTERLACE_CONTROL_BASE_IDX 2 9229#define regOTG2_OTG_INTERLACE_STATUS 0x1c45 9230#define regOTG2_OTG_INTERLACE_STATUS_BASE_IDX 2 9231#define regOTG2_OTG_PIXEL_DATA_READBACK0 0x1c47 9232#define regOTG2_OTG_PIXEL_DATA_READBACK0_BASE_IDX 2 9233#define regOTG2_OTG_PIXEL_DATA_READBACK1 0x1c48 9234#define regOTG2_OTG_PIXEL_DATA_READBACK1_BASE_IDX 2 9235#define regOTG2_OTG_STATUS 0x1c49 9236#define regOTG2_OTG_STATUS_BASE_IDX 2 9237#define regOTG2_OTG_STATUS_POSITION 0x1c4a 9238#define regOTG2_OTG_STATUS_POSITION_BASE_IDX 2 9239#define regOTG2_OTG_NOM_VERT_POSITION 0x1c4b 9240#define regOTG2_OTG_NOM_VERT_POSITION_BASE_IDX 2 9241#define regOTG2_OTG_STATUS_FRAME_COUNT 0x1c4c 9242#define regOTG2_OTG_STATUS_FRAME_COUNT_BASE_IDX 2 9243#define regOTG2_OTG_STATUS_VF_COUNT 0x1c4d 9244#define regOTG2_OTG_STATUS_VF_COUNT_BASE_IDX 2 9245#define regOTG2_OTG_STATUS_HV_COUNT 0x1c4e 9246#define regOTG2_OTG_STATUS_HV_COUNT_BASE_IDX 2 9247#define regOTG2_OTG_COUNT_CONTROL 0x1c4f 9248#define regOTG2_OTG_COUNT_CONTROL_BASE_IDX 2 9249#define regOTG2_OTG_COUNT_RESET 0x1c50 9250#define regOTG2_OTG_COUNT_RESET_BASE_IDX 2 9251#define regOTG2_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1c51 9252#define regOTG2_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2 9253#define regOTG2_OTG_VERT_SYNC_CONTROL 0x1c52 9254#define regOTG2_OTG_VERT_SYNC_CONTROL_BASE_IDX 2 9255#define regOTG2_OTG_STEREO_STATUS 0x1c53 9256#define regOTG2_OTG_STEREO_STATUS_BASE_IDX 2 9257#define regOTG2_OTG_STEREO_CONTROL 0x1c54 9258#define regOTG2_OTG_STEREO_CONTROL_BASE_IDX 2 9259#define regOTG2_OTG_SNAPSHOT_STATUS 0x1c55 9260#define regOTG2_OTG_SNAPSHOT_STATUS_BASE_IDX 2 9261#define regOTG2_OTG_SNAPSHOT_CONTROL 0x1c56 9262#define regOTG2_OTG_SNAPSHOT_CONTROL_BASE_IDX 2 9263#define regOTG2_OTG_SNAPSHOT_POSITION 0x1c57 9264#define regOTG2_OTG_SNAPSHOT_POSITION_BASE_IDX 2 9265#define regOTG2_OTG_SNAPSHOT_FRAME 0x1c58 9266#define regOTG2_OTG_SNAPSHOT_FRAME_BASE_IDX 2 9267#define regOTG2_OTG_INTERRUPT_CONTROL 0x1c59 9268#define regOTG2_OTG_INTERRUPT_CONTROL_BASE_IDX 2 9269#define regOTG2_OTG_UPDATE_LOCK 0x1c5a 9270#define regOTG2_OTG_UPDATE_LOCK_BASE_IDX 2 9271#define regOTG2_OTG_DOUBLE_BUFFER_CONTROL 0x1c5b 9272#define regOTG2_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 9273#define regOTG2_OTG_MASTER_EN 0x1c5c 9274#define regOTG2_OTG_MASTER_EN_BASE_IDX 2 9275#define regOTG2_OTG_VERTICAL_INTERRUPT0_POSITION 0x1c62 9276#define regOTG2_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2 9277#define regOTG2_OTG_VERTICAL_INTERRUPT0_CONTROL 0x1c63 9278#define regOTG2_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2 9279#define regOTG2_OTG_VERTICAL_INTERRUPT1_POSITION 0x1c64 9280#define regOTG2_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2 9281#define regOTG2_OTG_VERTICAL_INTERRUPT1_CONTROL 0x1c65 9282#define regOTG2_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2 9283#define regOTG2_OTG_VERTICAL_INTERRUPT2_POSITION 0x1c66 9284#define regOTG2_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2 9285#define regOTG2_OTG_VERTICAL_INTERRUPT2_CONTROL 0x1c67 9286#define regOTG2_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2 9287#define regOTG2_OTG_CRC_CNTL 0x1c68 9288#define regOTG2_OTG_CRC_CNTL_BASE_IDX 2 9289#define regOTG2_OTG_CRC_CNTL2 0x1c69 9290#define regOTG2_OTG_CRC_CNTL2_BASE_IDX 2 9291#define regOTG2_OTG_CRC0_WINDOWA_X_CONTROL 0x1c6a 9292#define regOTG2_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2 9293#define regOTG2_OTG_CRC0_WINDOWA_Y_CONTROL 0x1c6b 9294#define regOTG2_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2 9295#define regOTG2_OTG_CRC0_WINDOWB_X_CONTROL 0x1c6c 9296#define regOTG2_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2 9297#define regOTG2_OTG_CRC0_WINDOWB_Y_CONTROL 0x1c6d 9298#define regOTG2_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2 9299#define regOTG2_OTG_CRC0_DATA_RG 0x1c6e 9300#define regOTG2_OTG_CRC0_DATA_RG_BASE_IDX 2 9301#define regOTG2_OTG_CRC0_DATA_B 0x1c6f 9302#define regOTG2_OTG_CRC0_DATA_B_BASE_IDX 2 9303#define regOTG2_OTG_CRC1_WINDOWA_X_CONTROL 0x1c70 9304#define regOTG2_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2 9305#define regOTG2_OTG_CRC1_WINDOWA_Y_CONTROL 0x1c71 9306#define regOTG2_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2 9307#define regOTG2_OTG_CRC1_WINDOWB_X_CONTROL 0x1c72 9308#define regOTG2_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2 9309#define regOTG2_OTG_CRC1_WINDOWB_Y_CONTROL 0x1c73 9310#define regOTG2_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2 9311#define regOTG2_OTG_CRC1_DATA_RG 0x1c74 9312#define regOTG2_OTG_CRC1_DATA_RG_BASE_IDX 2 9313#define regOTG2_OTG_CRC1_DATA_B 0x1c75 9314#define regOTG2_OTG_CRC1_DATA_B_BASE_IDX 2 9315#define regOTG2_OTG_CRC2_DATA_RG 0x1c76 9316#define regOTG2_OTG_CRC2_DATA_RG_BASE_IDX 2 9317#define regOTG2_OTG_CRC2_DATA_B 0x1c77 9318#define regOTG2_OTG_CRC2_DATA_B_BASE_IDX 2 9319#define regOTG2_OTG_CRC3_DATA_RG 0x1c78 9320#define regOTG2_OTG_CRC3_DATA_RG_BASE_IDX 2 9321#define regOTG2_OTG_CRC3_DATA_B 0x1c79 9322#define regOTG2_OTG_CRC3_DATA_B_BASE_IDX 2 9323#define regOTG2_OTG_CRC_SIG_RED_GREEN_MASK 0x1c7a 9324#define regOTG2_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2 9325#define regOTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK 0x1c7b 9326#define regOTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2 9327#define regOTG2_OTG_STATIC_SCREEN_CONTROL 0x1c82 9328#define regOTG2_OTG_STATIC_SCREEN_CONTROL_BASE_IDX 2 9329#define regOTG2_OTG_3D_STRUCTURE_CONTROL 0x1c83 9330#define regOTG2_OTG_3D_STRUCTURE_CONTROL_BASE_IDX 2 9331#define regOTG2_OTG_GSL_VSYNC_GAP 0x1c84 9332#define regOTG2_OTG_GSL_VSYNC_GAP_BASE_IDX 2 9333#define regOTG2_OTG_MASTER_UPDATE_MODE 0x1c85 9334#define regOTG2_OTG_MASTER_UPDATE_MODE_BASE_IDX 2 9335#define regOTG2_OTG_CLOCK_CONTROL 0x1c86 9336#define regOTG2_OTG_CLOCK_CONTROL_BASE_IDX 2 9337#define regOTG2_OTG_VSTARTUP_PARAM 0x1c87 9338#define regOTG2_OTG_VSTARTUP_PARAM_BASE_IDX 2 9339#define regOTG2_OTG_VUPDATE_PARAM 0x1c88 9340#define regOTG2_OTG_VUPDATE_PARAM_BASE_IDX 2 9341#define regOTG2_OTG_VREADY_PARAM 0x1c89 9342#define regOTG2_OTG_VREADY_PARAM_BASE_IDX 2 9343#define regOTG2_OTG_GLOBAL_SYNC_STATUS 0x1c8a 9344#define regOTG2_OTG_GLOBAL_SYNC_STATUS_BASE_IDX 2 9345#define regOTG2_OTG_MASTER_UPDATE_LOCK 0x1c8b 9346#define regOTG2_OTG_MASTER_UPDATE_LOCK_BASE_IDX 2 9347#define regOTG2_OTG_GSL_CONTROL 0x1c8c 9348#define regOTG2_OTG_GSL_CONTROL_BASE_IDX 2 9349#define regOTG2_OTG_GSL_WINDOW_X 0x1c8d 9350#define regOTG2_OTG_GSL_WINDOW_X_BASE_IDX 2 9351#define regOTG2_OTG_GSL_WINDOW_Y 0x1c8e 9352#define regOTG2_OTG_GSL_WINDOW_Y_BASE_IDX 2 9353#define regOTG2_OTG_VUPDATE_KEEPOUT 0x1c8f 9354#define regOTG2_OTG_VUPDATE_KEEPOUT_BASE_IDX 2 9355#define regOTG2_OTG_GLOBAL_CONTROL0 0x1c90 9356#define regOTG2_OTG_GLOBAL_CONTROL0_BASE_IDX 2 9357#define regOTG2_OTG_GLOBAL_CONTROL1 0x1c91 9358#define regOTG2_OTG_GLOBAL_CONTROL1_BASE_IDX 2 9359#define regOTG2_OTG_GLOBAL_CONTROL2 0x1c92 9360#define regOTG2_OTG_GLOBAL_CONTROL2_BASE_IDX 2 9361#define regOTG2_OTG_GLOBAL_CONTROL3 0x1c93 9362#define regOTG2_OTG_GLOBAL_CONTROL3_BASE_IDX 2 9363#define regOTG2_OTG_GLOBAL_CONTROL4 0x1c94 9364#define regOTG2_OTG_GLOBAL_CONTROL4_BASE_IDX 2 9365#define regOTG2_OTG_TRIG_MANUAL_CONTROL 0x1c95 9366#define regOTG2_OTG_TRIG_MANUAL_CONTROL_BASE_IDX 2 9367#define regOTG2_OTG_MANUAL_FLOW_CONTROL 0x1c96 9368#define regOTG2_OTG_MANUAL_FLOW_CONTROL_BASE_IDX 2 9369#define regOTG2_OTG_DRR_TIMING_INT_STATUS 0x1c97 9370#define regOTG2_OTG_DRR_TIMING_INT_STATUS_BASE_IDX 2 9371#define regOTG2_OTG_DRR_V_TOTAL_REACH_RANGE 0x1c98 9372#define regOTG2_OTG_DRR_V_TOTAL_REACH_RANGE_BASE_IDX 2 9373#define regOTG2_OTG_DRR_V_TOTAL_CHANGE 0x1c99 9374#define regOTG2_OTG_DRR_V_TOTAL_CHANGE_BASE_IDX 2 9375#define regOTG2_OTG_DRR_TRIGGER_WINDOW 0x1c9a 9376#define regOTG2_OTG_DRR_TRIGGER_WINDOW_BASE_IDX 2 9377#define regOTG2_OTG_DRR_CONTROL 0x1c9b 9378#define regOTG2_OTG_DRR_CONTROL_BASE_IDX 2 9379#define regOTG2_OTG_M_CONST_DTO0 0x1c9c 9380#define regOTG2_OTG_M_CONST_DTO0_BASE_IDX 2 9381#define regOTG2_OTG_M_CONST_DTO1 0x1c9d 9382#define regOTG2_OTG_M_CONST_DTO1_BASE_IDX 2 9383#define regOTG2_OTG_REQUEST_CONTROL 0x1c9e 9384#define regOTG2_OTG_REQUEST_CONTROL_BASE_IDX 2 9385#define regOTG2_OTG_DSC_START_POSITION 0x1c9f 9386#define regOTG2_OTG_DSC_START_POSITION_BASE_IDX 2 9387#define regOTG2_OTG_PIPE_UPDATE_STATUS 0x1ca0 9388#define regOTG2_OTG_PIPE_UPDATE_STATUS_BASE_IDX 2 9389#define regOTG2_OTG_SPARE_REGISTER 0x1ca2 9390#define regOTG2_OTG_SPARE_REGISTER_BASE_IDX 2 9391 9392 9393// addressBlock: dce_dc_optc_otg3_dispdec 9394// base address: 0x600 9395#define regOTG3_OTG_H_TOTAL 0x1caa 9396#define regOTG3_OTG_H_TOTAL_BASE_IDX 2 9397#define regOTG3_OTG_H_BLANK_START_END 0x1cab 9398#define regOTG3_OTG_H_BLANK_START_END_BASE_IDX 2 9399#define regOTG3_OTG_H_SYNC_A 0x1cac 9400#define regOTG3_OTG_H_SYNC_A_BASE_IDX 2 9401#define regOTG3_OTG_H_SYNC_A_CNTL 0x1cad 9402#define regOTG3_OTG_H_SYNC_A_CNTL_BASE_IDX 2 9403#define regOTG3_OTG_H_TIMING_CNTL 0x1cae 9404#define regOTG3_OTG_H_TIMING_CNTL_BASE_IDX 2 9405#define regOTG3_OTG_V_TOTAL 0x1caf 9406#define regOTG3_OTG_V_TOTAL_BASE_IDX 2 9407#define regOTG3_OTG_V_TOTAL_MIN 0x1cb0 9408#define regOTG3_OTG_V_TOTAL_MIN_BASE_IDX 2 9409#define regOTG3_OTG_V_TOTAL_MAX 0x1cb1 9410#define regOTG3_OTG_V_TOTAL_MAX_BASE_IDX 2 9411#define regOTG3_OTG_V_TOTAL_MID 0x1cb2 9412#define regOTG3_OTG_V_TOTAL_MID_BASE_IDX 2 9413#define regOTG3_OTG_V_TOTAL_CONTROL 0x1cb3 9414#define regOTG3_OTG_V_TOTAL_CONTROL_BASE_IDX 2 9415#define regOTG3_OTG_V_TOTAL_INT_STATUS 0x1cb4 9416#define regOTG3_OTG_V_TOTAL_INT_STATUS_BASE_IDX 2 9417#define regOTG3_OTG_VSYNC_NOM_INT_STATUS 0x1cb5 9418#define regOTG3_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX 2 9419#define regOTG3_OTG_V_BLANK_START_END 0x1cb6 9420#define regOTG3_OTG_V_BLANK_START_END_BASE_IDX 2 9421#define regOTG3_OTG_V_SYNC_A 0x1cb7 9422#define regOTG3_OTG_V_SYNC_A_BASE_IDX 2 9423#define regOTG3_OTG_V_SYNC_A_CNTL 0x1cb8 9424#define regOTG3_OTG_V_SYNC_A_CNTL_BASE_IDX 2 9425#define regOTG3_OTG_TRIGA_CNTL 0x1cb9 9426#define regOTG3_OTG_TRIGA_CNTL_BASE_IDX 2 9427#define regOTG3_OTG_TRIGA_MANUAL_TRIG 0x1cba 9428#define regOTG3_OTG_TRIGA_MANUAL_TRIG_BASE_IDX 2 9429#define regOTG3_OTG_TRIGB_CNTL 0x1cbb 9430#define regOTG3_OTG_TRIGB_CNTL_BASE_IDX 2 9431#define regOTG3_OTG_TRIGB_MANUAL_TRIG 0x1cbc 9432#define regOTG3_OTG_TRIGB_MANUAL_TRIG_BASE_IDX 2 9433#define regOTG3_OTG_FORCE_COUNT_NOW_CNTL 0x1cbd 9434#define regOTG3_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX 2 9435#define regOTG3_OTG_FLOW_CONTROL 0x1cbe 9436#define regOTG3_OTG_FLOW_CONTROL_BASE_IDX 2 9437#define regOTG3_OTG_STEREO_FORCE_NEXT_EYE 0x1cbf 9438#define regOTG3_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX 2 9439#define regOTG3_OTG_CONTROL 0x1cc1 9440#define regOTG3_OTG_CONTROL_BASE_IDX 2 9441#define regOTG3_OTG_INTERLACE_CONTROL 0x1cc4 9442#define regOTG3_OTG_INTERLACE_CONTROL_BASE_IDX 2 9443#define regOTG3_OTG_INTERLACE_STATUS 0x1cc5 9444#define regOTG3_OTG_INTERLACE_STATUS_BASE_IDX 2 9445#define regOTG3_OTG_PIXEL_DATA_READBACK0 0x1cc7 9446#define regOTG3_OTG_PIXEL_DATA_READBACK0_BASE_IDX 2 9447#define regOTG3_OTG_PIXEL_DATA_READBACK1 0x1cc8 9448#define regOTG3_OTG_PIXEL_DATA_READBACK1_BASE_IDX 2 9449#define regOTG3_OTG_STATUS 0x1cc9 9450#define regOTG3_OTG_STATUS_BASE_IDX 2 9451#define regOTG3_OTG_STATUS_POSITION 0x1cca 9452#define regOTG3_OTG_STATUS_POSITION_BASE_IDX 2 9453#define regOTG3_OTG_NOM_VERT_POSITION 0x1ccb 9454#define regOTG3_OTG_NOM_VERT_POSITION_BASE_IDX 2 9455#define regOTG3_OTG_STATUS_FRAME_COUNT 0x1ccc 9456#define regOTG3_OTG_STATUS_FRAME_COUNT_BASE_IDX 2 9457#define regOTG3_OTG_STATUS_VF_COUNT 0x1ccd 9458#define regOTG3_OTG_STATUS_VF_COUNT_BASE_IDX 2 9459#define regOTG3_OTG_STATUS_HV_COUNT 0x1cce 9460#define regOTG3_OTG_STATUS_HV_COUNT_BASE_IDX 2 9461#define regOTG3_OTG_COUNT_CONTROL 0x1ccf 9462#define regOTG3_OTG_COUNT_CONTROL_BASE_IDX 2 9463#define regOTG3_OTG_COUNT_RESET 0x1cd0 9464#define regOTG3_OTG_COUNT_RESET_BASE_IDX 2 9465#define regOTG3_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1cd1 9466#define regOTG3_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2 9467#define regOTG3_OTG_VERT_SYNC_CONTROL 0x1cd2 9468#define regOTG3_OTG_VERT_SYNC_CONTROL_BASE_IDX 2 9469#define regOTG3_OTG_STEREO_STATUS 0x1cd3 9470#define regOTG3_OTG_STEREO_STATUS_BASE_IDX 2 9471#define regOTG3_OTG_STEREO_CONTROL 0x1cd4 9472#define regOTG3_OTG_STEREO_CONTROL_BASE_IDX 2 9473#define regOTG3_OTG_SNAPSHOT_STATUS 0x1cd5 9474#define regOTG3_OTG_SNAPSHOT_STATUS_BASE_IDX 2 9475#define regOTG3_OTG_SNAPSHOT_CONTROL 0x1cd6 9476#define regOTG3_OTG_SNAPSHOT_CONTROL_BASE_IDX 2 9477#define regOTG3_OTG_SNAPSHOT_POSITION 0x1cd7 9478#define regOTG3_OTG_SNAPSHOT_POSITION_BASE_IDX 2 9479#define regOTG3_OTG_SNAPSHOT_FRAME 0x1cd8 9480#define regOTG3_OTG_SNAPSHOT_FRAME_BASE_IDX 2 9481#define regOTG3_OTG_INTERRUPT_CONTROL 0x1cd9 9482#define regOTG3_OTG_INTERRUPT_CONTROL_BASE_IDX 2 9483#define regOTG3_OTG_UPDATE_LOCK 0x1cda 9484#define regOTG3_OTG_UPDATE_LOCK_BASE_IDX 2 9485#define regOTG3_OTG_DOUBLE_BUFFER_CONTROL 0x1cdb 9486#define regOTG3_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 9487#define regOTG3_OTG_MASTER_EN 0x1cdc 9488#define regOTG3_OTG_MASTER_EN_BASE_IDX 2 9489#define regOTG3_OTG_VERTICAL_INTERRUPT0_POSITION 0x1ce2 9490#define regOTG3_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2 9491#define regOTG3_OTG_VERTICAL_INTERRUPT0_CONTROL 0x1ce3 9492#define regOTG3_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2 9493#define regOTG3_OTG_VERTICAL_INTERRUPT1_POSITION 0x1ce4 9494#define regOTG3_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2 9495#define regOTG3_OTG_VERTICAL_INTERRUPT1_CONTROL 0x1ce5 9496#define regOTG3_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2 9497#define regOTG3_OTG_VERTICAL_INTERRUPT2_POSITION 0x1ce6 9498#define regOTG3_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2 9499#define regOTG3_OTG_VERTICAL_INTERRUPT2_CONTROL 0x1ce7 9500#define regOTG3_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2 9501#define regOTG3_OTG_CRC_CNTL 0x1ce8 9502#define regOTG3_OTG_CRC_CNTL_BASE_IDX 2 9503#define regOTG3_OTG_CRC_CNTL2 0x1ce9 9504#define regOTG3_OTG_CRC_CNTL2_BASE_IDX 2 9505#define regOTG3_OTG_CRC0_WINDOWA_X_CONTROL 0x1cea 9506#define regOTG3_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2 9507#define regOTG3_OTG_CRC0_WINDOWA_Y_CONTROL 0x1ceb 9508#define regOTG3_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2 9509#define regOTG3_OTG_CRC0_WINDOWB_X_CONTROL 0x1cec 9510#define regOTG3_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2 9511#define regOTG3_OTG_CRC0_WINDOWB_Y_CONTROL 0x1ced 9512#define regOTG3_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2 9513#define regOTG3_OTG_CRC0_DATA_RG 0x1cee 9514#define regOTG3_OTG_CRC0_DATA_RG_BASE_IDX 2 9515#define regOTG3_OTG_CRC0_DATA_B 0x1cef 9516#define regOTG3_OTG_CRC0_DATA_B_BASE_IDX 2 9517#define regOTG3_OTG_CRC1_WINDOWA_X_CONTROL 0x1cf0 9518#define regOTG3_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2 9519#define regOTG3_OTG_CRC1_WINDOWA_Y_CONTROL 0x1cf1 9520#define regOTG3_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2 9521#define regOTG3_OTG_CRC1_WINDOWB_X_CONTROL 0x1cf2 9522#define regOTG3_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2 9523#define regOTG3_OTG_CRC1_WINDOWB_Y_CONTROL 0x1cf3 9524#define regOTG3_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2 9525#define regOTG3_OTG_CRC1_DATA_RG 0x1cf4 9526#define regOTG3_OTG_CRC1_DATA_RG_BASE_IDX 2 9527#define regOTG3_OTG_CRC1_DATA_B 0x1cf5 9528#define regOTG3_OTG_CRC1_DATA_B_BASE_IDX 2 9529#define regOTG3_OTG_CRC2_DATA_RG 0x1cf6 9530#define regOTG3_OTG_CRC2_DATA_RG_BASE_IDX 2 9531#define regOTG3_OTG_CRC2_DATA_B 0x1cf7 9532#define regOTG3_OTG_CRC2_DATA_B_BASE_IDX 2 9533#define regOTG3_OTG_CRC3_DATA_RG 0x1cf8 9534#define regOTG3_OTG_CRC3_DATA_RG_BASE_IDX 2 9535#define regOTG3_OTG_CRC3_DATA_B 0x1cf9 9536#define regOTG3_OTG_CRC3_DATA_B_BASE_IDX 2 9537#define regOTG3_OTG_CRC_SIG_RED_GREEN_MASK 0x1cfa 9538#define regOTG3_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2 9539#define regOTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK 0x1cfb 9540#define regOTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2 9541#define regOTG3_OTG_STATIC_SCREEN_CONTROL 0x1d02 9542#define regOTG3_OTG_STATIC_SCREEN_CONTROL_BASE_IDX 2 9543#define regOTG3_OTG_3D_STRUCTURE_CONTROL 0x1d03 9544#define regOTG3_OTG_3D_STRUCTURE_CONTROL_BASE_IDX 2 9545#define regOTG3_OTG_GSL_VSYNC_GAP 0x1d04 9546#define regOTG3_OTG_GSL_VSYNC_GAP_BASE_IDX 2 9547#define regOTG3_OTG_MASTER_UPDATE_MODE 0x1d05 9548#define regOTG3_OTG_MASTER_UPDATE_MODE_BASE_IDX 2 9549#define regOTG3_OTG_CLOCK_CONTROL 0x1d06 9550#define regOTG3_OTG_CLOCK_CONTROL_BASE_IDX 2 9551#define regOTG3_OTG_VSTARTUP_PARAM 0x1d07 9552#define regOTG3_OTG_VSTARTUP_PARAM_BASE_IDX 2 9553#define regOTG3_OTG_VUPDATE_PARAM 0x1d08 9554#define regOTG3_OTG_VUPDATE_PARAM_BASE_IDX 2 9555#define regOTG3_OTG_VREADY_PARAM 0x1d09 9556#define regOTG3_OTG_VREADY_PARAM_BASE_IDX 2 9557#define regOTG3_OTG_GLOBAL_SYNC_STATUS 0x1d0a 9558#define regOTG3_OTG_GLOBAL_SYNC_STATUS_BASE_IDX 2 9559#define regOTG3_OTG_MASTER_UPDATE_LOCK 0x1d0b 9560#define regOTG3_OTG_MASTER_UPDATE_LOCK_BASE_IDX 2 9561#define regOTG3_OTG_GSL_CONTROL 0x1d0c 9562#define regOTG3_OTG_GSL_CONTROL_BASE_IDX 2 9563#define regOTG3_OTG_GSL_WINDOW_X 0x1d0d 9564#define regOTG3_OTG_GSL_WINDOW_X_BASE_IDX 2 9565#define regOTG3_OTG_GSL_WINDOW_Y 0x1d0e 9566#define regOTG3_OTG_GSL_WINDOW_Y_BASE_IDX 2 9567#define regOTG3_OTG_VUPDATE_KEEPOUT 0x1d0f 9568#define regOTG3_OTG_VUPDATE_KEEPOUT_BASE_IDX 2 9569#define regOTG3_OTG_GLOBAL_CONTROL0 0x1d10 9570#define regOTG3_OTG_GLOBAL_CONTROL0_BASE_IDX 2 9571#define regOTG3_OTG_GLOBAL_CONTROL1 0x1d11 9572#define regOTG3_OTG_GLOBAL_CONTROL1_BASE_IDX 2 9573#define regOTG3_OTG_GLOBAL_CONTROL2 0x1d12 9574#define regOTG3_OTG_GLOBAL_CONTROL2_BASE_IDX 2 9575#define regOTG3_OTG_GLOBAL_CONTROL3 0x1d13 9576#define regOTG3_OTG_GLOBAL_CONTROL3_BASE_IDX 2 9577#define regOTG3_OTG_GLOBAL_CONTROL4 0x1d14 9578#define regOTG3_OTG_GLOBAL_CONTROL4_BASE_IDX 2 9579#define regOTG3_OTG_TRIG_MANUAL_CONTROL 0x1d15 9580#define regOTG3_OTG_TRIG_MANUAL_CONTROL_BASE_IDX 2 9581#define regOTG3_OTG_MANUAL_FLOW_CONTROL 0x1d16 9582#define regOTG3_OTG_MANUAL_FLOW_CONTROL_BASE_IDX 2 9583#define regOTG3_OTG_DRR_TIMING_INT_STATUS 0x1d17 9584#define regOTG3_OTG_DRR_TIMING_INT_STATUS_BASE_IDX 2 9585#define regOTG3_OTG_DRR_V_TOTAL_REACH_RANGE 0x1d18 9586#define regOTG3_OTG_DRR_V_TOTAL_REACH_RANGE_BASE_IDX 2 9587#define regOTG3_OTG_DRR_V_TOTAL_CHANGE 0x1d19 9588#define regOTG3_OTG_DRR_V_TOTAL_CHANGE_BASE_IDX 2 9589#define regOTG3_OTG_DRR_TRIGGER_WINDOW 0x1d1a 9590#define regOTG3_OTG_DRR_TRIGGER_WINDOW_BASE_IDX 2 9591#define regOTG3_OTG_DRR_CONTROL 0x1d1b 9592#define regOTG3_OTG_DRR_CONTROL_BASE_IDX 2 9593#define regOTG3_OTG_M_CONST_DTO0 0x1d1c 9594#define regOTG3_OTG_M_CONST_DTO0_BASE_IDX 2 9595#define regOTG3_OTG_M_CONST_DTO1 0x1d1d 9596#define regOTG3_OTG_M_CONST_DTO1_BASE_IDX 2 9597#define regOTG3_OTG_REQUEST_CONTROL 0x1d1e 9598#define regOTG3_OTG_REQUEST_CONTROL_BASE_IDX 2 9599#define regOTG3_OTG_DSC_START_POSITION 0x1d1f 9600#define regOTG3_OTG_DSC_START_POSITION_BASE_IDX 2 9601#define regOTG3_OTG_PIPE_UPDATE_STATUS 0x1d20 9602#define regOTG3_OTG_PIPE_UPDATE_STATUS_BASE_IDX 2 9603#define regOTG3_OTG_SPARE_REGISTER 0x1d22 9604#define regOTG3_OTG_SPARE_REGISTER_BASE_IDX 2 9605 9606 9607// addressBlock: dce_dc_optc_optc_misc_dispdec 9608// base address: 0x0 9609#define regDWB_SOURCE_SELECT 0x1e2a 9610#define regDWB_SOURCE_SELECT_BASE_IDX 2 9611#define regGSL_SOURCE_SELECT 0x1e2b 9612#define regGSL_SOURCE_SELECT_BASE_IDX 2 9613#define regOPTC_CLOCK_CONTROL 0x1e2c 9614#define regOPTC_CLOCK_CONTROL_BASE_IDX 2 9615#define regODM_MEM_PWR_CTRL 0x1e2d 9616#define regODM_MEM_PWR_CTRL_BASE_IDX 2 9617#define regODM_MEM_PWR_CTRL3 0x1e2f 9618#define regODM_MEM_PWR_CTRL3_BASE_IDX 2 9619#define regODM_MEM_PWR_STATUS 0x1e30 9620#define regODM_MEM_PWR_STATUS_BASE_IDX 2 9621#define regOPTC_MISC_SPARE_REGISTER 0x1e31 9622#define regOPTC_MISC_SPARE_REGISTER_BASE_IDX 2 9623 9624 9625// addressBlock: dce_dc_optc_optc_dcperfmon_dc_perfmon_dispdec 9626// base address: 0x79a8 9627#define regDC_PERFMON17_PERFCOUNTER_CNTL 0x1e6a 9628#define regDC_PERFMON17_PERFCOUNTER_CNTL_BASE_IDX 2 9629#define regDC_PERFMON17_PERFCOUNTER_CNTL2 0x1e6b 9630#define regDC_PERFMON17_PERFCOUNTER_CNTL2_BASE_IDX 2 9631#define regDC_PERFMON17_PERFCOUNTER_STATE 0x1e6c 9632#define regDC_PERFMON17_PERFCOUNTER_STATE_BASE_IDX 2 9633#define regDC_PERFMON17_PERFMON_CNTL 0x1e6d 9634#define regDC_PERFMON17_PERFMON_CNTL_BASE_IDX 2 9635#define regDC_PERFMON17_PERFMON_CNTL2 0x1e6e 9636#define regDC_PERFMON17_PERFMON_CNTL2_BASE_IDX 2 9637#define regDC_PERFMON17_PERFMON_CVALUE_INT_MISC 0x1e6f 9638#define regDC_PERFMON17_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 9639#define regDC_PERFMON17_PERFMON_CVALUE_LOW 0x1e70 9640#define regDC_PERFMON17_PERFMON_CVALUE_LOW_BASE_IDX 2 9641#define regDC_PERFMON17_PERFMON_HI 0x1e71 9642#define regDC_PERFMON17_PERFMON_HI_BASE_IDX 2 9643#define regDC_PERFMON17_PERFMON_LOW 0x1e72 9644#define regDC_PERFMON17_PERFMON_LOW_BASE_IDX 2 9645 9646 9647// addressBlock: dce_dc_dio_hpd0_dispdec 9648// base address: 0x0 9649#define regHPD0_DC_HPD_INT_STATUS 0x1f14 9650#define regHPD0_DC_HPD_INT_STATUS_BASE_IDX 2 9651#define regHPD0_DC_HPD_INT_CONTROL 0x1f15 9652#define regHPD0_DC_HPD_INT_CONTROL_BASE_IDX 2 9653#define regHPD0_DC_HPD_CONTROL 0x1f16 9654#define regHPD0_DC_HPD_CONTROL_BASE_IDX 2 9655#define regHPD0_DC_HPD_FAST_TRAIN_CNTL 0x1f17 9656#define regHPD0_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2 9657#define regHPD0_DC_HPD_TOGGLE_FILT_CNTL 0x1f18 9658#define regHPD0_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2 9659 9660 9661// addressBlock: dce_dc_dio_hpd1_dispdec 9662// base address: 0x20 9663#define regHPD1_DC_HPD_INT_STATUS 0x1f1c 9664#define regHPD1_DC_HPD_INT_STATUS_BASE_IDX 2 9665#define regHPD1_DC_HPD_INT_CONTROL 0x1f1d 9666#define regHPD1_DC_HPD_INT_CONTROL_BASE_IDX 2 9667#define regHPD1_DC_HPD_CONTROL 0x1f1e 9668#define regHPD1_DC_HPD_CONTROL_BASE_IDX 2 9669#define regHPD1_DC_HPD_FAST_TRAIN_CNTL 0x1f1f 9670#define regHPD1_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2 9671#define regHPD1_DC_HPD_TOGGLE_FILT_CNTL 0x1f20 9672#define regHPD1_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2 9673 9674 9675// addressBlock: dce_dc_dio_hpd2_dispdec 9676// base address: 0x40 9677#define regHPD2_DC_HPD_INT_STATUS 0x1f24 9678#define regHPD2_DC_HPD_INT_STATUS_BASE_IDX 2 9679#define regHPD2_DC_HPD_INT_CONTROL 0x1f25 9680#define regHPD2_DC_HPD_INT_CONTROL_BASE_IDX 2 9681#define regHPD2_DC_HPD_CONTROL 0x1f26 9682#define regHPD2_DC_HPD_CONTROL_BASE_IDX 2 9683#define regHPD2_DC_HPD_FAST_TRAIN_CNTL 0x1f27 9684#define regHPD2_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2 9685#define regHPD2_DC_HPD_TOGGLE_FILT_CNTL 0x1f28 9686#define regHPD2_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2 9687 9688 9689// addressBlock: dce_dc_dio_hpd3_dispdec 9690// base address: 0x60 9691#define regHPD3_DC_HPD_INT_STATUS 0x1f2c 9692#define regHPD3_DC_HPD_INT_STATUS_BASE_IDX 2 9693#define regHPD3_DC_HPD_INT_CONTROL 0x1f2d 9694#define regHPD3_DC_HPD_INT_CONTROL_BASE_IDX 2 9695#define regHPD3_DC_HPD_CONTROL 0x1f2e 9696#define regHPD3_DC_HPD_CONTROL_BASE_IDX 2 9697#define regHPD3_DC_HPD_FAST_TRAIN_CNTL 0x1f2f 9698#define regHPD3_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2 9699#define regHPD3_DC_HPD_TOGGLE_FILT_CNTL 0x1f30 9700#define regHPD3_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2 9701 9702 9703// addressBlock: dce_dc_dio_hpd4_dispdec 9704// base address: 0x80 9705#define regHPD4_DC_HPD_INT_STATUS 0x1f34 9706#define regHPD4_DC_HPD_INT_STATUS_BASE_IDX 2 9707#define regHPD4_DC_HPD_INT_CONTROL 0x1f35 9708#define regHPD4_DC_HPD_INT_CONTROL_BASE_IDX 2 9709#define regHPD4_DC_HPD_CONTROL 0x1f36 9710#define regHPD4_DC_HPD_CONTROL_BASE_IDX 2 9711#define regHPD4_DC_HPD_FAST_TRAIN_CNTL 0x1f37 9712#define regHPD4_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2 9713#define regHPD4_DC_HPD_TOGGLE_FILT_CNTL 0x1f38 9714#define regHPD4_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2 9715 9716 9717// addressBlock: dce_dc_dio_dp0_dispdec 9718// base address: 0x0 9719#define regDP0_DP_LINK_CNTL 0x2108 9720#define regDP0_DP_LINK_CNTL_BASE_IDX 2 9721#define regDP0_DP_PIXEL_FORMAT 0x2109 9722#define regDP0_DP_PIXEL_FORMAT_BASE_IDX 2 9723#define regDP0_DP_MSA_COLORIMETRY 0x210a 9724#define regDP0_DP_MSA_COLORIMETRY_BASE_IDX 2 9725#define regDP0_DP_CONFIG 0x210b 9726#define regDP0_DP_CONFIG_BASE_IDX 2 9727#define regDP0_DP_VID_STREAM_CNTL 0x210c 9728#define regDP0_DP_VID_STREAM_CNTL_BASE_IDX 2 9729#define regDP0_DP_STEER_FIFO 0x210d 9730#define regDP0_DP_STEER_FIFO_BASE_IDX 2 9731#define regDP0_DP_MSA_MISC 0x210e 9732#define regDP0_DP_MSA_MISC_BASE_IDX 2 9733#define regDP0_DP_DPHY_INTERNAL_CTRL 0x210f 9734#define regDP0_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 9735#define regDP0_DP_VID_TIMING 0x2110 9736#define regDP0_DP_VID_TIMING_BASE_IDX 2 9737#define regDP0_DP_VID_N 0x2111 9738#define regDP0_DP_VID_N_BASE_IDX 2 9739#define regDP0_DP_VID_M 0x2112 9740#define regDP0_DP_VID_M_BASE_IDX 2 9741#define regDP0_DP_LINK_FRAMING_CNTL 0x2113 9742#define regDP0_DP_LINK_FRAMING_CNTL_BASE_IDX 2 9743#define regDP0_DP_HBR2_EYE_PATTERN 0x2114 9744#define regDP0_DP_HBR2_EYE_PATTERN_BASE_IDX 2 9745#define regDP0_DP_VID_MSA_VBID 0x2115 9746#define regDP0_DP_VID_MSA_VBID_BASE_IDX 2 9747#define regDP0_DP_VID_INTERRUPT_CNTL 0x2116 9748#define regDP0_DP_VID_INTERRUPT_CNTL_BASE_IDX 2 9749#define regDP0_DP_DPHY_CNTL 0x2117 9750#define regDP0_DP_DPHY_CNTL_BASE_IDX 2 9751#define regDP0_DP_DPHY_TRAINING_PATTERN_SEL 0x2118 9752#define regDP0_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2 9753#define regDP0_DP_DPHY_SYM0 0x2119 9754#define regDP0_DP_DPHY_SYM0_BASE_IDX 2 9755#define regDP0_DP_DPHY_SYM1 0x211a 9756#define regDP0_DP_DPHY_SYM1_BASE_IDX 2 9757#define regDP0_DP_DPHY_SYM2 0x211b 9758#define regDP0_DP_DPHY_SYM2_BASE_IDX 2 9759#define regDP0_DP_DPHY_8B10B_CNTL 0x211c 9760#define regDP0_DP_DPHY_8B10B_CNTL_BASE_IDX 2 9761#define regDP0_DP_DPHY_PRBS_CNTL 0x211d 9762#define regDP0_DP_DPHY_PRBS_CNTL_BASE_IDX 2 9763#define regDP0_DP_DPHY_SCRAM_CNTL 0x211e 9764#define regDP0_DP_DPHY_SCRAM_CNTL_BASE_IDX 2 9765#define regDP0_DP_DPHY_CRC_EN 0x211f 9766#define regDP0_DP_DPHY_CRC_EN_BASE_IDX 2 9767#define regDP0_DP_DPHY_CRC_CNTL 0x2120 9768#define regDP0_DP_DPHY_CRC_CNTL_BASE_IDX 2 9769#define regDP0_DP_DPHY_CRC_RESULT 0x2121 9770#define regDP0_DP_DPHY_CRC_RESULT_BASE_IDX 2 9771#define regDP0_DP_DPHY_CRC_MST_CNTL 0x2122 9772#define regDP0_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2 9773#define regDP0_DP_DPHY_CRC_MST_STATUS 0x2123 9774#define regDP0_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2 9775#define regDP0_DP_DPHY_FAST_TRAINING 0x2124 9776#define regDP0_DP_DPHY_FAST_TRAINING_BASE_IDX 2 9777#define regDP0_DP_DPHY_FAST_TRAINING_STATUS 0x2125 9778#define regDP0_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2 9779#define regDP0_DP_SEC_CNTL 0x212b 9780#define regDP0_DP_SEC_CNTL_BASE_IDX 2 9781#define regDP0_DP_SEC_CNTL1 0x212c 9782#define regDP0_DP_SEC_CNTL1_BASE_IDX 2 9783#define regDP0_DP_SEC_FRAMING1 0x212d 9784#define regDP0_DP_SEC_FRAMING1_BASE_IDX 2 9785#define regDP0_DP_SEC_FRAMING2 0x212e 9786#define regDP0_DP_SEC_FRAMING2_BASE_IDX 2 9787#define regDP0_DP_SEC_FRAMING3 0x212f 9788#define regDP0_DP_SEC_FRAMING3_BASE_IDX 2 9789#define regDP0_DP_SEC_FRAMING4 0x2130 9790#define regDP0_DP_SEC_FRAMING4_BASE_IDX 2 9791#define regDP0_DP_SEC_AUD_N 0x2131 9792#define regDP0_DP_SEC_AUD_N_BASE_IDX 2 9793#define regDP0_DP_SEC_AUD_N_READBACK 0x2132 9794#define regDP0_DP_SEC_AUD_N_READBACK_BASE_IDX 2 9795#define regDP0_DP_SEC_AUD_M 0x2133 9796#define regDP0_DP_SEC_AUD_M_BASE_IDX 2 9797#define regDP0_DP_SEC_AUD_M_READBACK 0x2134 9798#define regDP0_DP_SEC_AUD_M_READBACK_BASE_IDX 2 9799#define regDP0_DP_SEC_TIMESTAMP 0x2135 9800#define regDP0_DP_SEC_TIMESTAMP_BASE_IDX 2 9801#define regDP0_DP_SEC_PACKET_CNTL 0x2136 9802#define regDP0_DP_SEC_PACKET_CNTL_BASE_IDX 2 9803#define regDP0_DP_MSE_RATE_CNTL 0x2137 9804#define regDP0_DP_MSE_RATE_CNTL_BASE_IDX 2 9805#define regDP0_DP_MSE_RATE_UPDATE 0x2139 9806#define regDP0_DP_MSE_RATE_UPDATE_BASE_IDX 2 9807#define regDP0_DP_MSE_SAT0 0x213a 9808#define regDP0_DP_MSE_SAT0_BASE_IDX 2 9809#define regDP0_DP_MSE_SAT1 0x213b 9810#define regDP0_DP_MSE_SAT1_BASE_IDX 2 9811#define regDP0_DP_MSE_SAT2 0x213c 9812#define regDP0_DP_MSE_SAT2_BASE_IDX 2 9813#define regDP0_DP_MSE_SAT_UPDATE 0x213d 9814#define regDP0_DP_MSE_SAT_UPDATE_BASE_IDX 2 9815#define regDP0_DP_MSE_LINK_TIMING 0x213e 9816#define regDP0_DP_MSE_LINK_TIMING_BASE_IDX 2 9817#define regDP0_DP_MSE_MISC_CNTL 0x213f 9818#define regDP0_DP_MSE_MISC_CNTL_BASE_IDX 2 9819#define regDP0_DP_DPHY_BS_SR_SWAP_CNTL 0x2144 9820#define regDP0_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2 9821#define regDP0_DP_DPHY_HBR2_PATTERN_CONTROL 0x2145 9822#define regDP0_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2 9823#define regDP0_DP_MSE_SAT0_STATUS 0x2147 9824#define regDP0_DP_MSE_SAT0_STATUS_BASE_IDX 2 9825#define regDP0_DP_MSE_SAT1_STATUS 0x2148 9826#define regDP0_DP_MSE_SAT1_STATUS_BASE_IDX 2 9827#define regDP0_DP_MSE_SAT2_STATUS 0x2149 9828#define regDP0_DP_MSE_SAT2_STATUS_BASE_IDX 2 9829#define regDP0_DP_MSA_TIMING_PARAM1 0x214c 9830#define regDP0_DP_MSA_TIMING_PARAM1_BASE_IDX 2 9831#define regDP0_DP_MSA_TIMING_PARAM2 0x214d 9832#define regDP0_DP_MSA_TIMING_PARAM2_BASE_IDX 2 9833#define regDP0_DP_MSA_TIMING_PARAM3 0x214e 9834#define regDP0_DP_MSA_TIMING_PARAM3_BASE_IDX 2 9835#define regDP0_DP_MSA_TIMING_PARAM4 0x214f 9836#define regDP0_DP_MSA_TIMING_PARAM4_BASE_IDX 2 9837#define regDP0_DP_MSO_CNTL 0x2150 9838#define regDP0_DP_MSO_CNTL_BASE_IDX 2 9839#define regDP0_DP_MSO_CNTL1 0x2151 9840#define regDP0_DP_MSO_CNTL1_BASE_IDX 2 9841#define regDP0_DP_DSC_CNTL 0x2152 9842#define regDP0_DP_DSC_CNTL_BASE_IDX 2 9843#define regDP0_DP_SEC_CNTL2 0x2153 9844#define regDP0_DP_SEC_CNTL2_BASE_IDX 2 9845#define regDP0_DP_SEC_CNTL3 0x2154 9846#define regDP0_DP_SEC_CNTL3_BASE_IDX 2 9847#define regDP0_DP_SEC_CNTL4 0x2155 9848#define regDP0_DP_SEC_CNTL4_BASE_IDX 2 9849#define regDP0_DP_SEC_CNTL5 0x2156 9850#define regDP0_DP_SEC_CNTL5_BASE_IDX 2 9851#define regDP0_DP_SEC_CNTL6 0x2157 9852#define regDP0_DP_SEC_CNTL6_BASE_IDX 2 9853#define regDP0_DP_SEC_CNTL7 0x2158 9854#define regDP0_DP_SEC_CNTL7_BASE_IDX 2 9855#define regDP0_DP_DB_CNTL 0x2159 9856#define regDP0_DP_DB_CNTL_BASE_IDX 2 9857#define regDP0_DP_MSA_VBID_MISC 0x215a 9858#define regDP0_DP_MSA_VBID_MISC_BASE_IDX 2 9859#define regDP0_DP_SEC_METADATA_TRANSMISSION 0x215b 9860#define regDP0_DP_SEC_METADATA_TRANSMISSION_BASE_IDX 2 9861#define regDP0_DP_DSC_BYTES_PER_PIXEL 0x215c 9862#define regDP0_DP_DSC_BYTES_PER_PIXEL_BASE_IDX 2 9863#define regDP0_DP_ALPM_CNTL 0x215d 9864#define regDP0_DP_ALPM_CNTL_BASE_IDX 2 9865#define regDP0_DP_GSP8_CNTL 0x215e 9866#define regDP0_DP_GSP8_CNTL_BASE_IDX 2 9867#define regDP0_DP_GSP9_CNTL 0x215f 9868#define regDP0_DP_GSP9_CNTL_BASE_IDX 2 9869#define regDP0_DP_GSP10_CNTL 0x2160 9870#define regDP0_DP_GSP10_CNTL_BASE_IDX 2 9871#define regDP0_DP_GSP11_CNTL 0x2161 9872#define regDP0_DP_GSP11_CNTL_BASE_IDX 2 9873#define regDP0_DP_GSP_EN_DB_STATUS 0x2162 9874#define regDP0_DP_GSP_EN_DB_STATUS_BASE_IDX 2 9875 9876 9877// addressBlock: dce_dc_dio_dig0_dispdec 9878// base address: 0x0 9879#define regDIG0_DIG_FE_CNTL 0x208b 9880#define regDIG0_DIG_FE_CNTL_BASE_IDX 2 9881#define regDIG0_DIG_OUTPUT_CRC_CNTL 0x208c 9882#define regDIG0_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2 9883#define regDIG0_DIG_OUTPUT_CRC_RESULT 0x208d 9884#define regDIG0_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2 9885#define regDIG0_DIG_CLOCK_PATTERN 0x208e 9886#define regDIG0_DIG_CLOCK_PATTERN_BASE_IDX 2 9887#define regDIG0_DIG_TEST_PATTERN 0x208f 9888#define regDIG0_DIG_TEST_PATTERN_BASE_IDX 2 9889#define regDIG0_DIG_RANDOM_PATTERN_SEED 0x2090 9890#define regDIG0_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2 9891#define regDIG0_DIG_FIFO_STATUS 0x2091 9892#define regDIG0_DIG_FIFO_STATUS_BASE_IDX 2 9893#define regDIG0_HDMI_METADATA_PACKET_CONTROL 0x2092 9894#define regDIG0_HDMI_METADATA_PACKET_CONTROL_BASE_IDX 2 9895#define regDIG0_HDMI_CONTROL 0x2093 9896#define regDIG0_HDMI_CONTROL_BASE_IDX 2 9897#define regDIG0_HDMI_STATUS 0x2094 9898#define regDIG0_HDMI_STATUS_BASE_IDX 2 9899#define regDIG0_HDMI_AUDIO_PACKET_CONTROL 0x2095 9900#define regDIG0_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2 9901#define regDIG0_HDMI_ACR_PACKET_CONTROL 0x2096 9902#define regDIG0_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2 9903#define regDIG0_HDMI_VBI_PACKET_CONTROL 0x2097 9904#define regDIG0_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2 9905#define regDIG0_HDMI_INFOFRAME_CONTROL0 0x2098 9906#define regDIG0_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2 9907#define regDIG0_HDMI_INFOFRAME_CONTROL1 0x2099 9908#define regDIG0_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2 9909#define regDIG0_HDMI_GENERIC_PACKET_CONTROL0 0x209a 9910#define regDIG0_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2 9911#define regDIG0_HDMI_GENERIC_PACKET_CONTROL6 0x209b 9912#define regDIG0_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX 2 9913#define regDIG0_HDMI_GENERIC_PACKET_CONTROL5 0x209c 9914#define regDIG0_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX 2 9915#define regDIG0_HDMI_GC 0x209d 9916#define regDIG0_HDMI_GC_BASE_IDX 2 9917#define regDIG0_HDMI_GENERIC_PACKET_CONTROL1 0x209e 9918#define regDIG0_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2 9919#define regDIG0_HDMI_GENERIC_PACKET_CONTROL2 0x209f 9920#define regDIG0_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2 9921#define regDIG0_HDMI_GENERIC_PACKET_CONTROL3 0x20a0 9922#define regDIG0_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2 9923#define regDIG0_HDMI_GENERIC_PACKET_CONTROL4 0x20a1 9924#define regDIG0_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX 2 9925#define regDIG0_HDMI_GENERIC_PACKET_CONTROL7 0x20a2 9926#define regDIG0_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX 2 9927#define regDIG0_HDMI_GENERIC_PACKET_CONTROL8 0x20a3 9928#define regDIG0_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX 2 9929#define regDIG0_HDMI_GENERIC_PACKET_CONTROL9 0x20a4 9930#define regDIG0_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX 2 9931#define regDIG0_HDMI_GENERIC_PACKET_CONTROL10 0x20a5 9932#define regDIG0_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX 2 9933#define regDIG0_HDMI_DB_CONTROL 0x20a6 9934#define regDIG0_HDMI_DB_CONTROL_BASE_IDX 2 9935#define regDIG0_HDMI_ACR_32_0 0x20a7 9936#define regDIG0_HDMI_ACR_32_0_BASE_IDX 2 9937#define regDIG0_HDMI_ACR_32_1 0x20a8 9938#define regDIG0_HDMI_ACR_32_1_BASE_IDX 2 9939#define regDIG0_HDMI_ACR_44_0 0x20a9 9940#define regDIG0_HDMI_ACR_44_0_BASE_IDX 2 9941#define regDIG0_HDMI_ACR_44_1 0x20aa 9942#define regDIG0_HDMI_ACR_44_1_BASE_IDX 2 9943#define regDIG0_HDMI_ACR_48_0 0x20ab 9944#define regDIG0_HDMI_ACR_48_0_BASE_IDX 2 9945#define regDIG0_HDMI_ACR_48_1 0x20ac 9946#define regDIG0_HDMI_ACR_48_1_BASE_IDX 2 9947#define regDIG0_HDMI_ACR_STATUS_0 0x20ad 9948#define regDIG0_HDMI_ACR_STATUS_0_BASE_IDX 2 9949#define regDIG0_HDMI_ACR_STATUS_1 0x20ae 9950#define regDIG0_HDMI_ACR_STATUS_1_BASE_IDX 2 9951#define regDIG0_AFMT_CNTL 0x20af 9952#define regDIG0_AFMT_CNTL_BASE_IDX 2 9953#define regDIG0_DIG_BE_CNTL 0x20b0 9954#define regDIG0_DIG_BE_CNTL_BASE_IDX 2 9955#define regDIG0_DIG_BE_EN_CNTL 0x20b1 9956#define regDIG0_DIG_BE_EN_CNTL_BASE_IDX 2 9957#define regDIG0_TMDS_CNTL 0x20d7 9958#define regDIG0_TMDS_CNTL_BASE_IDX 2 9959#define regDIG0_TMDS_CONTROL_CHAR 0x20d8 9960#define regDIG0_TMDS_CONTROL_CHAR_BASE_IDX 2 9961#define regDIG0_TMDS_CONTROL0_FEEDBACK 0x20d9 9962#define regDIG0_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2 9963#define regDIG0_TMDS_STEREOSYNC_CTL_SEL 0x20da 9964#define regDIG0_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2 9965#define regDIG0_TMDS_SYNC_CHAR_PATTERN_0_1 0x20db 9966#define regDIG0_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2 9967#define regDIG0_TMDS_SYNC_CHAR_PATTERN_2_3 0x20dc 9968#define regDIG0_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2 9969#define regDIG0_TMDS_CTL_BITS 0x20de 9970#define regDIG0_TMDS_CTL_BITS_BASE_IDX 2 9971#define regDIG0_TMDS_DCBALANCER_CONTROL 0x20df 9972#define regDIG0_TMDS_DCBALANCER_CONTROL_BASE_IDX 2 9973#define regDIG0_TMDS_SYNC_DCBALANCE_CHAR 0x20e0 9974#define regDIG0_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX 2 9975#define regDIG0_TMDS_CTL0_1_GEN_CNTL 0x20e1 9976#define regDIG0_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2 9977#define regDIG0_TMDS_CTL2_3_GEN_CNTL 0x20e2 9978#define regDIG0_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2 9979#define regDIG0_DIG_VERSION 0x20e4 9980#define regDIG0_DIG_VERSION_BASE_IDX 2 9981#define regDIG0_FORCE_DIG_DISABLE 0x20e5 9982#define regDIG0_FORCE_DIG_DISABLE_BASE_IDX 2 9983 9984 9985// addressBlock: dce_dc_dio_dp1_dispdec 9986// base address: 0x400 9987#define regDP1_DP_LINK_CNTL 0x2208 9988#define regDP1_DP_LINK_CNTL_BASE_IDX 2 9989#define regDP1_DP_PIXEL_FORMAT 0x2209 9990#define regDP1_DP_PIXEL_FORMAT_BASE_IDX 2 9991#define regDP1_DP_MSA_COLORIMETRY 0x220a 9992#define regDP1_DP_MSA_COLORIMETRY_BASE_IDX 2 9993#define regDP1_DP_CONFIG 0x220b 9994#define regDP1_DP_CONFIG_BASE_IDX 2 9995#define regDP1_DP_VID_STREAM_CNTL 0x220c 9996#define regDP1_DP_VID_STREAM_CNTL_BASE_IDX 2 9997#define regDP1_DP_STEER_FIFO 0x220d 9998#define regDP1_DP_STEER_FIFO_BASE_IDX 2 9999#define regDP1_DP_MSA_MISC 0x220e 10000#define regDP1_DP_MSA_MISC_BASE_IDX 2 10001#define regDP1_DP_DPHY_INTERNAL_CTRL 0x220f 10002#define regDP1_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 10003#define regDP1_DP_VID_TIMING 0x2210 10004#define regDP1_DP_VID_TIMING_BASE_IDX 2 10005#define regDP1_DP_VID_N 0x2211 10006#define regDP1_DP_VID_N_BASE_IDX 2 10007#define regDP1_DP_VID_M 0x2212 10008#define regDP1_DP_VID_M_BASE_IDX 2 10009#define regDP1_DP_LINK_FRAMING_CNTL 0x2213 10010#define regDP1_DP_LINK_FRAMING_CNTL_BASE_IDX 2 10011#define regDP1_DP_HBR2_EYE_PATTERN 0x2214 10012#define regDP1_DP_HBR2_EYE_PATTERN_BASE_IDX 2 10013#define regDP1_DP_VID_MSA_VBID 0x2215 10014#define regDP1_DP_VID_MSA_VBID_BASE_IDX 2 10015#define regDP1_DP_VID_INTERRUPT_CNTL 0x2216 10016#define regDP1_DP_VID_INTERRUPT_CNTL_BASE_IDX 2 10017#define regDP1_DP_DPHY_CNTL 0x2217 10018#define regDP1_DP_DPHY_CNTL_BASE_IDX 2 10019#define regDP1_DP_DPHY_TRAINING_PATTERN_SEL 0x2218 10020#define regDP1_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2 10021#define regDP1_DP_DPHY_SYM0 0x2219 10022#define regDP1_DP_DPHY_SYM0_BASE_IDX 2 10023#define regDP1_DP_DPHY_SYM1 0x221a 10024#define regDP1_DP_DPHY_SYM1_BASE_IDX 2 10025#define regDP1_DP_DPHY_SYM2 0x221b 10026#define regDP1_DP_DPHY_SYM2_BASE_IDX 2 10027#define regDP1_DP_DPHY_8B10B_CNTL 0x221c 10028#define regDP1_DP_DPHY_8B10B_CNTL_BASE_IDX 2 10029#define regDP1_DP_DPHY_PRBS_CNTL 0x221d 10030#define regDP1_DP_DPHY_PRBS_CNTL_BASE_IDX 2 10031#define regDP1_DP_DPHY_SCRAM_CNTL 0x221e 10032#define regDP1_DP_DPHY_SCRAM_CNTL_BASE_IDX 2 10033#define regDP1_DP_DPHY_CRC_EN 0x221f 10034#define regDP1_DP_DPHY_CRC_EN_BASE_IDX 2 10035#define regDP1_DP_DPHY_CRC_CNTL 0x2220 10036#define regDP1_DP_DPHY_CRC_CNTL_BASE_IDX 2 10037#define regDP1_DP_DPHY_CRC_RESULT 0x2221 10038#define regDP1_DP_DPHY_CRC_RESULT_BASE_IDX 2 10039#define regDP1_DP_DPHY_CRC_MST_CNTL 0x2222 10040#define regDP1_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2 10041#define regDP1_DP_DPHY_CRC_MST_STATUS 0x2223 10042#define regDP1_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2 10043#define regDP1_DP_DPHY_FAST_TRAINING 0x2224 10044#define regDP1_DP_DPHY_FAST_TRAINING_BASE_IDX 2 10045#define regDP1_DP_DPHY_FAST_TRAINING_STATUS 0x2225 10046#define regDP1_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2 10047#define regDP1_DP_SEC_CNTL 0x222b 10048#define regDP1_DP_SEC_CNTL_BASE_IDX 2 10049#define regDP1_DP_SEC_CNTL1 0x222c 10050#define regDP1_DP_SEC_CNTL1_BASE_IDX 2 10051#define regDP1_DP_SEC_FRAMING1 0x222d 10052#define regDP1_DP_SEC_FRAMING1_BASE_IDX 2 10053#define regDP1_DP_SEC_FRAMING2 0x222e 10054#define regDP1_DP_SEC_FRAMING2_BASE_IDX 2 10055#define regDP1_DP_SEC_FRAMING3 0x222f 10056#define regDP1_DP_SEC_FRAMING3_BASE_IDX 2 10057#define regDP1_DP_SEC_FRAMING4 0x2230 10058#define regDP1_DP_SEC_FRAMING4_BASE_IDX 2 10059#define regDP1_DP_SEC_AUD_N 0x2231 10060#define regDP1_DP_SEC_AUD_N_BASE_IDX 2 10061#define regDP1_DP_SEC_AUD_N_READBACK 0x2232 10062#define regDP1_DP_SEC_AUD_N_READBACK_BASE_IDX 2 10063#define regDP1_DP_SEC_AUD_M 0x2233 10064#define regDP1_DP_SEC_AUD_M_BASE_IDX 2 10065#define regDP1_DP_SEC_AUD_M_READBACK 0x2234 10066#define regDP1_DP_SEC_AUD_M_READBACK_BASE_IDX 2 10067#define regDP1_DP_SEC_TIMESTAMP 0x2235 10068#define regDP1_DP_SEC_TIMESTAMP_BASE_IDX 2 10069#define regDP1_DP_SEC_PACKET_CNTL 0x2236 10070#define regDP1_DP_SEC_PACKET_CNTL_BASE_IDX 2 10071#define regDP1_DP_MSE_RATE_CNTL 0x2237 10072#define regDP1_DP_MSE_RATE_CNTL_BASE_IDX 2 10073#define regDP1_DP_MSE_RATE_UPDATE 0x2239 10074#define regDP1_DP_MSE_RATE_UPDATE_BASE_IDX 2 10075#define regDP1_DP_MSE_SAT0 0x223a 10076#define regDP1_DP_MSE_SAT0_BASE_IDX 2 10077#define regDP1_DP_MSE_SAT1 0x223b 10078#define regDP1_DP_MSE_SAT1_BASE_IDX 2 10079#define regDP1_DP_MSE_SAT2 0x223c 10080#define regDP1_DP_MSE_SAT2_BASE_IDX 2 10081#define regDP1_DP_MSE_SAT_UPDATE 0x223d 10082#define regDP1_DP_MSE_SAT_UPDATE_BASE_IDX 2 10083#define regDP1_DP_MSE_LINK_TIMING 0x223e 10084#define regDP1_DP_MSE_LINK_TIMING_BASE_IDX 2 10085#define regDP1_DP_MSE_MISC_CNTL 0x223f 10086#define regDP1_DP_MSE_MISC_CNTL_BASE_IDX 2 10087#define regDP1_DP_DPHY_BS_SR_SWAP_CNTL 0x2244 10088#define regDP1_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2 10089#define regDP1_DP_DPHY_HBR2_PATTERN_CONTROL 0x2245 10090#define regDP1_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2 10091#define regDP1_DP_MSE_SAT0_STATUS 0x2247 10092#define regDP1_DP_MSE_SAT0_STATUS_BASE_IDX 2 10093#define regDP1_DP_MSE_SAT1_STATUS 0x2248 10094#define regDP1_DP_MSE_SAT1_STATUS_BASE_IDX 2 10095#define regDP1_DP_MSE_SAT2_STATUS 0x2249 10096#define regDP1_DP_MSE_SAT2_STATUS_BASE_IDX 2 10097#define regDP1_DP_MSA_TIMING_PARAM1 0x224c 10098#define regDP1_DP_MSA_TIMING_PARAM1_BASE_IDX 2 10099#define regDP1_DP_MSA_TIMING_PARAM2 0x224d 10100#define regDP1_DP_MSA_TIMING_PARAM2_BASE_IDX 2 10101#define regDP1_DP_MSA_TIMING_PARAM3 0x224e 10102#define regDP1_DP_MSA_TIMING_PARAM3_BASE_IDX 2 10103#define regDP1_DP_MSA_TIMING_PARAM4 0x224f 10104#define regDP1_DP_MSA_TIMING_PARAM4_BASE_IDX 2 10105#define regDP1_DP_MSO_CNTL 0x2250 10106#define regDP1_DP_MSO_CNTL_BASE_IDX 2 10107#define regDP1_DP_MSO_CNTL1 0x2251 10108#define regDP1_DP_MSO_CNTL1_BASE_IDX 2 10109#define regDP1_DP_DSC_CNTL 0x2252 10110#define regDP1_DP_DSC_CNTL_BASE_IDX 2 10111#define regDP1_DP_SEC_CNTL2 0x2253 10112#define regDP1_DP_SEC_CNTL2_BASE_IDX 2 10113#define regDP1_DP_SEC_CNTL3 0x2254 10114#define regDP1_DP_SEC_CNTL3_BASE_IDX 2 10115#define regDP1_DP_SEC_CNTL4 0x2255 10116#define regDP1_DP_SEC_CNTL4_BASE_IDX 2 10117#define regDP1_DP_SEC_CNTL5 0x2256 10118#define regDP1_DP_SEC_CNTL5_BASE_IDX 2 10119#define regDP1_DP_SEC_CNTL6 0x2257 10120#define regDP1_DP_SEC_CNTL6_BASE_IDX 2 10121#define regDP1_DP_SEC_CNTL7 0x2258 10122#define regDP1_DP_SEC_CNTL7_BASE_IDX 2 10123#define regDP1_DP_DB_CNTL 0x2259 10124#define regDP1_DP_DB_CNTL_BASE_IDX 2 10125#define regDP1_DP_MSA_VBID_MISC 0x225a 10126#define regDP1_DP_MSA_VBID_MISC_BASE_IDX 2 10127#define regDP1_DP_SEC_METADATA_TRANSMISSION 0x225b 10128#define regDP1_DP_SEC_METADATA_TRANSMISSION_BASE_IDX 2 10129#define regDP1_DP_DSC_BYTES_PER_PIXEL 0x225c 10130#define regDP1_DP_DSC_BYTES_PER_PIXEL_BASE_IDX 2 10131#define regDP1_DP_ALPM_CNTL 0x225d 10132#define regDP1_DP_ALPM_CNTL_BASE_IDX 2 10133#define regDP1_DP_GSP8_CNTL 0x225e 10134#define regDP1_DP_GSP8_CNTL_BASE_IDX 2 10135#define regDP1_DP_GSP9_CNTL 0x225f 10136#define regDP1_DP_GSP9_CNTL_BASE_IDX 2 10137#define regDP1_DP_GSP10_CNTL 0x2260 10138#define regDP1_DP_GSP10_CNTL_BASE_IDX 2 10139#define regDP1_DP_GSP11_CNTL 0x2261 10140#define regDP1_DP_GSP11_CNTL_BASE_IDX 2 10141#define regDP1_DP_GSP_EN_DB_STATUS 0x2262 10142#define regDP1_DP_GSP_EN_DB_STATUS_BASE_IDX 2 10143 10144 10145// addressBlock: dce_dc_dio_dig1_dispdec 10146// base address: 0x400 10147#define regDIG1_DIG_FE_CNTL 0x218b 10148#define regDIG1_DIG_FE_CNTL_BASE_IDX 2 10149#define regDIG1_DIG_OUTPUT_CRC_CNTL 0x218c 10150#define regDIG1_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2 10151#define regDIG1_DIG_OUTPUT_CRC_RESULT 0x218d 10152#define regDIG1_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2 10153#define regDIG1_DIG_CLOCK_PATTERN 0x218e 10154#define regDIG1_DIG_CLOCK_PATTERN_BASE_IDX 2 10155#define regDIG1_DIG_TEST_PATTERN 0x218f 10156#define regDIG1_DIG_TEST_PATTERN_BASE_IDX 2 10157#define regDIG1_DIG_RANDOM_PATTERN_SEED 0x2190 10158#define regDIG1_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2 10159#define regDIG1_DIG_FIFO_STATUS 0x2191 10160#define regDIG1_DIG_FIFO_STATUS_BASE_IDX 2 10161#define regDIG1_HDMI_METADATA_PACKET_CONTROL 0x2192 10162#define regDIG1_HDMI_METADATA_PACKET_CONTROL_BASE_IDX 2 10163#define regDIG1_HDMI_CONTROL 0x2193 10164#define regDIG1_HDMI_CONTROL_BASE_IDX 2 10165#define regDIG1_HDMI_STATUS 0x2194 10166#define regDIG1_HDMI_STATUS_BASE_IDX 2 10167#define regDIG1_HDMI_AUDIO_PACKET_CONTROL 0x2195 10168#define regDIG1_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2 10169#define regDIG1_HDMI_ACR_PACKET_CONTROL 0x2196 10170#define regDIG1_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2 10171#define regDIG1_HDMI_VBI_PACKET_CONTROL 0x2197 10172#define regDIG1_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2 10173#define regDIG1_HDMI_INFOFRAME_CONTROL0 0x2198 10174#define regDIG1_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2 10175#define regDIG1_HDMI_INFOFRAME_CONTROL1 0x2199 10176#define regDIG1_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2 10177#define regDIG1_HDMI_GENERIC_PACKET_CONTROL0 0x219a 10178#define regDIG1_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2 10179#define regDIG1_HDMI_GENERIC_PACKET_CONTROL6 0x219b 10180#define regDIG1_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX 2 10181#define regDIG1_HDMI_GENERIC_PACKET_CONTROL5 0x219c 10182#define regDIG1_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX 2 10183#define regDIG1_HDMI_GC 0x219d 10184#define regDIG1_HDMI_GC_BASE_IDX 2 10185#define regDIG1_HDMI_GENERIC_PACKET_CONTROL1 0x219e 10186#define regDIG1_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2 10187#define regDIG1_HDMI_GENERIC_PACKET_CONTROL2 0x219f 10188#define regDIG1_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2 10189#define regDIG1_HDMI_GENERIC_PACKET_CONTROL3 0x21a0 10190#define regDIG1_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2 10191#define regDIG1_HDMI_GENERIC_PACKET_CONTROL4 0x21a1 10192#define regDIG1_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX 2 10193#define regDIG1_HDMI_GENERIC_PACKET_CONTROL7 0x21a2 10194#define regDIG1_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX 2 10195#define regDIG1_HDMI_GENERIC_PACKET_CONTROL8 0x21a3 10196#define regDIG1_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX 2 10197#define regDIG1_HDMI_GENERIC_PACKET_CONTROL9 0x21a4 10198#define regDIG1_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX 2 10199#define regDIG1_HDMI_GENERIC_PACKET_CONTROL10 0x21a5 10200#define regDIG1_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX 2 10201#define regDIG1_HDMI_DB_CONTROL 0x21a6 10202#define regDIG1_HDMI_DB_CONTROL_BASE_IDX 2 10203#define regDIG1_HDMI_ACR_32_0 0x21a7 10204#define regDIG1_HDMI_ACR_32_0_BASE_IDX 2 10205#define regDIG1_HDMI_ACR_32_1 0x21a8 10206#define regDIG1_HDMI_ACR_32_1_BASE_IDX 2 10207#define regDIG1_HDMI_ACR_44_0 0x21a9 10208#define regDIG1_HDMI_ACR_44_0_BASE_IDX 2 10209#define regDIG1_HDMI_ACR_44_1 0x21aa 10210#define regDIG1_HDMI_ACR_44_1_BASE_IDX 2 10211#define regDIG1_HDMI_ACR_48_0 0x21ab 10212#define regDIG1_HDMI_ACR_48_0_BASE_IDX 2 10213#define regDIG1_HDMI_ACR_48_1 0x21ac 10214#define regDIG1_HDMI_ACR_48_1_BASE_IDX 2 10215#define regDIG1_HDMI_ACR_STATUS_0 0x21ad 10216#define regDIG1_HDMI_ACR_STATUS_0_BASE_IDX 2 10217#define regDIG1_HDMI_ACR_STATUS_1 0x21ae 10218#define regDIG1_HDMI_ACR_STATUS_1_BASE_IDX 2 10219#define regDIG1_AFMT_CNTL 0x21af 10220#define regDIG1_AFMT_CNTL_BASE_IDX 2 10221#define regDIG1_DIG_BE_CNTL 0x21b0 10222#define regDIG1_DIG_BE_CNTL_BASE_IDX 2 10223#define regDIG1_DIG_BE_EN_CNTL 0x21b1 10224#define regDIG1_DIG_BE_EN_CNTL_BASE_IDX 2 10225#define regDIG1_TMDS_CNTL 0x21d7 10226#define regDIG1_TMDS_CNTL_BASE_IDX 2 10227#define regDIG1_TMDS_CONTROL_CHAR 0x21d8 10228#define regDIG1_TMDS_CONTROL_CHAR_BASE_IDX 2 10229#define regDIG1_TMDS_CONTROL0_FEEDBACK 0x21d9 10230#define regDIG1_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2 10231#define regDIG1_TMDS_STEREOSYNC_CTL_SEL 0x21da 10232#define regDIG1_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2 10233#define regDIG1_TMDS_SYNC_CHAR_PATTERN_0_1 0x21db 10234#define regDIG1_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2 10235#define regDIG1_TMDS_SYNC_CHAR_PATTERN_2_3 0x21dc 10236#define regDIG1_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2 10237#define regDIG1_TMDS_CTL_BITS 0x21de 10238#define regDIG1_TMDS_CTL_BITS_BASE_IDX 2 10239#define regDIG1_TMDS_DCBALANCER_CONTROL 0x21df 10240#define regDIG1_TMDS_DCBALANCER_CONTROL_BASE_IDX 2 10241#define regDIG1_TMDS_SYNC_DCBALANCE_CHAR 0x21e0 10242#define regDIG1_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX 2 10243#define regDIG1_TMDS_CTL0_1_GEN_CNTL 0x21e1 10244#define regDIG1_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2 10245#define regDIG1_TMDS_CTL2_3_GEN_CNTL 0x21e2 10246#define regDIG1_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2 10247#define regDIG1_DIG_VERSION 0x21e4 10248#define regDIG1_DIG_VERSION_BASE_IDX 2 10249#define regDIG1_FORCE_DIG_DISABLE 0x21e5 10250#define regDIG1_FORCE_DIG_DISABLE_BASE_IDX 2 10251 10252 10253// addressBlock: dce_dc_dio_dp2_dispdec 10254// base address: 0x800 10255#define regDP2_DP_LINK_CNTL 0x2308 10256#define regDP2_DP_LINK_CNTL_BASE_IDX 2 10257#define regDP2_DP_PIXEL_FORMAT 0x2309 10258#define regDP2_DP_PIXEL_FORMAT_BASE_IDX 2 10259#define regDP2_DP_MSA_COLORIMETRY 0x230a 10260#define regDP2_DP_MSA_COLORIMETRY_BASE_IDX 2 10261#define regDP2_DP_CONFIG 0x230b 10262#define regDP2_DP_CONFIG_BASE_IDX 2 10263#define regDP2_DP_VID_STREAM_CNTL 0x230c 10264#define regDP2_DP_VID_STREAM_CNTL_BASE_IDX 2 10265#define regDP2_DP_STEER_FIFO 0x230d 10266#define regDP2_DP_STEER_FIFO_BASE_IDX 2 10267#define regDP2_DP_MSA_MISC 0x230e 10268#define regDP2_DP_MSA_MISC_BASE_IDX 2 10269#define regDP2_DP_DPHY_INTERNAL_CTRL 0x230f 10270#define regDP2_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 10271#define regDP2_DP_VID_TIMING 0x2310 10272#define regDP2_DP_VID_TIMING_BASE_IDX 2 10273#define regDP2_DP_VID_N 0x2311 10274#define regDP2_DP_VID_N_BASE_IDX 2 10275#define regDP2_DP_VID_M 0x2312 10276#define regDP2_DP_VID_M_BASE_IDX 2 10277#define regDP2_DP_LINK_FRAMING_CNTL 0x2313 10278#define regDP2_DP_LINK_FRAMING_CNTL_BASE_IDX 2 10279#define regDP2_DP_HBR2_EYE_PATTERN 0x2314 10280#define regDP2_DP_HBR2_EYE_PATTERN_BASE_IDX 2 10281#define regDP2_DP_VID_MSA_VBID 0x2315 10282#define regDP2_DP_VID_MSA_VBID_BASE_IDX 2 10283#define regDP2_DP_VID_INTERRUPT_CNTL 0x2316 10284#define regDP2_DP_VID_INTERRUPT_CNTL_BASE_IDX 2 10285#define regDP2_DP_DPHY_CNTL 0x2317 10286#define regDP2_DP_DPHY_CNTL_BASE_IDX 2 10287#define regDP2_DP_DPHY_TRAINING_PATTERN_SEL 0x2318 10288#define regDP2_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2 10289#define regDP2_DP_DPHY_SYM0 0x2319 10290#define regDP2_DP_DPHY_SYM0_BASE_IDX 2 10291#define regDP2_DP_DPHY_SYM1 0x231a 10292#define regDP2_DP_DPHY_SYM1_BASE_IDX 2 10293#define regDP2_DP_DPHY_SYM2 0x231b 10294#define regDP2_DP_DPHY_SYM2_BASE_IDX 2 10295#define regDP2_DP_DPHY_8B10B_CNTL 0x231c 10296#define regDP2_DP_DPHY_8B10B_CNTL_BASE_IDX 2 10297#define regDP2_DP_DPHY_PRBS_CNTL 0x231d 10298#define regDP2_DP_DPHY_PRBS_CNTL_BASE_IDX 2 10299#define regDP2_DP_DPHY_SCRAM_CNTL 0x231e 10300#define regDP2_DP_DPHY_SCRAM_CNTL_BASE_IDX 2 10301#define regDP2_DP_DPHY_CRC_EN 0x231f 10302#define regDP2_DP_DPHY_CRC_EN_BASE_IDX 2 10303#define regDP2_DP_DPHY_CRC_CNTL 0x2320 10304#define regDP2_DP_DPHY_CRC_CNTL_BASE_IDX 2 10305#define regDP2_DP_DPHY_CRC_RESULT 0x2321 10306#define regDP2_DP_DPHY_CRC_RESULT_BASE_IDX 2 10307#define regDP2_DP_DPHY_CRC_MST_CNTL 0x2322 10308#define regDP2_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2 10309#define regDP2_DP_DPHY_CRC_MST_STATUS 0x2323 10310#define regDP2_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2 10311#define regDP2_DP_DPHY_FAST_TRAINING 0x2324 10312#define regDP2_DP_DPHY_FAST_TRAINING_BASE_IDX 2 10313#define regDP2_DP_DPHY_FAST_TRAINING_STATUS 0x2325 10314#define regDP2_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2 10315#define regDP2_DP_SEC_CNTL 0x232b 10316#define regDP2_DP_SEC_CNTL_BASE_IDX 2 10317#define regDP2_DP_SEC_CNTL1 0x232c 10318#define regDP2_DP_SEC_CNTL1_BASE_IDX 2 10319#define regDP2_DP_SEC_FRAMING1 0x232d 10320#define regDP2_DP_SEC_FRAMING1_BASE_IDX 2 10321#define regDP2_DP_SEC_FRAMING2 0x232e 10322#define regDP2_DP_SEC_FRAMING2_BASE_IDX 2 10323#define regDP2_DP_SEC_FRAMING3 0x232f 10324#define regDP2_DP_SEC_FRAMING3_BASE_IDX 2 10325#define regDP2_DP_SEC_FRAMING4 0x2330 10326#define regDP2_DP_SEC_FRAMING4_BASE_IDX 2 10327#define regDP2_DP_SEC_AUD_N 0x2331 10328#define regDP2_DP_SEC_AUD_N_BASE_IDX 2 10329#define regDP2_DP_SEC_AUD_N_READBACK 0x2332 10330#define regDP2_DP_SEC_AUD_N_READBACK_BASE_IDX 2 10331#define regDP2_DP_SEC_AUD_M 0x2333 10332#define regDP2_DP_SEC_AUD_M_BASE_IDX 2 10333#define regDP2_DP_SEC_AUD_M_READBACK 0x2334 10334#define regDP2_DP_SEC_AUD_M_READBACK_BASE_IDX 2 10335#define regDP2_DP_SEC_TIMESTAMP 0x2335 10336#define regDP2_DP_SEC_TIMESTAMP_BASE_IDX 2 10337#define regDP2_DP_SEC_PACKET_CNTL 0x2336 10338#define regDP2_DP_SEC_PACKET_CNTL_BASE_IDX 2 10339#define regDP2_DP_MSE_RATE_CNTL 0x2337 10340#define regDP2_DP_MSE_RATE_CNTL_BASE_IDX 2 10341#define regDP2_DP_MSE_RATE_UPDATE 0x2339 10342#define regDP2_DP_MSE_RATE_UPDATE_BASE_IDX 2 10343#define regDP2_DP_MSE_SAT0 0x233a 10344#define regDP2_DP_MSE_SAT0_BASE_IDX 2 10345#define regDP2_DP_MSE_SAT1 0x233b 10346#define regDP2_DP_MSE_SAT1_BASE_IDX 2 10347#define regDP2_DP_MSE_SAT2 0x233c 10348#define regDP2_DP_MSE_SAT2_BASE_IDX 2 10349#define regDP2_DP_MSE_SAT_UPDATE 0x233d 10350#define regDP2_DP_MSE_SAT_UPDATE_BASE_IDX 2 10351#define regDP2_DP_MSE_LINK_TIMING 0x233e 10352#define regDP2_DP_MSE_LINK_TIMING_BASE_IDX 2 10353#define regDP2_DP_MSE_MISC_CNTL 0x233f 10354#define regDP2_DP_MSE_MISC_CNTL_BASE_IDX 2 10355#define regDP2_DP_DPHY_BS_SR_SWAP_CNTL 0x2344 10356#define regDP2_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2 10357#define regDP2_DP_DPHY_HBR2_PATTERN_CONTROL 0x2345 10358#define regDP2_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2 10359#define regDP2_DP_MSE_SAT0_STATUS 0x2347 10360#define regDP2_DP_MSE_SAT0_STATUS_BASE_IDX 2 10361#define regDP2_DP_MSE_SAT1_STATUS 0x2348 10362#define regDP2_DP_MSE_SAT1_STATUS_BASE_IDX 2 10363#define regDP2_DP_MSE_SAT2_STATUS 0x2349 10364#define regDP2_DP_MSE_SAT2_STATUS_BASE_IDX 2 10365#define regDP2_DP_MSA_TIMING_PARAM1 0x234c 10366#define regDP2_DP_MSA_TIMING_PARAM1_BASE_IDX 2 10367#define regDP2_DP_MSA_TIMING_PARAM2 0x234d 10368#define regDP2_DP_MSA_TIMING_PARAM2_BASE_IDX 2 10369#define regDP2_DP_MSA_TIMING_PARAM3 0x234e 10370#define regDP2_DP_MSA_TIMING_PARAM3_BASE_IDX 2 10371#define regDP2_DP_MSA_TIMING_PARAM4 0x234f 10372#define regDP2_DP_MSA_TIMING_PARAM4_BASE_IDX 2 10373#define regDP2_DP_MSO_CNTL 0x2350 10374#define regDP2_DP_MSO_CNTL_BASE_IDX 2 10375#define regDP2_DP_MSO_CNTL1 0x2351 10376#define regDP2_DP_MSO_CNTL1_BASE_IDX 2 10377#define regDP2_DP_DSC_CNTL 0x2352 10378#define regDP2_DP_DSC_CNTL_BASE_IDX 2 10379#define regDP2_DP_SEC_CNTL2 0x2353 10380#define regDP2_DP_SEC_CNTL2_BASE_IDX 2 10381#define regDP2_DP_SEC_CNTL3 0x2354 10382#define regDP2_DP_SEC_CNTL3_BASE_IDX 2 10383#define regDP2_DP_SEC_CNTL4 0x2355 10384#define regDP2_DP_SEC_CNTL4_BASE_IDX 2 10385#define regDP2_DP_SEC_CNTL5 0x2356 10386#define regDP2_DP_SEC_CNTL5_BASE_IDX 2 10387#define regDP2_DP_SEC_CNTL6 0x2357 10388#define regDP2_DP_SEC_CNTL6_BASE_IDX 2 10389#define regDP2_DP_SEC_CNTL7 0x2358 10390#define regDP2_DP_SEC_CNTL7_BASE_IDX 2 10391#define regDP2_DP_DB_CNTL 0x2359 10392#define regDP2_DP_DB_CNTL_BASE_IDX 2 10393#define regDP2_DP_MSA_VBID_MISC 0x235a 10394#define regDP2_DP_MSA_VBID_MISC_BASE_IDX 2 10395#define regDP2_DP_SEC_METADATA_TRANSMISSION 0x235b 10396#define regDP2_DP_SEC_METADATA_TRANSMISSION_BASE_IDX 2 10397#define regDP2_DP_DSC_BYTES_PER_PIXEL 0x235c 10398#define regDP2_DP_DSC_BYTES_PER_PIXEL_BASE_IDX 2 10399#define regDP2_DP_ALPM_CNTL 0x235d 10400#define regDP2_DP_ALPM_CNTL_BASE_IDX 2 10401#define regDP2_DP_GSP8_CNTL 0x235e 10402#define regDP2_DP_GSP8_CNTL_BASE_IDX 2 10403#define regDP2_DP_GSP9_CNTL 0x235f 10404#define regDP2_DP_GSP9_CNTL_BASE_IDX 2 10405#define regDP2_DP_GSP10_CNTL 0x2360 10406#define regDP2_DP_GSP10_CNTL_BASE_IDX 2 10407#define regDP2_DP_GSP11_CNTL 0x2361 10408#define regDP2_DP_GSP11_CNTL_BASE_IDX 2 10409#define regDP2_DP_GSP_EN_DB_STATUS 0x2362 10410#define regDP2_DP_GSP_EN_DB_STATUS_BASE_IDX 2 10411 10412 10413// addressBlock: dce_dc_dio_dig2_dispdec 10414// base address: 0x800 10415#define regDIG2_DIG_FE_CNTL 0x228b 10416#define regDIG2_DIG_FE_CNTL_BASE_IDX 2 10417#define regDIG2_DIG_OUTPUT_CRC_CNTL 0x228c 10418#define regDIG2_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2 10419#define regDIG2_DIG_OUTPUT_CRC_RESULT 0x228d 10420#define regDIG2_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2 10421#define regDIG2_DIG_CLOCK_PATTERN 0x228e 10422#define regDIG2_DIG_CLOCK_PATTERN_BASE_IDX 2 10423#define regDIG2_DIG_TEST_PATTERN 0x228f 10424#define regDIG2_DIG_TEST_PATTERN_BASE_IDX 2 10425#define regDIG2_DIG_RANDOM_PATTERN_SEED 0x2290 10426#define regDIG2_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2 10427#define regDIG2_DIG_FIFO_STATUS 0x2291 10428#define regDIG2_DIG_FIFO_STATUS_BASE_IDX 2 10429#define regDIG2_HDMI_METADATA_PACKET_CONTROL 0x2292 10430#define regDIG2_HDMI_METADATA_PACKET_CONTROL_BASE_IDX 2 10431#define regDIG2_HDMI_CONTROL 0x2293 10432#define regDIG2_HDMI_CONTROL_BASE_IDX 2 10433#define regDIG2_HDMI_STATUS 0x2294 10434#define regDIG2_HDMI_STATUS_BASE_IDX 2 10435#define regDIG2_HDMI_AUDIO_PACKET_CONTROL 0x2295 10436#define regDIG2_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2 10437#define regDIG2_HDMI_ACR_PACKET_CONTROL 0x2296 10438#define regDIG2_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2 10439#define regDIG2_HDMI_VBI_PACKET_CONTROL 0x2297 10440#define regDIG2_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2 10441#define regDIG2_HDMI_INFOFRAME_CONTROL0 0x2298 10442#define regDIG2_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2 10443#define regDIG2_HDMI_INFOFRAME_CONTROL1 0x2299 10444#define regDIG2_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2 10445#define regDIG2_HDMI_GENERIC_PACKET_CONTROL0 0x229a 10446#define regDIG2_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2 10447#define regDIG2_HDMI_GENERIC_PACKET_CONTROL6 0x229b 10448#define regDIG2_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX 2 10449#define regDIG2_HDMI_GENERIC_PACKET_CONTROL5 0x229c 10450#define regDIG2_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX 2 10451#define regDIG2_HDMI_GC 0x229d 10452#define regDIG2_HDMI_GC_BASE_IDX 2 10453#define regDIG2_HDMI_GENERIC_PACKET_CONTROL1 0x229e 10454#define regDIG2_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2 10455#define regDIG2_HDMI_GENERIC_PACKET_CONTROL2 0x229f 10456#define regDIG2_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2 10457#define regDIG2_HDMI_GENERIC_PACKET_CONTROL3 0x22a0 10458#define regDIG2_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2 10459#define regDIG2_HDMI_GENERIC_PACKET_CONTROL4 0x22a1 10460#define regDIG2_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX 2 10461#define regDIG2_HDMI_GENERIC_PACKET_CONTROL7 0x22a2 10462#define regDIG2_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX 2 10463#define regDIG2_HDMI_GENERIC_PACKET_CONTROL8 0x22a3 10464#define regDIG2_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX 2 10465#define regDIG2_HDMI_GENERIC_PACKET_CONTROL9 0x22a4 10466#define regDIG2_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX 2 10467#define regDIG2_HDMI_GENERIC_PACKET_CONTROL10 0x22a5 10468#define regDIG2_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX 2 10469#define regDIG2_HDMI_DB_CONTROL 0x22a6 10470#define regDIG2_HDMI_DB_CONTROL_BASE_IDX 2 10471#define regDIG2_HDMI_ACR_32_0 0x22a7 10472#define regDIG2_HDMI_ACR_32_0_BASE_IDX 2 10473#define regDIG2_HDMI_ACR_32_1 0x22a8 10474#define regDIG2_HDMI_ACR_32_1_BASE_IDX 2 10475#define regDIG2_HDMI_ACR_44_0 0x22a9 10476#define regDIG2_HDMI_ACR_44_0_BASE_IDX 2 10477#define regDIG2_HDMI_ACR_44_1 0x22aa 10478#define regDIG2_HDMI_ACR_44_1_BASE_IDX 2 10479#define regDIG2_HDMI_ACR_48_0 0x22ab 10480#define regDIG2_HDMI_ACR_48_0_BASE_IDX 2 10481#define regDIG2_HDMI_ACR_48_1 0x22ac 10482#define regDIG2_HDMI_ACR_48_1_BASE_IDX 2 10483#define regDIG2_HDMI_ACR_STATUS_0 0x22ad 10484#define regDIG2_HDMI_ACR_STATUS_0_BASE_IDX 2 10485#define regDIG2_HDMI_ACR_STATUS_1 0x22ae 10486#define regDIG2_HDMI_ACR_STATUS_1_BASE_IDX 2 10487#define regDIG2_AFMT_CNTL 0x22af 10488#define regDIG2_AFMT_CNTL_BASE_IDX 2 10489#define regDIG2_DIG_BE_CNTL 0x22b0 10490#define regDIG2_DIG_BE_CNTL_BASE_IDX 2 10491#define regDIG2_DIG_BE_EN_CNTL 0x22b1 10492#define regDIG2_DIG_BE_EN_CNTL_BASE_IDX 2 10493#define regDIG2_TMDS_CNTL 0x22d7 10494#define regDIG2_TMDS_CNTL_BASE_IDX 2 10495#define regDIG2_TMDS_CONTROL_CHAR 0x22d8 10496#define regDIG2_TMDS_CONTROL_CHAR_BASE_IDX 2 10497#define regDIG2_TMDS_CONTROL0_FEEDBACK 0x22d9 10498#define regDIG2_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2 10499#define regDIG2_TMDS_STEREOSYNC_CTL_SEL 0x22da 10500#define regDIG2_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2 10501#define regDIG2_TMDS_SYNC_CHAR_PATTERN_0_1 0x22db 10502#define regDIG2_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2 10503#define regDIG2_TMDS_SYNC_CHAR_PATTERN_2_3 0x22dc 10504#define regDIG2_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2 10505#define regDIG2_TMDS_CTL_BITS 0x22de 10506#define regDIG2_TMDS_CTL_BITS_BASE_IDX 2 10507#define regDIG2_TMDS_DCBALANCER_CONTROL 0x22df 10508#define regDIG2_TMDS_DCBALANCER_CONTROL_BASE_IDX 2 10509#define regDIG2_TMDS_SYNC_DCBALANCE_CHAR 0x22e0 10510#define regDIG2_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX 2 10511#define regDIG2_TMDS_CTL0_1_GEN_CNTL 0x22e1 10512#define regDIG2_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2 10513#define regDIG2_TMDS_CTL2_3_GEN_CNTL 0x22e2 10514#define regDIG2_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2 10515#define regDIG2_DIG_VERSION 0x22e4 10516#define regDIG2_DIG_VERSION_BASE_IDX 2 10517#define regDIG2_FORCE_DIG_DISABLE 0x22e5 10518#define regDIG2_FORCE_DIG_DISABLE_BASE_IDX 2 10519 10520 10521// addressBlock: dce_dc_dio_dp3_dispdec 10522// base address: 0xc00 10523#define regDP3_DP_LINK_CNTL 0x2408 10524#define regDP3_DP_LINK_CNTL_BASE_IDX 2 10525#define regDP3_DP_PIXEL_FORMAT 0x2409 10526#define regDP3_DP_PIXEL_FORMAT_BASE_IDX 2 10527#define regDP3_DP_MSA_COLORIMETRY 0x240a 10528#define regDP3_DP_MSA_COLORIMETRY_BASE_IDX 2 10529#define regDP3_DP_CONFIG 0x240b 10530#define regDP3_DP_CONFIG_BASE_IDX 2 10531#define regDP3_DP_VID_STREAM_CNTL 0x240c 10532#define regDP3_DP_VID_STREAM_CNTL_BASE_IDX 2 10533#define regDP3_DP_STEER_FIFO 0x240d 10534#define regDP3_DP_STEER_FIFO_BASE_IDX 2 10535#define regDP3_DP_MSA_MISC 0x240e 10536#define regDP3_DP_MSA_MISC_BASE_IDX 2 10537#define regDP3_DP_DPHY_INTERNAL_CTRL 0x240f 10538#define regDP3_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 10539#define regDP3_DP_VID_TIMING 0x2410 10540#define regDP3_DP_VID_TIMING_BASE_IDX 2 10541#define regDP3_DP_VID_N 0x2411 10542#define regDP3_DP_VID_N_BASE_IDX 2 10543#define regDP3_DP_VID_M 0x2412 10544#define regDP3_DP_VID_M_BASE_IDX 2 10545#define regDP3_DP_LINK_FRAMING_CNTL 0x2413 10546#define regDP3_DP_LINK_FRAMING_CNTL_BASE_IDX 2 10547#define regDP3_DP_HBR2_EYE_PATTERN 0x2414 10548#define regDP3_DP_HBR2_EYE_PATTERN_BASE_IDX 2 10549#define regDP3_DP_VID_MSA_VBID 0x2415 10550#define regDP3_DP_VID_MSA_VBID_BASE_IDX 2 10551#define regDP3_DP_VID_INTERRUPT_CNTL 0x2416 10552#define regDP3_DP_VID_INTERRUPT_CNTL_BASE_IDX 2 10553#define regDP3_DP_DPHY_CNTL 0x2417 10554#define regDP3_DP_DPHY_CNTL_BASE_IDX 2 10555#define regDP3_DP_DPHY_TRAINING_PATTERN_SEL 0x2418 10556#define regDP3_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2 10557#define regDP3_DP_DPHY_SYM0 0x2419 10558#define regDP3_DP_DPHY_SYM0_BASE_IDX 2 10559#define regDP3_DP_DPHY_SYM1 0x241a 10560#define regDP3_DP_DPHY_SYM1_BASE_IDX 2 10561#define regDP3_DP_DPHY_SYM2 0x241b 10562#define regDP3_DP_DPHY_SYM2_BASE_IDX 2 10563#define regDP3_DP_DPHY_8B10B_CNTL 0x241c 10564#define regDP3_DP_DPHY_8B10B_CNTL_BASE_IDX 2 10565#define regDP3_DP_DPHY_PRBS_CNTL 0x241d 10566#define regDP3_DP_DPHY_PRBS_CNTL_BASE_IDX 2 10567#define regDP3_DP_DPHY_SCRAM_CNTL 0x241e 10568#define regDP3_DP_DPHY_SCRAM_CNTL_BASE_IDX 2 10569#define regDP3_DP_DPHY_CRC_EN 0x241f 10570#define regDP3_DP_DPHY_CRC_EN_BASE_IDX 2 10571#define regDP3_DP_DPHY_CRC_CNTL 0x2420 10572#define regDP3_DP_DPHY_CRC_CNTL_BASE_IDX 2 10573#define regDP3_DP_DPHY_CRC_RESULT 0x2421 10574#define regDP3_DP_DPHY_CRC_RESULT_BASE_IDX 2 10575#define regDP3_DP_DPHY_CRC_MST_CNTL 0x2422 10576#define regDP3_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2 10577#define regDP3_DP_DPHY_CRC_MST_STATUS 0x2423 10578#define regDP3_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2 10579#define regDP3_DP_DPHY_FAST_TRAINING 0x2424 10580#define regDP3_DP_DPHY_FAST_TRAINING_BASE_IDX 2 10581#define regDP3_DP_DPHY_FAST_TRAINING_STATUS 0x2425 10582#define regDP3_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2 10583#define regDP3_DP_SEC_CNTL 0x242b 10584#define regDP3_DP_SEC_CNTL_BASE_IDX 2 10585#define regDP3_DP_SEC_CNTL1 0x242c 10586#define regDP3_DP_SEC_CNTL1_BASE_IDX 2 10587#define regDP3_DP_SEC_FRAMING1 0x242d 10588#define regDP3_DP_SEC_FRAMING1_BASE_IDX 2 10589#define regDP3_DP_SEC_FRAMING2 0x242e 10590#define regDP3_DP_SEC_FRAMING2_BASE_IDX 2 10591#define regDP3_DP_SEC_FRAMING3 0x242f 10592#define regDP3_DP_SEC_FRAMING3_BASE_IDX 2 10593#define regDP3_DP_SEC_FRAMING4 0x2430 10594#define regDP3_DP_SEC_FRAMING4_BASE_IDX 2 10595#define regDP3_DP_SEC_AUD_N 0x2431 10596#define regDP3_DP_SEC_AUD_N_BASE_IDX 2 10597#define regDP3_DP_SEC_AUD_N_READBACK 0x2432 10598#define regDP3_DP_SEC_AUD_N_READBACK_BASE_IDX 2 10599#define regDP3_DP_SEC_AUD_M 0x2433 10600#define regDP3_DP_SEC_AUD_M_BASE_IDX 2 10601#define regDP3_DP_SEC_AUD_M_READBACK 0x2434 10602#define regDP3_DP_SEC_AUD_M_READBACK_BASE_IDX 2 10603#define regDP3_DP_SEC_TIMESTAMP 0x2435 10604#define regDP3_DP_SEC_TIMESTAMP_BASE_IDX 2 10605#define regDP3_DP_SEC_PACKET_CNTL 0x2436 10606#define regDP3_DP_SEC_PACKET_CNTL_BASE_IDX 2 10607#define regDP3_DP_MSE_RATE_CNTL 0x2437 10608#define regDP3_DP_MSE_RATE_CNTL_BASE_IDX 2 10609#define regDP3_DP_MSE_RATE_UPDATE 0x2439 10610#define regDP3_DP_MSE_RATE_UPDATE_BASE_IDX 2 10611#define regDP3_DP_MSE_SAT0 0x243a 10612#define regDP3_DP_MSE_SAT0_BASE_IDX 2 10613#define regDP3_DP_MSE_SAT1 0x243b 10614#define regDP3_DP_MSE_SAT1_BASE_IDX 2 10615#define regDP3_DP_MSE_SAT2 0x243c 10616#define regDP3_DP_MSE_SAT2_BASE_IDX 2 10617#define regDP3_DP_MSE_SAT_UPDATE 0x243d 10618#define regDP3_DP_MSE_SAT_UPDATE_BASE_IDX 2 10619#define regDP3_DP_MSE_LINK_TIMING 0x243e 10620#define regDP3_DP_MSE_LINK_TIMING_BASE_IDX 2 10621#define regDP3_DP_MSE_MISC_CNTL 0x243f 10622#define regDP3_DP_MSE_MISC_CNTL_BASE_IDX 2 10623#define regDP3_DP_DPHY_BS_SR_SWAP_CNTL 0x2444 10624#define regDP3_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2 10625#define regDP3_DP_DPHY_HBR2_PATTERN_CONTROL 0x2445 10626#define regDP3_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2 10627#define regDP3_DP_MSE_SAT0_STATUS 0x2447 10628#define regDP3_DP_MSE_SAT0_STATUS_BASE_IDX 2 10629#define regDP3_DP_MSE_SAT1_STATUS 0x2448 10630#define regDP3_DP_MSE_SAT1_STATUS_BASE_IDX 2 10631#define regDP3_DP_MSE_SAT2_STATUS 0x2449 10632#define regDP3_DP_MSE_SAT2_STATUS_BASE_IDX 2 10633#define regDP3_DP_MSA_TIMING_PARAM1 0x244c 10634#define regDP3_DP_MSA_TIMING_PARAM1_BASE_IDX 2 10635#define regDP3_DP_MSA_TIMING_PARAM2 0x244d 10636#define regDP3_DP_MSA_TIMING_PARAM2_BASE_IDX 2 10637#define regDP3_DP_MSA_TIMING_PARAM3 0x244e 10638#define regDP3_DP_MSA_TIMING_PARAM3_BASE_IDX 2 10639#define regDP3_DP_MSA_TIMING_PARAM4 0x244f 10640#define regDP3_DP_MSA_TIMING_PARAM4_BASE_IDX 2 10641#define regDP3_DP_MSO_CNTL 0x2450 10642#define regDP3_DP_MSO_CNTL_BASE_IDX 2 10643#define regDP3_DP_MSO_CNTL1 0x2451 10644#define regDP3_DP_MSO_CNTL1_BASE_IDX 2 10645#define regDP3_DP_DSC_CNTL 0x2452 10646#define regDP3_DP_DSC_CNTL_BASE_IDX 2 10647#define regDP3_DP_SEC_CNTL2 0x2453 10648#define regDP3_DP_SEC_CNTL2_BASE_IDX 2 10649#define regDP3_DP_SEC_CNTL3 0x2454 10650#define regDP3_DP_SEC_CNTL3_BASE_IDX 2 10651#define regDP3_DP_SEC_CNTL4 0x2455 10652#define regDP3_DP_SEC_CNTL4_BASE_IDX 2 10653#define regDP3_DP_SEC_CNTL5 0x2456 10654#define regDP3_DP_SEC_CNTL5_BASE_IDX 2 10655#define regDP3_DP_SEC_CNTL6 0x2457 10656#define regDP3_DP_SEC_CNTL6_BASE_IDX 2 10657#define regDP3_DP_SEC_CNTL7 0x2458 10658#define regDP3_DP_SEC_CNTL7_BASE_IDX 2 10659#define regDP3_DP_DB_CNTL 0x2459 10660#define regDP3_DP_DB_CNTL_BASE_IDX 2 10661#define regDP3_DP_MSA_VBID_MISC 0x245a 10662#define regDP3_DP_MSA_VBID_MISC_BASE_IDX 2 10663#define regDP3_DP_SEC_METADATA_TRANSMISSION 0x245b 10664#define regDP3_DP_SEC_METADATA_TRANSMISSION_BASE_IDX 2 10665#define regDP3_DP_DSC_BYTES_PER_PIXEL 0x245c 10666#define regDP3_DP_DSC_BYTES_PER_PIXEL_BASE_IDX 2 10667#define regDP3_DP_ALPM_CNTL 0x245d 10668#define regDP3_DP_ALPM_CNTL_BASE_IDX 2 10669#define regDP3_DP_GSP8_CNTL 0x245e 10670#define regDP3_DP_GSP8_CNTL_BASE_IDX 2 10671#define regDP3_DP_GSP9_CNTL 0x245f 10672#define regDP3_DP_GSP9_CNTL_BASE_IDX 2 10673#define regDP3_DP_GSP10_CNTL 0x2460 10674#define regDP3_DP_GSP10_CNTL_BASE_IDX 2 10675#define regDP3_DP_GSP11_CNTL 0x2461 10676#define regDP3_DP_GSP11_CNTL_BASE_IDX 2 10677#define regDP3_DP_GSP_EN_DB_STATUS 0x2462 10678#define regDP3_DP_GSP_EN_DB_STATUS_BASE_IDX 2 10679 10680 10681// addressBlock: dce_dc_dio_dig3_dispdec 10682// base address: 0xc00 10683#define regDIG3_DIG_FE_CNTL 0x238b 10684#define regDIG3_DIG_FE_CNTL_BASE_IDX 2 10685#define regDIG3_DIG_OUTPUT_CRC_CNTL 0x238c 10686#define regDIG3_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2 10687#define regDIG3_DIG_OUTPUT_CRC_RESULT 0x238d 10688#define regDIG3_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2 10689#define regDIG3_DIG_CLOCK_PATTERN 0x238e 10690#define regDIG3_DIG_CLOCK_PATTERN_BASE_IDX 2 10691#define regDIG3_DIG_TEST_PATTERN 0x238f 10692#define regDIG3_DIG_TEST_PATTERN_BASE_IDX 2 10693#define regDIG3_DIG_RANDOM_PATTERN_SEED 0x2390 10694#define regDIG3_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2 10695#define regDIG3_DIG_FIFO_STATUS 0x2391 10696#define regDIG3_DIG_FIFO_STATUS_BASE_IDX 2 10697#define regDIG3_HDMI_METADATA_PACKET_CONTROL 0x2392 10698#define regDIG3_HDMI_METADATA_PACKET_CONTROL_BASE_IDX 2 10699#define regDIG3_HDMI_CONTROL 0x2393 10700#define regDIG3_HDMI_CONTROL_BASE_IDX 2 10701#define regDIG3_HDMI_STATUS 0x2394 10702#define regDIG3_HDMI_STATUS_BASE_IDX 2 10703#define regDIG3_HDMI_AUDIO_PACKET_CONTROL 0x2395 10704#define regDIG3_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2 10705#define regDIG3_HDMI_ACR_PACKET_CONTROL 0x2396 10706#define regDIG3_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2 10707#define regDIG3_HDMI_VBI_PACKET_CONTROL 0x2397 10708#define regDIG3_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2 10709#define regDIG3_HDMI_INFOFRAME_CONTROL0 0x2398 10710#define regDIG3_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2 10711#define regDIG3_HDMI_INFOFRAME_CONTROL1 0x2399 10712#define regDIG3_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2 10713#define regDIG3_HDMI_GENERIC_PACKET_CONTROL0 0x239a 10714#define regDIG3_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2 10715#define regDIG3_HDMI_GENERIC_PACKET_CONTROL6 0x239b 10716#define regDIG3_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX 2 10717#define regDIG3_HDMI_GENERIC_PACKET_CONTROL5 0x239c 10718#define regDIG3_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX 2 10719#define regDIG3_HDMI_GC 0x239d 10720#define regDIG3_HDMI_GC_BASE_IDX 2 10721#define regDIG3_HDMI_GENERIC_PACKET_CONTROL1 0x239e 10722#define regDIG3_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2 10723#define regDIG3_HDMI_GENERIC_PACKET_CONTROL2 0x239f 10724#define regDIG3_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2 10725#define regDIG3_HDMI_GENERIC_PACKET_CONTROL3 0x23a0 10726#define regDIG3_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2 10727#define regDIG3_HDMI_GENERIC_PACKET_CONTROL4 0x23a1 10728#define regDIG3_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX 2 10729#define regDIG3_HDMI_GENERIC_PACKET_CONTROL7 0x23a2 10730#define regDIG3_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX 2 10731#define regDIG3_HDMI_GENERIC_PACKET_CONTROL8 0x23a3 10732#define regDIG3_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX 2 10733#define regDIG3_HDMI_GENERIC_PACKET_CONTROL9 0x23a4 10734#define regDIG3_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX 2 10735#define regDIG3_HDMI_GENERIC_PACKET_CONTROL10 0x23a5 10736#define regDIG3_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX 2 10737#define regDIG3_HDMI_DB_CONTROL 0x23a6 10738#define regDIG3_HDMI_DB_CONTROL_BASE_IDX 2 10739#define regDIG3_HDMI_ACR_32_0 0x23a7 10740#define regDIG3_HDMI_ACR_32_0_BASE_IDX 2 10741#define regDIG3_HDMI_ACR_32_1 0x23a8 10742#define regDIG3_HDMI_ACR_32_1_BASE_IDX 2 10743#define regDIG3_HDMI_ACR_44_0 0x23a9 10744#define regDIG3_HDMI_ACR_44_0_BASE_IDX 2 10745#define regDIG3_HDMI_ACR_44_1 0x23aa 10746#define regDIG3_HDMI_ACR_44_1_BASE_IDX 2 10747#define regDIG3_HDMI_ACR_48_0 0x23ab 10748#define regDIG3_HDMI_ACR_48_0_BASE_IDX 2 10749#define regDIG3_HDMI_ACR_48_1 0x23ac 10750#define regDIG3_HDMI_ACR_48_1_BASE_IDX 2 10751#define regDIG3_HDMI_ACR_STATUS_0 0x23ad 10752#define regDIG3_HDMI_ACR_STATUS_0_BASE_IDX 2 10753#define regDIG3_HDMI_ACR_STATUS_1 0x23ae 10754#define regDIG3_HDMI_ACR_STATUS_1_BASE_IDX 2 10755#define regDIG3_AFMT_CNTL 0x23af 10756#define regDIG3_AFMT_CNTL_BASE_IDX 2 10757#define regDIG3_DIG_BE_CNTL 0x23b0 10758#define regDIG3_DIG_BE_CNTL_BASE_IDX 2 10759#define regDIG3_DIG_BE_EN_CNTL 0x23b1 10760#define regDIG3_DIG_BE_EN_CNTL_BASE_IDX 2 10761#define regDIG3_TMDS_CNTL 0x23d7 10762#define regDIG3_TMDS_CNTL_BASE_IDX 2 10763#define regDIG3_TMDS_CONTROL_CHAR 0x23d8 10764#define regDIG3_TMDS_CONTROL_CHAR_BASE_IDX 2 10765#define regDIG3_TMDS_CONTROL0_FEEDBACK 0x23d9 10766#define regDIG3_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2 10767#define regDIG3_TMDS_STEREOSYNC_CTL_SEL 0x23da 10768#define regDIG3_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2 10769#define regDIG3_TMDS_SYNC_CHAR_PATTERN_0_1 0x23db 10770#define regDIG3_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2 10771#define regDIG3_TMDS_SYNC_CHAR_PATTERN_2_3 0x23dc 10772#define regDIG3_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2 10773#define regDIG3_TMDS_CTL_BITS 0x23de 10774#define regDIG3_TMDS_CTL_BITS_BASE_IDX 2 10775#define regDIG3_TMDS_DCBALANCER_CONTROL 0x23df 10776#define regDIG3_TMDS_DCBALANCER_CONTROL_BASE_IDX 2 10777#define regDIG3_TMDS_SYNC_DCBALANCE_CHAR 0x23e0 10778#define regDIG3_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX 2 10779#define regDIG3_TMDS_CTL0_1_GEN_CNTL 0x23e1 10780#define regDIG3_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2 10781#define regDIG3_TMDS_CTL2_3_GEN_CNTL 0x23e2 10782#define regDIG3_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2 10783#define regDIG3_DIG_VERSION 0x23e4 10784#define regDIG3_DIG_VERSION_BASE_IDX 2 10785#define regDIG3_FORCE_DIG_DISABLE 0x23e5 10786#define regDIG3_FORCE_DIG_DISABLE_BASE_IDX 2 10787 10788 10789// addressBlock: dce_dc_dio_dp4_dispdec 10790// base address: 0x1000 10791#define regDP4_DP_LINK_CNTL 0x2508 10792#define regDP4_DP_LINK_CNTL_BASE_IDX 2 10793#define regDP4_DP_PIXEL_FORMAT 0x2509 10794#define regDP4_DP_PIXEL_FORMAT_BASE_IDX 2 10795#define regDP4_DP_MSA_COLORIMETRY 0x250a 10796#define regDP4_DP_MSA_COLORIMETRY_BASE_IDX 2 10797#define regDP4_DP_CONFIG 0x250b 10798#define regDP4_DP_CONFIG_BASE_IDX 2 10799#define regDP4_DP_VID_STREAM_CNTL 0x250c 10800#define regDP4_DP_VID_STREAM_CNTL_BASE_IDX 2 10801#define regDP4_DP_STEER_FIFO 0x250d 10802#define regDP4_DP_STEER_FIFO_BASE_IDX 2 10803#define regDP4_DP_MSA_MISC 0x250e 10804#define regDP4_DP_MSA_MISC_BASE_IDX 2 10805#define regDP4_DP_DPHY_INTERNAL_CTRL 0x250f 10806#define regDP4_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 10807#define regDP4_DP_VID_TIMING 0x2510 10808#define regDP4_DP_VID_TIMING_BASE_IDX 2 10809#define regDP4_DP_VID_N 0x2511 10810#define regDP4_DP_VID_N_BASE_IDX 2 10811#define regDP4_DP_VID_M 0x2512 10812#define regDP4_DP_VID_M_BASE_IDX 2 10813#define regDP4_DP_LINK_FRAMING_CNTL 0x2513 10814#define regDP4_DP_LINK_FRAMING_CNTL_BASE_IDX 2 10815#define regDP4_DP_HBR2_EYE_PATTERN 0x2514 10816#define regDP4_DP_HBR2_EYE_PATTERN_BASE_IDX 2 10817#define regDP4_DP_VID_MSA_VBID 0x2515 10818#define regDP4_DP_VID_MSA_VBID_BASE_IDX 2 10819#define regDP4_DP_VID_INTERRUPT_CNTL 0x2516 10820#define regDP4_DP_VID_INTERRUPT_CNTL_BASE_IDX 2 10821#define regDP4_DP_DPHY_CNTL 0x2517 10822#define regDP4_DP_DPHY_CNTL_BASE_IDX 2 10823#define regDP4_DP_DPHY_TRAINING_PATTERN_SEL 0x2518 10824#define regDP4_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2 10825#define regDP4_DP_DPHY_SYM0 0x2519 10826#define regDP4_DP_DPHY_SYM0_BASE_IDX 2 10827#define regDP4_DP_DPHY_SYM1 0x251a 10828#define regDP4_DP_DPHY_SYM1_BASE_IDX 2 10829#define regDP4_DP_DPHY_SYM2 0x251b 10830#define regDP4_DP_DPHY_SYM2_BASE_IDX 2 10831#define regDP4_DP_DPHY_8B10B_CNTL 0x251c 10832#define regDP4_DP_DPHY_8B10B_CNTL_BASE_IDX 2 10833#define regDP4_DP_DPHY_PRBS_CNTL 0x251d 10834#define regDP4_DP_DPHY_PRBS_CNTL_BASE_IDX 2 10835#define regDP4_DP_DPHY_SCRAM_CNTL 0x251e 10836#define regDP4_DP_DPHY_SCRAM_CNTL_BASE_IDX 2 10837#define regDP4_DP_DPHY_CRC_EN 0x251f 10838#define regDP4_DP_DPHY_CRC_EN_BASE_IDX 2 10839#define regDP4_DP_DPHY_CRC_CNTL 0x2520 10840#define regDP4_DP_DPHY_CRC_CNTL_BASE_IDX 2 10841#define regDP4_DP_DPHY_CRC_RESULT 0x2521 10842#define regDP4_DP_DPHY_CRC_RESULT_BASE_IDX 2 10843#define regDP4_DP_DPHY_CRC_MST_CNTL 0x2522 10844#define regDP4_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2 10845#define regDP4_DP_DPHY_CRC_MST_STATUS 0x2523 10846#define regDP4_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2 10847#define regDP4_DP_DPHY_FAST_TRAINING 0x2524 10848#define regDP4_DP_DPHY_FAST_TRAINING_BASE_IDX 2 10849#define regDP4_DP_DPHY_FAST_TRAINING_STATUS 0x2525 10850#define regDP4_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2 10851#define regDP4_DP_SEC_CNTL 0x252b 10852#define regDP4_DP_SEC_CNTL_BASE_IDX 2 10853#define regDP4_DP_SEC_CNTL1 0x252c 10854#define regDP4_DP_SEC_CNTL1_BASE_IDX 2 10855#define regDP4_DP_SEC_FRAMING1 0x252d 10856#define regDP4_DP_SEC_FRAMING1_BASE_IDX 2 10857#define regDP4_DP_SEC_FRAMING2 0x252e 10858#define regDP4_DP_SEC_FRAMING2_BASE_IDX 2 10859#define regDP4_DP_SEC_FRAMING3 0x252f 10860#define regDP4_DP_SEC_FRAMING3_BASE_IDX 2 10861#define regDP4_DP_SEC_FRAMING4 0x2530 10862#define regDP4_DP_SEC_FRAMING4_BASE_IDX 2 10863#define regDP4_DP_SEC_AUD_N 0x2531 10864#define regDP4_DP_SEC_AUD_N_BASE_IDX 2 10865#define regDP4_DP_SEC_AUD_N_READBACK 0x2532 10866#define regDP4_DP_SEC_AUD_N_READBACK_BASE_IDX 2 10867#define regDP4_DP_SEC_AUD_M 0x2533 10868#define regDP4_DP_SEC_AUD_M_BASE_IDX 2 10869#define regDP4_DP_SEC_AUD_M_READBACK 0x2534 10870#define regDP4_DP_SEC_AUD_M_READBACK_BASE_IDX 2 10871#define regDP4_DP_SEC_TIMESTAMP 0x2535 10872#define regDP4_DP_SEC_TIMESTAMP_BASE_IDX 2 10873#define regDP4_DP_SEC_PACKET_CNTL 0x2536 10874#define regDP4_DP_SEC_PACKET_CNTL_BASE_IDX 2 10875#define regDP4_DP_MSE_RATE_CNTL 0x2537 10876#define regDP4_DP_MSE_RATE_CNTL_BASE_IDX 2 10877#define regDP4_DP_MSE_RATE_UPDATE 0x2539 10878#define regDP4_DP_MSE_RATE_UPDATE_BASE_IDX 2 10879#define regDP4_DP_MSE_SAT0 0x253a 10880#define regDP4_DP_MSE_SAT0_BASE_IDX 2 10881#define regDP4_DP_MSE_SAT1 0x253b 10882#define regDP4_DP_MSE_SAT1_BASE_IDX 2 10883#define regDP4_DP_MSE_SAT2 0x253c 10884#define regDP4_DP_MSE_SAT2_BASE_IDX 2 10885#define regDP4_DP_MSE_SAT_UPDATE 0x253d 10886#define regDP4_DP_MSE_SAT_UPDATE_BASE_IDX 2 10887#define regDP4_DP_MSE_LINK_TIMING 0x253e 10888#define regDP4_DP_MSE_LINK_TIMING_BASE_IDX 2 10889#define regDP4_DP_MSE_MISC_CNTL 0x253f 10890#define regDP4_DP_MSE_MISC_CNTL_BASE_IDX 2 10891#define regDP4_DP_DPHY_BS_SR_SWAP_CNTL 0x2544 10892#define regDP4_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2 10893#define regDP4_DP_DPHY_HBR2_PATTERN_CONTROL 0x2545 10894#define regDP4_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2 10895#define regDP4_DP_MSE_SAT0_STATUS 0x2547 10896#define regDP4_DP_MSE_SAT0_STATUS_BASE_IDX 2 10897#define regDP4_DP_MSE_SAT1_STATUS 0x2548 10898#define regDP4_DP_MSE_SAT1_STATUS_BASE_IDX 2 10899#define regDP4_DP_MSE_SAT2_STATUS 0x2549 10900#define regDP4_DP_MSE_SAT2_STATUS_BASE_IDX 2 10901#define regDP4_DP_MSA_TIMING_PARAM1 0x254c 10902#define regDP4_DP_MSA_TIMING_PARAM1_BASE_IDX 2 10903#define regDP4_DP_MSA_TIMING_PARAM2 0x254d 10904#define regDP4_DP_MSA_TIMING_PARAM2_BASE_IDX 2 10905#define regDP4_DP_MSA_TIMING_PARAM3 0x254e 10906#define regDP4_DP_MSA_TIMING_PARAM3_BASE_IDX 2 10907#define regDP4_DP_MSA_TIMING_PARAM4 0x254f 10908#define regDP4_DP_MSA_TIMING_PARAM4_BASE_IDX 2 10909#define regDP4_DP_MSO_CNTL 0x2550 10910#define regDP4_DP_MSO_CNTL_BASE_IDX 2 10911#define regDP4_DP_MSO_CNTL1 0x2551 10912#define regDP4_DP_MSO_CNTL1_BASE_IDX 2 10913#define regDP4_DP_DSC_CNTL 0x2552 10914#define regDP4_DP_DSC_CNTL_BASE_IDX 2 10915#define regDP4_DP_SEC_CNTL2 0x2553 10916#define regDP4_DP_SEC_CNTL2_BASE_IDX 2 10917#define regDP4_DP_SEC_CNTL3 0x2554 10918#define regDP4_DP_SEC_CNTL3_BASE_IDX 2 10919#define regDP4_DP_SEC_CNTL4 0x2555 10920#define regDP4_DP_SEC_CNTL4_BASE_IDX 2 10921#define regDP4_DP_SEC_CNTL5 0x2556 10922#define regDP4_DP_SEC_CNTL5_BASE_IDX 2 10923#define regDP4_DP_SEC_CNTL6 0x2557 10924#define regDP4_DP_SEC_CNTL6_BASE_IDX 2 10925#define regDP4_DP_SEC_CNTL7 0x2558 10926#define regDP4_DP_SEC_CNTL7_BASE_IDX 2 10927#define regDP4_DP_DB_CNTL 0x2559 10928#define regDP4_DP_DB_CNTL_BASE_IDX 2 10929#define regDP4_DP_MSA_VBID_MISC 0x255a 10930#define regDP4_DP_MSA_VBID_MISC_BASE_IDX 2 10931#define regDP4_DP_SEC_METADATA_TRANSMISSION 0x255b 10932#define regDP4_DP_SEC_METADATA_TRANSMISSION_BASE_IDX 2 10933#define regDP4_DP_DSC_BYTES_PER_PIXEL 0x255c 10934#define regDP4_DP_DSC_BYTES_PER_PIXEL_BASE_IDX 2 10935#define regDP4_DP_ALPM_CNTL 0x255d 10936#define regDP4_DP_ALPM_CNTL_BASE_IDX 2 10937#define regDP4_DP_GSP8_CNTL 0x255e 10938#define regDP4_DP_GSP8_CNTL_BASE_IDX 2 10939#define regDP4_DP_GSP9_CNTL 0x255f 10940#define regDP4_DP_GSP9_CNTL_BASE_IDX 2 10941#define regDP4_DP_GSP10_CNTL 0x2560 10942#define regDP4_DP_GSP10_CNTL_BASE_IDX 2 10943#define regDP4_DP_GSP11_CNTL 0x2561 10944#define regDP4_DP_GSP11_CNTL_BASE_IDX 2 10945#define regDP4_DP_GSP_EN_DB_STATUS 0x2562 10946#define regDP4_DP_GSP_EN_DB_STATUS_BASE_IDX 2 10947 10948 10949// addressBlock: dce_dc_dio_dig4_dispdec 10950// base address: 0x1000 10951#define regDIG4_DIG_FE_CNTL 0x248b 10952#define regDIG4_DIG_FE_CNTL_BASE_IDX 2 10953#define regDIG4_DIG_OUTPUT_CRC_CNTL 0x248c 10954#define regDIG4_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2 10955#define regDIG4_DIG_OUTPUT_CRC_RESULT 0x248d 10956#define regDIG4_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2 10957#define regDIG4_DIG_CLOCK_PATTERN 0x248e 10958#define regDIG4_DIG_CLOCK_PATTERN_BASE_IDX 2 10959#define regDIG4_DIG_TEST_PATTERN 0x248f 10960#define regDIG4_DIG_TEST_PATTERN_BASE_IDX 2 10961#define regDIG4_DIG_RANDOM_PATTERN_SEED 0x2490 10962#define regDIG4_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2 10963#define regDIG4_DIG_FIFO_STATUS 0x2491 10964#define regDIG4_DIG_FIFO_STATUS_BASE_IDX 2 10965#define regDIG4_HDMI_METADATA_PACKET_CONTROL 0x2492 10966#define regDIG4_HDMI_METADATA_PACKET_CONTROL_BASE_IDX 2 10967#define regDIG4_HDMI_CONTROL 0x2493 10968#define regDIG4_HDMI_CONTROL_BASE_IDX 2 10969#define regDIG4_HDMI_STATUS 0x2494 10970#define regDIG4_HDMI_STATUS_BASE_IDX 2 10971#define regDIG4_HDMI_AUDIO_PACKET_CONTROL 0x2495 10972#define regDIG4_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2 10973#define regDIG4_HDMI_ACR_PACKET_CONTROL 0x2496 10974#define regDIG4_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2 10975#define regDIG4_HDMI_VBI_PACKET_CONTROL 0x2497 10976#define regDIG4_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2 10977#define regDIG4_HDMI_INFOFRAME_CONTROL0 0x2498 10978#define regDIG4_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2 10979#define regDIG4_HDMI_INFOFRAME_CONTROL1 0x2499 10980#define regDIG4_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2 10981#define regDIG4_HDMI_GENERIC_PACKET_CONTROL0 0x249a 10982#define regDIG4_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2 10983#define regDIG4_HDMI_GENERIC_PACKET_CONTROL6 0x249b 10984#define regDIG4_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX 2 10985#define regDIG4_HDMI_GENERIC_PACKET_CONTROL5 0x249c 10986#define regDIG4_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX 2 10987#define regDIG4_HDMI_GC 0x249d 10988#define regDIG4_HDMI_GC_BASE_IDX 2 10989#define regDIG4_HDMI_GENERIC_PACKET_CONTROL1 0x249e 10990#define regDIG4_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2 10991#define regDIG4_HDMI_GENERIC_PACKET_CONTROL2 0x249f 10992#define regDIG4_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2 10993#define regDIG4_HDMI_GENERIC_PACKET_CONTROL3 0x24a0 10994#define regDIG4_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2 10995#define regDIG4_HDMI_GENERIC_PACKET_CONTROL4 0x24a1 10996#define regDIG4_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX 2 10997#define regDIG4_HDMI_GENERIC_PACKET_CONTROL7 0x24a2 10998#define regDIG4_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX 2 10999#define regDIG4_HDMI_GENERIC_PACKET_CONTROL8 0x24a3 11000#define regDIG4_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX 2 11001#define regDIG4_HDMI_GENERIC_PACKET_CONTROL9 0x24a4 11002#define regDIG4_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX 2 11003#define regDIG4_HDMI_GENERIC_PACKET_CONTROL10 0x24a5 11004#define regDIG4_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX 2 11005#define regDIG4_HDMI_DB_CONTROL 0x24a6 11006#define regDIG4_HDMI_DB_CONTROL_BASE_IDX 2 11007#define regDIG4_HDMI_ACR_32_0 0x24a7 11008#define regDIG4_HDMI_ACR_32_0_BASE_IDX 2 11009#define regDIG4_HDMI_ACR_32_1 0x24a8 11010#define regDIG4_HDMI_ACR_32_1_BASE_IDX 2 11011#define regDIG4_HDMI_ACR_44_0 0x24a9 11012#define regDIG4_HDMI_ACR_44_0_BASE_IDX 2 11013#define regDIG4_HDMI_ACR_44_1 0x24aa 11014#define regDIG4_HDMI_ACR_44_1_BASE_IDX 2 11015#define regDIG4_HDMI_ACR_48_0 0x24ab 11016#define regDIG4_HDMI_ACR_48_0_BASE_IDX 2 11017#define regDIG4_HDMI_ACR_48_1 0x24ac 11018#define regDIG4_HDMI_ACR_48_1_BASE_IDX 2 11019#define regDIG4_HDMI_ACR_STATUS_0 0x24ad 11020#define regDIG4_HDMI_ACR_STATUS_0_BASE_IDX 2 11021#define regDIG4_HDMI_ACR_STATUS_1 0x24ae 11022#define regDIG4_HDMI_ACR_STATUS_1_BASE_IDX 2 11023#define regDIG4_AFMT_CNTL 0x24af 11024#define regDIG4_AFMT_CNTL_BASE_IDX 2 11025#define regDIG4_DIG_BE_CNTL 0x24b0 11026#define regDIG4_DIG_BE_CNTL_BASE_IDX 2 11027#define regDIG4_DIG_BE_EN_CNTL 0x24b1 11028#define regDIG4_DIG_BE_EN_CNTL_BASE_IDX 2 11029#define regDIG4_TMDS_CNTL 0x24d7 11030#define regDIG4_TMDS_CNTL_BASE_IDX 2 11031#define regDIG4_TMDS_CONTROL_CHAR 0x24d8 11032#define regDIG4_TMDS_CONTROL_CHAR_BASE_IDX 2 11033#define regDIG4_TMDS_CONTROL0_FEEDBACK 0x24d9 11034#define regDIG4_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2 11035#define regDIG4_TMDS_STEREOSYNC_CTL_SEL 0x24da 11036#define regDIG4_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2 11037#define regDIG4_TMDS_SYNC_CHAR_PATTERN_0_1 0x24db 11038#define regDIG4_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2 11039#define regDIG4_TMDS_SYNC_CHAR_PATTERN_2_3 0x24dc 11040#define regDIG4_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2 11041#define regDIG4_TMDS_CTL_BITS 0x24de 11042#define regDIG4_TMDS_CTL_BITS_BASE_IDX 2 11043#define regDIG4_TMDS_DCBALANCER_CONTROL 0x24df 11044#define regDIG4_TMDS_DCBALANCER_CONTROL_BASE_IDX 2 11045#define regDIG4_TMDS_SYNC_DCBALANCE_CHAR 0x24e0 11046#define regDIG4_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX 2 11047#define regDIG4_TMDS_CTL0_1_GEN_CNTL 0x24e1 11048#define regDIG4_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2 11049#define regDIG4_TMDS_CTL2_3_GEN_CNTL 0x24e2 11050#define regDIG4_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2 11051#define regDIG4_DIG_VERSION 0x24e4 11052#define regDIG4_DIG_VERSION_BASE_IDX 2 11053#define regDIG4_FORCE_DIG_DISABLE 0x24e5 11054#define regDIG4_FORCE_DIG_DISABLE_BASE_IDX 2 11055 11056 11057// addressBlock: dce_dc_dio_dig0_afmt_afmt_dispdec 11058// base address: 0x154cc 11059#define regAFMT0_AFMT_VBI_PACKET_CONTROL 0x2074 11060#define regAFMT0_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2 11061#define regAFMT0_AFMT_AUDIO_PACKET_CONTROL2 0x2075 11062#define regAFMT0_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2 11063#define regAFMT0_AFMT_AUDIO_INFO0 0x2076 11064#define regAFMT0_AFMT_AUDIO_INFO0_BASE_IDX 2 11065#define regAFMT0_AFMT_AUDIO_INFO1 0x2077 11066#define regAFMT0_AFMT_AUDIO_INFO1_BASE_IDX 2 11067#define regAFMT0_AFMT_60958_0 0x2078 11068#define regAFMT0_AFMT_60958_0_BASE_IDX 2 11069#define regAFMT0_AFMT_60958_1 0x2079 11070#define regAFMT0_AFMT_60958_1_BASE_IDX 2 11071#define regAFMT0_AFMT_AUDIO_CRC_CONTROL 0x207a 11072#define regAFMT0_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2 11073#define regAFMT0_AFMT_RAMP_CONTROL0 0x207b 11074#define regAFMT0_AFMT_RAMP_CONTROL0_BASE_IDX 2 11075#define regAFMT0_AFMT_RAMP_CONTROL1 0x207c 11076#define regAFMT0_AFMT_RAMP_CONTROL1_BASE_IDX 2 11077#define regAFMT0_AFMT_RAMP_CONTROL2 0x207d 11078#define regAFMT0_AFMT_RAMP_CONTROL2_BASE_IDX 2 11079#define regAFMT0_AFMT_RAMP_CONTROL3 0x207e 11080#define regAFMT0_AFMT_RAMP_CONTROL3_BASE_IDX 2 11081#define regAFMT0_AFMT_60958_2 0x207f 11082#define regAFMT0_AFMT_60958_2_BASE_IDX 2 11083#define regAFMT0_AFMT_AUDIO_CRC_RESULT 0x2080 11084#define regAFMT0_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2 11085#define regAFMT0_AFMT_STATUS 0x2081 11086#define regAFMT0_AFMT_STATUS_BASE_IDX 2 11087#define regAFMT0_AFMT_AUDIO_PACKET_CONTROL 0x2082 11088#define regAFMT0_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2 11089#define regAFMT0_AFMT_INFOFRAME_CONTROL0 0x2083 11090#define regAFMT0_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2 11091#define regAFMT0_AFMT_INTERRUPT_STATUS 0x2084 11092#define regAFMT0_AFMT_INTERRUPT_STATUS_BASE_IDX 2 11093#define regAFMT0_AFMT_AUDIO_SRC_CONTROL 0x2085 11094#define regAFMT0_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2 11095#define regAFMT0_AFMT_MEM_PWR 0x2087 11096#define regAFMT0_AFMT_MEM_PWR_BASE_IDX 2 11097 11098 11099// addressBlock: dce_dc_dio_dig1_afmt_afmt_dispdec 11100// base address: 0x158cc 11101#define regAFMT1_AFMT_VBI_PACKET_CONTROL 0x2174 11102#define regAFMT1_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2 11103#define regAFMT1_AFMT_AUDIO_PACKET_CONTROL2 0x2175 11104#define regAFMT1_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2 11105#define regAFMT1_AFMT_AUDIO_INFO0 0x2176 11106#define regAFMT1_AFMT_AUDIO_INFO0_BASE_IDX 2 11107#define regAFMT1_AFMT_AUDIO_INFO1 0x2177 11108#define regAFMT1_AFMT_AUDIO_INFO1_BASE_IDX 2 11109#define regAFMT1_AFMT_60958_0 0x2178 11110#define regAFMT1_AFMT_60958_0_BASE_IDX 2 11111#define regAFMT1_AFMT_60958_1 0x2179 11112#define regAFMT1_AFMT_60958_1_BASE_IDX 2 11113#define regAFMT1_AFMT_AUDIO_CRC_CONTROL 0x217a 11114#define regAFMT1_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2 11115#define regAFMT1_AFMT_RAMP_CONTROL0 0x217b 11116#define regAFMT1_AFMT_RAMP_CONTROL0_BASE_IDX 2 11117#define regAFMT1_AFMT_RAMP_CONTROL1 0x217c 11118#define regAFMT1_AFMT_RAMP_CONTROL1_BASE_IDX 2 11119#define regAFMT1_AFMT_RAMP_CONTROL2 0x217d 11120#define regAFMT1_AFMT_RAMP_CONTROL2_BASE_IDX 2 11121#define regAFMT1_AFMT_RAMP_CONTROL3 0x217e 11122#define regAFMT1_AFMT_RAMP_CONTROL3_BASE_IDX 2 11123#define regAFMT1_AFMT_60958_2 0x217f 11124#define regAFMT1_AFMT_60958_2_BASE_IDX 2 11125#define regAFMT1_AFMT_AUDIO_CRC_RESULT 0x2180 11126#define regAFMT1_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2 11127#define regAFMT1_AFMT_STATUS 0x2181 11128#define regAFMT1_AFMT_STATUS_BASE_IDX 2 11129#define regAFMT1_AFMT_AUDIO_PACKET_CONTROL 0x2182 11130#define regAFMT1_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2 11131#define regAFMT1_AFMT_INFOFRAME_CONTROL0 0x2183 11132#define regAFMT1_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2 11133#define regAFMT1_AFMT_INTERRUPT_STATUS 0x2184 11134#define regAFMT1_AFMT_INTERRUPT_STATUS_BASE_IDX 2 11135#define regAFMT1_AFMT_AUDIO_SRC_CONTROL 0x2185 11136#define regAFMT1_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2 11137#define regAFMT1_AFMT_MEM_PWR 0x2187 11138#define regAFMT1_AFMT_MEM_PWR_BASE_IDX 2 11139 11140 11141// addressBlock: dce_dc_dio_dig2_afmt_afmt_dispdec 11142// base address: 0x15ccc 11143#define regAFMT2_AFMT_VBI_PACKET_CONTROL 0x2274 11144#define regAFMT2_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2 11145#define regAFMT2_AFMT_AUDIO_PACKET_CONTROL2 0x2275 11146#define regAFMT2_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2 11147#define regAFMT2_AFMT_AUDIO_INFO0 0x2276 11148#define regAFMT2_AFMT_AUDIO_INFO0_BASE_IDX 2 11149#define regAFMT2_AFMT_AUDIO_INFO1 0x2277 11150#define regAFMT2_AFMT_AUDIO_INFO1_BASE_IDX 2 11151#define regAFMT2_AFMT_60958_0 0x2278 11152#define regAFMT2_AFMT_60958_0_BASE_IDX 2 11153#define regAFMT2_AFMT_60958_1 0x2279 11154#define regAFMT2_AFMT_60958_1_BASE_IDX 2 11155#define regAFMT2_AFMT_AUDIO_CRC_CONTROL 0x227a 11156#define regAFMT2_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2 11157#define regAFMT2_AFMT_RAMP_CONTROL0 0x227b 11158#define regAFMT2_AFMT_RAMP_CONTROL0_BASE_IDX 2 11159#define regAFMT2_AFMT_RAMP_CONTROL1 0x227c 11160#define regAFMT2_AFMT_RAMP_CONTROL1_BASE_IDX 2 11161#define regAFMT2_AFMT_RAMP_CONTROL2 0x227d 11162#define regAFMT2_AFMT_RAMP_CONTROL2_BASE_IDX 2 11163#define regAFMT2_AFMT_RAMP_CONTROL3 0x227e 11164#define regAFMT2_AFMT_RAMP_CONTROL3_BASE_IDX 2 11165#define regAFMT2_AFMT_60958_2 0x227f 11166#define regAFMT2_AFMT_60958_2_BASE_IDX 2 11167#define regAFMT2_AFMT_AUDIO_CRC_RESULT 0x2280 11168#define regAFMT2_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2 11169#define regAFMT2_AFMT_STATUS 0x2281 11170#define regAFMT2_AFMT_STATUS_BASE_IDX 2 11171#define regAFMT2_AFMT_AUDIO_PACKET_CONTROL 0x2282 11172#define regAFMT2_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2 11173#define regAFMT2_AFMT_INFOFRAME_CONTROL0 0x2283 11174#define regAFMT2_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2 11175#define regAFMT2_AFMT_INTERRUPT_STATUS 0x2284 11176#define regAFMT2_AFMT_INTERRUPT_STATUS_BASE_IDX 2 11177#define regAFMT2_AFMT_AUDIO_SRC_CONTROL 0x2285 11178#define regAFMT2_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2 11179#define regAFMT2_AFMT_MEM_PWR 0x2287 11180#define regAFMT2_AFMT_MEM_PWR_BASE_IDX 2 11181 11182 11183// addressBlock: dce_dc_dio_dig3_afmt_afmt_dispdec 11184// base address: 0x160cc 11185#define regAFMT3_AFMT_VBI_PACKET_CONTROL 0x2374 11186#define regAFMT3_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2 11187#define regAFMT3_AFMT_AUDIO_PACKET_CONTROL2 0x2375 11188#define regAFMT3_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2 11189#define regAFMT3_AFMT_AUDIO_INFO0 0x2376 11190#define regAFMT3_AFMT_AUDIO_INFO0_BASE_IDX 2 11191#define regAFMT3_AFMT_AUDIO_INFO1 0x2377 11192#define regAFMT3_AFMT_AUDIO_INFO1_BASE_IDX 2 11193#define regAFMT3_AFMT_60958_0 0x2378 11194#define regAFMT3_AFMT_60958_0_BASE_IDX 2 11195#define regAFMT3_AFMT_60958_1 0x2379 11196#define regAFMT3_AFMT_60958_1_BASE_IDX 2 11197#define regAFMT3_AFMT_AUDIO_CRC_CONTROL 0x237a 11198#define regAFMT3_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2 11199#define regAFMT3_AFMT_RAMP_CONTROL0 0x237b 11200#define regAFMT3_AFMT_RAMP_CONTROL0_BASE_IDX 2 11201#define regAFMT3_AFMT_RAMP_CONTROL1 0x237c 11202#define regAFMT3_AFMT_RAMP_CONTROL1_BASE_IDX 2 11203#define regAFMT3_AFMT_RAMP_CONTROL2 0x237d 11204#define regAFMT3_AFMT_RAMP_CONTROL2_BASE_IDX 2 11205#define regAFMT3_AFMT_RAMP_CONTROL3 0x237e 11206#define regAFMT3_AFMT_RAMP_CONTROL3_BASE_IDX 2 11207#define regAFMT3_AFMT_60958_2 0x237f 11208#define regAFMT3_AFMT_60958_2_BASE_IDX 2 11209#define regAFMT3_AFMT_AUDIO_CRC_RESULT 0x2380 11210#define regAFMT3_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2 11211#define regAFMT3_AFMT_STATUS 0x2381 11212#define regAFMT3_AFMT_STATUS_BASE_IDX 2 11213#define regAFMT3_AFMT_AUDIO_PACKET_CONTROL 0x2382 11214#define regAFMT3_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2 11215#define regAFMT3_AFMT_INFOFRAME_CONTROL0 0x2383 11216#define regAFMT3_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2 11217#define regAFMT3_AFMT_INTERRUPT_STATUS 0x2384 11218#define regAFMT3_AFMT_INTERRUPT_STATUS_BASE_IDX 2 11219#define regAFMT3_AFMT_AUDIO_SRC_CONTROL 0x2385 11220#define regAFMT3_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2 11221#define regAFMT3_AFMT_MEM_PWR 0x2387 11222#define regAFMT3_AFMT_MEM_PWR_BASE_IDX 2 11223 11224 11225// addressBlock: dce_dc_dio_dig4_afmt_afmt_dispdec 11226// base address: 0x164cc 11227#define regAFMT4_AFMT_VBI_PACKET_CONTROL 0x2474 11228#define regAFMT4_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2 11229#define regAFMT4_AFMT_AUDIO_PACKET_CONTROL2 0x2475 11230#define regAFMT4_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2 11231#define regAFMT4_AFMT_AUDIO_INFO0 0x2476 11232#define regAFMT4_AFMT_AUDIO_INFO0_BASE_IDX 2 11233#define regAFMT4_AFMT_AUDIO_INFO1 0x2477 11234#define regAFMT4_AFMT_AUDIO_INFO1_BASE_IDX 2 11235#define regAFMT4_AFMT_60958_0 0x2478 11236#define regAFMT4_AFMT_60958_0_BASE_IDX 2 11237#define regAFMT4_AFMT_60958_1 0x2479 11238#define regAFMT4_AFMT_60958_1_BASE_IDX 2 11239#define regAFMT4_AFMT_AUDIO_CRC_CONTROL 0x247a 11240#define regAFMT4_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2 11241#define regAFMT4_AFMT_RAMP_CONTROL0 0x247b 11242#define regAFMT4_AFMT_RAMP_CONTROL0_BASE_IDX 2 11243#define regAFMT4_AFMT_RAMP_CONTROL1 0x247c 11244#define regAFMT4_AFMT_RAMP_CONTROL1_BASE_IDX 2 11245#define regAFMT4_AFMT_RAMP_CONTROL2 0x247d 11246#define regAFMT4_AFMT_RAMP_CONTROL2_BASE_IDX 2 11247#define regAFMT4_AFMT_RAMP_CONTROL3 0x247e 11248#define regAFMT4_AFMT_RAMP_CONTROL3_BASE_IDX 2 11249#define regAFMT4_AFMT_60958_2 0x247f 11250#define regAFMT4_AFMT_60958_2_BASE_IDX 2 11251#define regAFMT4_AFMT_AUDIO_CRC_RESULT 0x2480 11252#define regAFMT4_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2 11253#define regAFMT4_AFMT_STATUS 0x2481 11254#define regAFMT4_AFMT_STATUS_BASE_IDX 2 11255#define regAFMT4_AFMT_AUDIO_PACKET_CONTROL 0x2482 11256#define regAFMT4_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2 11257#define regAFMT4_AFMT_INFOFRAME_CONTROL0 0x2483 11258#define regAFMT4_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2 11259#define regAFMT4_AFMT_INTERRUPT_STATUS 0x2484 11260#define regAFMT4_AFMT_INTERRUPT_STATUS_BASE_IDX 2 11261#define regAFMT4_AFMT_AUDIO_SRC_CONTROL 0x2485 11262#define regAFMT4_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2 11263#define regAFMT4_AFMT_MEM_PWR 0x2487 11264#define regAFMT4_AFMT_MEM_PWR_BASE_IDX 2 11265 11266 11267// addressBlock: dce_dc_dio_dig0_dme_dme_dispdec 11268// base address: 0x15524 11269#define regDME0_DME_CONTROL 0x2089 11270#define regDME0_DME_CONTROL_BASE_IDX 2 11271#define regDME0_DME_MEMORY_CONTROL 0x208a 11272#define regDME0_DME_MEMORY_CONTROL_BASE_IDX 2 11273 11274 11275// addressBlock: dce_dc_dio_dig0_vpg_vpg_dispdec 11276// base address: 0x154a0 11277#define regVPG0_VPG_GENERIC_PACKET_ACCESS_CTRL 0x2068 11278#define regVPG0_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2 11279#define regVPG0_VPG_GENERIC_PACKET_DATA 0x2069 11280#define regVPG0_VPG_GENERIC_PACKET_DATA_BASE_IDX 2 11281#define regVPG0_VPG_GSP_FRAME_UPDATE_CTRL 0x206a 11282#define regVPG0_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2 11283#define regVPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x206b 11284#define regVPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2 11285#define regVPG0_VPG_GENERIC_STATUS 0x206c 11286#define regVPG0_VPG_GENERIC_STATUS_BASE_IDX 2 11287#define regVPG0_VPG_MEM_PWR 0x206d 11288#define regVPG0_VPG_MEM_PWR_BASE_IDX 2 11289#define regVPG0_VPG_ISRC1_2_ACCESS_CTRL 0x206e 11290#define regVPG0_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2 11291#define regVPG0_VPG_ISRC1_2_DATA 0x206f 11292#define regVPG0_VPG_ISRC1_2_DATA_BASE_IDX 2 11293#define regVPG0_VPG_MPEG_INFO0 0x2070 11294#define regVPG0_VPG_MPEG_INFO0_BASE_IDX 2 11295#define regVPG0_VPG_MPEG_INFO1 0x2071 11296#define regVPG0_VPG_MPEG_INFO1_BASE_IDX 2 11297 11298 11299// addressBlock: dce_dc_dio_dig1_dme_dme_dispdec 11300// base address: 0x15924 11301#define regDME1_DME_CONTROL 0x2189 11302#define regDME1_DME_CONTROL_BASE_IDX 2 11303#define regDME1_DME_MEMORY_CONTROL 0x218a 11304#define regDME1_DME_MEMORY_CONTROL_BASE_IDX 2 11305 11306 11307// addressBlock: dce_dc_dio_dig1_vpg_vpg_dispdec 11308// base address: 0x158a0 11309#define regVPG1_VPG_GENERIC_PACKET_ACCESS_CTRL 0x2168 11310#define regVPG1_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2 11311#define regVPG1_VPG_GENERIC_PACKET_DATA 0x2169 11312#define regVPG1_VPG_GENERIC_PACKET_DATA_BASE_IDX 2 11313#define regVPG1_VPG_GSP_FRAME_UPDATE_CTRL 0x216a 11314#define regVPG1_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2 11315#define regVPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x216b 11316#define regVPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2 11317#define regVPG1_VPG_GENERIC_STATUS 0x216c 11318#define regVPG1_VPG_GENERIC_STATUS_BASE_IDX 2 11319#define regVPG1_VPG_MEM_PWR 0x216d 11320#define regVPG1_VPG_MEM_PWR_BASE_IDX 2 11321#define regVPG1_VPG_ISRC1_2_ACCESS_CTRL 0x216e 11322#define regVPG1_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2 11323#define regVPG1_VPG_ISRC1_2_DATA 0x216f 11324#define regVPG1_VPG_ISRC1_2_DATA_BASE_IDX 2 11325#define regVPG1_VPG_MPEG_INFO0 0x2170 11326#define regVPG1_VPG_MPEG_INFO0_BASE_IDX 2 11327#define regVPG1_VPG_MPEG_INFO1 0x2171 11328#define regVPG1_VPG_MPEG_INFO1_BASE_IDX 2 11329 11330 11331// addressBlock: dce_dc_dio_dig2_dme_dme_dispdec 11332// base address: 0x15d24 11333#define regDME2_DME_CONTROL 0x2289 11334#define regDME2_DME_CONTROL_BASE_IDX 2 11335#define regDME2_DME_MEMORY_CONTROL 0x228a 11336#define regDME2_DME_MEMORY_CONTROL_BASE_IDX 2 11337 11338 11339// addressBlock: dce_dc_dio_dig2_vpg_vpg_dispdec 11340// base address: 0x15ca0 11341#define regVPG2_VPG_GENERIC_PACKET_ACCESS_CTRL 0x2268 11342#define regVPG2_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2 11343#define regVPG2_VPG_GENERIC_PACKET_DATA 0x2269 11344#define regVPG2_VPG_GENERIC_PACKET_DATA_BASE_IDX 2 11345#define regVPG2_VPG_GSP_FRAME_UPDATE_CTRL 0x226a 11346#define regVPG2_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2 11347#define regVPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x226b 11348#define regVPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2 11349#define regVPG2_VPG_GENERIC_STATUS 0x226c 11350#define regVPG2_VPG_GENERIC_STATUS_BASE_IDX 2 11351#define regVPG2_VPG_MEM_PWR 0x226d 11352#define regVPG2_VPG_MEM_PWR_BASE_IDX 2 11353#define regVPG2_VPG_ISRC1_2_ACCESS_CTRL 0x226e 11354#define regVPG2_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2 11355#define regVPG2_VPG_ISRC1_2_DATA 0x226f 11356#define regVPG2_VPG_ISRC1_2_DATA_BASE_IDX 2 11357#define regVPG2_VPG_MPEG_INFO0 0x2270 11358#define regVPG2_VPG_MPEG_INFO0_BASE_IDX 2 11359#define regVPG2_VPG_MPEG_INFO1 0x2271 11360#define regVPG2_VPG_MPEG_INFO1_BASE_IDX 2 11361 11362 11363// addressBlock: dce_dc_dio_dig3_dme_dme_dispdec 11364// base address: 0x16124 11365#define regDME3_DME_CONTROL 0x2389 11366#define regDME3_DME_CONTROL_BASE_IDX 2 11367#define regDME3_DME_MEMORY_CONTROL 0x238a 11368#define regDME3_DME_MEMORY_CONTROL_BASE_IDX 2 11369 11370 11371// addressBlock: dce_dc_dio_dig3_vpg_vpg_dispdec 11372// base address: 0x160a0 11373#define regVPG3_VPG_GENERIC_PACKET_ACCESS_CTRL 0x2368 11374#define regVPG3_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2 11375#define regVPG3_VPG_GENERIC_PACKET_DATA 0x2369 11376#define regVPG3_VPG_GENERIC_PACKET_DATA_BASE_IDX 2 11377#define regVPG3_VPG_GSP_FRAME_UPDATE_CTRL 0x236a 11378#define regVPG3_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2 11379#define regVPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x236b 11380#define regVPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2 11381#define regVPG3_VPG_GENERIC_STATUS 0x236c 11382#define regVPG3_VPG_GENERIC_STATUS_BASE_IDX 2 11383#define regVPG3_VPG_MEM_PWR 0x236d 11384#define regVPG3_VPG_MEM_PWR_BASE_IDX 2 11385#define regVPG3_VPG_ISRC1_2_ACCESS_CTRL 0x236e 11386#define regVPG3_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2 11387#define regVPG3_VPG_ISRC1_2_DATA 0x236f 11388#define regVPG3_VPG_ISRC1_2_DATA_BASE_IDX 2 11389#define regVPG3_VPG_MPEG_INFO0 0x2370 11390#define regVPG3_VPG_MPEG_INFO0_BASE_IDX 2 11391#define regVPG3_VPG_MPEG_INFO1 0x2371 11392#define regVPG3_VPG_MPEG_INFO1_BASE_IDX 2 11393 11394 11395// addressBlock: dce_dc_dio_dig4_dme_dme_dispdec 11396// base address: 0x16524 11397#define regDME4_DME_CONTROL 0x2489 11398#define regDME4_DME_CONTROL_BASE_IDX 2 11399#define regDME4_DME_MEMORY_CONTROL 0x248a 11400#define regDME4_DME_MEMORY_CONTROL_BASE_IDX 2 11401 11402 11403// addressBlock: dce_dc_dio_dig4_vpg_vpg_dispdec 11404// base address: 0x164a0 11405#define regVPG4_VPG_GENERIC_PACKET_ACCESS_CTRL 0x2468 11406#define regVPG4_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2 11407#define regVPG4_VPG_GENERIC_PACKET_DATA 0x2469 11408#define regVPG4_VPG_GENERIC_PACKET_DATA_BASE_IDX 2 11409#define regVPG4_VPG_GSP_FRAME_UPDATE_CTRL 0x246a 11410#define regVPG4_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2 11411#define regVPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x246b 11412#define regVPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2 11413#define regVPG4_VPG_GENERIC_STATUS 0x246c 11414#define regVPG4_VPG_GENERIC_STATUS_BASE_IDX 2 11415#define regVPG4_VPG_MEM_PWR 0x246d 11416#define regVPG4_VPG_MEM_PWR_BASE_IDX 2 11417#define regVPG4_VPG_ISRC1_2_ACCESS_CTRL 0x246e 11418#define regVPG4_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2 11419#define regVPG4_VPG_ISRC1_2_DATA 0x246f 11420#define regVPG4_VPG_ISRC1_2_DATA_BASE_IDX 2 11421#define regVPG4_VPG_MPEG_INFO0 0x2470 11422#define regVPG4_VPG_MPEG_INFO0_BASE_IDX 2 11423#define regVPG4_VPG_MPEG_INFO1 0x2471 11424#define regVPG4_VPG_MPEG_INFO1_BASE_IDX 2 11425 11426 11427// addressBlock: dce_dc_dio_dp_aux0_dispdec 11428// base address: 0x0 11429#define regDP_AUX0_AUX_CONTROL 0x1f50 11430#define regDP_AUX0_AUX_CONTROL_BASE_IDX 2 11431#define regDP_AUX0_AUX_SW_CONTROL 0x1f51 11432#define regDP_AUX0_AUX_SW_CONTROL_BASE_IDX 2 11433#define regDP_AUX0_AUX_ARB_CONTROL 0x1f52 11434#define regDP_AUX0_AUX_ARB_CONTROL_BASE_IDX 2 11435#define regDP_AUX0_AUX_INTERRUPT_CONTROL 0x1f53 11436#define regDP_AUX0_AUX_INTERRUPT_CONTROL_BASE_IDX 2 11437#define regDP_AUX0_AUX_SW_STATUS 0x1f54 11438#define regDP_AUX0_AUX_SW_STATUS_BASE_IDX 2 11439#define regDP_AUX0_AUX_LS_STATUS 0x1f55 11440#define regDP_AUX0_AUX_LS_STATUS_BASE_IDX 2 11441#define regDP_AUX0_AUX_SW_DATA 0x1f56 11442#define regDP_AUX0_AUX_SW_DATA_BASE_IDX 2 11443#define regDP_AUX0_AUX_LS_DATA 0x1f57 11444#define regDP_AUX0_AUX_LS_DATA_BASE_IDX 2 11445#define regDP_AUX0_AUX_DPHY_TX_REF_CONTROL 0x1f58 11446#define regDP_AUX0_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2 11447#define regDP_AUX0_AUX_DPHY_TX_CONTROL 0x1f59 11448#define regDP_AUX0_AUX_DPHY_TX_CONTROL_BASE_IDX 2 11449#define regDP_AUX0_AUX_DPHY_RX_CONTROL0 0x1f5a 11450#define regDP_AUX0_AUX_DPHY_RX_CONTROL0_BASE_IDX 2 11451#define regDP_AUX0_AUX_DPHY_RX_CONTROL1 0x1f5b 11452#define regDP_AUX0_AUX_DPHY_RX_CONTROL1_BASE_IDX 2 11453#define regDP_AUX0_AUX_DPHY_TX_STATUS 0x1f5c 11454#define regDP_AUX0_AUX_DPHY_TX_STATUS_BASE_IDX 2 11455#define regDP_AUX0_AUX_DPHY_RX_STATUS 0x1f5d 11456#define regDP_AUX0_AUX_DPHY_RX_STATUS_BASE_IDX 2 11457#define regDP_AUX0_AUX_GTC_SYNC_CONTROL 0x1f5e 11458#define regDP_AUX0_AUX_GTC_SYNC_CONTROL_BASE_IDX 2 11459#define regDP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL 0x1f5f 11460#define regDP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2 11461#define regDP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1f60 11462#define regDP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2 11463#define regDP_AUX0_AUX_GTC_SYNC_STATUS 0x1f61 11464#define regDP_AUX0_AUX_GTC_SYNC_STATUS_BASE_IDX 2 11465#define regDP_AUX0_AUX_PHY_WAKE_CNTL 0x1f66 11466#define regDP_AUX0_AUX_PHY_WAKE_CNTL_BASE_IDX 2 11467 11468 11469// addressBlock: dce_dc_dio_dp_aux1_dispdec 11470// base address: 0x70 11471#define regDP_AUX1_AUX_CONTROL 0x1f6c 11472#define regDP_AUX1_AUX_CONTROL_BASE_IDX 2 11473#define regDP_AUX1_AUX_SW_CONTROL 0x1f6d 11474#define regDP_AUX1_AUX_SW_CONTROL_BASE_IDX 2 11475#define regDP_AUX1_AUX_ARB_CONTROL 0x1f6e 11476#define regDP_AUX1_AUX_ARB_CONTROL_BASE_IDX 2 11477#define regDP_AUX1_AUX_INTERRUPT_CONTROL 0x1f6f 11478#define regDP_AUX1_AUX_INTERRUPT_CONTROL_BASE_IDX 2 11479#define regDP_AUX1_AUX_SW_STATUS 0x1f70 11480#define regDP_AUX1_AUX_SW_STATUS_BASE_IDX 2 11481#define regDP_AUX1_AUX_LS_STATUS 0x1f71 11482#define regDP_AUX1_AUX_LS_STATUS_BASE_IDX 2 11483#define regDP_AUX1_AUX_SW_DATA 0x1f72 11484#define regDP_AUX1_AUX_SW_DATA_BASE_IDX 2 11485#define regDP_AUX1_AUX_LS_DATA 0x1f73 11486#define regDP_AUX1_AUX_LS_DATA_BASE_IDX 2 11487#define regDP_AUX1_AUX_DPHY_TX_REF_CONTROL 0x1f74 11488#define regDP_AUX1_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2 11489#define regDP_AUX1_AUX_DPHY_TX_CONTROL 0x1f75 11490#define regDP_AUX1_AUX_DPHY_TX_CONTROL_BASE_IDX 2 11491#define regDP_AUX1_AUX_DPHY_RX_CONTROL0 0x1f76 11492#define regDP_AUX1_AUX_DPHY_RX_CONTROL0_BASE_IDX 2 11493#define regDP_AUX1_AUX_DPHY_RX_CONTROL1 0x1f77 11494#define regDP_AUX1_AUX_DPHY_RX_CONTROL1_BASE_IDX 2 11495#define regDP_AUX1_AUX_DPHY_TX_STATUS 0x1f78 11496#define regDP_AUX1_AUX_DPHY_TX_STATUS_BASE_IDX 2 11497#define regDP_AUX1_AUX_DPHY_RX_STATUS 0x1f79 11498#define regDP_AUX1_AUX_DPHY_RX_STATUS_BASE_IDX 2 11499#define regDP_AUX1_AUX_GTC_SYNC_CONTROL 0x1f7a 11500#define regDP_AUX1_AUX_GTC_SYNC_CONTROL_BASE_IDX 2 11501#define regDP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL 0x1f7b 11502#define regDP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2 11503#define regDP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1f7c 11504#define regDP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2 11505#define regDP_AUX1_AUX_GTC_SYNC_STATUS 0x1f7d 11506#define regDP_AUX1_AUX_GTC_SYNC_STATUS_BASE_IDX 2 11507#define regDP_AUX1_AUX_PHY_WAKE_CNTL 0x1f82 11508#define regDP_AUX1_AUX_PHY_WAKE_CNTL_BASE_IDX 2 11509 11510 11511// addressBlock: dce_dc_dio_dp_aux2_dispdec 11512// base address: 0xe0 11513#define regDP_AUX2_AUX_CONTROL 0x1f88 11514#define regDP_AUX2_AUX_CONTROL_BASE_IDX 2 11515#define regDP_AUX2_AUX_SW_CONTROL 0x1f89 11516#define regDP_AUX2_AUX_SW_CONTROL_BASE_IDX 2 11517#define regDP_AUX2_AUX_ARB_CONTROL 0x1f8a 11518#define regDP_AUX2_AUX_ARB_CONTROL_BASE_IDX 2 11519#define regDP_AUX2_AUX_INTERRUPT_CONTROL 0x1f8b 11520#define regDP_AUX2_AUX_INTERRUPT_CONTROL_BASE_IDX 2 11521#define regDP_AUX2_AUX_SW_STATUS 0x1f8c 11522#define regDP_AUX2_AUX_SW_STATUS_BASE_IDX 2 11523#define regDP_AUX2_AUX_LS_STATUS 0x1f8d 11524#define regDP_AUX2_AUX_LS_STATUS_BASE_IDX 2 11525#define regDP_AUX2_AUX_SW_DATA 0x1f8e 11526#define regDP_AUX2_AUX_SW_DATA_BASE_IDX 2 11527#define regDP_AUX2_AUX_LS_DATA 0x1f8f 11528#define regDP_AUX2_AUX_LS_DATA_BASE_IDX 2 11529#define regDP_AUX2_AUX_DPHY_TX_REF_CONTROL 0x1f90 11530#define regDP_AUX2_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2 11531#define regDP_AUX2_AUX_DPHY_TX_CONTROL 0x1f91 11532#define regDP_AUX2_AUX_DPHY_TX_CONTROL_BASE_IDX 2 11533#define regDP_AUX2_AUX_DPHY_RX_CONTROL0 0x1f92 11534#define regDP_AUX2_AUX_DPHY_RX_CONTROL0_BASE_IDX 2 11535#define regDP_AUX2_AUX_DPHY_RX_CONTROL1 0x1f93 11536#define regDP_AUX2_AUX_DPHY_RX_CONTROL1_BASE_IDX 2 11537#define regDP_AUX2_AUX_DPHY_TX_STATUS 0x1f94 11538#define regDP_AUX2_AUX_DPHY_TX_STATUS_BASE_IDX 2 11539#define regDP_AUX2_AUX_DPHY_RX_STATUS 0x1f95 11540#define regDP_AUX2_AUX_DPHY_RX_STATUS_BASE_IDX 2 11541#define regDP_AUX2_AUX_GTC_SYNC_CONTROL 0x1f96 11542#define regDP_AUX2_AUX_GTC_SYNC_CONTROL_BASE_IDX 2 11543#define regDP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL 0x1f97 11544#define regDP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2 11545#define regDP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1f98 11546#define regDP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2 11547#define regDP_AUX2_AUX_GTC_SYNC_STATUS 0x1f99 11548#define regDP_AUX2_AUX_GTC_SYNC_STATUS_BASE_IDX 2 11549#define regDP_AUX2_AUX_PHY_WAKE_CNTL 0x1f9e 11550#define regDP_AUX2_AUX_PHY_WAKE_CNTL_BASE_IDX 2 11551 11552 11553// addressBlock: dce_dc_dio_dp_aux3_dispdec 11554// base address: 0x150 11555#define regDP_AUX3_AUX_CONTROL 0x1fa4 11556#define regDP_AUX3_AUX_CONTROL_BASE_IDX 2 11557#define regDP_AUX3_AUX_SW_CONTROL 0x1fa5 11558#define regDP_AUX3_AUX_SW_CONTROL_BASE_IDX 2 11559#define regDP_AUX3_AUX_ARB_CONTROL 0x1fa6 11560#define regDP_AUX3_AUX_ARB_CONTROL_BASE_IDX 2 11561#define regDP_AUX3_AUX_INTERRUPT_CONTROL 0x1fa7 11562#define regDP_AUX3_AUX_INTERRUPT_CONTROL_BASE_IDX 2 11563#define regDP_AUX3_AUX_SW_STATUS 0x1fa8 11564#define regDP_AUX3_AUX_SW_STATUS_BASE_IDX 2 11565#define regDP_AUX3_AUX_LS_STATUS 0x1fa9 11566#define regDP_AUX3_AUX_LS_STATUS_BASE_IDX 2 11567#define regDP_AUX3_AUX_SW_DATA 0x1faa 11568#define regDP_AUX3_AUX_SW_DATA_BASE_IDX 2 11569#define regDP_AUX3_AUX_LS_DATA 0x1fab 11570#define regDP_AUX3_AUX_LS_DATA_BASE_IDX 2 11571#define regDP_AUX3_AUX_DPHY_TX_REF_CONTROL 0x1fac 11572#define regDP_AUX3_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2 11573#define regDP_AUX3_AUX_DPHY_TX_CONTROL 0x1fad 11574#define regDP_AUX3_AUX_DPHY_TX_CONTROL_BASE_IDX 2 11575#define regDP_AUX3_AUX_DPHY_RX_CONTROL0 0x1fae 11576#define regDP_AUX3_AUX_DPHY_RX_CONTROL0_BASE_IDX 2 11577#define regDP_AUX3_AUX_DPHY_RX_CONTROL1 0x1faf 11578#define regDP_AUX3_AUX_DPHY_RX_CONTROL1_BASE_IDX 2 11579#define regDP_AUX3_AUX_DPHY_TX_STATUS 0x1fb0 11580#define regDP_AUX3_AUX_DPHY_TX_STATUS_BASE_IDX 2 11581#define regDP_AUX3_AUX_DPHY_RX_STATUS 0x1fb1 11582#define regDP_AUX3_AUX_DPHY_RX_STATUS_BASE_IDX 2 11583#define regDP_AUX3_AUX_GTC_SYNC_CONTROL 0x1fb2 11584#define regDP_AUX3_AUX_GTC_SYNC_CONTROL_BASE_IDX 2 11585#define regDP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL 0x1fb3 11586#define regDP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2 11587#define regDP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1fb4 11588#define regDP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2 11589#define regDP_AUX3_AUX_GTC_SYNC_STATUS 0x1fb5 11590#define regDP_AUX3_AUX_GTC_SYNC_STATUS_BASE_IDX 2 11591#define regDP_AUX3_AUX_PHY_WAKE_CNTL 0x1fba 11592#define regDP_AUX3_AUX_PHY_WAKE_CNTL_BASE_IDX 2 11593 11594 11595// addressBlock: dce_dc_dio_dp_aux4_dispdec 11596// base address: 0x1c0 11597#define regDP_AUX4_AUX_CONTROL 0x1fc0 11598#define regDP_AUX4_AUX_CONTROL_BASE_IDX 2 11599#define regDP_AUX4_AUX_SW_CONTROL 0x1fc1 11600#define regDP_AUX4_AUX_SW_CONTROL_BASE_IDX 2 11601#define regDP_AUX4_AUX_ARB_CONTROL 0x1fc2 11602#define regDP_AUX4_AUX_ARB_CONTROL_BASE_IDX 2 11603#define regDP_AUX4_AUX_INTERRUPT_CONTROL 0x1fc3 11604#define regDP_AUX4_AUX_INTERRUPT_CONTROL_BASE_IDX 2 11605#define regDP_AUX4_AUX_SW_STATUS 0x1fc4 11606#define regDP_AUX4_AUX_SW_STATUS_BASE_IDX 2 11607#define regDP_AUX4_AUX_LS_STATUS 0x1fc5 11608#define regDP_AUX4_AUX_LS_STATUS_BASE_IDX 2 11609#define regDP_AUX4_AUX_SW_DATA 0x1fc6 11610#define regDP_AUX4_AUX_SW_DATA_BASE_IDX 2 11611#define regDP_AUX4_AUX_LS_DATA 0x1fc7 11612#define regDP_AUX4_AUX_LS_DATA_BASE_IDX 2 11613#define regDP_AUX4_AUX_DPHY_TX_REF_CONTROL 0x1fc8 11614#define regDP_AUX4_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2 11615#define regDP_AUX4_AUX_DPHY_TX_CONTROL 0x1fc9 11616#define regDP_AUX4_AUX_DPHY_TX_CONTROL_BASE_IDX 2 11617#define regDP_AUX4_AUX_DPHY_RX_CONTROL0 0x1fca 11618#define regDP_AUX4_AUX_DPHY_RX_CONTROL0_BASE_IDX 2 11619#define regDP_AUX4_AUX_DPHY_RX_CONTROL1 0x1fcb 11620#define regDP_AUX4_AUX_DPHY_RX_CONTROL1_BASE_IDX 2 11621#define regDP_AUX4_AUX_DPHY_TX_STATUS 0x1fcc 11622#define regDP_AUX4_AUX_DPHY_TX_STATUS_BASE_IDX 2 11623#define regDP_AUX4_AUX_DPHY_RX_STATUS 0x1fcd 11624#define regDP_AUX4_AUX_DPHY_RX_STATUS_BASE_IDX 2 11625#define regDP_AUX4_AUX_GTC_SYNC_CONTROL 0x1fce 11626#define regDP_AUX4_AUX_GTC_SYNC_CONTROL_BASE_IDX 2 11627#define regDP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL 0x1fcf 11628#define regDP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2 11629#define regDP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1fd0 11630#define regDP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2 11631#define regDP_AUX4_AUX_GTC_SYNC_STATUS 0x1fd1 11632#define regDP_AUX4_AUX_GTC_SYNC_STATUS_BASE_IDX 2 11633#define regDP_AUX4_AUX_PHY_WAKE_CNTL 0x1fd6 11634#define regDP_AUX4_AUX_PHY_WAKE_CNTL_BASE_IDX 2 11635 11636 11637// addressBlock: dce_dc_dio_dout_i2c_dispdec 11638// base address: 0x0 11639#define regDC_I2C_CONTROL 0x1e98 11640#define regDC_I2C_CONTROL_BASE_IDX 2 11641#define regDC_I2C_ARBITRATION 0x1e99 11642#define regDC_I2C_ARBITRATION_BASE_IDX 2 11643#define regDC_I2C_INTERRUPT_CONTROL 0x1e9a 11644#define regDC_I2C_INTERRUPT_CONTROL_BASE_IDX 2 11645#define regDC_I2C_SW_STATUS 0x1e9b 11646#define regDC_I2C_SW_STATUS_BASE_IDX 2 11647#define regDC_I2C_DDC1_HW_STATUS 0x1e9c 11648#define regDC_I2C_DDC1_HW_STATUS_BASE_IDX 2 11649#define regDC_I2C_DDC2_HW_STATUS 0x1e9d 11650#define regDC_I2C_DDC2_HW_STATUS_BASE_IDX 2 11651#define regDC_I2C_DDC3_HW_STATUS 0x1e9e 11652#define regDC_I2C_DDC3_HW_STATUS_BASE_IDX 2 11653#define regDC_I2C_DDC4_HW_STATUS 0x1e9f 11654#define regDC_I2C_DDC4_HW_STATUS_BASE_IDX 2 11655#define regDC_I2C_DDC5_HW_STATUS 0x1ea0 11656#define regDC_I2C_DDC5_HW_STATUS_BASE_IDX 2 11657#define regDC_I2C_DDC1_SPEED 0x1ea2 11658#define regDC_I2C_DDC1_SPEED_BASE_IDX 2 11659#define regDC_I2C_DDC1_SETUP 0x1ea3 11660#define regDC_I2C_DDC1_SETUP_BASE_IDX 2 11661#define regDC_I2C_DDC2_SPEED 0x1ea4 11662#define regDC_I2C_DDC2_SPEED_BASE_IDX 2 11663#define regDC_I2C_DDC2_SETUP 0x1ea5 11664#define regDC_I2C_DDC2_SETUP_BASE_IDX 2 11665#define regDC_I2C_DDC3_SPEED 0x1ea6 11666#define regDC_I2C_DDC3_SPEED_BASE_IDX 2 11667#define regDC_I2C_DDC3_SETUP 0x1ea7 11668#define regDC_I2C_DDC3_SETUP_BASE_IDX 2 11669#define regDC_I2C_DDC4_SPEED 0x1ea8 11670#define regDC_I2C_DDC4_SPEED_BASE_IDX 2 11671#define regDC_I2C_DDC4_SETUP 0x1ea9 11672#define regDC_I2C_DDC4_SETUP_BASE_IDX 2 11673#define regDC_I2C_DDC5_SPEED 0x1eaa 11674#define regDC_I2C_DDC5_SPEED_BASE_IDX 2 11675#define regDC_I2C_DDC5_SETUP 0x1eab 11676#define regDC_I2C_DDC5_SETUP_BASE_IDX 2 11677#define regDC_I2C_TRANSACTION0 0x1eae 11678#define regDC_I2C_TRANSACTION0_BASE_IDX 2 11679#define regDC_I2C_TRANSACTION1 0x1eaf 11680#define regDC_I2C_TRANSACTION1_BASE_IDX 2 11681#define regDC_I2C_TRANSACTION2 0x1eb0 11682#define regDC_I2C_TRANSACTION2_BASE_IDX 2 11683#define regDC_I2C_TRANSACTION3 0x1eb1 11684#define regDC_I2C_TRANSACTION3_BASE_IDX 2 11685#define regDC_I2C_DATA 0x1eb2 11686#define regDC_I2C_DATA_BASE_IDX 2 11687#define regDC_I2C_EDID_DETECT_CTRL 0x1eb6 11688#define regDC_I2C_EDID_DETECT_CTRL_BASE_IDX 2 11689#define regDC_I2C_READ_REQUEST_INTERRUPT 0x1eb7 11690#define regDC_I2C_READ_REQUEST_INTERRUPT_BASE_IDX 2 11691 11692 11693// addressBlock: dce_dc_dio_dio_misc_dispdec 11694// base address: 0x0 11695#define regDIO_SCRATCH0 0x1eca 11696#define regDIO_SCRATCH0_BASE_IDX 2 11697#define regDIO_SCRATCH1 0x1ecb 11698#define regDIO_SCRATCH1_BASE_IDX 2 11699#define regDIO_SCRATCH2 0x1ecc 11700#define regDIO_SCRATCH2_BASE_IDX 2 11701#define regDIO_SCRATCH3 0x1ecd 11702#define regDIO_SCRATCH3_BASE_IDX 2 11703#define regDIO_SCRATCH4 0x1ece 11704#define regDIO_SCRATCH4_BASE_IDX 2 11705#define regDIO_SCRATCH5 0x1ecf 11706#define regDIO_SCRATCH5_BASE_IDX 2 11707#define regDIO_SCRATCH6 0x1ed0 11708#define regDIO_SCRATCH6_BASE_IDX 2 11709#define regDIO_SCRATCH7 0x1ed1 11710#define regDIO_SCRATCH7_BASE_IDX 2 11711#define regDIO_MEM_PWR_STATUS 0x1edd 11712#define regDIO_MEM_PWR_STATUS_BASE_IDX 2 11713#define regDIO_MEM_PWR_CTRL 0x1ede 11714#define regDIO_MEM_PWR_CTRL_BASE_IDX 2 11715#define regDIO_MEM_PWR_CTRL2 0x1edf 11716#define regDIO_MEM_PWR_CTRL2_BASE_IDX 2 11717#define regDIO_CLK_CNTL 0x1ee0 11718#define regDIO_CLK_CNTL_BASE_IDX 2 11719#define regDIO_POWER_MANAGEMENT_CNTL 0x1ee4 11720#define regDIO_POWER_MANAGEMENT_CNTL_BASE_IDX 2 11721#define regDIG_SOFT_RESET 0x1eee 11722#define regDIG_SOFT_RESET_BASE_IDX 2 11723#define regDIO_CLK_CNTL2 0x1ef2 11724#define regDIO_CLK_CNTL2_BASE_IDX 2 11725#define regDIO_CLK_CNTL3 0x1ef3 11726#define regDIO_CLK_CNTL3_BASE_IDX 2 11727#define regDIO_HDMI_RXSTATUS_TIMER_CONTROL 0x1eff 11728#define regDIO_HDMI_RXSTATUS_TIMER_CONTROL_BASE_IDX 2 11729#define regDIO_GENERIC_INTERRUPT_MESSAGE 0x1f02 11730#define regDIO_GENERIC_INTERRUPT_MESSAGE_BASE_IDX 2 11731#define regDIO_GENERIC_INTERRUPT_CLEAR 0x1f03 11732#define regDIO_GENERIC_INTERRUPT_CLEAR_BASE_IDX 2 11733#define regDIO_LINKA_CNTL 0x1f04 11734#define regDIO_LINKA_CNTL_BASE_IDX 2 11735#define regDIO_LINKB_CNTL 0x1f05 11736#define regDIO_LINKB_CNTL_BASE_IDX 2 11737#define regDIO_LINKC_CNTL 0x1f06 11738#define regDIO_LINKC_CNTL_BASE_IDX 2 11739#define regDIO_LINKD_CNTL 0x1f07 11740#define regDIO_LINKD_CNTL_BASE_IDX 2 11741#define regDIO_LINKE_CNTL 0x1f08 11742#define regDIO_LINKE_CNTL_BASE_IDX 2 11743#define regDIO_LINKF_CNTL 0x1f09 11744#define regDIO_LINKF_CNTL_BASE_IDX 2 11745 11746 11747// addressBlock: dce_dc_dio_dio_dcperfmon_dc_perfmon_dispdec 11748// base address: 0x7d10 11749#define regDC_PERFMON18_PERFCOUNTER_CNTL 0x1f44 11750#define regDC_PERFMON18_PERFCOUNTER_CNTL_BASE_IDX 2 11751#define regDC_PERFMON18_PERFCOUNTER_CNTL2 0x1f45 11752#define regDC_PERFMON18_PERFCOUNTER_CNTL2_BASE_IDX 2 11753#define regDC_PERFMON18_PERFCOUNTER_STATE 0x1f46 11754#define regDC_PERFMON18_PERFCOUNTER_STATE_BASE_IDX 2 11755#define regDC_PERFMON18_PERFMON_CNTL 0x1f47 11756#define regDC_PERFMON18_PERFMON_CNTL_BASE_IDX 2 11757#define regDC_PERFMON18_PERFMON_CNTL2 0x1f48 11758#define regDC_PERFMON18_PERFMON_CNTL2_BASE_IDX 2 11759#define regDC_PERFMON18_PERFMON_CVALUE_INT_MISC 0x1f49 11760#define regDC_PERFMON18_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 11761#define regDC_PERFMON18_PERFMON_CVALUE_LOW 0x1f4a 11762#define regDC_PERFMON18_PERFMON_CVALUE_LOW_BASE_IDX 2 11763#define regDC_PERFMON18_PERFMON_HI 0x1f4b 11764#define regDC_PERFMON18_PERFMON_HI_BASE_IDX 2 11765#define regDC_PERFMON18_PERFMON_LOW 0x1f4c 11766#define regDC_PERFMON18_PERFMON_LOW_BASE_IDX 2 11767 11768 11769// addressBlock: dce_dc_dcio_dcio_dispdec 11770// base address: 0x0 11771#define regDC_GENERICA 0x2868 11772#define regDC_GENERICA_BASE_IDX 2 11773#define regDC_GENERICB 0x2869 11774#define regDC_GENERICB_BASE_IDX 2 11775#define regDCIO_CLOCK_CNTL 0x286a 11776#define regDCIO_CLOCK_CNTL_BASE_IDX 2 11777#define regDC_REF_CLK_CNTL 0x286b 11778#define regDC_REF_CLK_CNTL_BASE_IDX 2 11779#define regUNIPHYA_LINK_CNTL 0x286d 11780#define regUNIPHYA_LINK_CNTL_BASE_IDX 2 11781#define regUNIPHYA_CHANNEL_XBAR_CNTL 0x286e 11782#define regUNIPHYA_CHANNEL_XBAR_CNTL_BASE_IDX 2 11783#define regUNIPHYB_LINK_CNTL 0x286f 11784#define regUNIPHYB_LINK_CNTL_BASE_IDX 2 11785#define regUNIPHYB_CHANNEL_XBAR_CNTL 0x2870 11786#define regUNIPHYB_CHANNEL_XBAR_CNTL_BASE_IDX 2 11787#define regUNIPHYC_LINK_CNTL 0x2871 11788#define regUNIPHYC_LINK_CNTL_BASE_IDX 2 11789#define regUNIPHYC_CHANNEL_XBAR_CNTL 0x2872 11790#define regUNIPHYC_CHANNEL_XBAR_CNTL_BASE_IDX 2 11791#define regUNIPHYD_LINK_CNTL 0x2873 11792#define regUNIPHYD_LINK_CNTL_BASE_IDX 2 11793#define regUNIPHYD_CHANNEL_XBAR_CNTL 0x2874 11794#define regUNIPHYD_CHANNEL_XBAR_CNTL_BASE_IDX 2 11795#define regUNIPHYE_LINK_CNTL 0x2875 11796#define regUNIPHYE_LINK_CNTL_BASE_IDX 2 11797#define regUNIPHYE_CHANNEL_XBAR_CNTL 0x2876 11798#define regUNIPHYE_CHANNEL_XBAR_CNTL_BASE_IDX 2 11799#define regDCIO_WRCMD_DELAY 0x287e 11800#define regDCIO_WRCMD_DELAY_BASE_IDX 2 11801#define regDC_PINSTRAPS 0x2880 11802#define regDC_PINSTRAPS_BASE_IDX 2 11803#define regINTERCEPT_STATE 0x2884 11804#define regINTERCEPT_STATE_BASE_IDX 2 11805#define regDCIO_BL_PWM_FRAME_START_DISP_SEL 0x288b 11806#define regDCIO_BL_PWM_FRAME_START_DISP_SEL_BASE_IDX 2 11807#define regDCIO_GSL_GENLK_PAD_CNTL 0x288c 11808#define regDCIO_GSL_GENLK_PAD_CNTL_BASE_IDX 2 11809#define regDCIO_GSL_SWAPLOCK_PAD_CNTL 0x288d 11810#define regDCIO_GSL_SWAPLOCK_PAD_CNTL_BASE_IDX 2 11811#define regDCIO_SOFT_RESET 0x289e 11812#define regDCIO_SOFT_RESET_BASE_IDX 2 11813 11814 11815// addressBlock: dce_dc_dcio_dcio_chip_dispdec 11816// base address: 0x0 11817#define regDC_GPIO_GENERIC_MASK 0x28c8 11818#define regDC_GPIO_GENERIC_MASK_BASE_IDX 2 11819#define regDC_GPIO_GENERIC_A 0x28c9 11820#define regDC_GPIO_GENERIC_A_BASE_IDX 2 11821#define regDC_GPIO_GENERIC_EN 0x28ca 11822#define regDC_GPIO_GENERIC_EN_BASE_IDX 2 11823#define regDC_GPIO_GENERIC_Y 0x28cb 11824#define regDC_GPIO_GENERIC_Y_BASE_IDX 2 11825#define regDC_GPIO_DDC1_MASK 0x28d0 11826#define regDC_GPIO_DDC1_MASK_BASE_IDX 2 11827#define regDC_GPIO_DDC1_A 0x28d1 11828#define regDC_GPIO_DDC1_A_BASE_IDX 2 11829#define regDC_GPIO_DDC1_EN 0x28d2 11830#define regDC_GPIO_DDC1_EN_BASE_IDX 2 11831#define regDC_GPIO_DDC1_Y 0x28d3 11832#define regDC_GPIO_DDC1_Y_BASE_IDX 2 11833#define regDC_GPIO_DDC2_MASK 0x28d4 11834#define regDC_GPIO_DDC2_MASK_BASE_IDX 2 11835#define regDC_GPIO_DDC2_A 0x28d5 11836#define regDC_GPIO_DDC2_A_BASE_IDX 2 11837#define regDC_GPIO_DDC2_EN 0x28d6 11838#define regDC_GPIO_DDC2_EN_BASE_IDX 2 11839#define regDC_GPIO_DDC2_Y 0x28d7 11840#define regDC_GPIO_DDC2_Y_BASE_IDX 2 11841#define regDC_GPIO_DDC3_MASK 0x28d8 11842#define regDC_GPIO_DDC3_MASK_BASE_IDX 2 11843#define regDC_GPIO_DDC3_A 0x28d9 11844#define regDC_GPIO_DDC3_A_BASE_IDX 2 11845#define regDC_GPIO_DDC3_EN 0x28da 11846#define regDC_GPIO_DDC3_EN_BASE_IDX 2 11847#define regDC_GPIO_DDC3_Y 0x28db 11848#define regDC_GPIO_DDC3_Y_BASE_IDX 2 11849#define regDC_GPIO_DDC4_MASK 0x28dc 11850#define regDC_GPIO_DDC4_MASK_BASE_IDX 2 11851#define regDC_GPIO_DDC4_A 0x28dd 11852#define regDC_GPIO_DDC4_A_BASE_IDX 2 11853#define regDC_GPIO_DDC4_EN 0x28de 11854#define regDC_GPIO_DDC4_EN_BASE_IDX 2 11855#define regDC_GPIO_DDC4_Y 0x28df 11856#define regDC_GPIO_DDC4_Y_BASE_IDX 2 11857#define regDC_GPIO_DDC5_MASK 0x28e0 11858#define regDC_GPIO_DDC5_MASK_BASE_IDX 2 11859#define regDC_GPIO_DDC5_A 0x28e1 11860#define regDC_GPIO_DDC5_A_BASE_IDX 2 11861#define regDC_GPIO_DDC5_EN 0x28e2 11862#define regDC_GPIO_DDC5_EN_BASE_IDX 2 11863#define regDC_GPIO_DDC5_Y 0x28e3 11864#define regDC_GPIO_DDC5_Y_BASE_IDX 2 11865#define regDC_GPIO_DDCVGA_MASK 0x28e8 11866#define regDC_GPIO_DDCVGA_MASK_BASE_IDX 2 11867#define regDC_GPIO_DDCVGA_A 0x28e9 11868#define regDC_GPIO_DDCVGA_A_BASE_IDX 2 11869#define regDC_GPIO_DDCVGA_EN 0x28ea 11870#define regDC_GPIO_DDCVGA_EN_BASE_IDX 2 11871#define regDC_GPIO_DDCVGA_Y 0x28eb 11872#define regDC_GPIO_DDCVGA_Y_BASE_IDX 2 11873#define regDC_GPIO_GENLK_MASK 0x28f0 11874#define regDC_GPIO_GENLK_MASK_BASE_IDX 2 11875#define regDC_GPIO_GENLK_A 0x28f1 11876#define regDC_GPIO_GENLK_A_BASE_IDX 2 11877#define regDC_GPIO_GENLK_EN 0x28f2 11878#define regDC_GPIO_GENLK_EN_BASE_IDX 2 11879#define regDC_GPIO_GENLK_Y 0x28f3 11880#define regDC_GPIO_GENLK_Y_BASE_IDX 2 11881#define regDC_GPIO_HPD_MASK 0x28f4 11882#define regDC_GPIO_HPD_MASK_BASE_IDX 2 11883#define regDC_GPIO_HPD_A 0x28f5 11884#define regDC_GPIO_HPD_A_BASE_IDX 2 11885#define regDC_GPIO_HPD_EN 0x28f6 11886#define regDC_GPIO_HPD_EN_BASE_IDX 2 11887#define regDC_GPIO_HPD_Y 0x28f7 11888#define regDC_GPIO_HPD_Y_BASE_IDX 2 11889#define regDC_GPIO_PWRSEQ0_EN 0x28fa 11890#define regDC_GPIO_PWRSEQ0_EN_BASE_IDX 2 11891#define regDC_GPIO_PAD_STRENGTH_1 0x28fc 11892#define regDC_GPIO_PAD_STRENGTH_1_BASE_IDX 2 11893#define regDC_GPIO_PAD_STRENGTH_2 0x28fd 11894#define regDC_GPIO_PAD_STRENGTH_2_BASE_IDX 2 11895#define regPHY_AUX_CNTL 0x28ff 11896#define regPHY_AUX_CNTL_BASE_IDX 2 11897#define regDC_GPIO_PWRSEQ1_EN 0x2902 11898#define regDC_GPIO_PWRSEQ1_EN_BASE_IDX 2 11899#define regDC_GPIO_TX12_EN 0x2915 11900#define regDC_GPIO_TX12_EN_BASE_IDX 2 11901#define regDC_GPIO_AUX_CTRL_0 0x2916 11902#define regDC_GPIO_AUX_CTRL_0_BASE_IDX 2 11903#define regDC_GPIO_AUX_CTRL_1 0x2917 11904#define regDC_GPIO_AUX_CTRL_1_BASE_IDX 2 11905#define regDC_GPIO_AUX_CTRL_2 0x2918 11906#define regDC_GPIO_AUX_CTRL_2_BASE_IDX 2 11907#define regDC_GPIO_RXEN 0x2919 11908#define regDC_GPIO_RXEN_BASE_IDX 2 11909#define regDC_GPIO_PULLUPEN 0x291a 11910#define regDC_GPIO_PULLUPEN_BASE_IDX 2 11911#define regDC_GPIO_AUX_CTRL_3 0x291b 11912#define regDC_GPIO_AUX_CTRL_3_BASE_IDX 2 11913#define regDC_GPIO_AUX_CTRL_4 0x291c 11914#define regDC_GPIO_AUX_CTRL_4_BASE_IDX 2 11915#define regDC_GPIO_AUX_CTRL_5 0x291d 11916#define regDC_GPIO_AUX_CTRL_5_BASE_IDX 2 11917#define regAUXI2C_PAD_ALL_PWR_OK 0x291e 11918#define regAUXI2C_PAD_ALL_PWR_OK_BASE_IDX 2 11919 11920 11921// addressBlock: dce_dc_dcio_dcio_uniphy1_dispdec 11922// base address: 0x360 11923#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0 0x2a00 11924#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2 11925#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1 0x2a01 11926#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2 11927#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2 0x2a02 11928#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2 11929#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3 0x2a03 11930#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2 11931#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4 0x2a04 11932#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2 11933#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5 0x2a05 11934#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2 11935#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6 0x2a06 11936#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2 11937#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7 0x2a07 11938#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2 11939#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8 0x2a08 11940#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2 11941#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9 0x2a09 11942#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2 11943#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10 0x2a0a 11944#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2 11945#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11 0x2a0b 11946#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2 11947#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12 0x2a0c 11948#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2 11949#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13 0x2a0d 11950#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2 11951#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14 0x2a0e 11952#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2 11953#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15 0x2a0f 11954#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2 11955#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16 0x2a10 11956#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2 11957#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17 0x2a11 11958#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2 11959#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18 0x2a12 11960#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2 11961#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19 0x2a13 11962#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2 11963#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20 0x2a14 11964#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2 11965#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21 0x2a15 11966#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2 11967#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22 0x2a16 11968#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2 11969#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23 0x2a17 11970#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2 11971#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24 0x2a18 11972#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2 11973#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25 0x2a19 11974#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2 11975#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26 0x2a1a 11976#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2 11977#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27 0x2a1b 11978#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2 11979#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28 0x2a1c 11980#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2 11981#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29 0x2a1d 11982#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2 11983#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30 0x2a1e 11984#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2 11985#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31 0x2a1f 11986#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2 11987#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32 0x2a20 11988#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2 11989#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33 0x2a21 11990#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2 11991#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34 0x2a22 11992#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2 11993#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35 0x2a23 11994#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2 11995#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36 0x2a24 11996#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2 11997#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37 0x2a25 11998#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2 11999#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38 0x2a26 12000#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2 12001#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39 0x2a27 12002#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2 12003#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40 0x2a28 12004#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2 12005#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41 0x2a29 12006#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2 12007#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42 0x2a2a 12008#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2 12009#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43 0x2a2b 12010#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2 12011#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44 0x2a2c 12012#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2 12013#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45 0x2a2d 12014#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2 12015#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46 0x2a2e 12016#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2 12017#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47 0x2a2f 12018#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2 12019#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48 0x2a30 12020#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX 2 12021#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49 0x2a31 12022#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX 2 12023#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50 0x2a32 12024#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX 2 12025#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51 0x2a33 12026#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX 2 12027#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52 0x2a34 12028#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX 2 12029#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53 0x2a35 12030#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX 2 12031#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54 0x2a36 12032#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX 2 12033#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55 0x2a37 12034#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX 2 12035#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56 0x2a38 12036#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX 2 12037#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57 0x2a39 12038#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX 2 12039 12040 12041// addressBlock: dce_dc_dcio_dcio_uniphy2_dispdec 12042// base address: 0x6c0 12043#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0 0x2ad8 12044#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2 12045#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1 0x2ad9 12046#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2 12047#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2 0x2ada 12048#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2 12049#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3 0x2adb 12050#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2 12051#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4 0x2adc 12052#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2 12053#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5 0x2add 12054#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2 12055#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6 0x2ade 12056#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2 12057#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7 0x2adf 12058#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2 12059#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8 0x2ae0 12060#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2 12061#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9 0x2ae1 12062#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2 12063#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10 0x2ae2 12064#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2 12065#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11 0x2ae3 12066#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2 12067#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12 0x2ae4 12068#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2 12069#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13 0x2ae5 12070#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2 12071#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14 0x2ae6 12072#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2 12073#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15 0x2ae7 12074#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2 12075#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16 0x2ae8 12076#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2 12077#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17 0x2ae9 12078#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2 12079#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18 0x2aea 12080#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2 12081#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19 0x2aeb 12082#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2 12083#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20 0x2aec 12084#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2 12085#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21 0x2aed 12086#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2 12087#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22 0x2aee 12088#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2 12089#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23 0x2aef 12090#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2 12091#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24 0x2af0 12092#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2 12093#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25 0x2af1 12094#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2 12095#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26 0x2af2 12096#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2 12097#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27 0x2af3 12098#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2 12099#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28 0x2af4 12100#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2 12101#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29 0x2af5 12102#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2 12103#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30 0x2af6 12104#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2 12105#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31 0x2af7 12106#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2 12107#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32 0x2af8 12108#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2 12109#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33 0x2af9 12110#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2 12111#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34 0x2afa 12112#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2 12113#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35 0x2afb 12114#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2 12115#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36 0x2afc 12116#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2 12117#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37 0x2afd 12118#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2 12119#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38 0x2afe 12120#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2 12121#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39 0x2aff 12122#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2 12123#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40 0x2b00 12124#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2 12125#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41 0x2b01 12126#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2 12127#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42 0x2b02 12128#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2 12129#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43 0x2b03 12130#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2 12131#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44 0x2b04 12132#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2 12133#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45 0x2b05 12134#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2 12135#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46 0x2b06 12136#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2 12137#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47 0x2b07 12138#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2 12139#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48 0x2b08 12140#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX 2 12141#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49 0x2b09 12142#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX 2 12143#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50 0x2b0a 12144#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX 2 12145#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51 0x2b0b 12146#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX 2 12147#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52 0x2b0c 12148#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX 2 12149#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53 0x2b0d 12150#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX 2 12151#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54 0x2b0e 12152#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX 2 12153#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55 0x2b0f 12154#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX 2 12155#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56 0x2b10 12156#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX 2 12157#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57 0x2b11 12158#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX 2 12159 12160 12161// addressBlock: dce_dc_dcio_dcio_uniphy3_dispdec 12162// base address: 0xa20 12163#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0 0x2bb0 12164#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2 12165#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1 0x2bb1 12166#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2 12167#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2 0x2bb2 12168#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2 12169#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3 0x2bb3 12170#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2 12171#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4 0x2bb4 12172#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2 12173#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5 0x2bb5 12174#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2 12175#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6 0x2bb6 12176#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2 12177#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7 0x2bb7 12178#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2 12179#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8 0x2bb8 12180#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2 12181#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9 0x2bb9 12182#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2 12183#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10 0x2bba 12184#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2 12185#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11 0x2bbb 12186#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2 12187#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12 0x2bbc 12188#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2 12189#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13 0x2bbd 12190#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2 12191#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14 0x2bbe 12192#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2 12193#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15 0x2bbf 12194#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2 12195#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16 0x2bc0 12196#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2 12197#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17 0x2bc1 12198#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2 12199#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18 0x2bc2 12200#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2 12201#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19 0x2bc3 12202#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2 12203#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20 0x2bc4 12204#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2 12205#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21 0x2bc5 12206#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2 12207#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22 0x2bc6 12208#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2 12209#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23 0x2bc7 12210#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2 12211#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24 0x2bc8 12212#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2 12213#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25 0x2bc9 12214#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2 12215#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26 0x2bca 12216#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2 12217#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27 0x2bcb 12218#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2 12219#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28 0x2bcc 12220#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2 12221#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29 0x2bcd 12222#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2 12223#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30 0x2bce 12224#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2 12225#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31 0x2bcf 12226#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2 12227#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32 0x2bd0 12228#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2 12229#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33 0x2bd1 12230#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2 12231#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34 0x2bd2 12232#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2 12233#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35 0x2bd3 12234#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2 12235#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36 0x2bd4 12236#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2 12237#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37 0x2bd5 12238#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2 12239#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38 0x2bd6 12240#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2 12241#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39 0x2bd7 12242#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2 12243#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40 0x2bd8 12244#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2 12245#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41 0x2bd9 12246#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2 12247#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42 0x2bda 12248#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2 12249#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43 0x2bdb 12250#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2 12251#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44 0x2bdc 12252#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2 12253#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45 0x2bdd 12254#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2 12255#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46 0x2bde 12256#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2 12257#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47 0x2bdf 12258#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2 12259#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48 0x2be0 12260#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX 2 12261#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49 0x2be1 12262#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX 2 12263#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50 0x2be2 12264#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX 2 12265#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51 0x2be3 12266#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX 2 12267#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52 0x2be4 12268#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX 2 12269#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53 0x2be5 12270#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX 2 12271#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54 0x2be6 12272#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX 2 12273#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55 0x2be7 12274#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX 2 12275#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56 0x2be8 12276#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX 2 12277#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57 0x2be9 12278#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX 2 12279 12280 12281// addressBlock: dce_dc_dcio_dcio_uniphy4_dispdec 12282// base address: 0xd80 12283#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED0 0x2c88 12284#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2 12285#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED1 0x2c89 12286#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2 12287#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED2 0x2c8a 12288#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2 12289#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED3 0x2c8b 12290#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2 12291#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED4 0x2c8c 12292#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2 12293#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED5 0x2c8d 12294#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2 12295#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED6 0x2c8e 12296#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2 12297#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED7 0x2c8f 12298#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2 12299#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED8 0x2c90 12300#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2 12301#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED9 0x2c91 12302#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2 12303#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED10 0x2c92 12304#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2 12305#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED11 0x2c93 12306#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2 12307#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED12 0x2c94 12308#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2 12309#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED13 0x2c95 12310#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2 12311#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14 0x2c96 12312#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2 12313#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15 0x2c97 12314#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2 12315#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16 0x2c98 12316#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2 12317#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17 0x2c99 12318#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2 12319#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18 0x2c9a 12320#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2 12321#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19 0x2c9b 12322#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2 12323#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED20 0x2c9c 12324#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2 12325#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED21 0x2c9d 12326#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2 12327#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED22 0x2c9e 12328#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2 12329#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23 0x2c9f 12330#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2 12331#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24 0x2ca0 12332#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2 12333#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25 0x2ca1 12334#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2 12335#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26 0x2ca2 12336#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2 12337#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27 0x2ca3 12338#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2 12339#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28 0x2ca4 12340#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2 12341#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29 0x2ca5 12342#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2 12343#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30 0x2ca6 12344#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2 12345#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31 0x2ca7 12346#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2 12347#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED32 0x2ca8 12348#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2 12349#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED33 0x2ca9 12350#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2 12351#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED34 0x2caa 12352#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2 12353#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED35 0x2cab 12354#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2 12355#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED36 0x2cac 12356#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2 12357#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED37 0x2cad 12358#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2 12359#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED38 0x2cae 12360#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2 12361#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED39 0x2caf 12362#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2 12363#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED40 0x2cb0 12364#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2 12365#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED41 0x2cb1 12366#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2 12367#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED42 0x2cb2 12368#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2 12369#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED43 0x2cb3 12370#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2 12371#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED44 0x2cb4 12372#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2 12373#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED45 0x2cb5 12374#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2 12375#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED46 0x2cb6 12376#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2 12377#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED47 0x2cb7 12378#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2 12379#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED48 0x2cb8 12380#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX 2 12381#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED49 0x2cb9 12382#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX 2 12383#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED50 0x2cba 12384#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX 2 12385#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED51 0x2cbb 12386#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX 2 12387#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED52 0x2cbc 12388#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX 2 12389#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED53 0x2cbd 12390#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX 2 12391#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED54 0x2cbe 12392#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX 2 12393#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED55 0x2cbf 12394#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX 2 12395#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED56 0x2cc0 12396#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX 2 12397#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED57 0x2cc1 12398#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX 2 12399 12400 12401// addressBlock: dce_dc_pwrseq0_dispdec_pwrseq_dispdec 12402// base address: 0x0 12403#define regPWRSEQ0_DC_GPIO_PWRSEQ_EN 0x2f10 12404#define regPWRSEQ0_DC_GPIO_PWRSEQ_EN_BASE_IDX 2 12405#define regPWRSEQ0_DC_GPIO_PWRSEQ_CTRL 0x2f11 12406#define regPWRSEQ0_DC_GPIO_PWRSEQ_CTRL_BASE_IDX 2 12407#define regPWRSEQ0_DC_GPIO_PWRSEQ_MASK 0x2f12 12408#define regPWRSEQ0_DC_GPIO_PWRSEQ_MASK_BASE_IDX 2 12409#define regPWRSEQ0_DC_GPIO_PWRSEQ_A_Y 0x2f13 12410#define regPWRSEQ0_DC_GPIO_PWRSEQ_A_Y_BASE_IDX 2 12411#define regPWRSEQ0_PANEL_PWRSEQ_CNTL 0x2f14 12412#define regPWRSEQ0_PANEL_PWRSEQ_CNTL_BASE_IDX 2 12413#define regPWRSEQ0_PANEL_PWRSEQ_STATE 0x2f15 12414#define regPWRSEQ0_PANEL_PWRSEQ_STATE_BASE_IDX 2 12415#define regPWRSEQ0_PANEL_PWRSEQ_DELAY1 0x2f16 12416#define regPWRSEQ0_PANEL_PWRSEQ_DELAY1_BASE_IDX 2 12417#define regPWRSEQ0_PANEL_PWRSEQ_DELAY2 0x2f17 12418#define regPWRSEQ0_PANEL_PWRSEQ_DELAY2_BASE_IDX 2 12419#define regPWRSEQ0_PANEL_PWRSEQ_REF_DIV1 0x2f18 12420#define regPWRSEQ0_PANEL_PWRSEQ_REF_DIV1_BASE_IDX 2 12421#define regPWRSEQ0_BL_PWM_CNTL 0x2f19 12422#define regPWRSEQ0_BL_PWM_CNTL_BASE_IDX 2 12423#define regPWRSEQ0_BL_PWM_CNTL2 0x2f1a 12424#define regPWRSEQ0_BL_PWM_CNTL2_BASE_IDX 2 12425#define regPWRSEQ0_BL_PWM_PERIOD_CNTL 0x2f1b 12426#define regPWRSEQ0_BL_PWM_PERIOD_CNTL_BASE_IDX 2 12427#define regPWRSEQ0_BL_PWM_GRP1_REG_LOCK 0x2f1c 12428#define regPWRSEQ0_BL_PWM_GRP1_REG_LOCK_BASE_IDX 2 12429#define regPWRSEQ0_PANEL_PWRSEQ_REF_DIV2 0x2f1d 12430#define regPWRSEQ0_PANEL_PWRSEQ_REF_DIV2_BASE_IDX 2 12431#define regPWRSEQ0_PWRSEQ_SPARE 0x2f21 12432#define regPWRSEQ0_PWRSEQ_SPARE_BASE_IDX 2 12433 12434 12435// addressBlock: dce_dc_pwrseq1_dispdec_pwrseq_dispdec 12436// base address: 0x1b0 12437#define regPWRSEQ1_DC_GPIO_PWRSEQ_EN 0x2f7c 12438#define regPWRSEQ1_DC_GPIO_PWRSEQ_EN_BASE_IDX 2 12439#define regPWRSEQ1_DC_GPIO_PWRSEQ_CTRL 0x2f7d 12440#define regPWRSEQ1_DC_GPIO_PWRSEQ_CTRL_BASE_IDX 2 12441#define regPWRSEQ1_DC_GPIO_PWRSEQ_MASK 0x2f7e 12442#define regPWRSEQ1_DC_GPIO_PWRSEQ_MASK_BASE_IDX 2 12443#define regPWRSEQ1_DC_GPIO_PWRSEQ_A_Y 0x2f7f 12444#define regPWRSEQ1_DC_GPIO_PWRSEQ_A_Y_BASE_IDX 2 12445#define regPWRSEQ1_PANEL_PWRSEQ_CNTL 0x2f80 12446#define regPWRSEQ1_PANEL_PWRSEQ_CNTL_BASE_IDX 2 12447#define regPWRSEQ1_PANEL_PWRSEQ_STATE 0x2f81 12448#define regPWRSEQ1_PANEL_PWRSEQ_STATE_BASE_IDX 2 12449#define regPWRSEQ1_PANEL_PWRSEQ_DELAY1 0x2f82 12450#define regPWRSEQ1_PANEL_PWRSEQ_DELAY1_BASE_IDX 2 12451#define regPWRSEQ1_PANEL_PWRSEQ_DELAY2 0x2f83 12452#define regPWRSEQ1_PANEL_PWRSEQ_DELAY2_BASE_IDX 2 12453#define regPWRSEQ1_PANEL_PWRSEQ_REF_DIV1 0x2f84 12454#define regPWRSEQ1_PANEL_PWRSEQ_REF_DIV1_BASE_IDX 2 12455#define regPWRSEQ1_BL_PWM_CNTL 0x2f85 12456#define regPWRSEQ1_BL_PWM_CNTL_BASE_IDX 2 12457#define regPWRSEQ1_BL_PWM_CNTL2 0x2f86 12458#define regPWRSEQ1_BL_PWM_CNTL2_BASE_IDX 2 12459#define regPWRSEQ1_BL_PWM_PERIOD_CNTL 0x2f87 12460#define regPWRSEQ1_BL_PWM_PERIOD_CNTL_BASE_IDX 2 12461#define regPWRSEQ1_BL_PWM_GRP1_REG_LOCK 0x2f88 12462#define regPWRSEQ1_BL_PWM_GRP1_REG_LOCK_BASE_IDX 2 12463#define regPWRSEQ1_PANEL_PWRSEQ_REF_DIV2 0x2f89 12464#define regPWRSEQ1_PANEL_PWRSEQ_REF_DIV2_BASE_IDX 2 12465#define regPWRSEQ1_PWRSEQ_SPARE 0x2f8d 12466#define regPWRSEQ1_PWRSEQ_SPARE_BASE_IDX 2 12467 12468 12469// addressBlock: dce_dc_dsc0_dispdec_dscc_dispdec 12470// base address: 0x0 12471#define regDSCC0_DSCC_CONFIG0 0x300a 12472#define regDSCC0_DSCC_CONFIG0_BASE_IDX 2 12473#define regDSCC0_DSCC_CONFIG1 0x300b 12474#define regDSCC0_DSCC_CONFIG1_BASE_IDX 2 12475#define regDSCC0_DSCC_STATUS 0x300c 12476#define regDSCC0_DSCC_STATUS_BASE_IDX 2 12477#define regDSCC0_DSCC_INTERRUPT_CONTROL_STATUS 0x300d 12478#define regDSCC0_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX 2 12479#define regDSCC0_DSCC_PPS_CONFIG0 0x300e 12480#define regDSCC0_DSCC_PPS_CONFIG0_BASE_IDX 2 12481#define regDSCC0_DSCC_PPS_CONFIG1 0x300f 12482#define regDSCC0_DSCC_PPS_CONFIG1_BASE_IDX 2 12483#define regDSCC0_DSCC_PPS_CONFIG2 0x3010 12484#define regDSCC0_DSCC_PPS_CONFIG2_BASE_IDX 2 12485#define regDSCC0_DSCC_PPS_CONFIG3 0x3011 12486#define regDSCC0_DSCC_PPS_CONFIG3_BASE_IDX 2 12487#define regDSCC0_DSCC_PPS_CONFIG4 0x3012 12488#define regDSCC0_DSCC_PPS_CONFIG4_BASE_IDX 2 12489#define regDSCC0_DSCC_PPS_CONFIG5 0x3013 12490#define regDSCC0_DSCC_PPS_CONFIG5_BASE_IDX 2 12491#define regDSCC0_DSCC_PPS_CONFIG6 0x3014 12492#define regDSCC0_DSCC_PPS_CONFIG6_BASE_IDX 2 12493#define regDSCC0_DSCC_PPS_CONFIG7 0x3015 12494#define regDSCC0_DSCC_PPS_CONFIG7_BASE_IDX 2 12495#define regDSCC0_DSCC_PPS_CONFIG8 0x3016 12496#define regDSCC0_DSCC_PPS_CONFIG8_BASE_IDX 2 12497#define regDSCC0_DSCC_PPS_CONFIG9 0x3017 12498#define regDSCC0_DSCC_PPS_CONFIG9_BASE_IDX 2 12499#define regDSCC0_DSCC_PPS_CONFIG10 0x3018 12500#define regDSCC0_DSCC_PPS_CONFIG10_BASE_IDX 2 12501#define regDSCC0_DSCC_PPS_CONFIG11 0x3019 12502#define regDSCC0_DSCC_PPS_CONFIG11_BASE_IDX 2 12503#define regDSCC0_DSCC_PPS_CONFIG12 0x301a 12504#define regDSCC0_DSCC_PPS_CONFIG12_BASE_IDX 2 12505#define regDSCC0_DSCC_PPS_CONFIG13 0x301b 12506#define regDSCC0_DSCC_PPS_CONFIG13_BASE_IDX 2 12507#define regDSCC0_DSCC_PPS_CONFIG14 0x301c 12508#define regDSCC0_DSCC_PPS_CONFIG14_BASE_IDX 2 12509#define regDSCC0_DSCC_PPS_CONFIG15 0x301d 12510#define regDSCC0_DSCC_PPS_CONFIG15_BASE_IDX 2 12511#define regDSCC0_DSCC_PPS_CONFIG16 0x301e 12512#define regDSCC0_DSCC_PPS_CONFIG16_BASE_IDX 2 12513#define regDSCC0_DSCC_PPS_CONFIG17 0x301f 12514#define regDSCC0_DSCC_PPS_CONFIG17_BASE_IDX 2 12515#define regDSCC0_DSCC_PPS_CONFIG18 0x3020 12516#define regDSCC0_DSCC_PPS_CONFIG18_BASE_IDX 2 12517#define regDSCC0_DSCC_PPS_CONFIG19 0x3021 12518#define regDSCC0_DSCC_PPS_CONFIG19_BASE_IDX 2 12519#define regDSCC0_DSCC_PPS_CONFIG20 0x3022 12520#define regDSCC0_DSCC_PPS_CONFIG20_BASE_IDX 2 12521#define regDSCC0_DSCC_PPS_CONFIG21 0x3023 12522#define regDSCC0_DSCC_PPS_CONFIG21_BASE_IDX 2 12523#define regDSCC0_DSCC_PPS_CONFIG22 0x3024 12524#define regDSCC0_DSCC_PPS_CONFIG22_BASE_IDX 2 12525#define regDSCC0_DSCC_MEM_POWER_CONTROL 0x3025 12526#define regDSCC0_DSCC_MEM_POWER_CONTROL_BASE_IDX 2 12527#define regDSCC0_DSCC_R_Y_SQUARED_ERROR_LOWER 0x3026 12528#define regDSCC0_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX 2 12529#define regDSCC0_DSCC_R_Y_SQUARED_ERROR_UPPER 0x3027 12530#define regDSCC0_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX 2 12531#define regDSCC0_DSCC_G_CB_SQUARED_ERROR_LOWER 0x3028 12532#define regDSCC0_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX 2 12533#define regDSCC0_DSCC_G_CB_SQUARED_ERROR_UPPER 0x3029 12534#define regDSCC0_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX 2 12535#define regDSCC0_DSCC_B_CR_SQUARED_ERROR_LOWER 0x302a 12536#define regDSCC0_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX 2 12537#define regDSCC0_DSCC_B_CR_SQUARED_ERROR_UPPER 0x302b 12538#define regDSCC0_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX 2 12539#define regDSCC0_DSCC_MAX_ABS_ERROR0 0x302c 12540#define regDSCC0_DSCC_MAX_ABS_ERROR0_BASE_IDX 2 12541#define regDSCC0_DSCC_MAX_ABS_ERROR1 0x302d 12542#define regDSCC0_DSCC_MAX_ABS_ERROR1_BASE_IDX 2 12543#define regDSCC0_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL 0x302e 12544#define regDSCC0_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2 12545#define regDSCC0_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL 0x302f 12546#define regDSCC0_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2 12547#define regDSCC0_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL 0x3030 12548#define regDSCC0_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2 12549#define regDSCC0_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL 0x3031 12550#define regDSCC0_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2 12551#define regDSCC0_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL 0x3032 12552#define regDSCC0_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2 12553#define regDSCC0_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL 0x3033 12554#define regDSCC0_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2 12555#define regDSCC0_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL 0x3034 12556#define regDSCC0_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2 12557#define regDSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL 0x3035 12558#define regDSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2 12559#define regDSCC0_DSCC_TEST_DEBUG_BUS_ROTATE 0x303a 12560#define regDSCC0_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX 2 12561 12562 12563// addressBlock: dce_dc_dsc0_dispdec_dsccif_dispdec 12564// base address: 0x0 12565#define regDSCCIF0_DSCCIF_CONFIG0 0x3005 12566#define regDSCCIF0_DSCCIF_CONFIG0_BASE_IDX 2 12567#define regDSCCIF0_DSCCIF_CONFIG1 0x3006 12568#define regDSCCIF0_DSCCIF_CONFIG1_BASE_IDX 2 12569 12570 12571// addressBlock: dce_dc_dsc0_dispdec_dsc_top_dispdec 12572// base address: 0x0 12573#define regDSC_TOP0_DSC_TOP_CONTROL 0x3000 12574#define regDSC_TOP0_DSC_TOP_CONTROL_BASE_IDX 2 12575#define regDSC_TOP0_DSC_DEBUG_CONTROL 0x3001 12576#define regDSC_TOP0_DSC_DEBUG_CONTROL_BASE_IDX 2 12577 12578 12579// addressBlock: dce_dc_dsc0_dispdec_dsc_dcperfmon_dc_perfmon_dispdec 12580// base address: 0xc140 12581#define regDC_PERFMON19_PERFCOUNTER_CNTL 0x3050 12582#define regDC_PERFMON19_PERFCOUNTER_CNTL_BASE_IDX 2 12583#define regDC_PERFMON19_PERFCOUNTER_CNTL2 0x3051 12584#define regDC_PERFMON19_PERFCOUNTER_CNTL2_BASE_IDX 2 12585#define regDC_PERFMON19_PERFCOUNTER_STATE 0x3052 12586#define regDC_PERFMON19_PERFCOUNTER_STATE_BASE_IDX 2 12587#define regDC_PERFMON19_PERFMON_CNTL 0x3053 12588#define regDC_PERFMON19_PERFMON_CNTL_BASE_IDX 2 12589#define regDC_PERFMON19_PERFMON_CNTL2 0x3054 12590#define regDC_PERFMON19_PERFMON_CNTL2_BASE_IDX 2 12591#define regDC_PERFMON19_PERFMON_CVALUE_INT_MISC 0x3055 12592#define regDC_PERFMON19_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 12593#define regDC_PERFMON19_PERFMON_CVALUE_LOW 0x3056 12594#define regDC_PERFMON19_PERFMON_CVALUE_LOW_BASE_IDX 2 12595#define regDC_PERFMON19_PERFMON_HI 0x3057 12596#define regDC_PERFMON19_PERFMON_HI_BASE_IDX 2 12597#define regDC_PERFMON19_PERFMON_LOW 0x3058 12598#define regDC_PERFMON19_PERFMON_LOW_BASE_IDX 2 12599 12600 12601// addressBlock: dce_dc_dsc1_dispdec_dscc_dispdec 12602// base address: 0x170 12603#define regDSCC1_DSCC_CONFIG0 0x3066 12604#define regDSCC1_DSCC_CONFIG0_BASE_IDX 2 12605#define regDSCC1_DSCC_CONFIG1 0x3067 12606#define regDSCC1_DSCC_CONFIG1_BASE_IDX 2 12607#define regDSCC1_DSCC_STATUS 0x3068 12608#define regDSCC1_DSCC_STATUS_BASE_IDX 2 12609#define regDSCC1_DSCC_INTERRUPT_CONTROL_STATUS 0x3069 12610#define regDSCC1_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX 2 12611#define regDSCC1_DSCC_PPS_CONFIG0 0x306a 12612#define regDSCC1_DSCC_PPS_CONFIG0_BASE_IDX 2 12613#define regDSCC1_DSCC_PPS_CONFIG1 0x306b 12614#define regDSCC1_DSCC_PPS_CONFIG1_BASE_IDX 2 12615#define regDSCC1_DSCC_PPS_CONFIG2 0x306c 12616#define regDSCC1_DSCC_PPS_CONFIG2_BASE_IDX 2 12617#define regDSCC1_DSCC_PPS_CONFIG3 0x306d 12618#define regDSCC1_DSCC_PPS_CONFIG3_BASE_IDX 2 12619#define regDSCC1_DSCC_PPS_CONFIG4 0x306e 12620#define regDSCC1_DSCC_PPS_CONFIG4_BASE_IDX 2 12621#define regDSCC1_DSCC_PPS_CONFIG5 0x306f 12622#define regDSCC1_DSCC_PPS_CONFIG5_BASE_IDX 2 12623#define regDSCC1_DSCC_PPS_CONFIG6 0x3070 12624#define regDSCC1_DSCC_PPS_CONFIG6_BASE_IDX 2 12625#define regDSCC1_DSCC_PPS_CONFIG7 0x3071 12626#define regDSCC1_DSCC_PPS_CONFIG7_BASE_IDX 2 12627#define regDSCC1_DSCC_PPS_CONFIG8 0x3072 12628#define regDSCC1_DSCC_PPS_CONFIG8_BASE_IDX 2 12629#define regDSCC1_DSCC_PPS_CONFIG9 0x3073 12630#define regDSCC1_DSCC_PPS_CONFIG9_BASE_IDX 2 12631#define regDSCC1_DSCC_PPS_CONFIG10 0x3074 12632#define regDSCC1_DSCC_PPS_CONFIG10_BASE_IDX 2 12633#define regDSCC1_DSCC_PPS_CONFIG11 0x3075 12634#define regDSCC1_DSCC_PPS_CONFIG11_BASE_IDX 2 12635#define regDSCC1_DSCC_PPS_CONFIG12 0x3076 12636#define regDSCC1_DSCC_PPS_CONFIG12_BASE_IDX 2 12637#define regDSCC1_DSCC_PPS_CONFIG13 0x3077 12638#define regDSCC1_DSCC_PPS_CONFIG13_BASE_IDX 2 12639#define regDSCC1_DSCC_PPS_CONFIG14 0x3078 12640#define regDSCC1_DSCC_PPS_CONFIG14_BASE_IDX 2 12641#define regDSCC1_DSCC_PPS_CONFIG15 0x3079 12642#define regDSCC1_DSCC_PPS_CONFIG15_BASE_IDX 2 12643#define regDSCC1_DSCC_PPS_CONFIG16 0x307a 12644#define regDSCC1_DSCC_PPS_CONFIG16_BASE_IDX 2 12645#define regDSCC1_DSCC_PPS_CONFIG17 0x307b 12646#define regDSCC1_DSCC_PPS_CONFIG17_BASE_IDX 2 12647#define regDSCC1_DSCC_PPS_CONFIG18 0x307c 12648#define regDSCC1_DSCC_PPS_CONFIG18_BASE_IDX 2 12649#define regDSCC1_DSCC_PPS_CONFIG19 0x307d 12650#define regDSCC1_DSCC_PPS_CONFIG19_BASE_IDX 2 12651#define regDSCC1_DSCC_PPS_CONFIG20 0x307e 12652#define regDSCC1_DSCC_PPS_CONFIG20_BASE_IDX 2 12653#define regDSCC1_DSCC_PPS_CONFIG21 0x307f 12654#define regDSCC1_DSCC_PPS_CONFIG21_BASE_IDX 2 12655#define regDSCC1_DSCC_PPS_CONFIG22 0x3080 12656#define regDSCC1_DSCC_PPS_CONFIG22_BASE_IDX 2 12657#define regDSCC1_DSCC_MEM_POWER_CONTROL 0x3081 12658#define regDSCC1_DSCC_MEM_POWER_CONTROL_BASE_IDX 2 12659#define regDSCC1_DSCC_R_Y_SQUARED_ERROR_LOWER 0x3082 12660#define regDSCC1_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX 2 12661#define regDSCC1_DSCC_R_Y_SQUARED_ERROR_UPPER 0x3083 12662#define regDSCC1_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX 2 12663#define regDSCC1_DSCC_G_CB_SQUARED_ERROR_LOWER 0x3084 12664#define regDSCC1_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX 2 12665#define regDSCC1_DSCC_G_CB_SQUARED_ERROR_UPPER 0x3085 12666#define regDSCC1_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX 2 12667#define regDSCC1_DSCC_B_CR_SQUARED_ERROR_LOWER 0x3086 12668#define regDSCC1_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX 2 12669#define regDSCC1_DSCC_B_CR_SQUARED_ERROR_UPPER 0x3087 12670#define regDSCC1_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX 2 12671#define regDSCC1_DSCC_MAX_ABS_ERROR0 0x3088 12672#define regDSCC1_DSCC_MAX_ABS_ERROR0_BASE_IDX 2 12673#define regDSCC1_DSCC_MAX_ABS_ERROR1 0x3089 12674#define regDSCC1_DSCC_MAX_ABS_ERROR1_BASE_IDX 2 12675#define regDSCC1_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL 0x308a 12676#define regDSCC1_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2 12677#define regDSCC1_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL 0x308b 12678#define regDSCC1_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2 12679#define regDSCC1_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL 0x308c 12680#define regDSCC1_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2 12681#define regDSCC1_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL 0x308d 12682#define regDSCC1_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2 12683#define regDSCC1_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL 0x308e 12684#define regDSCC1_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2 12685#define regDSCC1_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL 0x308f 12686#define regDSCC1_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2 12687#define regDSCC1_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL 0x3090 12688#define regDSCC1_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2 12689#define regDSCC1_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL 0x3091 12690#define regDSCC1_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2 12691#define regDSCC1_DSCC_TEST_DEBUG_BUS_ROTATE 0x3096 12692#define regDSCC1_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX 2 12693 12694 12695// addressBlock: dce_dc_dsc1_dispdec_dsccif_dispdec 12696// base address: 0x170 12697#define regDSCCIF1_DSCCIF_CONFIG0 0x3061 12698#define regDSCCIF1_DSCCIF_CONFIG0_BASE_IDX 2 12699#define regDSCCIF1_DSCCIF_CONFIG1 0x3062 12700#define regDSCCIF1_DSCCIF_CONFIG1_BASE_IDX 2 12701 12702 12703// addressBlock: dce_dc_dsc1_dispdec_dsc_top_dispdec 12704// base address: 0x170 12705#define regDSC_TOP1_DSC_TOP_CONTROL 0x305c 12706#define regDSC_TOP1_DSC_TOP_CONTROL_BASE_IDX 2 12707#define regDSC_TOP1_DSC_DEBUG_CONTROL 0x305d 12708#define regDSC_TOP1_DSC_DEBUG_CONTROL_BASE_IDX 2 12709 12710 12711// addressBlock: dce_dc_dsc1_dispdec_dsc_dcperfmon_dc_perfmon_dispdec 12712// base address: 0xc2b0 12713#define regDC_PERFMON20_PERFCOUNTER_CNTL 0x30ac 12714#define regDC_PERFMON20_PERFCOUNTER_CNTL_BASE_IDX 2 12715#define regDC_PERFMON20_PERFCOUNTER_CNTL2 0x30ad 12716#define regDC_PERFMON20_PERFCOUNTER_CNTL2_BASE_IDX 2 12717#define regDC_PERFMON20_PERFCOUNTER_STATE 0x30ae 12718#define regDC_PERFMON20_PERFCOUNTER_STATE_BASE_IDX 2 12719#define regDC_PERFMON20_PERFMON_CNTL 0x30af 12720#define regDC_PERFMON20_PERFMON_CNTL_BASE_IDX 2 12721#define regDC_PERFMON20_PERFMON_CNTL2 0x30b0 12722#define regDC_PERFMON20_PERFMON_CNTL2_BASE_IDX 2 12723#define regDC_PERFMON20_PERFMON_CVALUE_INT_MISC 0x30b1 12724#define regDC_PERFMON20_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 12725#define regDC_PERFMON20_PERFMON_CVALUE_LOW 0x30b2 12726#define regDC_PERFMON20_PERFMON_CVALUE_LOW_BASE_IDX 2 12727#define regDC_PERFMON20_PERFMON_HI 0x30b3 12728#define regDC_PERFMON20_PERFMON_HI_BASE_IDX 2 12729#define regDC_PERFMON20_PERFMON_LOW 0x30b4 12730#define regDC_PERFMON20_PERFMON_LOW_BASE_IDX 2 12731 12732 12733// addressBlock: dce_dc_dsc2_dispdec_dscc_dispdec 12734// base address: 0x2e0 12735#define regDSCC2_DSCC_CONFIG0 0x30c2 12736#define regDSCC2_DSCC_CONFIG0_BASE_IDX 2 12737#define regDSCC2_DSCC_CONFIG1 0x30c3 12738#define regDSCC2_DSCC_CONFIG1_BASE_IDX 2 12739#define regDSCC2_DSCC_STATUS 0x30c4 12740#define regDSCC2_DSCC_STATUS_BASE_IDX 2 12741#define regDSCC2_DSCC_INTERRUPT_CONTROL_STATUS 0x30c5 12742#define regDSCC2_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX 2 12743#define regDSCC2_DSCC_PPS_CONFIG0 0x30c6 12744#define regDSCC2_DSCC_PPS_CONFIG0_BASE_IDX 2 12745#define regDSCC2_DSCC_PPS_CONFIG1 0x30c7 12746#define regDSCC2_DSCC_PPS_CONFIG1_BASE_IDX 2 12747#define regDSCC2_DSCC_PPS_CONFIG2 0x30c8 12748#define regDSCC2_DSCC_PPS_CONFIG2_BASE_IDX 2 12749#define regDSCC2_DSCC_PPS_CONFIG3 0x30c9 12750#define regDSCC2_DSCC_PPS_CONFIG3_BASE_IDX 2 12751#define regDSCC2_DSCC_PPS_CONFIG4 0x30ca 12752#define regDSCC2_DSCC_PPS_CONFIG4_BASE_IDX 2 12753#define regDSCC2_DSCC_PPS_CONFIG5 0x30cb 12754#define regDSCC2_DSCC_PPS_CONFIG5_BASE_IDX 2 12755#define regDSCC2_DSCC_PPS_CONFIG6 0x30cc 12756#define regDSCC2_DSCC_PPS_CONFIG6_BASE_IDX 2 12757#define regDSCC2_DSCC_PPS_CONFIG7 0x30cd 12758#define regDSCC2_DSCC_PPS_CONFIG7_BASE_IDX 2 12759#define regDSCC2_DSCC_PPS_CONFIG8 0x30ce 12760#define regDSCC2_DSCC_PPS_CONFIG8_BASE_IDX 2 12761#define regDSCC2_DSCC_PPS_CONFIG9 0x30cf 12762#define regDSCC2_DSCC_PPS_CONFIG9_BASE_IDX 2 12763#define regDSCC2_DSCC_PPS_CONFIG10 0x30d0 12764#define regDSCC2_DSCC_PPS_CONFIG10_BASE_IDX 2 12765#define regDSCC2_DSCC_PPS_CONFIG11 0x30d1 12766#define regDSCC2_DSCC_PPS_CONFIG11_BASE_IDX 2 12767#define regDSCC2_DSCC_PPS_CONFIG12 0x30d2 12768#define regDSCC2_DSCC_PPS_CONFIG12_BASE_IDX 2 12769#define regDSCC2_DSCC_PPS_CONFIG13 0x30d3 12770#define regDSCC2_DSCC_PPS_CONFIG13_BASE_IDX 2 12771#define regDSCC2_DSCC_PPS_CONFIG14 0x30d4 12772#define regDSCC2_DSCC_PPS_CONFIG14_BASE_IDX 2 12773#define regDSCC2_DSCC_PPS_CONFIG15 0x30d5 12774#define regDSCC2_DSCC_PPS_CONFIG15_BASE_IDX 2 12775#define regDSCC2_DSCC_PPS_CONFIG16 0x30d6 12776#define regDSCC2_DSCC_PPS_CONFIG16_BASE_IDX 2 12777#define regDSCC2_DSCC_PPS_CONFIG17 0x30d7 12778#define regDSCC2_DSCC_PPS_CONFIG17_BASE_IDX 2 12779#define regDSCC2_DSCC_PPS_CONFIG18 0x30d8 12780#define regDSCC2_DSCC_PPS_CONFIG18_BASE_IDX 2 12781#define regDSCC2_DSCC_PPS_CONFIG19 0x30d9 12782#define regDSCC2_DSCC_PPS_CONFIG19_BASE_IDX 2 12783#define regDSCC2_DSCC_PPS_CONFIG20 0x30da 12784#define regDSCC2_DSCC_PPS_CONFIG20_BASE_IDX 2 12785#define regDSCC2_DSCC_PPS_CONFIG21 0x30db 12786#define regDSCC2_DSCC_PPS_CONFIG21_BASE_IDX 2 12787#define regDSCC2_DSCC_PPS_CONFIG22 0x30dc 12788#define regDSCC2_DSCC_PPS_CONFIG22_BASE_IDX 2 12789#define regDSCC2_DSCC_MEM_POWER_CONTROL 0x30dd 12790#define regDSCC2_DSCC_MEM_POWER_CONTROL_BASE_IDX 2 12791#define regDSCC2_DSCC_R_Y_SQUARED_ERROR_LOWER 0x30de 12792#define regDSCC2_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX 2 12793#define regDSCC2_DSCC_R_Y_SQUARED_ERROR_UPPER 0x30df 12794#define regDSCC2_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX 2 12795#define regDSCC2_DSCC_G_CB_SQUARED_ERROR_LOWER 0x30e0 12796#define regDSCC2_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX 2 12797#define regDSCC2_DSCC_G_CB_SQUARED_ERROR_UPPER 0x30e1 12798#define regDSCC2_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX 2 12799#define regDSCC2_DSCC_B_CR_SQUARED_ERROR_LOWER 0x30e2 12800#define regDSCC2_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX 2 12801#define regDSCC2_DSCC_B_CR_SQUARED_ERROR_UPPER 0x30e3 12802#define regDSCC2_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX 2 12803#define regDSCC2_DSCC_MAX_ABS_ERROR0 0x30e4 12804#define regDSCC2_DSCC_MAX_ABS_ERROR0_BASE_IDX 2 12805#define regDSCC2_DSCC_MAX_ABS_ERROR1 0x30e5 12806#define regDSCC2_DSCC_MAX_ABS_ERROR1_BASE_IDX 2 12807#define regDSCC2_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL 0x30e6 12808#define regDSCC2_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2 12809#define regDSCC2_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL 0x30e7 12810#define regDSCC2_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2 12811#define regDSCC2_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL 0x30e8 12812#define regDSCC2_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2 12813#define regDSCC2_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL 0x30e9 12814#define regDSCC2_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2 12815#define regDSCC2_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL 0x30ea 12816#define regDSCC2_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2 12817#define regDSCC2_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL 0x30eb 12818#define regDSCC2_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2 12819#define regDSCC2_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL 0x30ec 12820#define regDSCC2_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2 12821#define regDSCC2_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL 0x30ed 12822#define regDSCC2_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2 12823#define regDSCC2_DSCC_TEST_DEBUG_BUS_ROTATE 0x30f2 12824#define regDSCC2_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX 2 12825 12826 12827// addressBlock: dce_dc_dsc2_dispdec_dsccif_dispdec 12828// base address: 0x2e0 12829#define regDSCCIF2_DSCCIF_CONFIG0 0x30bd 12830#define regDSCCIF2_DSCCIF_CONFIG0_BASE_IDX 2 12831#define regDSCCIF2_DSCCIF_CONFIG1 0x30be 12832#define regDSCCIF2_DSCCIF_CONFIG1_BASE_IDX 2 12833 12834 12835// addressBlock: dce_dc_dsc2_dispdec_dsc_top_dispdec 12836// base address: 0x2e0 12837#define regDSC_TOP2_DSC_TOP_CONTROL 0x30b8 12838#define regDSC_TOP2_DSC_TOP_CONTROL_BASE_IDX 2 12839#define regDSC_TOP2_DSC_DEBUG_CONTROL 0x30b9 12840#define regDSC_TOP2_DSC_DEBUG_CONTROL_BASE_IDX 2 12841 12842 12843// addressBlock: dce_dc_dsc2_dispdec_dsc_dcperfmon_dc_perfmon_dispdec 12844// base address: 0xc420 12845#define regDC_PERFMON21_PERFCOUNTER_CNTL 0x3108 12846#define regDC_PERFMON21_PERFCOUNTER_CNTL_BASE_IDX 2 12847#define regDC_PERFMON21_PERFCOUNTER_CNTL2 0x3109 12848#define regDC_PERFMON21_PERFCOUNTER_CNTL2_BASE_IDX 2 12849#define regDC_PERFMON21_PERFCOUNTER_STATE 0x310a 12850#define regDC_PERFMON21_PERFCOUNTER_STATE_BASE_IDX 2 12851#define regDC_PERFMON21_PERFMON_CNTL 0x310b 12852#define regDC_PERFMON21_PERFMON_CNTL_BASE_IDX 2 12853#define regDC_PERFMON21_PERFMON_CNTL2 0x310c 12854#define regDC_PERFMON21_PERFMON_CNTL2_BASE_IDX 2 12855#define regDC_PERFMON21_PERFMON_CVALUE_INT_MISC 0x310d 12856#define regDC_PERFMON21_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 12857#define regDC_PERFMON21_PERFMON_CVALUE_LOW 0x310e 12858#define regDC_PERFMON21_PERFMON_CVALUE_LOW_BASE_IDX 2 12859#define regDC_PERFMON21_PERFMON_HI 0x310f 12860#define regDC_PERFMON21_PERFMON_HI_BASE_IDX 2 12861#define regDC_PERFMON21_PERFMON_LOW 0x3110 12862#define regDC_PERFMON21_PERFMON_LOW_BASE_IDX 2 12863 12864 12865// addressBlock: dce_dc_hpo_hpo_top_dispdec 12866// base address: 0x2790c 12867#define regHPO_TOP_CLOCK_CONTROL 0x0e43 12868#define regHPO_TOP_CLOCK_CONTROL_BASE_IDX 3 12869#define regHPO_TOP_HW_CONTROL 0x0e4a 12870#define regHPO_TOP_HW_CONTROL_BASE_IDX 3 12871 12872 12873// addressBlock: dce_dc_hpo_dp_stream_mapper_dispdec 12874// base address: 0x27958 12875#define regDP_STREAM_MAPPER_CONTROL0 0x0e56 12876#define regDP_STREAM_MAPPER_CONTROL0_BASE_IDX 3 12877#define regDP_STREAM_MAPPER_CONTROL1 0x0e57 12878#define regDP_STREAM_MAPPER_CONTROL1_BASE_IDX 3 12879#define regDP_STREAM_MAPPER_CONTROL2 0x0e58 12880#define regDP_STREAM_MAPPER_CONTROL2_BASE_IDX 3 12881#define regDP_STREAM_MAPPER_CONTROL3 0x0e59 12882#define regDP_STREAM_MAPPER_CONTROL3_BASE_IDX 3 12883 12884 12885// addressBlock: dce_dc_hpo_hpo_dcperfmon_dc_perfmon_dispdec 12886// base address: 0x1a698 12887#define regDC_PERFMON22_PERFCOUNTER_CNTL 0x0e66 12888#define regDC_PERFMON22_PERFCOUNTER_CNTL_BASE_IDX 3 12889#define regDC_PERFMON22_PERFCOUNTER_CNTL2 0x0e67 12890#define regDC_PERFMON22_PERFCOUNTER_CNTL2_BASE_IDX 3 12891#define regDC_PERFMON22_PERFCOUNTER_STATE 0x0e68 12892#define regDC_PERFMON22_PERFCOUNTER_STATE_BASE_IDX 3 12893#define regDC_PERFMON22_PERFMON_CNTL 0x0e69 12894#define regDC_PERFMON22_PERFMON_CNTL_BASE_IDX 3 12895#define regDC_PERFMON22_PERFMON_CNTL2 0x0e6a 12896#define regDC_PERFMON22_PERFMON_CNTL2_BASE_IDX 3 12897#define regDC_PERFMON22_PERFMON_CVALUE_INT_MISC 0x0e6b 12898#define regDC_PERFMON22_PERFMON_CVALUE_INT_MISC_BASE_IDX 3 12899#define regDC_PERFMON22_PERFMON_CVALUE_LOW 0x0e6c 12900#define regDC_PERFMON22_PERFMON_CVALUE_LOW_BASE_IDX 3 12901#define regDC_PERFMON22_PERFMON_HI 0x0e6d 12902#define regDC_PERFMON22_PERFMON_HI_BASE_IDX 3 12903#define regDC_PERFMON22_PERFMON_LOW 0x0e6e 12904#define regDC_PERFMON22_PERFMON_LOW_BASE_IDX 3 12905 12906 12907// addressBlock: dce_dc_hpo_hdmi_stream_enc0_afmt_afmt_dispdec 12908// base address: 0x2646c 12909#define regAFMT5_AFMT_VBI_PACKET_CONTROL 0x091c 12910#define regAFMT5_AFMT_VBI_PACKET_CONTROL_BASE_IDX 3 12911#define regAFMT5_AFMT_AUDIO_PACKET_CONTROL2 0x091d 12912#define regAFMT5_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 3 12913#define regAFMT5_AFMT_AUDIO_INFO0 0x091e 12914#define regAFMT5_AFMT_AUDIO_INFO0_BASE_IDX 3 12915#define regAFMT5_AFMT_AUDIO_INFO1 0x091f 12916#define regAFMT5_AFMT_AUDIO_INFO1_BASE_IDX 3 12917#define regAFMT5_AFMT_60958_0 0x0920 12918#define regAFMT5_AFMT_60958_0_BASE_IDX 3 12919#define regAFMT5_AFMT_60958_1 0x0921 12920#define regAFMT5_AFMT_60958_1_BASE_IDX 3 12921#define regAFMT5_AFMT_AUDIO_CRC_CONTROL 0x0922 12922#define regAFMT5_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 3 12923#define regAFMT5_AFMT_RAMP_CONTROL0 0x0923 12924#define regAFMT5_AFMT_RAMP_CONTROL0_BASE_IDX 3 12925#define regAFMT5_AFMT_RAMP_CONTROL1 0x0924 12926#define regAFMT5_AFMT_RAMP_CONTROL1_BASE_IDX 3 12927#define regAFMT5_AFMT_RAMP_CONTROL2 0x0925 12928#define regAFMT5_AFMT_RAMP_CONTROL2_BASE_IDX 3 12929#define regAFMT5_AFMT_RAMP_CONTROL3 0x0926 12930#define regAFMT5_AFMT_RAMP_CONTROL3_BASE_IDX 3 12931#define regAFMT5_AFMT_60958_2 0x0927 12932#define regAFMT5_AFMT_60958_2_BASE_IDX 3 12933#define regAFMT5_AFMT_AUDIO_CRC_RESULT 0x0928 12934#define regAFMT5_AFMT_AUDIO_CRC_RESULT_BASE_IDX 3 12935#define regAFMT5_AFMT_STATUS 0x0929 12936#define regAFMT5_AFMT_STATUS_BASE_IDX 3 12937#define regAFMT5_AFMT_AUDIO_PACKET_CONTROL 0x092a 12938#define regAFMT5_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 3 12939#define regAFMT5_AFMT_INFOFRAME_CONTROL0 0x092b 12940#define regAFMT5_AFMT_INFOFRAME_CONTROL0_BASE_IDX 3 12941#define regAFMT5_AFMT_INTERRUPT_STATUS 0x092c 12942#define regAFMT5_AFMT_INTERRUPT_STATUS_BASE_IDX 3 12943#define regAFMT5_AFMT_AUDIO_SRC_CONTROL 0x092d 12944#define regAFMT5_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 3 12945#define regAFMT5_AFMT_MEM_PWR 0x092f 12946#define regAFMT5_AFMT_MEM_PWR_BASE_IDX 3 12947 12948 12949// addressBlock: dce_dc_hpo_hdmi_stream_enc0_dme_dme_dispdec 12950// base address: 0x264f0 12951#define regDME5_DME_CONTROL 0x093c 12952#define regDME5_DME_CONTROL_BASE_IDX 3 12953#define regDME5_DME_MEMORY_CONTROL 0x093d 12954#define regDME5_DME_MEMORY_CONTROL_BASE_IDX 3 12955 12956 12957// addressBlock: dce_dc_hpo_hdmi_stream_enc0_vpg_vpg_dispdec 12958// base address: 0x264c4 12959#define regVPG5_VPG_GENERIC_PACKET_ACCESS_CTRL 0x0931 12960#define regVPG5_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 3 12961#define regVPG5_VPG_GENERIC_PACKET_DATA 0x0932 12962#define regVPG5_VPG_GENERIC_PACKET_DATA_BASE_IDX 3 12963#define regVPG5_VPG_GSP_FRAME_UPDATE_CTRL 0x0933 12964#define regVPG5_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 3 12965#define regVPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x0934 12966#define regVPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 3 12967#define regVPG5_VPG_GENERIC_STATUS 0x0935 12968#define regVPG5_VPG_GENERIC_STATUS_BASE_IDX 3 12969#define regVPG5_VPG_MEM_PWR 0x0936 12970#define regVPG5_VPG_MEM_PWR_BASE_IDX 3 12971#define regVPG5_VPG_ISRC1_2_ACCESS_CTRL 0x0937 12972#define regVPG5_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 3 12973#define regVPG5_VPG_ISRC1_2_DATA 0x0938 12974#define regVPG5_VPG_ISRC1_2_DATA_BASE_IDX 3 12975#define regVPG5_VPG_MPEG_INFO0 0x0939 12976#define regVPG5_VPG_MPEG_INFO0_BASE_IDX 3 12977#define regVPG5_VPG_MPEG_INFO1 0x093a 12978#define regVPG5_VPG_MPEG_INFO1_BASE_IDX 3 12979 12980 12981// addressBlock: dce_dc_hpo_dp_stream_enc0_dispdec 12982// base address: 0x1ab8c 12983#define regDP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL 0x3623 12984#define regDP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL_BASE_IDX 2 12985#define regDP_STREAM_ENC0_DP_STREAM_ENC_INPUT_MUX_CONTROL 0x3624 12986#define regDP_STREAM_ENC0_DP_STREAM_ENC_INPUT_MUX_CONTROL_BASE_IDX 2 12987#define regDP_STREAM_ENC0_DP_STREAM_ENC_AUDIO_CONTROL 0x3625 12988#define regDP_STREAM_ENC0_DP_STREAM_ENC_AUDIO_CONTROL_BASE_IDX 2 12989#define regDP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0 0x3626 12990#define regDP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0_BASE_IDX 2 12991#define regDP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1 0x3627 12992#define regDP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1_BASE_IDX 2 12993#define regDP_STREAM_ENC0_DP_STREAM_ENC_SPARE 0x3628 12994#define regDP_STREAM_ENC0_DP_STREAM_ENC_SPARE_BASE_IDX 2 12995 12996 12997// addressBlock: dce_dc_hpo_dp_stream_enc0_apg_apg_dispdec 12998// base address: 0x1abc0 12999#define regAPG0_APG_CONTROL 0x3630 13000#define regAPG0_APG_CONTROL_BASE_IDX 2 13001#define regAPG0_APG_CONTROL2 0x3631 13002#define regAPG0_APG_CONTROL2_BASE_IDX 2 13003#define regAPG0_APG_DBG_GEN_CONTROL 0x3632 13004#define regAPG0_APG_DBG_GEN_CONTROL_BASE_IDX 2 13005#define regAPG0_APG_PACKET_CONTROL 0x3633 13006#define regAPG0_APG_PACKET_CONTROL_BASE_IDX 2 13007#define regAPG0_APG_AUDIO_CRC_CONTROL 0x363a 13008#define regAPG0_APG_AUDIO_CRC_CONTROL_BASE_IDX 2 13009#define regAPG0_APG_AUDIO_CRC_CONTROL2 0x363b 13010#define regAPG0_APG_AUDIO_CRC_CONTROL2_BASE_IDX 2 13011#define regAPG0_APG_AUDIO_CRC_RESULT 0x363c 13012#define regAPG0_APG_AUDIO_CRC_RESULT_BASE_IDX 2 13013#define regAPG0_APG_STATUS 0x3641 13014#define regAPG0_APG_STATUS_BASE_IDX 2 13015#define regAPG0_APG_STATUS2 0x3642 13016#define regAPG0_APG_STATUS2_BASE_IDX 2 13017#define regAPG0_APG_MEM_PWR 0x3644 13018#define regAPG0_APG_MEM_PWR_BASE_IDX 2 13019#define regAPG0_APG_SPARE 0x3646 13020#define regAPG0_APG_SPARE_BASE_IDX 2 13021 13022 13023// addressBlock: dce_dc_hpo_dp_stream_enc0_dme_dme_dispdec 13024// base address: 0x1ac38 13025#define regDME6_DME_CONTROL 0x364e 13026#define regDME6_DME_CONTROL_BASE_IDX 2 13027#define regDME6_DME_MEMORY_CONTROL 0x364f 13028#define regDME6_DME_MEMORY_CONTROL_BASE_IDX 2 13029 13030 13031// addressBlock: dce_dc_hpo_dp_stream_enc0_vpg_vpg_dispdec 13032// base address: 0x1ac44 13033#define regVPG6_VPG_GENERIC_PACKET_ACCESS_CTRL 0x3651 13034#define regVPG6_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2 13035#define regVPG6_VPG_GENERIC_PACKET_DATA 0x3652 13036#define regVPG6_VPG_GENERIC_PACKET_DATA_BASE_IDX 2 13037#define regVPG6_VPG_GSP_FRAME_UPDATE_CTRL 0x3653 13038#define regVPG6_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2 13039#define regVPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x3654 13040#define regVPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2 13041#define regVPG6_VPG_GENERIC_STATUS 0x3655 13042#define regVPG6_VPG_GENERIC_STATUS_BASE_IDX 2 13043#define regVPG6_VPG_MEM_PWR 0x3656 13044#define regVPG6_VPG_MEM_PWR_BASE_IDX 2 13045#define regVPG6_VPG_ISRC1_2_ACCESS_CTRL 0x3657 13046#define regVPG6_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2 13047#define regVPG6_VPG_ISRC1_2_DATA 0x3658 13048#define regVPG6_VPG_ISRC1_2_DATA_BASE_IDX 2 13049#define regVPG6_VPG_MPEG_INFO0 0x3659 13050#define regVPG6_VPG_MPEG_INFO0_BASE_IDX 2 13051#define regVPG6_VPG_MPEG_INFO1 0x365a 13052#define regVPG6_VPG_MPEG_INFO1_BASE_IDX 2 13053 13054 13055// addressBlock: dce_dc_hpo_dp_sym32_enc0_dispdec 13056// base address: 0x1ac74 13057#define regDP_SYM32_ENC0_DP_SYM32_ENC_CONTROL 0x365d 13058#define regDP_SYM32_ENC0_DP_SYM32_ENC_CONTROL_BASE_IDX 2 13059#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL 0x365e 13060#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL_BASE_IDX 2 13061#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL 0x365f 13062#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 13063#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL 0x3660 13064#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 13065#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT 0x3661 13066#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT_BASE_IDX 2 13067#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA0 0x3662 13068#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA0_BASE_IDX 2 13069#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA1 0x3663 13070#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA1_BASE_IDX 2 13071#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA2 0x3664 13072#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA2_BASE_IDX 2 13073#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA3 0x3665 13074#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA3_BASE_IDX 2 13075#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA4 0x3666 13076#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA4_BASE_IDX 2 13077#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA5 0x3667 13078#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA5_BASE_IDX 2 13079#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA6 0x3668 13080#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA6_BASE_IDX 2 13081#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA7 0x3669 13082#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA7_BASE_IDX 2 13083#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA8 0x366a 13084#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA8_BASE_IDX 2 13085#define regDP_SYM32_ENC0_DP_SYM32_ENC_HBLANK_CONTROL 0x366b 13086#define regDP_SYM32_ENC0_DP_SYM32_ENC_HBLANK_CONTROL_BASE_IDX 2 13087#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0 0x366c 13088#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0_BASE_IDX 2 13089#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1 0x366d 13090#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1_BASE_IDX 2 13091#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2 0x366e 13092#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2_BASE_IDX 2 13093#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3 0x366f 13094#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3_BASE_IDX 2 13095#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4 0x3670 13096#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4_BASE_IDX 2 13097#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5 0x3671 13098#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5_BASE_IDX 2 13099#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6 0x3672 13100#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6_BASE_IDX 2 13101#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7 0x3673 13102#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7_BASE_IDX 2 13103#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8 0x3674 13104#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8_BASE_IDX 2 13105#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9 0x3675 13106#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9_BASE_IDX 2 13107#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10 0x3676 13108#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10_BASE_IDX 2 13109#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11 0x3677 13110#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11_BASE_IDX 2 13111#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12 0x3678 13112#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12_BASE_IDX 2 13113#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13 0x3679 13114#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13_BASE_IDX 2 13115#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14 0x367a 13116#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14_BASE_IDX 2 13117#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_CONTROL 0x367b 13118#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_CONTROL_BASE_IDX 2 13119#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0 0x367c 13120#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0_BASE_IDX 2 13121#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL1 0x367d 13122#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL1_BASE_IDX 2 13123#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL 0x367e 13124#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL_BASE_IDX 2 13125#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_CONTROL 0x3683 13126#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_CONTROL_BASE_IDX 2 13127#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_VBID_CONTROL 0x3684 13128#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_VBID_CONTROL_BASE_IDX 2 13129#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_STREAM_CONTROL 0x3685 13130#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_STREAM_CONTROL_BASE_IDX 2 13131#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL 0x3686 13132#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL_BASE_IDX 2 13133#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_CONTROL 0x3687 13134#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_CONTROL_BASE_IDX 2 13135#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT0 0x3688 13136#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT0_BASE_IDX 2 13137#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT1 0x3689 13138#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT1_BASE_IDX 2 13139#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_STATUS 0x368a 13140#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_STATUS_BASE_IDX 2 13141#define regDP_SYM32_ENC0_DP_SYM32_ENC_MEM_POWER_CONTROL 0x368b 13142#define regDP_SYM32_ENC0_DP_SYM32_ENC_MEM_POWER_CONTROL_BASE_IDX 2 13143#define regDP_SYM32_ENC0_DP_SYM32_ENC_SPARE 0x368c 13144#define regDP_SYM32_ENC0_DP_SYM32_ENC_SPARE_BASE_IDX 2 13145 13146 13147// addressBlock: dce_dc_hpo_dp_stream_enc1_dispdec 13148// base address: 0x1aedc 13149#define regDP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL 0x36f7 13150#define regDP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL_BASE_IDX 2 13151#define regDP_STREAM_ENC1_DP_STREAM_ENC_INPUT_MUX_CONTROL 0x36f8 13152#define regDP_STREAM_ENC1_DP_STREAM_ENC_INPUT_MUX_CONTROL_BASE_IDX 2 13153#define regDP_STREAM_ENC1_DP_STREAM_ENC_AUDIO_CONTROL 0x36f9 13154#define regDP_STREAM_ENC1_DP_STREAM_ENC_AUDIO_CONTROL_BASE_IDX 2 13155#define regDP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0 0x36fa 13156#define regDP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0_BASE_IDX 2 13157#define regDP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1 0x36fb 13158#define regDP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1_BASE_IDX 2 13159#define regDP_STREAM_ENC1_DP_STREAM_ENC_SPARE 0x36fc 13160#define regDP_STREAM_ENC1_DP_STREAM_ENC_SPARE_BASE_IDX 2 13161 13162 13163// addressBlock: dce_dc_hpo_dp_stream_enc1_apg_apg_dispdec 13164// base address: 0x1af10 13165#define regAPG1_APG_CONTROL 0x3704 13166#define regAPG1_APG_CONTROL_BASE_IDX 2 13167#define regAPG1_APG_CONTROL2 0x3705 13168#define regAPG1_APG_CONTROL2_BASE_IDX 2 13169#define regAPG1_APG_DBG_GEN_CONTROL 0x3706 13170#define regAPG1_APG_DBG_GEN_CONTROL_BASE_IDX 2 13171#define regAPG1_APG_PACKET_CONTROL 0x3707 13172#define regAPG1_APG_PACKET_CONTROL_BASE_IDX 2 13173#define regAPG1_APG_AUDIO_CRC_CONTROL 0x370e 13174#define regAPG1_APG_AUDIO_CRC_CONTROL_BASE_IDX 2 13175#define regAPG1_APG_AUDIO_CRC_CONTROL2 0x370f 13176#define regAPG1_APG_AUDIO_CRC_CONTROL2_BASE_IDX 2 13177#define regAPG1_APG_AUDIO_CRC_RESULT 0x3710 13178#define regAPG1_APG_AUDIO_CRC_RESULT_BASE_IDX 2 13179#define regAPG1_APG_STATUS 0x3715 13180#define regAPG1_APG_STATUS_BASE_IDX 2 13181#define regAPG1_APG_STATUS2 0x3716 13182#define regAPG1_APG_STATUS2_BASE_IDX 2 13183#define regAPG1_APG_MEM_PWR 0x3718 13184#define regAPG1_APG_MEM_PWR_BASE_IDX 2 13185#define regAPG1_APG_SPARE 0x371a 13186#define regAPG1_APG_SPARE_BASE_IDX 2 13187 13188 13189// addressBlock: dce_dc_hpo_dp_stream_enc1_dme_dme_dispdec 13190// base address: 0x1af88 13191#define regDME7_DME_CONTROL 0x3722 13192#define regDME7_DME_CONTROL_BASE_IDX 2 13193#define regDME7_DME_MEMORY_CONTROL 0x3723 13194#define regDME7_DME_MEMORY_CONTROL_BASE_IDX 2 13195 13196 13197// addressBlock: dce_dc_hpo_dp_stream_enc1_vpg_vpg_dispdec 13198// base address: 0x1af94 13199#define regVPG7_VPG_GENERIC_PACKET_ACCESS_CTRL 0x3725 13200#define regVPG7_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2 13201#define regVPG7_VPG_GENERIC_PACKET_DATA 0x3726 13202#define regVPG7_VPG_GENERIC_PACKET_DATA_BASE_IDX 2 13203#define regVPG7_VPG_GSP_FRAME_UPDATE_CTRL 0x3727 13204#define regVPG7_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2 13205#define regVPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x3728 13206#define regVPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2 13207#define regVPG7_VPG_GENERIC_STATUS 0x3729 13208#define regVPG7_VPG_GENERIC_STATUS_BASE_IDX 2 13209#define regVPG7_VPG_MEM_PWR 0x372a 13210#define regVPG7_VPG_MEM_PWR_BASE_IDX 2 13211#define regVPG7_VPG_ISRC1_2_ACCESS_CTRL 0x372b 13212#define regVPG7_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2 13213#define regVPG7_VPG_ISRC1_2_DATA 0x372c 13214#define regVPG7_VPG_ISRC1_2_DATA_BASE_IDX 2 13215#define regVPG7_VPG_MPEG_INFO0 0x372d 13216#define regVPG7_VPG_MPEG_INFO0_BASE_IDX 2 13217#define regVPG7_VPG_MPEG_INFO1 0x372e 13218#define regVPG7_VPG_MPEG_INFO1_BASE_IDX 2 13219 13220 13221// addressBlock: dce_dc_hpo_dp_sym32_enc1_dispdec 13222// base address: 0x1afc4 13223#define regDP_SYM32_ENC1_DP_SYM32_ENC_CONTROL 0x3731 13224#define regDP_SYM32_ENC1_DP_SYM32_ENC_CONTROL_BASE_IDX 2 13225#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_FIFO_CONTROL 0x3732 13226#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_FIFO_CONTROL_BASE_IDX 2 13227#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL 0x3733 13228#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 13229#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL 0x3734 13230#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 13231#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT 0x3735 13232#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT_BASE_IDX 2 13233#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA0 0x3736 13234#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA0_BASE_IDX 2 13235#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA1 0x3737 13236#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA1_BASE_IDX 2 13237#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA2 0x3738 13238#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA2_BASE_IDX 2 13239#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA3 0x3739 13240#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA3_BASE_IDX 2 13241#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA4 0x373a 13242#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA4_BASE_IDX 2 13243#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA5 0x373b 13244#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA5_BASE_IDX 2 13245#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA6 0x373c 13246#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA6_BASE_IDX 2 13247#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA7 0x373d 13248#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA7_BASE_IDX 2 13249#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA8 0x373e 13250#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA8_BASE_IDX 2 13251#define regDP_SYM32_ENC1_DP_SYM32_ENC_HBLANK_CONTROL 0x373f 13252#define regDP_SYM32_ENC1_DP_SYM32_ENC_HBLANK_CONTROL_BASE_IDX 2 13253#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0 0x3740 13254#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0_BASE_IDX 2 13255#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1 0x3741 13256#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1_BASE_IDX 2 13257#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2 0x3742 13258#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2_BASE_IDX 2 13259#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3 0x3743 13260#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3_BASE_IDX 2 13261#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4 0x3744 13262#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4_BASE_IDX 2 13263#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5 0x3745 13264#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5_BASE_IDX 2 13265#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6 0x3746 13266#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6_BASE_IDX 2 13267#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7 0x3747 13268#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7_BASE_IDX 2 13269#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8 0x3748 13270#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8_BASE_IDX 2 13271#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9 0x3749 13272#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9_BASE_IDX 2 13273#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10 0x374a 13274#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10_BASE_IDX 2 13275#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11 0x374b 13276#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11_BASE_IDX 2 13277#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12 0x374c 13278#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12_BASE_IDX 2 13279#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13 0x374d 13280#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13_BASE_IDX 2 13281#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14 0x374e 13282#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14_BASE_IDX 2 13283#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_CONTROL 0x374f 13284#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_CONTROL_BASE_IDX 2 13285#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0 0x3750 13286#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0_BASE_IDX 2 13287#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL1 0x3751 13288#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL1_BASE_IDX 2 13289#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL 0x3752 13290#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL_BASE_IDX 2 13291#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_CONTROL 0x3757 13292#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_CONTROL_BASE_IDX 2 13293#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_VBID_CONTROL 0x3758 13294#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_VBID_CONTROL_BASE_IDX 2 13295#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_STREAM_CONTROL 0x3759 13296#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_STREAM_CONTROL_BASE_IDX 2 13297#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL 0x375a 13298#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL_BASE_IDX 2 13299#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_CONTROL 0x375b 13300#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_CONTROL_BASE_IDX 2 13301#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT0 0x375c 13302#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT0_BASE_IDX 2 13303#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT1 0x375d 13304#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT1_BASE_IDX 2 13305#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_STATUS 0x375e 13306#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_STATUS_BASE_IDX 2 13307#define regDP_SYM32_ENC1_DP_SYM32_ENC_MEM_POWER_CONTROL 0x375f 13308#define regDP_SYM32_ENC1_DP_SYM32_ENC_MEM_POWER_CONTROL_BASE_IDX 2 13309#define regDP_SYM32_ENC1_DP_SYM32_ENC_SPARE 0x3760 13310#define regDP_SYM32_ENC1_DP_SYM32_ENC_SPARE_BASE_IDX 2 13311 13312 13313// addressBlock: dce_dc_hpo_dp_stream_enc2_dispdec 13314// base address: 0x1b22c 13315#define regDP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL 0x37cb 13316#define regDP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL_BASE_IDX 2 13317#define regDP_STREAM_ENC2_DP_STREAM_ENC_INPUT_MUX_CONTROL 0x37cc 13318#define regDP_STREAM_ENC2_DP_STREAM_ENC_INPUT_MUX_CONTROL_BASE_IDX 2 13319#define regDP_STREAM_ENC2_DP_STREAM_ENC_AUDIO_CONTROL 0x37cd 13320#define regDP_STREAM_ENC2_DP_STREAM_ENC_AUDIO_CONTROL_BASE_IDX 2 13321#define regDP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0 0x37ce 13322#define regDP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0_BASE_IDX 2 13323#define regDP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1 0x37cf 13324#define regDP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1_BASE_IDX 2 13325#define regDP_STREAM_ENC2_DP_STREAM_ENC_SPARE 0x37d0 13326#define regDP_STREAM_ENC2_DP_STREAM_ENC_SPARE_BASE_IDX 2 13327 13328 13329// addressBlock: dce_dc_hpo_dp_stream_enc2_apg_apg_dispdec 13330// base address: 0x1b260 13331#define regAPG2_APG_CONTROL 0x37d8 13332#define regAPG2_APG_CONTROL_BASE_IDX 2 13333#define regAPG2_APG_CONTROL2 0x37d9 13334#define regAPG2_APG_CONTROL2_BASE_IDX 2 13335#define regAPG2_APG_DBG_GEN_CONTROL 0x37da 13336#define regAPG2_APG_DBG_GEN_CONTROL_BASE_IDX 2 13337#define regAPG2_APG_PACKET_CONTROL 0x37db 13338#define regAPG2_APG_PACKET_CONTROL_BASE_IDX 2 13339#define regAPG2_APG_AUDIO_CRC_CONTROL 0x37e2 13340#define regAPG2_APG_AUDIO_CRC_CONTROL_BASE_IDX 2 13341#define regAPG2_APG_AUDIO_CRC_CONTROL2 0x37e3 13342#define regAPG2_APG_AUDIO_CRC_CONTROL2_BASE_IDX 2 13343#define regAPG2_APG_AUDIO_CRC_RESULT 0x37e4 13344#define regAPG2_APG_AUDIO_CRC_RESULT_BASE_IDX 2 13345#define regAPG2_APG_STATUS 0x37e9 13346#define regAPG2_APG_STATUS_BASE_IDX 2 13347#define regAPG2_APG_STATUS2 0x37ea 13348#define regAPG2_APG_STATUS2_BASE_IDX 2 13349#define regAPG2_APG_MEM_PWR 0x37ec 13350#define regAPG2_APG_MEM_PWR_BASE_IDX 2 13351#define regAPG2_APG_SPARE 0x37ee 13352#define regAPG2_APG_SPARE_BASE_IDX 2 13353 13354 13355// addressBlock: dce_dc_hpo_dp_stream_enc2_dme_dme_dispdec 13356// base address: 0x1b2d8 13357#define regDME8_DME_CONTROL 0x37f6 13358#define regDME8_DME_CONTROL_BASE_IDX 2 13359#define regDME8_DME_MEMORY_CONTROL 0x37f7 13360#define regDME8_DME_MEMORY_CONTROL_BASE_IDX 2 13361 13362 13363// addressBlock: dce_dc_hpo_dp_stream_enc2_vpg_vpg_dispdec 13364// base address: 0x1b2e4 13365#define regVPG8_VPG_GENERIC_PACKET_ACCESS_CTRL 0x37f9 13366#define regVPG8_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2 13367#define regVPG8_VPG_GENERIC_PACKET_DATA 0x37fa 13368#define regVPG8_VPG_GENERIC_PACKET_DATA_BASE_IDX 2 13369#define regVPG8_VPG_GSP_FRAME_UPDATE_CTRL 0x37fb 13370#define regVPG8_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2 13371#define regVPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x37fc 13372#define regVPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2 13373#define regVPG8_VPG_GENERIC_STATUS 0x37fd 13374#define regVPG8_VPG_GENERIC_STATUS_BASE_IDX 2 13375#define regVPG8_VPG_MEM_PWR 0x37fe 13376#define regVPG8_VPG_MEM_PWR_BASE_IDX 2 13377#define regVPG8_VPG_ISRC1_2_ACCESS_CTRL 0x37ff 13378#define regVPG8_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2 13379#define regVPG8_VPG_ISRC1_2_DATA 0x3800 13380#define regVPG8_VPG_ISRC1_2_DATA_BASE_IDX 2 13381#define regVPG8_VPG_MPEG_INFO0 0x3801 13382#define regVPG8_VPG_MPEG_INFO0_BASE_IDX 2 13383#define regVPG8_VPG_MPEG_INFO1 0x3802 13384#define regVPG8_VPG_MPEG_INFO1_BASE_IDX 2 13385 13386 13387// addressBlock: dce_dc_hpo_dp_sym32_enc2_dispdec 13388// base address: 0x1b314 13389#define regDP_SYM32_ENC2_DP_SYM32_ENC_CONTROL 0x3805 13390#define regDP_SYM32_ENC2_DP_SYM32_ENC_CONTROL_BASE_IDX 2 13391#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_FIFO_CONTROL 0x3806 13392#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_FIFO_CONTROL_BASE_IDX 2 13393#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL 0x3807 13394#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 13395#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL 0x3808 13396#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 13397#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT 0x3809 13398#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT_BASE_IDX 2 13399#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA0 0x380a 13400#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA0_BASE_IDX 2 13401#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA1 0x380b 13402#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA1_BASE_IDX 2 13403#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA2 0x380c 13404#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA2_BASE_IDX 2 13405#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA3 0x380d 13406#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA3_BASE_IDX 2 13407#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA4 0x380e 13408#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA4_BASE_IDX 2 13409#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA5 0x380f 13410#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA5_BASE_IDX 2 13411#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA6 0x3810 13412#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA6_BASE_IDX 2 13413#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA7 0x3811 13414#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA7_BASE_IDX 2 13415#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA8 0x3812 13416#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA8_BASE_IDX 2 13417#define regDP_SYM32_ENC2_DP_SYM32_ENC_HBLANK_CONTROL 0x3813 13418#define regDP_SYM32_ENC2_DP_SYM32_ENC_HBLANK_CONTROL_BASE_IDX 2 13419#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0 0x3814 13420#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0_BASE_IDX 2 13421#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1 0x3815 13422#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1_BASE_IDX 2 13423#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2 0x3816 13424#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2_BASE_IDX 2 13425#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3 0x3817 13426#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3_BASE_IDX 2 13427#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4 0x3818 13428#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4_BASE_IDX 2 13429#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5 0x3819 13430#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5_BASE_IDX 2 13431#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6 0x381a 13432#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6_BASE_IDX 2 13433#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7 0x381b 13434#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7_BASE_IDX 2 13435#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8 0x381c 13436#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8_BASE_IDX 2 13437#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9 0x381d 13438#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9_BASE_IDX 2 13439#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10 0x381e 13440#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10_BASE_IDX 2 13441#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11 0x381f 13442#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11_BASE_IDX 2 13443#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12 0x3820 13444#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12_BASE_IDX 2 13445#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13 0x3821 13446#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13_BASE_IDX 2 13447#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14 0x3822 13448#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14_BASE_IDX 2 13449#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_CONTROL 0x3823 13450#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_CONTROL_BASE_IDX 2 13451#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0 0x3824 13452#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0_BASE_IDX 2 13453#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL1 0x3825 13454#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL1_BASE_IDX 2 13455#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL 0x3826 13456#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL_BASE_IDX 2 13457#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_CONTROL 0x382b 13458#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_CONTROL_BASE_IDX 2 13459#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_VBID_CONTROL 0x382c 13460#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_VBID_CONTROL_BASE_IDX 2 13461#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_STREAM_CONTROL 0x382d 13462#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_STREAM_CONTROL_BASE_IDX 2 13463#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL 0x382e 13464#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL_BASE_IDX 2 13465#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_CONTROL 0x382f 13466#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_CONTROL_BASE_IDX 2 13467#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT0 0x3830 13468#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT0_BASE_IDX 2 13469#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT1 0x3831 13470#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT1_BASE_IDX 2 13471#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_STATUS 0x3832 13472#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_STATUS_BASE_IDX 2 13473#define regDP_SYM32_ENC2_DP_SYM32_ENC_MEM_POWER_CONTROL 0x3833 13474#define regDP_SYM32_ENC2_DP_SYM32_ENC_MEM_POWER_CONTROL_BASE_IDX 2 13475#define regDP_SYM32_ENC2_DP_SYM32_ENC_SPARE 0x3834 13476#define regDP_SYM32_ENC2_DP_SYM32_ENC_SPARE_BASE_IDX 2 13477 13478 13479// addressBlock: dce_dc_hpo_dp_stream_enc3_dispdec 13480// base address: 0x1b57c 13481#define regDP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL 0x389f 13482#define regDP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL_BASE_IDX 2 13483#define regDP_STREAM_ENC3_DP_STREAM_ENC_INPUT_MUX_CONTROL 0x38a0 13484#define regDP_STREAM_ENC3_DP_STREAM_ENC_INPUT_MUX_CONTROL_BASE_IDX 2 13485#define regDP_STREAM_ENC3_DP_STREAM_ENC_AUDIO_CONTROL 0x38a1 13486#define regDP_STREAM_ENC3_DP_STREAM_ENC_AUDIO_CONTROL_BASE_IDX 2 13487#define regDP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0 0x38a2 13488#define regDP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0_BASE_IDX 2 13489#define regDP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1 0x38a3 13490#define regDP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1_BASE_IDX 2 13491#define regDP_STREAM_ENC3_DP_STREAM_ENC_SPARE 0x38a4 13492#define regDP_STREAM_ENC3_DP_STREAM_ENC_SPARE_BASE_IDX 2 13493 13494 13495// addressBlock: dce_dc_hpo_dp_stream_enc3_apg_apg_dispdec 13496// base address: 0x1b5b0 13497#define regAPG3_APG_CONTROL 0x38ac 13498#define regAPG3_APG_CONTROL_BASE_IDX 2 13499#define regAPG3_APG_CONTROL2 0x38ad 13500#define regAPG3_APG_CONTROL2_BASE_IDX 2 13501#define regAPG3_APG_DBG_GEN_CONTROL 0x38ae 13502#define regAPG3_APG_DBG_GEN_CONTROL_BASE_IDX 2 13503#define regAPG3_APG_PACKET_CONTROL 0x38af 13504#define regAPG3_APG_PACKET_CONTROL_BASE_IDX 2 13505#define regAPG3_APG_AUDIO_CRC_CONTROL 0x38b6 13506#define regAPG3_APG_AUDIO_CRC_CONTROL_BASE_IDX 2 13507#define regAPG3_APG_AUDIO_CRC_CONTROL2 0x38b7 13508#define regAPG3_APG_AUDIO_CRC_CONTROL2_BASE_IDX 2 13509#define regAPG3_APG_AUDIO_CRC_RESULT 0x38b8 13510#define regAPG3_APG_AUDIO_CRC_RESULT_BASE_IDX 2 13511#define regAPG3_APG_STATUS 0x38bd 13512#define regAPG3_APG_STATUS_BASE_IDX 2 13513#define regAPG3_APG_STATUS2 0x38be 13514#define regAPG3_APG_STATUS2_BASE_IDX 2 13515#define regAPG3_APG_MEM_PWR 0x38c0 13516#define regAPG3_APG_MEM_PWR_BASE_IDX 2 13517#define regAPG3_APG_SPARE 0x38c2 13518#define regAPG3_APG_SPARE_BASE_IDX 2 13519 13520 13521// addressBlock: dce_dc_hpo_dp_stream_enc3_dme_dme_dispdec 13522// base address: 0x1b628 13523#define regDME9_DME_CONTROL 0x38ca 13524#define regDME9_DME_CONTROL_BASE_IDX 2 13525#define regDME9_DME_MEMORY_CONTROL 0x38cb 13526#define regDME9_DME_MEMORY_CONTROL_BASE_IDX 2 13527 13528 13529// addressBlock: dce_dc_hpo_dp_stream_enc3_vpg_vpg_dispdec 13530// base address: 0x1b634 13531#define regVPG9_VPG_GENERIC_PACKET_ACCESS_CTRL 0x38cd 13532#define regVPG9_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2 13533#define regVPG9_VPG_GENERIC_PACKET_DATA 0x38ce 13534#define regVPG9_VPG_GENERIC_PACKET_DATA_BASE_IDX 2 13535#define regVPG9_VPG_GSP_FRAME_UPDATE_CTRL 0x38cf 13536#define regVPG9_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2 13537#define regVPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x38d0 13538#define regVPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2 13539#define regVPG9_VPG_GENERIC_STATUS 0x38d1 13540#define regVPG9_VPG_GENERIC_STATUS_BASE_IDX 2 13541#define regVPG9_VPG_MEM_PWR 0x38d2 13542#define regVPG9_VPG_MEM_PWR_BASE_IDX 2 13543#define regVPG9_VPG_ISRC1_2_ACCESS_CTRL 0x38d3 13544#define regVPG9_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2 13545#define regVPG9_VPG_ISRC1_2_DATA 0x38d4 13546#define regVPG9_VPG_ISRC1_2_DATA_BASE_IDX 2 13547#define regVPG9_VPG_MPEG_INFO0 0x38d5 13548#define regVPG9_VPG_MPEG_INFO0_BASE_IDX 2 13549#define regVPG9_VPG_MPEG_INFO1 0x38d6 13550#define regVPG9_VPG_MPEG_INFO1_BASE_IDX 2 13551 13552 13553// addressBlock: dce_dc_hpo_dp_sym32_enc3_dispdec 13554// base address: 0x1b664 13555#define regDP_SYM32_ENC3_DP_SYM32_ENC_CONTROL 0x38d9 13556#define regDP_SYM32_ENC3_DP_SYM32_ENC_CONTROL_BASE_IDX 2 13557#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_FIFO_CONTROL 0x38da 13558#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_FIFO_CONTROL_BASE_IDX 2 13559#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL 0x38db 13560#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 13561#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL 0x38dc 13562#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 13563#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT 0x38dd 13564#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT_BASE_IDX 2 13565#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA0 0x38de 13566#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA0_BASE_IDX 2 13567#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA1 0x38df 13568#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA1_BASE_IDX 2 13569#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA2 0x38e0 13570#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA2_BASE_IDX 2 13571#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA3 0x38e1 13572#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA3_BASE_IDX 2 13573#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA4 0x38e2 13574#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA4_BASE_IDX 2 13575#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA5 0x38e3 13576#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA5_BASE_IDX 2 13577#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA6 0x38e4 13578#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA6_BASE_IDX 2 13579#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA7 0x38e5 13580#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA7_BASE_IDX 2 13581#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA8 0x38e6 13582#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA8_BASE_IDX 2 13583#define regDP_SYM32_ENC3_DP_SYM32_ENC_HBLANK_CONTROL 0x38e7 13584#define regDP_SYM32_ENC3_DP_SYM32_ENC_HBLANK_CONTROL_BASE_IDX 2 13585#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0 0x38e8 13586#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0_BASE_IDX 2 13587#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1 0x38e9 13588#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1_BASE_IDX 2 13589#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2 0x38ea 13590#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2_BASE_IDX 2 13591#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3 0x38eb 13592#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3_BASE_IDX 2 13593#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4 0x38ec 13594#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4_BASE_IDX 2 13595#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5 0x38ed 13596#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5_BASE_IDX 2 13597#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6 0x38ee 13598#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6_BASE_IDX 2 13599#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7 0x38ef 13600#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7_BASE_IDX 2 13601#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8 0x38f0 13602#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8_BASE_IDX 2 13603#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9 0x38f1 13604#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9_BASE_IDX 2 13605#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10 0x38f2 13606#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10_BASE_IDX 2 13607#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11 0x38f3 13608#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11_BASE_IDX 2 13609#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12 0x38f4 13610#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12_BASE_IDX 2 13611#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13 0x38f5 13612#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13_BASE_IDX 2 13613#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14 0x38f6 13614#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14_BASE_IDX 2 13615#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_CONTROL 0x38f7 13616#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_CONTROL_BASE_IDX 2 13617#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0 0x38f8 13618#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0_BASE_IDX 2 13619#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL1 0x38f9 13620#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL1_BASE_IDX 2 13621#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL 0x38fa 13622#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL_BASE_IDX 2 13623#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_CONTROL 0x38ff 13624#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_CONTROL_BASE_IDX 2 13625#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_VBID_CONTROL 0x3900 13626#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_VBID_CONTROL_BASE_IDX 2 13627#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_STREAM_CONTROL 0x3901 13628#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_STREAM_CONTROL_BASE_IDX 2 13629#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL 0x3902 13630#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL_BASE_IDX 2 13631#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_CONTROL 0x3903 13632#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_CONTROL_BASE_IDX 2 13633#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT0 0x3904 13634#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT0_BASE_IDX 2 13635#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT1 0x3905 13636#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT1_BASE_IDX 2 13637#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_STATUS 0x3906 13638#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_STATUS_BASE_IDX 2 13639#define regDP_SYM32_ENC3_DP_SYM32_ENC_MEM_POWER_CONTROL 0x3907 13640#define regDP_SYM32_ENC3_DP_SYM32_ENC_MEM_POWER_CONTROL_BASE_IDX 2 13641#define regDP_SYM32_ENC3_DP_SYM32_ENC_SPARE 0x3908 13642#define regDP_SYM32_ENC3_DP_SYM32_ENC_SPARE_BASE_IDX 2 13643 13644 13645// addressBlock: dce_dc_hpo_dp_link_enc0_dispdec 13646// base address: 0x1ad5c 13647#define regDP_LINK_ENC0_DP_LINK_ENC_CLOCK_CONTROL 0x3697 13648#define regDP_LINK_ENC0_DP_LINK_ENC_CLOCK_CONTROL_BASE_IDX 2 13649#define regDP_LINK_ENC0_DP_LINK_ENC_SPARE 0x3698 13650#define regDP_LINK_ENC0_DP_LINK_ENC_SPARE_BASE_IDX 2 13651 13652 13653// addressBlock: dce_dc_hpo_dp_dphy_sym320_dispdec 13654// base address: 0x1ae00 13655#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL 0x36c0 13656#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL_BASE_IDX 2 13657#define regDP_DPHY_SYM320_DP_DPHY_SYM32_STATUS 0x36c1 13658#define regDP_DPHY_SYM320_DP_DPHY_SYM32_STATUS_BASE_IDX 2 13659#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_UPDATE 0x36c4 13660#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_UPDATE_BASE_IDX 2 13661#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL0 0x36c5 13662#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL0_BASE_IDX 2 13663#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL1 0x36c6 13664#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL1_BASE_IDX 2 13665#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL2 0x36c7 13666#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL2_BASE_IDX 2 13667#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL3 0x36c8 13668#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL3_BASE_IDX 2 13669#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC0 0x36cb 13670#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC0_BASE_IDX 2 13671#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC1 0x36cc 13672#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC1_BASE_IDX 2 13673#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC2 0x36cd 13674#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC2_BASE_IDX 2 13675#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC3 0x36ce 13676#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC3_BASE_IDX 2 13677#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS0 0x36d1 13678#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS0_BASE_IDX 2 13679#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS1 0x36d2 13680#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS1_BASE_IDX 2 13681#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS2 0x36d3 13682#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS2_BASE_IDX 2 13683#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS3 0x36d4 13684#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS3_BASE_IDX 2 13685#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG 0x36d7 13686#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG_BASE_IDX 2 13687#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED0 0x36d8 13688#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED0_BASE_IDX 2 13689#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED1 0x36d9 13690#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED1_BASE_IDX 2 13691#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED2 0x36da 13692#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED2_BASE_IDX 2 13693#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED3 0x36db 13694#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED3_BASE_IDX 2 13695#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_SQ_PULSE 0x36dc 13696#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_SQ_PULSE_BASE_IDX 2 13697#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM0 0x36dd 13698#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM0_BASE_IDX 2 13699#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM1 0x36de 13700#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM1_BASE_IDX 2 13701#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM2 0x36df 13702#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM2_BASE_IDX 2 13703#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM3 0x36e0 13704#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM3_BASE_IDX 2 13705#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM4 0x36e1 13706#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM4_BASE_IDX 2 13707#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM5 0x36e2 13708#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM5_BASE_IDX 2 13709#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM6 0x36e3 13710#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM6_BASE_IDX 2 13711#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM7 0x36e4 13712#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM7_BASE_IDX 2 13713#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM8 0x36e5 13714#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM8_BASE_IDX 2 13715#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM9 0x36e6 13716#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM9_BASE_IDX 2 13717#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM10 0x36e7 13718#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM10_BASE_IDX 2 13719#define regDP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS 0x36e8 13720#define regDP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS_BASE_IDX 2 13721#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE 0x36ea 13722#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE_BASE_IDX 2 13723#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0 0x36eb 13724#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0_BASE_IDX 2 13725#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG1 0x36ec 13726#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG1_BASE_IDX 2 13727#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_STATUS 0x36ed 13728#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_STATUS_BASE_IDX 2 13729#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_COUNT 0x36ee 13730#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_COUNT_BASE_IDX 2 13731 13732 13733// addressBlock: dce_dc_hpo_dp_link_enc1_dispdec 13734// base address: 0x1b0ac 13735#define regDP_LINK_ENC1_DP_LINK_ENC_CLOCK_CONTROL 0x376b 13736#define regDP_LINK_ENC1_DP_LINK_ENC_CLOCK_CONTROL_BASE_IDX 2 13737#define regDP_LINK_ENC1_DP_LINK_ENC_SPARE 0x376c 13738#define regDP_LINK_ENC1_DP_LINK_ENC_SPARE_BASE_IDX 2 13739 13740 13741// addressBlock: dce_dc_hpo_dp_dphy_sym321_dispdec 13742// base address: 0x1b150 13743#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL 0x3794 13744#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL_BASE_IDX 2 13745#define regDP_DPHY_SYM321_DP_DPHY_SYM32_STATUS 0x3795 13746#define regDP_DPHY_SYM321_DP_DPHY_SYM32_STATUS_BASE_IDX 2 13747#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_UPDATE 0x3798 13748#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_UPDATE_BASE_IDX 2 13749#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL0 0x3799 13750#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL0_BASE_IDX 2 13751#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL1 0x379a 13752#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL1_BASE_IDX 2 13753#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL2 0x379b 13754#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL2_BASE_IDX 2 13755#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL3 0x379c 13756#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL3_BASE_IDX 2 13757#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC0 0x379f 13758#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC0_BASE_IDX 2 13759#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC1 0x37a0 13760#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC1_BASE_IDX 2 13761#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC2 0x37a1 13762#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC2_BASE_IDX 2 13763#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC3 0x37a2 13764#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC3_BASE_IDX 2 13765#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS0 0x37a5 13766#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS0_BASE_IDX 2 13767#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS1 0x37a6 13768#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS1_BASE_IDX 2 13769#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS2 0x37a7 13770#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS2_BASE_IDX 2 13771#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS3 0x37a8 13772#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS3_BASE_IDX 2 13773#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG 0x37ab 13774#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG_BASE_IDX 2 13775#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED0 0x37ac 13776#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED0_BASE_IDX 2 13777#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED1 0x37ad 13778#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED1_BASE_IDX 2 13779#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED2 0x37ae 13780#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED2_BASE_IDX 2 13781#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED3 0x37af 13782#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED3_BASE_IDX 2 13783#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_SQ_PULSE 0x37b0 13784#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_SQ_PULSE_BASE_IDX 2 13785#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM0 0x37b1 13786#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM0_BASE_IDX 2 13787#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM1 0x37b2 13788#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM1_BASE_IDX 2 13789#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM2 0x37b3 13790#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM2_BASE_IDX 2 13791#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM3 0x37b4 13792#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM3_BASE_IDX 2 13793#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM4 0x37b5 13794#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM4_BASE_IDX 2 13795#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM5 0x37b6 13796#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM5_BASE_IDX 2 13797#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM6 0x37b7 13798#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM6_BASE_IDX 2 13799#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM7 0x37b8 13800#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM7_BASE_IDX 2 13801#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM8 0x37b9 13802#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM8_BASE_IDX 2 13803#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM9 0x37ba 13804#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM9_BASE_IDX 2 13805#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM10 0x37bb 13806#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM10_BASE_IDX 2 13807#define regDP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS 0x37bc 13808#define regDP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS_BASE_IDX 2 13809#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE 0x37be 13810#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE_BASE_IDX 2 13811#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0 0x37bf 13812#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0_BASE_IDX 2 13813#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG1 0x37c0 13814#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG1_BASE_IDX 2 13815#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_STATUS 0x37c1 13816#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_STATUS_BASE_IDX 2 13817#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_COUNT 0x37c2 13818#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_COUNT_BASE_IDX 2 13819 13820 13821// addressBlock: dce_dc_dchvm_hvm_dispdec 13822// base address: 0x0 13823#define regDCHVM_CTRL0 0x3603 13824#define regDCHVM_CTRL0_BASE_IDX 2 13825#define regDCHVM_CTRL1 0x3604 13826#define regDCHVM_CTRL1_BASE_IDX 2 13827#define regDCHVM_CLK_CTRL 0x3605 13828#define regDCHVM_CLK_CTRL_BASE_IDX 2 13829#define regDCHVM_MEM_CTRL 0x3606 13830#define regDCHVM_MEM_CTRL_BASE_IDX 2 13831#define regDCHVM_RIOMMU_CTRL0 0x3607 13832#define regDCHVM_RIOMMU_CTRL0_BASE_IDX 2 13833#define regDCHVM_RIOMMU_STAT0 0x3608 13834#define regDCHVM_RIOMMU_STAT0_BASE_IDX 2 13835 13836// addressBlock: vga_vgaseqind 13837// base address: 0x0 13838#define ixSEQ00 0x0000 13839#define ixSEQ01 0x0001 13840#define ixSEQ02 0x0002 13841#define ixSEQ03 0x0003 13842#define ixSEQ04 0x0004 13843 13844 13845// addressBlock: vga_vgacrtind 13846// base address: 0x0 13847#define ixCRT00 0x0000 13848#define ixCRT01 0x0001 13849#define ixCRT02 0x0002 13850#define ixCRT03 0x0003 13851#define ixCRT04 0x0004 13852#define ixCRT05 0x0005 13853#define ixCRT06 0x0006 13854#define ixCRT07 0x0007 13855#define ixCRT08 0x0008 13856#define ixCRT09 0x0009 13857#define ixCRT0A 0x000a 13858#define ixCRT0B 0x000b 13859#define ixCRT0C 0x000c 13860#define ixCRT0D 0x000d 13861#define ixCRT0E 0x000e 13862#define ixCRT0F 0x000f 13863#define ixCRT10 0x0010 13864#define ixCRT11 0x0011 13865#define ixCRT12 0x0012 13866#define ixCRT13 0x0013 13867#define ixCRT14 0x0014 13868#define ixCRT15 0x0015 13869#define ixCRT16 0x0016 13870#define ixCRT17 0x0017 13871#define ixCRT18 0x0018 13872#define ixCRT1E 0x001e 13873#define ixCRT1F 0x001f 13874#define ixCRT22 0x0022 13875 13876 13877// addressBlock: vga_vgagrphind 13878// base address: 0x0 13879#define ixGRA00 0x0000 13880#define ixGRA01 0x0001 13881#define ixGRA02 0x0002 13882#define ixGRA03 0x0003 13883#define ixGRA04 0x0004 13884#define ixGRA05 0x0005 13885#define ixGRA06 0x0006 13886#define ixGRA07 0x0007 13887#define ixGRA08 0x0008 13888 13889 13890// addressBlock: vga_vgaattrind 13891// base address: 0x0 13892#define ixATTR00 0x0000 13893#define ixATTR01 0x0001 13894#define ixATTR02 0x0002 13895#define ixATTR03 0x0003 13896#define ixATTR04 0x0004 13897#define ixATTR05 0x0005 13898#define ixATTR06 0x0006 13899#define ixATTR07 0x0007 13900#define ixATTR08 0x0008 13901#define ixATTR09 0x0009 13902#define ixATTR0A 0x000a 13903#define ixATTR0B 0x000b 13904#define ixATTR0C 0x000c 13905#define ixATTR0D 0x000d 13906#define ixATTR0E 0x000e 13907#define ixATTR0F 0x000f 13908#define ixATTR10 0x0010 13909#define ixATTR11 0x0011 13910#define ixATTR12 0x0012 13911#define ixATTR13 0x0013 13912#define ixATTR14 0x0014 13913 13914 13915// addressBlock: azendpoint_f2codecind 13916// base address: 0x0 13917#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x2200 13918#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x2706 13919#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x270d 13920#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2 0x270e 13921#define ixAZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL 0x2724 13922#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3 0x273e 13923#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x2770 13924#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x2771 13925#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x2f09 13926#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x2f0a 13927#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x2f0b 13928#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY 0x3702 13929#define ixAZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x3707 13930#define ixAZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x3708 13931#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x3709 13932#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x371c 13933#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2 0x371d 13934#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3 0x371e 13935#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4 0x371f 13936#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION 0x3770 13937#define ixAZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION 0x3771 13938#define ixAZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO 0x3772 13939#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR 0x3776 13940#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA 0x3776 13941#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE 0x3777 13942#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE 0x3778 13943#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE 0x3779 13944#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE 0x377a 13945#define ixAZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC 0x377b 13946#define ixAZALIA_F2_CODEC_PIN_CONTROL_HBR 0x377c 13947#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX 0x3780 13948#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA 0x3781 13949#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE 0x3785 13950#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE 0x3786 13951#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE 0x3787 13952#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE 0x3788 13953#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x3789 13954#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x378a 13955#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x378b 13956#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x378c 13957#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x378d 13958#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x378e 13959#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x378f 13960#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x3790 13961#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x3791 13962#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x3792 13963#define ixAZALIA_F2_CODEC_PIN_ASSOCIATION_INFO 0x3793 13964#define ixAZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x3797 13965#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x3798 13966#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB 0x3799 13967#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x379a 13968#define ixAZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE 0x379b 13969#define ixAZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x379c 13970#define ixAZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x379d 13971#define ixAZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x379e 13972#define ixAZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x3f09 13973#define ixAZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES 0x3f0c 13974#define ixAZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH 0x3f0e 13975 13976 13977// addressBlock: azendpoint_descriptorind 13978// base address: 0x0 13979#define ixAUDIO_DESCRIPTOR0 0x0001 13980#define ixAUDIO_DESCRIPTOR1 0x0002 13981#define ixAUDIO_DESCRIPTOR2 0x0003 13982#define ixAUDIO_DESCRIPTOR3 0x0004 13983#define ixAUDIO_DESCRIPTOR4 0x0005 13984#define ixAUDIO_DESCRIPTOR5 0x0006 13985#define ixAUDIO_DESCRIPTOR6 0x0007 13986#define ixAUDIO_DESCRIPTOR7 0x0008 13987#define ixAUDIO_DESCRIPTOR8 0x0009 13988#define ixAUDIO_DESCRIPTOR9 0x000a 13989#define ixAUDIO_DESCRIPTOR10 0x000b 13990#define ixAUDIO_DESCRIPTOR11 0x000c 13991#define ixAUDIO_DESCRIPTOR12 0x000d 13992#define ixAUDIO_DESCRIPTOR13 0x000e 13993 13994 13995// addressBlock: azendpoint_sinkinfoind 13996// base address: 0x0 13997#define ixAZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID 0x0000 13998#define ixAZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID 0x0001 13999#define ixAZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN 0x0002 14000#define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID0 0x0003 14001#define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID1 0x0004 14002#define ixSINK_DESCRIPTION0 0x0005 14003#define ixSINK_DESCRIPTION1 0x0006 14004#define ixSINK_DESCRIPTION2 0x0007 14005#define ixSINK_DESCRIPTION3 0x0008 14006#define ixSINK_DESCRIPTION4 0x0009 14007#define ixSINK_DESCRIPTION5 0x000a 14008#define ixSINK_DESCRIPTION6 0x000b 14009#define ixSINK_DESCRIPTION7 0x000c 14010#define ixSINK_DESCRIPTION8 0x000d 14011#define ixSINK_DESCRIPTION9 0x000e 14012#define ixSINK_DESCRIPTION10 0x000f 14013#define ixSINK_DESCRIPTION11 0x0010 14014#define ixSINK_DESCRIPTION12 0x0011 14015#define ixSINK_DESCRIPTION13 0x0012 14016#define ixSINK_DESCRIPTION14 0x0013 14017#define ixSINK_DESCRIPTION15 0x0014 14018#define ixSINK_DESCRIPTION16 0x0015 14019#define ixSINK_DESCRIPTION17 0x0016 14020 14021 14022// addressBlock: azf0controller_azinputcrc0resultind 14023// base address: 0x0 14024#define ixAZALIA_INPUT_CRC0_CHANNEL0 0x0000 14025#define ixAZALIA_INPUT_CRC0_CHANNEL1 0x0001 14026#define ixAZALIA_INPUT_CRC0_CHANNEL2 0x0002 14027#define ixAZALIA_INPUT_CRC0_CHANNEL3 0x0003 14028#define ixAZALIA_INPUT_CRC0_CHANNEL4 0x0004 14029#define ixAZALIA_INPUT_CRC0_CHANNEL5 0x0005 14030#define ixAZALIA_INPUT_CRC0_CHANNEL6 0x0006 14031#define ixAZALIA_INPUT_CRC0_CHANNEL7 0x0007 14032 14033 14034// addressBlock: azf0controller_azinputcrc1resultind 14035// base address: 0x0 14036#define ixAZALIA_INPUT_CRC1_CHANNEL0 0x0000 14037#define ixAZALIA_INPUT_CRC1_CHANNEL1 0x0001 14038#define ixAZALIA_INPUT_CRC1_CHANNEL2 0x0002 14039#define ixAZALIA_INPUT_CRC1_CHANNEL3 0x0003 14040#define ixAZALIA_INPUT_CRC1_CHANNEL4 0x0004 14041#define ixAZALIA_INPUT_CRC1_CHANNEL5 0x0005 14042#define ixAZALIA_INPUT_CRC1_CHANNEL6 0x0006 14043#define ixAZALIA_INPUT_CRC1_CHANNEL7 0x0007 14044 14045 14046// addressBlock: azf0controller_azcrc0resultind 14047// base address: 0x0 14048#define ixAZALIA_CRC0_CHANNEL0 0x0000 14049#define ixAZALIA_CRC0_CHANNEL1 0x0001 14050#define ixAZALIA_CRC0_CHANNEL2 0x0002 14051#define ixAZALIA_CRC0_CHANNEL3 0x0003 14052#define ixAZALIA_CRC0_CHANNEL4 0x0004 14053#define ixAZALIA_CRC0_CHANNEL5 0x0005 14054#define ixAZALIA_CRC0_CHANNEL6 0x0006 14055#define ixAZALIA_CRC0_CHANNEL7 0x0007 14056 14057 14058// addressBlock: azf0controller_azcrc1resultind 14059// base address: 0x0 14060#define ixAZALIA_CRC1_CHANNEL0 0x0000 14061#define ixAZALIA_CRC1_CHANNEL1 0x0001 14062#define ixAZALIA_CRC1_CHANNEL2 0x0002 14063#define ixAZALIA_CRC1_CHANNEL3 0x0003 14064#define ixAZALIA_CRC1_CHANNEL4 0x0004 14065#define ixAZALIA_CRC1_CHANNEL5 0x0005 14066#define ixAZALIA_CRC1_CHANNEL6 0x0006 14067#define ixAZALIA_CRC1_CHANNEL7 0x0007 14068 14069 14070// addressBlock: azinputendpoint_f2codecind 14071// base address: 0x0 14072#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x6200 14073#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x6706 14074#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x670d 14075#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x6f09 14076#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x6f0a 14077#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x6f0b 14078#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x7707 14079#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x7708 14080#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE 0x7709 14081#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x771c 14082#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2 0x771d 14083#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3 0x771e 14084#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4 0x771f 14085#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x7771 14086#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE 0x7777 14087#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE 0x7778 14088#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE 0x7779 14089#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE 0x777a 14090#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR 0x777c 14091#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE 0x7785 14092#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE 0x7786 14093#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE 0x7787 14094#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE 0x7788 14095#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x7798 14096#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB 0x7799 14097#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x779a 14098#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x779b 14099#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x779c 14100#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L 0x779d 14101#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H 0x779e 14102#define ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x7f09 14103#define ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x7f0c 14104 14105 14106// addressBlock: azroot_f2codecind 14107// base address: 0x0 14108#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID 0x0f00 14109#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID 0x0f02 14110#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT 0x0f04 14111#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE 0x1705 14112#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID 0x1720 14113#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2 0x1721 14114#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3 0x1722 14115#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4 0x1723 14116#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION 0x1770 14117#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESET 0x17ff 14118#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT 0x1f04 14119#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE 0x1f05 14120#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES 0x1f0a 14121#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS 0x1f0b 14122#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES 0x1f0f 14123 14124 14125// addressBlock: azf0stream0_streamind 14126// base address: 0x0 14127#define ixAZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL 0x0000 14128#define ixAZF0STREAM0_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 14129#define ixAZF0STREAM0_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 14130#define ixAZF0STREAM0_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 14131#define ixAZF0STREAM0_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 14132 14133 14134// addressBlock: azf0stream1_streamind 14135// base address: 0x0 14136#define ixAZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL 0x0000 14137#define ixAZF0STREAM1_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 14138#define ixAZF0STREAM1_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 14139#define ixAZF0STREAM1_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 14140#define ixAZF0STREAM1_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 14141 14142 14143// addressBlock: azf0stream2_streamind 14144// base address: 0x0 14145#define ixAZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL 0x0000 14146#define ixAZF0STREAM2_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 14147#define ixAZF0STREAM2_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 14148#define ixAZF0STREAM2_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 14149#define ixAZF0STREAM2_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 14150 14151 14152// addressBlock: azf0stream3_streamind 14153// base address: 0x0 14154#define ixAZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL 0x0000 14155#define ixAZF0STREAM3_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 14156#define ixAZF0STREAM3_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 14157#define ixAZF0STREAM3_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 14158#define ixAZF0STREAM3_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 14159 14160 14161// addressBlock: azf0stream4_streamind 14162// base address: 0x0 14163#define ixAZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL 0x0000 14164#define ixAZF0STREAM4_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 14165#define ixAZF0STREAM4_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 14166#define ixAZF0STREAM4_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 14167#define ixAZF0STREAM4_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 14168 14169 14170// addressBlock: azf0stream5_streamind 14171// base address: 0x0 14172#define ixAZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL 0x0000 14173#define ixAZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 14174#define ixAZF0STREAM5_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 14175#define ixAZF0STREAM5_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 14176#define ixAZF0STREAM5_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 14177 14178 14179// addressBlock: azf0stream6_streamind 14180// base address: 0x0 14181#define ixAZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL 0x0000 14182#define ixAZF0STREAM6_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 14183#define ixAZF0STREAM6_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 14184#define ixAZF0STREAM6_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 14185#define ixAZF0STREAM6_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 14186 14187 14188// addressBlock: azf0stream7_streamind 14189// base address: 0x0 14190#define ixAZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL 0x0000 14191#define ixAZF0STREAM7_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 14192#define ixAZF0STREAM7_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 14193#define ixAZF0STREAM7_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 14194#define ixAZF0STREAM7_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 14195 14196 14197// addressBlock: azf0stream8_streamind 14198// base address: 0x0 14199#define ixAZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL 0x0000 14200#define ixAZF0STREAM8_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 14201#define ixAZF0STREAM8_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 14202#define ixAZF0STREAM8_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 14203#define ixAZF0STREAM8_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 14204 14205 14206// addressBlock: azf0stream9_streamind 14207// base address: 0x0 14208#define ixAZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL 0x0000 14209#define ixAZF0STREAM9_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 14210#define ixAZF0STREAM9_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 14211#define ixAZF0STREAM9_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 14212#define ixAZF0STREAM9_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 14213 14214 14215// addressBlock: azf0stream10_streamind 14216// base address: 0x0 14217#define ixAZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL 0x0000 14218#define ixAZF0STREAM10_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 14219#define ixAZF0STREAM10_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 14220#define ixAZF0STREAM10_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 14221#define ixAZF0STREAM10_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 14222 14223 14224// addressBlock: azf0stream11_streamind 14225// base address: 0x0 14226#define ixAZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL 0x0000 14227#define ixAZF0STREAM11_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 14228#define ixAZF0STREAM11_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 14229#define ixAZF0STREAM11_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 14230#define ixAZF0STREAM11_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 14231 14232 14233// addressBlock: azf0stream12_streamind 14234// base address: 0x0 14235#define ixAZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL 0x0000 14236#define ixAZF0STREAM12_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 14237#define ixAZF0STREAM12_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 14238#define ixAZF0STREAM12_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 14239#define ixAZF0STREAM12_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 14240 14241 14242// addressBlock: azf0stream13_streamind 14243// base address: 0x0 14244#define ixAZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL 0x0000 14245#define ixAZF0STREAM13_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 14246#define ixAZF0STREAM13_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 14247#define ixAZF0STREAM13_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 14248#define ixAZF0STREAM13_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 14249 14250 14251// addressBlock: azf0stream14_streamind 14252// base address: 0x0 14253#define ixAZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL 0x0000 14254#define ixAZF0STREAM14_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 14255#define ixAZF0STREAM14_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 14256#define ixAZF0STREAM14_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 14257#define ixAZF0STREAM14_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 14258 14259 14260// addressBlock: azf0stream15_streamind 14261// base address: 0x0 14262#define ixAZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL 0x0000 14263#define ixAZF0STREAM15_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 14264#define ixAZF0STREAM15_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 14265#define ixAZF0STREAM15_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 14266#define ixAZF0STREAM15_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 14267 14268 14269// addressBlock: azf0endpoint0_endpointind 14270// base address: 0x0 14271#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 14272#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 14273#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 14274#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 14275#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 14276#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 14277#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 14278#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 14279#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 14280#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c 14281#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d 14282#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e 14283#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 14284#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 14285#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 14286#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 14287#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 14288#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 14289#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 14290#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 14291#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a 14292#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b 14293#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c 14294#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d 14295#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e 14296#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f 14297#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 14298#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 14299#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 14300#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 14301#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 14302#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 14303#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 14304#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 14305#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 14306#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a 14307#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b 14308#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c 14309#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d 14310#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e 14311#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f 14312#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 14313#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 14314#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 14315#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 14316#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 14317#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 14318#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 14319#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 14320#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 14321#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a 14322#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b 14323#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c 14324#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d 14325#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e 14326#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f 14327#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 14328#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 14329#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 14330#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 14331#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 14332#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 14333#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 14334#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 14335#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 14336#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 14337#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a 14338#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b 14339#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c 14340#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d 14341#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e 14342 14343 14344// addressBlock: azf0endpoint1_endpointind 14345// base address: 0x0 14346#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 14347#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 14348#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 14349#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 14350#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 14351#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 14352#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 14353#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 14354#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 14355#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c 14356#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d 14357#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e 14358#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 14359#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 14360#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 14361#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 14362#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 14363#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 14364#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 14365#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 14366#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a 14367#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b 14368#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c 14369#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d 14370#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e 14371#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f 14372#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 14373#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 14374#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 14375#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 14376#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 14377#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 14378#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 14379#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 14380#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 14381#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a 14382#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b 14383#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c 14384#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d 14385#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e 14386#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f 14387#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 14388#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 14389#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 14390#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 14391#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 14392#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 14393#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 14394#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 14395#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 14396#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a 14397#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b 14398#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c 14399#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d 14400#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e 14401#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f 14402#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 14403#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 14404#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 14405#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 14406#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 14407#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 14408#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 14409#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 14410#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 14411#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 14412#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a 14413#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b 14414#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c 14415#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d 14416#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e 14417 14418 14419// addressBlock: azf0endpoint2_endpointind 14420// base address: 0x0 14421#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 14422#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 14423#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 14424#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 14425#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 14426#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 14427#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 14428#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 14429#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 14430#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c 14431#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d 14432#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e 14433#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 14434#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 14435#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 14436#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 14437#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 14438#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 14439#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 14440#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 14441#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a 14442#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b 14443#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c 14444#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d 14445#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e 14446#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f 14447#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 14448#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 14449#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 14450#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 14451#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 14452#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 14453#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 14454#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 14455#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 14456#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a 14457#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b 14458#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c 14459#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d 14460#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e 14461#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f 14462#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 14463#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 14464#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 14465#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 14466#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 14467#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 14468#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 14469#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 14470#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 14471#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a 14472#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b 14473#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c 14474#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d 14475#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e 14476#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f 14477#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 14478#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 14479#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 14480#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 14481#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 14482#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 14483#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 14484#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 14485#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 14486#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 14487#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a 14488#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b 14489#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c 14490#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d 14491#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e 14492 14493 14494// addressBlock: azf0endpoint3_endpointind 14495// base address: 0x0 14496#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 14497#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 14498#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 14499#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 14500#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 14501#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 14502#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 14503#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 14504#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 14505#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c 14506#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d 14507#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e 14508#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 14509#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 14510#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 14511#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 14512#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 14513#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 14514#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 14515#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 14516#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a 14517#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b 14518#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c 14519#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d 14520#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e 14521#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f 14522#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 14523#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 14524#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 14525#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 14526#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 14527#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 14528#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 14529#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 14530#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 14531#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a 14532#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b 14533#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c 14534#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d 14535#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e 14536#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f 14537#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 14538#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 14539#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 14540#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 14541#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 14542#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 14543#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 14544#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 14545#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 14546#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a 14547#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b 14548#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c 14549#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d 14550#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e 14551#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f 14552#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 14553#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 14554#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 14555#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 14556#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 14557#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 14558#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 14559#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 14560#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 14561#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 14562#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a 14563#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b 14564#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c 14565#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d 14566#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e 14567 14568 14569// addressBlock: azf0endpoint4_endpointind 14570// base address: 0x0 14571#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 14572#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 14573#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 14574#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 14575#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 14576#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 14577#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 14578#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 14579#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 14580#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c 14581#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d 14582#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e 14583#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 14584#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 14585#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 14586#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 14587#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 14588#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 14589#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 14590#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 14591#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a 14592#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b 14593#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c 14594#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d 14595#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e 14596#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f 14597#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 14598#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 14599#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 14600#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 14601#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 14602#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 14603#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 14604#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 14605#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 14606#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a 14607#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b 14608#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c 14609#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d 14610#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e 14611#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f 14612#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 14613#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 14614#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 14615#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 14616#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 14617#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 14618#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 14619#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 14620#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 14621#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a 14622#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b 14623#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c 14624#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d 14625#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e 14626#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f 14627#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 14628#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 14629#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 14630#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 14631#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 14632#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 14633#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 14634#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 14635#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 14636#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 14637#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a 14638#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b 14639#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c 14640#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d 14641#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e 14642 14643 14644// addressBlock: azf0endpoint5_endpointind 14645// base address: 0x0 14646#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 14647#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 14648#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 14649#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 14650#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 14651#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 14652#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 14653#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 14654#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 14655#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c 14656#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d 14657#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e 14658#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 14659#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 14660#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 14661#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 14662#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 14663#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 14664#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 14665#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 14666#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a 14667#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b 14668#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c 14669#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d 14670#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e 14671#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f 14672#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 14673#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 14674#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 14675#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 14676#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 14677#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 14678#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 14679#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 14680#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 14681#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a 14682#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b 14683#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c 14684#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d 14685#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e 14686#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f 14687#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 14688#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 14689#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 14690#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 14691#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 14692#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 14693#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 14694#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 14695#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 14696#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a 14697#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b 14698#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c 14699#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d 14700#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e 14701#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f 14702#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 14703#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 14704#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 14705#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 14706#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 14707#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 14708#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 14709#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 14710#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 14711#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 14712#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a 14713#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b 14714#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c 14715#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d 14716#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e 14717 14718 14719// addressBlock: azf0endpoint6_endpointind 14720// base address: 0x0 14721#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 14722#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 14723#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 14724#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 14725#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 14726#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 14727#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 14728#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 14729#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 14730#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c 14731#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d 14732#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e 14733#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 14734#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 14735#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 14736#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 14737#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 14738#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 14739#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 14740#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 14741#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a 14742#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b 14743#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c 14744#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d 14745#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e 14746#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f 14747#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 14748#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 14749#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 14750#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 14751#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 14752#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 14753#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 14754#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 14755#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 14756#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a 14757#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b 14758#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c 14759#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d 14760#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e 14761#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f 14762#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 14763#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 14764#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 14765#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 14766#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 14767#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 14768#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 14769#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 14770#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 14771#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a 14772#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b 14773#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c 14774#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d 14775#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e 14776#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f 14777#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 14778#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 14779#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 14780#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 14781#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 14782#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 14783#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 14784#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 14785#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 14786#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 14787#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a 14788#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b 14789#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c 14790#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d 14791#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e 14792 14793 14794// addressBlock: azf0endpoint7_endpointind 14795// base address: 0x0 14796#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 14797#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 14798#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 14799#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 14800#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 14801#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 14802#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 14803#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 14804#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 14805#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c 14806#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d 14807#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e 14808#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 14809#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 14810#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 14811#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 14812#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 14813#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 14814#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 14815#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 14816#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a 14817#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b 14818#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c 14819#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d 14820#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e 14821#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f 14822#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 14823#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 14824#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 14825#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 14826#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 14827#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 14828#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 14829#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 14830#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 14831#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a 14832#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b 14833#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c 14834#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d 14835#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e 14836#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f 14837#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 14838#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 14839#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 14840#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 14841#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 14842#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 14843#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 14844#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 14845#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 14846#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a 14847#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b 14848#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c 14849#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d 14850#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e 14851#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f 14852#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 14853#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 14854#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 14855#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 14856#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 14857#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 14858#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 14859#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 14860#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 14861#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 14862#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a 14863#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b 14864#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c 14865#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d 14866#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e 14867 14868 14869// addressBlock: azf0inputendpoint0_inputendpointind 14870// base address: 0x0 14871#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 14872#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 14873#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 14874#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 14875#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 14876#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 14877#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 14878#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 14879#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 14880#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 14881#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 14882#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 14883#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 14884#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 14885#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 14886#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 14887#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 14888#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 14889#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 14890#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 14891#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 14892#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 14893#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 14894 14895 14896// addressBlock: azf0inputendpoint1_inputendpointind 14897// base address: 0x0 14898#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 14899#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 14900#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 14901#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 14902#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 14903#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 14904#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 14905#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 14906#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 14907#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 14908#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 14909#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 14910#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 14911#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 14912#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 14913#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 14914#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 14915#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 14916#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 14917#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 14918#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 14919#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 14920#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 14921 14922 14923// addressBlock: azf0inputendpoint2_inputendpointind 14924// base address: 0x0 14925#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 14926#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 14927#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 14928#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 14929#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 14930#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 14931#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 14932#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 14933#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 14934#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 14935#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 14936#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 14937#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 14938#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 14939#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 14940#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 14941#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 14942#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 14943#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 14944#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 14945#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 14946#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 14947#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 14948 14949 14950// addressBlock: azf0inputendpoint3_inputendpointind 14951// base address: 0x0 14952#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 14953#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 14954#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 14955#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 14956#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 14957#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 14958#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 14959#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 14960#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 14961#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 14962#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 14963#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 14964#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 14965#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 14966#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 14967#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 14968#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 14969#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 14970#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 14971#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 14972#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 14973#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 14974#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 14975 14976 14977// addressBlock: azf0inputendpoint4_inputendpointind 14978// base address: 0x0 14979#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 14980#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 14981#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 14982#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 14983#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 14984#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 14985#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 14986#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 14987#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 14988#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 14989#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 14990#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 14991#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 14992#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 14993#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 14994#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 14995#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 14996#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 14997#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 14998#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 14999#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 15000#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 15001#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 15002 15003 15004// addressBlock: azf0inputendpoint5_inputendpointind 15005// base address: 0x0 15006#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 15007#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 15008#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 15009#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 15010#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 15011#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 15012#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 15013#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 15014#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 15015#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 15016#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 15017#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 15018#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 15019#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 15020#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 15021#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 15022#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 15023#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 15024#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 15025#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 15026#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 15027#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 15028#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 15029 15030 15031// addressBlock: azf0inputendpoint6_inputendpointind 15032// base address: 0x0 15033#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 15034#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 15035#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 15036#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 15037#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 15038#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 15039#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 15040#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 15041#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 15042#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 15043#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 15044#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 15045#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 15046#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 15047#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 15048#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 15049#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 15050#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 15051#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 15052#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 15053#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 15054#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 15055#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 15056 15057 15058// addressBlock: azf0inputendpoint7_inputendpointind 15059// base address: 0x0 15060#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 15061#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 15062#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 15063#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 15064#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 15065#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 15066#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 15067#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 15068#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 15069#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 15070#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 15071#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 15072#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 15073#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 15074#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 15075#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 15076#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 15077#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 15078#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 15079#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 15080#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 15081#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 15082#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 15083 15084 15085#endif 15086