| #
f8646661 |
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18-Aug-2020 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: fix up DCHUBBUB_SDPIF_MMIO_CNTRL_0 handling
Properly define this register using a relative offset rather
than an absolute offset and use the proper SOC15 macros to
access it. It's also DCN, not DCE, so remove it from the
DCE12 header.
No functional change.
Acked-by: Nirmoy Das <nirmoy.das@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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| #
a3ed353c |
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27-Jan-2020 |
Shirish S <shirish.s@amd.com> |
amdgpu/gmc_v9: save/restore sdpif regs during S3
fixes S3 issue with IOMMU + S/G enabled @ 64M VRAM.
Suggested-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Shirish S <shirish.s@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
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| #
c2ecd79b |
|
27-Jan-2020 |
Shirish S <shirish.s@amd.com> |
amdgpu/gmc_v9: save/restore sdpif regs during S3
fixes S3 issue with IOMMU + S/G enabled @ 64M VRAM.
Suggested-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Shirish S <shirish.s@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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| #
d82420b5 |
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14-Feb-2018 |
Roman Li <Roman.Li@amd.com> |
drm/amd: Add dce-12.1 gpio aux registers (v2)
Updating dce12 register headers by adding dc registers
required for potential DP LTTPR support.
v2: fix mode change
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Roman Li <Roman.Li@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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| #
135d4b10 |
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23-Nov-2017 |
Feifei Xu <Feifei.Xu@amd.com> |
drm/amd/include:cleanup vega10 dce header files.
Cleanup asic_reg/vega10/DC folder.Remove dce_12_0_default.h.
Signed-off-by: Feifei Xu <Feifei.Xu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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