Searched refs:fifo (Results 1 - 18 of 18) sorted by relevance

/haiku/src/add-ons/kernel/network/stack/
H A Dutility.cpp161 // #pragma mark - fifo
165 init_fifo(net_fifo* fifo, const char* name, size_t maxBytes) argument
167 mutex_init_etc(&fifo->lock, name, MUTEX_FLAG_CLONE_NAME);
168 fifo->notify = create_sem(0, name);
169 if (fifo->notify < B_OK) {
170 mutex_destroy(&fifo->lock);
171 return fifo->notify;
174 fifo->max_bytes = maxBytes;
175 fifo->current_bytes = 0;
176 fifo
184 uninit_fifo(net_fifo* fifo) argument
194 base_fifo_enqueue_buffer(net_fifo* fifo, net_buffer* buffer) argument
209 fifo_enqueue_buffer(net_fifo* fifo, net_buffer* buffer) argument
226 fifo_dequeue_buffer(net_fifo* fifo, uint32 flags, bigtime_t timeout, net_buffer** _buffer) argument
284 clear_fifo(net_fifo* fifo) argument
302 fifo_socket_enqueue_buffer(net_fifo* fifo, net_socket* socket, uint8 event, net_buffer* _buffer) argument
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H A Dutility.h55 status_t init_fifo(net_fifo* fifo, const char *name, size_t maxBytes);
56 void uninit_fifo(net_fifo* fifo);
57 status_t fifo_enqueue_buffer(net_fifo* fifo, struct net_buffer* buffer);
58 ssize_t fifo_dequeue_buffer(net_fifo* fifo, uint32 flags, bigtime_t timeout,
60 status_t clear_fifo(net_fifo* fifo);
61 status_t fifo_socket_enqueue_buffer(net_fifo* fifo, net_socket* socket,
/haiku/src/system/kernel/arch/arm64/
H A Darch_uart_linflex.cpp65 // Set LCR 8n1, enable fifo
101 // Wait until there is room in fifo
102 bool fifo = LinflexCell()->UARTCR.B.TFBM == 1; local
104 if (fifo) {
113 if (!fifo) {
138 bool fifo = LinflexCell()->UARTCR.B.RFBM == 1; local
140 if (fifo) {
183 // Wait until transmit fifo empty
190 // Wait until receive fifo empty
/haiku/src/add-ons/accelerants/nvidia/engine/
H A Dnv_acc.c1003 /*** setup acceleration engine command shortcuts (so via fifo) ***/
1009 si->engine.fifo.handle[0] = NV_ROP5_SOLID;
1010 si->engine.fifo.handle[1] = NV_IMAGE_BLACK_RECTANGLE;
1011 si->engine.fifo.handle[2] = NV_IMAGE_PATTERN;
1012 si->engine.fifo.handle[3] = NV4_SURFACE; /* NV10_CONTEXT_SURFACES_2D is identical */
1013 si->engine.fifo.handle[4] = NV_IMAGE_BLIT;
1014 si->engine.fifo.handle[5] = NV4_GDI_RECTANGLE_TEXT;
1017 si->engine.fifo.handle[6] = NV1_RENDER_SOLID_LIN;
1018 si->engine.fifo.handle[7] = NV4_DX5_TEXTURE_TRIANGLE;
1023 si->engine.fifo
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H A Dnv_acc_dma.c1027 si->engine.fifo.handle[0] = NV_ROP5_SOLID;
1028 si->engine.fifo.handle[1] = NV_IMAGE_BLACK_RECTANGLE;
1029 si->engine.fifo.handle[2] = NV_IMAGE_PATTERN;
1030 si->engine.fifo.handle[3] = NV4_SURFACE; /* NV10_CONTEXT_SURFACES_2D is identical */
1031 si->engine.fifo.handle[4] = NV_IMAGE_BLIT;
1032 si->engine.fifo.handle[5] = NV4_GDI_RECTANGLE_TEXT;
1033 si->engine.fifo.handle[6] = NV4_CONTEXT_SURFACES_ARGB_ZS;//NV1_RENDER_SOLID_LIN;
1034 si->engine.fifo.handle[7] = NV4_DX5_TEXTURE_TRIANGLE;
1038 si->engine.fifo.ch_ptr[cnt] = 0;
1045 si->engine.fifo
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/haiku/headers/private/net/
H A Dnet_stack.h146 // fifo
147 status_t (*init_fifo)(net_fifo* fifo, const char* name, size_t maxBytes);
148 void (*uninit_fifo)(net_fifo* fifo);
149 status_t (*fifo_enqueue_buffer)(net_fifo* fifo, net_buffer* buffer);
150 ssize_t (*fifo_dequeue_buffer)(net_fifo* fifo, uint32 flags,
152 status_t (*clear_fifo)(net_fifo* fifo);
153 status_t (*fifo_socket_enqueue_buffer)(net_fifo* fifo,
/haiku/src/system/kernel/fs/
H A Dfifo.cpp8 #include "fifo.h"
46 namespace fifo { namespace
530 THREAD_BLOCK_TYPE_OTHER, "fifo read request");
643 TRACE("Inode %p::Open(): fifo becomes active\n", this);
848 FIFOInode* fifo = (FIFOInode*)vnode->private_node; local
849 fs_vnode* superVnode = fifo->SuperVnode();
855 delete fifo;
864 FIFOInode* fifo = (FIFOInode*)vnode->private_node; local
865 fs_vnode* superVnode = fifo->SuperVnode();
871 delete fifo;
903 FIFOInode* fifo = (FIFOInode*)vnode->private_node; local
1008 FIFOInode* fifo = (FIFOInode*)vnode->private_node; local
1195 FIFOInode* fifo = (FIFOInode*)vnode->private_node; local
1300 FIFOInode* fifo = new(std::nothrow) FIFOInode(vnode); local
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/haiku/src/add-ons/kernel/network/protocols/unix/
H A DUnixStreamEndpoint.cpp285 UnixFifo* fifo = new(nothrow) UnixFifo(UNIX_MAX_TRANSFER_UNIT, UnixFifoType::Stream); local
287 ObjectDeleter<UnixFifo> fifoDeleter(fifo);
291 if ((error = fifo->Init()) != B_OK || (error = peerFifo->Init()) != B_OK)
314 fReceiveFifo = fifo;
507 UnixFifo* fifo = fReceiveFifo; local
508 BReference<UnixFifo> _(fifo);
509 UnixFifoLocker fifoLocker(fifo);
514 ssize_t result = fifo->Read(vecs, vecCount, _ancillaryData, NULL, timeout);
517 size_t writable = fifo->Writable();
519 && !fifo
705 _Spawn(UnixStreamEndpoint* connectingEndpoint, UnixStreamEndpoint* listeningEndpoint, UnixFifo* fifo) argument
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H A DUnixDatagramEndpoint.cpp365 UnixFifo* fifo = fReceiveFifo; local
366 BReference<UnixFifo> fifoReference(fifo);
367 UnixFifoLocker fifoLocker(fifo);
373 ssize_t result = fifo->Read(vecs, vecCount, _ancillaryData, &addressStorage, timeout);
376 size_t writable = fifo->Writable();
378 && !fifo->IsWriteShutdown());
382 size_t readable = fifo->Readable();
384 && !fifo->IsReadShutdown());
H A DUnixStreamEndpoint.h75 UnixStreamEndpoint* listeningEndpoint, UnixFifo* fifo);
/haiku/src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/
H A Dif_ath_tx_edma.c184 "%s: called; TXQ=%d, fifo.depth=%d, axq_q empty=%d\n",
274 TAILQ_CONCAT(&txq->fifo.axq_q, &sq, bf_list);
276 txq->fifo.axq_depth += sqdepth;
281 "%s: queued %d packets; depth=%d, fifo depth=%d\n",
282 __func__, sqdepth, txq->fifo.axq_depth, txq->axq_fifo_depth);
293 txq->fifo.axq_depth);
309 "%s: Q%d: called; fifo.depth=%d, fifo depth=%d, depth=%d, aggr_depth=%d\n",
312 txq->fifo.axq_depth,
365 txq->fifo
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H A Dif_ath_beacon.c642 TAILQ_CONCAT(&cabq->fifo.axq_q, &cabq->axq_q, bf_list);
644 cabq->fifo.axq_depth += cabq->axq_depth;
H A Dif_ath_tx.c1962 if (sc->sc_cabq->axq_depth + sc->sc_cabq->fifo.axq_depth
2461 if (sc->sc_cabq->axq_depth + sc->sc_cabq->fifo.axq_depth
3222 if (txq->axq_depth + txq->fifo.axq_depth == 0) {
3260 } else if ((txq->axq_depth + txq->fifo.axq_depth < sc->sc_hwq_limit_nonaggr) &&
5772 * fifo.axq_depth is the number of frames (or aggregates) pushed
5787 * and fifo.axq_depth is how many frames have been dispatched
5790 if (txq->axq_depth + txq->fifo.axq_depth >= sc->sc_hwq_limit_nonaggr) {
5827 if (txq->axq_aggr_depth + txq->fifo.axq_depth >= sc->sc_hwq_limit_aggr) {
H A Dif_ath.c3962 TAILQ_INIT(&txq->fifo.axq_q);
4921 bf = TAILQ_FIRST(&txq->fifo.axq_q);
4930 "%s: Q%d: fifo_depth=0, fifo.axq_depth=%d?\n",
4933 txq->fifo.axq_depth);
4937 ATH_TXQ_REMOVE(&txq->fifo, bf, bf_list);
4944 if (txq->axq_fifo_depth != 0 || txq->fifo.axq_depth != 0) {
4946 "%s: Q%d: fifo_depth=%d, fifo.axq_depth=%d\n",
4950 txq->fifo.axq_depth);
5257 * wait long enough for the RX fifo to drain, reset the
H A Dif_athvar.h379 } fifo; member in struct:ath_txq
/haiku/headers/private/graphics/nvidia/
H A DDriverInterface.h193 * caused by the existance of DMA engine command buffers in cardRAM and/or fifo
197 * - we need at least 70kB distance from the end of RAM for fifo-reassigning 'bug'
207 * - we need at least ???kB distance from the end of RAM for fifo-reassigning 'bug'
208 * (fixme: unknown yet because fifo assignment switching isn't used here atm);
212 /* fifo re-assigning bug definition:
213 * if the fifo assignment is changed while at the same time card memory in the
342 } fifo; member in struct:__anon21::__anon23
/haiku/build/scripts/
H A Dbuild_haiku_image84 fifoBasePath=/tmp/build_haiku_image-$$-fifo
/haiku/src/add-ons/kernel/drivers/network/wlan/idualwifi7260/dev/pci/
H A Dif_iwm.c2398 iwm_enable_ac_txq(struct iwm_softc *sc, int qid, int fifo) argument
2431 (fifo << IWM_SCD_QUEUE_STTS_REG_POS_TXF) |
2443 iwm_enable_txq(struct iwm_softc *sc, int sta_id, int qid, int fifo, argument
2475 cmd.tx_fifo = fifo;
3567 int fifo; local
3586 fifo = iwm_ac_to_tx_fifo[ac];
3622 err = iwm_enable_txq(sc, IWM_STATION_ID, qid, fifo, 1, tid,

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