1/*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer, 12 * without modification. 13 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 14 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 15 * redistribution must be conditioned upon including a substantially 16 * similar Disclaimer requirement for further binary redistribution. 17 * 18 * NO WARRANTY 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 21 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 22 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 23 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 24 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 27 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 29 * THE POSSIBILITY OF SUCH DAMAGES. 30 * 31 * $FreeBSD: releng/12.0/sys/dev/ath/if_athvar.h 326255 2017-11-27 14:52:40Z pfg $ 32 */ 33 34/* 35 * Defintions for the Atheros Wireless LAN controller driver. 36 */ 37#ifndef _DEV_ATH_ATHVAR_H 38#define _DEV_ATH_ATHVAR_H 39 40#include <machine/atomic.h> 41 42#include <dev/ath/ath_hal/ah.h> 43#include <dev/ath/ath_hal/ah_desc.h> 44#include <net80211/ieee80211_radiotap.h> 45#include <dev/ath/if_athioctl.h> 46#include <dev/ath/if_athrate.h> 47#ifdef ATH_DEBUG_ALQ 48#include <dev/ath/if_ath_alq.h> 49#endif 50 51#define ATH_TIMEOUT 1000 52 53/* 54 * There is a separate TX ath_buf pool for management frames. 55 * This ensures that management frames such as probe responses 56 * and BAR frames can be transmitted during periods of high 57 * TX activity. 58 */ 59#define ATH_MGMT_TXBUF 32 60 61/* 62 * 802.11n requires more TX and RX buffers to do AMPDU. 63 */ 64#ifdef ATH_ENABLE_11N 65#define ATH_TXBUF 512 66#define ATH_RXBUF 512 67#endif 68 69#ifndef ATH_RXBUF 70#define ATH_RXBUF 40 /* number of RX buffers */ 71#endif 72#ifndef ATH_TXBUF 73#define ATH_TXBUF 200 /* number of TX buffers */ 74#endif 75#define ATH_BCBUF 4 /* number of beacon buffers */ 76 77#define ATH_TXDESC 10 /* number of descriptors per buffer */ 78#define ATH_TXMAXTRY 11 /* max number of transmit attempts */ 79#define ATH_TXMGTTRY 4 /* xmit attempts for mgt/ctl frames */ 80#define ATH_TXINTR_PERIOD 5 /* max number of batched tx descriptors */ 81 82#define ATH_BEACON_AIFS_DEFAULT 1 /* default aifs for ap beacon q */ 83#define ATH_BEACON_CWMIN_DEFAULT 0 /* default cwmin for ap beacon q */ 84#define ATH_BEACON_CWMAX_DEFAULT 0 /* default cwmax for ap beacon q */ 85 86/* 87 * The following bits can be set during the PCI (and perhaps non-PCI 88 * later) device probe path. 89 * 90 * It controls some of the driver and HAL behaviour. 91 */ 92 93#define ATH_PCI_CUS198 0x0001 94#define ATH_PCI_CUS230 0x0002 95#define ATH_PCI_CUS217 0x0004 96#define ATH_PCI_CUS252 0x0008 97#define ATH_PCI_WOW 0x0010 98#define ATH_PCI_BT_ANT_DIV 0x0020 99#define ATH_PCI_D3_L1_WAR 0x0040 100#define ATH_PCI_AR9565_1ANT 0x0080 101#define ATH_PCI_AR9565_2ANT 0x0100 102#define ATH_PCI_NO_PLL_PWRSAVE 0x0200 103#define ATH_PCI_KILLER 0x0400 104 105/* 106 * The key cache is used for h/w cipher state and also for 107 * tracking station state such as the current tx antenna. 108 * We also setup a mapping table between key cache slot indices 109 * and station state to short-circuit node lookups on rx. 110 * Different parts have different size key caches. We handle 111 * up to ATH_KEYMAX entries (could dynamically allocate state). 112 */ 113#define ATH_KEYMAX 128 /* max key cache size we handle */ 114#define ATH_KEYBYTES (ATH_KEYMAX/NBBY) /* storage space in bytes */ 115 116struct taskqueue; 117struct kthread; 118struct ath_buf; 119 120#define ATH_TID_MAX_BUFS (2 * IEEE80211_AGGR_BAWMAX) 121 122/* 123 * Per-TID state 124 * 125 * Note that TID 16 (WME_NUM_TID+1) is for handling non-QoS frames. 126 */ 127struct ath_tid { 128 TAILQ_HEAD(,ath_buf) tid_q; /* pending buffers */ 129 struct ath_node *an; /* pointer to parent */ 130 int tid; /* tid */ 131 int ac; /* which AC gets this traffic */ 132 int hwq_depth; /* how many buffers are on HW */ 133 u_int axq_depth; /* SW queue depth */ 134 135 struct { 136 TAILQ_HEAD(,ath_buf) tid_q; /* filtered queue */ 137 u_int axq_depth; /* SW queue depth */ 138 } filtq; 139 140 /* 141 * Entry on the ath_txq; when there's traffic 142 * to send 143 */ 144 TAILQ_ENTRY(ath_tid) axq_qelem; 145 int sched; 146 int paused; /* >0 if the TID has been paused */ 147 148 /* 149 * These are flags - perhaps later collapse 150 * down to a single uint32_t ? 151 */ 152 int addba_tx_pending; /* TX ADDBA pending */ 153 int bar_wait; /* waiting for BAR */ 154 int bar_tx; /* BAR TXed */ 155 int isfiltered; /* is this node currently filtered */ 156 157 /* 158 * Is the TID being cleaned up after a transition 159 * from aggregation to non-aggregation? 160 * When this is set to 1, this TID will be paused 161 * and no further traffic will be queued until all 162 * the hardware packets pending for this TID have been 163 * TXed/completed; at which point (non-aggregation) 164 * traffic will resume being TXed. 165 */ 166 int cleanup_inprogress; 167 /* 168 * How many hardware-queued packets are 169 * waiting to be cleaned up. 170 * This is only valid if cleanup_inprogress is 1. 171 */ 172 int incomp; 173 174 /* 175 * The following implements a ring representing 176 * the frames in the current BAW. 177 * To avoid copying the array content each time 178 * the BAW is moved, the baw_head/baw_tail point 179 * to the current BAW begin/end; when the BAW is 180 * shifted the head/tail of the array are also 181 * appropriately shifted. 182 */ 183 /* active tx buffers, beginning at current BAW */ 184 struct ath_buf *tx_buf[ATH_TID_MAX_BUFS]; 185 /* where the baw head is in the array */ 186 int baw_head; 187 /* where the BAW tail is in the array */ 188 int baw_tail; 189}; 190 191/* driver-specific node state */ 192struct ath_node { 193 struct ieee80211_node an_node; /* base class */ 194 u_int8_t an_mgmtrix; /* min h/w rate index */ 195 u_int8_t an_mcastrix; /* mcast h/w rate index */ 196 uint32_t an_is_powersave; /* node is sleeping */ 197 uint32_t an_stack_psq; /* net80211 psq isn't empty */ 198 uint32_t an_tim_set; /* TIM has been set */ 199 struct ath_buf *an_ff_buf[WME_NUM_AC]; /* ff staging area */ 200 struct ath_tid an_tid[IEEE80211_TID_SIZE]; /* per-TID state */ 201 char an_name[32]; /* eg "wlan0_a1" */ 202 struct mtx an_mtx; /* protecting the rate control state */ 203 uint32_t an_swq_depth; /* how many SWQ packets for this 204 node */ 205 int clrdmask; /* has clrdmask been set */ 206 uint32_t an_leak_count; /* How many frames to leak during pause */ 207 HAL_NODE_STATS an_node_stats; /* HAL node stats for this node */ 208 /* variable-length rate control state follows */ 209}; 210#define ATH_NODE(ni) ((struct ath_node *)(ni)) 211#define ATH_NODE_CONST(ni) ((const struct ath_node *)(ni)) 212 213#define ATH_RSSI_LPF_LEN 10 214#define ATH_RSSI_DUMMY_MARKER 0x127 215#define ATH_EP_MUL(x, mul) ((x) * (mul)) 216#define ATH_RSSI_IN(x) (ATH_EP_MUL((x), HAL_RSSI_EP_MULTIPLIER)) 217#define ATH_LPF_RSSI(x, y, len) \ 218 ((x != ATH_RSSI_DUMMY_MARKER) ? (((x) * ((len) - 1) + (y)) / (len)) : (y)) 219#define ATH_RSSI_LPF(x, y) do { \ 220 if ((y) >= -20) \ 221 x = ATH_LPF_RSSI((x), ATH_RSSI_IN((y)), ATH_RSSI_LPF_LEN); \ 222} while (0) 223#define ATH_EP_RND(x,mul) \ 224 ((((x)%(mul)) >= ((mul)/2)) ? ((x) + ((mul) - 1)) / (mul) : (x)/(mul)) 225#define ATH_RSSI(x) ATH_EP_RND(x, HAL_RSSI_EP_MULTIPLIER) 226 227typedef enum { 228 ATH_BUFTYPE_NORMAL = 0, 229 ATH_BUFTYPE_MGMT = 1, 230} ath_buf_type_t; 231 232struct ath_buf { 233 TAILQ_ENTRY(ath_buf) bf_list; 234 struct ath_buf * bf_next; /* next buffer in the aggregate */ 235 int bf_nseg; 236 HAL_STATUS bf_rxstatus; 237 uint16_t bf_flags; /* status flags (below) */ 238 uint16_t bf_descid; /* 16 bit descriptor ID */ 239 struct ath_desc *bf_desc; /* virtual addr of desc */ 240 struct ath_desc_status bf_status; /* tx/rx status */ 241 bus_addr_t bf_daddr; /* physical addr of desc */ 242 bus_dmamap_t bf_dmamap; /* DMA map for mbuf chain */ 243 struct mbuf *bf_m; /* mbuf for buf */ 244 struct ieee80211_node *bf_node; /* pointer to the node */ 245 struct ath_desc *bf_lastds; /* last descriptor for comp status */ 246 struct ath_buf *bf_last; /* last buffer in aggregate, or self for non-aggregate */ 247 bus_size_t bf_mapsize; 248#define ATH_MAX_SCATTER ATH_TXDESC /* max(tx,rx,beacon) desc's */ 249 bus_dma_segment_t bf_segs[ATH_MAX_SCATTER]; 250 uint32_t bf_nextfraglen; /* length of next fragment */ 251 252 /* Completion function to call on TX complete (fail or not) */ 253 /* 254 * "fail" here is set to 1 if the queue entries were removed 255 * through a call to ath_tx_draintxq(). 256 */ 257 void(* bf_comp) (struct ath_softc *sc, struct ath_buf *bf, int fail); 258 259 /* This state is kept to support software retries and aggregation */ 260 struct { 261 uint16_t bfs_seqno; /* sequence number of this packet */ 262 uint16_t bfs_ndelim; /* number of delims for padding */ 263 264 uint8_t bfs_retries; /* retry count */ 265 uint8_t bfs_tid; /* packet TID (or TID_MAX for no QoS) */ 266 uint8_t bfs_nframes; /* number of frames in aggregate */ 267 uint8_t bfs_pri; /* packet AC priority */ 268 uint8_t bfs_tx_queue; /* destination hardware TX queue */ 269 270 u_int32_t bfs_aggr:1, /* part of aggregate? */ 271 bfs_aggrburst:1, /* part of aggregate burst? */ 272 bfs_isretried:1, /* retried frame? */ 273 bfs_dobaw:1, /* actually check against BAW? */ 274 bfs_addedbaw:1, /* has been added to the BAW */ 275 bfs_shpream:1, /* use short preamble */ 276 bfs_istxfrag:1, /* is fragmented */ 277 bfs_ismrr:1, /* do multi-rate TX retry */ 278 bfs_doprot:1, /* do RTS/CTS based protection */ 279 bfs_doratelookup:1; /* do rate lookup before each TX */ 280 281 /* 282 * These fields are passed into the 283 * descriptor setup functions. 284 */ 285 286 /* Make this an 8 bit value? */ 287 HAL_PKT_TYPE bfs_atype; /* packet type */ 288 289 uint32_t bfs_pktlen; /* length of this packet */ 290 291 uint16_t bfs_hdrlen; /* length of this packet header */ 292 uint16_t bfs_al; /* length of aggregate */ 293 294 uint16_t bfs_txflags; /* HAL (tx) descriptor flags */ 295 uint8_t bfs_txrate0; /* first TX rate */ 296 uint8_t bfs_try0; /* first try count */ 297 298 uint16_t bfs_txpower; /* tx power */ 299 uint8_t bfs_ctsrate0; /* Non-zero - use this as ctsrate */ 300 uint8_t bfs_ctsrate; /* CTS rate */ 301 302 /* 16 bit? */ 303 int32_t bfs_keyix; /* crypto key index */ 304 int32_t bfs_txantenna; /* TX antenna config */ 305 306 /* Make this an 8 bit value? */ 307 enum ieee80211_protmode bfs_protmode; 308 309 /* 16 bit? */ 310 uint32_t bfs_ctsduration; /* CTS duration (pre-11n NICs) */ 311 int32_t bfs_rc_maxpktlen; /* max packet length/bucket from ratectrl or -1 */ 312 struct ath_rc_series bfs_rc[ATH_RC_NUM]; /* non-11n TX series */ 313 } bf_state; 314}; 315typedef TAILQ_HEAD(ath_bufhead_s, ath_buf) ath_bufhead; 316 317#define ATH_BUF_MGMT 0x00000001 /* (tx) desc is a mgmt desc */ 318#define ATH_BUF_BUSY 0x00000002 /* (tx) desc owned by h/w */ 319#define ATH_BUF_FIFOEND 0x00000004 320#define ATH_BUF_FIFOPTR 0x00000008 321#define ATH_BUF_TOA_PROBE 0x00000010 /* ToD/ToA exchange probe */ 322 323#define ATH_BUF_FLAGS_CLONE (ATH_BUF_MGMT | ATH_BUF_TOA_PROBE) 324 325/* 326 * DMA state for tx/rx descriptors. 327 */ 328struct ath_descdma { 329 const char* dd_name; 330 struct ath_desc *dd_desc; /* descriptors */ 331 int dd_descsize; /* size of single descriptor */ 332 bus_addr_t dd_desc_paddr; /* physical addr of dd_desc */ 333 bus_size_t dd_desc_len; /* size of dd_desc */ 334 bus_dma_segment_t dd_dseg; 335 bus_dma_tag_t dd_dmat; /* bus DMA tag */ 336 bus_dmamap_t dd_dmamap; /* DMA map for descriptors */ 337 struct ath_buf *dd_bufptr; /* associated buffers */ 338}; 339 340/* 341 * Data transmit queue state. One of these exists for each 342 * hardware transmit queue. Packets sent to us from above 343 * are assigned to queues based on their priority. Not all 344 * devices support a complete set of hardware transmit queues. 345 * For those devices the array sc_ac2q will map multiple 346 * priorities to fewer hardware queues (typically all to one 347 * hardware queue). 348 */ 349struct ath_txq { 350 struct ath_softc *axq_softc; /* Needed for scheduling */ 351 u_int axq_qnum; /* hardware q number */ 352#define ATH_TXQ_SWQ (HAL_NUM_TX_QUEUES+1) /* qnum for s/w only queue */ 353 u_int axq_ac; /* WME AC */ 354 u_int axq_flags; 355//#define ATH_TXQ_PUTPENDING 0x0001 /* ath_hal_puttxbuf pending */ 356#define ATH_TXQ_PUTRUNNING 0x0002 /* ath_hal_puttxbuf has been called */ 357 u_int axq_depth; /* queue depth (stat only) */ 358 u_int axq_aggr_depth; /* how many aggregates are queued */ 359 u_int axq_intrcnt; /* interrupt count */ 360 u_int32_t *axq_link; /* link ptr in last TX desc */ 361 TAILQ_HEAD(axq_q_s, ath_buf) axq_q; /* transmit queue */ 362 struct mtx axq_lock; /* lock on q and link */ 363 364 /* 365 * This is the FIFO staging buffer when doing EDMA. 366 * 367 * For legacy chips, we just push the head pointer to 368 * the hardware and we ignore this list. 369 * 370 * For EDMA, the staging buffer is treated as normal; 371 * when it's time to push a list of frames to the hardware 372 * we move that list here and we stamp buffers with 373 * flags to identify the beginning/end of that particular 374 * FIFO entry. 375 */ 376 struct { 377 TAILQ_HEAD(axq_q_f_s, ath_buf) axq_q; 378 u_int axq_depth; /* how many frames (1 per legacy, 1 per A-MPDU list) are in the FIFO queue */ 379 } fifo; 380 u_int axq_fifo_depth; /* how many FIFO slots are active */ 381 382 /* 383 * XXX the holdingbf field is protected by the TXBUF lock 384 * for now, NOT the TXQ lock. 385 * 386 * Architecturally, it would likely be better to move 387 * the holdingbf field to a separate array in ath_softc 388 * just to highlight that it's not protected by the normal 389 * TX path lock. 390 */ 391 struct ath_buf *axq_holdingbf; /* holding TX buffer */ 392 char axq_name[12]; /* e.g. "ath0_txq4" */ 393 394 /* Per-TID traffic queue for software -> hardware TX */ 395 /* 396 * This is protected by the general TX path lock, not (for now) 397 * by the TXQ lock. 398 */ 399 TAILQ_HEAD(axq_t_s,ath_tid) axq_tidq; 400}; 401 402#define ATH_TXQ_LOCK_INIT(_sc, _tq) do { \ 403 snprintf((_tq)->axq_name, sizeof((_tq)->axq_name), "%s_txq%u", \ 404 device_get_nameunit((_sc)->sc_dev), (_tq)->axq_qnum); \ 405 mtx_init(&(_tq)->axq_lock, (_tq)->axq_name, NULL, MTX_DEF); \ 406 } while (0) 407#define ATH_TXQ_LOCK_DESTROY(_tq) mtx_destroy(&(_tq)->axq_lock) 408#define ATH_TXQ_LOCK(_tq) mtx_lock(&(_tq)->axq_lock) 409#define ATH_TXQ_UNLOCK(_tq) mtx_unlock(&(_tq)->axq_lock) 410#define ATH_TXQ_LOCK_ASSERT(_tq) mtx_assert(&(_tq)->axq_lock, MA_OWNED) 411#define ATH_TXQ_UNLOCK_ASSERT(_tq) mtx_assert(&(_tq)->axq_lock, \ 412 MA_NOTOWNED) 413 414#define ATH_NODE_LOCK(_an) mtx_lock(&(_an)->an_mtx) 415#define ATH_NODE_UNLOCK(_an) mtx_unlock(&(_an)->an_mtx) 416#define ATH_NODE_LOCK_ASSERT(_an) mtx_assert(&(_an)->an_mtx, MA_OWNED) 417#define ATH_NODE_UNLOCK_ASSERT(_an) mtx_assert(&(_an)->an_mtx, \ 418 MA_NOTOWNED) 419 420/* 421 * These are for the hardware queue. 422 */ 423#define ATH_TXQ_INSERT_HEAD(_tq, _elm, _field) do { \ 424 TAILQ_INSERT_HEAD(&(_tq)->axq_q, (_elm), _field); \ 425 (_tq)->axq_depth++; \ 426} while (0) 427#define ATH_TXQ_INSERT_TAIL(_tq, _elm, _field) do { \ 428 TAILQ_INSERT_TAIL(&(_tq)->axq_q, (_elm), _field); \ 429 (_tq)->axq_depth++; \ 430} while (0) 431#define ATH_TXQ_REMOVE(_tq, _elm, _field) do { \ 432 TAILQ_REMOVE(&(_tq)->axq_q, _elm, _field); \ 433 (_tq)->axq_depth--; \ 434} while (0) 435#define ATH_TXQ_FIRST(_tq) TAILQ_FIRST(&(_tq)->axq_q) 436#define ATH_TXQ_LAST(_tq, _field) TAILQ_LAST(&(_tq)->axq_q, _field) 437 438/* 439 * These are for the TID software queue. 440 */ 441#define ATH_TID_INSERT_HEAD(_tq, _elm, _field) do { \ 442 TAILQ_INSERT_HEAD(&(_tq)->tid_q, (_elm), _field); \ 443 (_tq)->axq_depth++; \ 444 (_tq)->an->an_swq_depth++; \ 445} while (0) 446#define ATH_TID_INSERT_TAIL(_tq, _elm, _field) do { \ 447 TAILQ_INSERT_TAIL(&(_tq)->tid_q, (_elm), _field); \ 448 (_tq)->axq_depth++; \ 449 (_tq)->an->an_swq_depth++; \ 450} while (0) 451#define ATH_TID_REMOVE(_tq, _elm, _field) do { \ 452 TAILQ_REMOVE(&(_tq)->tid_q, _elm, _field); \ 453 (_tq)->axq_depth--; \ 454 (_tq)->an->an_swq_depth--; \ 455} while (0) 456#define ATH_TID_FIRST(_tq) TAILQ_FIRST(&(_tq)->tid_q) 457#define ATH_TID_LAST(_tq, _field) TAILQ_LAST(&(_tq)->tid_q, _field) 458 459/* 460 * These are for the TID filtered frame queue 461 */ 462#define ATH_TID_FILT_INSERT_HEAD(_tq, _elm, _field) do { \ 463 TAILQ_INSERT_HEAD(&(_tq)->filtq.tid_q, (_elm), _field); \ 464 (_tq)->axq_depth++; \ 465 (_tq)->an->an_swq_depth++; \ 466} while (0) 467#define ATH_TID_FILT_INSERT_TAIL(_tq, _elm, _field) do { \ 468 TAILQ_INSERT_TAIL(&(_tq)->filtq.tid_q, (_elm), _field); \ 469 (_tq)->axq_depth++; \ 470 (_tq)->an->an_swq_depth++; \ 471} while (0) 472#define ATH_TID_FILT_REMOVE(_tq, _elm, _field) do { \ 473 TAILQ_REMOVE(&(_tq)->filtq.tid_q, _elm, _field); \ 474 (_tq)->axq_depth--; \ 475 (_tq)->an->an_swq_depth--; \ 476} while (0) 477#define ATH_TID_FILT_FIRST(_tq) TAILQ_FIRST(&(_tq)->filtq.tid_q) 478#define ATH_TID_FILT_LAST(_tq, _field) TAILQ_LAST(&(_tq)->filtq.tid_q,_field) 479 480struct ath_vap { 481 struct ieee80211vap av_vap; /* base class */ 482 int av_bslot; /* beacon slot index */ 483 struct ath_buf *av_bcbuf; /* beacon buffer */ 484 struct ath_txq av_mcastq; /* buffered mcast s/w queue */ 485 486 void (*av_recv_mgmt)(struct ieee80211_node *, 487 struct mbuf *, int, 488 const struct ieee80211_rx_stats *, int, int); 489 int (*av_newstate)(struct ieee80211vap *, 490 enum ieee80211_state, int); 491 void (*av_bmiss)(struct ieee80211vap *); 492 void (*av_node_ps)(struct ieee80211_node *, int); 493 int (*av_set_tim)(struct ieee80211_node *, int); 494 void (*av_recv_pspoll)(struct ieee80211_node *, 495 struct mbuf *); 496 struct ieee80211_quiet_ie quiet_ie; 497}; 498#define ATH_VAP(vap) ((struct ath_vap *)(vap)) 499 500struct taskqueue; 501struct ath_tx99; 502 503/* 504 * Whether to reset the TX/RX queue with or without 505 * a queue flush. 506 */ 507typedef enum { 508 ATH_RESET_DEFAULT = 0, 509 ATH_RESET_NOLOSS = 1, 510 ATH_RESET_FULL = 2, 511} ATH_RESET_TYPE; 512 513struct ath_rx_methods { 514 void (*recv_sched_queue)(struct ath_softc *sc, 515 HAL_RX_QUEUE q, int dosched); 516 void (*recv_sched)(struct ath_softc *sc, int dosched); 517 void (*recv_stop)(struct ath_softc *sc, int dodelay); 518 int (*recv_start)(struct ath_softc *sc); 519 void (*recv_flush)(struct ath_softc *sc); 520 void (*recv_tasklet)(void *arg, int npending); 521 int (*recv_rxbuf_init)(struct ath_softc *sc, 522 struct ath_buf *bf); 523 int (*recv_setup)(struct ath_softc *sc); 524 int (*recv_teardown)(struct ath_softc *sc); 525}; 526 527/* 528 * Represent the current state of the RX FIFO. 529 */ 530struct ath_rx_edma { 531 struct ath_buf **m_fifo; 532 int m_fifolen; 533 int m_fifo_head; 534 int m_fifo_tail; 535 int m_fifo_depth; 536 struct mbuf *m_rxpending; 537 struct ath_buf *m_holdbf; 538}; 539 540struct ath_tx_edma_fifo { 541 struct ath_buf **m_fifo; 542 int m_fifolen; 543 int m_fifo_head; 544 int m_fifo_tail; 545 int m_fifo_depth; 546}; 547 548struct ath_tx_methods { 549 int (*xmit_setup)(struct ath_softc *sc); 550 int (*xmit_teardown)(struct ath_softc *sc); 551 void (*xmit_attach_comp_func)(struct ath_softc *sc); 552 553 void (*xmit_dma_restart)(struct ath_softc *sc, 554 struct ath_txq *txq); 555 void (*xmit_handoff)(struct ath_softc *sc, 556 struct ath_txq *txq, struct ath_buf *bf); 557 void (*xmit_drain)(struct ath_softc *sc, 558 ATH_RESET_TYPE reset_type); 559}; 560 561struct ath_softc { 562 struct ieee80211com sc_ic; 563 struct ath_stats sc_stats; /* device statistics */ 564 struct ath_tx_aggr_stats sc_aggr_stats; 565 struct ath_intr_stats sc_intr_stats; 566 uint64_t sc_debug; 567 uint64_t sc_ktrdebug; 568 int sc_nvaps; /* # vaps */ 569 int sc_nstavaps; /* # station vaps */ 570 int sc_nmeshvaps; /* # mbss vaps */ 571 u_int8_t sc_hwbssidmask[IEEE80211_ADDR_LEN]; 572 u_int8_t sc_nbssid0; /* # vap's using base mac */ 573 uint32_t sc_bssidmask; /* bssid mask */ 574 575 struct ath_rx_methods sc_rx; 576 struct ath_rx_edma sc_rxedma[HAL_NUM_RX_QUEUES]; /* HP/LP queues */ 577 ath_bufhead sc_rx_rxlist[HAL_NUM_RX_QUEUES]; /* deferred RX completion */ 578 struct ath_tx_methods sc_tx; 579 struct ath_tx_edma_fifo sc_txedma[HAL_NUM_TX_QUEUES]; 580 581 /* 582 * This is (currently) protected by the TX queue lock; 583 * it should migrate to a separate lock later 584 * so as to minimise contention. 585 */ 586 ath_bufhead sc_txbuf_list; 587 588 int sc_rx_statuslen; 589 int sc_tx_desclen; 590 int sc_tx_statuslen; 591 int sc_tx_nmaps; /* Number of TX maps */ 592 int sc_edma_bufsize; 593 int sc_rx_stopped; /* XXX only for EDMA */ 594 int sc_rx_resetted; /* XXX only for EDMA */ 595 596 void (*sc_node_cleanup)(struct ieee80211_node *); 597 void (*sc_node_free)(struct ieee80211_node *); 598 device_t sc_dev; 599 HAL_BUS_TAG sc_st; /* bus space tag */ 600 HAL_BUS_HANDLE sc_sh; /* bus space handle */ 601 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 602 struct mtx sc_mtx; /* master lock (recursive) */ 603 struct mtx sc_pcu_mtx; /* PCU access mutex */ 604 char sc_pcu_mtx_name[32]; 605 struct mtx sc_rx_mtx; /* RX access mutex */ 606 char sc_rx_mtx_name[32]; 607 struct mtx sc_tx_mtx; /* TX handling/comp mutex */ 608 char sc_tx_mtx_name[32]; 609 struct mtx sc_tx_ic_mtx; /* TX queue mutex */ 610 char sc_tx_ic_mtx_name[32]; 611 struct taskqueue *sc_tq; /* private task queue */ 612 struct ath_hal *sc_ah; /* Atheros HAL */ 613 struct ath_ratectrl *sc_rc; /* tx rate control support */ 614 struct ath_tx99 *sc_tx99; /* tx99 adjunct state */ 615 void (*sc_setdefantenna)(struct ath_softc *, u_int); 616 617 /* 618 * First set of flags. 619 */ 620 uint32_t sc_invalid : 1,/* disable hardware accesses */ 621 sc_mrretry : 1,/* multi-rate retry support */ 622 sc_mrrprot : 1,/* MRR + protection support */ 623 sc_softled : 1,/* enable LED gpio status */ 624 sc_hardled : 1,/* enable MAC LED status */ 625 sc_splitmic : 1,/* split TKIP MIC keys */ 626 sc_needmib : 1,/* enable MIB stats intr */ 627 sc_diversity: 1,/* enable rx diversity */ 628 sc_hasveol : 1,/* tx VEOL support */ 629 sc_ledstate : 1,/* LED on/off state */ 630 sc_blinking : 1,/* LED blink operation active */ 631 sc_mcastkey : 1,/* mcast key cache search */ 632 sc_scanning : 1,/* scanning active */ 633 sc_syncbeacon:1,/* sync/resync beacon timers */ 634 sc_hasclrkey: 1,/* CLR key supported */ 635 sc_xchanmode: 1,/* extended channel mode */ 636 sc_outdoor : 1,/* outdoor operation */ 637 sc_dturbo : 1,/* dynamic turbo in use */ 638 sc_hasbmask : 1,/* bssid mask support */ 639 sc_hasbmatch: 1,/* bssid match disable support*/ 640 sc_hastsfadd: 1,/* tsf adjust support */ 641 sc_beacons : 1,/* beacons running */ 642 sc_swbmiss : 1,/* sta mode using sw bmiss */ 643 sc_stagbeacons:1,/* use staggered beacons */ 644 sc_wmetkipmic:1,/* can do WME+TKIP MIC */ 645 sc_resume_up: 1,/* on resume, start all vaps */ 646 sc_tdma : 1,/* TDMA in use */ 647 sc_setcca : 1,/* set/clr CCA with TDMA */ 648 sc_resetcal : 1,/* reset cal state next trip */ 649 sc_rxslink : 1,/* do self-linked final descriptor */ 650 sc_rxtsf32 : 1,/* RX dec TSF is 32 bits */ 651 sc_isedma : 1,/* supports EDMA */ 652 sc_do_mybeacon : 1; /* supports mybeacon */ 653 654 /* 655 * Second set of flags. 656 */ 657 u_int32_t sc_running : 1, /* initialized */ 658 sc_use_ent : 1, 659 sc_rx_stbc : 1, 660 sc_tx_stbc : 1, 661 sc_has_ldpc : 1, 662 sc_hasenforcetxop : 1, /* support enforce TxOP */ 663 sc_hasdivcomb : 1, /* RX diversity combining */ 664 sc_rx_lnamixer : 1, /* RX using LNA mixing */ 665 sc_btcoex_mci : 1; /* MCI bluetooth coex */ 666 667 int sc_cabq_enable; /* Enable cabq transmission */ 668 669 /* 670 * Enterprise mode configuration for AR9380 and later chipsets. 671 */ 672 uint32_t sc_ent_cfg; 673 674 uint32_t sc_eerd; /* regdomain from EEPROM */ 675 uint32_t sc_eecc; /* country code from EEPROM */ 676 /* rate tables */ 677 const HAL_RATE_TABLE *sc_rates[IEEE80211_MODE_MAX]; 678 const HAL_RATE_TABLE *sc_currates; /* current rate table */ 679 enum ieee80211_phymode sc_curmode; /* current phy mode */ 680 HAL_OPMODE sc_opmode; /* current operating mode */ 681 u_int16_t sc_curtxpow; /* current tx power limit */ 682 u_int16_t sc_curaid; /* current association id */ 683 struct ieee80211_channel *sc_curchan; /* current installed channel */ 684 u_int8_t sc_curbssid[IEEE80211_ADDR_LEN]; 685 u_int8_t sc_rixmap[256]; /* IEEE to h/w rate table ix */ 686 struct { 687 u_int8_t ieeerate; /* IEEE rate */ 688 u_int8_t rxflags; /* radiotap rx flags */ 689 u_int8_t txflags; /* radiotap tx flags */ 690 u_int16_t ledon; /* softled on time */ 691 u_int16_t ledoff; /* softled off time */ 692 } sc_hwmap[32]; /* h/w rate ix mappings */ 693 u_int8_t sc_protrix; /* protection rate index */ 694 u_int8_t sc_lastdatarix; /* last data frame rate index */ 695 u_int sc_mcastrate; /* ieee rate for mcastrateix */ 696 u_int sc_fftxqmin; /* min frames before staging */ 697 u_int sc_fftxqmax; /* max frames before drop */ 698 u_int sc_txantenna; /* tx antenna (fixed or auto) */ 699 700 HAL_INT sc_imask; /* interrupt mask copy */ 701 702 /* 703 * These are modified in the interrupt handler as well as 704 * the task queues and other contexts. Thus these must be 705 * protected by a mutex, or they could clash. 706 * 707 * For now, access to these is behind the ATH_LOCK, 708 * just to save time. 709 */ 710 uint32_t sc_txq_active; /* bitmap of active TXQs */ 711 uint32_t sc_kickpcu; /* whether to kick the PCU */ 712 uint32_t sc_rxproc_cnt; /* In RX processing */ 713 uint32_t sc_txproc_cnt; /* In TX processing */ 714 uint32_t sc_txstart_cnt; /* In TX output (raw/start) */ 715 uint32_t sc_inreset_cnt; /* In active reset/chanchange */ 716 uint32_t sc_txrx_cnt; /* refcount on stop/start'ing TX */ 717 uint32_t sc_intr_cnt; /* refcount on interrupt handling */ 718 719 u_int sc_keymax; /* size of key cache */ 720 u_int8_t sc_keymap[ATH_KEYBYTES];/* key use bit map */ 721 722 /* 723 * Software based LED blinking 724 */ 725 u_int sc_ledpin; /* GPIO pin for driving LED */ 726 u_int sc_ledon; /* pin setting for LED on */ 727 u_int sc_ledidle; /* idle polling interval */ 728 int sc_ledevent; /* time of last LED event */ 729 u_int8_t sc_txrix; /* current tx rate for LED */ 730 u_int16_t sc_ledoff; /* off time for current blink */ 731 struct callout sc_ledtimer; /* led off timer */ 732 733 /* 734 * Hardware based LED blinking 735 */ 736 int sc_led_pwr_pin; /* MAC power LED GPIO pin */ 737 int sc_led_net_pin; /* MAC network LED GPIO pin */ 738 739 u_int sc_rfsilentpin; /* GPIO pin for rfkill int */ 740 u_int sc_rfsilentpol; /* pin setting for rfkill on */ 741 742 struct ath_descdma sc_rxdma; /* RX descriptors */ 743 ath_bufhead sc_rxbuf; /* receive buffer */ 744 u_int32_t *sc_rxlink; /* link ptr in last RX desc */ 745 struct task sc_rxtask; /* rx int processing */ 746 u_int8_t sc_defant; /* current default antenna */ 747 u_int8_t sc_rxotherant; /* rx's on non-default antenna*/ 748 u_int64_t sc_lastrx; /* tsf at last rx'd frame */ 749 struct ath_rx_status *sc_lastrs; /* h/w status of last rx */ 750 struct ath_rx_radiotap_header sc_rx_th; 751 int sc_rx_th_len; 752 u_int sc_monpass; /* frames to pass in mon.mode */ 753 754 struct ath_descdma sc_txdma; /* TX descriptors */ 755 uint16_t sc_txbuf_descid; 756 ath_bufhead sc_txbuf; /* transmit buffer */ 757 int sc_txbuf_cnt; /* how many buffers avail */ 758 struct ath_descdma sc_txdma_mgmt; /* mgmt TX descriptors */ 759 ath_bufhead sc_txbuf_mgmt; /* mgmt transmit buffer */ 760 struct ath_descdma sc_txsdma; /* EDMA TX status desc's */ 761 struct mtx sc_txbuflock; /* txbuf lock */ 762 char sc_txname[12]; /* e.g. "ath0_buf" */ 763 u_int sc_txqsetup; /* h/w queues setup */ 764 u_int sc_txintrperiod;/* tx interrupt batching */ 765 struct ath_txq sc_txq[HAL_NUM_TX_QUEUES]; 766 struct ath_txq *sc_ac2q[5]; /* WME AC -> h/w q map */ 767 struct task sc_txtask; /* tx int processing */ 768 struct task sc_txqtask; /* tx proc processing */ 769 770 struct ath_descdma sc_txcompdma; /* TX EDMA completion */ 771 struct mtx sc_txcomplock; /* TX EDMA completion lock */ 772 char sc_txcompname[12]; /* eg ath0_txcomp */ 773 774 int sc_wd_timer; /* count down for wd timer */ 775 struct callout sc_wd_ch; /* tx watchdog timer */ 776 struct ath_tx_radiotap_header sc_tx_th; 777 int sc_tx_th_len; 778 779 struct ath_descdma sc_bdma; /* beacon descriptors */ 780 ath_bufhead sc_bbuf; /* beacon buffers */ 781 u_int sc_bhalq; /* HAL q for outgoing beacons */ 782 u_int sc_bmisscount; /* missed beacon transmits */ 783 u_int32_t sc_ant_tx[ATH_IOCTL_STATS_NUM_TX_ANTENNA]; 784 /* recent tx frames/antenna */ 785 struct ath_txq *sc_cabq; /* tx q for cab frames */ 786 struct task sc_bmisstask; /* bmiss int processing */ 787 struct task sc_bstucktask; /* stuck beacon processing */ 788 struct task sc_resettask; /* interface reset task */ 789 struct task sc_fataltask; /* fatal task */ 790 enum { 791 OK, /* no change needed */ 792 UPDATE, /* update pending */ 793 COMMIT /* beacon sent, commit change */ 794 } sc_updateslot; /* slot time update fsm */ 795 int sc_slotupdate; /* slot to advance fsm */ 796 struct ieee80211vap *sc_bslot[ATH_BCBUF]; 797 int sc_nbcnvaps; /* # vaps with beacons */ 798 799 struct callout sc_cal_ch; /* callout handle for cals */ 800 int sc_lastlongcal; /* last long cal completed */ 801 int sc_lastcalreset;/* last cal reset done */ 802 int sc_lastani; /* last ANI poll */ 803 int sc_lastshortcal; /* last short calibration */ 804 HAL_BOOL sc_doresetcal; /* Yes, we're doing a reset cal atm */ 805 HAL_NODE_STATS sc_halstats; /* station-mode rssi stats */ 806 u_int sc_tdmadbaprep; /* TDMA DBA prep time */ 807 u_int sc_tdmaswbaprep;/* TDMA SWBA prep time */ 808 u_int sc_tdmaswba; /* TDMA SWBA counter */ 809 u_int32_t sc_tdmabintval; /* TDMA beacon interval (TU) */ 810 u_int32_t sc_tdmaguard; /* TDMA guard time (usec) */ 811 u_int sc_tdmaslotlen; /* TDMA slot length (usec) */ 812 u_int32_t sc_avgtsfdeltap;/* TDMA slot adjust (+) */ 813 u_int32_t sc_avgtsfdeltam;/* TDMA slot adjust (-) */ 814 uint16_t *sc_eepromdata; /* Local eeprom data, if AR9100 */ 815 uint32_t sc_txchainmask; /* hardware TX chainmask */ 816 uint32_t sc_rxchainmask; /* hardware RX chainmask */ 817 uint32_t sc_cur_txchainmask; /* currently configured TX chainmask */ 818 uint32_t sc_cur_rxchainmask; /* currently configured RX chainmask */ 819 uint32_t sc_rts_aggr_limit; /* TX limit on RTS aggregates */ 820 int sc_aggr_limit; /* TX limit on all aggregates */ 821 int sc_delim_min_pad; /* Minimum delimiter count */ 822 823 /* Queue limits */ 824 825 /* 826 * To avoid queue starvation in congested conditions, 827 * these parameters tune the maximum number of frames 828 * queued to the data/mcastq before they're dropped. 829 * 830 * This is to prevent: 831 * + a single destination overwhelming everything, including 832 * management/multicast frames; 833 * + multicast frames overwhelming everything (when the 834 * air is sufficiently busy that cabq can't drain.) 835 * + A node in powersave shouldn't be allowed to exhaust 836 * all available mbufs; 837 * 838 * These implement: 839 * + data_minfree is the maximum number of free buffers 840 * overall to successfully allow a data frame. 841 * 842 * + mcastq_maxdepth is the maximum depth allowed of the cabq. 843 */ 844 int sc_txq_node_maxdepth; 845 int sc_txq_data_minfree; 846 int sc_txq_mcastq_maxdepth; 847 int sc_txq_node_psq_maxdepth; 848 849 /* 850 * Software queue twiddles 851 * 852 * hwq_limit_nonaggr: 853 * when to begin limiting non-aggregate frames to the 854 * hardware queue, regardless of the TID. 855 * hwq_limit_aggr: 856 * when to begin limiting A-MPDU frames to the 857 * hardware queue, regardless of the TID. 858 * tid_hwq_lo: how low the per-TID hwq count has to be before the 859 * TID will be scheduled again 860 * tid_hwq_hi: how many frames to queue to the HWQ before the TID 861 * stops being scheduled. 862 */ 863 int sc_hwq_limit_nonaggr; 864 int sc_hwq_limit_aggr; 865 int sc_tid_hwq_lo; 866 int sc_tid_hwq_hi; 867 868 /* DFS related state */ 869 void *sc_dfs; /* Used by an optional DFS module */ 870 int sc_dodfs; /* Whether to enable DFS rx filter bits */ 871 struct task sc_dfstask; /* DFS processing task */ 872 873 /* Spectral related state */ 874 void *sc_spectral; 875 int sc_dospectral; 876 877 /* LNA diversity related state */ 878 void *sc_lna_div; 879 int sc_dolnadiv; 880 881#if defined(__HAIKU__) 882 HAL_INT sc_intr_status; 883#endif 884 885 /* ALQ */ 886#ifdef ATH_DEBUG_ALQ 887 struct if_ath_alq sc_alq; 888#endif 889 890 /* TX AMPDU handling */ 891 int (*sc_addba_request)(struct ieee80211_node *, 892 struct ieee80211_tx_ampdu *, int, int, int); 893 int (*sc_addba_response)(struct ieee80211_node *, 894 struct ieee80211_tx_ampdu *, int, int, int); 895 void (*sc_addba_stop)(struct ieee80211_node *, 896 struct ieee80211_tx_ampdu *); 897 void (*sc_addba_response_timeout) 898 (struct ieee80211_node *, 899 struct ieee80211_tx_ampdu *); 900 void (*sc_bar_response)(struct ieee80211_node *ni, 901 struct ieee80211_tx_ampdu *tap, 902 int status); 903 904 /* 905 * Powersave state tracking. 906 * 907 * target/cur powerstate is the chip power state. 908 * target selfgen state is the self-generated frames 909 * state. The chip can be awake but transmitted frames 910 * can have the PWRMGT bit set to 1 so the destination 911 * thinks the node is asleep. 912 */ 913 HAL_POWER_MODE sc_target_powerstate; 914 HAL_POWER_MODE sc_target_selfgen_state; 915 916 HAL_POWER_MODE sc_cur_powerstate; 917 918 int sc_powersave_refcnt; 919 920 /* ATH_PCI_* flags */ 921 uint32_t sc_pci_devinfo; 922 923 /* BT coex */ 924 struct { 925 struct ath_descdma buf; 926 927 /* gpm/sched buffer, saved pointers */ 928 char *sched_buf; 929 bus_addr_t sched_paddr; 930 char *gpm_buf; 931 bus_addr_t gpm_paddr; 932 933 uint32_t wlan_channels[4]; 934 } sc_btcoex; 935}; 936 937#define ATH_LOCK_INIT(_sc) \ 938 mtx_init(&(_sc)->sc_mtx, device_get_nameunit((_sc)->sc_dev), \ 939 NULL, MTX_DEF | MTX_RECURSE) 940#define ATH_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_mtx) 941#define ATH_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) 942#define ATH_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) 943#define ATH_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED) 944#define ATH_UNLOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_NOTOWNED) 945 946/* 947 * The TX lock is non-reentrant and serialises the TX frame send 948 * and completion operations. 949 */ 950#define ATH_TX_LOCK_INIT(_sc) do {\ 951 snprintf((_sc)->sc_tx_mtx_name, \ 952 sizeof((_sc)->sc_tx_mtx_name), \ 953 "%s TX lock", \ 954 device_get_nameunit((_sc)->sc_dev)); \ 955 mtx_init(&(_sc)->sc_tx_mtx, (_sc)->sc_tx_mtx_name, \ 956 NULL, MTX_DEF); \ 957 } while (0) 958#define ATH_TX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_tx_mtx) 959#define ATH_TX_LOCK(_sc) mtx_lock(&(_sc)->sc_tx_mtx) 960#define ATH_TX_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_tx_mtx) 961#define ATH_TX_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_tx_mtx, \ 962 MA_OWNED) 963#define ATH_TX_UNLOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_tx_mtx, \ 964 MA_NOTOWNED) 965#define ATH_TX_TRYLOCK(_sc) (mtx_owned(&(_sc)->sc_tx_mtx) != 0 && \ 966 mtx_trylock(&(_sc)->sc_tx_mtx)) 967 968/* 969 * The PCU lock is non-recursive and should be treated as a spinlock. 970 * Although currently the interrupt code is run in netisr context and 971 * doesn't require this, this may change in the future. 972 * Please keep this in mind when protecting certain code paths 973 * with the PCU lock. 974 * 975 * The PCU lock is used to serialise access to the PCU so things such 976 * as TX, RX, state change (eg channel change), channel reset and updates 977 * from interrupt context (eg kickpcu, txqactive bits) do not clash. 978 * 979 * Although the current single-thread taskqueue mechanism protects the 980 * majority of these situations by simply serialising them, there are 981 * a few others which occur at the same time. These include the TX path 982 * (which only acquires ATH_LOCK when recycling buffers to the free list), 983 * ath_set_channel, the channel scanning API and perhaps quite a bit more. 984 */ 985#define ATH_PCU_LOCK_INIT(_sc) do {\ 986 snprintf((_sc)->sc_pcu_mtx_name, \ 987 sizeof((_sc)->sc_pcu_mtx_name), \ 988 "%s PCU lock", \ 989 device_get_nameunit((_sc)->sc_dev)); \ 990 mtx_init(&(_sc)->sc_pcu_mtx, (_sc)->sc_pcu_mtx_name, \ 991 NULL, MTX_DEF); \ 992 } while (0) 993#define ATH_PCU_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_pcu_mtx) 994#define ATH_PCU_LOCK(_sc) mtx_lock(&(_sc)->sc_pcu_mtx) 995#define ATH_PCU_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_pcu_mtx) 996#define ATH_PCU_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_pcu_mtx, \ 997 MA_OWNED) 998#define ATH_PCU_UNLOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_pcu_mtx, \ 999 MA_NOTOWNED) 1000 1001/* 1002 * The RX lock is primarily a(nother) workaround to ensure that the 1003 * RX FIFO/list isn't modified by various execution paths. 1004 * Even though RX occurs in a single context (the ath taskqueue), the 1005 * RX path can be executed via various reset/channel change paths. 1006 */ 1007#define ATH_RX_LOCK_INIT(_sc) do {\ 1008 snprintf((_sc)->sc_rx_mtx_name, \ 1009 sizeof((_sc)->sc_rx_mtx_name), \ 1010 "%s RX lock", \ 1011 device_get_nameunit((_sc)->sc_dev)); \ 1012 mtx_init(&(_sc)->sc_rx_mtx, (_sc)->sc_rx_mtx_name, \ 1013 NULL, MTX_DEF); \ 1014 } while (0) 1015#define ATH_RX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_rx_mtx) 1016#define ATH_RX_LOCK(_sc) mtx_lock(&(_sc)->sc_rx_mtx) 1017#define ATH_RX_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_rx_mtx) 1018#define ATH_RX_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_rx_mtx, \ 1019 MA_OWNED) 1020#define ATH_RX_UNLOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_rx_mtx, \ 1021 MA_NOTOWNED) 1022 1023#define ATH_TXQ_SETUP(sc, i) ((sc)->sc_txqsetup & (1<<i)) 1024 1025#define ATH_TXBUF_LOCK_INIT(_sc) do { \ 1026 snprintf((_sc)->sc_txname, sizeof((_sc)->sc_txname), "%s_buf", \ 1027 device_get_nameunit((_sc)->sc_dev)); \ 1028 mtx_init(&(_sc)->sc_txbuflock, (_sc)->sc_txname, NULL, MTX_DEF); \ 1029} while (0) 1030#define ATH_TXBUF_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_txbuflock) 1031#define ATH_TXBUF_LOCK(_sc) mtx_lock(&(_sc)->sc_txbuflock) 1032#define ATH_TXBUF_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_txbuflock) 1033#define ATH_TXBUF_LOCK_ASSERT(_sc) \ 1034 mtx_assert(&(_sc)->sc_txbuflock, MA_OWNED) 1035#define ATH_TXBUF_UNLOCK_ASSERT(_sc) \ 1036 mtx_assert(&(_sc)->sc_txbuflock, MA_NOTOWNED) 1037 1038#define ATH_TXSTATUS_LOCK_INIT(_sc) do { \ 1039 snprintf((_sc)->sc_txcompname, sizeof((_sc)->sc_txcompname), \ 1040 "%s_buf", \ 1041 device_get_nameunit((_sc)->sc_dev)); \ 1042 mtx_init(&(_sc)->sc_txcomplock, (_sc)->sc_txcompname, NULL, \ 1043 MTX_DEF); \ 1044} while (0) 1045#define ATH_TXSTATUS_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_txcomplock) 1046#define ATH_TXSTATUS_LOCK(_sc) mtx_lock(&(_sc)->sc_txcomplock) 1047#define ATH_TXSTATUS_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_txcomplock) 1048#define ATH_TXSTATUS_LOCK_ASSERT(_sc) \ 1049 mtx_assert(&(_sc)->sc_txcomplock, MA_OWNED) 1050 1051int ath_attach(u_int16_t, struct ath_softc *); 1052int ath_detach(struct ath_softc *); 1053void ath_resume(struct ath_softc *); 1054void ath_suspend(struct ath_softc *); 1055void ath_shutdown(struct ath_softc *); 1056void ath_intr(void *); 1057 1058/* 1059 * HAL definitions to comply with local coding convention. 1060 */ 1061#define ath_hal_detach(_ah) \ 1062 ((*(_ah)->ah_detach)((_ah))) 1063#define ath_hal_reset(_ah, _opmode, _chan, _fullreset, _resettype, _pstatus) \ 1064 ((*(_ah)->ah_reset)((_ah), (_opmode), (_chan), (_fullreset), \ 1065 (_resettype), (_pstatus))) 1066#define ath_hal_macversion(_ah) \ 1067 (((_ah)->ah_macVersion << 4) | ((_ah)->ah_macRev)) 1068#define ath_hal_getratetable(_ah, _mode) \ 1069 ((*(_ah)->ah_getRateTable)((_ah), (_mode))) 1070#define ath_hal_getmac(_ah, _mac) \ 1071 ((*(_ah)->ah_getMacAddress)((_ah), (_mac))) 1072#define ath_hal_setmac(_ah, _mac) \ 1073 ((*(_ah)->ah_setMacAddress)((_ah), (_mac))) 1074#define ath_hal_getbssidmask(_ah, _mask) \ 1075 ((*(_ah)->ah_getBssIdMask)((_ah), (_mask))) 1076#define ath_hal_setbssidmask(_ah, _mask) \ 1077 ((*(_ah)->ah_setBssIdMask)((_ah), (_mask))) 1078#define ath_hal_intrset(_ah, _mask) \ 1079 ((*(_ah)->ah_setInterrupts)((_ah), (_mask))) 1080#define ath_hal_intrget(_ah) \ 1081 ((*(_ah)->ah_getInterrupts)((_ah))) 1082#define ath_hal_intrpend(_ah) \ 1083 ((*(_ah)->ah_isInterruptPending)((_ah))) 1084#define ath_hal_getisr(_ah, _pmask) \ 1085 ((*(_ah)->ah_getPendingInterrupts)((_ah), (_pmask))) 1086#define ath_hal_updatetxtriglevel(_ah, _inc) \ 1087 ((*(_ah)->ah_updateTxTrigLevel)((_ah), (_inc))) 1088#define ath_hal_setpower(_ah, _mode) \ 1089 ((*(_ah)->ah_setPowerMode)((_ah), (_mode), AH_TRUE)) 1090#define ath_hal_setselfgenpower(_ah, _mode) \ 1091 ((*(_ah)->ah_setPowerMode)((_ah), (_mode), AH_FALSE)) 1092#define ath_hal_keycachesize(_ah) \ 1093 ((*(_ah)->ah_getKeyCacheSize)((_ah))) 1094#define ath_hal_keyreset(_ah, _ix) \ 1095 ((*(_ah)->ah_resetKeyCacheEntry)((_ah), (_ix))) 1096#define ath_hal_keyset(_ah, _ix, _pk, _mac) \ 1097 ((*(_ah)->ah_setKeyCacheEntry)((_ah), (_ix), (_pk), (_mac), AH_FALSE)) 1098#define ath_hal_keyisvalid(_ah, _ix) \ 1099 (((*(_ah)->ah_isKeyCacheEntryValid)((_ah), (_ix)))) 1100#define ath_hal_keysetmac(_ah, _ix, _mac) \ 1101 ((*(_ah)->ah_setKeyCacheEntryMac)((_ah), (_ix), (_mac))) 1102#define ath_hal_getrxfilter(_ah) \ 1103 ((*(_ah)->ah_getRxFilter)((_ah))) 1104#define ath_hal_setrxfilter(_ah, _filter) \ 1105 ((*(_ah)->ah_setRxFilter)((_ah), (_filter))) 1106#define ath_hal_setmcastfilter(_ah, _mfilt0, _mfilt1) \ 1107 ((*(_ah)->ah_setMulticastFilter)((_ah), (_mfilt0), (_mfilt1))) 1108#define ath_hal_waitforbeacon(_ah, _bf) \ 1109 ((*(_ah)->ah_waitForBeaconDone)((_ah), (_bf)->bf_daddr)) 1110#define ath_hal_putrxbuf(_ah, _bufaddr, _rxq) \ 1111 ((*(_ah)->ah_setRxDP)((_ah), (_bufaddr), (_rxq))) 1112/* NB: common across all chips */ 1113#define AR_TSF_L32 0x804c /* MAC local clock lower 32 bits */ 1114#define ath_hal_gettsf32(_ah) \ 1115 OS_REG_READ(_ah, AR_TSF_L32) 1116#define ath_hal_gettsf64(_ah) \ 1117 ((*(_ah)->ah_getTsf64)((_ah))) 1118#define ath_hal_settsf64(_ah, _val) \ 1119 ((*(_ah)->ah_setTsf64)((_ah), (_val))) 1120#define ath_hal_resettsf(_ah) \ 1121 ((*(_ah)->ah_resetTsf)((_ah))) 1122#define ath_hal_rxena(_ah) \ 1123 ((*(_ah)->ah_enableReceive)((_ah))) 1124#define ath_hal_puttxbuf(_ah, _q, _bufaddr) \ 1125 ((*(_ah)->ah_setTxDP)((_ah), (_q), (_bufaddr))) 1126#define ath_hal_gettxbuf(_ah, _q) \ 1127 ((*(_ah)->ah_getTxDP)((_ah), (_q))) 1128#define ath_hal_numtxpending(_ah, _q) \ 1129 ((*(_ah)->ah_numTxPending)((_ah), (_q))) 1130#define ath_hal_getrxbuf(_ah, _rxq) \ 1131 ((*(_ah)->ah_getRxDP)((_ah), (_rxq))) 1132#define ath_hal_txstart(_ah, _q) \ 1133 ((*(_ah)->ah_startTxDma)((_ah), (_q))) 1134#define ath_hal_setchannel(_ah, _chan) \ 1135 ((*(_ah)->ah_setChannel)((_ah), (_chan))) 1136#define ath_hal_calibrate(_ah, _chan, _iqcal) \ 1137 ((*(_ah)->ah_perCalibration)((_ah), (_chan), (_iqcal))) 1138#define ath_hal_calibrateN(_ah, _chan, _lcal, _isdone) \ 1139 ((*(_ah)->ah_perCalibrationN)((_ah), (_chan), 0x1, (_lcal), (_isdone))) 1140#define ath_hal_calreset(_ah, _chan) \ 1141 ((*(_ah)->ah_resetCalValid)((_ah), (_chan))) 1142#define ath_hal_setledstate(_ah, _state) \ 1143 ((*(_ah)->ah_setLedState)((_ah), (_state))) 1144#define ath_hal_beaconinit(_ah, _nextb, _bperiod) \ 1145 ((*(_ah)->ah_beaconInit)((_ah), (_nextb), (_bperiod))) 1146#define ath_hal_beaconreset(_ah) \ 1147 ((*(_ah)->ah_resetStationBeaconTimers)((_ah))) 1148#define ath_hal_beaconsettimers(_ah, _bt) \ 1149 ((*(_ah)->ah_setBeaconTimers)((_ah), (_bt))) 1150#define ath_hal_beacontimers(_ah, _bs) \ 1151 ((*(_ah)->ah_setStationBeaconTimers)((_ah), (_bs))) 1152#define ath_hal_getnexttbtt(_ah) \ 1153 ((*(_ah)->ah_getNextTBTT)((_ah))) 1154#define ath_hal_setassocid(_ah, _bss, _associd) \ 1155 ((*(_ah)->ah_writeAssocid)((_ah), (_bss), (_associd))) 1156#define ath_hal_phydisable(_ah) \ 1157 ((*(_ah)->ah_phyDisable)((_ah))) 1158#define ath_hal_setopmode(_ah) \ 1159 ((*(_ah)->ah_setPCUConfig)((_ah))) 1160#define ath_hal_stoptxdma(_ah, _qnum) \ 1161 ((*(_ah)->ah_stopTxDma)((_ah), (_qnum))) 1162#define ath_hal_stoppcurecv(_ah) \ 1163 ((*(_ah)->ah_stopPcuReceive)((_ah))) 1164#define ath_hal_startpcurecv(_ah, _is_scanning) \ 1165 ((*(_ah)->ah_startPcuReceive)((_ah), (_is_scanning))) 1166#define ath_hal_stopdmarecv(_ah) \ 1167 ((*(_ah)->ah_stopDmaReceive)((_ah))) 1168#define ath_hal_getdiagstate(_ah, _id, _indata, _insize, _outdata, _outsize) \ 1169 ((*(_ah)->ah_getDiagState)((_ah), (_id), \ 1170 (_indata), (_insize), (_outdata), (_outsize))) 1171#define ath_hal_getfatalstate(_ah, _outdata, _outsize) \ 1172 ath_hal_getdiagstate(_ah, 29, NULL, 0, (_outdata), _outsize) 1173#define ath_hal_setuptxqueue(_ah, _type, _irq) \ 1174 ((*(_ah)->ah_setupTxQueue)((_ah), (_type), (_irq))) 1175#define ath_hal_resettxqueue(_ah, _q) \ 1176 ((*(_ah)->ah_resetTxQueue)((_ah), (_q))) 1177#define ath_hal_releasetxqueue(_ah, _q) \ 1178 ((*(_ah)->ah_releaseTxQueue)((_ah), (_q))) 1179#define ath_hal_gettxqueueprops(_ah, _q, _qi) \ 1180 ((*(_ah)->ah_getTxQueueProps)((_ah), (_q), (_qi))) 1181#define ath_hal_settxqueueprops(_ah, _q, _qi) \ 1182 ((*(_ah)->ah_setTxQueueProps)((_ah), (_q), (_qi))) 1183/* NB: common across all chips */ 1184#define AR_Q_TXE 0x0840 /* MAC Transmit Queue enable */ 1185#define ath_hal_txqenabled(_ah, _qnum) \ 1186 (OS_REG_READ(_ah, AR_Q_TXE) & (1<<(_qnum))) 1187#define ath_hal_getrfgain(_ah) \ 1188 ((*(_ah)->ah_getRfGain)((_ah))) 1189#define ath_hal_getdefantenna(_ah) \ 1190 ((*(_ah)->ah_getDefAntenna)((_ah))) 1191#define ath_hal_setdefantenna(_ah, _ant) \ 1192 ((*(_ah)->ah_setDefAntenna)((_ah), (_ant))) 1193#define ath_hal_rxmonitor(_ah, _arg, _chan) \ 1194 ((*(_ah)->ah_rxMonitor)((_ah), (_arg), (_chan))) 1195#define ath_hal_ani_poll(_ah, _chan) \ 1196 ((*(_ah)->ah_aniPoll)((_ah), (_chan))) 1197#define ath_hal_mibevent(_ah, _stats) \ 1198 ((*(_ah)->ah_procMibEvent)((_ah), (_stats))) 1199#define ath_hal_setslottime(_ah, _us) \ 1200 ((*(_ah)->ah_setSlotTime)((_ah), (_us))) 1201#define ath_hal_getslottime(_ah) \ 1202 ((*(_ah)->ah_getSlotTime)((_ah))) 1203#define ath_hal_setacktimeout(_ah, _us) \ 1204 ((*(_ah)->ah_setAckTimeout)((_ah), (_us))) 1205#define ath_hal_getacktimeout(_ah) \ 1206 ((*(_ah)->ah_getAckTimeout)((_ah))) 1207#define ath_hal_setctstimeout(_ah, _us) \ 1208 ((*(_ah)->ah_setCTSTimeout)((_ah), (_us))) 1209#define ath_hal_getctstimeout(_ah) \ 1210 ((*(_ah)->ah_getCTSTimeout)((_ah))) 1211#define ath_hal_getcapability(_ah, _cap, _param, _result) \ 1212 ((*(_ah)->ah_getCapability)((_ah), (_cap), (_param), (_result))) 1213#define ath_hal_setcapability(_ah, _cap, _param, _v, _status) \ 1214 ((*(_ah)->ah_setCapability)((_ah), (_cap), (_param), (_v), (_status))) 1215#define ath_hal_ciphersupported(_ah, _cipher) \ 1216 (ath_hal_getcapability(_ah, HAL_CAP_CIPHER, _cipher, NULL) == HAL_OK) 1217#define ath_hal_getregdomain(_ah, _prd) \ 1218 (ath_hal_getcapability(_ah, HAL_CAP_REG_DMN, 0, (_prd)) == HAL_OK) 1219#define ath_hal_setregdomain(_ah, _rd) \ 1220 ath_hal_setcapability(_ah, HAL_CAP_REG_DMN, 0, _rd, NULL) 1221#define ath_hal_getcountrycode(_ah, _pcc) \ 1222 (*(_pcc) = (_ah)->ah_countryCode) 1223#define ath_hal_gettkipmic(_ah) \ 1224 (ath_hal_getcapability(_ah, HAL_CAP_TKIP_MIC, 1, NULL) == HAL_OK) 1225#define ath_hal_settkipmic(_ah, _v) \ 1226 ath_hal_setcapability(_ah, HAL_CAP_TKIP_MIC, 1, _v, NULL) 1227#define ath_hal_hastkipsplit(_ah) \ 1228 (ath_hal_getcapability(_ah, HAL_CAP_TKIP_SPLIT, 0, NULL) == HAL_OK) 1229#define ath_hal_gettkipsplit(_ah) \ 1230 (ath_hal_getcapability(_ah, HAL_CAP_TKIP_SPLIT, 1, NULL) == HAL_OK) 1231#define ath_hal_settkipsplit(_ah, _v) \ 1232 ath_hal_setcapability(_ah, HAL_CAP_TKIP_SPLIT, 1, _v, NULL) 1233#define ath_hal_haswmetkipmic(_ah) \ 1234 (ath_hal_getcapability(_ah, HAL_CAP_WME_TKIPMIC, 0, NULL) == HAL_OK) 1235#define ath_hal_hwphycounters(_ah) \ 1236 (ath_hal_getcapability(_ah, HAL_CAP_PHYCOUNTERS, 0, NULL) == HAL_OK) 1237#define ath_hal_hasdiversity(_ah) \ 1238 (ath_hal_getcapability(_ah, HAL_CAP_DIVERSITY, 0, NULL) == HAL_OK) 1239#define ath_hal_getdiversity(_ah) \ 1240 (ath_hal_getcapability(_ah, HAL_CAP_DIVERSITY, 1, NULL) == HAL_OK) 1241#define ath_hal_setdiversity(_ah, _v) \ 1242 ath_hal_setcapability(_ah, HAL_CAP_DIVERSITY, 1, _v, NULL) 1243#define ath_hal_getantennaswitch(_ah) \ 1244 ((*(_ah)->ah_getAntennaSwitch)((_ah))) 1245#define ath_hal_setantennaswitch(_ah, _v) \ 1246 ((*(_ah)->ah_setAntennaSwitch)((_ah), (_v))) 1247#define ath_hal_getdiag(_ah, _pv) \ 1248 (ath_hal_getcapability(_ah, HAL_CAP_DIAG, 0, _pv) == HAL_OK) 1249#define ath_hal_setdiag(_ah, _v) \ 1250 ath_hal_setcapability(_ah, HAL_CAP_DIAG, 0, _v, NULL) 1251#define ath_hal_getnumtxqueues(_ah, _pv) \ 1252 (ath_hal_getcapability(_ah, HAL_CAP_NUM_TXQUEUES, 0, _pv) == HAL_OK) 1253#define ath_hal_hasveol(_ah) \ 1254 (ath_hal_getcapability(_ah, HAL_CAP_VEOL, 0, NULL) == HAL_OK) 1255#define ath_hal_hastxpowlimit(_ah) \ 1256 (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 0, NULL) == HAL_OK) 1257#define ath_hal_settxpowlimit(_ah, _pow) \ 1258 ((*(_ah)->ah_setTxPowerLimit)((_ah), (_pow))) 1259#define ath_hal_gettxpowlimit(_ah, _ppow) \ 1260 (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 1, _ppow) == HAL_OK) 1261#define ath_hal_getmaxtxpow(_ah, _ppow) \ 1262 (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 2, _ppow) == HAL_OK) 1263#define ath_hal_gettpscale(_ah, _scale) \ 1264 (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 3, _scale) == HAL_OK) 1265#define ath_hal_settpscale(_ah, _v) \ 1266 ath_hal_setcapability(_ah, HAL_CAP_TXPOW, 3, _v, NULL) 1267#define ath_hal_hastpc(_ah) \ 1268 (ath_hal_getcapability(_ah, HAL_CAP_TPC, 0, NULL) == HAL_OK) 1269#define ath_hal_gettpc(_ah) \ 1270 (ath_hal_getcapability(_ah, HAL_CAP_TPC, 1, NULL) == HAL_OK) 1271#define ath_hal_settpc(_ah, _v) \ 1272 ath_hal_setcapability(_ah, HAL_CAP_TPC, 1, _v, NULL) 1273#define ath_hal_hasbursting(_ah) \ 1274 (ath_hal_getcapability(_ah, HAL_CAP_BURST, 0, NULL) == HAL_OK) 1275#define ath_hal_setmcastkeysearch(_ah, _v) \ 1276 ath_hal_setcapability(_ah, HAL_CAP_MCAST_KEYSRCH, 0, _v, NULL) 1277#define ath_hal_hasmcastkeysearch(_ah) \ 1278 (ath_hal_getcapability(_ah, HAL_CAP_MCAST_KEYSRCH, 0, NULL) == HAL_OK) 1279#define ath_hal_getmcastkeysearch(_ah) \ 1280 (ath_hal_getcapability(_ah, HAL_CAP_MCAST_KEYSRCH, 1, NULL) == HAL_OK) 1281#define ath_hal_hasfastframes(_ah) \ 1282 (ath_hal_getcapability(_ah, HAL_CAP_FASTFRAME, 0, NULL) == HAL_OK) 1283#define ath_hal_hasbssidmask(_ah) \ 1284 (ath_hal_getcapability(_ah, HAL_CAP_BSSIDMASK, 0, NULL) == HAL_OK) 1285#define ath_hal_hasbssidmatch(_ah) \ 1286 (ath_hal_getcapability(_ah, HAL_CAP_BSSIDMATCH, 0, NULL) == HAL_OK) 1287#define ath_hal_hastsfadjust(_ah) \ 1288 (ath_hal_getcapability(_ah, HAL_CAP_TSF_ADJUST, 0, NULL) == HAL_OK) 1289#define ath_hal_gettsfadjust(_ah) \ 1290 (ath_hal_getcapability(_ah, HAL_CAP_TSF_ADJUST, 1, NULL) == HAL_OK) 1291#define ath_hal_settsfadjust(_ah, _onoff) \ 1292 ath_hal_setcapability(_ah, HAL_CAP_TSF_ADJUST, 1, _onoff, NULL) 1293#define ath_hal_hasrfsilent(_ah) \ 1294 (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 0, NULL) == HAL_OK) 1295#define ath_hal_getrfkill(_ah) \ 1296 (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 1, NULL) == HAL_OK) 1297#define ath_hal_setrfkill(_ah, _onoff) \ 1298 ath_hal_setcapability(_ah, HAL_CAP_RFSILENT, 1, _onoff, NULL) 1299#define ath_hal_getrfsilent(_ah, _prfsilent) \ 1300 (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 2, _prfsilent) == HAL_OK) 1301#define ath_hal_setrfsilent(_ah, _rfsilent) \ 1302 ath_hal_setcapability(_ah, HAL_CAP_RFSILENT, 2, _rfsilent, NULL) 1303#define ath_hal_gettpack(_ah, _ptpack) \ 1304 (ath_hal_getcapability(_ah, HAL_CAP_TPC_ACK, 0, _ptpack) == HAL_OK) 1305#define ath_hal_settpack(_ah, _tpack) \ 1306 ath_hal_setcapability(_ah, HAL_CAP_TPC_ACK, 0, _tpack, NULL) 1307#define ath_hal_gettpcts(_ah, _ptpcts) \ 1308 (ath_hal_getcapability(_ah, HAL_CAP_TPC_CTS, 0, _ptpcts) == HAL_OK) 1309#define ath_hal_settpcts(_ah, _tpcts) \ 1310 ath_hal_setcapability(_ah, HAL_CAP_TPC_CTS, 0, _tpcts, NULL) 1311#define ath_hal_hasintmit(_ah) \ 1312 (ath_hal_getcapability(_ah, HAL_CAP_INTMIT, \ 1313 HAL_CAP_INTMIT_PRESENT, NULL) == HAL_OK) 1314#define ath_hal_getintmit(_ah) \ 1315 (ath_hal_getcapability(_ah, HAL_CAP_INTMIT, \ 1316 HAL_CAP_INTMIT_ENABLE, NULL) == HAL_OK) 1317#define ath_hal_setintmit(_ah, _v) \ 1318 ath_hal_setcapability(_ah, HAL_CAP_INTMIT, \ 1319 HAL_CAP_INTMIT_ENABLE, _v, NULL) 1320#define ath_hal_hasmybeacon(_ah) \ 1321 (ath_hal_getcapability(_ah, HAL_CAP_DO_MYBEACON, 1, NULL) == HAL_OK) 1322 1323#define ath_hal_hasenforcetxop(_ah) \ 1324 (ath_hal_getcapability(_ah, HAL_CAP_ENFORCE_TXOP, 0, NULL) == HAL_OK) 1325#define ath_hal_getenforcetxop(_ah) \ 1326 (ath_hal_getcapability(_ah, HAL_CAP_ENFORCE_TXOP, 1, NULL) == HAL_OK) 1327#define ath_hal_setenforcetxop(_ah, _v) \ 1328 ath_hal_setcapability(_ah, HAL_CAP_ENFORCE_TXOP, 1, _v, NULL) 1329 1330#define ath_hal_hasrxlnamixer(_ah) \ 1331 (ath_hal_getcapability(_ah, HAL_CAP_RX_LNA_MIXING, 0, NULL) == HAL_OK) 1332 1333#define ath_hal_hasdivantcomb(_ah) \ 1334 (ath_hal_getcapability(_ah, HAL_CAP_ANT_DIV_COMB, 0, NULL) == HAL_OK) 1335#define ath_hal_hasldpc(_ah) \ 1336 (ath_hal_getcapability(_ah, HAL_CAP_LDPC, 0, NULL) == HAL_OK) 1337#define ath_hal_hasldpcwar(_ah) \ 1338 (ath_hal_getcapability(_ah, HAL_CAP_LDPCWAR, 0, NULL) == HAL_OK) 1339 1340/* EDMA definitions */ 1341#define ath_hal_hasedma(_ah) \ 1342 (ath_hal_getcapability(_ah, HAL_CAP_ENHANCED_DMA_SUPPORT, \ 1343 0, NULL) == HAL_OK) 1344#define ath_hal_getrxfifodepth(_ah, _qtype, _req) \ 1345 (ath_hal_getcapability(_ah, HAL_CAP_RXFIFODEPTH, _qtype, _req) \ 1346 == HAL_OK) 1347#define ath_hal_getntxmaps(_ah, _req) \ 1348 (ath_hal_getcapability(_ah, HAL_CAP_NUM_TXMAPS, 0, _req) \ 1349 == HAL_OK) 1350#define ath_hal_gettxdesclen(_ah, _req) \ 1351 (ath_hal_getcapability(_ah, HAL_CAP_TXDESCLEN, 0, _req) \ 1352 == HAL_OK) 1353#define ath_hal_gettxstatuslen(_ah, _req) \ 1354 (ath_hal_getcapability(_ah, HAL_CAP_TXSTATUSLEN, 0, _req) \ 1355 == HAL_OK) 1356#define ath_hal_getrxstatuslen(_ah, _req) \ 1357 (ath_hal_getcapability(_ah, HAL_CAP_RXSTATUSLEN, 0, _req) \ 1358 == HAL_OK) 1359#define ath_hal_setrxbufsize(_ah, _req) \ 1360 (ath_hal_setcapability(_ah, HAL_CAP_RXBUFSIZE, 0, _req, NULL) \ 1361 == AH_TRUE) 1362 1363#define ath_hal_getchannoise(_ah, _c) \ 1364 ((*(_ah)->ah_getChanNoise)((_ah), (_c))) 1365 1366/* 802.11n HAL methods */ 1367#define ath_hal_getrxchainmask(_ah, _prxchainmask) \ 1368 (ath_hal_getcapability(_ah, HAL_CAP_RX_CHAINMASK, 0, _prxchainmask)) 1369#define ath_hal_gettxchainmask(_ah, _ptxchainmask) \ 1370 (ath_hal_getcapability(_ah, HAL_CAP_TX_CHAINMASK, 0, _ptxchainmask)) 1371#define ath_hal_setrxchainmask(_ah, _rx) \ 1372 (ath_hal_setcapability(_ah, HAL_CAP_RX_CHAINMASK, 1, _rx, NULL)) 1373#define ath_hal_settxchainmask(_ah, _tx) \ 1374 (ath_hal_setcapability(_ah, HAL_CAP_TX_CHAINMASK, 1, _tx, NULL)) 1375#define ath_hal_split4ktrans(_ah) \ 1376 (ath_hal_getcapability(_ah, HAL_CAP_SPLIT_4KB_TRANS, \ 1377 0, NULL) == HAL_OK) 1378#define ath_hal_self_linked_final_rxdesc(_ah) \ 1379 (ath_hal_getcapability(_ah, HAL_CAP_RXDESC_SELFLINK, \ 1380 0, NULL) == HAL_OK) 1381#define ath_hal_gtxto_supported(_ah) \ 1382 (ath_hal_getcapability(_ah, HAL_CAP_GTXTO, 0, NULL) == HAL_OK) 1383#define ath_hal_get_rx_tsf_prec(_ah, _pr) \ 1384 (ath_hal_getcapability((_ah), HAL_CAP_RXTSTAMP_PREC, 0, (_pr)) \ 1385 == HAL_OK) 1386#define ath_hal_get_tx_tsf_prec(_ah, _pr) \ 1387 (ath_hal_getcapability((_ah), HAL_CAP_TXTSTAMP_PREC, 0, (_pr)) \ 1388 == HAL_OK) 1389#define ath_hal_setuprxdesc(_ah, _ds, _size, _intreq) \ 1390 ((*(_ah)->ah_setupRxDesc)((_ah), (_ds), (_size), (_intreq))) 1391#define ath_hal_rxprocdesc(_ah, _ds, _dspa, _dsnext, _rs) \ 1392 ((*(_ah)->ah_procRxDesc)((_ah), (_ds), (_dspa), (_dsnext), 0, (_rs))) 1393#define ath_hal_setuptxdesc(_ah, _ds, _plen, _hlen, _atype, _txpow, \ 1394 _txr0, _txtr0, _keyix, _ant, _flags, \ 1395 _rtsrate, _rtsdura) \ 1396 ((*(_ah)->ah_setupTxDesc)((_ah), (_ds), (_plen), (_hlen), (_atype), \ 1397 (_txpow), (_txr0), (_txtr0), (_keyix), (_ant), \ 1398 (_flags), (_rtsrate), (_rtsdura), 0, 0, 0)) 1399#define ath_hal_setupxtxdesc(_ah, _ds, \ 1400 _txr1, _txtr1, _txr2, _txtr2, _txr3, _txtr3) \ 1401 ((*(_ah)->ah_setupXTxDesc)((_ah), (_ds), \ 1402 (_txr1), (_txtr1), (_txr2), (_txtr2), (_txr3), (_txtr3))) 1403#define ath_hal_filltxdesc(_ah, _ds, _b, _l, _did, _qid, _first, _last, _ds0) \ 1404 ((*(_ah)->ah_fillTxDesc)((_ah), (_ds), (_b), (_l), (_did), (_qid), \ 1405 (_first), (_last), (_ds0))) 1406#define ath_hal_txprocdesc(_ah, _ds, _ts) \ 1407 ((*(_ah)->ah_procTxDesc)((_ah), (_ds), (_ts))) 1408#define ath_hal_gettxintrtxqs(_ah, _txqs) \ 1409 ((*(_ah)->ah_getTxIntrQueue)((_ah), (_txqs))) 1410#define ath_hal_gettxcompletionrates(_ah, _ds, _rates, _tries) \ 1411 ((*(_ah)->ah_getTxCompletionRates)((_ah), (_ds), (_rates), (_tries))) 1412#define ath_hal_settxdesclink(_ah, _ds, _link) \ 1413 ((*(_ah)->ah_setTxDescLink)((_ah), (_ds), (_link))) 1414#define ath_hal_gettxdesclink(_ah, _ds, _link) \ 1415 ((*(_ah)->ah_getTxDescLink)((_ah), (_ds), (_link))) 1416#define ath_hal_gettxdesclinkptr(_ah, _ds, _linkptr) \ 1417 ((*(_ah)->ah_getTxDescLinkPtr)((_ah), (_ds), (_linkptr))) 1418#define ath_hal_setuptxstatusring(_ah, _tsstart, _tspstart, _size) \ 1419 ((*(_ah)->ah_setupTxStatusRing)((_ah), (_tsstart), (_tspstart), \ 1420 (_size))) 1421#define ath_hal_gettxrawtxdesc(_ah, _txstatus) \ 1422 ((*(_ah)->ah_getTxRawTxDesc)((_ah), (_txstatus))) 1423 1424#define ath_hal_setupfirsttxdesc(_ah, _ds, _aggrlen, _flags, _txpower, \ 1425 _txr0, _txtr0, _antm, _rcr, _rcd) \ 1426 ((*(_ah)->ah_setupFirstTxDesc)((_ah), (_ds), (_aggrlen), (_flags), \ 1427 (_txpower), (_txr0), (_txtr0), (_antm), (_rcr), (_rcd))) 1428#define ath_hal_chaintxdesc(_ah, _ds, _bl, _sl, _pktlen, _hdrlen, _type, \ 1429 _keyix, _cipher, _delims, _first, _last, _lastaggr) \ 1430 ((*(_ah)->ah_chainTxDesc)((_ah), (_ds), (_bl), (_sl), \ 1431 (_pktlen), (_hdrlen), (_type), (_keyix), (_cipher), (_delims), \ 1432 (_first), (_last), (_lastaggr))) 1433#define ath_hal_setuplasttxdesc(_ah, _ds, _ds0) \ 1434 ((*(_ah)->ah_setupLastTxDesc)((_ah), (_ds), (_ds0))) 1435 1436#define ath_hal_set11nratescenario(_ah, _ds, _dur, _rt, _series, _ns, _flags) \ 1437 ((*(_ah)->ah_set11nRateScenario)((_ah), (_ds), (_dur), (_rt), \ 1438 (_series), (_ns), (_flags))) 1439 1440#define ath_hal_set11n_aggr_first(_ah, _ds, _len, _num) \ 1441 ((*(_ah)->ah_set11nAggrFirst)((_ah), (_ds), (_len), (_num))) 1442#define ath_hal_set11n_aggr_middle(_ah, _ds, _num) \ 1443 ((*(_ah)->ah_set11nAggrMiddle)((_ah), (_ds), (_num))) 1444#define ath_hal_set11n_aggr_last(_ah, _ds) \ 1445 ((*(_ah)->ah_set11nAggrLast)((_ah), (_ds))) 1446 1447#define ath_hal_set11nburstduration(_ah, _ds, _dur) \ 1448 ((*(_ah)->ah_set11nBurstDuration)((_ah), (_ds), (_dur))) 1449#define ath_hal_clr11n_aggr(_ah, _ds) \ 1450 ((*(_ah)->ah_clr11nAggr)((_ah), (_ds))) 1451#define ath_hal_set11n_virtmorefrag(_ah, _ds, _v) \ 1452 ((*(_ah)->ah_set11nVirtMoreFrag)((_ah), (_ds), (_v))) 1453 1454#define ath_hal_gpioCfgOutput(_ah, _gpio, _type) \ 1455 ((*(_ah)->ah_gpioCfgOutput)((_ah), (_gpio), (_type))) 1456#define ath_hal_gpioset(_ah, _gpio, _b) \ 1457 ((*(_ah)->ah_gpioSet)((_ah), (_gpio), (_b))) 1458#define ath_hal_gpioget(_ah, _gpio) \ 1459 ((*(_ah)->ah_gpioGet)((_ah), (_gpio))) 1460#define ath_hal_gpiosetintr(_ah, _gpio, _b) \ 1461 ((*(_ah)->ah_gpioSetIntr)((_ah), (_gpio), (_b))) 1462 1463/* 1464 * PCIe suspend/resume/poweron/poweroff related macros 1465 */ 1466#define ath_hal_enablepcie(_ah, _restore, _poweroff) \ 1467 ((*(_ah)->ah_configPCIE)((_ah), (_restore), (_poweroff))) 1468#define ath_hal_disablepcie(_ah) \ 1469 ((*(_ah)->ah_disablePCIE)((_ah))) 1470 1471/* 1472 * This is badly-named; you need to set the correct parameters 1473 * to begin to receive useful radar events; and even then 1474 * it doesn't "enable" DFS. See the ath_dfs/null/ module for 1475 * more information. 1476 */ 1477#define ath_hal_enabledfs(_ah, _param) \ 1478 ((*(_ah)->ah_enableDfs)((_ah), (_param))) 1479#define ath_hal_getdfsthresh(_ah, _param) \ 1480 ((*(_ah)->ah_getDfsThresh)((_ah), (_param))) 1481#define ath_hal_getdfsdefaultthresh(_ah, _param) \ 1482 ((*(_ah)->ah_getDfsDefaultThresh)((_ah), (_param))) 1483#define ath_hal_procradarevent(_ah, _rxs, _fulltsf, _buf, _event) \ 1484 ((*(_ah)->ah_procRadarEvent)((_ah), (_rxs), (_fulltsf), \ 1485 (_buf), (_event))) 1486#define ath_hal_is_fast_clock_enabled(_ah) \ 1487 ((*(_ah)->ah_isFastClockEnabled)((_ah))) 1488#define ath_hal_radar_wait(_ah, _chan) \ 1489 ((*(_ah)->ah_radarWait)((_ah), (_chan))) 1490#define ath_hal_get_mib_cycle_counts(_ah, _sample) \ 1491 ((*(_ah)->ah_getMibCycleCounts)((_ah), (_sample))) 1492#define ath_hal_get_chan_ext_busy(_ah) \ 1493 ((*(_ah)->ah_get11nExtBusy)((_ah))) 1494#define ath_hal_setchainmasks(_ah, _txchainmask, _rxchainmask) \ 1495 ((*(_ah)->ah_setChainMasks)((_ah), (_txchainmask), (_rxchainmask))) 1496#define ath_hal_set_quiet(_ah, _p, _d, _o, _f) \ 1497 ((*(_ah)->ah_setQuiet)((_ah), (_p), (_d), (_o), (_f))) 1498 1499#define ath_hal_spectral_supported(_ah) \ 1500 (ath_hal_getcapability(_ah, HAL_CAP_SPECTRAL_SCAN, 0, NULL) == HAL_OK) 1501#define ath_hal_spectral_get_config(_ah, _p) \ 1502 ((*(_ah)->ah_spectralGetConfig)((_ah), (_p))) 1503#define ath_hal_spectral_configure(_ah, _p) \ 1504 ((*(_ah)->ah_spectralConfigure)((_ah), (_p))) 1505#define ath_hal_spectral_start(_ah) \ 1506 ((*(_ah)->ah_spectralStart)((_ah))) 1507#define ath_hal_spectral_stop(_ah) \ 1508 ((*(_ah)->ah_spectralStop)((_ah))) 1509 1510#define ath_hal_btcoex_supported(_ah) \ 1511 (ath_hal_getcapability(_ah, HAL_CAP_BT_COEX, 0, NULL) == HAL_OK) 1512#define ath_hal_btcoex_set_info(_ah, _info) \ 1513 ((*(_ah)->ah_btCoexSetInfo)((_ah), (_info))) 1514#define ath_hal_btcoex_set_config(_ah, _cfg) \ 1515 ((*(_ah)->ah_btCoexSetConfig)((_ah), (_cfg))) 1516#define ath_hal_btcoex_set_qcu_thresh(_ah, _qcuid) \ 1517 ((*(_ah)->ah_btCoexSetQcuThresh)((_ah), (_qcuid))) 1518#define ath_hal_btcoex_set_weights(_ah, _weight) \ 1519 ((*(_ah)->ah_btCoexSetWeights)((_ah), (_weight))) 1520#define ath_hal_btcoex_set_bmiss_thresh(_ah, _thr) \ 1521 ((*(_ah)->ah_btCoexSetBmissThresh)((_ah), (_thr))) 1522#define ath_hal_btcoex_set_parameter(_ah, _attrib, _val) \ 1523 ((*(_ah)->ah_btCoexSetParameter)((_ah), (_attrib), (_val))) 1524#define ath_hal_btcoex_enable(_ah) \ 1525 ((*(_ah)->ah_btCoexEnable)((_ah))) 1526#define ath_hal_btcoex_disable(_ah) \ 1527 ((*(_ah)->ah_btCoexDisable)((_ah))) 1528 1529#define ath_hal_btcoex_mci_setup(_ah, _gp, _gb, _gl, _sp) \ 1530 ((*(_ah)->ah_btMciSetup)((_ah), (_gp), (_gb), (_gl), (_sp))) 1531#define ath_hal_btcoex_mci_send_message(_ah, _h, _f, _p, _l, _wd, _cbt) \ 1532 ((*(_ah)->ah_btMciSendMessage)((_ah), (_h), (_f), (_p), (_l), (_wd), (_cbt))) 1533#define ath_hal_btcoex_mci_get_interrupt(_ah, _mi, _mm) \ 1534 ((*(_ah)->ah_btMciGetInterrupt)((_ah), (_mi), (_mm))) 1535#define ath_hal_btcoex_mci_state(_ah, _st, _pd) \ 1536 ((*(_ah)->ah_btMciState)((_ah), (_st), (_pd))) 1537#define ath_hal_btcoex_mci_detach(_ah) \ 1538 ((*(_ah)->ah_btMciDetach)((_ah))) 1539 1540#define ath_hal_div_comb_conf_get(_ah, _conf) \ 1541 ((*(_ah)->ah_divLnaConfGet)((_ah), (_conf))) 1542#define ath_hal_div_comb_conf_set(_ah, _conf) \ 1543 ((*(_ah)->ah_divLnaConfSet)((_ah), (_conf))) 1544 1545#endif /* _DEV_ATH_ATHVAR_H */ 1546