nvidia/engine/nv_acc_dma.c

1027 	si->engine.fifo.handle[0] = NV_ROP5_SOLID;
1028 	si->engine.fifo.handle[1] = NV_IMAGE_BLACK_RECTANGLE;
1029 	si->engine.fifo.handle[2] = NV_IMAGE_PATTERN;
1030 	si->engine.fifo.handle[3] = NV4_SURFACE; /* NV10_CONTEXT_SURFACES_2D is identical */
1031 	si->engine.fifo.handle[4] = NV_IMAGE_BLIT;
1032 	si->engine.fifo.handle[5] = NV4_GDI_RECTANGLE_TEXT;
1033 	si->engine.fifo.handle[6] = NV4_CONTEXT_SURFACES_ARGB_ZS;//NV1_RENDER_SOLID_LIN;
1034 	si->engine.fifo.handle[7] = NV4_DX5_TEXTURE_TRIANGLE;
1038 		si->engine.fifo.ch_ptr[cnt] = 0;
1045 		si->engine.fifo.ch_ptr[(si->engine.fifo.handle[cnt])]
1074 	/* wait for room in fifo for new FIFO assigment cmds if needed: */
1084 	nv_acc_set_ch_dma(NV_GENERAL_FIFO_CH0, si->engine.fifo.handle[0]);
1086 	nv_acc_set_ch_dma(NV_GENERAL_FIFO_CH1, si->engine.fifo.handle[1]);
1088 	nv_acc_set_ch_dma(NV_GENERAL_FIFO_CH2, si->engine.fifo.handle[2]);
1090 	nv_acc_set_ch_dma(NV_GENERAL_FIFO_CH3, si->engine.fifo.handle[3]);
1092 	nv_acc_set_ch_dma(NV_GENERAL_FIFO_CH4, si->engine.fifo.handle[4]);
1094 	nv_acc_set_ch_dma(NV_GENERAL_FIFO_CH5, si->engine.fifo.handle[5]);
1098 		nv_acc_set_ch_dma(NV_GENERAL_FIFO_CH6, si->engine.fifo.handle[6]);
1100 		nv_acc_set_ch_dma(NV_GENERAL_FIFO_CH7, si->engine.fifo.handle[7]);
1125 	/* wait for room in fifo for surface setup cmd if needed */
1139 	/* wait for room in fifo for pattern colordepth setup cmd if needed */
1145 	/* wait for room in fifo for bitmap colordepth setup cmd if needed */
1152 	/* wait for room in fifo for pattern cmd if needed. */
1575 		((si->engine.fifo.ch_ptr[cmd] + offset) & 0x0000fffc));
1593  * switching fifo channel assignments this way has no noticable slowdown:
1599 	if (!si->engine.fifo.ch_ptr[NV_ROP5_SOLID] ||
1600 		!si->engine.fifo.ch_ptr[NV_IMAGE_BLACK_RECTANGLE] ||
1601 		!si->engine.fifo.ch_ptr[NV_IMAGE_PATTERN] ||
1602 		!si->engine.fifo.ch_ptr[NV4_SURFACE] ||
1603 		!si->engine.fifo.ch_ptr[NV_IMAGE_BLIT] ||
1604 		!si->engine.fifo.ch_ptr[NV4_GDI_RECTANGLE_TEXT] ||
1605 		!si->engine.fifo.ch_ptr[NV_SCALED_IMAGE_FROM_MEMORY])
1610 		si->engine.fifo.ch_ptr[si->engine.fifo.handle[0]] = 0;
1611 		si->engine.fifo.ch_ptr[si->engine.fifo.handle[1]] = 0;
1612 		si->engine.fifo.ch_ptr[si->engine.fifo.handle[2]] = 0;
1613 		si->engine.fifo.ch_ptr[si->engine.fifo.handle[3]] = 0;
1614 		si->engine.fifo.ch_ptr[si->engine.fifo.handle[4]] = 0;
1615 		si->engine.fifo.ch_ptr[si->engine.fifo.handle[5]] = 0;
1616 		si->engine.fifo.ch_ptr[si->engine.fifo.handle[6]] = 0;
1619 		si->engine.fifo.handle[0] = NV_ROP5_SOLID;
1620 		si->engine.fifo.handle[1] = NV_IMAGE_BLACK_RECTANGLE;
1621 		si->engine.fifo.handle[2] = NV_IMAGE_PATTERN;
1622 		si->engine.fifo.handle[3] = NV4_SURFACE;
1623 		si->engine.fifo.handle[4] = NV_IMAGE_BLIT;
1624 		si->engine.fifo.handle[5] = NV4_GDI_RECTANGLE_TEXT;
1625 		si->engine.fifo.handle[6] = NV_SCALED_IMAGE_FROM_MEMORY;
1632 			si->engine.fifo.ch_ptr[(si->engine.fifo.handle[cnt])] =
1636 		/* wait for room in fifo for new FIFO assigment cmds if needed. */
1641 		nv_acc_set_ch_dma(NV_GENERAL_FIFO_CH0, si->engine.fifo.handle[0]);
1643 		nv_acc_set_ch_dma(NV_GENERAL_FIFO_CH1, si->engine.fifo.handle[1]);
1645 		nv_acc_set_ch_dma(NV_GENERAL_FIFO_CH2, si->engine.fifo.handle[2]);
1647 		nv_acc_set_ch_dma(NV_GENERAL_FIFO_CH3, si->engine.fifo.handle[3]);
1649 		nv_acc_set_ch_dma(NV_GENERAL_FIFO_CH4, si->engine.fifo.handle[4]);
1651 		nv_acc_set_ch_dma(NV_GENERAL_FIFO_CH5, si->engine.fifo.handle[5]);
1653 		nv_acc_set_ch_dma(NV_GENERAL_FIFO_CH6, si->engine.fifo.handle[6]);
1684 	 * wait for room in fifo for ROP cmd if needed. */
1701 		/* wait for room in fifo for blit cmd if needed. */
1775 		/* wait for room in fifo for surface setup cmd if needed */
1785 		/* wait for room in fifo for cmds if needed. */
1795 		/* wait for room in fifo for cmd if needed. */
1815 		/* wait for room in fifo for blit cmd if needed. */
1873 		/* wait for room in fifo for surface setup cmd if needed */
1940 		/* wait for room in fifo for surface setup cmd if needed */
1950 		/* wait for room in fifo for cmds if needed. */
1960 		/* wait for room in fifo for cmd if needed. */
1982 		/* wait for room in fifo for blit cmd if needed. */
2054 		/* wait for room in fifo for surface setup cmd if needed */
2077 	 * wait for room in fifo for ROP and bitmap cmd if needed. */
2095 		/* wait for room in fifo for bitmap cmd if needed. */
2129 	 * wait for room in fifo for ROP and bitmap cmd if needed. */
2147 		/* wait for room in fifo for bitmap cmd if needed. */
2180 	 * wait for room in fifo for ROP and bitmap cmd if needed. */
2198 		/* wait for room in fifo for bitmap cmd if needed. */