/linux-master/drivers/gpu/drm/i915/gem/selftests/ |
H A D | mock_context.c | 32 INIT_LIST_HEAD(&ctx->stale.engines); 52 RCU_INIT_POINTER(ctx->engines, e); 113 struct i915_gem_engines *engines; local 118 engines = alloc_engines(1); 119 if (!engines) 124 __free_engines(engines, 0); 130 __free_engines(engines, 0); 135 engines->engines[0] = ce; 136 engines [all...] |
/linux-master/drivers/gpu/drm/i915/gt/ |
H A D | selftest_rc6.c | 163 struct intel_engine_cs *engine, **engines; local 173 engines = kmalloc_array(n, sizeof(*engines), GFP_KERNEL); 174 if (!engines) 179 engines[n++] = engine; 181 i915_prandom_shuffle(engines, sizeof(*engines), n, prng); 184 return engines; 190 struct intel_engine_cs **engines; local 199 engines [all...] |
H A D | intel_gt_engines_debugfs.c | 27 DEFINE_INTEL_GT_DEBUGFS_ATTRIBUTE(engines); variable 32 { "engines", &engines_fops },
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H A D | intel_engine_user.c | 82 struct list_head *engines) 89 list_add(&engine->uabi_list, engines); 91 list_sort(NULL, engines, engine_cmp); 111 for_each_uabi_engine(engine, i915) { /* all engines must agree! */ 210 LIST_HEAD(engines); 212 sort_engines(i915, &engines); 216 list_for_each_safe(it, next, &engines) { 221 continue; /* ignore incomplete engines */ 81 sort_engines(struct drm_i915_private *i915, struct list_head *engines) argument
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H A D | intel_engine.h | 295 intel_engine_create_parallel(struct intel_engine_cs **engines, argument 299 GEM_BUG_ON(!engines[0]->cops->create_parallel); 300 return engines[0]->cops->create_parallel(engines, num_engines, width);
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H A D | intel_context_types.h | 71 struct intel_context *(*create_parallel)(struct intel_engine_cs **engines,
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/linux-master/drivers/gpu/drm/i915/gem/ |
H A D | i915_gem_context_types.h | 34 * struct i915_gem_engines - A set of engines 38 /** @link: Link in i915_gem_context::stale::engines */ 45 /** @fence: Fence used for delayed destruction of engines */ 51 /** @num_engines: Number of engines in this set */ 54 /** @engines: Array of engines */ 55 struct intel_context *engines[]; member in struct:i915_gem_engines 62 /** @idx: Index into i915_gem_engines::engines */ 65 /** @engines: Engine set being iterated */ 66 const struct i915_gem_engines *engines; member in struct:i915_gem_engines_iter 256 struct i915_gem_engines __rcu *engines; member in struct:i915_gem_context 418 struct list_head engines; member in struct:i915_gem_context::__anon226 [all...] |
H A D | i915_gem_context.h | 186 return rcu_dereference_protected(ctx->engines, 211 struct i915_gem_engines *e = rcu_dereference(ctx->engines); 214 else if (likely(idx < e->num_engines && e->engines[idx])) 215 ce = intel_context_get(e->engines[idx]); 225 struct i915_gem_engines *engines) 227 it->engines = engines; 234 #define for_each_gem_engine(ce, engines, it) \ 235 for (i915_gem_engines_iter_init(&(it), (engines)); \ 224 i915_gem_engines_iter_init(struct i915_gem_engines_iter *it, struct i915_gem_engines *engines) argument
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H A D | i915_gem_context.c | 395 struct i915_gem_proto_engine *engines; member in struct:set_proto_ctx_engines 424 if (set->engines[idx].type != I915_GEM_ENGINE_TYPE_INVALID) { 451 if (copy_from_user(&ci, &ext->engines[n], sizeof(ci))) { 469 set->engines[idx].type = I915_GEM_ENGINE_TYPE_PHYSICAL; 470 set->engines[idx].engine = siblings[0]; 473 set->engines[idx].type = I915_GEM_ENGINE_TYPE_BALANCED; 474 set->engines[idx].num_siblings = num_siblings; 475 set->engines[idx].siblings = siblings; 516 if (set->engines[idx].type == I915_GEM_ENGINE_TYPE_INVALID) { 521 if (set->engines[id 1035 struct i915_gem_engines *engines = local 1042 accumulate_runtime(struct i915_drm_client *client, struct i915_gem_engines *engines) argument 1064 struct i915_gem_engines *engines = local 1382 kill_engines(struct i915_gem_engines *engines, bool exit, bool persistent) argument 1447 engines_idle_release(struct i915_gem_context *ctx, struct i915_gem_engines *engines) argument [all...] |
/linux-master/drivers/gpu/drm/i915/gt/uc/ |
H A D | selftest_guc_multi_lrc.c | 13 static void logical_sort(struct intel_engine_cs **engines, int num_engines) argument 20 if (engines[j]->logical_mask & BIT(i)) { 21 sorted[i] = engines[j]; 26 memcpy(*engines, *sorted, 122 gt_dbg(gt, "Not enough engines in class: %d\n", class);
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/linux-master/drivers/dma/idxd/ |
H A D | defaults.c | 46 engine = idxd->engines[0];
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H A D | device.c | 674 engine = idxd->engines[i]; 864 iowrite64(group->grpcfg.engines, idxd->reg_base + grpcfg_offset); 1042 int i, engines = 0; local 1048 group->grpcfg.engines = 0; 1052 eng = idxd->engines[i]; 1058 group->grpcfg.engines |= BIT(eng->id); 1059 engines++; 1062 if (!engines) 1202 group->grpcfg.engines = ioread64(idxd->reg_base + grpcfg_offset); 1204 grpcfg_offset, group->grpcfg.engines); [all...] |
H A D | init.c | 232 idxd->engines = kcalloc_node(idxd->max_engines, sizeof(struct idxd_engine *), 234 if (!idxd->engines) 258 idxd->engines[i] = engine; 265 engine = idxd->engines[i]; 337 put_device(engine_confdev(idxd->engines[i])); 417 put_device(engine_confdev(idxd->engines[i])); 495 dev_dbg(dev, "max engines: %u\n", idxd->max_engines);
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/linux-master/drivers/gpu/drm/nouveau/nvif/ |
H A D | fifo.c | 64 device->runlist[i].engines = a->v.runlist[i].data; 82 if (device->runlist[i].engines & engine)
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/linux-master/drivers/crypto/marvell/cesa/ |
H A D | cesa.c | 377 struct mv_cesa_engine *engine = &cesa->engines[idx]; 422 struct mv_cesa_engine *engine = &cesa->engines[idx]; 439 struct mv_cesa_engine *engines; local 470 cesa->engines = devm_kcalloc(dev, caps->nengines, sizeof(*engines), 472 if (!cesa->engines) 490 struct mv_cesa_engine *engine = &cesa->engines[i]; 574 clk_disable_unprepare(cesa->engines[i].zclk); 575 clk_disable_unprepare(cesa->engines[i].clk); 577 if (cesa->engines[ [all...] |
/linux-master/drivers/gpu/drm/xe/ |
H A D | xe_query.c | 187 struct drm_xe_query_engines *engines; local 201 engines = kzalloc(size, GFP_KERNEL); 202 if (!engines) 210 engines->engines[i].instance.engine_class = 212 engines->engines[i].instance.engine_instance = 214 engines->engines[i].instance.gt_id = gt->info.id; 219 engines [all...] |
/linux-master/drivers/gpu/drm/nouveau/include/nvif/ |
H A D | device.h | 14 u64 engines; member in struct:nvif_device::nvif_fifo_runlist
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/linux-master/drivers/gpu/drm/omapdrm/ |
H A D | omap_dmm_tiler.c | 290 if (dmm->engines[i].async) 291 release_engine(&dmm->engines[i]); 293 complete(&dmm->engines[i].compl); 471 * silently fail, leading to leaking DMM engines, which may eventually 472 * lead to deadlock if we run out of DMM engines. 751 kfree(omap_dmm->engines); 885 /* alloc engines */ 886 omap_dmm->engines = kcalloc(omap_dmm->num_engines, 887 sizeof(*omap_dmm->engines), GFP_KERNEL); 888 if (!omap_dmm->engines) { [all...] |
H A D | omap_dmm_priv.h | 164 /* refill engines */ 167 struct refill_engine *engines; member in struct:dmm
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/linux-master/include/uapi/drm/ |
H A D | i915_drm.h | 160 * Different engines serve different roles, and there may be more than one 163 * on a certain subset of engines, or for providing information about that 170 * Render engines support instructions used for 3D, Compute (GPGPU), 181 * Copy engines (also referred to as "blitters") support instructions 184 * Copy engines can perform pre-defined logical or bitwise operations 192 * Video engines (also referred to as "bit stream decode" (BSD) or 201 * Video enhancement engines (also referred to as "vebox") support 209 * Compute engines support a subset of the instructions available 210 * on render engines: compute engines suppor 2304 struct i915_engine_class_instance engines[]; member in struct:i915_context_engines_load_balance 2342 struct i915_engine_class_instance engines[]; member in struct:i915_context_engines_bond 2469 struct i915_engine_class_instance engines[]; member in struct:i915_context_engines_parallel_submit 2544 struct i915_engine_class_instance engines[]; member in struct:i915_context_param_engines 3332 struct drm_i915_engine_info engines[]; member in struct:drm_i915_query_engine_info [all...] |
/linux-master/tools/include/uapi/drm/ |
H A D | i915_drm.h | 160 * Different engines serve different roles, and there may be more than one 163 * on a certain subset of engines, or for providing information about that 170 * Render engines support instructions used for 3D, Compute (GPGPU), 181 * Copy engines (also referred to as "blitters") support instructions 184 * Copy engines can perform pre-defined logical or bitwise operations 192 * Video engines (also referred to as "bit stream decode" (BSD) or 201 * Video enhancement engines (also referred to as "vebox") support 209 * Compute engines support a subset of the instructions available 210 * on render engines: compute engines suppor 2304 struct i915_engine_class_instance engines[]; member in struct:i915_context_engines_load_balance 2342 struct i915_engine_class_instance engines[]; member in struct:i915_context_engines_bond 2469 struct i915_engine_class_instance engines[]; member in struct:i915_context_engines_parallel_submit 2544 struct i915_engine_class_instance engines[]; member in struct:i915_context_param_engines 3332 struct drm_i915_engine_info engines[]; member in struct:drm_i915_query_engine_info [all...] |
/linux-master/drivers/leds/ |
H A D | leds-lp55xx-common.h | 149 * @engines : Engine structure for the device attribute R/W interface 160 struct lp55xx_engine engines[LP55XX_ENGINE_MAX]; member in struct:lp55xx_chip
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/linux-master/drivers/gpu/drm/amd/display/dc/dce/ |
H A D | dce_aux.c | 443 struct dce_aux *aux_engine = ddc->ctx->dc->res_pool->engines[ddc_pin->pin_data->en]; 577 aux_engine = ddc->ctx->dc->res_pool->engines[ddc_pin->pin_data->en]; 623 struct dce_aux *aux_engine = ddc->ctx->dc->res_pool->engines[ddc_pin->pin_data->en]; 716 aux_engine = ddc->ctx->dc->res_pool->engines[ddc_pin->pin_data->en];
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/linux-master/drivers/gpu/drm/amd/display/dc/dce60/ |
H A D | dce60_resource.c | 823 if (pool->base.engines[i] != NULL) 824 dce110_engine_destroy(&pool->base.engines[i]); 1074 pool->base.engines[i] = dce60_aux_engine_create(ctx, i); 1075 if (pool->base.engines[i] == NULL) { 1272 pool->base.engines[i] = dce60_aux_engine_create(ctx, i); 1273 if (pool->base.engines[i] == NULL) { 1466 pool->base.engines[i] = dce60_aux_engine_create(ctx, i); 1467 if (pool->base.engines[i] == NULL) {
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/linux-master/drivers/gpu/drm/amd/display/dc/resource/dce80/ |
H A D | dce80_resource.c | 830 if (pool->base.engines[i] != NULL) 831 dce110_engine_destroy(&pool->base.engines[i]); 1088 pool->base.engines[i] = dce80_aux_engine_create(ctx, i); 1089 if (pool->base.engines[i] == NULL) { 1288 pool->base.engines[i] = dce80_aux_engine_create(ctx, i); 1289 if (pool->base.engines[i] == NULL) { 1485 pool->base.engines[i] = dce80_aux_engine_create(ctx, i); 1486 if (pool->base.engines[i] == NULL) {
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