1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
4 * Author: Rob Clark <rob@ti.com>
5 *         Andy Gross <andy.gross@ti.com>
6 */
7
8#ifndef OMAP_DMM_PRIV_H
9#define OMAP_DMM_PRIV_H
10
11#define DMM_REVISION          0x000
12#define DMM_HWINFO            0x004
13#define DMM_LISA_HWINFO       0x008
14#define DMM_DMM_SYSCONFIG     0x010
15#define DMM_LISA_LOCK         0x01C
16#define DMM_LISA_MAP__0       0x040
17#define DMM_LISA_MAP__1       0x044
18#define DMM_TILER_HWINFO      0x208
19#define DMM_TILER_OR__0       0x220
20#define DMM_TILER_OR__1       0x224
21#define DMM_PAT_HWINFO        0x408
22#define DMM_PAT_GEOMETRY      0x40C
23#define DMM_PAT_CONFIG        0x410
24#define DMM_PAT_VIEW__0       0x420
25#define DMM_PAT_VIEW__1       0x424
26#define DMM_PAT_VIEW_MAP__0   0x440
27#define DMM_PAT_VIEW_MAP_BASE 0x460
28#define DMM_PAT_IRQ_EOI       0x478
29#define DMM_PAT_IRQSTATUS_RAW 0x480
30#define DMM_PAT_IRQSTATUS     0x490
31#define DMM_PAT_IRQENABLE_SET 0x4A0
32#define DMM_PAT_IRQENABLE_CLR 0x4B0
33#define DMM_PAT_STATUS__0     0x4C0
34#define DMM_PAT_STATUS__1     0x4C4
35#define DMM_PAT_STATUS__2     0x4C8
36#define DMM_PAT_STATUS__3     0x4CC
37#define DMM_PAT_DESCR__0      0x500
38#define DMM_PAT_DESCR__1      0x510
39#define DMM_PAT_DESCR__2      0x520
40#define DMM_PAT_DESCR__3      0x530
41#define DMM_PEG_HWINFO        0x608
42#define DMM_PEG_PRIO          0x620
43#define DMM_PEG_PRIO_PAT      0x640
44
45#define DMM_IRQSTAT_DST			(1<<0)
46#define DMM_IRQSTAT_LST			(1<<1)
47#define DMM_IRQSTAT_ERR_INV_DSC		(1<<2)
48#define DMM_IRQSTAT_ERR_INV_DATA	(1<<3)
49#define DMM_IRQSTAT_ERR_UPD_AREA	(1<<4)
50#define DMM_IRQSTAT_ERR_UPD_CTRL	(1<<5)
51#define DMM_IRQSTAT_ERR_UPD_DATA	(1<<6)
52#define DMM_IRQSTAT_ERR_LUT_MISS	(1<<7)
53
54#define DMM_IRQSTAT_ERR_MASK	(DMM_IRQSTAT_ERR_INV_DSC | \
55				DMM_IRQSTAT_ERR_INV_DATA | \
56				DMM_IRQSTAT_ERR_UPD_AREA | \
57				DMM_IRQSTAT_ERR_UPD_CTRL | \
58				DMM_IRQSTAT_ERR_UPD_DATA | \
59				DMM_IRQSTAT_ERR_LUT_MISS)
60
61#define DMM_PATSTATUS_READY		(1<<0)
62#define DMM_PATSTATUS_VALID		(1<<1)
63#define DMM_PATSTATUS_RUN		(1<<2)
64#define DMM_PATSTATUS_DONE		(1<<3)
65#define DMM_PATSTATUS_LINKED		(1<<4)
66#define DMM_PATSTATUS_BYPASSED		(1<<7)
67#define DMM_PATSTATUS_ERR_INV_DESCR	(1<<10)
68#define DMM_PATSTATUS_ERR_INV_DATA	(1<<11)
69#define DMM_PATSTATUS_ERR_UPD_AREA	(1<<12)
70#define DMM_PATSTATUS_ERR_UPD_CTRL	(1<<13)
71#define DMM_PATSTATUS_ERR_UPD_DATA	(1<<14)
72#define DMM_PATSTATUS_ERR_ACCESS	(1<<15)
73
74/* note: don't treat DMM_PATSTATUS_ERR_ACCESS as an error */
75#define DMM_PATSTATUS_ERR	(DMM_PATSTATUS_ERR_INV_DESCR | \
76				DMM_PATSTATUS_ERR_INV_DATA | \
77				DMM_PATSTATUS_ERR_UPD_AREA | \
78				DMM_PATSTATUS_ERR_UPD_CTRL | \
79				DMM_PATSTATUS_ERR_UPD_DATA)
80
81
82
83enum {
84	PAT_STATUS,
85	PAT_DESCR
86};
87
88struct pat_ctrl {
89	u32 start:4;
90	u32 dir:4;
91	u32 lut_id:8;
92	u32 sync:12;
93	u32 ini:4;
94};
95
96struct pat {
97	u32 next_pa;
98	struct pat_area area;
99	struct pat_ctrl ctrl;
100	u32 data_pa;
101};
102
103#define DMM_FIXED_RETRY_COUNT 1000
104
105/* create refill buffer big enough to refill all slots, plus 3 descriptors..
106 * 3 descriptors is probably the worst-case for # of 2d-slices in a 1d area,
107 * but I guess you don't hit that worst case at the same time as full area
108 * refill
109 */
110#define DESCR_SIZE 128
111#define REFILL_BUFFER_SIZE ((4 * 128 * 256) + (3 * DESCR_SIZE))
112
113/* For OMAP5, a fixed offset is added to all Y coordinates for 1D buffers.
114 * This is used in programming to address the upper portion of the LUT
115*/
116#define OMAP5_LUT_OFFSET       128
117
118struct dmm;
119
120struct dmm_txn {
121	void *engine_handle;
122	struct tcm *tcm;
123
124	u8 *current_va;
125	dma_addr_t current_pa;
126
127	struct pat *last_pat;
128};
129
130struct refill_engine {
131	int id;
132	struct dmm *dmm;
133	struct tcm *tcm;
134
135	u8 *refill_va;
136	dma_addr_t refill_pa;
137
138	/* only one trans per engine for now */
139	struct dmm_txn txn;
140
141	bool async;
142
143	struct completion compl;
144
145	struct list_head idle_node;
146};
147
148struct dmm_platform_data {
149	u32 cpu_cache_flags;
150};
151
152struct dmm {
153	struct device *dev;
154	dma_addr_t phys_base;
155	void __iomem *base;
156	int irq;
157
158	struct page *dummy_page;
159	dma_addr_t dummy_pa;
160
161	void *refill_va;
162	dma_addr_t refill_pa;
163
164	/* refill engines */
165	wait_queue_head_t engine_queue;
166	struct list_head idle_head;
167	struct refill_engine *engines;
168	int num_engines;
169	atomic_t engine_counter;
170
171	/* container information */
172	int container_width;
173	int container_height;
174	int lut_width;
175	int lut_height;
176	int num_lut;
177
178	/* array of LUT - TCM containers */
179	struct tcm **tcm;
180
181	/* allocation list and lock */
182	struct list_head alloc_head;
183
184	const struct dmm_platform_data *plat_data;
185
186	bool dmm_workaround;
187	spinlock_t wa_lock;
188	u32 *wa_dma_data;
189	dma_addr_t wa_dma_handle;
190	struct dma_chan *wa_dma_chan;
191};
192
193#endif
194