uapi/drm/i915_drm.h

160  * Different engines serve different roles, and there may be more than one
163  * on a certain subset of engines, or for providing information about that
170 	 * Render engines support instructions used for 3D, Compute (GPGPU),
181 	 * Copy engines (also referred to as "blitters") support instructions
184 	 * Copy engines can perform pre-defined logical or bitwise operations
192 	 * Video engines (also referred to as "bit stream decode" (BSD) or
201 	 * Video enhancement engines (also referred to as "vebox") support
209 	 * Compute engines support a subset of the instructions available
210 	 * on render engines:  compute engines support Compute (GPGPU) and
728  * value reports the support of context isolation for individual engines by
1278  * clients or engines (i.e. suballocating objects), the implicit tracking
1603 	 * conditions which prevent the report of which engines are busy from
1605 	 * object is idle, the result of the ioctl, that all engines are idle,
1618 	 * The high word (bits 16:31) are a bitmask of which engines classes
1619 	 * are currently reading from the object. Multiple engines may be
1625 	 * Some hardware may have parallel execution engines, e.g. multiple
1626 	 * media engines, which are mapped to the same class identifier and so
1631 	 * the object is idle or busy. The report of which engines are busy
1700 	 * Special GPU caching mode which is coherent with the scanout engines.
2046  * Bind this context to operate on this subset of available engines. Henceforth,
2048  * an index into this array of engines; I915_EXEC_DEFAULT selecting engine[0]
2056  * Setting the number of engines bound to the context to 0, by passing a zero
2168  * Not all GPUs or engines support this functionality in which case an error
2220  * physical engines, submit a batch buffer, and let the driver execute it on any
2224  * class engine, like for example GT3+ Skylake parts with their two VCS engines.
2226  * For instance userspace can enumerate all engines of a certain class using the
2242  * 		.engines = { { I915_ENGINE_CLASS_VIDEO, 0 },
2245  * 	I915_DEFINE_CONTEXT_PARAM_ENGINES(engines, 1) = {
2246  * 		.engines = { { I915_ENGINE_CLASS_INVALID,
2256  * 			.value = to_user_pointer(&engines),
2257  * 			.size = sizeof(engines),
2282  * Enable load balancing across this set of engines.
2285  * used will proxy the execbuffer request onto one of the set of engines
2288  * The set of engines must be compatible (e.g. the same HW class) as they
2292  * the backing engines (bypassing the load balancing proxy), the context must
2293  * be defined to use a single timeline for all engines.
2304 	struct i915_engine_class_instance engines[];
2313 	struct i915_engine_class_instance engines[N__]; \
2321  * All engines are equal, but some are more equal than others. Given
2323  * a request on a given subset of engines in parallel to a request on a
2324  * specific engine. We enable this selection of engines within a virtual
2336 	__u16 virtual_index; /* index of virtual engine in ctx->engines[] */
2342 	struct i915_engine_class_instance engines[];
2352 	struct i915_engine_class_instance engines[N__]; \
2392  *		     engines=CS[0],CS[1])
2400  *		     engines=CS[0],CS[2],CS[1],CS[3])
2406  *	This can be thought of as two virtual engines, each containing two
2407  *	engines thereby making a 2D array. However, there are bonds tying the
2419  *		     engines=CS[0],CS[1],CS[1],CS[3])
2464 	 * @engines: 2-d array of engine instances to configure parallel engine
2469 	struct i915_engine_class_instance engines[];
2481 	struct i915_engine_class_instance engines[N__]; \
2487  * Context engine map is a new way of addressing engines when submitting batch-
2491  * To use it created GEM contexts need to be configured with a list of engines
2503  * 	I915_DEFINE_CONTEXT_PARAM_ENGINES(engines, 2) = {
2504  * 		.engines = { { I915_ENGINE_CLASS_RENDER, 0 },
2513  * 			.value = to_user_pointer(&engines),
2514  * 			.size = sizeof(engines),
2524  * 	// We have now created a GEM context with two engines in the map:
2525  * 	// Index 0 points to rcs0 while index 1 points to bcs0. Other engines
2544 	struct i915_engine_class_instance engines[];
2549 	struct i915_engine_class_instance engines[N__]; \
2816 	 * Multiple engines may be mapped to the same OA unit. The OA unit is
3221  * Engine discovery uAPI is a way of enumerating physical engines present in a
3227  * started to establish a pattern of having multiple engines of a same class,
3233  * Example for getting the list of engines:
3248  * 	// enough to hold our array of engines. The kernel will fill out the
3260  * 	// blob, which the kernel can then populate with info on all engines.
3268  * 		struct drm_i915_engine_info einfo = info->engines[i];
3276  * Each of the enumerated engines, apart from being defined by its class and
3280  * For instance video engines which support HEVC encoding will have the
3284  * of addressing engines when submitting batch buffers using contexts with
3321  * Engine info query enumerates all engines known to the driver by filling in
3331 	/** @engines: Marker for drm_i915_engine_info structures. */
3332 	struct drm_i915_engine_info engines[];