Searched refs:dsc_cfg (Results 1 - 25 of 29) sorted by relevance

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/linux-master/drivers/gpu/drm/amd/display/dc/dsc/
H A Drc_calc_dpi.c71 static void copy_rc_to_cfg(struct drm_dsc_config *dsc_cfg, const struct rc_params *rc) argument
75 dsc_cfg->rc_quant_incr_limit0 = rc->rc_quant_incr_limit0;
76 dsc_cfg->rc_quant_incr_limit1 = rc->rc_quant_incr_limit1;
77 dsc_cfg->initial_offset = rc->initial_fullness_offset;
78 dsc_cfg->initial_xmit_delay = rc->initial_xmit_delay;
79 dsc_cfg->first_line_bpg_offset = rc->first_line_bpg_offset;
80 dsc_cfg->second_line_bpg_offset = rc->second_line_bpg_offset;
81 dsc_cfg->flatness_min_qp = rc->flatness_min_qp;
82 dsc_cfg->flatness_max_qp = rc->flatness_max_qp;
84 dsc_cfg
103 struct drm_dsc_config dsc_cfg; local
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H A Ddsc.h102 bool (*dsc_validate_stream)(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg);
103 void (*dsc_set_config)(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg,
105 bool (*dsc_get_packed_pps)(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg,
H A Ddc_dsc.c96 timing->dsc_cfg.bits_per_pixel,
97 timing->dsc_cfg.num_slices_h,
98 timing->dsc_cfg.is_dp);
184 struct dc_dsc_config *dsc_cfg);
854 * dsc_cfg - DSC configuration to use if it was possible to come up with
857 * dsc_cfg.bits_per_pixel (in U6.4 format) by pixel rate, e.g.
859 * dsc_stream_bitrate_kbps = (int)ceil(timing->pix_clk_khz * dsc_cfg.bits_per_pixel / 16.0);
868 struct dc_dsc_config *dsc_cfg)
884 memset(dsc_cfg, 0, sizeof(struct dc_dsc_config));
906 dsc_cfg
861 setup_dsc_config( const struct dsc_dec_dpcd_caps *dsc_sink_caps, const struct dsc_enc_caps *dsc_enc_caps, int target_bandwidth_kbps, const struct dc_crtc_timing *timing, const struct dc_dsc_config_options *options, const enum dc_link_encoding_format link_encoding, struct dc_dsc_config *dsc_cfg) argument
1090 dc_dsc_compute_config( const struct display_stream_compressor *dsc, const struct dsc_dec_dpcd_caps *dsc_sink_caps, const struct dc_dsc_config_options *options, uint32_t target_bandwidth_kbps, const struct dc_crtc_timing *timing, const enum dc_link_encoding_format link_encoding, struct dc_dsc_config *dsc_cfg) argument
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/linux-master/drivers/gpu/drm/amd/display/dc/dsc/dcn20/
H A Ddcn20_dsc.c37 static bool dsc2_validate_stream(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg);
38 static void dsc2_set_config(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg,
174 static bool dsc2_validate_stream(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg) argument
179 if (dsc_cfg->pic_width > dsc20->max_image_width)
182 return dsc_prepare_config(dsc_cfg, &dsc20->reg_vals, &dsc_optc_cfg);
197 static void dsc2_set_config(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg, argument
204 dsc_config_log(dsc, dsc_cfg);
205 is_config_ok = dsc_prepare_config(dsc_cfg, &dsc20->reg_vals, dsc_optc_cfg);
213 bool dsc2_get_packed_pps(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg, uint8_t *dsc_packed_pps) argument
223 dsc_config_log(dsc, dsc_cfg);
374 dsc_prepare_config(const struct dsc_config *dsc_cfg, struct dsc_reg_values *dsc_reg_vals, struct dsc_optc_config *dsc_optc_cfg) argument
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H A Ddcn20_dsc.h561 bool dsc_prepare_config(const struct dsc_config *dsc_cfg,
585 const struct dsc_config *dsc_cfg,
/linux-master/drivers/gpu/drm/display/
H A Ddrm_dsc_helper.c86 * @dsc_cfg:
98 const struct drm_dsc_config *dsc_cfg)
110 dsc_cfg->dsc_version_minor |
111 dsc_cfg->dsc_version_major << DSC_PPS_VERSION_MAJOR_SHIFT;
117 dsc_cfg->line_buf_depth |
118 dsc_cfg->bits_per_component << DSC_PPS_BPC_SHIFT;
122 ((dsc_cfg->bits_per_pixel & DSC_PPS_BPP_HIGH_MASK) >>
124 dsc_cfg->vbr_enable << DSC_PPS_VBR_EN_SHIFT |
125 dsc_cfg->simple_422 << DSC_PPS_SIMPLE422_SHIFT |
126 dsc_cfg
97 drm_dsc_pps_payload_pack(struct drm_dsc_picture_parameter_set *pps_payload, const struct drm_dsc_config *dsc_cfg) argument
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/linux-master/include/drm/display/
H A Ddrm_dsc_helper.h23 const struct drm_dsc_config *dsc_cfg);
/linux-master/drivers/gpu/drm/amd/display/dc/hwss/dcn314/
H A Ddcn314_hwseq.c84 struct dsc_config dsc_cfg; local
89 dsc_cfg.pic_width = (stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right) / opp_cnt;
90 dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top + stream->timing.v_border_bottom;
91 dsc_cfg.pixel_encoding = stream->timing.pixel_encoding;
92 dsc_cfg.color_depth = stream->timing.display_color_depth;
93 dsc_cfg.is_odm = pipe_ctx->next_odm_pipe ? true : false;
94 dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg;
95 ASSERT(dsc_cfg.dc_dsc_cfg.num_slices_h % opp_cnt == 0);
96 dsc_cfg
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/linux-master/drivers/gpu/drm/amd/display/dc/
H A Ddc_dsc.h86 struct dc_dsc_config *dsc_cfg);
H A Ddc_hw_types.h952 struct dc_dsc_config dsc_cfg; member in struct:dc_crtc_timing
/linux-master/drivers/gpu/drm/amd/display/dc/core/
H A Ddc_stream.c108 memset(&stream->timing.dsc_cfg, 0, sizeof(stream->timing.dsc_cfg));
109 stream->timing.dsc_cfg.num_slices_h = 0;
110 stream->timing.dsc_cfg.num_slices_v = 0;
111 stream->timing.dsc_cfg.bits_per_pixel = 128;
112 stream->timing.dsc_cfg.block_pred_enable = 1;
113 stream->timing.dsc_cfg.linebuf_depth = 9;
114 stream->timing.dsc_cfg.version_minor = 2;
115 stream->timing.dsc_cfg.ycbcr422_simple = 0;
782 stream->timing.dsc_cfg
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/linux-master/drivers/gpu/drm/amd/display/dc/link/
H A Dlink_dpms.c805 struct dsc_config dsc_cfg; local
810 dsc_cfg.pic_width = (stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right) / opp_cnt;
811 dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top + stream->timing.v_border_bottom;
812 dsc_cfg.pixel_encoding = stream->timing.pixel_encoding;
813 dsc_cfg.color_depth = stream->timing.display_color_depth;
814 dsc_cfg.is_odm = pipe_ctx->next_odm_pipe ? true : false;
815 dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg;
816 ASSERT(dsc_cfg.dc_dsc_cfg.num_slices_h % opp_cnt == 0);
817 dsc_cfg
913 struct dsc_config dsc_cfg; local
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H A Dlink_validation.c128 if (timing->flags.DSC && !timing->dsc_cfg.is_frl)
/linux-master/drivers/gpu/drm/amd/display/dc/hwss/dcn32/
H A Ddcn32_hwseq.c994 struct dsc_config dsc_cfg; local
999 dsc_cfg.pic_width = (stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right) / opp_cnt;
1000 dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top + stream->timing.v_border_bottom;
1001 dsc_cfg.pixel_encoding = stream->timing.pixel_encoding;
1002 dsc_cfg.color_depth = stream->timing.display_color_depth;
1003 dsc_cfg.is_odm = pipe_ctx->next_odm_pipe ? true : false;
1004 dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg;
1005 ASSERT(dsc_cfg.dc_dsc_cfg.num_slices_h % opp_cnt == 0);
1006 dsc_cfg
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/linux-master/drivers/gpu/drm/amd/display/dc/hwss/dcn35/
H A Ddcn35_hwseq.c375 struct dsc_config dsc_cfg; local
380 dsc_cfg.pic_width = (stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right) / opp_cnt;
381 dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top + stream->timing.v_border_bottom;
382 dsc_cfg.pixel_encoding = stream->timing.pixel_encoding;
383 dsc_cfg.color_depth = stream->timing.display_color_depth;
384 dsc_cfg.is_odm = pipe_ctx->next_odm_pipe ? true : false;
385 dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg;
386 ASSERT(dsc_cfg.dc_dsc_cfg.num_slices_h % opp_cnt == 0);
387 dsc_cfg
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/linux-master/drivers/gpu/drm/amd/display/amdgpu_dm/
H A Damdgpu_dm_mst_types.c831 memset(&params[i].timing->dsc_cfg, 0, sizeof(params[i].timing->dsc_cfg));
839 &params[i].timing->dsc_cfg)) {
843 params[i].timing->dsc_cfg.bits_per_pixel = params[i].bpp_overwrite;
845 params[i].timing->dsc_cfg.bits_per_pixel = vars[i + k].bpp_x16;
848 params[i].timing->dsc_cfg.num_slices_h = params[i].num_slices_h;
851 params[i].timing->dsc_cfg.num_slices_v = params[i].num_slices_v;
855 params[i].timing->dsc_cfg.mst_pbn = vars[i + k].pbn;
868 params[i].timing->dsc_cfg.bits_per_pixel,
1645 &stream->timing.dsc_cfg)) {
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H A Damdgpu_dm.c6039 struct dc_dsc_config dsc_cfg = {0}; local
6071 &dsc_cfg)) {
6072 stream->timing.dsc_cfg = dsc_cfg;
6074 stream->timing.dsc_cfg.bits_per_pixel = edp_max_bpp_x16;
6086 &dsc_cfg)) {
6087 stream->timing.dsc_cfg = dsc_cfg;
6130 &stream->timing.dsc_cfg)) {
6149 &stream->timing.dsc_cfg)) {
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/linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn20/
H A Ddcn20_resource.c1669 struct dsc_config dsc_cfg; local
1680 dsc_cfg.pic_width = (stream->timing.h_addressable + stream->timing.h_border_left
1682 dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top
1684 dsc_cfg.pixel_encoding = stream->timing.pixel_encoding;
1685 dsc_cfg.color_depth = stream->timing.display_color_depth;
1686 dsc_cfg.is_odm = pipe_ctx->next_odm_pipe ? true : false;
1687 dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg;
1688 dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt;
1690 if (!pipe_ctx->stream_res.dsc->funcs->dsc_validate_stream(pipe_ctx->stream_res.dsc, &dsc_cfg))
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/linux-master/drivers/gpu/drm/amd/display/dc/dcn32/
H A Ddcn32_dio_stream_encoder.c240 && !timing->dsc_cfg.ycbcr422_simple);
/linux-master/drivers/gpu/drm/amd/display/dc/dcn314/
H A Ddcn314_dio_stream_encoder.c273 && !timing->dsc_cfg.ycbcr422_simple);
/linux-master/drivers/gpu/drm/amd/display/dc/dcn35/
H A Ddcn35_dio_stream_encoder.c272 && !timing->dsc_cfg.ycbcr422_simple);
/linux-master/drivers/gpu/drm/amd/display/modules/power/
H A Dpower_helpers.c953 !stream->timing.dsc_cfg.num_slices_v)
959 if (stream->timing.dsc_cfg.num_slices_v == 0)
962 slice_height = pic_height / stream->timing.dsc_cfg.num_slices_v;
/linux-master/drivers/gpu/drm/amd/display/dc/dcn20/
H A Ddcn20_stream_encoder.c464 && !timing->dsc_cfg.ycbcr422_simple);
/linux-master/drivers/gpu/drm/amd/display/dc/dcn31/
H A Ddcn31_dccg.c566 && !params->timing->dsc_cfg.ycbcr422_simple)) {
/linux-master/drivers/gpu/drm/amd/display/dc/optc/dcn10/
H A Ddcn10_optc.c1618 && !timing->dsc_cfg.ycbcr422_simple);

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