Searched refs:dpm_table (Results 1 - 24 of 24) sorted by relevance

/linux-master/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
H A Dvega12_hwmgr.c601 struct vega12_single_dpm_table *dpm_table, PPCLK_e clk_id)
611 dpm_table->count = num_of_levels;
618 dpm_table->dpm_levels[i].value = clk;
619 dpm_table->dpm_levels[i].enabled = true;
638 struct vega12_single_dpm_table *dpm_table; local
641 memset(&data->dpm_table, 0, sizeof(data->dpm_table));
644 dpm_table = &(data->dpm_table.soc_table);
646 ret = vega12_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_SOCCL
600 vega12_setup_single_dpm_table(struct pp_hwmgr *hwmgr, struct vega12_single_dpm_table *dpm_table, PPCLK_e clk_id) argument
1851 struct vega12_single_dpm_table *dpm_table; local
1884 struct vega12_single_dpm_table *dpm_table; local
1911 struct vega12_single_dpm_table *dpm_table; local
1939 struct vega12_single_dpm_table *dpm_table; local
2351 struct vega12_single_dpm_table *dpm_table; local
2508 vega12_set_uclk_to_highest_dpm_level(struct pp_hwmgr *hwmgr, struct vega12_single_dpm_table *dpm_table) argument
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H A Dvega20_hwmgr.c558 struct vega20_single_dpm_table *dpm_table, PPCLK_e clk_id)
568 dpm_table->count = num_of_levels;
575 dpm_table->dpm_levels[i].value = clk;
576 dpm_table->dpm_levels[i].enabled = true;
586 struct vega20_single_dpm_table *dpm_table; local
589 dpm_table = &(data->dpm_table.gfx_table);
591 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_GFXCLK);
596 dpm_table->count = 1;
597 dpm_table
557 vega20_setup_single_dpm_table(struct pp_hwmgr *hwmgr, struct vega20_single_dpm_table *dpm_table, PPCLK_e clk_id) argument
607 struct vega20_single_dpm_table *dpm_table; local
636 struct vega20_single_dpm_table *dpm_table; local
2341 struct vega20_single_dpm_table *dpm_table = local
2808 struct vega20_single_dpm_table *dpm_table = &(data->dpm_table.gfx_table); local
2836 struct vega20_single_dpm_table *dpm_table = &(data->dpm_table.mem_table); local
2861 struct vega20_single_dpm_table *dpm_table = &(data->dpm_table.dcef_table); local
2883 struct vega20_single_dpm_table *dpm_table = &(data->dpm_table.soc_table); local
3573 vega20_set_uclk_to_highest_dpm_level(struct pp_hwmgr *hwmgr, struct vega20_single_dpm_table *dpm_table) argument
3602 struct vega20_single_dpm_table *dpm_table = &(data->dpm_table.fclk_table); local
3731 struct vega20_single_dpm_table *dpm_table; local
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H A Dvega10_hwmgr.c1230 struct vega10_single_dpm_table *dpm_table,
1235 dpm_table->count = 0;
1238 if (i == 0 || dpm_table->dpm_levels[dpm_table->count - 1].value <=
1240 dpm_table->dpm_levels[dpm_table->count].value =
1242 dpm_table->dpm_levels[dpm_table->count].enabled = true;
1243 dpm_table->count++;
1250 struct vega10_pcie_table *pcie_table = &(data->dpm_table
1229 vega10_setup_default_single_dpm_table(struct pp_hwmgr *hwmgr, struct vega10_single_dpm_table *dpm_table, struct phm_ppt_v1_clock_voltage_dependency_table *dep_table) argument
1301 struct vega10_single_dpm_table *dpm_table; local
1722 struct vega10_single_dpm_table *dpm_table = &(data->dpm_table.gfx_table); local
1871 struct vega10_single_dpm_table *dpm_table = local
2009 struct vega10_single_dpm_table *dpm_table = &(data->dpm_table.eclk_table); local
3460 struct vega10_dpm_table *dpm_table = &data->dpm_table; local
3500 vega10_trim_single_dpm_states(struct pp_hwmgr *hwmgr, struct vega10_single_dpm_table *dpm_table, uint32_t low_limit, uint32_t high_limit) argument
3516 vega10_trim_single_dpm_states_with_mask(struct pp_hwmgr *hwmgr, struct vega10_single_dpm_table *dpm_table, uint32_t low_limit, uint32_t high_limit, uint32_t disable_dpm_mask) argument
3921 struct vega10_dpm_table *dpm_table = &data->dpm_table; local
4063 struct vega10_single_dpm_table *dpm_table = local
5469 struct vega10_single_dpm_table *dpm_table = &data->golden_dpm_table.mem_table; local
5540 struct vega10_single_dpm_table *dpm_table; local
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H A Dsmu7_hwmgr.c662 phm_reset_single_dpm_table(&data->dpm_table.pcie_speed_table,
673 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, i - 1,
679 data->dpm_table.pcie_speed_table.count = max_entry - 1;
683 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 0,
688 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 1,
693 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 2,
698 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 3,
703 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 4,
708 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 5,
714 data->dpm_table
4137 struct smu7_dpm_table *dpm_table = &data->dpm_table; local
4247 struct smu7_dpm_table *dpm_table = &data->dpm_table; local
4290 smu7_trim_single_dpm_states(struct pp_hwmgr *hwmgr, struct smu7_single_dpm_table *dpm_table, uint32_t low_limit, uint32_t high_limit) argument
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H A Dsmu_helper.c351 struct vi_dpm_table *dpm_table = (struct vi_dpm_table *)table; local
353 dpm_table->count = count > max ? max : count;
355 for (i = 0; i < dpm_table->count; i++)
356 dpm_table->dpm_level[i].enabled = false;
366 struct vi_dpm_table *dpm_table = (struct vi_dpm_table *)table; local
367 dpm_table->dpm_level[index].value = pcie_gen;
368 dpm_table->dpm_level[index].param1 = pcie_lanes;
369 dpm_table->dpm_level[index].enabled = 1;
376 struct vi_dpm_table *dpm_table = (struct vi_dpm_table *)table; local
378 for (i = dpm_table
448 struct vi_dpm_table *dpm_table = (struct vi_dpm_table *)table; local
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H A Dsmu7_hwmgr.h214 struct smu7_dpm_table dpm_table; member in struct:smu7_hwmgr
H A Dvega10_hwmgr.h311 struct vega10_dpm_table dpm_table; member in struct:vega10_hwmgr
H A Dvega12_hwmgr.h313 struct vega12_dpm_table dpm_table; member in struct:vega12_hwmgr
H A Dvega20_hwmgr.h435 struct vega20_dpm_table dpm_table; member in struct:vega20_hwmgr
/linux-master/drivers/gpu/drm/amd/pm/swsmu/smu13/
H A Dsmu_v13_0_7_ppt.c579 struct smu_13_0_dpm_table *dpm_table; local
585 dpm_table = &dpm_context->dpm_tables.soc_table;
589 dpm_table);
593 dpm_table->count = 1;
594 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100;
595 dpm_table->dpm_levels[0].enabled = true;
596 dpm_table->min = dpm_table->dpm_levels[0].value;
597 dpm_table->max = dpm_table
895 struct smu_13_0_dpm_table *dpm_table; local
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H A Daldebaran_ppt.c312 struct smu_13_0_dpm_table *dpm_table = NULL; local
317 dpm_table = &dpm_context->dpm_tables.soc_table;
321 dpm_table);
325 dpm_table->count = 1;
326 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100;
327 dpm_table->dpm_levels[0].enabled = true;
328 dpm_table->min = dpm_table->dpm_levels[0].value;
329 dpm_table->max = dpm_table
550 aldebaran_get_clk_table(struct smu_context *smu, struct pp_clock_levels_with_latency *clocks, struct smu_13_0_dpm_table *dpm_table) argument
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H A Dsmu_v13_0_0_ppt.c572 struct smu_13_0_dpm_table *dpm_table; local
578 dpm_table = &dpm_context->dpm_tables.soc_table;
582 dpm_table);
586 dpm_table->count = 1;
587 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100;
588 dpm_table->dpm_levels[0].enabled = true;
589 dpm_table->min = dpm_table->dpm_levels[0].value;
590 dpm_table->max = dpm_table
906 struct smu_13_0_dpm_table *dpm_table; local
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H A Dsmu_v13_0_6_ppt.c259 struct smu_13_0_dpm_table *dpm_table; member in struct:smu_v13_0_6_dpm_map
643 struct smu_13_0_dpm_table *dpm_table = NULL; local
669 dpm_table = &dpm_context->dpm_tables.gfx_table;
679 dpm_table->count = 2;
680 dpm_table->dpm_levels[0].value = gfxclkmin;
681 dpm_table->dpm_levels[0].enabled = true;
682 dpm_table->dpm_levels[1].value = gfxclkmax;
683 dpm_table->dpm_levels[1].enabled = true;
684 dpm_table->min = dpm_table
793 smu_v13_0_6_get_clk_table(struct smu_context *smu, struct pp_clock_levels_with_latency *clocks, struct smu_13_0_dpm_table *dpm_table) argument
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/linux-master/drivers/gpu/drm/amd/pm/powerplay/smumgr/
H A Dfiji_smumgr.c490 SMU73_Discrete_DpmTable *dpm_table = &(smu_data->smc_state_table); local
502 dpm_table->DefaultTdp = PP_HOST_TO_SMC_US(
504 dpm_table->TargetTdp = PP_HOST_TO_SMC_US(
511 dpm_table->GpuTjMax = (uint8_t)(cac_dtp_table->usTargetOperatingTemp);
512 dpm_table->GpuTjHyst = 8;
514 dpm_table->DTEAmbientTempBase = defaults->DTEAmbientTempBase;
517 dpm_table->TemperatureLimitEdge = PP_HOST_TO_SMC_US(
519 dpm_table->TemperatureLimitHotspot = PP_HOST_TO_SMC_US(
521 dpm_table->TemperatureLimitLiquid1 = PP_HOST_TO_SMC_US(
523 dpm_table
830 struct smu7_dpm_table *dpm_table = &data->dpm_table; local
1004 struct smu7_dpm_table *dpm_table = &data->dpm_table; local
1223 struct smu7_dpm_table *dpm_table = &data->dpm_table; local
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H A Diceland_smumgr.c767 struct smu7_dpm_table *dpm_table = &data->dpm_table; local
771 /* Index (dpm_table->pcie_speed_table.count) is reserved for PCIE boot level. */
772 for (i = 0; i <= dpm_table->pcie_speed_table.count; i++) {
774 (uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value;
776 (uint8_t)encode_pcie_lane_width(dpm_table->pcie_speed_table.dpm_levels[i].param1);
788 (uint8_t)dpm_table->pcie_speed_table.count;
790 phm_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table);
963 struct smu7_dpm_table *dpm_table = &data->dpm_table; local
1350 struct smu7_dpm_table *dpm_table = &data->dpm_table; local
1854 SMU71_Discrete_DpmTable *dpm_table = &(smu_data->smc_state_table); local
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H A Dvegam_smumgr.c574 struct smu7_dpm_table *dpm_table = &data->dpm_table; local
577 /* Index (dpm_table->pcie_speed_table.count)
579 for (i = 0; i <= dpm_table->pcie_speed_table.count; i++) {
581 (uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value;
583 dpm_table->pcie_speed_table.dpm_levels[i].param1);
591 (uint8_t)dpm_table->pcie_speed_table.count;
595 phm_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table);
868 struct smu7_dpm_table *dpm_table = &hw_data->dpm_table; local
1038 struct smu7_dpm_table *dpm_table = &hw_data->dpm_table; local
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H A Dci_smumgr.c476 struct smu7_dpm_table *dpm_table = &data->dpm_table; local
486 for (i = 0; i < dpm_table->sclk_table.count; i++) {
488 dpm_table->sclk_table.dpm_levels[i].value,
494 if (i == (dpm_table->sclk_table.count - 1))
501 smu_data->smc_state_table.GraphicsDpmLevelCount = (u8)dpm_table->sclk_table.count;
503 phm_get_dpm_level_enable_mask_value(&dpm_table->sclk_table);
720 SMU7_Discrete_DpmTable *dpm_table = &(smu_data->smc_state_table); local
726 dpm_table->DefaultTdp = PP_HOST_TO_SMC_US((uint16_t)(cac_dtp_table->usTDP * 256));
727 dpm_table
1000 struct smu7_dpm_table *dpm_table = &data->dpm_table; local
1304 struct smu7_dpm_table *dpm_table = &data->dpm_table; local
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H A Dtonga_smumgr.c510 struct smu7_dpm_table *dpm_table = &data->dpm_table; local
514 /* Index (dpm_table->pcie_speed_table.count) is reserved for PCIE boot level. */
515 for (i = 0; i <= dpm_table->pcie_speed_table.count; i++) {
517 (uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value;
519 (uint8_t)encode_pcie_lane_width(dpm_table->pcie_speed_table.dpm_levels[i].param1);
531 (uint8_t)dpm_table->pcie_speed_table.count;
533 phm_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table);
691 struct smu7_dpm_table *dpm_table = &data->dpm_table; local
1091 struct smu7_dpm_table *dpm_table = &data->dpm_table; local
1831 SMU72_Discrete_DpmTable *dpm_table = &(smu_data->smc_state_table); local
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H A Dpolaris10_smumgr.c820 struct smu7_dpm_table *dpm_table = &data->dpm_table; local
823 /* Index (dpm_table->pcie_speed_table.count)
825 for (i = 0; i <= dpm_table->pcie_speed_table.count; i++) {
827 (uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value;
829 dpm_table->pcie_speed_table.dpm_levels[i].param1);
837 (uint8_t)dpm_table->pcie_speed_table.count;
841 phm_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table);
1040 struct smu7_dpm_table *dpm_table = &hw_data->dpm_table; local
1212 struct smu7_dpm_table *dpm_table = &hw_data->dpm_table; local
[all...]
/linux-master/drivers/gpu/drm/amd/pm/swsmu/smu11/
H A Dnavi10_ppt.c970 struct smu_11_0_dpm_table *dpm_table; local
974 dpm_table = &dpm_context->dpm_tables.soc_table;
978 dpm_table);
981 dpm_table->is_fine_grained =
984 dpm_table->count = 1;
985 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100;
986 dpm_table->dpm_levels[0].enabled = true;
987 dpm_table->min = dpm_table->dpm_levels[0].value;
988 dpm_table
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H A Darcturus_ppt.c331 struct smu_11_0_dpm_table *dpm_table = NULL; local
335 dpm_table = &dpm_context->dpm_tables.soc_table;
339 dpm_table);
342 dpm_table->is_fine_grained =
345 dpm_table->count = 1;
346 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100;
347 dpm_table->dpm_levels[0].enabled = true;
348 dpm_table->min = dpm_table->dpm_levels[0].value;
349 dpm_table
572 arcturus_get_clk_table(struct smu_context *smu, struct pp_clock_levels_with_latency *clocks, struct smu_11_0_dpm_table *dpm_table) argument
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H A Dsienna_cichlid_ppt.c957 struct smu_11_0_dpm_table *dpm_table; local
963 dpm_table = &dpm_context->dpm_tables.soc_table;
968 dpm_table);
971 dpm_table->is_fine_grained =
974 dpm_table->count = 1;
975 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100;
976 dpm_table->dpm_levels[0].enabled = true;
977 dpm_table->min = dpm_table->dpm_levels[0].value;
978 dpm_table
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/linux-master/drivers/gpu/drm/radeon/
H A Dci_dpm.c405 SMU7_Discrete_DpmTable *dpm_table = &pi->smc_state_table; local
413 dpm_table->DefaultTdp = cac_tdp_table->tdp * 256;
414 dpm_table->TargetTdp = cac_tdp_table->configurable_tdp * 256;
416 dpm_table->DTETjOffset = (u8)pi->dte_tj_offset;
417 dpm_table->GpuTjMax =
419 dpm_table->GpuTjHyst = 8;
421 dpm_table->DTEAmbientTempBase = pt_defaults->dte_ambient_temp_base;
424 dpm_table->PPM_PkgPwrLimit = cpu_to_be16((u16)ppm->dgpu_tdp * 256 / 1000);
425 dpm_table->PPM_TemperatureLimit = cpu_to_be16((u16)ppm->tj_max * 256);
427 dpm_table
2566 ci_get_dpm_level_enable_mask_value(struct ci_single_dpm_table *dpm_table) argument
2586 struct ci_dpm_table *dpm_table = &pi->dpm_table; local
3235 struct ci_dpm_table *dpm_table = &pi->dpm_table; local
3282 struct ci_dpm_table *dpm_table = &pi->dpm_table; local
3330 ci_reset_single_dpm_table(struct radeon_device *rdev, struct ci_single_dpm_table *dpm_table, u32 count) argument
3341 ci_setup_pcie_table_entry(struct ci_single_dpm_table *dpm_table, u32 index, u32 pcie_gen, u32 pcie_lanes) argument
3659 ci_trim_single_dpm_states(struct radeon_device *rdev, struct ci_single_dpm_table *dpm_table, u32 low_limit, u32 high_limit) argument
3860 struct ci_dpm_table *dpm_table = &pi->dpm_table; local
5644 SMU7_Discrete_DpmTable *dpm_table; local
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H A Dci_dpm.h193 struct ci_dpm_table dpm_table; member in struct:ci_power_info

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