Searched refs:dcn_reg_offsets (Results 1 - 13 of 13) sorted by relevance

/linux-master/drivers/gpu/drm/amd/display/dmub/src/
H A Ddmub_dcn351.c11 #define BASE_INNER(seg) ctx->dcn_reg_offsets[seg]
H A Ddmub_dcn32.c35 #define BASE_INNER(seg) ctx->dcn_reg_offsets[seg]
H A Ddmub_dcn35.c35 #define BASE_INNER(seg) ctx->dcn_reg_offsets[seg]
/linux-master/drivers/gpu/drm/amd/display/dc/irq/dcn35/
H A Dirq_service_dcn35.c193 #define BASE_INNER(seg) ctx->dcn_reg_offsets[seg]
/linux-master/drivers/gpu/drm/amd/display/dc/irq/dcn351/
H A Dirq_service_dcn351.c172 #define BASE_INNER(seg) ctx->dcn_reg_offsets[seg]
/linux-master/drivers/gpu/drm/amd/display/dc/
H A Ddc_types.h797 uint32_t *dcn_reg_offsets; member in struct:dc_context
H A Ddc.h1057 uint32_t *dcn_reg_offsets; member in struct:dc
1120 uint32_t *dcn_reg_offsets; member in struct:dc_init_data
/linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn32/
H A Ddcn32_resource.c112 #define BASE_INNER(seg) ctx->dcn_reg_offsets[seg]
198 (ctx->dcn_reg_offsets[reg ## reg_name ## _BASE_IDX] + reg ## reg_name)
1097 generic_reg_get(ctx, ctx->dcn_reg_offsets[regDC_PINSTRAPS_BASE_IDX] + regDC_PINSTRAPS,
/linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn321/
H A Ddcn321_resource.c113 #define BASE_INNER(seg) ctx->dcn_reg_offsets[seg]
198 (ctx->dcn_reg_offsets[reg ## reg_name ## _BASE_IDX] + reg ## reg_name)
1081 generic_reg_get(ctx, ctx->dcn_reg_offsets[regDC_PINSTRAPS_BASE_IDX] + regDC_PINSTRAPS,
/linux-master/drivers/gpu/drm/amd/display/dc/core/
H A Ddc.c896 dc_ctx->dcn_reg_offsets = init_params->dcn_reg_offsets;
1415 dc->dcn_reg_offsets = init_params->dcn_reg_offsets;
/linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn35/
H A Ddcn35_resource.c127 #define BASE_INNER(seg) ctx->dcn_reg_offsets[seg]
/linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn351/
H A Ddcn351_resource.c107 #define BASE_INNER(seg) ctx->dcn_reg_offsets[seg]
/linux-master/drivers/gpu/drm/amd/display/amdgpu_dm/
H A Damdgpu_dm.c1723 init_data.dcn_reg_offsets = adev->reg_offset[DCE_HWIP][0];

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