| /broadcom-cfe-1.4.2/cfe/dev/ |
| H A D | dev_bcm5700.c | 1902 uint32_t ctrl; local
1908 ctrl = READCSR(sc, R_RCV_LIST_STATS_CTRL);
1909 ctrl |= M_STATS_ENABLE;
1910 WRITECSR(sc, R_RCV_LIST_STATS_CTRL, ctrl);
1914 ctrl = READCSR(sc, R_SND_DATA_STATS_CTRL);
1915 ctrl |= (M_STATS_ENABLE | M_STATS_FASTUPDATE);
1916 WRITECSR(sc, R_SND_DATA_STATS_CTRL, ctrl);
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| H A D | dev_bcm5780_ht1000.c | 69 pcireg_t ctrl; local
76 ctrl = pci_conf_read(tag, BCM5780_HOST_CFG_FEATURE_ENABLE0);
78 ctrl |= BCM5780_H0ST_FE0_IDE_ENABLE;
80 ctrl |= BCM5780_H0ST_FE0_USB_ENABLE;
81 pci_conf_write(tag, BCM5780_HOST_CFG_FEATURE_ENABLE0, ctrl);
82 ctrl = pci_conf_read(tag, BCM5780_HOST_CFG_FEATURE_ENABLE0); /* push */
85 ctrl = pci_conf_read(tag, BCM5780_HOST_CFG_FEATURE_ENABLE2);
87 ctrl |= BCM5780_H0ST_FE2_SATA_ENABLE;
88 pci_conf_write(tag, BCM5780_HOST_CFG_FEATURE_ENABLE2, ctrl);
89 ctrl
[all...] |
| H A D | dev_ht7520.c | 101 pcireg_t ctrl; local
106 ctrl = pci_conf_read(tag, APIC_CONTROL_REG);
107 ctrl |= APIC_CONTROL_IOAEN | APIC_CONTROL_OSVISBAR;
108 pci_conf_write(tag, APIC_CONTROL_REG, ctrl);
109 ctrl = pci_conf_read(tag, APIC_CONTROL_REG); /* push */
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| H A D | dev_aic6915.c | 1083 uint32_t ctrl; local
1098 ctrl = READCSR(sc, R_RxDmaCtrl);
1099 ctrl &= ~M_RxBurstSize;
1100 ctrl |= (16 << S_RxBurstSize);
1132 uint32_t ctrl; local
1149 ctrl = READCSR(sc, R_TxFrameCtrl);
1150 ctrl &= ~M_DmaCompletionAfterTransmitComplete;
1151 WRITECSR(sc, R_TxFrameCtrl, ctrl);
1221 uint32_t ctrl; local
1223 ctrl
[all...] |
| H A D | dev_dp83815.c | 784 uint32_t ctrl; local
787 ctrl = READCSR(sc, R_MEAR);
789 ctrl |= M_MEAR_EESEL;
790 WRITECSR(sc, R_MEAR, ctrl);
795 ctrl ^= M_MEAR_EECLK;
796 WRITECSR(sc, R_MEAR, ctrl);
801 ctrl &=~ M_MEAR_EESEL;
802 WRITECSR(sc, R_MEAR, ctrl);
809 uint32_t ctrl; local
811 ctrl
837 uint32_t ctrl; local
857 uint32_t ctrl; local
1049 uint32_t ctrl; local
1070 uint32_t ctrl; local
1107 uint32_t ctrl; local
[all...] |
| H A D | dev_tulip.c | 442 uint32_t ctrl = 0; local
450 ctrl = M_RDES1_ENDOFRING;
457 rxd->rxd_bufsize = V_RDES1_BUF1SIZE(1520) | ctrl;
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| H A D | dev_bcm4401.c | 996 uint32_t ctrl; local
998 ctrl = READCSR(sc, R_XMT_CONTROL1);
1002 ctrl |= (M_TCTL_FD | M_TCTL_SB);
1005 ctrl &= ~(M_TCTL_FD | M_TCTL_SB);
1008 WRITECSR(sc, R_XMT_CONTROL1, ctrl);
1015 uint32_t ctrl; local
1051 ctrl = READCSR(sc, R_EMAC_CONTROL);
1052 ctrl |= M_EMCTL_CC;
1053 WRITECSR(sc, R_EMAC_CONTROL, ctrl);
1062 ctrl
[all...] |
| H A D | dev_sp1011.c | 95 pcireg_t t, ctrl, intmap; local
103 ctrl = pci_conf_read(tag, LPB_READ_CTRL_REG) & ~LPB_READ_CTRL_MASK;
106 ctrl |= (LPB_READ_CTRL_PREF_EN
110 pci_conf_write(tag, LPB_READ_CTRL_REG, ctrl);
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| /broadcom-cfe-1.4.2/cfe/arch/mips/cpu/bcm1480/src/ |
| H A D | bcm1480_hsp_utils.c | 502 volatile pcireg_t cmd, ctrl; local
514 ctrl = pci_conf_read32(BCM1480_EXTx_BRIDGE(port), R_LDT_BRCMD);
515 ctrl |= LDT_COMMAND_WARM_RESET;
516 pci_conf_write32(BCM1480_EXTx_BRIDGE(port), R_LDT_BRCMD, ctrl); local
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| /broadcom-cfe-1.4.2/cfe/arch/mips/chipset/bcmsb/src/ |
| H A D | dev_sb_mac.c | 1101 uint32_t ctrl; local
1103 ctrl = READCSR(sc, R_XMT_CONTROL1);
1107 ctrl |= (M_TCTL_FD | M_TCTL_SB);
1110 ctrl &= ~(M_TCTL_FD | M_TCTL_SB);
1113 WRITECSR(sc, R_XMT_CONTROL1, ctrl);
1120 uint32_t ctrl; local
1176 ctrl = READCSR(sc, R_EMAC_CONTROL);
1177 ctrl |= M_EMCTL_CC;
1178 WRITECSR(sc, R_EMAC_CONTROL, ctrl);
1187 ctrl
[all...] |
| H A D | sb_pci_machdep.c | 255 uint32_t ctrl; local
261 ctrl = M_PCICTL_OE; /* enable reset output */
264 ctrl = M_PCICTL_OE | M_PCICTL_CE;/* enable the tristate drivers */
265 WRITECSR(R_PCI_CONTROL, ctrl);
266 ctrl |= M_PCICTL_CO; /* enable the PCI clock */
268 WRITECSR(R_PCI_CONTROL, ctrl);
270 ctrl |= M_PCICTL_RO; /* release reset */
271 WRITECSR(R_PCI_CONTROL, ctrl);
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| /broadcom-cfe-1.4.2/cfe/arch/ppc/chipset/mpc824x/src/ |
| H A D | dev_tulip.c | 508 uint32_t ctrl; local
511 ctrl = sc->rxdscr_ctrl;
517 ctrl = M_RDES1_ENDOFRING;
524 rxd->rxd_bufsize = DMA_SWAP(sc, V_RDES1_BUF1SIZE(1520) | ctrl);
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| /broadcom-cfe-1.4.2/cfe/arch/mips/cpu/sb1250/src/ |
| H A D | sb1250_pci_machdep.c | 525 volatile pcireg_t ctrl; local
531 ctrl = 0;
533 while ((ctrl & (LDT_LINKCTRL_INITDONE | LDT_LINKCTRL_LINKFAIL)) == 0
535 ctrl = pci_conf_read32(SB1250_LDT_BRIDGE, LHB_LINKCTRL_REG);
536 if ((ctrl & LHB_LINKCTRL_ERRORS) != 0 && !linkerr) {
540 count, ctrl & 0xFFFF);
|