1/* ********************************************************************* 2 * Broadcom Common Firmware Environment (CFE) 3 * 4 * AP1011/SP1011 (Sturgeon) Support File: dev_sp1011.c 5 * 6 ********************************************************************* 7 * 8 * Copyright 2000,2001,2002,2003 9 * Broadcom Corporation. All rights reserved. 10 * 11 * This software is furnished under license and may be used and 12 * copied only in accordance with the following terms and 13 * conditions. Subject to these conditions, you may download, 14 * copy, install, use, modify and distribute modified or unmodified 15 * copies of this software in source and/or binary form. No title 16 * or ownership is transferred hereby. 17 * 18 * 1) Any source code used, modified or distributed must reproduce 19 * and retain this copyright notice and list of conditions 20 * as they appear in the source file. 21 * 22 * 2) No right is granted to use any trade name, trademark, or 23 * logo of Broadcom Corporation. The "Broadcom Corporation" 24 * name may not be used to endorse or promote products derived 25 * from this software without the prior written permission of 26 * Broadcom Corporation. 27 * 28 * 3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR 29 * IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED 30 * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 31 * PURPOSE, OR NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT 32 * SHALL BROADCOM BE LIABLE FOR ANY DAMAGES WHATSOEVER, AND IN 33 * PARTICULAR, BROADCOM SHALL NOT BE LIABLE FOR DIRECT, INDIRECT, 34 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 35 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE 36 * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 37 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY 38 * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR 39 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE), EVEN IF ADVISED OF 40 * THE POSSIBILITY OF SUCH DAMAGE. 41 ********************************************************************* */ 42 43#include "lib_types.h" 44 45#include "pcireg.h" 46#include "pcivar.h" 47#include "pci_internal.h" 48 49extern int eoi_implemented; 50 51void sp1011_setup (pcitag_t tag, pci_flags_t flags); 52void as90l10208_setup(pcitag_t tag, pci_flags_t flags); 53 54 55/* Sturgeon LDT-to-PCI bridge (LPB) specific definitions. */ 56 57#define PCI_VENDOR_ALSC 0x14D9 58#define PCI_PRODUCT_ALSC_SP1011 0x0010 59 60/* Sturgeon specific registers */ 61#define LPB_READ_CTRL_REG 0x60 62#define LPB_READ_CTRL_MASK 0xFFFFFF 63 64#define LPB_READ_CTRL_PREF_EN (1 << 0) 65#define LPB_READ_CTRL_RD_PREF_EN (1 << 1) 66#define LPB_READ_CTRL_MULT_PREF_SHIFT 2 67#define LPB_READ_CTRL_MULT_PREF_MASK (7 << LPB_READ_CTRL_MULT_PREF_SHIFT) 68#define LPB_READ_CTRL_LINE_PREF_SHIFT 5 69#define LPB_READ_CTRL_LINE_PREF_MASK (7 << LPB_READ_CTRL_LINE_PREF_SHIFT) 70#define LPB_READ_CTRL_DEL_REQ_SHIFT 8 71#define LPB_READ_CTRL_DEL_REQ_MASK (3 << LPB_READ_CTRL_DEL_REQ_SHIFT) 72 73#define LPB_INT_CTRL_BASE 0xA0 74 75#define LPB_INT_CTRL_ENABLE (1 << 15) 76#define LPB_INT_CTRL_DESTMODE (1 << 14) 77#define LPB_INT_CTRL_DEST_SHIFT 6 78#define LPB_INT_CTRL_DEST_MASK (0xFF << LPB_INT_CTRL_DEST_SHIFT) 79#define LPB_INT_CTRL_MSGTYPE_SHIFT 4 80#define LPB_INT_CTRL_MSGTYPE_MASK (0x3 << LPB_INT_CTRL_MSGTYPE_SHIFT) 81#define LPB_INT_CTRL_POLARITY (1 << 3) 82#define LPB_INT_CTRL_TRIGGERMODE (1 << 2) 83#define LPB_INT_CTRL_VECTOR_SHIFT 0 84#define LPB_INT_CTRL_VECTOR_MASK (0x3 << 0) 85 86#define LPB_INT_BLOCK1_REG 0xC4 87 88void 89sp1011_setup (pcitag_t tag, pci_flags_t flags) 90{ 91 int port, bus, device, function; 92 int secondary; 93 struct pci_bus *pb; 94 unsigned offset; 95 pcireg_t t, ctrl, intmap; 96 97 pci_break_tag(tag, &port, &bus, &device, &function); 98 99 secondary = (pci_conf_read(tag, PPB_BUSINFO_REG) >> 8) & 0xFF; 100 pb = pci_businfo(port, secondary); 101 102 /* set up READ CONTROL register for selected prefetch option */ 103 ctrl = pci_conf_read(tag, LPB_READ_CTRL_REG) & ~LPB_READ_CTRL_MASK; 104 /* Default prefetch enable: all cycle types, 2 delayed requests, 105 4 lines of fetch ahead for MemRdMult */ 106 ctrl |= (LPB_READ_CTRL_PREF_EN 107 | LPB_READ_CTRL_RD_PREF_EN 108 | (3 << LPB_READ_CTRL_MULT_PREF_SHIFT) 109 | (1 << LPB_READ_CTRL_DEL_REQ_SHIFT)); 110 pci_conf_write(tag, LPB_READ_CTRL_REG, ctrl); 111 112 /* It's apparently not possible for software to distinguish 113 the CSWARM's debug Sturgeon (which has floating interrupt 114 inputs), so we route interrupts only if there are secondary 115 devices. */ 116 if (pb->ndev > 0) { 117 /* Setup interrupt mapping for Block 1: 118 Enabled, Dest=Logical (CPU 0 + CPU 1), Type=Fixed */ 119 intmap = (LPB_INT_CTRL_ENABLE | 120 LPB_INT_CTRL_DESTMODE | /* Logical */ 121 (0x3 << LPB_INT_CTRL_DEST_SHIFT) | /* CPU 0+1 */ 122 (0x0 << LPB_INT_CTRL_MSGTYPE_SHIFT)); /* Fixed */ 123 if (eoi_implemented) { 124 /* Passes >=2 have working EOI. Trigger=Level */ 125 intmap |= LPB_INT_CTRL_TRIGGERMODE; /* Level */ 126 } else { 127 /* Pass 1 lacks working EOI. Trigger=Edge */ 128 intmap |= 0; /* Edge */ 129 } 130 131 offset = pb->inta_shift % 4; 132 t = (intmap + offset); 133 offset = (offset+1) % 4; 134 t |= (intmap + offset) << 16; 135 pci_conf_write(tag, LPB_INT_CTRL_BASE + 8, t); 136 137 offset = (offset+1) % 4; 138 t = (intmap + offset); 139 offset = (offset+1) % 4; 140 t |= (intmap + offset) << 16; 141 pci_conf_write(tag, LPB_INT_CTRL_BASE + 12, t); 142 143 t = pci_conf_read(tag, LPB_INT_BLOCK1_REG); 144 t &= 0xFFFFFF00; 145 t |= (0x40 | (56 >> 2)); 146 pci_conf_write(tag, LPB_INT_BLOCK1_REG, t); 147 } 148} 149 150 151void as90l10208_setup(pcitag_t tag, pci_flags_t flags) 152{ 153 /* Just a placeholder pending release of specs. */ 154} 155