/linux-master/drivers/clk/ |
H A D | clk-clps711x.c | 119 clk_hw_register_divider_table(NULL, "timer1", "timer_ref", 0, 123 clk_hw_register_divider_table(NULL, "timer2", "timer_ref", 0, 131 clk_hw_register_divider_table(NULL, "spi", "spi_ref", 0,
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H A D | clk-ast2600.c | 555 hw = clk_hw_register_divider_table(dev, "emmc_extclk", 571 hw = clk_hw_register_divider_table(dev, "sd_extclk", "sd_extclk_gate", 585 hw = clk_hw_register_divider_table(dev, "mac12", "hpll", 0, 615 hw = clk_hw_register_divider_table(dev, "mac34", "hpll", 0, 640 hw = clk_hw_register_divider_table(dev, "lhclk", "hpll", 0, 663 hw = clk_hw_register_divider_table(dev, "bclk", "epll", 0, 681 hw = clk_hw_register_divider_table(dev, "eclk", NULL, 0,
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H A D | clk-aspeed.c | 449 hw = clk_hw_register_divider_table(dev, "sd_extclk", "sd_extclk_gate", 458 hw = clk_hw_register_divider_table(dev, "mac", "hpll", 0, 491 hw = clk_hw_register_divider_table(dev, "lhclk", "hpll", 0, 500 hw = clk_hw_register_divider_table(dev, "bclk", "hpll", 0, 523 hw = clk_hw_register_divider_table(dev, "eclk", "eclk-mux", 0, 644 hw = clk_hw_register_divider_table(NULL, "apb", "hpll", 0,
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H A D | clk-stm32h7.c | 513 hws[SYS_D1CPRE] = clk_hw_register_divider_table(NULL, "d1cpre", 517 hws[HCLK] = clk_hw_register_divider_table(NULL, "hclk", "d1cpre", 527 hws[PCLK3] = clk_hw_register_divider_table(NULL, "pclk3", "hclk", 0, 533 hws[PCLK1] = clk_hw_register_divider_table(NULL, "pclk1", "hclk", 0, 542 hws[PCLK2] = clk_hw_register_divider_table(NULL, "pclk2", "hclk", 0, 551 hws[PCLK4] = clk_hw_register_divider_table(NULL, "pclk4", "hclk", 0,
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/linux-master/drivers/clk/imx/ |
H A D | clk-imx6ul.c | 222 hws[IMX6UL_CLK_ENET_REF] = clk_hw_register_divider_table(NULL, "enet1_ref", "pll6_enet", 0, 224 hws[IMX6UL_CLK_ENET2_REF] = clk_hw_register_divider_table(NULL, "enet2_ref", "pll6_enet", 0, 232 hws[IMX6UL_CLK_PLL4_POST_DIV] = clk_hw_register_divider_table(NULL, "pll4_post_div", "pll4_audio", 236 hws[IMX6UL_CLK_PLL5_POST_DIV] = clk_hw_register_divider_table(NULL, "pll5_post_div", "pll5_video", 238 hws[IMX6UL_CLK_PLL5_VIDEO_DIV] = clk_hw_register_divider_table(NULL, "pll5_video_div", "pll5_post_div",
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H A D | clk-imx6sx.c | 219 hws[IMX6SX_CLK_ENET_REF] = clk_hw_register_divider_table(NULL, "enet_ref", "pll6_enet", 0, 222 hws[IMX6SX_CLK_ENET2_REF] = clk_hw_register_divider_table(NULL, "enet2_ref", "pll6_enet", 0, 248 hws[IMX6SX_CLK_PLL4_POST_DIV] = clk_hw_register_divider_table(NULL, "pll4_post_div", "pll4_audio", 252 hws[IMX6SX_CLK_PLL5_POST_DIV] = clk_hw_register_divider_table(NULL, "pll5_post_div", "pll5_video", 254 hws[IMX6SX_CLK_PLL5_VIDEO_DIV] = clk_hw_register_divider_table(NULL, "pll5_video_div", "pll5_post_div",
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H A D | clk-imx6sll.c | 175 hws[IMX6SLL_CLK_PLL4_POST_DIV] = clk_hw_register_divider_table(NULL, "pll4_post_div", "pll4_audio", 179 hws[IMX6SLL_CLK_PLL5_POST_DIV] = clk_hw_register_divider_table(NULL, "pll5_post_div", "pll5_video", 181 hws[IMX6SLL_CLK_PLL5_VIDEO_DIV] = clk_hw_register_divider_table(NULL, "pll5_video_div", "pll5_post_div",
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H A D | clk-imx6sl.c | 267 hws[IMX6SL_CLK_PLL4_POST_DIV] = clk_hw_register_divider_table(NULL, "pll4_post_div", "pll4_audio", CLK_SET_RATE_PARENT, base + 0x70, 19, 2, 0, post_div_table, &imx_ccm_lock); 269 hws[IMX6SL_CLK_PLL5_POST_DIV] = clk_hw_register_divider_table(NULL, "pll5_post_div", "pll5_video", CLK_SET_RATE_PARENT, base + 0xa0, 19, 2, 0, post_div_table, &imx_ccm_lock); 270 hws[IMX6SL_CLK_PLL5_VIDEO_DIV] = clk_hw_register_divider_table(NULL, "pll5_video_div", "pll5_post_div", CLK_SET_RATE_PARENT, base + 0x170, 30, 2, 0, video_div_table, &imx_ccm_lock); 271 hws[IMX6SL_CLK_ENET_REF] = clk_hw_register_divider_table(NULL, "enet_ref", "pll6_enet", 0, base + 0xe0, 0, 2, 0, clk_enet_ref_table, &imx_ccm_lock);
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H A D | clk-imx7d.c | 429 hws[IMX7D_PLL_DRAM_TEST_DIV] = clk_hw_register_divider_table(NULL, "pll_dram_test_div", "pll_dram_main_bypass", 431 hws[IMX7D_PLL_AUDIO_TEST_DIV] = clk_hw_register_divider_table(NULL, "pll_audio_test_div", "pll_audio_main_clk", 433 hws[IMX7D_PLL_AUDIO_POST_DIV] = clk_hw_register_divider_table(NULL, "pll_audio_post_div", "pll_audio_test_div", 435 hws[IMX7D_PLL_VIDEO_TEST_DIV] = clk_hw_register_divider_table(NULL, "pll_video_test_div", "pll_video_main_clk", 437 hws[IMX7D_PLL_VIDEO_POST_DIV] = clk_hw_register_divider_table(NULL, "pll_video_post_div", "pll_video_test_div",
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H A D | clk-imx6q.c | 545 hws[IMX6QDL_CLK_ENET_REF] = clk_hw_register_divider_table(NULL, "enet_ref", "pll6_enet", 0, 598 hws[IMX6QDL_CLK_PLL4_POST_DIV] = clk_hw_register_divider_table(NULL, "pll4_post_div", "pll4_audio", CLK_SET_RATE_PARENT, base + 0x70, 19, 2, 0, post_div_table, &imx_ccm_lock); 603 hws[IMX6QDL_CLK_PLL5_POST_DIV] = clk_hw_register_divider_table(NULL, "pll5_post_div", "pll5_video", CLK_SET_RATE_PARENT, base + 0xa0, 19, 2, 0, post_div_table, &imx_ccm_lock); 604 hws[IMX6QDL_CLK_PLL5_VIDEO_DIV] = clk_hw_register_divider_table(NULL, "pll5_video_div", "pll5_post_div", CLK_SET_RATE_PARENT, base + 0x170, 30, 2, 0, video_div_table, &imx_ccm_lock);
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/linux-master/drivers/clk/samsung/ |
H A D | clk.c | 219 clk_hw = clk_hw_register_divider_table(ctx->dev,
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/linux-master/include/linux/ |
H A D | clk-provider.h | 815 * clk_hw_register_divider_table - register a table based divider clock with 828 #define clk_hw_register_divider_table(dev, name, parent_name, flags, reg, \ macro
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/linux-master/drivers/clk/renesas/ |
H A D | rzg2l-cpg.c | 422 clk_hw = clk_hw_register_divider_table(dev, core->name,
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/linux-master/drivers/clk/stm32/ |
H A D | clk-stm32mp1.c | 430 return clk_hw_register_divider_table(dev,
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