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f316cdff |
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17-Aug-2023 |
Kees Cook <keescook@chromium.org> |
clk: Annotate struct clk_hw_onecell_data with __counted_by Prepare for the coming implementation by GCC and Clang of the __counted_by attribute. Flexible array members annotated with __counted_by can have their accesses bounds-checked at run-time checking via CONFIG_UBSAN_BOUNDS (for array indexing) and CONFIG_FORTIFY_SOURCE (for strcpy/memcpy-family functions). As found with Coccinelle[1], add __counted_by for struct clk_hw_onecell_data. Additionally, since the element count member must be set before accessing the annotated flexible array member, move its initialization earlier. [1] https://github.com/kees/kernel-tools/blob/trunk/coccinelle/examples/counted_by.cocci Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@kernel.org> Cc: Joel Stanley <joel@jms.id.au> Cc: Andrew Jeffery <andrew@aj.id.au> Cc: Taichi Sugaya <sugaya.taichi@socionext.com> Cc: Takao Orito <orito.takao@socionext.com> Cc: Qin Jian <qinjian@cqplus1.com> Cc: Andrew Lunn <andrew@lunn.ch> Cc: Gregory Clement <gregory.clement@bootlin.com> Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Cc: Andy Gross <agross@kernel.org> Cc: Bjorn Andersson <andersson@kernel.org> Cc: Konrad Dybcio <konrad.dybcio@linaro.org> Cc: Sergio Paracuellos <sergio.paracuellos@gmail.com> Cc: Matthias Brugger <matthias.bgg@gmail.com> Cc: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Cc: Maxime Ripard <mripard@kernel.org> Cc: Chen-Yu Tsai <wens@csie.org> Cc: Jernej Skrabec <jernej.skrabec@gmail.com> Cc: David Airlie <airlied@gmail.com> Cc: Daniel Vetter <daniel@ffwll.ch> Cc: Samuel Holland <samuel@sholland.org> Cc: Vinod Koul <vkoul@kernel.org> Cc: Kishon Vijay Abraham I <kishon@kernel.org> Cc: linux-clk@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-aspeed@lists.ozlabs.org Cc: linux-arm-msm@vger.kernel.org Cc: linux-mediatek@lists.infradead.org Cc: dri-devel@lists.freedesktop.org Cc: linux-sunxi@lists.linux.dev Cc: linux-phy@lists.infradead.org Signed-off-by: Kees Cook <keescook@chromium.org> Link: https://lore.kernel.org/r/20230817203019.never.795-kees@kernel.org Reviewed-by: Gustavo A. R. Silva <gustavoars@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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a96cbb14 |
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18-Jul-2023 |
Rob Herring <robh@kernel.org> |
clk: Explicitly include correct DT includes The DT of_device.h and of_platform.h date back to the separate of_platform_bus_type before it as merged into the regular platform bus. As part of that merge prepping Arm DT support 13 years ago, they "temporarily" include each other. They also include platform_device.h and of.h. As a result, there's a pretty much random mix of those include files used throughout the tree. In order to detangle these headers and replace the implicit includes with struct declarations, users need to explicitly include the correct includes. Acked-by: Dinh Nguyen <dinguyen@kernel.org> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> # samsung Acked-by: Heiko Stuebner <heiko@sntech.de> #rockchip Acked-by: Chanwoo Choi <cw00.choi@samsung.com> Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Luca Ceresoli <luca.ceresoli@bootlin.com> # versaclock5 Signed-off-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20230718143156.1066339-1-robh@kernel.org Acked-by: Abel Vesa <abel.vesa@linaro.org> #imx Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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801b787a |
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09-Oct-2019 |
Andrew Jeffery <andrew@aj.id.au> |
clk: aspeed: Add RMII RCLK gates for both AST2500 MACs RCLK is a fixed 50MHz clock derived from HPLL that is described by a single gate for each MAC. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lkml.kernel.org/r/20191010020655.3776-3-andrew@aj.id.au Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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c1c4942e |
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25-Aug-2019 |
Joel Stanley <joel@jms.id.au> |
clk: aspeed: Move structures to header They will be reused by the ast2600 driver. Signed-off-by: Joel Stanley <joel@jms.id.au> Link: https://lkml.kernel.org/r/20190825141848.17346-2-joel@jms.id.au Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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ebd5f82d |
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10-Jul-2019 |
Joel Stanley <joel@jms.id.au> |
clk: aspeed: Add SDIO gate The clock divisor comes with an enable bit (gate). This was not implemented as we didn't have access to SD hardware when writing the driver. Now that we can test it, add the gate as a parent to the divisor. There is no reason to expose the gate separately, so users will enable it by turning on the ASPEED_CLK_SDIO divisor. Signed-off-by: Joel Stanley <joel@jms.id.au> [aj: Minor style cleanup] Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lkml.kernel.org/r/20190710141009.20651-1-andrew@aj.id.au Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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defb149b |
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02-Apr-2019 |
Eddie James <eajames@linux.ibm.com> |
clk: Aspeed: Setup video engine clocking Add eclk mux and clock divider table. Also change the video engine reset to the correct clock; it was previously on the video capture but needs to be on the video engine clock. Signed-off-by: Eddie James <eajames@linux.ibm.com> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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565b9937 |
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28-Jun-2018 |
Joel Stanley <joel@jms.id.au> |
clk: aspeed: Support HPLL strapping on ast2400 The HPLL can be configured through a register (SCU24), however some platforms chose to configure it through the strapping settings and do not use the register. This was not noticed as the logic for bit 18 in SCU24 was confused: set means programmed, but the driver read it as set means strapped. This gives us the correct HPLL value on Palmetto systems, from which most of the peripheral clocks are generated. Fixes: 5eda5d79e4be ("clk: Add clock driver for ASPEED BMC SoCs") Cc: stable@vger.kernel.org # v4.15 Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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cd88259a |
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25-Jun-2018 |
Lei YU <mine260309@gmail.com> |
clk: aspeed: Fix SDCLK name The SDCLK was named SDCLKCLK, and no one has used this yet. Fix it. Signed-off-by: Lei YU <mine260309@gmail.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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974c7c6d |
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07-Jun-2018 |
Joel Stanley <joel@jms.id.au> |
clk: aspeed: Mark bclk (PCIe) and dclk (VGA) as critical This is used by the host to talk to the BMC's PCIe slave device. The BMC is not involved, but the clock needs to be enabled so the host can use the device. Fixes: 15ed8ce5f84e ("clk: aspeed: Register gated clocks") Cc: stable@vger.kernel.org # 4.15 Acked-by: Andrew Jeffery <andrew@aj.id.au> Tested-by: Lei YU <mine260309@gmail.com> Signed-off-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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edc6f7e9 |
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03-Jul-2018 |
Benjamin Herrenschmidt <benh@linux.vnet.ibm.com> |
clk: aspeed: Treat a gate in reset as disabled On some systems, we come out of the bootloader with some gates set with the clock "enabled" but the reset also asserted. Since 8a53fc511c5e "clk: aspeed: Prevent reset if clock is enabled" we check that enabled bit in aspeed_clk_enabled(), and do nothing if already set. This breaks when the above scenario occurs, as the clock is enabled, but the reset still needs to be lifted. This patch fixes it by also checking the reset bit (if any) and treating a gate in "reset" as being disabled. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Fixes: 8a53fc511c5e "clk: aspeed: Prevent reset if clock is enabled" Cc: Eddie James <eajames@linux.vnet.ibm.com> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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acafe7e3 |
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08-May-2018 |
Kees Cook <keescook@chromium.org> |
treewide: Use struct_size() for kmalloc()-family One of the more common cases of allocation size calculations is finding the size of a structure that has a zero-sized array at the end, along with memory for some number of elements for that array. For example: struct foo { int stuff; void *entry[]; }; instance = kmalloc(sizeof(struct foo) + sizeof(void *) * count, GFP_KERNEL); Instead of leaving these open-coded and prone to type mistakes, we can now use the new struct_size() helper: instance = kmalloc(struct_size(instance, entry, count), GFP_KERNEL); This patch makes the changes for kmalloc()-family (and kvmalloc()-family) uses. It was done via automatic conversion with manual review for the "CHECKME" non-standard cases noted below, using the following Coccinelle script: // pkey_cache = kmalloc(sizeof *pkey_cache + tprops->pkey_tbl_len * // sizeof *pkey_cache->table, GFP_KERNEL); @@ identifier alloc =~ "kmalloc|kzalloc|kvmalloc|kvzalloc"; expression GFP; identifier VAR, ELEMENT; expression COUNT; @@ - alloc(sizeof(*VAR) + COUNT * sizeof(*VAR->ELEMENT), GFP) + alloc(struct_size(VAR, ELEMENT, COUNT), GFP) // mr = kzalloc(sizeof(*mr) + m * sizeof(mr->map[0]), GFP_KERNEL); @@ identifier alloc =~ "kmalloc|kzalloc|kvmalloc|kvzalloc"; expression GFP; identifier VAR, ELEMENT; expression COUNT; @@ - alloc(sizeof(*VAR) + COUNT * sizeof(VAR->ELEMENT[0]), GFP) + alloc(struct_size(VAR, ELEMENT, COUNT), GFP) // Same pattern, but can't trivially locate the trailing element name, // or variable name. @@ identifier alloc =~ "kmalloc|kzalloc|kvmalloc|kvzalloc"; expression GFP; expression SOMETHING, COUNT, ELEMENT; @@ - alloc(sizeof(SOMETHING) + COUNT * sizeof(ELEMENT), GFP) + alloc(CHECKME_struct_size(&SOMETHING, ELEMENT, COUNT), GFP) Signed-off-by: Kees Cook <keescook@chromium.org>
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67b6e5cf |
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18-May-2018 |
Lei YU <mine260309@gmail.com> |
clk: aspeed: Add 24MHz fixed clock Add a 24MHz fixed clock. This clock will be used for certain devices, e.g. pwm. Signed-off-by: Lei YU <mine260309@gmail.com> Reviewed-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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e76e5682 |
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26-Apr-2018 |
Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com> |
clk:aspeed: Fix reset bits for PCI/VGA and PECI This commit fixes incorrect setting of reset bits for PCI/VGA and PECI modules. 1. Reset bit for PCI/VGA is 8. 2. PECI reset bit is missing so added bit 10 as its reset bit. Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com> Fixes: 15ed8ce5f84e ("clk: aspeed: Register gated clocks") Cc: stable <stable@vger.kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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dcb899c4 |
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26-Apr-2018 |
Joel Stanley <joel@jms.id.au> |
clk: aspeed: Support second reset register The ast2500 has an additional reset register that contains resets not present in the ast2400. This enables support for this register, and adds the one reset line that is controlled by it. Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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8a53fc51 |
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08-Mar-2018 |
Eddie James <eajames@linux.vnet.ibm.com> |
clk: aspeed: Prevent reset if clock is enabled According to the Aspeed specification, the reset and enable sequence should be done when the clock is stopped. The specification doesn't define behavior if the reset is done while the clock is enabled. From testing on the AST2500, the LPC Controller has problems if the clock is reset while enabled. Therefore, check whether the clock is enabled or not before performing the reset and enable sequence in the Aspeed clock driver. Reported-by: Lei Yu <mine260309@gmail.com> Signed-off-by: Eddie James <eajames@linux.vnet.ibm.com> Fixes: 15ed8ce5f84e ("clk: aspeed: Register gated clocks") Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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d90c76bb |
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08-Mar-2018 |
Eddie James <eajames@linux.vnet.ibm.com> |
clk: aspeed: Fix is_enabled for certain clocks Some of the Aspeed clocks are disabled by setting the relevant bit in the "clock stop control" register to one, while others are disabled by setting their bit to zero. The driver already uses a flag per gate to identify this behavior, but doesn't apply it in the clock is_enabled function. Use the existing gate flag to correctly return whether or not a clock is enabled in the aspeed_clk_is_enabled function. Signed-off-by: Eddie James <eajames@linux.vnet.ibm.com> Fixes: 6671507f0fbd ("clk: aspeed: Handle inverse polarity of USB port 1 clock gate") Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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6671507f |
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11-Jan-2018 |
Benjamin Herrenschmidt <benh@kernel.crashing.org> |
clk: aspeed: Handle inverse polarity of USB port 1 clock gate The USB port 1 clock gate control has an inversed polarity from all the other clock gates in the chip. This makes the aspeed_clk_{enable,disable} functions honor the flag CLK_GATE_SET_TO_DISABLE and set that flag appropriately so it's set for all clocks except USB port 1. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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accf475a |
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04-Jan-2018 |
Wei Yongjun <weiyongjun1@huawei.com> |
clk: aspeed: Fix return value check in aspeed_cc_init() In case of error, the function of_iomap() returns NULL pointer not ERR_PTR(). The IS_ERR() test in the return value check should be replaced with NULL test. Fixes: a2e230c7b2ea ("clk: Add clock driver for ASPEED BMC SoCs") Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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f7989839 |
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21-Dec-2017 |
Joel Stanley <joel@jms.id.au> |
clk: aspeed: Add reset controller There are some resets that are not associated with gates. These are represented by a reset controller. Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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15ed8ce5 |
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21-Dec-2017 |
Joel Stanley <joel@jms.id.au> |
clk: aspeed: Register gated clocks The majority of the clocks in the system are gates paired with a reset controller that holds the IP in reset. This borrows from clk_hw_register_gate, but registers two 'gates', one to control the clock enable register and the other to control the reset IP. This allows us to enforce the ordering: 1. Place IP in reset 2. Enable clock 3. Delay 4. Release reset There are some gates that do not have an associated reset; these are handled by using -1 as the index for the reset. Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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98f3118d |
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21-Dec-2017 |
Joel Stanley <joel@jms.id.au> |
clk: aspeed: Add platform driver and register PLLs This registers a platform driver to set up all of the non-core clocks. The clocks that have configurable rates are now registered. Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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99d01e0e |
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21-Dec-2017 |
Joel Stanley <joel@jms.id.au> |
clk: aspeed: Register core clocks This registers the core clocks; those which are required to calculate the rate of the timer peripheral so the system can load a clocksource driver. Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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5eda5d79 |
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21-Dec-2017 |
Joel Stanley <joel@jms.id.au> |
clk: Add clock driver for ASPEED BMC SoCs This adds the stub of a driver for the ASPEED SoCs. The clocks are defined and the static registration is set up. Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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