Searched refs:bic (Results 1 - 25 of 56) sorted by relevance

123

/freebsd-11-stable/contrib/llvm-project/compiler-rt/lib/builtins/arm/
H A Dsync_fetch_and_nand_8.S18 bic rD_LO, rN_LO, rM_LO ; \
19 bic rD_HI, rN_HI, rM_HI
H A Dsync_fetch_and_nand_4.S16 #define nand_4(rD, rN, rM) bic rD, rN, rM
H A Dbswapdi2.S26 bic r2, r2, #0xff0000
31 bic r0, r0, #0xff0000
H A Dbswapsi2.S25 bic r1, r1, #0xff0000
/freebsd-11-stable/lib/libc/arm/gen/
H A Dalloca.S42 bic r0, r0, #0x00000007
H A Dsigsetjmp.S63 bic r3, r3, #(_JB_MAGIC__SETJMP ^ _JB_MAGIC__SETJMP_VFP)
/freebsd-11-stable/sys/arm/arm/
H A Dsetstack.s65 bic r2, r3, #(PSR_MODE)
84 bic r2, r3, #(PSR_MODE)
H A Dcpufunc_asm_pj4b.S45 bic r0, r0, #(1 << 12) /* LDSTM first issue is single word */
53 bic r0, r0, #(1 << 2) /* Disable static branch prediction */
71 bic r0, r0, #(1 << 23) /* Enable fast LDR */
93 bic r2, r2, #(1 << 8)
H A Dsetcpsr.S56 * r0 - bic mask
62 bic r2, r3, r0
H A Dlocore-v6.S76 bic r0, r0, #(PSR_MODE) ;\
134 bic r7, #CPU_CONTROL_DC_ENABLE
135 bic r7, #CPU_CONTROL_AFLT_ENABLE
136 bic r7, #CPU_CONTROL_MMU_ENABLE
137 bic r7, #CPU_CONTROL_IC_ENABLE
138 bic r7, #CPU_CONTROL_BPRD_ENABLE
139 bic r7, #CPU_CONTROL_SW_ENABLE
161 bic r5, pc, r2
215 bic sp, sp, #7 /* align stack to 8 bytes */
347 bic r
[all...]
H A Dfiq_subr.S57 bic r2, r2, #(PSR_MODE) ; \
H A Dcpufunc_asm_armv5_ec.S85 bic r0, r0, r3
124 bic r0, r0, r3
143 bic r0, r0, r3
166 bic r0, r0, r3
185 bic r0, r0, r3
H A Dcpufunc_asm_xscale_c3.S173 bic r0, r0, #0x1f
195 bic r0, r0, #0x1f
216 bic r0, r0, #0x1f
237 bic r0, r0, #0x1f
281 bic r0, r0, #0x1f
303 bic r0, r0, #0x1f
322 bic r0, r0, #0x1f
H A Dswtch-v6.S191 bic r0, #3
203 bic r0, r2
209 bic r0, r2
252 bic r0, #3
377 bic r0, #3
390 bic r0, r2
396 bic r0, r2
H A Dcpufunc_asm_arm9.S80 bic r0, r0, r3
123 bic r0, r0, r3
140 bic r0, r0, r3
161 bic r0, r0, r3
178 bic r0, r0, r3
H A Dcpufunc_asm_fa526.S102 bic r0, r0, #(CACHELINE_SIZE - 1)
123 bic r0, r0, #(CACHELINE_SIZE - 1)
137 bic r0, r0, #(CACHELINE_SIZE - 1)
153 bic r0, r0, #(CACHELINE_SIZE - 1)
171 bic r0, r0, #(CACHELINE_SIZE - 1)
H A Dlocore-v4.S149 bic r2, r2, #(CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_DC_ENABLE |\
151 bic r2, r2, #(CPU_CONTROL_IC_ENABLE)
152 bic r2, r2, #(CPU_CONTROL_BPRD_ENABLE)
172 bic r5, pc, r2
251 bic sp, sp, #7 /* align stack to 8 bytes */
381 bic r2, r2, #(PSR_MODE)
H A Dcpufunc_asm_xscale.S115 bic r2, r3, r0 /* Clear bits */
370 bic r0, r0, #0x1f
391 bic r0, r0, #0x1f
413 bic r0, r0, #0x1f
434 bic r0, r0, #0x1f
452 bic r0, r0, #0x1f
H A Dexception.S156 bic r2, r2, #(PSR_MODE); /* Fix for SVC mode */ \
160 bic sp, sp, #7; /* Align sp to an 8-byte addrress */ \
194 bic r2, r2, #(PSR_MODE); /* Fix for SVC mode */ \
198 bic sp, sp, #7; /* Align sp to an 8-byte addrress */ \
261 bic r4, r4, #(PSR_I|PSR_F); \
425 bic r8, #(PSR_F) /* just disable FIQ and return. */
H A Dcpufunc_asm_armv7.S105 bic r0, r0, r1
191 bic r0, r0, r3
207 bic r0, r0, r3
227 bic r0, r0, r3
243 bic r0, r0, r3
302 bic r3, r2, r0 /* Clear bits */
/freebsd-11-stable/sys/arm64/arm64/
H A Dcpufunc_asm.S62 bic x0, x0, x4 /* Clear the low bit of the address */
108 bic x0, x0, x1
/freebsd-11-stable/sys/arm/mv/armadaxp/
H A Dmptramp.S39 bic r3, r3, #(PSR_MODE)
/freebsd-11-stable/libexec/rtld-elf/arm/
H A Drtld_start.S41 bic sp, sp, #7 /* align the stack pointer */
90 bic sp, sp, #7 /* Align the stack pointer */
/freebsd-11-stable/sys/arm/include/
H A Dcpufunc.h66 u_int (*cf_control) (u_int bic, u_int eor);
211 u_int cpufunc_control (u_int clear, u_int bic);
365 u_int xscale_control (u_int clear, u_int bic);
435 __set_cpsr(uint32_t bic, uint32_t eor) argument
441 "bic %1, %0, %2\n" /* Clear bits */
445 : "r" (bic), "r" (eor) : "memory");
/freebsd-11-stable/secure/lib/libcrypto/aarch64/
H A Dsha256-armv8.S47 bic w19,w26,w24
72 bic w28,w25,w23
96 bic w19,w24,w22
121 bic w28,w23,w21
145 bic w19,w22,w20
170 bic w28,w21,w27
194 bic w19,w20,w26
219 bic w28,w27,w25
243 bic w19,w26,w24
268 bic w2
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