MFC 332906,332907,332976,333679,336053: Expand testing of breakpoints.

332906:
Extend support for ptrace() tests using breakpoints.

- Use a single list of platforms to define HAVE_BREAKPOINT for platforms
that expose a functional breakpoint() inline to userland. Replace
existing lists of platform tests with HAVE_BREAKPOINT instead.
- Add support for advancing PC past a breakpoint inserted via breakpoint()
to support the existing ptrace__PT_CONTINUE_different_thread test on
non-x86 platforms (x86 advances the PC past the breakpoint instruction,
but other platforms do not). This is implemented by defining a new
SKIP_BREAK macro which accepts a pointer to a 'struct reg' as its sole
argument and modifies the contents to advance the PC. The intention is
to use it in between PT_GETREGS and PT_SETREGS.

332907:
Expose breakpoint() to userland from <machine/cpufunc.h> on MIPS.

Enable ptrace() tests using breakpoint on MIPS as well.

332976:
Shorten some recently-added lines that are an extra indent over 80 columns.

333679:
Export a breakpoint() function to userland for riscv.

As a result, enable tests using breakpoint() on riscv.

336053:
Export a breakpoint() function to userland for arm and arm64.

Enable ptrace() tests using breakpoint() on these architectures.

Revert r330897:

This was intended to be a non-functional change. It wasn't. The commit
message was thus wrong. In addition it broke arm, and merged crypto
related code.

Revert with prejudice.

This revert skips files touched in r316370 since that commit was since
MFCed. This revert also skips files that require $FreeBSD$ property
changes.

Thank you to those who helped me get out of this mess including but not
limited to gonzo, kevans, rgrimes.

Requested by: gjb (re)

Partial merge of the SPDX changes

These changes are incomplete but are making it difficult
to determine what other changes can/should be merged.

No objections from: pfg

MFC r306704,r308406:

r306704:
ARM: Remove next bunch of unused cpu_functions from ARMv6.
r308406:
Only include sys/boot.h if LINUX_BOOT_ABI is defined

MFC r306631,r306640,r306641,r306650,r306656:

r306631:
Use C99 designated initializers to create the armv6 cpu_functions structs.
This will help with a later cleanup of what functions we implement.
r306640:
Only define the CF_* macros on ARMv4/v5. They are unused on armv6.
r306641:
Remove the parts of cpu_functions from armv6 that are unused on that
architecture.
r306650:
Add the Cortex-A{53,57,72} ID register values. These can all run 32-bit
code so could run a 32-bit kernel.
r306656:
Use the cortex functions when booting on one of the Cortex-A ARMv8 CPUs.
This list is incomplete, however we don't have the ID values for the
missing Cortex-A32 or A35.

MFC r312292, r313573:

Stop including sys/types.h from arm's machine/atomic.h, fix the places
where atomic.h was being included without ensuring that types.h (via
param.h) was included first, as required by atomic(9).

Remove arm's cpuconf.h, and references to it, after moving a few lines from
it into pmap-v4.h where they are used. Other than those few lines of
support for different MMU types, nothing in cpuconf.h has been used in our
code for quite a while.
The file existed to set up a variety of symbols to describe the
architecture. Over the past few years we have converted all of our source
to use the new architecture symbols standardized by ARM Inc, and predefined
by both clang and gcc.

MFC r306756:

ARM: SEV/WFE instructions are implemented starting from ARMv6K, use it
directly.

Copy head@r302406 to stable/11 as part of the 11.0-RELEASE cycle.
Prune svn:mergeinfo from the new branch, as nothing has been merged
here.

Additional commits post-branch will follow.

Approved by: re (implicit)
Sponsored by: The FreeBSD Foundation

ARM: Use new ARMv6 naming conventions for cache and TLB functions
in all but ARMv4 specific files.
Expand ARMv6 compatibility stubs in cpu-v4.h. Use physical address
in L2 cache functions if ARM_L2_PIPT is defined.

ARM: Don't use ugly (and hidden) global variable, control register is
readable at any time.

ARM: Consistently use cpu_setttb() instead of setttb().
Remove unused #define for drain_writebuf.

ARM: Replace only once used cpu_icache_sync_all() by ranged equivalent.
Remove it from cpu_functions table.

ARM: Remove support for xscale i80219 and i80321 CPUs. We haven't single
supported config/board with these CPUs.

ARM: All remaining functions in cpufunc_asm_arm10.S are identical with
functions in cpufunc_asm_arm9.S. Use arm9 variants and remove
cpufunc_asm_arm10.S completly.

ARM: Remove last unused function, cpu_flush_prefetchbuf(),
from cpu_functions table.

ARM: Remove never used cpu_tlb_flushI and cpu_tlb_flushI_SE() functions
and their implementations.

ARM: cpufunc_domains, cpufunc_faultstatus and cpufunc_faultaddress
functions are equal for all ARM variants. Remove them from cpu_functions
table.

ARM: Next round of cpufunc.* cleaning. Nobody uses flush_brnchtgt* functions,
delete them.

ARM: First round of cpufunc.* cleaning. All abort_fixup functions are
not currently used or defined. Delete them.

ARM: Remove TLB IPI.
We don't support SMP on ARMv6. All ARMv7 multicore cpus already uses
hardware broadcast for TLB and cache operations.

ARM: Remove outdated katelib.h.

Approved by: kib (mentor)

ARM: Refactor interrupt_enable/disable/restore.
Allow manipulation with PSR_A bit on ARMv6+.
Remove declaration of unused functions.

This effectively enables asynchronous aborts on early bootstrap stage,
which previously was not enabled due to an error in enable_interrupts().

PR: 201434
Reported by: Gregory Soutade <soutade at gmail.com>
Approved by: kib (mentor)

ARM: Remove trailing whitespace from sys/arm/include
No functional changes.

Approved by: kib (mentor)

It appears to be armv7_sleep is a duplication of armv7_cpu_sleep.
For consistency with the naming conventions used by the other
implementations kill armv7_sleep and keep armv7_cpu_sleep.

Differential Revision: https://reviews.freebsd.org/D2537
Submitted by: John Wehle
Reviewed by: ian@, andrew@

Remove support for CPU_XSCALE_80200. None of our configs support it, and
there wasn;t an option to enable it.

While here remove a check for CPU_ARM10 being defined as it has also been
removed.

Remove support for CPU_FA626TE. It's unused by any of our kernel configs.

pj4b_config and pj4bv7_setup are only used when CPU_MV_PJ4B is defined.

Remove arm1136 support. We don't have any configs that use it, and I don't
expect us to add support for any more arm11 SoCs.

Remove the bootconfig parsing. We never used it and always passed either an
empty string or NULL to the setup functions that called into it.

Remove unused cpufunc arm11 and armv6 code. While here only define the
remaining functions in the context we use them in.

Remove unused arm10_* functions. The remaining functions are only used in
mv configs.

Remove support for CPU_ARM10. No kernel configs could possibly use this as
it's not an available option. Along with this we will never support this
cpu type as very few arm10 chips were made.

Initial version of DTrace on ARM32.

Submitted by: Howard Su based on work by Oleksandr Tymoshenko
Reviewed by: ian, andrew, rpaulo, markj

Eliminate an unused macro whose name clashes now with a function in the
new cpu-v6.h. This should have been part of r276334.

Delete obsolete and unused PJ4B CPU functions

Since PJ4Bv7 uses armv7_ CPU functions only pj4b_config
function is necessary. Remove obsolete routines.

Add cpu_l2cache_drain_writebuf(), use it to implement generic_bs_barrier().

On modern ARM SoCs the L2 cache controller sits between the CPU and the
AXI bus, and most on-chip memory-mapped devices are on the AXI bus. We
map the device registers using the 'Device' memory attribute, which means
the memory is not cached, but writes to it are buffered. Ensuring that a
write has made it all the way to a device may require that the L2
controller take some action.

There is currently only one implementation of the new function, for the
PL310 cache controller. It invokes a function that the controller
manual calls "cache sync" but it actually has nothing to do with cache at
all, it triggers a drain of all pending store buffer writes and it blocks
until they complete.

The sheeva and xscale L2 controllers (which predate the concept of Device
memory) don't seem to have a corresponding function. It appears that the
standard armv5 drain_writebuf function includes draining all the way
through the L2 controller.

Make this declaration into a proper function prototype.

Provide a proper armv7 implementation of icache_sync_all rather than
using armv7_idcache_wbinv_all, because wbinv_all doesn't broadcast the
operation to other cores. In elf_cpu_load_file() use icache_sync_all()
and explain why it's needed (and why other sync operations aren't).

As part of doing this, all callers of cpu_icache_sync_all() were
inspected to ensure they weren't relying on the old side effect of
doing a wbinv_all along with the icache work.

Remove all traces of support for ARM chips prior to the arm9 series. We
never actually ran on these chips (other than using SA1 support in an
emulator to do the early porting to FreeBSD long long ago). The clutter
and complexity of some of this code keeps getting in the way of other
maintenance, so it's time to go.

Add an armv7 implementation of cpu_sleep(). The arm11/armv6 implementation
we've been using was actually just spinning due to ARM having redefined
the old 'wait for interrupt' operation via the system coprocessor as a nop
and replacing it with a WFI instruction.

Add a new cache maintenance function, idcache_inv_all, to the table, and
implementations for each of the chips we support. Most chips up through
armv6 can use the armv4 implementation which has a single coprocessor
opcode for this operation. The rather more complex armv7 implementation
comes from netbsd.

Add identification and necessary type checks for Krait CPU cores. Krait CPU is used in
Qualcomm Snapdragon S4 and Snapdragon 400/600/800 SoCs and has architectural
similarities to ARM Cortex-A15. As for development boards IFC6400 series embedded
boards from Inforce Computing uses Snapdragon S4 Pro/APQ8064.

Approved by: stas (mentor)

Switch off explicit broadcasting of the TLB flush operations for PJ4B CPU

Since CPU_MV_PJ4B describes ARMv7 compliant CPU there is no need for
sending an IPI each time when TLB is flushed in any way.

Tested by: kevlo

Remove not working and deprecated PJ4Bv6 support

Sheeva PJ4Bv6 - based chips were only prototypes for V7 class Armada
SoC family. Current in-tree support for PJ4Bv6 will not work and also
there should be no platforms in active use that would incorporate that
CPU revision.

Replace generic ARM11 option with more specific
support for ARM1136 and ARM1176

Submitted by: Daisuke Aoyama <aoyama at peach.ne.jp>
Obtained from: NetBSD

Don't define intr_disable and intr_restore as macros. The macros
interfere with structure fields of the same name in drivers, like
the intr_disable function pointer in struct cphy_ops in cxgb(4).
Instead define intr_disable and intr_restore as inline functions.

With intr_disable() an inline function, the I32_bit and F32_bit
macros now need to be visible in MI code and given the rather
poor names, this is not at all good. Define ARM_CPSR_F32 and
ARM_CPSR_I32 and use that instead of F32_bit and I32_bit (resp)
for now.

Add support for ARM11 cpufunc

Obtained from: NetBSD (partially)

Merging projects/armv6, part 1

Cummulative patch of changes that are not vendor-specific:
- ARMv6 and ARMv7 architecture support
- ARM SMP support
- VFP/Neon support
- ARM Generic Interrupt Controller driver
- Simplification of startup code for all platforms

trim trailing whitespace

Add basic cpu_sleep() support for Marvell SoCs. This drops my SheevaPlug's
heatsink termperature in open air from 49C to 43C when idle.

Add support for FA626TE.
Tested on GM8181 development board.

Add support for Cavium Econa CNS11XX ARM boards. These boards were
previously know by StarSemi STR9104.

Tested by the submitter on an Emprex NSD-100 board.

Submitted by: Yohanes Nugroho <yohanes at gmail.com>
Reviewed by: freebsd-arm, stas
Obtained from: //depot/projects/str91xx/...

Fix confusing naming of Marvell ARM CPU specific routines.

- The contents of 'feroceon_cpufuncs' dispatch table was really dedicated for the
new Sheeva CPU (in 88F6xxx and MV-78xxx SOCs), and NOT Feroceon.

- Feroceon CPU (in 88F5xxx SOCs) appears as a regular ARM926EJ-S core and does
not require dedicated routines.

This will be accompanied by a file rename commit.

Introduce low-level support for new Marvell core CPUs: 88FR131, 88FR571.

They are compliant with ARMv5TE and integrated on 88F6281 (Kirkwood) and
MV78100 (Discovery) system-on-chip families.

Obtained from: Marvell, Semihalf

Merge support from p4 (from NetBSD) for arm9e and arm10, arm11 cores. Not
yet connected to the build, but reduces diffs to p4 repo.

Obtained from: NetBSD

Add a new set of functions to handle L2 cache. Make them no-op for every
CPU except Xscale core 3.

Approved by: re (blanket)

Remove __P

Identify the xscale 81342.

Finally bring it support for the i80219 XScale processor.

Submitted by: Max M. Boyarov <m.boyarov bsd by>

Don't enable the FIQ in enable_interrupts() if F32_bit is not specified.
This has been committed by mistake.

Reported by: ssouhlal

Bring in bits I forgot while importing write back support for arm9.

Start all license statements with /*-

Implement enough to be able to enter and leave DDB.

Use interrupts_disable() and interrupts_restore() as intr_disable() and
intr_restore() instead of re-implement it.

Nuke disable_intr() and enable_intr(), as it already exists elsewhere.

Implement a stub breakpoint().

Import FreeBSD/arm kernel bits.
It only supports sa1110 (on simics) right now, but xscale support should come
soon.
Some of the initial work has been provided by :
Stephane Potvin <sepotvin at videotron.ca>
Most of this comes from NetBSD.