1/* $NetBSD: exception.S,v 1.13 2003/10/31 16:30:15 scw Exp $ */ 2 3/*- 4 * Copyright (c) 1994-1997 Mark Brinicombe. 5 * Copyright (c) 1994 Brini. 6 * All rights reserved. 7 * 8 * This code is derived from software written for Brini by Mark Brinicombe 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by Brini. 21 * 4. The name of the company nor the name of the author may be used to 22 * endorse or promote products derived from this software without specific 23 * prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED 26 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 27 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 28 * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 29 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 30 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 31 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 35 * SUCH DAMAGE. 36 * 37 * RiscBSD kernel project 38 * 39 * exception.S 40 * 41 * Low level handlers for exception vectors 42 * 43 * Created : 24/09/94 44 * 45 * Based on kate/display/abort.s 46 * 47 */ 48 49#include "assym.s" 50 51#include <machine/asm.h> 52#include <machine/armreg.h> 53#include <machine/asmacros.h> 54#include <machine/trap.h> 55 56__FBSDID("$FreeBSD$"); 57 58#ifdef KDTRACE_HOOKS 59 .bss 60 .align 4 61 .global _C_LABEL(dtrace_invop_jump_addr) 62_C_LABEL(dtrace_invop_jump_addr): 63 .word 0 64 .word 0 65#endif 66 67 .text 68 .align 2 69 70/* 71 * ASM macros for pushing and pulling trapframes from the stack 72 * 73 * These macros are used to handle the irqframe and trapframe structures 74 * defined above. 75 */ 76 77/* 78 * PUSHFRAME - macro to push a trap frame on the stack in the current mode 79 * Since the current mode is used, the SVC lr field is not defined. 80 * 81 * NOTE: r13 and r14 are stored separately as a work around for the 82 * SA110 rev 2 STM^ bug 83 */ 84#if __ARM_ARCH < 6 85#define PUSHFRAME \ 86 sub sp, sp, #4; /* Align the stack */ \ 87 str lr, [sp, #-4]!; /* Push the return address */ \ 88 sub sp, sp, #(4*17); /* Adjust the stack pointer */ \ 89 stmia sp, {r0-r12}; /* Push the user mode registers */ \ 90 add r0, sp, #(4*13); /* Adjust the stack pointer */ \ 91 stmia r0, {r13-r14}^; /* Push the user mode registers */ \ 92 mov r0, r0; /* NOP for previous instruction */ \ 93 mrs r0, spsr; /* Put the SPSR on the stack */ \ 94 str r0, [sp, #-4]!; \ 95 ldr r0, =ARM_RAS_START; \ 96 mov r1, #0; \ 97 str r1, [r0]; \ 98 mov r1, #0xffffffff; \ 99 str r1, [r0, #4]; 100#else 101#define PUSHFRAME \ 102 sub sp, sp, #4; /* Align the stack */ \ 103 str lr, [sp, #-4]!; /* Push the return address */ \ 104 sub sp, sp, #(4*17); /* Adjust the stack pointer */ \ 105 stmia sp, {r0-r12}; /* Push the user mode registers */ \ 106 add r0, sp, #(4*13); /* Adjust the stack pointer */ \ 107 stmia r0, {r13-r14}^; /* Push the user mode registers */ \ 108 mov r0, r0; /* NOP for previous instruction */ \ 109 mrs r0, spsr; /* Put the SPSR on the stack */ \ 110 str r0, [sp, #-4]!; 111#endif 112 113/* 114 * PULLFRAME - macro to pull a trap frame from the stack in the current mode 115 * Since the current mode is used, the SVC lr field is ignored. 116 */ 117 118#if __ARM_ARCH < 6 119#define PULLFRAME \ 120 ldr r0, [sp], #4; /* Get the SPSR from stack */ \ 121 msr spsr_fsxc, r0; \ 122 ldmia sp, {r0-r14}^; /* Restore registers (usr mode) */ \ 123 mov r0, r0; /* NOP for previous instruction */ \ 124 add sp, sp, #(4*17); /* Adjust the stack pointer */ \ 125 ldr lr, [sp], #4; /* Pull the return address */ \ 126 add sp, sp, #4 /* Align the stack */ 127#else 128#define PULLFRAME \ 129 ldr r0, [sp], #4 ; /* Get the SPSR from stack */ \ 130 msr spsr_fsxc, r0; \ 131 clrex; \ 132 ldmia sp, {r0-r14}^; /* Restore registers (usr mode) */ \ 133 mov r0, r0; /* NOP for previous instruction */ \ 134 add sp, sp, #(4*17); /* Adjust the stack pointer */ \ 135 ldr lr, [sp], #4; /* Pull the return address */ \ 136 add sp, sp, #4 /* Align the stack */ 137#endif 138 139/* 140 * PUSHFRAMEINSVC - macro to push a trap frame on the stack in SVC32 mode 141 * This should only be used if the processor is not currently in SVC32 142 * mode. The processor mode is switched to SVC mode and the trap frame is 143 * stored. The SVC lr field is used to store the previous value of 144 * lr in SVC mode. 145 * 146 * NOTE: r13 and r14 are stored separately as a work around for the 147 * SA110 rev 2 STM^ bug 148 */ 149#if __ARM_ARCH < 6 150#define PUSHFRAMEINSVC \ 151 stmdb sp, {r0-r3}; /* Save 4 registers */ \ 152 mov r0, lr; /* Save xxx32 r14 */ \ 153 mov r1, sp; /* Save xxx32 sp */ \ 154 mrs r3, spsr; /* Save xxx32 spsr */ \ 155 mrs r2, cpsr; /* Get the CPSR */ \ 156 bic r2, r2, #(PSR_MODE); /* Fix for SVC mode */ \ 157 orr r2, r2, #(PSR_SVC32_MODE); \ 158 msr cpsr_c, r2; /* Punch into SVC mode */ \ 159 mov r2, sp; /* Save SVC sp */ \ 160 bic sp, sp, #7; /* Align sp to an 8-byte addrress */ \ 161 sub sp, sp, #(4 * 17); /* Pad trapframe to keep alignment */ \ 162 /* and for dtrace to emulate push/pop */ \ 163 str r0, [sp, #-4]!; /* Push return address */ \ 164 str lr, [sp, #-4]!; /* Push SVC lr */ \ 165 str r2, [sp, #-4]!; /* Push SVC sp */ \ 166 msr spsr_fsxc, r3; /* Restore correct spsr */ \ 167 ldmdb r1, {r0-r3}; /* Restore 4 regs from xxx mode */ \ 168 sub sp, sp, #(4*15); /* Adjust the stack pointer */ \ 169 stmia sp, {r0-r12}; /* Push the user mode registers */ \ 170 add r0, sp, #(4*13); /* Adjust the stack pointer */ \ 171 stmia r0, {r13-r14}^; /* Push the user mode registers */ \ 172 mov r0, r0; /* NOP for previous instruction */ \ 173 ldr r5, =ARM_RAS_START; /* Check if there's any RAS */ \ 174 ldr r4, [r5, #4]; /* reset it to point at the */ \ 175 cmp r4, #0xffffffff; /* end of memory if necessary; */ \ 176 movne r1, #0xffffffff; /* leave value in r4 for later */ \ 177 strne r1, [r5, #4]; /* comparison against PC. */ \ 178 ldr r3, [r5]; /* Retrieve global RAS_START */ \ 179 cmp r3, #0; /* and reset it if non-zero. */ \ 180 movne r1, #0; /* If non-zero RAS_START and */ \ 181 strne r1, [r5]; /* PC was lower than RAS_END, */ \ 182 ldrne r1, [r0, #16]; /* adjust the saved PC so that */ \ 183 cmpne r4, r1; /* execution later resumes at */ \ 184 strhi r3, [r0, #16]; /* the RAS_START location. */ \ 185 mrs r0, spsr; \ 186 str r0, [sp, #-4]! 187#else 188#define PUSHFRAMEINSVC \ 189 stmdb sp, {r0-r3}; /* Save 4 registers */ \ 190 mov r0, lr; /* Save xxx32 r14 */ \ 191 mov r1, sp; /* Save xxx32 sp */ \ 192 mrs r3, spsr; /* Save xxx32 spsr */ \ 193 mrs r2, cpsr; /* Get the CPSR */ \ 194 bic r2, r2, #(PSR_MODE); /* Fix for SVC mode */ \ 195 orr r2, r2, #(PSR_SVC32_MODE); \ 196 msr cpsr_c, r2; /* Punch into SVC mode */ \ 197 mov r2, sp; /* Save SVC sp */ \ 198 bic sp, sp, #7; /* Align sp to an 8-byte addrress */ \ 199 sub sp, sp, #(4 * 17); /* Pad trapframe to keep alignment */ \ 200 /* and for dtrace to emulate push/pop */ \ 201 str r0, [sp, #-4]!; /* Push return address */ \ 202 str lr, [sp, #-4]!; /* Push SVC lr */ \ 203 str r2, [sp, #-4]!; /* Push SVC sp */ \ 204 msr spsr_fsxc, r3; /* Restore correct spsr */ \ 205 ldmdb r1, {r0-r3}; /* Restore 4 regs from xxx mode */ \ 206 sub sp, sp, #(4*15); /* Adjust the stack pointer */ \ 207 stmia sp, {r0-r12}; /* Push the user mode registers */ \ 208 add r0, sp, #(4*13); /* Adjust the stack pointer */ \ 209 stmia r0, {r13-r14}^; /* Push the user mode registers */ \ 210 mov r0, r0; /* NOP for previous instruction */ \ 211 mrs r0, spsr; /* Put the SPSR on the stack */ \ 212 str r0, [sp, #-4]! 213#endif 214 215/* 216 * PULLFRAMEFROMSVCANDEXIT - macro to pull a trap frame from the stack 217 * in SVC32 mode and restore the saved processor mode and PC. 218 * This should be used when the SVC lr register needs to be restored on 219 * exit. 220 */ 221 222#if __ARM_ARCH < 6 223#define PULLFRAMEFROMSVCANDEXIT \ 224 ldr r0, [sp], #4; /* Get the SPSR from stack */ \ 225 msr spsr_fsxc, r0; /* restore SPSR */ \ 226 ldmia sp, {r0-r14}^; /* Restore registers (usr mode) */ \ 227 mov r0, r0; /* NOP for previous instruction */ \ 228 add sp, sp, #(4*15); /* Adjust the stack pointer */ \ 229 ldmia sp, {sp, lr, pc}^ /* Restore lr and exit */ 230#else 231#define PULLFRAMEFROMSVCANDEXIT \ 232 ldr r0, [sp], #4; /* Get the SPSR from stack */ \ 233 msr spsr_fsxc, r0; /* restore SPSR */ \ 234 clrex; \ 235 ldmia sp, {r0-r14}^; /* Restore registers (usr mode) */ \ 236 mov r0, r0; /* NOP for previous instruction */ \ 237 add sp, sp, #(4*15); /* Adjust the stack pointer */ \ 238 ldmia sp, {sp, lr, pc}^ /* Restore lr and exit */ 239#endif 240 241/* 242 * Unwind hints so we can unwind past functions that use 243 * PULLFRAMEFROMSVCANDEXIT. They are run in reverse order. 244 * As the last thing we do is restore the stack pointer 245 * we can ignore the padding at the end of struct trapframe. 246 */ 247#define UNWINDSVCFRAME \ 248 .save {r13-r15}; /* Restore sp, lr, pc */ \ 249 .pad #(2*4); /* Skip user sp and lr */ \ 250 .save {r0-r12}; /* Restore r0-r12 */ \ 251 .pad #(4) /* Skip spsr */ 252 253#define DO_AST \ 254 ldr r0, [sp]; /* Get the SPSR from stack */ \ 255 mrs r4, cpsr; /* save CPSR */ \ 256 orr r1, r4, #(PSR_I|PSR_F); \ 257 msr cpsr_c, r1; /* Disable interrupts */ \ 258 and r0, r0, #(PSR_MODE); /* Returning to USR mode? */ \ 259 teq r0, #(PSR_USR32_MODE); \ 260 bne 2f; /* Nope, get out now */ \ 261 bic r4, r4, #(PSR_I|PSR_F); \ 2621: GET_CURTHREAD_PTR(r5); \ 263 ldr r1, [r5, #(TD_FLAGS)]; \ 264 and r1, r1, #(TDF_ASTPENDING|TDF_NEEDRESCHED); \ 265 teq r1, #0; \ 266 beq 2f; /* Nope. Just bail */ \ 267 msr cpsr_c, r4; /* Restore interrupts */ \ 268 mov r0, sp; \ 269 bl _C_LABEL(ast); /* ast(frame) */ \ 270 orr r0, r4, #(PSR_I|PSR_F); \ 271 msr cpsr_c, r0; \ 272 b 1b; \ 2732: 274 275 276/* 277 * Entry point for a Software Interrupt (SWI). 278 * 279 * The hardware switches to svc32 mode on a swi, so we're already on the 280 * right stack; just build a trapframe and call the handler. 281 */ 282ASENTRY_NP(swi_entry) 283 PUSHFRAME /* Build the trapframe on the */ 284 mov r0, sp /* scv32 stack, pass it to the */ 285 bl _C_LABEL(swi_handler) /* swi handler. */ 286 /* 287 * The fork_trampoline() code in swtch.S aranges for the MI fork_exit() 288 * to return to swi_exit here, to return to userland. The net effect is 289 * that a newly created thread appears to return from a SWI just like 290 * the parent thread that created it. 291 */ 292ASEENTRY_NP(swi_exit) 293 DO_AST /* Handle pending signals. */ 294 PULLFRAME /* Deallocate trapframe. */ 295 movs pc, lr /* Return to userland. */ 296 STOP_UNWINDING /* Don't unwind into user mode. */ 297EEND(swi_exit) 298END(swi_entry) 299 300/* 301 * Standard exception exit handler. 302 * 303 * This is used to return from all exceptions except SWI. It uses DO_AST and 304 * PULLFRAMEFROMSVCANDEXIT and can only be called if the exception entry code 305 * used PUSHFRAMEINSVC. 306 * 307 * If the return is to user mode, this uses DO_AST to deliver any pending 308 * signals and/or handle TDF_NEEDRESCHED first. 309 */ 310ASENTRY_NP(exception_exit) 311 DO_AST /* Handle pending signals. */ 312 PULLFRAMEFROMSVCANDEXIT /* Return. */ 313 UNWINDSVCFRAME /* Special unwinding for exceptions. */ 314END(exception_exit) 315 316/* 317 * Entry point for a Prefetch Abort exception. 318 * 319 * The hardware switches to the abort mode stack; we switch to svc32 before 320 * calling the handler, then return directly to the original mode/stack 321 * on exit (without transitioning back through the abort mode stack). 322 */ 323ASENTRY_NP(prefetch_abort_entry) 324#ifdef __XSCALE__ 325 nop /* Make absolutely sure any pending */ 326 nop /* imprecise aborts have occurred. */ 327#endif 328 sub lr, lr, #4 /* Adjust the lr. Transition to scv32 */ 329 PUSHFRAMEINSVC /* mode stack, build trapframe there. */ 330 adr lr, exception_exit /* Return from handler via standard */ 331 mov r0, sp /* exception exit routine. Pass the */ 332 mov r1, #1 /* Type flag */ 333 b _C_LABEL(abort_handler) 334END(prefetch_abort_entry) 335 336/* 337 * Entry point for a Data Abort exception. 338 * 339 * The hardware switches to the abort mode stack; we switch to svc32 before 340 * calling the handler, then return directly to the original mode/stack 341 * on exit (without transitioning back through the abort mode stack). 342 */ 343ASENTRY_NP(data_abort_entry) 344#ifdef __XSCALE__ 345 nop /* Make absolutely sure any pending */ 346 nop /* imprecise aborts have occurred. */ 347#endif 348 sub lr, lr, #8 /* Adjust the lr. Transition to scv32 */ 349 PUSHFRAMEINSVC /* mode stack, build trapframe there. */ 350 adr lr, exception_exit /* Exception exit routine */ 351 mov r0, sp /* Trapframe to the handler */ 352 mov r1, #0 /* Type flag */ 353 b _C_LABEL(abort_handler) 354END(data_abort_entry) 355 356/* 357 * Entry point for an Undefined Instruction exception. 358 * 359 * The hardware switches to the undefined mode stack; we switch to svc32 before 360 * calling the handler, then return directly to the original mode/stack 361 * on exit (without transitioning back through the undefined mode stack). 362 */ 363ASENTRY_NP(undefined_entry) 364 PUSHFRAMEINSVC /* mode stack, build trapframe there. */ 365 mov r4, r0 /* R0 contains SPSR */ 366 adr lr, exception_exit /* Return from handler via standard */ 367 mov r0, sp /* exception exit routine. pass frame */ 368 369 ldr r2, [sp, #(TF_PC)] /* load pc */ 370#if __ARM_ARCH >= 7 371 tst r4, #(PSR_T) /* test if PSR_T */ 372 subne r2, r2, #(THUMB_INSN_SIZE) 373 subeq r2, r2, #(INSN_SIZE) 374#else 375 sub r2, r2, #(INSN_SIZE) /* fix pc */ 376#endif 377 str r2, [sp, #TF_PC] /* store pc */ 378 379#ifdef KDTRACE_HOOKS 380 /* Check if dtrace is enabled */ 381 ldr r1, =_C_LABEL(dtrace_invop_jump_addr) 382 ldr r3, [r1] 383 cmp r3, #0 384 beq undefinedinstruction 385 386 and r4, r4, #(PSR_MODE) /* Mask out unneeded bits */ 387 cmp r4, #(PSR_USR32_MODE) /* Check if we came from usermode */ 388 beq undefinedinstruction 389 390 ldr r4, [r2] /* load instrution */ 391 ldr r1, =FBT_BREAKPOINT /* load fbt inv op */ 392 cmp r1, r4 393 bne undefinedinstruction 394 395 bx r3 /* call invop_jump_addr */ 396#endif 397 b undefinedinstruction /* call stadnard handler */ 398END(undefined_entry) 399 400/* 401 * Entry point for a normal IRQ. 402 * 403 * The hardware switches to the IRQ mode stack; we switch to svc32 before 404 * calling the handler, then return directly to the original mode/stack 405 * on exit (without transitioning back through the IRQ mode stack). 406 */ 407ASENTRY_NP(irq_entry) 408 sub lr, lr, #4 /* Adjust the lr. Transition to scv32 */ 409 PUSHFRAMEINSVC /* mode stack, build trapframe there. */ 410 adr lr, exception_exit /* Return from handler via standard */ 411 mov r0, sp /* exception exit routine. Pass the */ 412 b _C_LABEL(intr_irq_handler)/* trapframe to the handler. */ 413END(irq_entry) 414 415/* 416 * Entry point for an FIQ interrupt. 417 * 418 * We don't currently support FIQ handlers very much. Something can 419 * install itself in the FIQ vector using code (that may or may not work 420 * these days) in fiq.c. If nobody does that and an FIQ happens, this 421 * default handler just disables FIQs and otherwise ignores it. 422 */ 423ASENTRY_NP(fiq_entry) 424 mrs r8, cpsr /* FIQ handling isn't supported, */ 425 bic r8, #(PSR_F) /* just disable FIQ and return. */ 426 msr cpsr_c, r8 /* The r8 we trash here is the */ 427 subs pc, lr, #4 /* banked FIQ-mode r8. */ 428END(fiq_entry) 429 430/* 431 * Entry point for an Address Exception exception. 432 * This is an arm26 exception that should never happen. 433 */ 434ASENTRY_NP(addr_exception_entry) 435 mov r3, lr 436 mrs r2, spsr 437 mrs r1, cpsr 438 adr r0, Laddr_exception_msg 439 b _C_LABEL(panic) 440Laddr_exception_msg: 441 .asciz "Address Exception CPSR=0x%08x SPSR=0x%08x LR=0x%08x\n" 442 .balign 4 443END(addr_exception_entry) 444 445/* 446 * Entry point for the system Reset vector. 447 * This should never happen, so panic. 448 */ 449ASENTRY_NP(reset_entry) 450 mov r1, lr 451 adr r0, Lreset_panicmsg 452 b _C_LABEL(panic) 453 /* NOTREACHED */ 454Lreset_panicmsg: 455 .asciz "Reset vector called, LR = 0x%08x" 456 .balign 4 457END(reset_entry) 458 459/* 460 * page0 and page0_data -- An image of the ARM vectors which is copied to 461 * the ARM vectors page (high or low) as part of CPU initialization. The 462 * code that does the copy assumes that page0_data holds one 32-bit word 463 * of data for each of the predefined ARM vectors. It also assumes that 464 * page0_data follows the vectors in page0, but other stuff can appear 465 * between the two. We currently leave room between the two for some fiq 466 * handler code to be copied in. 467 */ 468 .global _C_LABEL(page0), _C_LABEL(page0_data) 469 470_C_LABEL(page0): 471 ldr pc, .Lreset_entry 472 ldr pc, .Lundefined_entry 473 ldr pc, .Lswi_entry 474 ldr pc, .Lprefetch_abort_entry 475 ldr pc, .Ldata_abort_entry 476 ldr pc, .Laddr_exception_entry 477 ldr pc, .Lirq_entry 478.fiqv: ldr pc, .Lfiq_entry 479 .space 256 /* room for some fiq handler code */ 480 481_C_LABEL(page0_data): 482.Lreset_entry: .word reset_entry 483.Lundefined_entry: .word undefined_entry 484.Lswi_entry: .word swi_entry 485.Lprefetch_abort_entry: .word prefetch_abort_entry 486.Ldata_abort_entry: .word data_abort_entry 487.Laddr_exception_entry: .word addr_exception_entry 488.Lirq_entry: .word irq_entry 489.Lfiq_entry: .word fiq_entry 490 491/* 492 * These items are used by the code in fiq.c to install what it calls the 493 * "null" handler. It's actually our default vector entry that just jumps 494 * to the default handler which just disables FIQs and returns. 495 */ 496 .global _C_LABEL(fiq_nullhandler_code), _C_LABEL(fiq_nullhandler_size) 497 498_C_LABEL(fiq_nullhandler_code): 499 .word .fiqv 500_C_LABEL(fiq_nullhandler_size): 501 .word 4 502 503 504