/linux-master/drivers/gpu/drm/amd/pm/powerplay/smumgr/ |
H A D | vegam_smumgr.c | 1246 SMU75_Discrete_MCArbDramTimingTableEntry *arb_regs) 1268 arb_regs->McArbDramTiming = PP_HOST_TO_SMC_UL(dram_timing); 1269 arb_regs->McArbDramTiming2 = PP_HOST_TO_SMC_UL(dram_timing2); 1270 arb_regs->McArbBurstTime = PP_HOST_TO_SMC_UL(burst_time); 1271 arb_regs->McArbRfshRate = PP_HOST_TO_SMC_UL(rfsh_rate); 1272 arb_regs->McArbMisc3 = PP_HOST_TO_SMC_UL(misc3); 1281 struct SMU75_Discrete_MCArbDramTimingTable arb_regs; local 1285 memset(&arb_regs, 0, sizeof(SMU75_Discrete_MCArbDramTimingTable)); 1292 &arb_regs.entries[i][j]); 1301 (uint8_t *)&arb_regs, 1244 vegam_populate_memory_timing_parameters(struct pp_hwmgr *hwmgr, int32_t eng_clock, int32_t mem_clock, SMU75_Discrete_MCArbDramTimingTableEntry *arb_regs) argument [all...] |
H A D | fiji_smumgr.c | 1495 struct SMU73_Discrete_MCArbDramTimingTableEntry *arb_regs) 1515 arb_regs->McArbDramTiming = PP_HOST_TO_SMC_UL(dram_timing); 1516 arb_regs->McArbDramTiming2 = PP_HOST_TO_SMC_UL(dram_timing2); 1517 arb_regs->McArbBurstTime = (uint8_t)burstTime; 1518 arb_regs->TRRDS = (uint8_t)trrds; 1519 arb_regs->TRRDL = (uint8_t)trrdl; 1528 struct SMU73_Discrete_MCArbDramTimingTable arb_regs; local 1537 &arb_regs.entries[i][j]); 1547 (uint8_t *)&arb_regs, 1493 fiji_populate_memory_timing_parameters(struct pp_hwmgr *hwmgr, int32_t eng_clock, int32_t mem_clock, struct SMU73_Discrete_MCArbDramTimingTableEntry *arb_regs) argument
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H A D | iceland_smumgr.c | 1586 struct SMU71_Discrete_MCArbDramTimingTableEntry *arb_regs 1604 arb_regs->McArbDramTiming = PP_HOST_TO_SMC_UL(dramTiming); 1605 arb_regs->McArbDramTiming2 = PP_HOST_TO_SMC_UL(dramTiming2); 1606 arb_regs->McArbBurstTime = (uint8_t)burstTime; 1616 SMU71_Discrete_MCArbDramTimingTable arb_regs; local 1619 memset(&arb_regs, 0x00, sizeof(SMU71_Discrete_MCArbDramTimingTable)); 1626 &arb_regs.entries[i][j]); 1638 (uint8_t *)&arb_regs,
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H A D | tonga_smumgr.c | 1461 struct SMU72_Discrete_MCArbDramTimingTableEntry *arb_regs 1479 arb_regs->McArbDramTiming = PP_HOST_TO_SMC_UL(dramTiming); 1480 arb_regs->McArbDramTiming2 = PP_HOST_TO_SMC_UL(dramTiming2); 1481 arb_regs->McArbBurstTime = (uint8_t)burstTime; 1492 SMU72_Discrete_MCArbDramTimingTable arb_regs; local 1495 memset(&arb_regs, 0x00, sizeof(SMU72_Discrete_MCArbDramTimingTable)); 1502 &arb_regs.entries[i][j]); 1513 (uint8_t *)&arb_regs,
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H A D | ci_smumgr.c | 1625 struct SMU7_Discrete_MCArbDramTimingTableEntry *arb_regs 1643 arb_regs->McArbDramTiming = PP_HOST_TO_SMC_UL(dramTiming); 1644 arb_regs->McArbDramTiming2 = PP_HOST_TO_SMC_UL(dramTiming2); 1645 arb_regs->McArbBurstTime = (uint8_t)burstTime; 1655 SMU7_Discrete_MCArbDramTimingTable arb_regs; local 1658 memset(&arb_regs, 0x00, sizeof(SMU7_Discrete_MCArbDramTimingTable)); 1665 &arb_regs.entries[i][j]); 1676 (uint8_t *)&arb_regs,
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H A D | polaris10_smumgr.c | 1466 SMU74_Discrete_MCArbDramTimingTableEntry *arb_regs) 1483 arb_regs->McArbDramTiming = PP_HOST_TO_SMC_UL(dram_timing); 1484 arb_regs->McArbDramTiming2 = PP_HOST_TO_SMC_UL(dram_timing2); 1485 arb_regs->McArbBurstTime = (uint8_t)burst_time; 1494 struct SMU74_Discrete_MCArbDramTimingTable arb_regs; local 1503 &arb_regs.entries[i][j]); 1514 (uint8_t *)&arb_regs, 1464 polaris10_populate_memory_timing_parameters(struct pp_hwmgr *hwmgr, int32_t eng_clock, int32_t mem_clock, SMU74_Discrete_MCArbDramTimingTableEntry *arb_regs) argument
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/linux-master/drivers/gpu/drm/radeon/ |
H A D | ni_dpm.c | 1615 SMC_NIslands_MCArbDramTimingRegisterSet *arb_regs) 1620 arb_regs->mc_arb_rfsh_rate = 1629 arb_regs->mc_arb_dram_timing = cpu_to_be32(dram_timing); 1630 arb_regs->mc_arb_dram_timing2 = cpu_to_be32(dram_timing2); 1642 SMC_NIslands_MCArbDramTimingRegisterSet arb_regs = { 0 }; local 1646 ret = ni_populate_memory_timing_parameters(rdev, &state->performance_levels[i], &arb_regs); 1654 (u8 *)&arb_regs, 1613 ni_populate_memory_timing_parameters(struct radeon_device *rdev, struct rv7xx_pl *pl, SMC_NIslands_MCArbDramTimingRegisterSet *arb_regs) argument
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H A D | ci_dpm.c | 2481 SMU7_Discrete_MCArbDramTimingTableEntry *arb_regs) 2495 arb_regs->McArbDramTiming = cpu_to_be32(dram_timing); 2496 arb_regs->McArbDramTiming2 = cpu_to_be32(dram_timing2); 2497 arb_regs->McArbBurstTime = (u8)burst_time; 2505 SMU7_Discrete_MCArbDramTimingTable arb_regs; local 2509 memset(&arb_regs, 0, sizeof(SMU7_Discrete_MCArbDramTimingTable)); 2516 &arb_regs.entries[i][j]); 2525 (u8 *)&arb_regs, 2478 ci_populate_memory_timing_parameters(struct radeon_device *rdev, u32 sclk, u32 mclk, SMU7_Discrete_MCArbDramTimingTableEntry *arb_regs) argument
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H A D | si_dpm.c | 4230 SMC_SIslands_MCArbDramTimingRegisterSet *arb_regs) 4236 arb_regs->mc_arb_rfsh_rate = 4247 arb_regs->mc_arb_dram_timing = cpu_to_be32(dram_timing); 4248 arb_regs->mc_arb_dram_timing2 = cpu_to_be32(dram_timing2); 4249 arb_regs->mc_arb_burst_time = (u8)burst_time; 4260 SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 }; local 4264 ret = si_populate_memory_timing_parameters(rdev, &state->performance_levels[i], &arb_regs); 4271 (u8 *)&arb_regs, 4600 SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 }; local 4604 &arb_regs); 4228 si_populate_memory_timing_parameters(struct radeon_device *rdev, struct rv7xx_pl *pl, SMC_SIslands_MCArbDramTimingRegisterSet *arb_regs) argument [all...] |
/linux-master/drivers/gpu/drm/amd/pm/legacy-dpm/ |
H A D | si_dpm.c | 4753 SMC_SIslands_MCArbDramTimingRegisterSet *arb_regs) 4759 arb_regs->mc_arb_rfsh_rate = 4770 arb_regs->mc_arb_dram_timing = cpu_to_be32(dram_timing); 4771 arb_regs->mc_arb_dram_timing2 = cpu_to_be32(dram_timing2); 4772 arb_regs->mc_arb_burst_time = (u8)burst_time; 4783 SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 }; local 4787 ret = si_populate_memory_timing_parameters(adev, &state->performance_levels[i], &arb_regs); 4794 (u8 *)&arb_regs, 5147 SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 }; local 5151 &arb_regs); 4751 si_populate_memory_timing_parameters(struct amdgpu_device *adev, struct rv7xx_pl *pl, SMC_SIslands_MCArbDramTimingRegisterSet *arb_regs) argument [all...] |