Searched refs:anatop_base (Results 1 - 7 of 7) sorted by path
/linux-master/arch/arm/mach-imx/ |
H A D | anatop.c | 97 void __iomem *anatop_base; local 104 anatop_base = of_iomap(np, 0); 105 WARN_ON(!anatop_base); 110 digprog = readl_relaxed(anatop_base + offset); 111 iounmap(anatop_base);
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/linux-master/drivers/clk/imx/ |
H A D | clk-imx6q.c | 396 static void disable_anatop_clocks(void __iomem *anatop_base) argument 401 reg = readl_relaxed(anatop_base + CCM_ANALOG_PFD_528); 408 writel_relaxed(reg, anatop_base + CCM_ANALOG_PFD_528); 411 reg = readl_relaxed(anatop_base + CCM_ANALOG_PFD_480); 413 writel_relaxed(reg, anatop_base + CCM_ANALOG_PFD_480); 416 reg = readl_relaxed(anatop_base + CCM_ANALOG_PLL_VIDEO); 418 writel_relaxed(reg, anatop_base + CCM_ANALOG_PLL_VIDEO); 439 void __iomem *anatop_base, *base; local 461 anatop_base = base = of_iomap(np, 0); 644 disable_anatop_clocks(anatop_base); [all...] |
H A D | clk-imx6sl.c | 103 static void __iomem *anatop_base; variable 132 if ((readl_relaxed(anatop_base + PLL_ARM) & 146 saved_pll_arm = val = readl_relaxed(anatop_base + PLL_ARM); 149 writel_relaxed(val, anatop_base + PLL_ARM); 150 while (!(readl_relaxed(anatop_base + PLL_ARM) & BM_PLL_ARM_LOCK)) 153 writel_relaxed(saved_pll_arm, anatop_base + PLL_ARM); 206 anatop_base = base;
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H A D | clk-imx8mp.c | 412 void __iomem *anatop_base, *ccm_base; local 416 anatop_base = devm_of_iomap(dev, np, 0, NULL); 418 if (WARN_ON(IS_ERR(anatop_base))) 419 return PTR_ERR(anatop_base); 441 hws[IMX8MP_AUDIO_PLL1_REF_SEL] = imx_clk_hw_mux("audio_pll1_ref_sel", anatop_base + 0x0, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); 442 hws[IMX8MP_AUDIO_PLL2_REF_SEL] = imx_clk_hw_mux("audio_pll2_ref_sel", anatop_base + 0x14, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); 443 hws[IMX8MP_VIDEO_PLL1_REF_SEL] = imx_clk_hw_mux("video_pll1_ref_sel", anatop_base + 0x28, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); 444 hws[IMX8MP_DRAM_PLL_REF_SEL] = imx_clk_hw_mux("dram_pll_ref_sel", anatop_base + 0x50, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); 445 hws[IMX8MP_GPU_PLL_REF_SEL] = imx_clk_hw_mux("gpu_pll_ref_sel", anatop_base + 0x64, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); 446 hws[IMX8MP_VPU_PLL_REF_SEL] = imx_clk_hw_mux("vpu_pll_ref_sel", anatop_base [all...] |
H A D | clk-imx93.c | 266 void __iomem *base, *anatop_base; local 293 anatop_base = devm_of_iomap(dev, np, 0, NULL); 295 if (WARN_ON(IS_ERR(anatop_base))) { 296 ret = PTR_ERR(anatop_base); 301 anatop_base + 0x1000, 303 clks[IMX93_CLK_AUDIO_PLL] = imx_clk_fracn_gppll("audio_pll", "osc_24m", anatop_base + 0x1200, 305 clks[IMX93_CLK_VIDEO_PLL] = imx_clk_fracn_gppll("video_pll", "osc_24m", anatop_base + 0x1400,
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H A D | clk-vf610.c | 56 #define PFD_PLL1_BASE (anatop_base + 0x2b0) 57 #define PFD_PLL2_BASE (anatop_base + 0x100) 58 #define PFD_PLL3_BASE (anatop_base + 0xf0) 59 #define PLL1_CTRL (anatop_base + 0x270) 60 #define PLL2_CTRL (anatop_base + 0x30) 61 #define PLL3_CTRL (anatop_base + 0x10) 62 #define PLL4_CTRL (anatop_base + 0x70) 63 #define PLL5_CTRL (anatop_base + 0xe0) 64 #define PLL6_CTRL (anatop_base + 0xa0) 65 #define PLL7_CTRL (anatop_base 68 static void __iomem *anatop_base; variable [all...] |
/linux-master/drivers/soc/imx/ |
H A D | soc-imx8m.c | 134 void __iomem *anatop_base; local 141 anatop_base = of_iomap(np, 0); 142 WARN_ON(!anatop_base); 144 rev = readl_relaxed(anatop_base + ANADIG_DIGPROG_IMX8MM); 146 iounmap(anatop_base);
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