Searched refs:UVD_SUVD_CGC_GATE__IME_HEVC_MASK (Results 1 - 16 of 16) sorted by path

/linux-master/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_sh_mask.h478 #define UVD_SUVD_CGC_GATE__IME_HEVC_MASK 0x01000000L macro
H A Dvcn_2_0_0_sh_mask.h3233 #define UVD_SUVD_CGC_GATE__IME_HEVC_MASK 0x01000000L macro
H A Dvcn_2_5_sh_mask.h2107 #define UVD_SUVD_CGC_GATE__IME_HEVC_MASK 0x01000000L macro
H A Dvcn_2_6_0_sh_mask.h3778 #define UVD_SUVD_CGC_GATE__IME_HEVC_MASK 0x01000000L macro
H A Dvcn_3_0_0_sh_mask.h2843 #define UVD_SUVD_CGC_GATE__IME_HEVC_MASK 0x01000000L macro
H A Dvcn_4_0_0_sh_mask.h1360 #define UVD_SUVD_CGC_GATE__IME_HEVC_MASK 0x01000000L macro
H A Dvcn_4_0_3_sh_mask.h1360 #define UVD_SUVD_CGC_GATE__IME_HEVC_MASK 0x01000000L macro
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H A Dvcn_4_0_5_sh_mask.h1356 #define UVD_SUVD_CGC_GATE__IME_HEVC_MASK 0x01000000L macro
H A Dvcn_5_0_0_sh_mask.h1165 #define UVD_SUVD_CGC_GATE__IME_HEVC_MASK 0x01000000L macro
/linux-master/drivers/gpu/drm/amd/amdgpu/
H A Dvcn_v1_0.c553 | UVD_SUVD_CGC_GATE__IME_HEVC_MASK);
H A Dvcn_v2_0.c578 | UVD_SUVD_CGC_GATE__IME_HEVC_MASK);
H A Dvcn_v2_5.c667 | UVD_SUVD_CGC_GATE__IME_HEVC_MASK);
H A Dvcn_v3_0.c788 | UVD_SUVD_CGC_GATE__IME_HEVC_MASK
H A Dvcn_v4_0.c754 | UVD_SUVD_CGC_GATE__IME_HEVC_MASK);
H A Dvcn_v4_0_3.c588 | UVD_SUVD_CGC_GATE__IME_HEVC_MASK);
H A Dvcn_v4_0_5.c689 | UVD_SUVD_CGC_GATE__IME_HEVC_MASK);

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