Searched refs:UVD_DPG_LMA_CTL__READ_WRITE__SHIFT (Results 1 - 11 of 11) sorted by path

/linux-master/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_sh_mask.h91 #define UVD_DPG_LMA_CTL__READ_WRITE__SHIFT 0x0 macro
H A Dvcn_2_0_0_sh_mask.h1547 #define UVD_DPG_LMA_CTL__READ_WRITE__SHIFT 0x0 macro
H A Dvcn_2_5_sh_mask.h1550 #define UVD_DPG_LMA_CTL__READ_WRITE__SHIFT 0x0 macro
H A Dvcn_2_6_0_sh_mask.h2988 #define UVD_DPG_LMA_CTL__READ_WRITE__SHIFT 0x0 macro
H A Dvcn_3_0_0_sh_mask.h2096 #define UVD_DPG_LMA_CTL__READ_WRITE__SHIFT 0x0 macro
H A Dvcn_4_0_0_sh_mask.h6377 #define UVD_DPG_LMA_CTL__READ_WRITE__SHIFT 0x0 macro
H A Dvcn_4_0_3_sh_mask.h7193 #define UVD_DPG_LMA_CTL__READ_WRITE__SHIFT 0x0 macro
[all...]
H A Dvcn_4_0_5_sh_mask.h6210 #define UVD_DPG_LMA_CTL__READ_WRITE__SHIFT 0x0 macro
H A Dvcn_5_0_0_sh_mask.h5387 #define UVD_DPG_LMA_CTL__READ_WRITE__SHIFT 0x0 macro
/linux-master/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_jpeg.h57 (0x0 << UVD_DPG_LMA_CTL__READ_WRITE__SHIFT | \
H A Damdgpu_vcn.h138 (0x0 << UVD_DPG_LMA_CTL__READ_WRITE__SHIFT | \
152 (0x1 << UVD_DPG_LMA_CTL__READ_WRITE__SHIFT | \
194 (0x1 << UVD_DPG_LMA_CTL__READ_WRITE__SHIFT | \

Completed in 1166 milliseconds