Searched refs:UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT (Results 1 - 11 of 11) sorted by path

/linux-master/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_sh_mask.h95 #define UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT 0x10 macro
H A Dvcn_2_0_0_sh_mask.h1551 #define UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT 0x10 macro
H A Dvcn_2_5_sh_mask.h1554 #define UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT 0x10 macro
H A Dvcn_2_6_0_sh_mask.h2992 #define UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT 0x10 macro
H A Dvcn_3_0_0_sh_mask.h2100 #define UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT 0x10 macro
H A Dvcn_4_0_0_sh_mask.h6381 #define UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT 0x10 macro
H A Dvcn_4_0_3_sh_mask.h7197 #define UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT 0x10 macro
[all...]
H A Dvcn_4_0_5_sh_mask.h6214 #define UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT 0xe macro
H A Dvcn_5_0_0_sh_mask.h5391 #define UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT 0xe macro
/linux-master/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_jpeg.h44 offset << UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT | \
59 offset << UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT)); \
H A Damdgpu_vcn.h86 << UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT) | \
98 << UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT) | \
140 offset << UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT)); \
154 offset << UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT)); \
196 offset << UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT)); \

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