Searched refs:TCR (Results 1 - 25 of 33) sorted by relevance

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/linux-master/drivers/staging/rtl8712/
H A Drtl8712_cmdctrl_regdef.h12 #define TCR (RTL8712_CMDCTRL_ + 0x0004) macro
H A Dhal_init.c210 tmp16 = r8712_read16(adapter, TCR);
213 tmp16 = r8712_read16(adapter, TCR);
239 tmp16 = r8712_read16(adapter, TCR);
242 tmp16 = r8712_read16(adapter, TCR);
261 r8712_read32(adapter, TCR);
265 tmp16 = r8712_read16(adapter, TCR);
268 tmp16 = r8712_read16(adapter, TCR);
290 tmp16 = r8712_read16(adapter, TCR);
293 tmp16 = r8712_read16(adapter, TCR);
306 tmp16 = r8712_read16(adapter, TCR);
[all...]
H A Dusb_halinit.c264 val8 = r8712_read8(adapter, TCR);
/linux-master/drivers/clocksource/
H A Dtimer-keystone.c24 #define TCR 0x20 macro
79 tcr = keystone_timer_readl(TCR);
86 keystone_timer_writel(off, TCR);
102 keystone_timer_writel(tcr, TCR);
110 tcr = keystone_timer_readl(TCR);
114 keystone_timer_writel(tcr, TCR);
178 keystone_timer_writel(0, TCR);
H A Dsh_tmu.c73 #define TCR 2 /* channel register */ macro
99 if (reg_nr == TCR)
121 if (reg_nr == TCR)
164 sh_tmu_write(ch, TCR, TCR_TPSC_CLK4);
189 sh_tmu_write(ch, TCR, TCR_TPSC_CLK4);
216 sh_tmu_read(ch, TCR);
219 sh_tmu_write(ch, TCR, TCR_UNIE | TCR_TPSC_CLK4);
239 sh_tmu_write(ch, TCR, TCR_TPSC_CLK4);
241 sh_tmu_write(ch, TCR, TCR_UNIE | TCR_TPSC_CLK4);
H A Dsh_mtu2.c56 #define TCR 0 /* channel register */ macro
147 [TCR] = 0,
231 sh_mtu2_write(ch, TCR, TCR_CCLR_TGRA | TCR_TPSC_P64);
/linux-master/arch/sh/include/asm/
H A Ddma-register.h16 #define TCR 0x08 /* Transfer Count Register */ macro
/linux-master/drivers/watchdog/
H A Ddavinci_wdt.c36 #define TCR (0x20) macro
40 /* TCR bit definitions */
80 iowrite32(0, davinci_wdt->base + TCR);
94 iowrite32(ENAMODE12_PERIODIC, davinci_wdt->base + TCR);
96 * TIM12, TIM34, PRD12, PRD34, TCR, TGCR, WDTCR are
149 iowrite32(0, davinci_wdt->base + TCR);
/linux-master/drivers/net/wireless/realtek/rtlwifi/rtl8192se/
H A Dfw.c40 cpustatus = rtl_read_byte(rtlpriv, TCR);
207 cpustatus = rtl_read_byte(rtlpriv, TCR);
224 cpustatus = rtl_read_byte(rtlpriv, TCR);
247 cpustatus = rtl_read_byte(rtlpriv, TCR);
267 cpustatus = rtl_read_byte(rtlpriv, TCR);
284 /* If right here, we can set TCR/RCR to desired value */
286 tmpu4b = rtl_read_dword(rtlpriv, TCR);
287 rtl_write_dword(rtlpriv, TCR, (tmpu4b & (~TCR_ICV)));
H A Dhw.c574 rtl_write_byte(rtlpriv, TCR, 0);
714 tmpu1b = rtl_read_byte(rtlpriv, TCR);
722 pr_err("Polling TXDMA_INIT_VALUE timeout!! Current TCR(%#x)\n",
760 /* Set TCR TX DMA pre 2 FULL enable bit */
761 rtl_write_dword(rtlpriv, TCR, rtl_read_dword(rtlpriv, TCR) |
1178 temp = rtl_read_dword(rtlpriv, TCR);
1179 rtl_write_dword(rtlpriv, TCR, temp & (~BIT(8)));
1180 rtl_write_dword(rtlpriv, TCR, temp | BIT(8));
1421 rtl_write_byte(rtlpriv, TCR,
[all...]
/linux-master/drivers/net/ethernet/smsc/
H A Dsmc9194.h64 #define TCR 0 /* transmit control register */ macro
72 /* the normal settings for the TCR register : */
H A Dsmc91c92_cs.c149 #define TCR 0 /* transmit control register */ macro
1101 mask_bits(0xff00, ioaddr + TCR);
1297 outw(inw(ioaddr + TCR) | TCR_ENABLE | smc->duplex, ioaddr + TCR); local
1332 outw(inw(ioaddr + TCR) | TCR_ENABLE | smc->duplex, ioaddr + TCR); local
1656 outw(TCR_CLEAR, ioaddr + TCR);
1685 TCR_ENABLE | TCR_PAD_EN | smc->duplex, ioaddr + TCR);
1791 outw(inw(ioaddr + TCR) | smc->duplex, ioaddr + TCR); local
[all...]
H A Dsmc9194.c332 outw( TCR_CLEAR, ioaddr + TCR );
362 /* see the header file for options in TCR/RCR NORMAL*/
363 outw( TCR_NORMAL, ioaddr + TCR );
394 outb( TCR_CLEAR, ioaddr + TCR );
1286 outw( inw( ioaddr + TCR ) | TCR_ENABLE, ioaddr + TCR ); local
/linux-master/arch/powerpc/kernel/
H A Dswsusp_asm64.S115 SAVE_SPR(TCR)
239 /* Restore TCR and clear any pending bits in TSR. */
240 RESTORE_SPR(TCR)
/linux-master/arch/sh/drivers/dma/
H A Ddma-sh.c237 (dma_base_addr(chan->chan) + TCR));
249 return __raw_readl(dma_base_addr(chan->chan) + TCR)
/linux-master/sound/soc/intel/keembay/
H A Dkmb_platform.h39 #define TCR(x) (0x40 * (x) + 0x034) macro
/linux-master/sound/soc/dwc/
H A Dlocal.h47 #define TCR(x) (0x40 * x + 0x034) macro
/linux-master/drivers/net/ethernet/amd/
H A Dariadne.h381 volatile u_char TCR; /* Timer Control Register */ member in struct:MC68230
/linux-master/drivers/tty/
H A Dsynclink_gt.c363 #define TCR 0x82 /* tx control */ macro
1321 value = rd_reg16(info, TCR);
1326 wr_reg16(info, TCR, value);
2202 unsigned short val = rd_reg16(info, TCR);
2203 wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */
2204 wr_reg16(info, TCR, val); /* clear reset bit */
2779 /* TCR (tx control) 07 1=RTS driver control */
2780 val = rd_reg16(info, TCR);
2785 wr_reg16(info, TCR, val);
3918 wr_reg16(info, TCR,
[all...]
/linux-master/drivers/dma/sh/
H A Dshdmac.c39 #define TCR 0x08 /* Transfer Count Register */ macro
218 sh_dmae_writel(sh_chan, hw->tcr >> sh_chan->xmit_shift, TCR);
422 (sh_dmae_readl(sh_chan, TCR) << sh_chan->xmit_shift);
/linux-master/drivers/net/wan/
H A Dhd64572.h103 #define TCR 0x152 /* Tx DMA Critical Request Reg */ macro
/linux-master/drivers/net/ethernet/via/
H A Dvia-velocity.c933 BYTE_REG_BITS_OFF(TCR_TB2BDIS, &regs->TCR);
940 BYTE_REG_BITS_ON(TCR_TB2BDIS, &regs->TCR);
1850 BYTE_REG_BITS_ON(TCR_TB2BDIS, &regs->TCR);
1852 BYTE_REG_BITS_OFF(TCR_TB2BDIS, &regs->TCR);
2563 td_ptr->tdesc1.TCR = TCR0_TIC;
2597 td_ptr->tdesc1.TCR |= TCR0_VETAG;
2606 td_ptr->tdesc1.TCR |= TCR0_TCPCK;
2608 td_ptr->tdesc1.TCR |= (TCR0_UDPCK);
2609 td_ptr->tdesc1.TCR |= TCR0_IPCK;
/linux-master/arch/m68k/include/asm/
H A DMC68VZ328.h697 #define TCR WORD_REF(TCR_ADDR) macro
701 #define TCR1 TCR
H A DMC68EZ328.h605 #define TCR WORD_REF(TCR_ADDR) macro
609 #define TCR1 TCR
/linux-master/drivers/net/usb/
H A Drtl8150.c24 #define TCR 0x012f macro
630 set_registers(dev, TCR, 1, &tcr);

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