1// SPDX-License-Identifier: GPL-2.0 2/* Copyright(c) 2009-2012 Realtek Corporation.*/ 3 4#include "../wifi.h" 5#include "../efuse.h" 6#include "../base.h" 7#include "../regd.h" 8#include "../cam.h" 9#include "../ps.h" 10#include "../pci.h" 11#include "reg.h" 12#include "def.h" 13#include "phy.h" 14#include "dm.h" 15#include "fw.h" 16#include "led.h" 17#include "hw.h" 18 19void rtl92se_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val) 20{ 21 struct rtl_priv *rtlpriv = rtl_priv(hw); 22 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 23 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 24 25 switch (variable) { 26 case HW_VAR_RCR: { 27 *((u32 *) (val)) = rtlpci->receive_config; 28 break; 29 } 30 case HW_VAR_RF_STATE: { 31 *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state; 32 break; 33 } 34 case HW_VAR_FW_PSMODE_STATUS: { 35 *((bool *) (val)) = ppsc->fw_current_inpsmode; 36 break; 37 } 38 case HW_VAR_CORRECT_TSF: { 39 u64 tsf; 40 u32 *ptsf_low = (u32 *)&tsf; 41 u32 *ptsf_high = ((u32 *)&tsf) + 1; 42 43 *ptsf_high = rtl_read_dword(rtlpriv, (TSFR + 4)); 44 *ptsf_low = rtl_read_dword(rtlpriv, TSFR); 45 46 *((u64 *) (val)) = tsf; 47 48 break; 49 } 50 case HW_VAR_MRC: { 51 *((bool *)(val)) = rtlpriv->dm.current_mrc_switch; 52 break; 53 } 54 case HAL_DEF_WOWLAN: 55 break; 56 default: 57 pr_err("switch case %#x not processed\n", variable); 58 break; 59 } 60} 61 62void rtl92se_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val) 63{ 64 struct rtl_priv *rtlpriv = rtl_priv(hw); 65 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 66 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 67 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 68 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 69 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 70 71 switch (variable) { 72 case HW_VAR_ETHER_ADDR:{ 73 rtl_write_dword(rtlpriv, IDR0, ((u32 *)(val))[0]); 74 rtl_write_word(rtlpriv, IDR4, ((u16 *)(val + 4))[0]); 75 break; 76 } 77 case HW_VAR_BASIC_RATE:{ 78 u16 rate_cfg = ((u16 *) val)[0]; 79 u8 rate_index = 0; 80 81 if (rtlhal->version == VERSION_8192S_ACUT) 82 rate_cfg = rate_cfg & 0x150; 83 else 84 rate_cfg = rate_cfg & 0x15f; 85 86 rate_cfg |= 0x01; 87 88 rtl_write_byte(rtlpriv, RRSR, rate_cfg & 0xff); 89 rtl_write_byte(rtlpriv, RRSR + 1, 90 (rate_cfg >> 8) & 0xff); 91 92 while (rate_cfg > 0x1) { 93 rate_cfg = (rate_cfg >> 1); 94 rate_index++; 95 } 96 rtl_write_byte(rtlpriv, INIRTSMCS_SEL, rate_index); 97 98 break; 99 } 100 case HW_VAR_BSSID:{ 101 rtl_write_dword(rtlpriv, BSSIDR, ((u32 *)(val))[0]); 102 rtl_write_word(rtlpriv, BSSIDR + 4, 103 ((u16 *)(val + 4))[0]); 104 break; 105 } 106 case HW_VAR_SIFS:{ 107 rtl_write_byte(rtlpriv, SIFS_OFDM, val[0]); 108 rtl_write_byte(rtlpriv, SIFS_OFDM + 1, val[1]); 109 break; 110 } 111 case HW_VAR_SLOT_TIME:{ 112 u8 e_aci; 113 114 rtl_dbg(rtlpriv, COMP_MLME, DBG_LOUD, 115 "HW_VAR_SLOT_TIME %x\n", val[0]); 116 117 rtl_write_byte(rtlpriv, SLOT_TIME, val[0]); 118 119 for (e_aci = 0; e_aci < AC_MAX; e_aci++) { 120 rtlpriv->cfg->ops->set_hw_reg(hw, 121 HW_VAR_AC_PARAM, 122 (&e_aci)); 123 } 124 break; 125 } 126 case HW_VAR_ACK_PREAMBLE:{ 127 u8 reg_tmp; 128 u8 short_preamble = (bool) (*val); 129 reg_tmp = (mac->cur_40_prime_sc) << 5; 130 if (short_preamble) 131 reg_tmp |= 0x80; 132 133 rtl_write_byte(rtlpriv, RRSR + 2, reg_tmp); 134 break; 135 } 136 case HW_VAR_AMPDU_MIN_SPACE:{ 137 u8 min_spacing_to_set; 138 u8 sec_min_space; 139 140 min_spacing_to_set = *val; 141 if (min_spacing_to_set <= 7) { 142 if (rtlpriv->sec.pairwise_enc_algorithm == 143 NO_ENCRYPTION) 144 sec_min_space = 0; 145 else 146 sec_min_space = 1; 147 148 if (min_spacing_to_set < sec_min_space) 149 min_spacing_to_set = sec_min_space; 150 if (min_spacing_to_set > 5) 151 min_spacing_to_set = 5; 152 153 mac->min_space_cfg = 154 ((mac->min_space_cfg & 0xf8) | 155 min_spacing_to_set); 156 157 *val = min_spacing_to_set; 158 159 rtl_dbg(rtlpriv, COMP_MLME, DBG_LOUD, 160 "Set HW_VAR_AMPDU_MIN_SPACE: %#x\n", 161 mac->min_space_cfg); 162 163 rtl_write_byte(rtlpriv, AMPDU_MIN_SPACE, 164 mac->min_space_cfg); 165 } 166 break; 167 } 168 case HW_VAR_SHORTGI_DENSITY:{ 169 u8 density_to_set; 170 171 density_to_set = *val; 172 mac->min_space_cfg = rtlpriv->rtlhal.minspace_cfg; 173 mac->min_space_cfg |= (density_to_set << 3); 174 175 rtl_dbg(rtlpriv, COMP_MLME, DBG_LOUD, 176 "Set HW_VAR_SHORTGI_DENSITY: %#x\n", 177 mac->min_space_cfg); 178 179 rtl_write_byte(rtlpriv, AMPDU_MIN_SPACE, 180 mac->min_space_cfg); 181 182 break; 183 } 184 case HW_VAR_AMPDU_FACTOR:{ 185 u8 factor_toset; 186 u8 regtoset; 187 u8 factorlevel[18] = { 188 2, 4, 4, 7, 7, 13, 13, 189 13, 2, 7, 7, 13, 13, 190 15, 15, 15, 15, 0}; 191 u8 index = 0; 192 193 factor_toset = *val; 194 if (factor_toset <= 3) { 195 factor_toset = (1 << (factor_toset + 2)); 196 if (factor_toset > 0xf) 197 factor_toset = 0xf; 198 199 for (index = 0; index < 17; index++) { 200 if (factorlevel[index] > factor_toset) 201 factorlevel[index] = 202 factor_toset; 203 } 204 205 for (index = 0; index < 8; index++) { 206 regtoset = ((factorlevel[index * 2]) | 207 (factorlevel[index * 208 2 + 1] << 4)); 209 rtl_write_byte(rtlpriv, 210 AGGLEN_LMT_L + index, 211 regtoset); 212 } 213 214 regtoset = ((factorlevel[16]) | 215 (factorlevel[17] << 4)); 216 rtl_write_byte(rtlpriv, AGGLEN_LMT_H, regtoset); 217 218 rtl_dbg(rtlpriv, COMP_MLME, DBG_LOUD, 219 "Set HW_VAR_AMPDU_FACTOR: %#x\n", 220 factor_toset); 221 } 222 break; 223 } 224 case HW_VAR_AC_PARAM:{ 225 u8 e_aci = *val; 226 rtl92s_dm_init_edca_turbo(hw); 227 228 if (rtlpci->acm_method != EACMWAY2_SW) 229 rtlpriv->cfg->ops->set_hw_reg(hw, 230 HW_VAR_ACM_CTRL, 231 &e_aci); 232 break; 233 } 234 case HW_VAR_ACM_CTRL:{ 235 u8 e_aci = *val; 236 union aci_aifsn *p_aci_aifsn = (union aci_aifsn *)(&( 237 mac->ac[0].aifs)); 238 u8 acm = p_aci_aifsn->f.acm; 239 u8 acm_ctrl = rtl_read_byte(rtlpriv, ACMHWCTRL); 240 241 acm_ctrl = acm_ctrl | ((rtlpci->acm_method == 2) ? 242 0x0 : 0x1); 243 244 if (acm) { 245 switch (e_aci) { 246 case AC0_BE: 247 acm_ctrl |= ACMHW_BEQEN; 248 break; 249 case AC2_VI: 250 acm_ctrl |= ACMHW_VIQEN; 251 break; 252 case AC3_VO: 253 acm_ctrl |= ACMHW_VOQEN; 254 break; 255 default: 256 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING, 257 "HW_VAR_ACM_CTRL acm set failed: eACI is %d\n", 258 acm); 259 break; 260 } 261 } else { 262 switch (e_aci) { 263 case AC0_BE: 264 acm_ctrl &= (~ACMHW_BEQEN); 265 break; 266 case AC2_VI: 267 acm_ctrl &= (~ACMHW_VIQEN); 268 break; 269 case AC3_VO: 270 acm_ctrl &= (~ACMHW_VOQEN); 271 break; 272 default: 273 pr_err("switch case %#x not processed\n", 274 e_aci); 275 break; 276 } 277 } 278 279 rtl_dbg(rtlpriv, COMP_QOS, DBG_TRACE, 280 "HW_VAR_ACM_CTRL Write 0x%X\n", acm_ctrl); 281 rtl_write_byte(rtlpriv, ACMHWCTRL, acm_ctrl); 282 break; 283 } 284 case HW_VAR_RCR:{ 285 rtl_write_dword(rtlpriv, RCR, ((u32 *) (val))[0]); 286 rtlpci->receive_config = ((u32 *) (val))[0]; 287 break; 288 } 289 case HW_VAR_RETRY_LIMIT:{ 290 u8 retry_limit = val[0]; 291 292 rtl_write_word(rtlpriv, RETRY_LIMIT, 293 retry_limit << RETRY_LIMIT_SHORT_SHIFT | 294 retry_limit << RETRY_LIMIT_LONG_SHIFT); 295 break; 296 } 297 case HW_VAR_DUAL_TSF_RST: { 298 break; 299 } 300 case HW_VAR_EFUSE_BYTES: { 301 rtlefuse->efuse_usedbytes = *((u16 *) val); 302 break; 303 } 304 case HW_VAR_EFUSE_USAGE: { 305 rtlefuse->efuse_usedpercentage = *val; 306 break; 307 } 308 case HW_VAR_IO_CMD: { 309 break; 310 } 311 case HW_VAR_WPA_CONFIG: { 312 rtl_write_byte(rtlpriv, REG_SECR, *val); 313 break; 314 } 315 case HW_VAR_SET_RPWM:{ 316 break; 317 } 318 case HW_VAR_H2C_FW_PWRMODE:{ 319 break; 320 } 321 case HW_VAR_FW_PSMODE_STATUS: { 322 ppsc->fw_current_inpsmode = *((bool *) val); 323 break; 324 } 325 case HW_VAR_H2C_FW_JOINBSSRPT:{ 326 break; 327 } 328 case HW_VAR_AID:{ 329 break; 330 } 331 case HW_VAR_CORRECT_TSF:{ 332 break; 333 } 334 case HW_VAR_MRC: { 335 bool bmrc_toset = *((bool *)val); 336 u8 u1bdata = 0; 337 338 if (bmrc_toset) { 339 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, 340 MASKBYTE0, 0x33); 341 u1bdata = (u8)rtl_get_bbreg(hw, 342 ROFDM1_TRXPATHENABLE, 343 MASKBYTE0); 344 rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE, 345 MASKBYTE0, 346 ((u1bdata & 0xf0) | 0x03)); 347 u1bdata = (u8)rtl_get_bbreg(hw, 348 ROFDM0_TRXPATHENABLE, 349 MASKBYTE1); 350 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, 351 MASKBYTE1, 352 (u1bdata | 0x04)); 353 354 /* Update current settings. */ 355 rtlpriv->dm.current_mrc_switch = bmrc_toset; 356 } else { 357 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, 358 MASKBYTE0, 0x13); 359 u1bdata = (u8)rtl_get_bbreg(hw, 360 ROFDM1_TRXPATHENABLE, 361 MASKBYTE0); 362 rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE, 363 MASKBYTE0, 364 ((u1bdata & 0xf0) | 0x01)); 365 u1bdata = (u8)rtl_get_bbreg(hw, 366 ROFDM0_TRXPATHENABLE, 367 MASKBYTE1); 368 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, 369 MASKBYTE1, (u1bdata & 0xfb)); 370 371 /* Update current settings. */ 372 rtlpriv->dm.current_mrc_switch = bmrc_toset; 373 } 374 375 break; 376 } 377 case HW_VAR_FW_LPS_ACTION: { 378 bool enter_fwlps = *((bool *)val); 379 u8 rpwm_val, fw_pwrmode; 380 bool fw_current_inps; 381 382 if (enter_fwlps) { 383 rpwm_val = 0x02; /* RF off */ 384 fw_current_inps = true; 385 rtlpriv->cfg->ops->set_hw_reg(hw, 386 HW_VAR_FW_PSMODE_STATUS, 387 (u8 *)(&fw_current_inps)); 388 rtlpriv->cfg->ops->set_hw_reg(hw, 389 HW_VAR_H2C_FW_PWRMODE, 390 &ppsc->fwctrl_psmode); 391 392 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM, 393 &rpwm_val); 394 } else { 395 rpwm_val = 0x0C; /* RF on */ 396 fw_pwrmode = FW_PS_ACTIVE_MODE; 397 fw_current_inps = false; 398 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM, 399 &rpwm_val); 400 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE, 401 &fw_pwrmode); 402 403 rtlpriv->cfg->ops->set_hw_reg(hw, 404 HW_VAR_FW_PSMODE_STATUS, 405 (u8 *)(&fw_current_inps)); 406 } 407 break; } 408 default: 409 pr_err("switch case %#x not processed\n", variable); 410 break; 411 } 412 413} 414 415void rtl92se_enable_hw_security_config(struct ieee80211_hw *hw) 416{ 417 struct rtl_priv *rtlpriv = rtl_priv(hw); 418 u8 sec_reg_value = 0x0; 419 420 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 421 "PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n", 422 rtlpriv->sec.pairwise_enc_algorithm, 423 rtlpriv->sec.group_enc_algorithm); 424 425 if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) { 426 rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG, 427 "not open hw encryption\n"); 428 return; 429 } 430 431 sec_reg_value = SCR_TXENCENABLE | SCR_RXENCENABLE; 432 433 if (rtlpriv->sec.use_defaultkey) { 434 sec_reg_value |= SCR_TXUSEDK; 435 sec_reg_value |= SCR_RXUSEDK; 436 } 437 438 rtl_dbg(rtlpriv, COMP_SEC, DBG_LOUD, "The SECR-value %x\n", 439 sec_reg_value); 440 441 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value); 442 443} 444 445static u8 _rtl92se_halset_sysclk(struct ieee80211_hw *hw, u8 data) 446{ 447 struct rtl_priv *rtlpriv = rtl_priv(hw); 448 u8 waitcount = 100; 449 bool bresult = false; 450 u8 tmpvalue; 451 452 rtl_write_byte(rtlpriv, SYS_CLKR + 1, data); 453 454 /* Wait the MAC synchronized. */ 455 udelay(400); 456 457 /* Check if it is set ready. */ 458 tmpvalue = rtl_read_byte(rtlpriv, SYS_CLKR + 1); 459 bresult = ((tmpvalue & BIT(7)) == (data & BIT(7))); 460 461 if (!(data & (BIT(6) | BIT(7)))) { 462 waitcount = 100; 463 tmpvalue = 0; 464 465 while (1) { 466 waitcount--; 467 468 tmpvalue = rtl_read_byte(rtlpriv, SYS_CLKR + 1); 469 if ((tmpvalue & BIT(6))) 470 break; 471 472 pr_err("wait for BIT(6) return value %x\n", tmpvalue); 473 if (waitcount == 0) 474 break; 475 476 udelay(10); 477 } 478 479 if (waitcount == 0) 480 bresult = false; 481 else 482 bresult = true; 483 } 484 485 return bresult; 486} 487 488void rtl8192se_gpiobit3_cfg_inputmode(struct ieee80211_hw *hw) 489{ 490 struct rtl_priv *rtlpriv = rtl_priv(hw); 491 u8 u1tmp; 492 493 /* The following config GPIO function */ 494 rtl_write_byte(rtlpriv, MAC_PINMUX_CFG, (GPIOMUX_EN | GPIOSEL_GPIO)); 495 u1tmp = rtl_read_byte(rtlpriv, GPIO_IO_SEL); 496 497 /* config GPIO3 to input */ 498 u1tmp &= HAL_8192S_HW_GPIO_OFF_MASK; 499 rtl_write_byte(rtlpriv, GPIO_IO_SEL, u1tmp); 500 501} 502 503static u8 _rtl92se_rf_onoff_detect(struct ieee80211_hw *hw) 504{ 505 struct rtl_priv *rtlpriv = rtl_priv(hw); 506 u8 u1tmp; 507 u8 retval = ERFON; 508 509 /* The following config GPIO function */ 510 rtl_write_byte(rtlpriv, MAC_PINMUX_CFG, (GPIOMUX_EN | GPIOSEL_GPIO)); 511 u1tmp = rtl_read_byte(rtlpriv, GPIO_IO_SEL); 512 513 /* config GPIO3 to input */ 514 u1tmp &= HAL_8192S_HW_GPIO_OFF_MASK; 515 rtl_write_byte(rtlpriv, GPIO_IO_SEL, u1tmp); 516 517 /* On some of the platform, driver cannot read correct 518 * value without delay between Write_GPIO_SEL and Read_GPIO_IN */ 519 mdelay(10); 520 521 /* check GPIO3 */ 522 u1tmp = rtl_read_byte(rtlpriv, GPIO_IN_SE); 523 retval = (u1tmp & HAL_8192S_HW_GPIO_OFF_BIT) ? ERFON : ERFOFF; 524 525 return retval; 526} 527 528static void _rtl92se_macconfig_before_fwdownload(struct ieee80211_hw *hw) 529{ 530 struct rtl_priv *rtlpriv = rtl_priv(hw); 531 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 532 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 533 534 u8 i; 535 u8 tmpu1b; 536 u16 tmpu2b; 537 u8 pollingcnt = 20; 538 539 if (rtlpci->first_init) { 540 /* Reset PCIE Digital */ 541 tmpu1b = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1); 542 tmpu1b &= 0xFE; 543 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmpu1b); 544 udelay(1); 545 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmpu1b | BIT(0)); 546 } 547 548 /* Switch to SW IO control */ 549 tmpu1b = rtl_read_byte(rtlpriv, (SYS_CLKR + 1)); 550 if (tmpu1b & BIT(7)) { 551 tmpu1b &= ~(BIT(6) | BIT(7)); 552 553 /* Set failed, return to prevent hang. */ 554 if (!_rtl92se_halset_sysclk(hw, tmpu1b)) 555 return; 556 } 557 558 rtl_write_byte(rtlpriv, AFE_PLL_CTRL, 0x0); 559 udelay(50); 560 rtl_write_byte(rtlpriv, LDOA15_CTRL, 0x34); 561 udelay(50); 562 563 /* Clear FW RPWM for FW control LPS.*/ 564 rtl_write_byte(rtlpriv, RPWM, 0x0); 565 566 /* Reset MAC-IO and CPU and Core Digital BIT(10)/11/15 */ 567 tmpu1b = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1); 568 tmpu1b &= 0x73; 569 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmpu1b); 570 /* wait for BIT 10/11/15 to pull high automatically!! */ 571 mdelay(1); 572 573 rtl_write_byte(rtlpriv, CMDR, 0); 574 rtl_write_byte(rtlpriv, TCR, 0); 575 576 /* Data sheet not define 0x562!!! Copy from WMAC!!!!! */ 577 tmpu1b = rtl_read_byte(rtlpriv, 0x562); 578 tmpu1b |= 0x08; 579 rtl_write_byte(rtlpriv, 0x562, tmpu1b); 580 tmpu1b &= ~(BIT(3)); 581 rtl_write_byte(rtlpriv, 0x562, tmpu1b); 582 583 /* Enable AFE clock source */ 584 tmpu1b = rtl_read_byte(rtlpriv, AFE_XTAL_CTRL); 585 rtl_write_byte(rtlpriv, AFE_XTAL_CTRL, (tmpu1b | 0x01)); 586 /* Delay 1.5ms */ 587 mdelay(2); 588 tmpu1b = rtl_read_byte(rtlpriv, AFE_XTAL_CTRL + 1); 589 rtl_write_byte(rtlpriv, AFE_XTAL_CTRL + 1, (tmpu1b & 0xfb)); 590 591 /* Enable AFE Macro Block's Bandgap */ 592 tmpu1b = rtl_read_byte(rtlpriv, AFE_MISC); 593 rtl_write_byte(rtlpriv, AFE_MISC, (tmpu1b | BIT(0))); 594 mdelay(1); 595 596 /* Enable AFE Mbias */ 597 tmpu1b = rtl_read_byte(rtlpriv, AFE_MISC); 598 rtl_write_byte(rtlpriv, AFE_MISC, (tmpu1b | 0x02)); 599 mdelay(1); 600 601 /* Enable LDOA15 block */ 602 tmpu1b = rtl_read_byte(rtlpriv, LDOA15_CTRL); 603 rtl_write_byte(rtlpriv, LDOA15_CTRL, (tmpu1b | BIT(0))); 604 605 /* Set Digital Vdd to Retention isolation Path. */ 606 tmpu2b = rtl_read_word(rtlpriv, REG_SYS_ISO_CTRL); 607 rtl_write_word(rtlpriv, REG_SYS_ISO_CTRL, (tmpu2b | BIT(11))); 608 609 /* For warm reboot NIC disappera bug. */ 610 tmpu2b = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN); 611 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (tmpu2b | BIT(13))); 612 613 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL + 1, 0x68); 614 615 /* Enable AFE PLL Macro Block */ 616 /* We need to delay 100u before enabling PLL. */ 617 udelay(200); 618 tmpu1b = rtl_read_byte(rtlpriv, AFE_PLL_CTRL); 619 rtl_write_byte(rtlpriv, AFE_PLL_CTRL, (tmpu1b | BIT(0) | BIT(4))); 620 621 /* for divider reset */ 622 udelay(100); 623 rtl_write_byte(rtlpriv, AFE_PLL_CTRL, (tmpu1b | BIT(0) | 624 BIT(4) | BIT(6))); 625 udelay(10); 626 rtl_write_byte(rtlpriv, AFE_PLL_CTRL, (tmpu1b | BIT(0) | BIT(4))); 627 udelay(10); 628 629 /* Enable MAC 80MHZ clock */ 630 tmpu1b = rtl_read_byte(rtlpriv, AFE_PLL_CTRL + 1); 631 rtl_write_byte(rtlpriv, AFE_PLL_CTRL + 1, (tmpu1b | BIT(0))); 632 mdelay(1); 633 634 /* Release isolation AFE PLL & MD */ 635 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL, 0xA6); 636 637 /* Enable MAC clock */ 638 tmpu2b = rtl_read_word(rtlpriv, SYS_CLKR); 639 rtl_write_word(rtlpriv, SYS_CLKR, (tmpu2b | BIT(12) | BIT(11))); 640 641 /* Enable Core digital and enable IOREG R/W */ 642 tmpu2b = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN); 643 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (tmpu2b | BIT(11))); 644 645 tmpu1b = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1); 646 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmpu1b & ~(BIT(7))); 647 648 /* enable REG_EN */ 649 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (tmpu2b | BIT(11) | BIT(15))); 650 651 /* Switch the control path. */ 652 tmpu2b = rtl_read_word(rtlpriv, SYS_CLKR); 653 rtl_write_word(rtlpriv, SYS_CLKR, (tmpu2b & (~BIT(2)))); 654 655 tmpu1b = rtl_read_byte(rtlpriv, (SYS_CLKR + 1)); 656 tmpu1b = ((tmpu1b | BIT(7)) & (~BIT(6))); 657 if (!_rtl92se_halset_sysclk(hw, tmpu1b)) 658 return; /* Set failed, return to prevent hang. */ 659 660 rtl_write_word(rtlpriv, CMDR, 0x07FC); 661 662 /* MH We must enable the section of code to prevent load IMEM fail. */ 663 /* Load MAC register from WMAc temporarily We simulate macreg. */ 664 /* txt HW will provide MAC txt later */ 665 rtl_write_byte(rtlpriv, 0x6, 0x30); 666 rtl_write_byte(rtlpriv, 0x49, 0xf0); 667 668 rtl_write_byte(rtlpriv, 0x4b, 0x81); 669 670 rtl_write_byte(rtlpriv, 0xb5, 0x21); 671 672 rtl_write_byte(rtlpriv, 0xdc, 0xff); 673 rtl_write_byte(rtlpriv, 0xdd, 0xff); 674 rtl_write_byte(rtlpriv, 0xde, 0xff); 675 rtl_write_byte(rtlpriv, 0xdf, 0xff); 676 677 rtl_write_byte(rtlpriv, 0x11a, 0x00); 678 rtl_write_byte(rtlpriv, 0x11b, 0x00); 679 680 for (i = 0; i < 32; i++) 681 rtl_write_byte(rtlpriv, INIMCS_SEL + i, 0x1b); 682 683 rtl_write_byte(rtlpriv, 0x236, 0xff); 684 685 rtl_write_byte(rtlpriv, 0x503, 0x22); 686 687 if (ppsc->support_aspm && !ppsc->support_backdoor) 688 rtl_write_byte(rtlpriv, 0x560, 0x40); 689 else 690 rtl_write_byte(rtlpriv, 0x560, 0x00); 691 692 rtl_write_byte(rtlpriv, DBG_PORT, 0x91); 693 694 /* Set RX Desc Address */ 695 rtl_write_dword(rtlpriv, RDQDA, rtlpci->rx_ring[RX_MPDU_QUEUE].dma); 696 rtl_write_dword(rtlpriv, RCDA, rtlpci->rx_ring[RX_CMD_QUEUE].dma); 697 698 /* Set TX Desc Address */ 699 rtl_write_dword(rtlpriv, TBKDA, rtlpci->tx_ring[BK_QUEUE].dma); 700 rtl_write_dword(rtlpriv, TBEDA, rtlpci->tx_ring[BE_QUEUE].dma); 701 rtl_write_dword(rtlpriv, TVIDA, rtlpci->tx_ring[VI_QUEUE].dma); 702 rtl_write_dword(rtlpriv, TVODA, rtlpci->tx_ring[VO_QUEUE].dma); 703 rtl_write_dword(rtlpriv, TBDA, rtlpci->tx_ring[BEACON_QUEUE].dma); 704 rtl_write_dword(rtlpriv, TCDA, rtlpci->tx_ring[TXCMD_QUEUE].dma); 705 rtl_write_dword(rtlpriv, TMDA, rtlpci->tx_ring[MGNT_QUEUE].dma); 706 rtl_write_dword(rtlpriv, THPDA, rtlpci->tx_ring[HIGH_QUEUE].dma); 707 rtl_write_dword(rtlpriv, HDA, rtlpci->tx_ring[HCCA_QUEUE].dma); 708 709 rtl_write_word(rtlpriv, CMDR, 0x37FC); 710 711 /* To make sure that TxDMA can ready to download FW. */ 712 /* We should reset TxDMA if IMEM RPT was not ready. */ 713 do { 714 tmpu1b = rtl_read_byte(rtlpriv, TCR); 715 if ((tmpu1b & TXDMA_INIT_VALUE) == TXDMA_INIT_VALUE) 716 break; 717 718 udelay(5); 719 } while (pollingcnt--); 720 721 if (pollingcnt <= 0) { 722 pr_err("Polling TXDMA_INIT_VALUE timeout!! Current TCR(%#x)\n", 723 tmpu1b); 724 tmpu1b = rtl_read_byte(rtlpriv, CMDR); 725 rtl_write_byte(rtlpriv, CMDR, tmpu1b & (~TXDMA_EN)); 726 udelay(2); 727 /* Reset TxDMA */ 728 rtl_write_byte(rtlpriv, CMDR, tmpu1b | TXDMA_EN); 729 } 730 731 /* After MACIO reset,we must refresh LED state. */ 732 if ((ppsc->rfoff_reason == RF_CHANGE_BY_IPS) || 733 (ppsc->rfoff_reason == 0)) { 734 enum rtl_led_pin pin0 = rtlpriv->ledctl.sw_led0; 735 enum rf_pwrstate rfpwr_state_toset; 736 rfpwr_state_toset = _rtl92se_rf_onoff_detect(hw); 737 738 if (rfpwr_state_toset == ERFON) 739 rtl92se_sw_led_on(hw, pin0); 740 } 741} 742 743static void _rtl92se_macconfig_after_fwdownload(struct ieee80211_hw *hw) 744{ 745 struct rtl_priv *rtlpriv = rtl_priv(hw); 746 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 747 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 748 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 749 u8 i; 750 u16 tmpu2b; 751 752 /* 1. System Configure Register (Offset: 0x0000 - 0x003F) */ 753 754 /* 2. Command Control Register (Offset: 0x0040 - 0x004F) */ 755 /* Turn on 0x40 Command register */ 756 rtl_write_word(rtlpriv, CMDR, (BBRSTN | BB_GLB_RSTN | 757 SCHEDULE_EN | MACRXEN | MACTXEN | DDMA_EN | FW2HW_EN | 758 RXDMA_EN | TXDMA_EN | HCI_RXDMA_EN | HCI_TXDMA_EN)); 759 760 /* Set TCR TX DMA pre 2 FULL enable bit */ 761 rtl_write_dword(rtlpriv, TCR, rtl_read_dword(rtlpriv, TCR) | 762 TXDMAPRE2FULL); 763 764 /* Set RCR */ 765 rtl_write_dword(rtlpriv, RCR, rtlpci->receive_config); 766 767 /* 3. MACID Setting Register (Offset: 0x0050 - 0x007F) */ 768 769 /* 4. Timing Control Register (Offset: 0x0080 - 0x009F) */ 770 /* Set CCK/OFDM SIFS */ 771 /* CCK SIFS shall always be 10us. */ 772 rtl_write_word(rtlpriv, SIFS_CCK, 0x0a0a); 773 rtl_write_word(rtlpriv, SIFS_OFDM, 0x1010); 774 775 /* Set AckTimeout */ 776 rtl_write_byte(rtlpriv, ACK_TIMEOUT, 0x40); 777 778 /* Beacon related */ 779 rtl_write_word(rtlpriv, BCN_INTERVAL, 100); 780 rtl_write_word(rtlpriv, ATIMWND, 2); 781 782 /* 5. FIFO Control Register (Offset: 0x00A0 - 0x015F) */ 783 /* 5.1 Initialize Number of Reserved Pages in Firmware Queue */ 784 /* Firmware allocate now, associate with FW internal setting.!!! */ 785 786 /* 5.2 Setting TX/RX page size 0/1/2/3/4=64/128/256/512/1024 */ 787 /* 5.3 Set driver info, we only accept PHY status now. */ 788 /* 5.4 Set RXDMA arbitration to control RXDMA/MAC/FW R/W for RXFIFO */ 789 rtl_write_byte(rtlpriv, RXDMA, rtl_read_byte(rtlpriv, RXDMA) | BIT(6)); 790 791 /* 6. Adaptive Control Register (Offset: 0x0160 - 0x01CF) */ 792 /* Set RRSR to all legacy rate and HT rate 793 * CCK rate is supported by default. 794 * CCK rate will be filtered out only when associated 795 * AP does not support it. 796 * Only enable ACK rate to OFDM 24M 797 * Disable RRSR for CCK rate in A-Cut */ 798 799 if (rtlhal->version == VERSION_8192S_ACUT) 800 rtl_write_byte(rtlpriv, RRSR, 0xf0); 801 else if (rtlhal->version == VERSION_8192S_BCUT) 802 rtl_write_byte(rtlpriv, RRSR, 0xff); 803 rtl_write_byte(rtlpriv, RRSR + 1, 0x01); 804 rtl_write_byte(rtlpriv, RRSR + 2, 0x00); 805 806 /* A-Cut IC do not support CCK rate. We forbid ARFR to */ 807 /* fallback to CCK rate */ 808 for (i = 0; i < 8; i++) { 809 /*Disable RRSR for CCK rate in A-Cut */ 810 if (rtlhal->version == VERSION_8192S_ACUT) 811 rtl_write_dword(rtlpriv, ARFR0 + i * 4, 0x1f0ff0f0); 812 } 813 814 /* Different rate use different AMPDU size */ 815 /* MCS32/ MCS15_SG use max AMPDU size 15*2=30K */ 816 rtl_write_byte(rtlpriv, AGGLEN_LMT_H, 0x0f); 817 /* MCS0/1/2/3 use max AMPDU size 4*2=8K */ 818 rtl_write_word(rtlpriv, AGGLEN_LMT_L, 0x7442); 819 /* MCS4/5 use max AMPDU size 8*2=16K 6/7 use 10*2=20K */ 820 rtl_write_word(rtlpriv, AGGLEN_LMT_L + 2, 0xddd7); 821 /* MCS8/9 use max AMPDU size 8*2=16K 10/11 use 10*2=20K */ 822 rtl_write_word(rtlpriv, AGGLEN_LMT_L + 4, 0xd772); 823 /* MCS12/13/14/15 use max AMPDU size 15*2=30K */ 824 rtl_write_word(rtlpriv, AGGLEN_LMT_L + 6, 0xfffd); 825 826 /* Set Data / Response auto rate fallack retry count */ 827 rtl_write_dword(rtlpriv, DARFRC, 0x04010000); 828 rtl_write_dword(rtlpriv, DARFRC + 4, 0x09070605); 829 rtl_write_dword(rtlpriv, RARFRC, 0x04010000); 830 rtl_write_dword(rtlpriv, RARFRC + 4, 0x09070605); 831 832 /* 7. EDCA Setting Register (Offset: 0x01D0 - 0x01FF) */ 833 /* Set all rate to support SG */ 834 rtl_write_word(rtlpriv, SG_RATE, 0xFFFF); 835 836 /* 8. WMAC, BA, and CCX related Register (Offset: 0x0200 - 0x023F) */ 837 /* Set NAV protection length */ 838 rtl_write_word(rtlpriv, NAV_PROT_LEN, 0x0080); 839 /* CF-END Threshold */ 840 rtl_write_byte(rtlpriv, CFEND_TH, 0xFF); 841 /* Set AMPDU minimum space */ 842 rtl_write_byte(rtlpriv, AMPDU_MIN_SPACE, 0x07); 843 /* Set TXOP stall control for several queue/HI/BCN/MGT/ */ 844 rtl_write_byte(rtlpriv, TXOP_STALL_CTRL, 0x00); 845 846 /* 9. Security Control Register (Offset: 0x0240 - 0x025F) */ 847 /* 10. Power Save Control Register (Offset: 0x0260 - 0x02DF) */ 848 /* 11. General Purpose Register (Offset: 0x02E0 - 0x02FF) */ 849 /* 12. Host Interrupt Status Register (Offset: 0x0300 - 0x030F) */ 850 /* 13. Test mode and Debug Control Register (Offset: 0x0310 - 0x034F) */ 851 852 /* 14. Set driver info, we only accept PHY status now. */ 853 rtl_write_byte(rtlpriv, RXDRVINFO_SZ, 4); 854 855 /* 15. For EEPROM R/W Workaround */ 856 /* 16. For EFUSE to share REG_SYS_FUNC_EN with EEPROM!!! */ 857 tmpu2b = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN); 858 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, tmpu2b | BIT(13)); 859 tmpu2b = rtl_read_byte(rtlpriv, REG_SYS_ISO_CTRL); 860 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL, tmpu2b & (~BIT(8))); 861 862 /* 17. For EFUSE */ 863 /* We may R/W EFUSE in EEPROM mode */ 864 if (rtlefuse->epromtype == EEPROM_BOOT_EFUSE) { 865 u8 tempval; 866 867 tempval = rtl_read_byte(rtlpriv, REG_SYS_ISO_CTRL + 1); 868 tempval &= 0xFE; 869 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL + 1, tempval); 870 871 /* Change Program timing */ 872 rtl_write_byte(rtlpriv, REG_EFUSE_CTRL + 3, 0x72); 873 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, "EFUSE CONFIG OK\n"); 874 } 875 876 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, "OK\n"); 877 878} 879 880static void _rtl92se_hw_configure(struct ieee80211_hw *hw) 881{ 882 struct rtl_priv *rtlpriv = rtl_priv(hw); 883 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 884 struct rtl_phy *rtlphy = &(rtlpriv->phy); 885 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 886 887 u8 reg_bw_opmode = 0; 888 u32 reg_rrsr = 0; 889 u8 regtmp = 0; 890 891 reg_bw_opmode = BW_OPMODE_20MHZ; 892 reg_rrsr = RATE_ALL_CCK | RATE_ALL_OFDM_AG; 893 894 regtmp = rtl_read_byte(rtlpriv, INIRTSMCS_SEL); 895 reg_rrsr = ((reg_rrsr & 0x000fffff) << 8) | regtmp; 896 rtl_write_dword(rtlpriv, INIRTSMCS_SEL, reg_rrsr); 897 rtl_write_byte(rtlpriv, BW_OPMODE, reg_bw_opmode); 898 899 /* Set Retry Limit here */ 900 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RETRY_LIMIT, 901 (u8 *)(&rtlpci->shortretry_limit)); 902 903 rtl_write_byte(rtlpriv, MLT, 0x8f); 904 905 /* For Min Spacing configuration. */ 906 switch (rtlphy->rf_type) { 907 case RF_1T2R: 908 case RF_1T1R: 909 rtlhal->minspace_cfg = (MAX_MSS_DENSITY_1T << 3); 910 break; 911 case RF_2T2R: 912 case RF_2T2R_GREEN: 913 rtlhal->minspace_cfg = (MAX_MSS_DENSITY_2T << 3); 914 break; 915 } 916 rtl_write_byte(rtlpriv, AMPDU_MIN_SPACE, rtlhal->minspace_cfg); 917} 918 919int rtl92se_hw_init(struct ieee80211_hw *hw) 920{ 921 struct rtl_priv *rtlpriv = rtl_priv(hw); 922 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 923 struct rtl_phy *rtlphy = &(rtlpriv->phy); 924 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 925 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 926 u8 tmp_byte = 0; 927 unsigned long flags; 928 bool rtstatus = true; 929 u8 tmp_u1b; 930 int err = false; 931 u8 i; 932 int wdcapra_add[] = { 933 EDCAPARA_BE, EDCAPARA_BK, 934 EDCAPARA_VI, EDCAPARA_VO}; 935 u8 secr_value = 0x0; 936 937 rtlpci->being_init_adapter = true; 938 939 /* As this function can take a very long time (up to 350 ms) 940 * and can be called with irqs disabled, reenable the irqs 941 * to let the other devices continue being serviced. 942 * 943 * It is safe doing so since our own interrupts will only be enabled 944 * in a subsequent step. 945 */ 946 local_save_flags(flags); 947 local_irq_enable(); 948 949 rtlpriv->intf_ops->disable_aspm(hw); 950 951 /* 1. MAC Initialize */ 952 /* Before FW download, we have to set some MAC register */ 953 _rtl92se_macconfig_before_fwdownload(hw); 954 955 rtlhal->version = (enum version_8192s)((rtl_read_dword(rtlpriv, 956 PMC_FSM) >> 16) & 0xF); 957 958 rtl8192se_gpiobit3_cfg_inputmode(hw); 959 960 /* 2. download firmware */ 961 rtstatus = rtl92s_download_fw(hw); 962 if (!rtstatus) { 963 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING, 964 "Failed to download FW. Init HW without FW now... Please copy FW into /lib/firmware/rtlwifi\n"); 965 err = 1; 966 goto exit; 967 } 968 969 /* After FW download, we have to reset MAC register */ 970 _rtl92se_macconfig_after_fwdownload(hw); 971 972 /*Retrieve default FW Cmd IO map. */ 973 rtlhal->fwcmd_iomap = rtl_read_word(rtlpriv, LBUS_MON_ADDR); 974 rtlhal->fwcmd_ioparam = rtl_read_dword(rtlpriv, LBUS_ADDR_MASK); 975 976 /* 3. Initialize MAC/PHY Config by MACPHY_reg.txt */ 977 if (!rtl92s_phy_mac_config(hw)) { 978 pr_err("MAC Config failed\n"); 979 err = rtstatus; 980 goto exit; 981 } 982 983 /* because last function modify RCR, so we update 984 * rcr var here, or TP will unstable for receive_config 985 * is wrong, RX RCR_ACRC32 will cause TP unstabel & Rx 986 * RCR_APP_ICV will cause mac80211 unassoc for cisco 1252 987 */ 988 rtlpci->receive_config = rtl_read_dword(rtlpriv, RCR); 989 rtlpci->receive_config &= ~(RCR_ACRC32 | RCR_AICV); 990 rtl_write_dword(rtlpriv, RCR, rtlpci->receive_config); 991 992 /* Make sure BB/RF write OK. We should prevent enter IPS. radio off. */ 993 /* We must set flag avoid BB/RF config period later!! */ 994 rtl_write_dword(rtlpriv, CMDR, 0x37FC); 995 996 /* 4. Initialize BB After MAC Config PHY_reg.txt, AGC_Tab.txt */ 997 if (!rtl92s_phy_bb_config(hw)) { 998 pr_err("BB Config failed\n"); 999 err = rtstatus; 1000 goto exit; 1001 } 1002 1003 /* 5. Initiailze RF RAIO_A.txt RF RAIO_B.txt */ 1004 /* Before initalizing RF. We can not use FW to do RF-R/W. */ 1005 1006 rtlphy->rf_mode = RF_OP_BY_SW_3WIRE; 1007 1008 /* Before RF-R/W we must execute the IO from Scott's suggestion. */ 1009 rtl_write_byte(rtlpriv, AFE_XTAL_CTRL + 1, 0xDB); 1010 if (rtlhal->version == VERSION_8192S_ACUT) 1011 rtl_write_byte(rtlpriv, SPS1_CTRL + 3, 0x07); 1012 else 1013 rtl_write_byte(rtlpriv, RF_CTRL, 0x07); 1014 1015 if (!rtl92s_phy_rf_config(hw)) { 1016 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, "RF Config failed\n"); 1017 err = rtstatus; 1018 goto exit; 1019 } 1020 1021 /* After read predefined TXT, we must set BB/MAC/RF 1022 * register as our requirement */ 1023 1024 rtlphy->rfreg_chnlval[0] = rtl92s_phy_query_rf_reg(hw, 1025 (enum radio_path)0, 1026 RF_CHNLBW, 1027 RFREG_OFFSET_MASK); 1028 rtlphy->rfreg_chnlval[1] = rtl92s_phy_query_rf_reg(hw, 1029 (enum radio_path)1, 1030 RF_CHNLBW, 1031 RFREG_OFFSET_MASK); 1032 1033 /*---- Set CCK and OFDM Block "ON"----*/ 1034 rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0x1); 1035 rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0x1); 1036 1037 /*3 Set Hardware(Do nothing now) */ 1038 _rtl92se_hw_configure(hw); 1039 1040 /* Read EEPROM TX power index and PHY_REG_PG.txt to capture correct */ 1041 /* TX power index for different rate set. */ 1042 /* Get original hw reg values */ 1043 rtl92s_phy_get_hw_reg_originalvalue(hw); 1044 /* Write correct tx power index */ 1045 rtl92s_phy_set_txpower(hw, rtlphy->current_channel); 1046 1047 /* We must set MAC address after firmware download. */ 1048 for (i = 0; i < 6; i++) 1049 rtl_write_byte(rtlpriv, MACIDR0 + i, rtlefuse->dev_addr[i]); 1050 1051 /* EEPROM R/W workaround */ 1052 tmp_u1b = rtl_read_byte(rtlpriv, MAC_PINMUX_CFG); 1053 rtl_write_byte(rtlpriv, MAC_PINMUX_CFG, tmp_u1b & (~BIT(3))); 1054 1055 rtl_write_byte(rtlpriv, 0x4d, 0x0); 1056 1057 if (hal_get_firmwareversion(rtlpriv) >= 0x49) { 1058 tmp_byte = rtl_read_byte(rtlpriv, FW_RSVD_PG_CRTL) & (~BIT(4)); 1059 tmp_byte = tmp_byte | BIT(5); 1060 rtl_write_byte(rtlpriv, FW_RSVD_PG_CRTL, tmp_byte); 1061 rtl_write_dword(rtlpriv, TXDESC_MSK, 0xFFFFCFFF); 1062 } 1063 1064 /* We enable high power and RA related mechanism after NIC 1065 * initialized. */ 1066 if (hal_get_firmwareversion(rtlpriv) >= 0x35) { 1067 /* Fw v.53 and later. */ 1068 rtl92s_phy_set_fw_cmd(hw, FW_CMD_RA_INIT); 1069 } else if (hal_get_firmwareversion(rtlpriv) == 0x34) { 1070 /* Fw v.52. */ 1071 rtl_write_dword(rtlpriv, WFM5, FW_RA_INIT); 1072 rtl92s_phy_chk_fwcmd_iodone(hw); 1073 } else { 1074 /* Compatible earlier FW version. */ 1075 rtl_write_dword(rtlpriv, WFM5, FW_RA_RESET); 1076 rtl92s_phy_chk_fwcmd_iodone(hw); 1077 rtl_write_dword(rtlpriv, WFM5, FW_RA_ACTIVE); 1078 rtl92s_phy_chk_fwcmd_iodone(hw); 1079 rtl_write_dword(rtlpriv, WFM5, FW_RA_REFRESH); 1080 rtl92s_phy_chk_fwcmd_iodone(hw); 1081 } 1082 1083 /* Add to prevent ASPM bug. */ 1084 /* Always enable hst and NIC clock request. */ 1085 rtl92s_phy_switch_ephy_parameter(hw); 1086 1087 /* Security related 1088 * 1. Clear all H/W keys. 1089 * 2. Enable H/W encryption/decryption. */ 1090 rtl_cam_reset_all_entry(hw); 1091 secr_value |= SCR_TXENCENABLE; 1092 secr_value |= SCR_RXENCENABLE; 1093 secr_value |= SCR_NOSKMC; 1094 rtl_write_byte(rtlpriv, REG_SECR, secr_value); 1095 1096 for (i = 0; i < 4; i++) 1097 rtl_write_dword(rtlpriv, wdcapra_add[i], 0x5e4322); 1098 1099 if (rtlphy->rf_type == RF_1T2R) { 1100 bool mrc2set = true; 1101 /* Turn on B-Path */ 1102 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_MRC, (u8 *)&mrc2set); 1103 } 1104 1105 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_ON); 1106 rtl92s_dm_init(hw); 1107exit: 1108 local_irq_restore(flags); 1109 rtlpci->being_init_adapter = false; 1110 return err; 1111} 1112 1113void rtl92se_set_mac_addr(struct rtl_io *io, const u8 *addr) 1114{ 1115 /* This is a stub. */ 1116} 1117 1118void rtl92se_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid) 1119{ 1120 struct rtl_priv *rtlpriv = rtl_priv(hw); 1121 u32 reg_rcr; 1122 1123 if (rtlpriv->psc.rfpwr_state != ERFON) 1124 return; 1125 1126 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RCR, (u8 *)(®_rcr)); 1127 1128 if (check_bssid) { 1129 reg_rcr |= (RCR_CBSSID); 1130 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR, (u8 *)(®_rcr)); 1131 } else if (!check_bssid) { 1132 reg_rcr &= (~RCR_CBSSID); 1133 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR, (u8 *)(®_rcr)); 1134 } 1135 1136} 1137 1138static int _rtl92se_set_media_status(struct ieee80211_hw *hw, 1139 enum nl80211_iftype type) 1140{ 1141 struct rtl_priv *rtlpriv = rtl_priv(hw); 1142 u8 bt_msr = rtl_read_byte(rtlpriv, MSR); 1143 u32 temp; 1144 bt_msr &= ~MSR_LINK_MASK; 1145 1146 switch (type) { 1147 case NL80211_IFTYPE_UNSPECIFIED: 1148 bt_msr |= (MSR_LINK_NONE << MSR_LINK_SHIFT); 1149 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, 1150 "Set Network type to NO LINK!\n"); 1151 break; 1152 case NL80211_IFTYPE_ADHOC: 1153 bt_msr |= (MSR_LINK_ADHOC << MSR_LINK_SHIFT); 1154 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, 1155 "Set Network type to Ad Hoc!\n"); 1156 break; 1157 case NL80211_IFTYPE_STATION: 1158 bt_msr |= (MSR_LINK_MANAGED << MSR_LINK_SHIFT); 1159 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, 1160 "Set Network type to STA!\n"); 1161 break; 1162 case NL80211_IFTYPE_AP: 1163 bt_msr |= (MSR_LINK_MASTER << MSR_LINK_SHIFT); 1164 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, 1165 "Set Network type to AP!\n"); 1166 break; 1167 default: 1168 pr_err("Network type %d not supported!\n", type); 1169 return 1; 1170 1171 } 1172 1173 if (type != NL80211_IFTYPE_AP && 1174 rtlpriv->mac80211.link_state < MAC80211_LINKED) 1175 bt_msr = rtl_read_byte(rtlpriv, MSR) & ~MSR_LINK_MASK; 1176 rtl_write_byte(rtlpriv, MSR, bt_msr); 1177 1178 temp = rtl_read_dword(rtlpriv, TCR); 1179 rtl_write_dword(rtlpriv, TCR, temp & (~BIT(8))); 1180 rtl_write_dword(rtlpriv, TCR, temp | BIT(8)); 1181 1182 1183 return 0; 1184} 1185 1186/* HW_VAR_MEDIA_STATUS & HW_VAR_CECHK_BSSID */ 1187int rtl92se_set_network_type(struct ieee80211_hw *hw, enum nl80211_iftype type) 1188{ 1189 struct rtl_priv *rtlpriv = rtl_priv(hw); 1190 1191 if (_rtl92se_set_media_status(hw, type)) 1192 return -EOPNOTSUPP; 1193 1194 if (rtlpriv->mac80211.link_state == MAC80211_LINKED) { 1195 if (type != NL80211_IFTYPE_AP) 1196 rtl92se_set_check_bssid(hw, true); 1197 } else { 1198 rtl92se_set_check_bssid(hw, false); 1199 } 1200 1201 return 0; 1202} 1203 1204/* don't set REG_EDCA_BE_PARAM here because mac80211 will send pkt when scan */ 1205void rtl92se_set_qos(struct ieee80211_hw *hw, int aci) 1206{ 1207 struct rtl_priv *rtlpriv = rtl_priv(hw); 1208 rtl92s_dm_init_edca_turbo(hw); 1209 1210 switch (aci) { 1211 case AC1_BK: 1212 rtl_write_dword(rtlpriv, EDCAPARA_BK, 0xa44f); 1213 break; 1214 case AC0_BE: 1215 /* rtl_write_dword(rtlpriv, EDCAPARA_BE, u4b_ac_param); */ 1216 break; 1217 case AC2_VI: 1218 rtl_write_dword(rtlpriv, EDCAPARA_VI, 0x5e4322); 1219 break; 1220 case AC3_VO: 1221 rtl_write_dword(rtlpriv, EDCAPARA_VO, 0x2f3222); 1222 break; 1223 default: 1224 WARN_ONCE(true, "rtl8192se: invalid aci: %d !\n", aci); 1225 break; 1226 } 1227} 1228 1229void rtl92se_enable_interrupt(struct ieee80211_hw *hw) 1230{ 1231 struct rtl_priv *rtlpriv = rtl_priv(hw); 1232 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1233 1234 rtl_write_dword(rtlpriv, INTA_MASK, rtlpci->irq_mask[0]); 1235 /* Support Bit 32-37(Assign as Bit 0-5) interrupt setting now */ 1236 rtl_write_dword(rtlpriv, INTA_MASK + 4, rtlpci->irq_mask[1] & 0x3F); 1237 rtlpci->irq_enabled = true; 1238} 1239 1240void rtl92se_disable_interrupt(struct ieee80211_hw *hw) 1241{ 1242 struct rtl_priv *rtlpriv; 1243 struct rtl_pci *rtlpci; 1244 1245 rtlpriv = rtl_priv(hw); 1246 /* if firmware not available, no interrupts */ 1247 if (!rtlpriv || !rtlpriv->max_fw_size) 1248 return; 1249 rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1250 rtl_write_dword(rtlpriv, INTA_MASK, 0); 1251 rtl_write_dword(rtlpriv, INTA_MASK + 4, 0); 1252 rtlpci->irq_enabled = false; 1253} 1254 1255static u8 _rtl92s_set_sysclk(struct ieee80211_hw *hw, u8 data) 1256{ 1257 struct rtl_priv *rtlpriv = rtl_priv(hw); 1258 u8 waitcnt = 100; 1259 bool result = false; 1260 u8 tmp; 1261 1262 rtl_write_byte(rtlpriv, SYS_CLKR + 1, data); 1263 1264 /* Wait the MAC synchronized. */ 1265 udelay(400); 1266 1267 /* Check if it is set ready. */ 1268 tmp = rtl_read_byte(rtlpriv, SYS_CLKR + 1); 1269 result = ((tmp & BIT(7)) == (data & BIT(7))); 1270 1271 if (!(data & (BIT(6) | BIT(7)))) { 1272 waitcnt = 100; 1273 tmp = 0; 1274 1275 while (1) { 1276 waitcnt--; 1277 tmp = rtl_read_byte(rtlpriv, SYS_CLKR + 1); 1278 1279 if ((tmp & BIT(6))) 1280 break; 1281 1282 pr_err("wait for BIT(6) return value %x\n", tmp); 1283 1284 if (waitcnt == 0) 1285 break; 1286 udelay(10); 1287 } 1288 1289 if (waitcnt == 0) 1290 result = false; 1291 else 1292 result = true; 1293 } 1294 1295 return result; 1296} 1297 1298static void _rtl92s_phy_set_rfhalt(struct ieee80211_hw *hw) 1299{ 1300 struct rtl_priv *rtlpriv = rtl_priv(hw); 1301 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1302 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 1303 u8 u1btmp; 1304 1305 if (rtlhal->driver_is_goingto_unload) 1306 rtl_write_byte(rtlpriv, 0x560, 0x0); 1307 1308 /* Power save for BB/RF */ 1309 u1btmp = rtl_read_byte(rtlpriv, LDOV12D_CTRL); 1310 u1btmp |= BIT(0); 1311 rtl_write_byte(rtlpriv, LDOV12D_CTRL, u1btmp); 1312 rtl_write_byte(rtlpriv, SPS1_CTRL, 0x0); 1313 rtl_write_byte(rtlpriv, TXPAUSE, 0xFF); 1314 rtl_write_word(rtlpriv, CMDR, 0x57FC); 1315 udelay(100); 1316 rtl_write_word(rtlpriv, CMDR, 0x77FC); 1317 rtl_write_byte(rtlpriv, PHY_CCA, 0x0); 1318 udelay(10); 1319 rtl_write_word(rtlpriv, CMDR, 0x37FC); 1320 udelay(10); 1321 rtl_write_word(rtlpriv, CMDR, 0x77FC); 1322 udelay(10); 1323 rtl_write_word(rtlpriv, CMDR, 0x57FC); 1324 rtl_write_word(rtlpriv, CMDR, 0x0000); 1325 1326 if (rtlhal->driver_is_goingto_unload) { 1327 u1btmp = rtl_read_byte(rtlpriv, (REG_SYS_FUNC_EN + 1)); 1328 u1btmp &= ~(BIT(0)); 1329 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, u1btmp); 1330 } 1331 1332 u1btmp = rtl_read_byte(rtlpriv, (SYS_CLKR + 1)); 1333 1334 /* Add description. After switch control path. register 1335 * after page1 will be invisible. We can not do any IO 1336 * for register>0x40. After resume&MACIO reset, we need 1337 * to remember previous reg content. */ 1338 if (u1btmp & BIT(7)) { 1339 u1btmp &= ~(BIT(6) | BIT(7)); 1340 if (!_rtl92s_set_sysclk(hw, u1btmp)) { 1341 pr_err("Switch ctrl path fail\n"); 1342 return; 1343 } 1344 } 1345 1346 /* Power save for MAC */ 1347 if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS && 1348 !rtlhal->driver_is_goingto_unload) { 1349 /* enable LED function */ 1350 rtl_write_byte(rtlpriv, 0x03, 0xF9); 1351 /* SW/HW radio off or halt adapter!! For example S3/S4 */ 1352 } else { 1353 /* LED function disable. Power range is about 8mA now. */ 1354 /* if write 0xF1 disconnect_pci power 1355 * ifconfig wlan0 down power are both high 35:70 */ 1356 /* if write oxF9 disconnect_pci power 1357 * ifconfig wlan0 down power are both low 12:45*/ 1358 rtl_write_byte(rtlpriv, 0x03, 0xF9); 1359 } 1360 1361 rtl_write_byte(rtlpriv, SYS_CLKR + 1, 0x70); 1362 rtl_write_byte(rtlpriv, AFE_PLL_CTRL + 1, 0x68); 1363 rtl_write_byte(rtlpriv, AFE_PLL_CTRL, 0x00); 1364 rtl_write_byte(rtlpriv, LDOA15_CTRL, 0x34); 1365 rtl_write_byte(rtlpriv, AFE_XTAL_CTRL, 0x0E); 1366 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC); 1367 1368} 1369 1370static void _rtl92se_gen_refreshledstate(struct ieee80211_hw *hw) 1371{ 1372 struct rtl_priv *rtlpriv = rtl_priv(hw); 1373 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1374 enum rtl_led_pin pin0 = rtlpriv->ledctl.sw_led0; 1375 1376 if (rtlpci->up_first_time) 1377 return; 1378 1379 if (rtlpriv->psc.rfoff_reason == RF_CHANGE_BY_IPS) 1380 rtl92se_sw_led_on(hw, pin0); 1381 else 1382 rtl92se_sw_led_off(hw, pin0); 1383} 1384 1385 1386static void _rtl92se_power_domain_init(struct ieee80211_hw *hw) 1387{ 1388 struct rtl_priv *rtlpriv = rtl_priv(hw); 1389 u16 tmpu2b; 1390 u8 tmpu1b; 1391 1392 rtlpriv->psc.pwrdomain_protect = true; 1393 1394 tmpu1b = rtl_read_byte(rtlpriv, (SYS_CLKR + 1)); 1395 if (tmpu1b & BIT(7)) { 1396 tmpu1b &= ~(BIT(6) | BIT(7)); 1397 if (!_rtl92s_set_sysclk(hw, tmpu1b)) { 1398 rtlpriv->psc.pwrdomain_protect = false; 1399 return; 1400 } 1401 } 1402 1403 rtl_write_byte(rtlpriv, AFE_PLL_CTRL, 0x0); 1404 rtl_write_byte(rtlpriv, LDOA15_CTRL, 0x34); 1405 1406 /* Reset MAC-IO and CPU and Core Digital BIT10/11/15 */ 1407 tmpu1b = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1); 1408 1409 /* If IPS we need to turn LED on. So we not 1410 * disable BIT 3/7 of reg3. */ 1411 if (rtlpriv->psc.rfoff_reason & (RF_CHANGE_BY_IPS | RF_CHANGE_BY_HW)) 1412 tmpu1b &= 0xFB; 1413 else 1414 tmpu1b &= 0x73; 1415 1416 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmpu1b); 1417 /* wait for BIT 10/11/15 to pull high automatically!! */ 1418 mdelay(1); 1419 1420 rtl_write_byte(rtlpriv, CMDR, 0); 1421 rtl_write_byte(rtlpriv, TCR, 0); 1422 1423 /* Data sheet not define 0x562!!! Copy from WMAC!!!!! */ 1424 tmpu1b = rtl_read_byte(rtlpriv, 0x562); 1425 tmpu1b |= 0x08; 1426 rtl_write_byte(rtlpriv, 0x562, tmpu1b); 1427 tmpu1b &= ~(BIT(3)); 1428 rtl_write_byte(rtlpriv, 0x562, tmpu1b); 1429 1430 /* Enable AFE clock source */ 1431 tmpu1b = rtl_read_byte(rtlpriv, AFE_XTAL_CTRL); 1432 rtl_write_byte(rtlpriv, AFE_XTAL_CTRL, (tmpu1b | 0x01)); 1433 /* Delay 1.5ms */ 1434 udelay(1500); 1435 tmpu1b = rtl_read_byte(rtlpriv, AFE_XTAL_CTRL + 1); 1436 rtl_write_byte(rtlpriv, AFE_XTAL_CTRL + 1, (tmpu1b & 0xfb)); 1437 1438 /* Enable AFE Macro Block's Bandgap */ 1439 tmpu1b = rtl_read_byte(rtlpriv, AFE_MISC); 1440 rtl_write_byte(rtlpriv, AFE_MISC, (tmpu1b | BIT(0))); 1441 mdelay(1); 1442 1443 /* Enable AFE Mbias */ 1444 tmpu1b = rtl_read_byte(rtlpriv, AFE_MISC); 1445 rtl_write_byte(rtlpriv, AFE_MISC, (tmpu1b | 0x02)); 1446 mdelay(1); 1447 1448 /* Enable LDOA15 block */ 1449 tmpu1b = rtl_read_byte(rtlpriv, LDOA15_CTRL); 1450 rtl_write_byte(rtlpriv, LDOA15_CTRL, (tmpu1b | BIT(0))); 1451 1452 /* Set Digital Vdd to Retention isolation Path. */ 1453 tmpu2b = rtl_read_word(rtlpriv, REG_SYS_ISO_CTRL); 1454 rtl_write_word(rtlpriv, REG_SYS_ISO_CTRL, (tmpu2b | BIT(11))); 1455 1456 1457 /* For warm reboot NIC disappera bug. */ 1458 tmpu2b = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN); 1459 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (tmpu2b | BIT(13))); 1460 1461 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL + 1, 0x68); 1462 1463 /* Enable AFE PLL Macro Block */ 1464 tmpu1b = rtl_read_byte(rtlpriv, AFE_PLL_CTRL); 1465 rtl_write_byte(rtlpriv, AFE_PLL_CTRL, (tmpu1b | BIT(0) | BIT(4))); 1466 /* Enable MAC 80MHZ clock */ 1467 tmpu1b = rtl_read_byte(rtlpriv, AFE_PLL_CTRL + 1); 1468 rtl_write_byte(rtlpriv, AFE_PLL_CTRL + 1, (tmpu1b | BIT(0))); 1469 mdelay(1); 1470 1471 /* Release isolation AFE PLL & MD */ 1472 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL, 0xA6); 1473 1474 /* Enable MAC clock */ 1475 tmpu2b = rtl_read_word(rtlpriv, SYS_CLKR); 1476 rtl_write_word(rtlpriv, SYS_CLKR, (tmpu2b | BIT(12) | BIT(11))); 1477 1478 /* Enable Core digital and enable IOREG R/W */ 1479 tmpu2b = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN); 1480 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (tmpu2b | BIT(11))); 1481 /* enable REG_EN */ 1482 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (tmpu2b | BIT(11) | BIT(15))); 1483 1484 /* Switch the control path. */ 1485 tmpu2b = rtl_read_word(rtlpriv, SYS_CLKR); 1486 rtl_write_word(rtlpriv, SYS_CLKR, (tmpu2b & (~BIT(2)))); 1487 1488 tmpu1b = rtl_read_byte(rtlpriv, (SYS_CLKR + 1)); 1489 tmpu1b = ((tmpu1b | BIT(7)) & (~BIT(6))); 1490 if (!_rtl92s_set_sysclk(hw, tmpu1b)) { 1491 rtlpriv->psc.pwrdomain_protect = false; 1492 return; 1493 } 1494 1495 rtl_write_word(rtlpriv, CMDR, 0x37FC); 1496 1497 /* After MACIO reset,we must refresh LED state. */ 1498 _rtl92se_gen_refreshledstate(hw); 1499 1500 rtlpriv->psc.pwrdomain_protect = false; 1501} 1502 1503void rtl92se_card_disable(struct ieee80211_hw *hw) 1504{ 1505 struct rtl_priv *rtlpriv = rtl_priv(hw); 1506 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1507 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1508 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 1509 enum nl80211_iftype opmode; 1510 u8 wait = 30; 1511 1512 rtlpriv->intf_ops->enable_aspm(hw); 1513 1514 if (rtlpci->driver_is_goingto_unload || 1515 ppsc->rfoff_reason > RF_CHANGE_BY_PS) 1516 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF); 1517 1518 /* we should chnge GPIO to input mode 1519 * this will drop away current about 25mA*/ 1520 rtl8192se_gpiobit3_cfg_inputmode(hw); 1521 1522 /* this is very important for ips power save */ 1523 while (wait-- >= 10 && rtlpriv->psc.pwrdomain_protect) { 1524 if (rtlpriv->psc.pwrdomain_protect) 1525 mdelay(20); 1526 else 1527 break; 1528 } 1529 1530 mac->link_state = MAC80211_NOLINK; 1531 opmode = NL80211_IFTYPE_UNSPECIFIED; 1532 _rtl92se_set_media_status(hw, opmode); 1533 1534 _rtl92s_phy_set_rfhalt(hw); 1535 udelay(100); 1536} 1537 1538void rtl92se_interrupt_recognized(struct ieee80211_hw *hw, 1539 struct rtl_int *intvec) 1540{ 1541 struct rtl_priv *rtlpriv = rtl_priv(hw); 1542 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1543 1544 intvec->inta = rtl_read_dword(rtlpriv, ISR) & rtlpci->irq_mask[0]; 1545 rtl_write_dword(rtlpriv, ISR, intvec->inta); 1546 1547 intvec->intb = rtl_read_dword(rtlpriv, ISR + 4) & rtlpci->irq_mask[1]; 1548 rtl_write_dword(rtlpriv, ISR + 4, intvec->intb); 1549} 1550 1551void rtl92se_set_beacon_related_registers(struct ieee80211_hw *hw) 1552{ 1553 struct rtl_priv *rtlpriv = rtl_priv(hw); 1554 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1555 u16 atim_window = 2; 1556 1557 /* ATIM Window (in unit of TU). */ 1558 rtl_write_word(rtlpriv, ATIMWND, atim_window); 1559 1560 /* Beacon interval (in unit of TU). */ 1561 rtl_write_word(rtlpriv, BCN_INTERVAL, mac->beacon_interval); 1562 1563 /* DrvErlyInt (in unit of TU). (Time to send 1564 * interrupt to notify driver to change 1565 * beacon content) */ 1566 rtl_write_word(rtlpriv, BCN_DRV_EARLY_INT, 10 << 4); 1567 1568 /* BcnDMATIM(in unit of us). Indicates the 1569 * time before TBTT to perform beacon queue DMA */ 1570 rtl_write_word(rtlpriv, BCN_DMATIME, 256); 1571 1572 /* Force beacon frame transmission even 1573 * after receiving beacon frame from 1574 * other ad hoc STA */ 1575 rtl_write_byte(rtlpriv, BCN_ERR_THRESH, 100); 1576 1577 /*for beacon changed */ 1578 rtl92s_phy_set_beacon_hwreg(hw, mac->beacon_interval); 1579} 1580 1581void rtl92se_set_beacon_interval(struct ieee80211_hw *hw) 1582{ 1583 struct rtl_priv *rtlpriv = rtl_priv(hw); 1584 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1585 u16 bcn_interval = mac->beacon_interval; 1586 1587 /* Beacon interval (in unit of TU). */ 1588 rtl_write_word(rtlpriv, BCN_INTERVAL, bcn_interval); 1589 /* 2008.10.24 added by tynli for beacon changed. */ 1590 rtl92s_phy_set_beacon_hwreg(hw, bcn_interval); 1591} 1592 1593void rtl92se_update_interrupt_mask(struct ieee80211_hw *hw, 1594 u32 add_msr, u32 rm_msr) 1595{ 1596 struct rtl_priv *rtlpriv = rtl_priv(hw); 1597 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1598 1599 rtl_dbg(rtlpriv, COMP_INTR, DBG_LOUD, "add_msr:%x, rm_msr:%x\n", 1600 add_msr, rm_msr); 1601 1602 if (add_msr) 1603 rtlpci->irq_mask[0] |= add_msr; 1604 1605 if (rm_msr) 1606 rtlpci->irq_mask[0] &= (~rm_msr); 1607 1608 rtl92se_disable_interrupt(hw); 1609 rtl92se_enable_interrupt(hw); 1610} 1611 1612static void _rtl8192se_get_ic_inferiority(struct ieee80211_hw *hw) 1613{ 1614 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 1615 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1616 u8 efuse_id; 1617 1618 rtlhal->ic_class = IC_INFERIORITY_A; 1619 1620 /* Only retrieving while using EFUSE. */ 1621 if ((rtlefuse->epromtype == EEPROM_BOOT_EFUSE) && 1622 !rtlefuse->autoload_failflag) { 1623 efuse_id = efuse_read_1byte(hw, EFUSE_IC_ID_OFFSET); 1624 1625 if (efuse_id == 0xfe) 1626 rtlhal->ic_class = IC_INFERIORITY_B; 1627 } 1628} 1629 1630static void _rtl92se_read_adapter_info(struct ieee80211_hw *hw) 1631{ 1632 struct rtl_priv *rtlpriv = rtl_priv(hw); 1633 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 1634 struct rtl_phy *rtlphy = &(rtlpriv->phy); 1635 struct device *dev = &rtl_pcipriv(hw)->dev.pdev->dev; 1636 u16 i, usvalue; 1637 u16 eeprom_id; 1638 u8 tempval; 1639 u8 hwinfo[HWSET_MAX_SIZE_92S]; 1640 u8 rf_path, index; 1641 1642 switch (rtlefuse->epromtype) { 1643 case EEPROM_BOOT_EFUSE: 1644 rtl_efuse_shadow_map_update(hw); 1645 break; 1646 1647 case EEPROM_93C46: 1648 pr_err("RTL819X Not boot from eeprom, check it !!\n"); 1649 return; 1650 1651 default: 1652 dev_warn(dev, "no efuse data\n"); 1653 return; 1654 } 1655 1656 memcpy(hwinfo, &rtlefuse->efuse_map[EFUSE_INIT_MAP][0], 1657 HWSET_MAX_SIZE_92S); 1658 1659 RT_PRINT_DATA(rtlpriv, COMP_INIT, DBG_DMESG, "MAP", 1660 hwinfo, HWSET_MAX_SIZE_92S); 1661 1662 eeprom_id = *((u16 *)&hwinfo[0]); 1663 if (eeprom_id != RTL8190_EEPROM_ID) { 1664 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING, 1665 "EEPROM ID(%#x) is invalid!!\n", eeprom_id); 1666 rtlefuse->autoload_failflag = true; 1667 } else { 1668 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n"); 1669 rtlefuse->autoload_failflag = false; 1670 } 1671 1672 if (rtlefuse->autoload_failflag) 1673 return; 1674 1675 _rtl8192se_get_ic_inferiority(hw); 1676 1677 /* Read IC Version && Channel Plan */ 1678 /* VID, DID SE 0xA-D */ 1679 rtlefuse->eeprom_vid = *(u16 *)&hwinfo[EEPROM_VID]; 1680 rtlefuse->eeprom_did = *(u16 *)&hwinfo[EEPROM_DID]; 1681 rtlefuse->eeprom_svid = *(u16 *)&hwinfo[EEPROM_SVID]; 1682 rtlefuse->eeprom_smid = *(u16 *)&hwinfo[EEPROM_SMID]; 1683 rtlefuse->eeprom_version = *(u16 *)&hwinfo[EEPROM_VERSION]; 1684 1685 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 1686 "EEPROMId = 0x%4x\n", eeprom_id); 1687 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 1688 "EEPROM VID = 0x%4x\n", rtlefuse->eeprom_vid); 1689 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 1690 "EEPROM DID = 0x%4x\n", rtlefuse->eeprom_did); 1691 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 1692 "EEPROM SVID = 0x%4x\n", rtlefuse->eeprom_svid); 1693 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 1694 "EEPROM SMID = 0x%4x\n", rtlefuse->eeprom_smid); 1695 1696 for (i = 0; i < 6; i += 2) { 1697 usvalue = *(u16 *)&hwinfo[EEPROM_MAC_ADDR + i]; 1698 *((u16 *) (&rtlefuse->dev_addr[i])) = usvalue; 1699 } 1700 1701 for (i = 0; i < 6; i++) 1702 rtl_write_byte(rtlpriv, MACIDR0 + i, rtlefuse->dev_addr[i]); 1703 1704 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, "%pM\n", rtlefuse->dev_addr); 1705 1706 /* Get Tx Power Level by Channel */ 1707 /* Read Tx power of Channel 1 ~ 14 from EEPROM. */ 1708 /* 92S suupport RF A & B */ 1709 for (rf_path = 0; rf_path < 2; rf_path++) { 1710 for (i = 0; i < 3; i++) { 1711 /* Read CCK RF A & B Tx power */ 1712 rtlefuse->eeprom_chnlarea_txpwr_cck[rf_path][i] = 1713 hwinfo[EEPROM_TXPOWERBASE + rf_path * 3 + i]; 1714 1715 /* Read OFDM RF A & B Tx power for 1T */ 1716 rtlefuse->eeprom_chnlarea_txpwr_ht40_1s[rf_path][i] = 1717 hwinfo[EEPROM_TXPOWERBASE + 6 + rf_path * 3 + i]; 1718 1719 /* Read OFDM RF A & B Tx power for 2T */ 1720 rtlefuse->eprom_chnl_txpwr_ht40_2sdf[rf_path][i] 1721 = hwinfo[EEPROM_TXPOWERBASE + 12 + 1722 rf_path * 3 + i]; 1723 } 1724 } 1725 1726 for (rf_path = 0; rf_path < 2; rf_path++) 1727 for (i = 0; i < 3; i++) 1728 RTPRINT(rtlpriv, FINIT, INIT_EEPROM, 1729 "RF(%d) EEPROM CCK Area(%d) = 0x%x\n", 1730 rf_path, i, 1731 rtlefuse->eeprom_chnlarea_txpwr_cck 1732 [rf_path][i]); 1733 for (rf_path = 0; rf_path < 2; rf_path++) 1734 for (i = 0; i < 3; i++) 1735 RTPRINT(rtlpriv, FINIT, INIT_EEPROM, 1736 "RF(%d) EEPROM HT40 1S Area(%d) = 0x%x\n", 1737 rf_path, i, 1738 rtlefuse->eeprom_chnlarea_txpwr_ht40_1s 1739 [rf_path][i]); 1740 for (rf_path = 0; rf_path < 2; rf_path++) 1741 for (i = 0; i < 3; i++) 1742 RTPRINT(rtlpriv, FINIT, INIT_EEPROM, 1743 "RF(%d) EEPROM HT40 2S Diff Area(%d) = 0x%x\n", 1744 rf_path, i, 1745 rtlefuse->eprom_chnl_txpwr_ht40_2sdf 1746 [rf_path][i]); 1747 1748 for (rf_path = 0; rf_path < 2; rf_path++) { 1749 1750 /* Assign dedicated channel tx power */ 1751 for (i = 0; i < 14; i++) { 1752 /* channel 1~3 use the same Tx Power Level. */ 1753 if (i < 3) 1754 index = 0; 1755 /* Channel 4-8 */ 1756 else if (i < 8) 1757 index = 1; 1758 /* Channel 9-14 */ 1759 else 1760 index = 2; 1761 1762 /* Record A & B CCK /OFDM - 1T/2T Channel area 1763 * tx power */ 1764 rtlefuse->txpwrlevel_cck[rf_path][i] = 1765 rtlefuse->eeprom_chnlarea_txpwr_cck 1766 [rf_path][index]; 1767 rtlefuse->txpwrlevel_ht40_1s[rf_path][i] = 1768 rtlefuse->eeprom_chnlarea_txpwr_ht40_1s 1769 [rf_path][index]; 1770 rtlefuse->txpwrlevel_ht40_2s[rf_path][i] = 1771 rtlefuse->eprom_chnl_txpwr_ht40_2sdf 1772 [rf_path][index]; 1773 } 1774 1775 for (i = 0; i < 14; i++) { 1776 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 1777 "RF(%d)-Ch(%d) [CCK / HT40_1S / HT40_2S] = [0x%x / 0x%x / 0x%x]\n", 1778 rf_path, i, 1779 rtlefuse->txpwrlevel_cck[rf_path][i], 1780 rtlefuse->txpwrlevel_ht40_1s[rf_path][i], 1781 rtlefuse->txpwrlevel_ht40_2s[rf_path][i]); 1782 } 1783 } 1784 1785 for (rf_path = 0; rf_path < 2; rf_path++) { 1786 for (i = 0; i < 3; i++) { 1787 /* Read Power diff limit. */ 1788 rtlefuse->eeprom_pwrgroup[rf_path][i] = 1789 hwinfo[EEPROM_TXPWRGROUP + rf_path * 3 + i]; 1790 } 1791 } 1792 1793 for (rf_path = 0; rf_path < 2; rf_path++) { 1794 /* Fill Pwr group */ 1795 for (i = 0; i < 14; i++) { 1796 /* Chanel 1-3 */ 1797 if (i < 3) 1798 index = 0; 1799 /* Channel 4-8 */ 1800 else if (i < 8) 1801 index = 1; 1802 /* Channel 9-13 */ 1803 else 1804 index = 2; 1805 1806 rtlefuse->pwrgroup_ht20[rf_path][i] = 1807 (rtlefuse->eeprom_pwrgroup[rf_path][index] & 1808 0xf); 1809 rtlefuse->pwrgroup_ht40[rf_path][i] = 1810 ((rtlefuse->eeprom_pwrgroup[rf_path][index] & 1811 0xf0) >> 4); 1812 1813 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 1814 "RF-%d pwrgroup_ht20[%d] = 0x%x\n", 1815 rf_path, i, 1816 rtlefuse->pwrgroup_ht20[rf_path][i]); 1817 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 1818 "RF-%d pwrgroup_ht40[%d] = 0x%x\n", 1819 rf_path, i, 1820 rtlefuse->pwrgroup_ht40[rf_path][i]); 1821 } 1822 } 1823 1824 for (i = 0; i < 14; i++) { 1825 /* Read tx power difference between HT OFDM 20/40 MHZ */ 1826 /* channel 1-3 */ 1827 if (i < 3) 1828 index = 0; 1829 /* Channel 4-8 */ 1830 else if (i < 8) 1831 index = 1; 1832 /* Channel 9-14 */ 1833 else 1834 index = 2; 1835 1836 tempval = hwinfo[EEPROM_TX_PWR_HT20_DIFF + index] & 0xff; 1837 rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] = (tempval & 0xF); 1838 rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] = 1839 ((tempval >> 4) & 0xF); 1840 1841 /* Read OFDM<->HT tx power diff */ 1842 /* Channel 1-3 */ 1843 if (i < 3) 1844 index = 0; 1845 /* Channel 4-8 */ 1846 else if (i < 8) 1847 index = 0x11; 1848 /* Channel 9-14 */ 1849 else 1850 index = 1; 1851 1852 tempval = hwinfo[EEPROM_TX_PWR_OFDM_DIFF + index] & 0xff; 1853 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i] = 1854 (tempval & 0xF); 1855 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i] = 1856 ((tempval >> 4) & 0xF); 1857 1858 tempval = hwinfo[TX_PWR_SAFETY_CHK]; 1859 rtlefuse->txpwr_safetyflag = (tempval & 0x01); 1860 } 1861 1862 rtlefuse->eeprom_regulatory = 0; 1863 if (rtlefuse->eeprom_version >= 2) { 1864 /* BIT(0)~2 */ 1865 if (rtlefuse->eeprom_version >= 4) 1866 rtlefuse->eeprom_regulatory = 1867 (hwinfo[EEPROM_REGULATORY] & 0x7); 1868 else /* BIT(0) */ 1869 rtlefuse->eeprom_regulatory = 1870 (hwinfo[EEPROM_REGULATORY] & 0x1); 1871 } 1872 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 1873 "eeprom_regulatory = 0x%x\n", rtlefuse->eeprom_regulatory); 1874 1875 for (i = 0; i < 14; i++) 1876 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 1877 "RF-A Ht20 to HT40 Diff[%d] = 0x%x\n", 1878 i, rtlefuse->txpwr_ht20diff[RF90_PATH_A][i]); 1879 for (i = 0; i < 14; i++) 1880 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 1881 "RF-A Legacy to Ht40 Diff[%d] = 0x%x\n", 1882 i, rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i]); 1883 for (i = 0; i < 14; i++) 1884 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 1885 "RF-B Ht20 to HT40 Diff[%d] = 0x%x\n", 1886 i, rtlefuse->txpwr_ht20diff[RF90_PATH_B][i]); 1887 for (i = 0; i < 14; i++) 1888 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 1889 "RF-B Legacy to HT40 Diff[%d] = 0x%x\n", 1890 i, rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i]); 1891 1892 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 1893 "TxPwrSafetyFlag = %d\n", rtlefuse->txpwr_safetyflag); 1894 1895 /* Read RF-indication and Tx Power gain 1896 * index diff of legacy to HT OFDM rate. */ 1897 tempval = hwinfo[EEPROM_RFIND_POWERDIFF] & 0xff; 1898 rtlefuse->eeprom_txpowerdiff = tempval; 1899 rtlefuse->legacy_ht_txpowerdiff = 1900 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][0]; 1901 1902 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 1903 "TxPowerDiff = %#x\n", rtlefuse->eeprom_txpowerdiff); 1904 1905 /* Get TSSI value for each path. */ 1906 usvalue = *(u16 *)&hwinfo[EEPROM_TSSI_A]; 1907 rtlefuse->eeprom_tssi[RF90_PATH_A] = (u8)((usvalue & 0xff00) >> 8); 1908 usvalue = hwinfo[EEPROM_TSSI_B]; 1909 rtlefuse->eeprom_tssi[RF90_PATH_B] = (u8)(usvalue & 0xff); 1910 1911 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, "TSSI_A = 0x%x, TSSI_B = 0x%x\n", 1912 rtlefuse->eeprom_tssi[RF90_PATH_A], 1913 rtlefuse->eeprom_tssi[RF90_PATH_B]); 1914 1915 /* Read antenna tx power offset of B/C/D to A from EEPROM */ 1916 /* and read ThermalMeter from EEPROM */ 1917 tempval = hwinfo[EEPROM_THERMALMETER]; 1918 rtlefuse->eeprom_thermalmeter = tempval; 1919 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 1920 "thermalmeter = 0x%x\n", rtlefuse->eeprom_thermalmeter); 1921 1922 /* ThermalMeter, BIT(0)~3 for RFIC1, BIT(4)~7 for RFIC2 */ 1923 rtlefuse->thermalmeter[0] = (rtlefuse->eeprom_thermalmeter & 0x1f); 1924 rtlefuse->tssi_13dbm = rtlefuse->eeprom_thermalmeter * 100; 1925 1926 /* Read CrystalCap from EEPROM */ 1927 tempval = hwinfo[EEPROM_CRYSTALCAP] >> 4; 1928 rtlefuse->eeprom_crystalcap = tempval; 1929 /* CrystalCap, BIT(12)~15 */ 1930 rtlefuse->crystalcap = rtlefuse->eeprom_crystalcap; 1931 1932 /* Read IC Version && Channel Plan */ 1933 /* Version ID, Channel plan */ 1934 rtlefuse->eeprom_channelplan = hwinfo[EEPROM_CHANNELPLAN]; 1935 rtlefuse->txpwr_fromeprom = true; 1936 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 1937 "EEPROM ChannelPlan = 0x%4x\n", rtlefuse->eeprom_channelplan); 1938 1939 /* Read Customer ID or Board Type!!! */ 1940 tempval = hwinfo[EEPROM_BOARDTYPE]; 1941 /* Change RF type definition */ 1942 if (tempval == 0) 1943 rtlphy->rf_type = RF_2T2R; 1944 else if (tempval == 1) 1945 rtlphy->rf_type = RF_1T2R; 1946 else if (tempval == 2) 1947 rtlphy->rf_type = RF_1T2R; 1948 else if (tempval == 3) 1949 rtlphy->rf_type = RF_1T1R; 1950 1951 /* 1T2R but 1SS (1x1 receive combining) */ 1952 rtlefuse->b1x1_recvcombine = false; 1953 if (rtlphy->rf_type == RF_1T2R) { 1954 tempval = rtl_read_byte(rtlpriv, 0x07); 1955 if (!(tempval & BIT(0))) { 1956 rtlefuse->b1x1_recvcombine = true; 1957 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 1958 "RF_TYPE=1T2R but only 1SS\n"); 1959 } 1960 } 1961 rtlefuse->b1ss_support = rtlefuse->b1x1_recvcombine; 1962 rtlefuse->eeprom_oemid = *&hwinfo[EEPROM_CUSTOMID]; 1963 1964 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "EEPROM Customer ID: 0x%2x\n", 1965 rtlefuse->eeprom_oemid); 1966 1967 /* set channel paln to world wide 13 */ 1968 rtlefuse->channel_plan = COUNTRY_CODE_WORLD_WIDE_13; 1969} 1970 1971void rtl92se_read_eeprom_info(struct ieee80211_hw *hw) 1972{ 1973 struct rtl_priv *rtlpriv = rtl_priv(hw); 1974 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 1975 u8 tmp_u1b = 0; 1976 1977 tmp_u1b = rtl_read_byte(rtlpriv, EPROM_CMD); 1978 1979 if (tmp_u1b & BIT(4)) { 1980 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EEPROM\n"); 1981 rtlefuse->epromtype = EEPROM_93C46; 1982 } else { 1983 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EFUSE\n"); 1984 rtlefuse->epromtype = EEPROM_BOOT_EFUSE; 1985 } 1986 1987 if (tmp_u1b & BIT(5)) { 1988 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n"); 1989 rtlefuse->autoload_failflag = false; 1990 _rtl92se_read_adapter_info(hw); 1991 } else { 1992 pr_err("Autoload ERR!!\n"); 1993 rtlefuse->autoload_failflag = true; 1994 } 1995} 1996 1997static void rtl92se_update_hal_rate_table(struct ieee80211_hw *hw, 1998 struct ieee80211_sta *sta) 1999{ 2000 struct rtl_priv *rtlpriv = rtl_priv(hw); 2001 struct rtl_phy *rtlphy = &(rtlpriv->phy); 2002 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 2003 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 2004 u32 ratr_value; 2005 u8 ratr_index = 0; 2006 u8 nmode = mac->ht_enable; 2007 u8 mimo_ps = IEEE80211_SMPS_OFF; 2008 u16 shortgi_rate = 0; 2009 u32 tmp_ratr_value = 0; 2010 u8 curtxbw_40mhz = mac->bw_40; 2011 u8 curshortgi_40mhz = (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ? 2012 1 : 0; 2013 u8 curshortgi_20mhz = (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ? 2014 1 : 0; 2015 enum wireless_mode wirelessmode = mac->mode; 2016 2017 if (rtlhal->current_bandtype == BAND_ON_5G) 2018 ratr_value = sta->deflink.supp_rates[1] << 4; 2019 else 2020 ratr_value = sta->deflink.supp_rates[0]; 2021 if (mac->opmode == NL80211_IFTYPE_ADHOC) 2022 ratr_value = 0xfff; 2023 ratr_value |= (sta->deflink.ht_cap.mcs.rx_mask[1] << 20 | 2024 sta->deflink.ht_cap.mcs.rx_mask[0] << 12); 2025 switch (wirelessmode) { 2026 case WIRELESS_MODE_B: 2027 ratr_value &= 0x0000000D; 2028 break; 2029 case WIRELESS_MODE_G: 2030 ratr_value &= 0x00000FF5; 2031 break; 2032 case WIRELESS_MODE_N_24G: 2033 case WIRELESS_MODE_N_5G: 2034 nmode = 1; 2035 if (mimo_ps == IEEE80211_SMPS_STATIC) { 2036 ratr_value &= 0x0007F005; 2037 } else { 2038 u32 ratr_mask; 2039 2040 if (get_rf_type(rtlphy) == RF_1T2R || 2041 get_rf_type(rtlphy) == RF_1T1R) { 2042 if (curtxbw_40mhz) 2043 ratr_mask = 0x000ff015; 2044 else 2045 ratr_mask = 0x000ff005; 2046 } else { 2047 if (curtxbw_40mhz) 2048 ratr_mask = 0x0f0ff015; 2049 else 2050 ratr_mask = 0x0f0ff005; 2051 } 2052 2053 ratr_value &= ratr_mask; 2054 } 2055 break; 2056 default: 2057 if (rtlphy->rf_type == RF_1T2R) 2058 ratr_value &= 0x000ff0ff; 2059 else 2060 ratr_value &= 0x0f0ff0ff; 2061 2062 break; 2063 } 2064 2065 if (rtlpriv->rtlhal.version >= VERSION_8192S_BCUT) 2066 ratr_value &= 0x0FFFFFFF; 2067 else if (rtlpriv->rtlhal.version == VERSION_8192S_ACUT) 2068 ratr_value &= 0x0FFFFFF0; 2069 2070 if (nmode && ((curtxbw_40mhz && 2071 curshortgi_40mhz) || (!curtxbw_40mhz && 2072 curshortgi_20mhz))) { 2073 2074 ratr_value |= 0x10000000; 2075 tmp_ratr_value = (ratr_value >> 12); 2076 2077 for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) { 2078 if ((1 << shortgi_rate) & tmp_ratr_value) 2079 break; 2080 } 2081 2082 shortgi_rate = (shortgi_rate << 12) | (shortgi_rate << 8) | 2083 (shortgi_rate << 4) | (shortgi_rate); 2084 2085 rtl_write_byte(rtlpriv, SG_RATE, shortgi_rate); 2086 } 2087 2088 rtl_write_dword(rtlpriv, ARFR0 + ratr_index * 4, ratr_value); 2089 if (ratr_value & 0xfffff000) 2090 rtl92s_phy_set_fw_cmd(hw, FW_CMD_RA_REFRESH_N); 2091 else 2092 rtl92s_phy_set_fw_cmd(hw, FW_CMD_RA_REFRESH_BG); 2093 2094 rtl_dbg(rtlpriv, COMP_RATR, DBG_DMESG, "%x\n", 2095 rtl_read_dword(rtlpriv, ARFR0)); 2096} 2097 2098static void rtl92se_update_hal_rate_mask(struct ieee80211_hw *hw, 2099 struct ieee80211_sta *sta, 2100 u8 rssi_level, bool update_bw) 2101{ 2102 struct rtl_priv *rtlpriv = rtl_priv(hw); 2103 struct rtl_phy *rtlphy = &(rtlpriv->phy); 2104 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 2105 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 2106 struct rtl_sta_info *sta_entry = NULL; 2107 u32 ratr_bitmap; 2108 u8 ratr_index = 0; 2109 u8 curtxbw_40mhz = (sta->deflink.bandwidth >= IEEE80211_STA_RX_BW_40) ? 1 : 0; 2110 u8 curshortgi_40mhz = (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ? 2111 1 : 0; 2112 u8 curshortgi_20mhz = (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ? 2113 1 : 0; 2114 enum wireless_mode wirelessmode = 0; 2115 bool shortgi = false; 2116 u32 ratr_value = 0; 2117 u8 shortgi_rate = 0; 2118 u32 mask = 0; 2119 u32 band = 0; 2120 bool bmulticast = false; 2121 u8 macid = 0; 2122 u8 mimo_ps = IEEE80211_SMPS_OFF; 2123 2124 sta_entry = (struct rtl_sta_info *) sta->drv_priv; 2125 wirelessmode = sta_entry->wireless_mode; 2126 if (mac->opmode == NL80211_IFTYPE_STATION) 2127 curtxbw_40mhz = mac->bw_40; 2128 else if (mac->opmode == NL80211_IFTYPE_AP || 2129 mac->opmode == NL80211_IFTYPE_ADHOC) 2130 macid = sta->aid + 1; 2131 2132 if (rtlhal->current_bandtype == BAND_ON_5G) 2133 ratr_bitmap = sta->deflink.supp_rates[1] << 4; 2134 else 2135 ratr_bitmap = sta->deflink.supp_rates[0]; 2136 if (mac->opmode == NL80211_IFTYPE_ADHOC) 2137 ratr_bitmap = 0xfff; 2138 ratr_bitmap |= (sta->deflink.ht_cap.mcs.rx_mask[1] << 20 | 2139 sta->deflink.ht_cap.mcs.rx_mask[0] << 12); 2140 switch (wirelessmode) { 2141 case WIRELESS_MODE_B: 2142 band |= WIRELESS_11B; 2143 ratr_index = RATR_INX_WIRELESS_B; 2144 if (ratr_bitmap & 0x0000000c) 2145 ratr_bitmap &= 0x0000000d; 2146 else 2147 ratr_bitmap &= 0x0000000f; 2148 break; 2149 case WIRELESS_MODE_G: 2150 band |= (WIRELESS_11G | WIRELESS_11B); 2151 ratr_index = RATR_INX_WIRELESS_GB; 2152 2153 if (rssi_level == 1) 2154 ratr_bitmap &= 0x00000f00; 2155 else if (rssi_level == 2) 2156 ratr_bitmap &= 0x00000ff0; 2157 else 2158 ratr_bitmap &= 0x00000ff5; 2159 break; 2160 case WIRELESS_MODE_A: 2161 band |= WIRELESS_11A; 2162 ratr_index = RATR_INX_WIRELESS_A; 2163 ratr_bitmap &= 0x00000ff0; 2164 break; 2165 case WIRELESS_MODE_N_24G: 2166 case WIRELESS_MODE_N_5G: 2167 band |= (WIRELESS_11N | WIRELESS_11G | WIRELESS_11B); 2168 ratr_index = RATR_INX_WIRELESS_NGB; 2169 2170 if (mimo_ps == IEEE80211_SMPS_STATIC) { 2171 if (rssi_level == 1) 2172 ratr_bitmap &= 0x00070000; 2173 else if (rssi_level == 2) 2174 ratr_bitmap &= 0x0007f000; 2175 else 2176 ratr_bitmap &= 0x0007f005; 2177 } else { 2178 if (rtlphy->rf_type == RF_1T2R || 2179 rtlphy->rf_type == RF_1T1R) { 2180 if (rssi_level == 1) { 2181 ratr_bitmap &= 0x000f0000; 2182 } else if (rssi_level == 3) { 2183 ratr_bitmap &= 0x000fc000; 2184 } else if (rssi_level == 5) { 2185 ratr_bitmap &= 0x000ff000; 2186 } else { 2187 if (curtxbw_40mhz) 2188 ratr_bitmap &= 0x000ff015; 2189 else 2190 ratr_bitmap &= 0x000ff005; 2191 } 2192 } else { 2193 if (rssi_level == 1) { 2194 ratr_bitmap &= 0x0f8f0000; 2195 } else if (rssi_level == 3) { 2196 ratr_bitmap &= 0x0f8fc000; 2197 } else if (rssi_level == 5) { 2198 ratr_bitmap &= 0x0f8ff000; 2199 } else { 2200 if (curtxbw_40mhz) 2201 ratr_bitmap &= 0x0f8ff015; 2202 else 2203 ratr_bitmap &= 0x0f8ff005; 2204 } 2205 } 2206 } 2207 2208 if ((curtxbw_40mhz && curshortgi_40mhz) || 2209 (!curtxbw_40mhz && curshortgi_20mhz)) { 2210 if (macid == 0) 2211 shortgi = true; 2212 else if (macid == 1) 2213 shortgi = false; 2214 } 2215 break; 2216 default: 2217 band |= (WIRELESS_11N | WIRELESS_11G | WIRELESS_11B); 2218 ratr_index = RATR_INX_WIRELESS_NGB; 2219 2220 if (rtlphy->rf_type == RF_1T2R) 2221 ratr_bitmap &= 0x000ff0ff; 2222 else 2223 ratr_bitmap &= 0x0f8ff0ff; 2224 break; 2225 } 2226 sta_entry->ratr_index = ratr_index; 2227 2228 if (rtlpriv->rtlhal.version >= VERSION_8192S_BCUT) 2229 ratr_bitmap &= 0x0FFFFFFF; 2230 else if (rtlpriv->rtlhal.version == VERSION_8192S_ACUT) 2231 ratr_bitmap &= 0x0FFFFFF0; 2232 2233 if (shortgi) { 2234 ratr_bitmap |= 0x10000000; 2235 /* Get MAX MCS available. */ 2236 ratr_value = (ratr_bitmap >> 12); 2237 for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) { 2238 if ((1 << shortgi_rate) & ratr_value) 2239 break; 2240 } 2241 2242 shortgi_rate = (shortgi_rate << 12) | (shortgi_rate << 8) | 2243 (shortgi_rate << 4) | (shortgi_rate); 2244 rtl_write_byte(rtlpriv, SG_RATE, shortgi_rate); 2245 } 2246 2247 mask |= (bmulticast ? 1 : 0) << 9 | (macid & 0x1f) << 4 | (band & 0xf); 2248 2249 rtl_dbg(rtlpriv, COMP_RATR, DBG_TRACE, "mask = %x, bitmap = %x\n", 2250 mask, ratr_bitmap); 2251 rtl_write_dword(rtlpriv, 0x2c4, ratr_bitmap); 2252 rtl_write_dword(rtlpriv, WFM5, (FW_RA_UPDATE_MASK | (mask << 8))); 2253 2254 if (macid != 0) 2255 sta_entry->ratr_index = ratr_index; 2256} 2257 2258void rtl92se_update_hal_rate_tbl(struct ieee80211_hw *hw, 2259 struct ieee80211_sta *sta, u8 rssi_level, bool update_bw) 2260{ 2261 struct rtl_priv *rtlpriv = rtl_priv(hw); 2262 2263 if (rtlpriv->dm.useramask) 2264 rtl92se_update_hal_rate_mask(hw, sta, rssi_level, update_bw); 2265 else 2266 rtl92se_update_hal_rate_table(hw, sta); 2267} 2268 2269void rtl92se_update_channel_access_setting(struct ieee80211_hw *hw) 2270{ 2271 struct rtl_priv *rtlpriv = rtl_priv(hw); 2272 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 2273 u16 sifs_timer; 2274 2275 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME, 2276 &mac->slot_time); 2277 sifs_timer = 0x0e0e; 2278 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer); 2279 2280} 2281 2282/* this ifunction is for RFKILL, it's different with windows, 2283 * because UI will disable wireless when GPIO Radio Off. 2284 * And here we not check or Disable/Enable ASPM like windows*/ 2285bool rtl92se_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid) 2286{ 2287 struct rtl_priv *rtlpriv = rtl_priv(hw); 2288 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 2289 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 2290 enum rf_pwrstate rfpwr_toset /*, cur_rfstate */; 2291 unsigned long flag = 0; 2292 bool actuallyset = false; 2293 bool turnonbypowerdomain = false; 2294 2295 /* just 8191se can check gpio before firstup, 92c/92d have fixed it */ 2296 if (rtlpci->up_first_time || rtlpci->being_init_adapter) 2297 return false; 2298 2299 if (ppsc->swrf_processing) 2300 return false; 2301 2302 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag); 2303 if (ppsc->rfchange_inprogress) { 2304 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag); 2305 return false; 2306 } else { 2307 ppsc->rfchange_inprogress = true; 2308 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag); 2309 } 2310 2311 /* cur_rfstate = ppsc->rfpwr_state;*/ 2312 2313 /* because after _rtl92s_phy_set_rfhalt, all power 2314 * closed, so we must open some power for GPIO check, 2315 * or we will always check GPIO RFOFF here, 2316 * And we should close power after GPIO check */ 2317 if (RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC)) { 2318 _rtl92se_power_domain_init(hw); 2319 turnonbypowerdomain = true; 2320 } 2321 2322 rfpwr_toset = _rtl92se_rf_onoff_detect(hw); 2323 2324 if ((ppsc->hwradiooff) && (rfpwr_toset == ERFON)) { 2325 rtl_dbg(rtlpriv, COMP_RF, DBG_DMESG, 2326 "RFKILL-HW Radio ON, RF ON\n"); 2327 2328 rfpwr_toset = ERFON; 2329 ppsc->hwradiooff = false; 2330 actuallyset = true; 2331 } else if ((!ppsc->hwradiooff) && (rfpwr_toset == ERFOFF)) { 2332 rtl_dbg(rtlpriv, COMP_RF, 2333 DBG_DMESG, "RFKILL-HW Radio OFF, RF OFF\n"); 2334 2335 rfpwr_toset = ERFOFF; 2336 ppsc->hwradiooff = true; 2337 actuallyset = true; 2338 } 2339 2340 if (actuallyset) { 2341 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag); 2342 ppsc->rfchange_inprogress = false; 2343 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag); 2344 2345 /* this not include ifconfig wlan0 down case */ 2346 /* } else if (rfpwr_toset == ERFOFF || cur_rfstate == ERFOFF) { */ 2347 } else { 2348 /* because power_domain_init may be happen when 2349 * _rtl92s_phy_set_rfhalt, this will open some powers 2350 * and cause current increasing about 40 mA for ips, 2351 * rfoff and ifconfig down, so we set 2352 * _rtl92s_phy_set_rfhalt again here */ 2353 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC && 2354 turnonbypowerdomain) { 2355 _rtl92s_phy_set_rfhalt(hw); 2356 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC); 2357 } 2358 2359 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag); 2360 ppsc->rfchange_inprogress = false; 2361 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag); 2362 } 2363 2364 *valid = 1; 2365 return !ppsc->hwradiooff; 2366 2367} 2368 2369/* Is_wepkey just used for WEP used as group & pairwise key 2370 * if pairwise is AES ang group is WEP Is_wepkey == false.*/ 2371void rtl92se_set_key(struct ieee80211_hw *hw, u32 key_index, u8 *p_macaddr, 2372 bool is_group, u8 enc_algo, bool is_wepkey, bool clear_all) 2373{ 2374 struct rtl_priv *rtlpriv = rtl_priv(hw); 2375 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 2376 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 2377 u8 *macaddr = p_macaddr; 2378 2379 u32 entry_id = 0; 2380 bool is_pairwise = false; 2381 2382 static u8 cam_const_addr[4][6] = { 2383 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, 2384 {0x00, 0x00, 0x00, 0x00, 0x00, 0x01}, 2385 {0x00, 0x00, 0x00, 0x00, 0x00, 0x02}, 2386 {0x00, 0x00, 0x00, 0x00, 0x00, 0x03} 2387 }; 2388 static u8 cam_const_broad[] = { 2389 0xff, 0xff, 0xff, 0xff, 0xff, 0xff 2390 }; 2391 2392 if (clear_all) { 2393 u8 idx = 0; 2394 u8 cam_offset = 0; 2395 u8 clear_number = 5; 2396 2397 rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG, "clear_all\n"); 2398 2399 for (idx = 0; idx < clear_number; idx++) { 2400 rtl_cam_mark_invalid(hw, cam_offset + idx); 2401 rtl_cam_empty_entry(hw, cam_offset + idx); 2402 2403 if (idx < 5) { 2404 memset(rtlpriv->sec.key_buf[idx], 0, 2405 MAX_KEY_LEN); 2406 rtlpriv->sec.key_len[idx] = 0; 2407 } 2408 } 2409 2410 } else { 2411 switch (enc_algo) { 2412 case WEP40_ENCRYPTION: 2413 enc_algo = CAM_WEP40; 2414 break; 2415 case WEP104_ENCRYPTION: 2416 enc_algo = CAM_WEP104; 2417 break; 2418 case TKIP_ENCRYPTION: 2419 enc_algo = CAM_TKIP; 2420 break; 2421 case AESCCMP_ENCRYPTION: 2422 enc_algo = CAM_AES; 2423 break; 2424 default: 2425 pr_err("switch case %#x not processed\n", 2426 enc_algo); 2427 enc_algo = CAM_TKIP; 2428 break; 2429 } 2430 2431 if (is_wepkey || rtlpriv->sec.use_defaultkey) { 2432 macaddr = cam_const_addr[key_index]; 2433 entry_id = key_index; 2434 } else { 2435 if (is_group) { 2436 macaddr = cam_const_broad; 2437 entry_id = key_index; 2438 } else { 2439 if (mac->opmode == NL80211_IFTYPE_AP) { 2440 entry_id = rtl_cam_get_free_entry(hw, 2441 p_macaddr); 2442 if (entry_id >= TOTAL_CAM_ENTRY) { 2443 pr_err("Can not find free hw security cam entry\n"); 2444 return; 2445 } 2446 } else { 2447 entry_id = CAM_PAIRWISE_KEY_POSITION; 2448 } 2449 2450 key_index = PAIRWISE_KEYIDX; 2451 is_pairwise = true; 2452 } 2453 } 2454 2455 if (rtlpriv->sec.key_len[key_index] == 0) { 2456 rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG, 2457 "delete one entry, entry_id is %d\n", 2458 entry_id); 2459 if (mac->opmode == NL80211_IFTYPE_AP) 2460 rtl_cam_del_entry(hw, p_macaddr); 2461 rtl_cam_delete_one_entry(hw, p_macaddr, entry_id); 2462 } else { 2463 rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG, 2464 "add one entry\n"); 2465 if (is_pairwise) { 2466 rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG, 2467 "set Pairwise key\n"); 2468 2469 rtl_cam_add_one_entry(hw, macaddr, key_index, 2470 entry_id, enc_algo, 2471 CAM_CONFIG_NO_USEDK, 2472 rtlpriv->sec.key_buf[key_index]); 2473 } else { 2474 rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG, 2475 "set group key\n"); 2476 2477 if (mac->opmode == NL80211_IFTYPE_ADHOC) { 2478 rtl_cam_add_one_entry(hw, 2479 rtlefuse->dev_addr, 2480 PAIRWISE_KEYIDX, 2481 CAM_PAIRWISE_KEY_POSITION, 2482 enc_algo, CAM_CONFIG_NO_USEDK, 2483 rtlpriv->sec.key_buf[entry_id]); 2484 } 2485 2486 rtl_cam_add_one_entry(hw, macaddr, key_index, 2487 entry_id, enc_algo, 2488 CAM_CONFIG_NO_USEDK, 2489 rtlpriv->sec.key_buf[entry_id]); 2490 } 2491 2492 } 2493 } 2494} 2495 2496void rtl92se_suspend(struct ieee80211_hw *hw) 2497{ 2498 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 2499 2500 rtlpci->up_first_time = true; 2501} 2502 2503void rtl92se_resume(struct ieee80211_hw *hw) 2504{ 2505 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 2506 u32 val; 2507 2508 pci_read_config_dword(rtlpci->pdev, 0x40, &val); 2509 if ((val & 0x0000ff00) != 0) 2510 pci_write_config_dword(rtlpci->pdev, 0x40, 2511 val & 0xffff00ff); 2512} 2513