Searched refs:SKL_DPLL_CTRL1 (Results 1 - 3 of 3) sorted by relevance

/haiku/src/add-ons/accelerants/intel_extreme/
H A DPipes.cpp574 portSel = read32(SKL_DPLL_CTRL1);
577 write32(SKL_DPLL_CTRL1, portSel | (1 << (*pllSel * 6)));
608 TRACE("Skylake DPLL_CTRL1: 0x%" B_PRIx32 "\n", read32(SKL_DPLL_CTRL1));
H A DPorts.cpp2472 linkBandwidth = (read32(SKL_DPLL_CTRL1) >> (1 + 6 * pllSel)) & SKL_DPLL_DP_LINKRATE_MASK;
/haiku/headers/private/graphics/intel_extreme/
H A Dintel_extreme.h901 #define SKL_DPLL_CTRL1 (0xc058 | REGS_NORTH_PIPE_AND_PORT) macro

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