1/* 2 * Copyright 2006-2016, Haiku, Inc. All Rights Reserved. 3 * Distributed under the terms of the MIT License. 4 * 5 * Authors: 6 * Axel D��rfler, axeld@pinc-software.de 7 * Alexander von Gluck, kallisti5@unixzen.com 8 */ 9#ifndef INTEL_EXTREME_H 10#define INTEL_EXTREME_H 11 12 13#include "lock.h" 14 15#include <Accelerant.h> 16#include <Drivers.h> 17#include <PCI.h> 18 19#include <edid.h> 20 21 22#define VENDOR_ID_INTEL 0x8086 23 24#define INTEL_FAMILY_MASK 0x00ff0000 25#define INTEL_GROUP_MASK 0x00fffff0 26#define INTEL_MODEL_MASK 0x00ffffff 27#define INTEL_TYPE_MASK 0x0000000f 28 29// families 30#define INTEL_FAMILY_8xx 0x00020000 // Second Gen 31#define INTEL_FAMILY_9xx 0x00040000 // Third Gen + 32#define INTEL_FAMILY_SER5 0x00080000 // Intel5 Series 33#define INTEL_FAMILY_SOC0 0x00200000 // Atom SOC 34#define INTEL_FAMILY_LAKE 0x00400000 // Intel Lakes 35 36// groups 37#define INTEL_GROUP_83x (INTEL_FAMILY_8xx | 0x0010) 38#define INTEL_GROUP_85x (INTEL_FAMILY_8xx | 0x0020) 39#define INTEL_GROUP_91x (INTEL_FAMILY_9xx | 0x0010) 40#define INTEL_GROUP_94x (INTEL_FAMILY_9xx | 0x0020) 41#define INTEL_GROUP_96x (INTEL_FAMILY_9xx | 0x0040) 42#define INTEL_GROUP_Gxx (INTEL_FAMILY_9xx | 0x0080) 43#define INTEL_GROUP_G4x (INTEL_FAMILY_9xx | 0x0100) 44#define INTEL_GROUP_PIN (INTEL_FAMILY_9xx | 0x0200) // PineView 45#define INTEL_GROUP_ILK (INTEL_FAMILY_SER5 | 0x0010) // IronLake 46#define INTEL_GROUP_SNB (INTEL_FAMILY_SER5 | 0x0020) // SandyBridge 47#define INTEL_GROUP_IVB (INTEL_FAMILY_SER5 | 0x0040) // IvyBridge 48#define INTEL_GROUP_HAS (INTEL_FAMILY_SER5 | 0x0080) // Haswell 49#define INTEL_GROUP_VLV (INTEL_FAMILY_SOC0 | 0x0010) // ValleyView 50#define INTEL_GROUP_CHV (INTEL_FAMILY_SOC0 | 0x0020) // CherryView 51#define INTEL_GROUP_BDW (INTEL_FAMILY_SOC0 | 0x0040) // Broadwell 52#define INTEL_GROUP_SKY (INTEL_FAMILY_LAKE | 0x0010) // SkyLake 53#define INTEL_GROUP_KBY (INTEL_FAMILY_LAKE | 0x0020) // KabyLake 54#define INTEL_GROUP_CFL (INTEL_FAMILY_LAKE | 0x0040) // CoffeeLake 55#define INTEL_GROUP_CML (INTEL_FAMILY_LAKE | 0x0080) // CometLake 56#define INTEL_GROUP_JSL (INTEL_FAMILY_LAKE | 0x0100) // JasperLake 57#define INTEL_GROUP_TGL (INTEL_FAMILY_LAKE | 0x0200) // TigerLake 58// models 59#define INTEL_TYPE_SERVER 0x0004 60#define INTEL_TYPE_MOBILE 0x0008 61#define INTEL_MODEL_915 (INTEL_GROUP_91x) 62#define INTEL_MODEL_915M (INTEL_GROUP_91x | INTEL_TYPE_MOBILE) 63#define INTEL_MODEL_945 (INTEL_GROUP_94x) 64#define INTEL_MODEL_945M (INTEL_GROUP_94x | INTEL_TYPE_MOBILE) 65#define INTEL_MODEL_965 (INTEL_GROUP_96x) 66#define INTEL_MODEL_965M (INTEL_GROUP_96x | INTEL_TYPE_MOBILE) 67#define INTEL_MODEL_G33 (INTEL_GROUP_Gxx) 68#define INTEL_MODEL_G45 (INTEL_GROUP_G4x) 69#define INTEL_MODEL_GM45 (INTEL_GROUP_G4x | INTEL_TYPE_MOBILE) 70#define INTEL_MODEL_PINE (INTEL_GROUP_PIN) 71#define INTEL_MODEL_PINEM (INTEL_GROUP_PIN | INTEL_TYPE_MOBILE) 72#define INTEL_MODEL_ILKG (INTEL_GROUP_ILK) 73#define INTEL_MODEL_ILKGM (INTEL_GROUP_ILK | INTEL_TYPE_MOBILE) 74#define INTEL_MODEL_SNBG (INTEL_GROUP_SNB) 75#define INTEL_MODEL_SNBGM (INTEL_GROUP_SNB | INTEL_TYPE_MOBILE) 76#define INTEL_MODEL_SNBGS (INTEL_GROUP_SNB | INTEL_TYPE_SERVER) 77#define INTEL_MODEL_IVBG (INTEL_GROUP_IVB) 78#define INTEL_MODEL_IVBGM (INTEL_GROUP_IVB | INTEL_TYPE_MOBILE) 79#define INTEL_MODEL_IVBGS (INTEL_GROUP_IVB | INTEL_TYPE_SERVER) 80#define INTEL_MODEL_HAS (INTEL_GROUP_HAS) 81#define INTEL_MODEL_HASM (INTEL_GROUP_HAS | INTEL_TYPE_MOBILE) 82#define INTEL_MODEL_VLV (INTEL_GROUP_VLV) 83#define INTEL_MODEL_VLVM (INTEL_GROUP_VLV | INTEL_TYPE_MOBILE) 84#define INTEL_MODEL_BDW (INTEL_GROUP_BDW) 85#define INTEL_MODEL_BDWM (INTEL_GROUP_BDW | INTEL_TYPE_MOBILE) 86#define INTEL_MODEL_BDWS (INTEL_GROUP_BDW | INTEL_TYPE_SERVER) 87#define INTEL_MODEL_SKY (INTEL_GROUP_SKY) 88#define INTEL_MODEL_SKYM (INTEL_GROUP_SKY | INTEL_TYPE_MOBILE) 89#define INTEL_MODEL_SKYS (INTEL_GROUP_SKY | INTEL_TYPE_SERVER) 90#define INTEL_MODEL_KBY (INTEL_GROUP_KBY) 91#define INTEL_MODEL_KBYM (INTEL_GROUP_KBY | INTEL_TYPE_MOBILE) 92#define INTEL_MODEL_CFL (INTEL_GROUP_CFL) 93#define INTEL_MODEL_CFLM (INTEL_GROUP_CFL | INTEL_TYPE_MOBILE) 94#define INTEL_MODEL_CML (INTEL_GROUP_CML) 95#define INTEL_MODEL_CMLM (INTEL_GROUP_CML | INTEL_TYPE_MOBILE) 96#define INTEL_MODEL_JSL (INTEL_GROUP_JSL) 97#define INTEL_MODEL_JSLM (INTEL_GROUP_JSL | INTEL_TYPE_MOBILE) 98#define INTEL_MODEL_TGLM (INTEL_GROUP_TGL | INTEL_TYPE_MOBILE) 99 100#define INTEL_PCH_DEVICE_ID_MASK 0xff80 101#define INTEL_PCH_IBX_DEVICE_ID 0x3b00 102#define INTEL_PCH_CPT_DEVICE_ID 0x1c00 103#define INTEL_PCH_PPT_DEVICE_ID 0x1e00 104#define INTEL_PCH_LPT_DEVICE_ID 0x8c00 105#define INTEL_PCH_LPT_LP_DEVICE_ID 0x9c00 106#define INTEL_PCH_WPT_DEVICE_ID 0x8c80 107#define INTEL_PCH_WPT_LP_DEVICE_ID 0x9c80 108#define INTEL_PCH_SPT_DEVICE_ID 0xa100 109#define INTEL_PCH_SPT_LP_DEVICE_ID 0x9d00 110#define INTEL_PCH_KBP_DEVICE_ID 0xa280 111#define INTEL_PCH_CNP_DEVICE_ID 0xa300 112#define INTEL_PCH_CNP_LP_DEVICE_ID 0x9d80 113#define INTEL_PCH_CMP_DEVICE_ID 0x0280 114#define INTEL_PCH_CMP2_DEVICE_ID 0x0680 115#define INTEL_PCH_CMP_V_DEVICE_ID 0xa380 116#define INTEL_PCH_ICP_DEVICE_ID 0x3480 117#define INTEL_PCH_ICP2_DEVICE_ID 0x3880 118#define INTEL_PCH_MCC_DEVICE_ID 0x4b00 119#define INTEL_PCH_TGP_DEVICE_ID 0xa080 120#define INTEL_PCH_TGP2_DEVICE_ID 0x4380 121#define INTEL_PCH_JSP_DEVICE_ID 0x4d80 122#define INTEL_PCH_ADP_DEVICE_ID 0x7a80 123#define INTEL_PCH_ADP2_DEVICE_ID 0x5180 124#define INTEL_PCH_ADP3_DEVICE_ID 0x7a00 125#define INTEL_PCH_ADP4_DEVICE_ID 0x5480 126#define INTEL_PCH_P2X_DEVICE_ID 0x7100 127#define INTEL_PCH_P3X_DEVICE_ID 0x7000 128 129// ValleyView MMIO offset 130#define VLV_DISPLAY_BASE 0x180000 131 132#define DEVICE_NAME "intel_extreme" 133#define INTEL_ACCELERANT_NAME "intel_extreme.accelerant" 134 135// We encode the register block into the value and extract/translate it when 136// actually accessing. 137#define REGISTER_BLOCK_COUNT 6 138#define REGISTER_BLOCK_SHIFT 24 139#define REGISTER_BLOCK_MASK 0xff000000 140#define REGISTER_REGISTER_MASK 0x00ffffff 141#define REGISTER_BLOCK(x) ((x & REGISTER_BLOCK_MASK) >> REGISTER_BLOCK_SHIFT) 142#define REGISTER_REGISTER(x) (x & REGISTER_REGISTER_MASK) 143 144#define REGS_FLAT (0 << REGISTER_BLOCK_SHIFT) 145#define REGS_NORTH_SHARED (1 << REGISTER_BLOCK_SHIFT) 146#define REGS_NORTH_PIPE_AND_PORT (2 << REGISTER_BLOCK_SHIFT) 147#define REGS_NORTH_PLANE_CONTROL (3 << REGISTER_BLOCK_SHIFT) 148#define REGS_SOUTH_SHARED (4 << REGISTER_BLOCK_SHIFT) 149#define REGS_SOUTH_TRANSCODER_PORT (5 << REGISTER_BLOCK_SHIFT) 150 151// register blocks for (G)MCH/ICH based platforms 152#define MCH_SHARED_REGISTER_BASE 0x00000 153#define MCH_PIPE_AND_PORT_REGISTER_BASE 0x60000 154#define MCH_PLANE_CONTROL_REGISTER_BASE 0x70000 155 156#define ICH_SHARED_REGISTER_BASE 0x00000 157#define ICH_PORT_REGISTER_BASE 0x60000 158 159// PCH - Platform Control Hub - Some hardware moves from a MCH/ICH based 160// setup to a PCH based one, that means anything that used to communicate via 161// (G)MCH registers needs to use different ones on PCH based platforms 162// (Ironlake, SandyBridge, IvyBridge, Some Haswell). 163#define PCH_NORTH_SHARED_REGISTER_BASE 0x40000 164#define PCH_NORTH_PIPE_AND_PORT_REGISTER_BASE 0x60000 165#define PCH_NORTH_PLANE_CONTROL_REGISTER_BASE 0x70000 166#define PCH_SOUTH_SHARED_REGISTER_BASE 0xc0000 167#define PCH_SOUTH_TRANSCODER_AND_PORT_REGISTER_BASE 0xe0000 168 169 170struct DeviceType { 171 uint32 type; 172 173 DeviceType(int t) 174 { 175 type = t; 176 } 177 178 DeviceType& operator=(int t) 179 { 180 type = t; 181 return *this; 182 } 183 184 bool InFamily(uint32 family) const 185 { 186 return (type & INTEL_FAMILY_MASK) == family; 187 } 188 189 bool InGroup(uint32 group) const 190 { 191 return (type & INTEL_GROUP_MASK) == group; 192 } 193 194 bool IsModel(uint32 model) const 195 { 196 return (type & INTEL_MODEL_MASK) == model; 197 } 198 199 bool IsMobile() const 200 { 201 return (type & INTEL_TYPE_MASK) == INTEL_TYPE_MOBILE; 202 } 203 204 bool SupportsHDMI() const 205 { 206 return InGroup(INTEL_GROUP_G4x) || InFamily(INTEL_FAMILY_SER5) 207 || InFamily(INTEL_FAMILY_SOC0); 208 } 209 210 bool HasDDI() const 211 { 212 // Intel Digital Display Interface 213 return InGroup(INTEL_GROUP_HAS) || (Generation() >= 8); 214 } 215 216 int Generation() const 217 { 218 if (InFamily(INTEL_FAMILY_8xx)) 219 return 2; 220 if (InGroup(INTEL_GROUP_91x) || InGroup(INTEL_GROUP_94x) 221 || IsModel(INTEL_MODEL_G33) || InGroup(INTEL_GROUP_PIN)) 222 return 3; 223 if (InFamily(INTEL_FAMILY_9xx)) 224 return 4; 225 if (InGroup(INTEL_GROUP_ILK)) 226 return 5; 227 if (InGroup(INTEL_GROUP_SNB)) 228 return 6; 229 if (InFamily(INTEL_FAMILY_SER5) || InGroup(INTEL_GROUP_VLV)) 230 return 7; 231 if (InGroup(INTEL_GROUP_CHV) || InGroup(INTEL_GROUP_BDW)) 232 return 8; 233 if (InGroup(INTEL_GROUP_JSL)) 234 return 11; 235 if (InGroup(INTEL_GROUP_TGL)) 236 return 12; 237 if (InFamily(INTEL_FAMILY_LAKE)) 238 return 9; 239 240 // Generation 0 means something is wrong :-) 241 return 0; 242 } 243}; 244 245enum port_index { 246 INTEL_PORT_ANY, // wildcard for lookup functions 247 INTEL_PORT_A, 248 INTEL_PORT_B, 249 INTEL_PORT_C, 250 INTEL_PORT_D, 251 INTEL_PORT_E, 252 INTEL_PORT_F, 253 INTEL_PORT_G 254}; 255 256enum pch_info { 257 INTEL_PCH_NONE = 0, // No PCH present 258 INTEL_PCH_IBX, // Ibexpeak 259 INTEL_PCH_CPT, // Cougarpoint 260 INTEL_PCH_LPT, // Lynxpoint 261 INTEL_PCH_SPT, // SunrisePoint 262 INTEL_PCH_CNP, // CannonLake 263 INTEL_PCH_ICP, // IceLake 264 INTEL_PCH_JSP, // JasperLake 265 INTEL_PCH_MCC, // Mule Creek Canyon 266 INTEL_PCH_TGP, // TigerLake 267 INTEL_PCH_ADP, // AlderLake 268 INTEL_PCH_NOP 269}; 270 271// info about PLL on graphics card 272struct pll_info { 273 uint32 reference_frequency; 274 uint32 max_frequency; 275 uint32 min_frequency; 276 uint32 divisor_register; 277}; 278 279struct ring_buffer { 280 struct lock lock; 281 uint32 register_base; 282 uint32 offset; 283 uint32 size; 284 uint32 position; 285 uint32 space_left; 286 uint8* base; 287}; 288 289 290struct child_device_config { 291 uint16 handle; 292 uint16 device_type; 293#define DEVICE_TYPE_ANALOG_OUTPUT (1 << 0) 294#define DEVICE_TYPE_DIGITAL_OUTPUT (1 << 1) 295#define DEVICE_TYPE_DISPLAYPORT_OUTPUT (1 << 2) 296#define DEVICE_TYPE_VIDEO_SIGNALING (1 << 3) 297#define DEVICE_TYPE_TMDS_DVI_SIGNALING (1 << 4) 298#define DEVICE_TYPE_LVDS_SIGNALING (1 << 5) 299#define DEVICE_TYPE_HIGH_SPEED_LINK (1 << 6) 300#define DEVICE_TYPE_DUAL_CHANNEL (1 << 8) 301#define DEVICE_TYPE_COMPOSITE_OUTPUT (1 << 9) 302#define DEVICE_TYPE_MIPI_OUTPUT (1 << 10) 303#define DEVICE_TYPE_NOT_HDMI_OUTPUT (1 << 11) 304#define DEVICE_TYPE_INTERNAL_CONNECTOR (1 << 12) 305#define DEVICE_TYPE_HOTPLUG_SIGNALING (1 << 13) 306#define DEVICE_TYPE_POWER_MANAGEMENT (1 << 14) 307#define DEVICE_TYPE_CLASS_EXTENSION (1 << 15) 308 309 uint8 device_id[10]; 310 uint16 addin_offset; 311 uint8 dvo_port; 312 uint8 i2c_pin; 313 uint8 slave_addr; 314 uint8 ddc_pin; 315 uint16 edid_ptr; 316 uint8 dvo_cfg; 317 318 struct { 319 bool efp_routed:1; 320 bool lane_reversal:1; 321 bool lspcon:1; 322 bool iboost:1; 323 bool hpd_invert:1; 324 bool use_vbt_vswing:1; 325 uint8 reserved:2; 326 bool hdmi_support:1; 327 bool dp_support:1; 328 bool tmds_support:1; 329 uint8 reserved2:5; 330 uint8 aux_channel; 331 uint8 dongle_detect; 332 } __attribute__((packed)); 333 334 uint8 caps; 335 uint8 dvo_wiring; 336 uint8 dvo2_wiring; 337 uint16 extended_type; 338 uint8 dvo_function; 339 340 bool dp_usb_type_c:1; 341 bool tbt:1; 342 uint8 reserved3:2; 343 uint8 dp_port_trace_length:4; 344 uint8 dp_gpio_index; 345 uint8 dp_gpio_pin_num; 346 uint8 dp_iboost_level:4; 347 uint8 hdmi_iboost_level:4; 348 uint8 dp_max_link_rate:3; 349 uint8 dp_max_link_rate_reserved:5; 350} __attribute__((packed)); 351 352 353enum dvo_port { 354 DVO_PORT_HDMIA, 355 DVO_PORT_HDMIB, 356 DVO_PORT_HDMIC, 357 DVO_PORT_HDMID, 358 DVO_PORT_LVDS, 359 DVO_PORT_TV, 360 DVO_PORT_CRT, 361 DVO_PORT_DPB, 362 DVO_PORT_DPC, 363 DVO_PORT_DPD, 364 DVO_PORT_DPA, 365 DVO_PORT_DPE, 366 DVO_PORT_HDMIE, 367 DVO_PORT_DPF, 368 DVO_PORT_HDMIF, 369 DVO_PORT_DPG, 370 DVO_PORT_HDMIG, 371 DVO_PORT_DPH, 372 DVO_PORT_HDMIH, 373 DVO_PORT_DPI, 374 DVO_PORT_HDMII, 375}; 376 377 378enum dp_aux_channel { 379 DP_AUX_A = 0x40, 380 DP_AUX_B = 0x10, 381 DP_AUX_C = 0x20, 382 DP_AUX_D = 0x30, 383 DP_AUX_E = 0x50, 384 DP_AUX_F = 0x60, 385 DP_AUX_G = 0x70, 386 DP_AUX_H = 0x80, 387 DP_AUX_I = 0x90 388}; 389 390 391enum aux_channel { 392 AUX_CH_A, 393 AUX_CH_B, 394 AUX_CH_C, 395 AUX_CH_D, 396 AUX_CH_E, 397 AUX_CH_F, 398 AUX_CH_G, 399 AUX_CH_H, 400 AUX_CH_I, 401}; 402 403 404enum hpd_pin { 405 HPD_PORT_A, 406 HPD_PORT_B, 407 HPD_PORT_C, 408 HPD_PORT_D, 409 HPD_PORT_E, 410 HPD_PORT_TC1, 411 HPD_PORT_TC2, 412 HPD_PORT_TC3, 413 HPD_PORT_TC4, 414 HPD_PORT_TC5, 415 HPD_PORT_TC6, 416}; 417 418 419struct intel_shared_info { 420 area_id mode_list_area; // area containing display mode list 421 uint32 mode_count; 422 423 display_mode current_mode; // pretty much a hack until per-display modes 424 display_timing panel_timing; // Hardware timings of the LVDS panel, extracted from BIOS 425 uint32 bytes_per_row; 426 uint32 bits_per_pixel; 427 uint32 dpms_mode; 428 uint16 min_brightness; 429 430 area_id registers_area; // area of memory mapped registers 431 uint32 register_blocks[REGISTER_BLOCK_COUNT]; 432 433 uint8* status_page; 434 phys_addr_t physical_status_page; 435 uint8* graphics_memory; 436 phys_addr_t physical_graphics_memory; 437 uint32 graphics_memory_size; 438 439 addr_t frame_buffer; 440 uint32 frame_buffer_offset; 441 442 uint32 fdi_link_frequency; // In Mhz 443 uint32 hraw_clock; 444 uint32 hw_cdclk; 445 446 bool got_vbt; 447 bool single_head_locked; 448 449 struct lock accelerant_lock; 450 struct lock engine_lock; 451 452 ring_buffer primary_ring_buffer; 453 454 int32 overlay_channel_used; 455 bool overlay_active; 456 uintptr_t overlay_token; 457 phys_addr_t physical_overlay_registers; 458 uint32 overlay_offset; 459 460 bool hardware_cursor_enabled; 461 sem_id vblank_sem; 462 463 uint8* cursor_memory; 464 phys_addr_t physical_cursor_memory; 465 uint32 cursor_buffer_offset; 466 uint32 cursor_format; 467 bool cursor_visible; 468 uint16 cursor_hot_x; 469 uint16 cursor_hot_y; 470 471 DeviceType device_type; 472 char device_identifier[32]; 473 struct pll_info pll_info; 474 475 enum pch_info pch_info; 476 477 edid1_info vesa_edid_info; 478 bool has_vesa_edid_info; 479 480 bool internal_crt_support; 481 uint32 device_config_count; 482 child_device_config device_configs[10]; 483}; 484 485enum pipe_index { 486 INTEL_PIPE_ANY, 487 INTEL_PIPE_A, 488 INTEL_PIPE_B, 489 INTEL_PIPE_C, 490 INTEL_PIPE_D 491}; 492 493class pipes { 494public: 495 pipes() : bitmask(0) {} 496 497 bool HasPipe(pipe_index pipe) 498 { 499 if (pipe == INTEL_PIPE_ANY) 500 return bitmask != 0; 501 502 return (bitmask & (1 << pipe)) != 0; 503 } 504 505 void SetPipe(pipe_index pipe) 506 { 507 if (pipe == INTEL_PIPE_ANY) { 508 bitmask = ~1; 509 // first bit corresponds to INTEL_PIPE_ANY but it's never used, 510 // so it should be 0 511 } 512 bitmask |= (1 << pipe); 513 } 514 515 void ClearPipe(pipe_index pipe) 516 { 517 if (pipe == INTEL_PIPE_ANY) 518 bitmask = 0; 519 520 bitmask &= ~(1 << pipe); 521 } 522 523private: 524 uint8 bitmask; 525}; 526 527//----------------- ioctl() interface ---------------- 528 529// magic code for ioctls 530#define INTEL_PRIVATE_DATA_MAGIC 'itic' 531 532// list ioctls 533enum { 534 INTEL_GET_PRIVATE_DATA = B_DEVICE_OP_CODES_END + 1, 535 536 INTEL_GET_DEVICE_NAME, 537 INTEL_ALLOCATE_GRAPHICS_MEMORY, 538 INTEL_FREE_GRAPHICS_MEMORY, 539 INTEL_GET_BRIGHTNESS_LEGACY, 540 INTEL_SET_BRIGHTNESS_LEGACY 541}; 542 543// retrieve the area_id of the kernel/accelerant shared info 544struct intel_get_private_data { 545 uint32 magic; // magic number 546 area_id shared_info_area; 547}; 548 549// allocate graphics memory 550struct intel_allocate_graphics_memory { 551 uint32 magic; 552 uint32 size; 553 uint32 alignment; 554 uint32 flags; 555 addr_t buffer_base; 556}; 557 558// free graphics memory 559struct intel_free_graphics_memory { 560 uint32 magic; 561 addr_t buffer_base; 562}; 563 564// brightness legacy 565struct intel_brightness_legacy { 566 uint32 magic; 567 uint8 lpc; 568}; 569 570//---------------------------------------------------------- 571// Register definitions, taken from X driver 572 573// PCI bridge memory management 574#define INTEL_GRAPHICS_MEMORY_CONTROL 0x52 // i830+ 575 576 // GGC - (G)MCH Graphics Control Register 577#define MEMORY_CONTROL_ENABLED 0x0004 578#define MEMORY_MASK 0x0001 579#define STOLEN_MEMORY_MASK 0x00f0 580#define i965_GTT_MASK 0x000e 581#define G33_GTT_MASK 0x0300 582#define G4X_GTT_MASK 0x0f00 // GGMS (GSM Memory Size) mask 583 584// models i830 and up 585#define i830_LOCAL_MEMORY_ONLY 0x10 586#define i830_STOLEN_512K 0x20 587#define i830_STOLEN_1M 0x30 588#define i830_STOLEN_8M 0x40 589#define i830_FRAME_BUFFER_64M 0x01 590#define i830_FRAME_BUFFER_128M 0x00 591 592// models i855 and up 593#define i855_STOLEN_MEMORY_1M 0x10 594#define i855_STOLEN_MEMORY_4M 0x20 595#define i855_STOLEN_MEMORY_8M 0x30 596#define i855_STOLEN_MEMORY_16M 0x40 597#define i855_STOLEN_MEMORY_32M 0x50 598#define i855_STOLEN_MEMORY_48M 0x60 599#define i855_STOLEN_MEMORY_64M 0x70 600#define i855_STOLEN_MEMORY_128M 0x80 601#define i855_STOLEN_MEMORY_256M 0x90 602 603#define G4X_STOLEN_MEMORY_96MB 0xa0 // GMS - Graphics Mode Select 604#define G4X_STOLEN_MEMORY_160MB 0xb0 605#define G4X_STOLEN_MEMORY_224MB 0xc0 606#define G4X_STOLEN_MEMORY_352MB 0xd0 607 608// SandyBridge (SNB) 609 610#define SNB_GRAPHICS_MEMORY_CONTROL 0x50 611 612#define SNB_STOLEN_MEMORY_MASK 0xf8 613#define SNB_STOLEN_MEMORY_32MB (1 << 3) 614#define SNB_STOLEN_MEMORY_64MB (2 << 3) 615#define SNB_STOLEN_MEMORY_96MB (3 << 3) 616#define SNB_STOLEN_MEMORY_128MB (4 << 3) 617#define SNB_STOLEN_MEMORY_160MB (5 << 3) 618#define SNB_STOLEN_MEMORY_192MB (6 << 3) 619#define SNB_STOLEN_MEMORY_224MB (7 << 3) 620#define SNB_STOLEN_MEMORY_256MB (8 << 3) 621#define SNB_STOLEN_MEMORY_288MB (9 << 3) 622#define SNB_STOLEN_MEMORY_320MB (10 << 3) 623#define SNB_STOLEN_MEMORY_352MB (11 << 3) 624#define SNB_STOLEN_MEMORY_384MB (12 << 3) 625#define SNB_STOLEN_MEMORY_416MB (13 << 3) 626#define SNB_STOLEN_MEMORY_448MB (14 << 3) 627#define SNB_STOLEN_MEMORY_480MB (15 << 3) 628#define SNB_STOLEN_MEMORY_512MB (16 << 3) 629 630#define SNB_GTT_SIZE_MASK (3 << 8) 631#define SNB_GTT_SIZE_NONE (0 << 8) 632#define SNB_GTT_SIZE_1MB (1 << 8) 633#define SNB_GTT_SIZE_2MB (2 << 8) 634 635// BDW+ (GGC_0_0_0_PCI) 636 637#define BDW_GRAPHICS_MEMORY_CONTROL 0x50 638 639#define BDW_STOLEN_MEMORY_MASK 0xff00 640#define BDW_STOLEN_MEMORY_32MB (1 << 8) 641#define BDW_STOLEN_MEMORY_64MB (2 << 8) 642#define BDW_STOLEN_MEMORY_96MB (3 << 8) 643#define BDW_STOLEN_MEMORY_128MB (4 << 8) 644#define BDW_STOLEN_MEMORY_160MB (5 << 8) 645#define BDW_STOLEN_MEMORY_192MB (6 << 8) 646#define BDW_STOLEN_MEMORY_224MB (7 << 8) 647#define BDW_STOLEN_MEMORY_256MB (8 << 8) 648#define BDW_STOLEN_MEMORY_288MB (9 << 8) 649#define BDW_STOLEN_MEMORY_320MB (10 << 8) 650#define BDW_STOLEN_MEMORY_352MB (11 << 8) 651#define BDW_STOLEN_MEMORY_384MB (12 << 8) 652#define BDW_STOLEN_MEMORY_416MB (13 << 8) 653#define BDW_STOLEN_MEMORY_448MB (14 << 8) 654#define BDW_STOLEN_MEMORY_480MB (15 << 8) 655#define BDW_STOLEN_MEMORY_512MB (16 << 8) 656#define BDW_STOLEN_MEMORY_1024MB (32 << 8) 657#define BDW_STOLEN_MEMORY_1536MB (48 << 8) 658#define BDW_STOLEN_MEMORY_2016MB (63 << 8) 659#define SKL_STOLEN_MEMORY_2048MB (64 << 8) 660#define SKL_STOLEN_MEMORY_4MB (240 << 8) 661#define SKL_STOLEN_MEMORY_8MB (241 << 8) 662#define SKL_STOLEN_MEMORY_12MB (242 << 8) 663#define SKL_STOLEN_MEMORY_16MB (243 << 8) 664#define SKL_STOLEN_MEMORY_20MB (244 << 8) 665#define SKL_STOLEN_MEMORY_24MB (245 << 8) 666#define SKL_STOLEN_MEMORY_28MB (246 << 8) 667#define SKL_STOLEN_MEMORY_32MB (247 << 8) 668#define SKL_STOLEN_MEMORY_36MB (248 << 8) 669#define SKL_STOLEN_MEMORY_40MB (249 << 8) 670#define SKL_STOLEN_MEMORY_44MB (250 << 8) 671#define SKL_STOLEN_MEMORY_48MB (251 << 8) 672#define SKL_STOLEN_MEMORY_52MB (252 << 8) 673#define SKL_STOLEN_MEMORY_56MB (253 << 8) 674#define SKL_STOLEN_MEMORY_60MB (254 << 8) 675 676 677#define BDW_GTT_SIZE_MASK (3 << 6) 678#define BDW_GTT_SIZE_NONE (0 << 6) 679#define BDW_GTT_SIZE_2MB (1 << 6) 680#define BDW_GTT_SIZE_4MB (2 << 6) 681#define BDW_GTT_SIZE_8MB (3 << 6) 682 683// Gen2, i915GM, i945GM 684#define LEGACY_BACKLIGHT_BRIGHTNESS 0xf4 685 686// graphics page translation table 687#define INTEL_PAGE_TABLE_CONTROL 0x02020 688#define PAGE_TABLE_ENABLED 0x00000001 689#define INTEL_PAGE_TABLE_ERROR 0x02024 690#define INTEL_HARDWARE_STATUS_PAGE 0x02080 691#define i915_GTT_BASE 0x1c 692#define i830_GTT_BASE 0x10000 // (- 0x2ffff) 693#define i830_GTT_SIZE 0x20000 694#define i965_GTT_BASE 0x80000 // (- 0xfffff) 695#define i965_GTT_SIZE 0x80000 696#define i965_GTT_128K (2 << 1) 697#define i965_GTT_256K (1 << 1) 698#define i965_GTT_512K (0 << 1) 699#define G33_GTT_1M (1 << 8) 700#define G33_GTT_2M (2 << 8) 701#define G4X_GTT_NONE 0x000 // GGMS - GSM Memory Size 702#define G4X_GTT_1M_NO_IVT 0x100 // no Intel Virtualization Tech. 703#define G4X_GTT_2M_NO_IVT 0x300 704#define G4X_GTT_2M_IVT 0x900 // with Intel Virt. Tech. 705#define G4X_GTT_3M_IVT 0xa00 706#define G4X_GTT_4M_IVT 0xb00 707 708 709#define GTT_ENTRY_VALID 0x01 710#define GTT_ENTRY_LOCAL_MEMORY 0x02 711#define GTT_PAGE_SHIFT 12 712 713 714// ring buffer 715#define INTEL_PRIMARY_RING_BUFFER 0x02030 716#define INTEL_SECONDARY_RING_BUFFER_0 0x02100 717#define INTEL_SECONDARY_RING_BUFFER_1 0x02110 718// offsets for the ring buffer base registers above 719#define RING_BUFFER_TAIL 0x0 720#define RING_BUFFER_HEAD 0x4 721#define RING_BUFFER_START 0x8 722#define RING_BUFFER_CONTROL 0xc 723#define INTEL_RING_BUFFER_SIZE_MASK 0x001ff000 724#define INTEL_RING_BUFFER_HEAD_MASK 0x001ffffc 725#define INTEL_RING_BUFFER_ENABLED 1 726 727// interrupts 728#define INTEL_INTERRUPT_ENABLED 0x020a0 729#define INTEL_INTERRUPT_IDENTITY 0x020a4 730#define INTEL_INTERRUPT_MASK 0x020a8 731#define INTEL_INTERRUPT_STATUS 0x020ac 732#define INTERRUPT_VBLANK_PIPEA (1 << 7) 733#define INTERRUPT_VBLANK_PIPEB (1 << 5) 734 735// PCH interrupts 736#define PCH_INTERRUPT_STATUS 0x44000 737#define PCH_INTERRUPT_MASK 0x44004 738#define PCH_INTERRUPT_IDENTITY 0x44008 739#define PCH_INTERRUPT_ENABLED 0x4400c 740 741#define PCH_INTERRUPT_VBLANK_PIPEA (1 << 0) 742#define PCH_INTERRUPT_VBLANK_PIPEB (1 << 5) 743#define PCH_INTERRUPT_VBLANK_PIPEC (1 << 10) 744 745// SandyBridge had only two pipes, and things were shuffled aroud again with 746// the introduction of pipe C. 747#define PCH_INTERRUPT_VBLANK_PIPEA_SNB (1 << 7) 748#define PCH_INTERRUPT_VBLANK_PIPEB_SNB (1 << 15) 749#define PCH_INTERRUPT_GLOBAL_SNB (1 << 31) 750 751#define PCH_MASTER_INT_CTL_BDW 0x44200 752 753#define PCH_MASTER_INT_CTL_PIPE_PENDING_BDW(pipe) (1 << (15 + pipe)) 754#define GEN8_DE_PCH_IRQ (1 << 23) 755#define GEN8_DE_PORT_IRQ (1 << 20) 756#define PCH_MASTER_INT_CTL_GLOBAL_BDW (1 << 31) 757 758#define PCH_INTERRUPT_PIPE_STATUS_BDW(pipe) (0x44400 + (pipe - 1) * 0x10) // GEN8_DE_PIPE_ISR 759#define PCH_INTERRUPT_PIPE_MASK_BDW(pipe) (0x44404 + (pipe - 1) * 0x10) // GEN8_DE_PIPE_IMR 760#define PCH_INTERRUPT_PIPE_IDENTITY_BDW(pipe) (0x44408 + (pipe - 1) * 0x10) // GEN8_DE_PIPE_IIR 761#define PCH_INTERRUPT_PIPE_ENABLED_BDW(pipe) (0x4440c + (pipe - 1) * 0x10) // GEN8_DE_PIPE_IER 762 763#define GEN8_DE_PORT_ISR 0x44440 764#define GEN8_DE_PORT_IMR 0x44444 765#define GEN8_DE_PORT_IIR 0x44448 766#define GEN8_DE_PORT_IER 0x4444c 767#define GEN8_AUX_CHANNEL_A (1 << 0) 768#define GEN9_AUX_CHANNEL_B (1 << 25) 769#define GEN9_AUX_CHANNEL_C (1 << 26) 770#define GEN9_AUX_CHANNEL_D (1 << 27) 771#define CNL_AUX_CHANNEL_F (1 << 28) 772#define ICL_AUX_CHANNEL_E (1 << 29) 773 774#define GEN8_DE_MISC_ISR 0x44460 775#define GEN8_DE_MISC_IMR 0x44464 776#define GEN8_DE_MISC_IIR 0x44468 777#define GEN8_DE_MISC_IER 0x4446c 778#define GEN8_DE_EDP_PSR (1 << 19) 779 780#define GEN11_DE_HPD_ISR 0x44470 781#define GEN11_DE_HPD_IMR 0x44474 782#define GEN11_DE_HPD_IIR 0x44478 783#define GEN11_DE_HPD_IER 0x4447c 784#define GEN11_DE_TC_HOTPLUG_MASK (0x3f << 16) 785#define GEN11_DE_TBT_HOTPLUG_MASK (0x3f) 786 787#define GEN11_TBT_HOTPLUG_CTL 0x44030 788#define GEN11_TC_HOTPLUG_CTL 0x44038 789 790#define SHPD_FILTER_CNT 0xc4038 791#define SHPD_FILTER_CNT_500_ADJ 0x1d9 792 793#define SDEISR 0xc4000 794#define SDEIMR 0xc4004 795#define SDEIIR 0xc4008 796#define SDEIER 0xc400c 797#define SDE_GMBUS_ICP (1 << 23) 798 799#define SHOTPLUG_CTL_DDI 0xc4030 800#define SHOTPLUG_CTL_DDI_HPD_ENABLE(hpd_pin) (0x8 << (4 * ((hpd_pin) - HPD_PORT_A))) 801#define SHOTPLUG_CTL_TC 0xc4034 802#define SHOTPLUG_CTL_TC_HPD_ENABLE(hpd_pin) (0x8 << (4 * ((hpd_pin) - HPD_PORT_TC1))) 803 804#define PCH_PORT_HOTPLUG SHOTPLUG_CTL_DDI 805#define PCH_PORT_HOTPLUG2 0xc403c 806 807#define PCH_INTERRUPT_VBLANK_BDW (1 << 0) // GEN8_PIPE_VBLANK 808#define GEN8_PIPE_VSYNC (1 << 1) 809#define GEN8_PIPE_SCAN_LINE_EVENT (1 << 2) 810 811#define GEN11_GFX_MSTR_IRQ 0x190010 812#define GEN11_MASTER_IRQ (1 << 31) 813#define GEN11_DISPLAY_IRQ (1 << 16) 814#define GEN11_GT_DW1_IRQ (1 << 1) 815#define GEN11_GT_DW0_IRQ (1 << 0) 816 817#define GEN11_DISPLAY_INT_CTL 0x44200 // same as PCH_MASTER_INT_CTL_BDW 818#define GEN11_DE_HPD_IRQ (1 << 21) 819 820#define GEN11_GT_INTR_DW0 0x190018 821#define GEN11_GT_INTR_DW1 0x19001c 822 823#define GEN11_GU_MISC_IMR 0x444f4 824#define GEN11_GU_MISC_IIR 0x444f8 825#define GEN11_GU_MISC_IER 0x444fc 826#define GEN11_GU_MISC_GSE (1 << 27) 827 828 829// graphics port control (i.e. G45) 830#define DISPLAY_MONITOR_PORT_ENABLED (1UL << 31) 831#define DISPLAY_MONITOR_PIPE_B (1UL << 30) 832#define DISPLAY_MONITOR_VGA_POLARITY (1UL << 15) 833#define DISPLAY_MONITOR_MODE_MASK (3UL << 10) 834#define DISPLAY_MONITOR_ON 0 835#define DISPLAY_MONITOR_SUSPEND (1UL << 10) 836#define DISPLAY_MONITOR_STAND_BY (2UL << 10) 837#define DISPLAY_MONITOR_OFF (3UL << 10) 838#define DISPLAY_MONITOR_POLARITY_MASK (3UL << 3) 839#define DISPLAY_MONITOR_POSITIVE_HSYNC (1UL << 3) 840#define DISPLAY_MONITOR_POSITIVE_VSYNC (2UL << 3) 841#define DISPLAY_MONITOR_PORT_DETECTED (1UL << 2) // TMDS/DisplayPort only 842 843// Cougar Point transcoder pipe selection 844// (replaces DISPLAY_MONITOR_PIPE_B) 845#define PORT_TRANS_A_SEL_CPT 0 846#define PORT_TRANS_B_SEL_CPT (1<<29) 847#define PORT_TRANS_C_SEL_CPT (2<<29) 848#define PORT_TRANS_SEL_MASK (3<<29) 849 850#define LVDS_POST2_RATE_SLOW 14 // PLL Divisors 851#define LVDS_POST2_RATE_FAST 7 852#define LVDS_B0B3_POWER_MASK (3UL << 2) 853#define LVDS_B0B3_POWER_UP (3UL << 2) 854#define LVDS_CLKB_POWER_MASK (3UL << 4) 855#define LVDS_CLKB_POWER_UP (3UL << 4) 856#define LVDS_A3_POWER_MASK (3UL << 6) 857#define LVDS_A3_POWER_UP (3UL << 6) 858#define LVDS_A0A2_CLKA_POWER_UP (3UL << 8) 859#define LVDS_BORDER_ENABLE (1UL << 15) 860#define LVDS_HSYNC_POLARITY (1UL << 20) 861#define LVDS_VSYNC_POLARITY (1UL << 21) 862#define LVDS_18BIT_DITHER (1UL << 25) 863#define LVDS_PORT_EN (1UL << 31) 864 865// PLL flags (pre-DDI) 866#define DISPLAY_PLL_ENABLED (1UL << 31) 867#define DISPLAY_PLL_2X_CLOCK (1UL << 30) 868#define DISPLAY_PLL_SYNC_LOCK_ENABLED (1UL << 29) 869#define DISPLAY_PLL_NO_VGA_CONTROL (1UL << 28) 870#define DISPLAY_PLL_MODE_NORMAL (1UL << 26) 871#define DISPLAY_PLL_MODE_LVDS (2UL << 26) 872#define DISPLAY_PLL_DIVIDE_HIGH (1UL << 24) 873#define DISPLAY_PLL_DIVIDE_4X (1UL << 23) 874#define DISPLAY_PLL_POST1_DIVIDE_2 (1UL << 21) 875#define DISPLAY_PLL_POST1_DIVISOR_MASK 0x001f0000 876#define DISPLAY_PLL_9xx_POST1_DIVISOR_MASK 0x00ff0000 877#define DISPLAY_PLL_SNB_FP0_POST1_DIVISOR_MASK 0x000000ff 878#define DISPLAY_PLL_IGD_POST1_DIVISOR_MASK 0x00ff8000 879#define DISPLAY_PLL_POST1_DIVISOR_SHIFT 16 880#define DISPLAY_PLL_SNB_FP0_POST1_DIVISOR_SHIFT 0 881#define DISPLAY_PLL_IGD_POST1_DIVISOR_SHIFT 15 882#define DISPLAY_PLL_DIVISOR_1 (1UL << 8) 883#define DISPLAY_PLL_N_DIVISOR_MASK 0x001f0000 884#define DISPLAY_PLL_IGD_N_DIVISOR_MASK 0x00ff0000 885#define DISPLAY_PLL_M1_DIVISOR_MASK 0x00001f00 886#define DISPLAY_PLL_M2_DIVISOR_MASK 0x0000001f 887#define DISPLAY_PLL_IGD_M2_DIVISOR_MASK 0x000000ff 888#define DISPLAY_PLL_N_DIVISOR_SHIFT 16 889#define DISPLAY_PLL_M1_DIVISOR_SHIFT 8 890#define DISPLAY_PLL_M2_DIVISOR_SHIFT 0 891#define DISPLAY_PLL_PULSE_PHASE_SHIFT 9 892 893// Skylake PLLs 894#define SKL_DPLL1_CFGCR1 (0xc040 | REGS_NORTH_PIPE_AND_PORT) 895#define SKL_DPLL1_CFGCR2 (0xc044 | REGS_NORTH_PIPE_AND_PORT) 896#define SKL_DPLL2_CFGCR1 (0xc048 | REGS_NORTH_PIPE_AND_PORT) 897#define SKL_DPLL2_CFGCR2 (0xc04c | REGS_NORTH_PIPE_AND_PORT) 898#define SKL_DPLL3_CFGCR1 (0xc050 | REGS_NORTH_PIPE_AND_PORT) 899#define SKL_DPLL3_CFGCR2 (0xc054 | REGS_NORTH_PIPE_AND_PORT) 900// These exist also still in CoffeeLake (confirmed): 901#define SKL_DPLL_CTRL1 (0xc058 | REGS_NORTH_PIPE_AND_PORT) 902#define SKL_DPLL_CTRL2 (0xc05c | REGS_NORTH_PIPE_AND_PORT) 903#define SKL_DPLL_STATUS (0xc060 | REGS_NORTH_PIPE_AND_PORT) 904#define SKL_DPLL0_DP_LINKRATE_SHIFT 1 905#define SKL_DPLL1_DP_LINKRATE_SHIFT 7 906#define SKL_DPLL2_DP_LINKRATE_SHIFT 13 907#define SKL_DPLL3_DP_LINKRATE_SHIFT 19 908#define SKL_DPLL_DP_LINKRATE_MASK 7 909#define SKL_DPLL_CTRL1_2700 0 910#define SKL_DPLL_CTRL1_1350 1 911#define SKL_DPLL_CTRL1_810 2 912#define SKL_DPLL_CTRL1_1620 3 913#define SKL_DPLL_CTRL1_1080 4 914#define SKL_DPLL_CTRL1_2160 5 915 916// Icelake PLLs 917#define ICL_DSSM 0x51004 918#define ICL_DSSM_REF_FREQ_SHIFT 29 919#define ICL_DSSM_REF_FREQ_MASK (7 << ICL_DSSM_REF_FREQ_SHIFT) 920#define ICL_DSSM_24000 0 921#define ICL_DSSM_19200 1 922#define ICL_DSSM_38400 2 923 924#define LCPLL_CTL 0x130040 925#define LCPLL_CLK_FREQ_MASK (3 << 26) 926#define LCPLL_CLK_FREQ_450 (0 << 26) 927#define LCPLL_CLK_FREQ_54O_BDW (1 << 26) 928#define LCPLL_CLK_FREQ_337_5_BDW (2 << 26) 929#define LCPLL_CD_SOURCE_FCLK (1 << 21) 930 931#define FUSE_STRAP 0x42014 932#define HSW_CDCLK_LIMIT (1 << 24) 933 934// display 935 936#define INTEL_DISPLAY_OFFSET 0x1000 937 938// Note: on Skylake below registers are part of the transcoder 939#define INTEL_DISPLAY_A_HTOTAL (0x0000 | REGS_NORTH_PIPE_AND_PORT) 940#define INTEL_DISPLAY_A_HBLANK (0x0004 | REGS_NORTH_PIPE_AND_PORT) 941#define INTEL_DISPLAY_A_HSYNC (0x0008 | REGS_NORTH_PIPE_AND_PORT) 942#define INTEL_DISPLAY_A_VTOTAL (0x000c | REGS_NORTH_PIPE_AND_PORT) 943#define INTEL_DISPLAY_A_VBLANK (0x0010 | REGS_NORTH_PIPE_AND_PORT) 944#define INTEL_DISPLAY_A_VSYNC (0x0014 | REGS_NORTH_PIPE_AND_PORT) 945#define INTEL_DISPLAY_B_HTOTAL (0x1000 | REGS_NORTH_PIPE_AND_PORT) 946#define INTEL_DISPLAY_B_HBLANK (0x1004 | REGS_NORTH_PIPE_AND_PORT) 947#define INTEL_DISPLAY_B_HSYNC (0x1008 | REGS_NORTH_PIPE_AND_PORT) 948#define INTEL_DISPLAY_B_VTOTAL (0x100c | REGS_NORTH_PIPE_AND_PORT) 949#define INTEL_DISPLAY_B_VBLANK (0x1010 | REGS_NORTH_PIPE_AND_PORT) 950#define INTEL_DISPLAY_B_VSYNC (0x1014 | REGS_NORTH_PIPE_AND_PORT) 951 952#define INTEL_DISPLAY_A_PIPE_SIZE (0x001c | REGS_NORTH_PIPE_AND_PORT) 953#define INTEL_DISPLAY_B_PIPE_SIZE (0x101c | REGS_NORTH_PIPE_AND_PORT) 954 955//G45 displayport link 956#define INTEL_PIPE_A_DATA_M (0x0050 | REGS_NORTH_PLANE_CONTROL) 957#define INTEL_PIPE_B_DATA_M (0x1050 | REGS_NORTH_PLANE_CONTROL) 958#define INTEL_PIPE_A_DATA_N (0x0054 | REGS_NORTH_PLANE_CONTROL) 959#define INTEL_PIPE_B_DATA_N (0x1054 | REGS_NORTH_PLANE_CONTROL) 960#define INTEL_PIPE_A_LINK_M (0x0060 | REGS_NORTH_PLANE_CONTROL) 961#define INTEL_PIPE_B_LINK_M (0x1060 | REGS_NORTH_PLANE_CONTROL) 962#define INTEL_PIPE_A_LINK_N (0x0064 | REGS_NORTH_PLANE_CONTROL) 963#define INTEL_PIPE_B_LINK_N (0x1064 | REGS_NORTH_PLANE_CONTROL) 964 965//DDI port link 966#define INTEL_DDI_PIPE_A_DATA_M (0x0030 | REGS_NORTH_PIPE_AND_PORT) 967#define INTEL_DDI_PIPE_B_DATA_M (0x1030 | REGS_NORTH_PIPE_AND_PORT) 968#define INTEL_DDI_PIPE_A_DATA_N (0x0034 | REGS_NORTH_PIPE_AND_PORT) 969#define INTEL_DDI_PIPE_B_DATA_N (0x1034 | REGS_NORTH_PIPE_AND_PORT) 970#define INTEL_DDI_PIPE_A_LINK_M (0x0040 | REGS_NORTH_PIPE_AND_PORT) 971#define INTEL_DDI_PIPE_B_LINK_M (0x1040 | REGS_NORTH_PIPE_AND_PORT) 972#define INTEL_DDI_PIPE_A_LINK_N (0x0044 | REGS_NORTH_PIPE_AND_PORT) 973#define INTEL_DDI_PIPE_B_LINK_N (0x1044 | REGS_NORTH_PIPE_AND_PORT) 974 975// on PCH we also have to set the transcoder 976#define INTEL_TRANSCODER_A_HTOTAL (0x0000 | REGS_SOUTH_TRANSCODER_PORT) 977#define INTEL_TRANSCODER_A_HBLANK (0x0004 | REGS_SOUTH_TRANSCODER_PORT) 978#define INTEL_TRANSCODER_A_HSYNC (0x0008 | REGS_SOUTH_TRANSCODER_PORT) 979#define INTEL_TRANSCODER_A_VTOTAL (0x000c | REGS_SOUTH_TRANSCODER_PORT) 980#define INTEL_TRANSCODER_A_VBLANK (0x0010 | REGS_SOUTH_TRANSCODER_PORT) 981#define INTEL_TRANSCODER_A_VSYNC (0x0014 | REGS_SOUTH_TRANSCODER_PORT) 982#define INTEL_TRANSCODER_B_HTOTAL (0x1000 | REGS_SOUTH_TRANSCODER_PORT) 983#define INTEL_TRANSCODER_B_HBLANK (0x1004 | REGS_SOUTH_TRANSCODER_PORT) 984#define INTEL_TRANSCODER_B_HSYNC (0x1008 | REGS_SOUTH_TRANSCODER_PORT) 985#define INTEL_TRANSCODER_B_VTOTAL (0x100c | REGS_SOUTH_TRANSCODER_PORT) 986#define INTEL_TRANSCODER_B_VBLANK (0x1010 | REGS_SOUTH_TRANSCODER_PORT) 987#define INTEL_TRANSCODER_B_VSYNC (0x1014 | REGS_SOUTH_TRANSCODER_PORT) 988 989// transcoder M/N DATA AND LINK VALUES (refreshrate) 990#define INTEL_TRANSCODER_A_DATA_M1 (0x0030 | REGS_SOUTH_TRANSCODER_PORT) 991#define INTEL_TRANSCODER_A_DATA_M2 (0x0038 | REGS_SOUTH_TRANSCODER_PORT) 992#define INTEL_TRANSCODER_B_DATA_M1 (0x1030 | REGS_SOUTH_TRANSCODER_PORT) 993#define INTEL_TRANSCODER_B_DATA_M2 (0x1038 | REGS_SOUTH_TRANSCODER_PORT) 994#define INTEL_TRANSCODER_C_DATA_M1 (0x2030 | REGS_SOUTH_TRANSCODER_PORT) 995#define INTEL_TRANSCODER_C_DATA_M2 (0x2038 | REGS_SOUTH_TRANSCODER_PORT) 996#define INTEL_TRANSCODER_A_DATA_N1 (0x0034 | REGS_SOUTH_TRANSCODER_PORT) 997#define INTEL_TRANSCODER_A_DATA_N2 (0x003c | REGS_SOUTH_TRANSCODER_PORT) 998#define INTEL_TRANSCODER_B_DATA_N1 (0x1034 | REGS_SOUTH_TRANSCODER_PORT) 999#define INTEL_TRANSCODER_B_DATA_N2 (0x103c | REGS_SOUTH_TRANSCODER_PORT) 1000#define INTEL_TRANSCODER_C_DATA_N1 (0x2034 | REGS_SOUTH_TRANSCODER_PORT) 1001#define INTEL_TRANSCODER_C_DATA_N2 (0x203c | REGS_SOUTH_TRANSCODER_PORT) 1002#define INTEL_TRANSCODER_A_LINK_M1 (0x0040 | REGS_SOUTH_TRANSCODER_PORT) 1003#define INTEL_TRANSCODER_A_LINK_M2 (0x0048 | REGS_SOUTH_TRANSCODER_PORT) 1004#define INTEL_TRANSCODER_B_LINK_M1 (0x1040 | REGS_SOUTH_TRANSCODER_PORT) 1005#define INTEL_TRANSCODER_B_LINK_M2 (0x1048 | REGS_SOUTH_TRANSCODER_PORT) 1006#define INTEL_TRANSCODER_C_LINK_M1 (0x2040 | REGS_SOUTH_TRANSCODER_PORT) 1007#define INTEL_TRANSCODER_C_LINK_M2 (0x2048 | REGS_SOUTH_TRANSCODER_PORT) 1008#define INTEL_TRANSCODER_A_LINK_N1 (0x0044 | REGS_SOUTH_TRANSCODER_PORT) 1009#define INTEL_TRANSCODER_A_LINK_N2 (0x004c | REGS_SOUTH_TRANSCODER_PORT) 1010#define INTEL_TRANSCODER_B_LINK_N1 (0x1044 | REGS_SOUTH_TRANSCODER_PORT) 1011#define INTEL_TRANSCODER_B_LINK_N2 (0x104c | REGS_SOUTH_TRANSCODER_PORT) 1012#define INTEL_TRANSCODER_C_LINK_N1 (0x2044 | REGS_SOUTH_TRANSCODER_PORT) 1013#define INTEL_TRANSCODER_C_LINK_N2 (0x204c | REGS_SOUTH_TRANSCODER_PORT) 1014#define INTEL_TRANSCODER_MN_TU_SIZE_MASK (0x3f << 25) 1015#define INTEL_TRANSCODER_MN_VALUE_MASK (0xffffff << 0) 1016 1017#define INTEL_TRANSCODER_A_IMAGE_SIZE (0x001c | REGS_SOUTH_TRANSCODER_PORT) 1018#define INTEL_TRANSCODER_B_IMAGE_SIZE (0x101c | REGS_SOUTH_TRANSCODER_PORT) 1019 1020// TODO: Is there consolidation that could happen here with digital ports? 1021 1022#define INTEL_ANALOG_PORT (0x1100 | REGS_SOUTH_TRANSCODER_PORT) 1023#define INTEL_DIGITAL_PORT_A (0x1120 | REGS_SOUTH_TRANSCODER_PORT) 1024#define INTEL_DIGITAL_PORT_B (0x1140 | REGS_SOUTH_TRANSCODER_PORT) 1025#define INTEL_DIGITAL_PORT_C (0x1160 | REGS_SOUTH_TRANSCODER_PORT) 1026#define INTEL_DIGITAL_LVDS_PORT (0x1180 | REGS_SOUTH_TRANSCODER_PORT) 1027 1028#define INTEL_HDMI_PORT_B (0x1140 | REGS_SOUTH_TRANSCODER_PORT) 1029#define INTEL_HDMI_PORT_C (0x1160 | REGS_SOUTH_TRANSCODER_PORT) 1030 1031#define PCH_HDMI_PORT_B (0x1140 | REGS_SOUTH_TRANSCODER_PORT) 1032#define PCH_HDMI_PORT_C (0x1150 | REGS_SOUTH_TRANSCODER_PORT) 1033#define PCH_HDMI_PORT_D (0x1160 | REGS_SOUTH_TRANSCODER_PORT) 1034 1035#define GEN4_HDMI_PORT_B (0x1140 | REGS_SOUTH_TRANSCODER_PORT) 1036#define GEN4_HDMI_PORT_C (0x1160 | REGS_SOUTH_TRANSCODER_PORT) 1037#define CHV_HDMI_PORT_D (0x116C | REGS_SOUTH_TRANSCODER_PORT) 1038 1039// DDI Buffer Control (This replaces DP on Haswell+) 1040#define DDI_BUF_CTL_A (0x4000 | REGS_NORTH_PIPE_AND_PORT) 1041#define DDI_BUF_CTL_B (0x4100 | REGS_NORTH_PIPE_AND_PORT) 1042#define DDI_BUF_CTL_C (0x4200 | REGS_NORTH_PIPE_AND_PORT) 1043#define DDI_BUF_CTL_D (0x4300 | REGS_NORTH_PIPE_AND_PORT) 1044#define DDI_BUF_CTL_E (0x4400 | REGS_NORTH_PIPE_AND_PORT) 1045#define DDI_BUF_CTL_F (0x4500 | REGS_NORTH_PIPE_AND_PORT) 1046#define DDI_BUF_CTL_G (0x4600 | REGS_NORTH_PIPE_AND_PORT) 1047#define DDI_BUF_CTL_ENABLE (1 << 31) 1048#define DDI_BUF_TRANS_SELECT(n) ((n) << 24) 1049#define DDI_BUF_EMP_MASK (0xf << 24) 1050#define DDI_BUF_PORT_REVERSAL (1 << 16) 1051#define DDI_BUF_IS_IDLE (1 << 7) 1052#define DDI_A_4_LANES (1 << 4) 1053#define DDI_PORT_WIDTH(width) (((width) - 1) << 1) 1054#define DDI_INIT_DISPLAY_DETECTED (1 << 0) 1055 1056#define PIPE_DDI_FUNC_CTL_A (0x0400 | REGS_NORTH_PIPE_AND_PORT) 1057#define PIPE_DDI_FUNC_CTL_B (0x1400 | REGS_NORTH_PIPE_AND_PORT) 1058#define PIPE_DDI_FUNC_CTL_C (0x2400 | REGS_NORTH_PIPE_AND_PORT) 1059#define PIPE_DDI_FUNC_CTL_EDP (0xF400 | REGS_NORTH_PIPE_AND_PORT) 1060#define PIPE_DDI_FUNC_CTL_DSI0 (0xB400 | REGS_NORTH_PIPE_AND_PORT) 1061#define PIPE_DDI_FUNC_CTL_DSI1 (0xBC00 | REGS_NORTH_PIPE_AND_PORT) 1062#define PIPE_DDI_FUNC_CTL_ENABLE (1 << 31) 1063#define PIPE_DDI_SELECT_SHIFT 28 1064#define TGL_PIPE_DDI_SELECT_SHIFT 27 1065#define PIPE_DDI_SELECT_PORT(x) ((x) << PIPE_DDI_SELECT_SHIFT) 1066#define TGL_PIPE_DDI_SELECT_PORT(x) ((x) << TGL_PIPE_DDI_SELECT_SHIFT) 1067#define PIPE_DDI_SELECT_MASK (7 << PIPE_DDI_SELECT_SHIFT) 1068#define TGL_PIPE_DDI_SELECT_MASK (7 << TGL_PIPE_DDI_SELECT_SHIFT) 1069#define PIPE_DDI_PORT_NONE 0 1070#define PIPE_DDI_PORT_B 1 1071#define PIPE_DDI_PORT_C 2 1072#define PIPE_DDI_PORT_D 3 1073#define PIPE_DDI_PORT_E 4 1074#define PIPE_DDI_PORT_F 5 1075#define PIPE_DDI_PORT_G 6 1076#define PIPE_DDI_MODESEL_SHIFT 24 1077#define PIPE_DDI_MODESEL_MODE(x) ((x) << PIPE_DDI_MODESEL_SHIFT) 1078#define PIPE_DDI_MODESEL_MASK (7 << PIPE_DDI_MODESEL_SHIFT) 1079#define PIPE_DDI_MODE_HDMI 0 1080#define PIPE_DDI_MODE_DVI 1 1081#define PIPE_DDI_MODE_DP_SST 2 1082#define PIPE_DDI_MODE_DP_MST 3 1083#define PIPE_DDI_COLOR_SHIFT 20 1084#define PIPE_DDI_BPC(x) ((x) << PIPE_DDI_COLOR_SHIFT) 1085#define PIPE_DDI_BPC_MASK (7 << PIPE_DDI_COLOR_SHIFT) 1086#define PIPE_DDI_8BPC 0 1087#define PIPE_DDI_10BPC 1 1088#define PIPE_DDI_6BPC 2 1089#define PIPE_DDI_12BPC 3 1090#define PIPE_DDI_DP_WIDTH_SHIFT 1 1091#define PIPE_DDI_DP_WIDTH_SEL(x) ((x) << PIPE_DDI_DP_WIDTH_SHIFT) 1092#define PIPE_DDI_DP_WIDTH_MASK (7 << PIPE_DDI_DP_WIDTH_SHIFT) 1093#define PIPE_DDI_DP_WIDTH_1 0 1094#define PIPE_DDI_DP_WIDTH_2 1 1095#define PIPE_DDI_DP_WIDTH_4 2 1096 1097// DP_A always @ 6xxxx, DP_B-DP_D move with PCH 1098#define INTEL_DISPLAY_PORT_A (0x4000 | REGS_NORTH_PIPE_AND_PORT) 1099#define INTEL_DISPLAY_PORT_B (0x4100 | REGS_SOUTH_TRANSCODER_PORT) 1100#define INTEL_DISPLAY_PORT_C (0x4200 | REGS_SOUTH_TRANSCODER_PORT) 1101#define INTEL_DISPLAY_PORT_D (0x4300 | REGS_SOUTH_TRANSCODER_PORT) 1102 1103#define INTEL_DISP_PORTA_SNB_PIPE_SHIFT 30 1104#define INTEL_DISP_PORTA_SNB_PIPE_MASK (1 << INTEL_DISP_PORTA_SNB_PIPE_SHIFT) 1105#define INTEL_DISP_PORTA_SNB_PIPE_A 0 1106#define INTEL_DISP_PORTA_SNB_PIPE_B 1 1107#define INTEL_DISP_PORTA_IVB_PIPE_SHIFT 29 1108#define INTEL_DISP_PORTA_IVB_PIPE_MASK (3 << INTEL_DISP_PORTA_IVB_PIPE_SHIFT) 1109#define INTEL_DISP_PORTA_IVB_PIPE_A 0 1110#define INTEL_DISP_PORTA_IVB_PIPE_B 1 1111#define INTEL_DISP_PORTA_IVB_PIPE_C 2 1112 1113#define INTEL_DISP_PORT_WIDTH_SHIFT 19 1114#define INTEL_DISP_PORT_WIDTH_MASK (7 << INTEL_DISP_PORT_WIDTH_SHIFT) 1115#define INTEL_DISP_PORT_WIDTH_1 0 1116#define INTEL_DISP_PORT_WIDTH_2 1 1117#define INTEL_DISP_PORT_WIDTH_4 3 1118#define INTEL_DISP_EDP_PLL_FREQ_SHIFT 16 1119#define INTEL_DISP_EDP_PLL_FREQ_MASK (3 << INTEL_DISP_EDP_PLL_FREQ_SHIFT) 1120#define INTEL_DISP_EDP_PLL_FREQ_270 0 1121#define INTEL_DISP_EDP_PLL_FREQ_162 1 1122 1123#define INTEL_TRANSCODER_A_DP_CTL (0x0300 | REGS_SOUTH_TRANSCODER_PORT) 1124#define INTEL_TRANSCODER_B_DP_CTL (0x1300 | REGS_SOUTH_TRANSCODER_PORT) 1125#define INTEL_TRANSCODER_C_DP_CTL (0x2300 | REGS_SOUTH_TRANSCODER_PORT) 1126 1127#define INTEL_TRANS_DP_COLOR_SHIFT 9 1128#define INTEL_TRANS_DP_BPC(x) ((x) << INTEL_TRANS_DP_COLOR_SHIFT) 1129#define INTEL_TRANS_DP_BPC_MASK (7 << INTEL_TRANS_DP_COLOR_SHIFT) 1130#define INTEL_TRANS_DP_PORT_SHIFT 29 1131#define INTEL_TRANS_DP_PORT(x) ((x) << INTEL_TRANS_DP_PORT_SHIFT) 1132#define INTEL_TRANS_DP_PORT_MASK (3 << INTEL_TRANS_DP_PORT_SHIFT) 1133#define INTEL_TRANS_DP_PORT_B 0 1134#define INTEL_TRANS_DP_PORT_C 1 1135#define INTEL_TRANS_DP_PORT_D 2 1136#define INTEL_TRANS_DP_PORT_NONE 3 1137 1138// Unless you're a damn Valley/CherryView unicorn :-( 1139#define VLV_DISPLAY_PORT_B (VLV_DISPLAY_BASE + 0x64100) 1140#define VLV_DISPLAY_PORT_C (VLV_DISPLAY_BASE + 0x64200) 1141#define CHV_DISPLAY_PORT_D (VLV_DISPLAY_BASE + 0x64300) 1142 1143// DP AUX channels 1144#define _DPA_AUX_CH_CTL (0x4010 | REGS_NORTH_PIPE_AND_PORT) 1145#define _DPA_AUX_CH_DATA1 (0x4014 | REGS_NORTH_PIPE_AND_PORT) 1146#define _DPB_AUX_CH_CTL (0x4110 | REGS_NORTH_PIPE_AND_PORT) 1147#define _DPB_AUX_CH_DATA1 (0x4114 | REGS_NORTH_PIPE_AND_PORT) 1148#define DP_AUX_CH_CTL(aux) \ 1149 (_DPA_AUX_CH_CTL + (_DPB_AUX_CH_CTL - _DPA_AUX_CH_CTL) * aux) 1150#define DP_AUX_CH_DATA(aux, i) \ 1151 (_DPA_AUX_CH_DATA1 + (_DPB_AUX_CH_DATA1 - _DPA_AUX_CH_DATA1) * aux + i * 4) 1152#define _PCH_DPB_AUX_CH_CTL (0x4110 | REGS_SOUTH_TRANSCODER_PORT) 1153#define _PCH_DPB_AUX_CH_DATA1 (0x4114 | REGS_SOUTH_TRANSCODER_PORT) 1154#define _PCH_DPC_AUX_CH_CTL (0x4210 | REGS_SOUTH_TRANSCODER_PORT) 1155#define _PCH_DPC_AUX_CH_DATA1 (0x4214 | REGS_SOUTH_TRANSCODER_PORT) 1156#define PCH_DP_AUX_CH_CTL(aux) \ 1157 (_PCH_DPB_AUX_CH_CTL + (_PCH_DPC_AUX_CH_CTL - _PCH_DPB_AUX_CH_CTL) * (aux - AUX_CH_B)) 1158#define PCH_DP_AUX_CH_DATA(aux, i) \ 1159 (_PCH_DPB_AUX_CH_DATA1 + (_PCH_DPC_AUX_CH_DATA1 - _PCH_DPB_AUX_CH_DATA1) * (aux - AUX_CH_B) \ 1160 + i * 4) 1161 1162#define INTEL_DP_AUX_CTL_BUSY (1 << 31) 1163#define INTEL_DP_AUX_CTL_DONE (1 << 30) 1164#define INTEL_DP_AUX_CTL_INTERRUPT (1 << 29) 1165#define INTEL_DP_AUX_CTL_TIMEOUT_ERROR (1 << 28) 1166#define INTEL_DP_AUX_CTL_TIMEOUT_400us (0 << 26) 1167#define INTEL_DP_AUX_CTL_TIMEOUT_600us (1 << 26) 1168#define INTEL_DP_AUX_CTL_TIMEOUT_800us (2 << 26) 1169#define INTEL_DP_AUX_CTL_TIMEOUT_1600us (3 << 26) 1170#define INTEL_DP_AUX_CTL_TIMEOUT_MASK (3 << 26) 1171#define INTEL_DP_AUX_CTL_RECEIVE_ERROR (1 << 25) 1172#define INTEL_DP_AUX_CTL_MSG_SIZE_MASK (0x1f << 20) 1173#define INTEL_DP_AUX_CTL_MSG_SIZE_SHIFT 20 1174#define INTEL_DP_AUX_CTL_PRECHARGE_2US_MASK (0xf << 16) 1175#define INTEL_DP_AUX_CTL_PRECHARGE_2US_SHIFT 16 1176#define INTEL_DP_AUX_CTL_BIT_CLOCK_2X_MASK (0x7ff) 1177#define INTEL_DP_AUX_CTL_BIT_CLOCK_2X_SHIFT 0 1178#define INTEL_DP_AUX_CTL_FW_SYNC_PULSE_SKL(c) (((c) - 1) << 5) 1179#define INTEL_DP_AUX_CTL_SYNC_PULSE_SKL(c) ((c) - 1) 1180 1181// planes 1182#define INTEL_PIPE_ENABLED (1UL << 31) 1183#define INTEL_PIPE_STATE (1UL << 30) 1184 1185#define INTEL_PLANE_OFFSET 0x1000 1186 1187#define INTEL_DISPLAY_A_PIPE_CONTROL (0x0008 | REGS_NORTH_PLANE_CONTROL) 1188#define INTEL_DISPLAY_B_PIPE_CONTROL (0x1008 | REGS_NORTH_PLANE_CONTROL) 1189#define INTEL_DISPLAY_C_PIPE_CONTROL (0x2008 | REGS_NORTH_PLANE_CONTROL) 1190#define INTEL_DISPLAY_A_PIPE_STATUS (0x0024 | REGS_NORTH_PLANE_CONTROL) 1191#define INTEL_DISPLAY_B_PIPE_STATUS (0x1024 | REGS_NORTH_PLANE_CONTROL) 1192 1193#define INTEL_DISPLAY_A_PIPE_WATERMARK (0x5100 | REGS_NORTH_PLANE_CONTROL) 1194#define INTEL_DISPLAY_B_PIPE_WATERMARK (0x5104 | REGS_NORTH_PLANE_CONTROL) 1195#define INTEL_DISPLAY_C_PIPE_WATERMARK (0x5200 | REGS_NORTH_PLANE_CONTROL) 1196 1197#define DISPLAY_PIPE_VBLANK_ENABLED (1UL << 17) 1198#define DISPLAY_PIPE_VBLANK_STATUS (1UL << 1) 1199 1200#define INTEL_DISPLAY_A_CONTROL (0x0180 | REGS_NORTH_PLANE_CONTROL) 1201#define INTEL_DISPLAY_A_BASE (0x0184 | REGS_NORTH_PLANE_CONTROL) 1202#define INTEL_DISPLAY_A_BYTES_PER_ROW (0x0188 | REGS_NORTH_PLANE_CONTROL) 1203#define INTEL_DISPLAY_A_POS (0x018c | REGS_NORTH_PLANE_CONTROL) 1204 // reserved on A 1205#define INTEL_DISPLAY_A_IMAGE_SIZE (0x0190 | REGS_NORTH_PLANE_CONTROL) 1206#define INTEL_DISPLAY_A_SURFACE (0x019c | REGS_NORTH_PLANE_CONTROL) 1207#define INTEL_DISPLAY_A_OFFSET_HAS (0x01a4 | REGS_NORTH_PLANE_CONTROL) 1208 // i965 and up only 1209 1210#define INTEL_DISPLAY_B_CONTROL (0x1180 | REGS_NORTH_PLANE_CONTROL) 1211#define INTEL_DISPLAY_B_BASE (0x1184 | REGS_NORTH_PLANE_CONTROL) 1212#define INTEL_DISPLAY_B_BYTES_PER_ROW (0x1188 | REGS_NORTH_PLANE_CONTROL) 1213#define INTEL_DISPLAY_B_POS (0x118c | REGS_NORTH_PLANE_CONTROL) 1214#define INTEL_DISPLAY_B_IMAGE_SIZE (0x1190 | REGS_NORTH_PLANE_CONTROL) 1215#define INTEL_DISPLAY_B_SURFACE (0x119c | REGS_NORTH_PLANE_CONTROL) 1216#define INTEL_DISPLAY_B_OFFSET_HAS (0x11a4 | REGS_NORTH_PLANE_CONTROL) 1217 // i965 and up only 1218 1219// INTEL_DISPLAY_A_CONTROL source pixel format 1220#define DISPLAY_CONTROL_ENABLED (1UL << 31) 1221#define DISPLAY_CONTROL_GAMMA (1UL << 30) 1222#define DISPLAY_CONTROL_COLOR_MASK (0x0fUL << 26) 1223#define DISPLAY_CONTROL_CMAP8 (2UL << 26) 1224#define DISPLAY_CONTROL_RGB15 (4UL << 26) 1225#define DISPLAY_CONTROL_RGB16 (5UL << 26) 1226#define DISPLAY_CONTROL_RGB32 (6UL << 26) 1227#define DISPLAY_CONTROL_RGB64 (0x0cUL << 26) 1228// Skylake 1229#define DISPLAY_CONTROL_COLOR_MASK_SKY (0x0fUL << 24) 1230#define DISPLAY_CONTROL_CMAP8_SKY (0x0cUL << 24) 1231#define DISPLAY_CONTROL_RGB15_SKY (0x0eUL << 24) 1232#define DISPLAY_CONTROL_RGB16_SKY (0x0eUL << 24) 1233#define DISPLAY_CONTROL_RGB32_SKY (0x04UL << 24) 1234#define DISPLAY_CONTROL_RGB64_SKY (0x06UL << 24) 1235 1236// INTEL_DISPLAY_A_PIPE_CONTROL ILK+ 1237#define INTEL_PIPE_DITHER_TYPE_MASK (0x0000000c) 1238#define INTEL_PIPE_DITHER_TYPE_SP (0 << 2) 1239#define INTEL_PIPE_DITHER_TYPE_ST1 (1 << 2) 1240#define INTEL_PIPE_DITHER_TYPE_ST2 (2 << 2) 1241#define INTEL_PIPE_DITHER_TYPE_TEMP (3 << 2) 1242#define INTEL_PIPE_DITHER_EN (1 << 4) 1243#define INTEL_PIPE_COLOR_SHIFT 5 1244#define INTEL_PIPE_BPC(x) ((x) << INTEL_PIPE_COLOR_SHIFT) 1245#define INTEL_PIPE_BPC_MASK (7 << INTEL_PIPE_COLOR_SHIFT) 1246#define INTEL_PIPE_8BPC 0 1247#define INTEL_PIPE_10BPC 1 1248#define INTEL_PIPE_6BPC 2 1249#define INTEL_PIPE_12BPC 3 1250#define INTEL_PIPE_PROGRESSIVE (0 << 21) 1251 1252// cursors 1253#define INTEL_CURSOR_CONTROL (0x0080 | REGS_NORTH_PLANE_CONTROL) 1254#define INTEL_CURSOR_BASE (0x0084 | REGS_NORTH_PLANE_CONTROL) 1255#define INTEL_CURSOR_POSITION (0x0088 | REGS_NORTH_PLANE_CONTROL) 1256#define INTEL_CURSOR_PALETTE (0x0090 | REGS_NORTH_PLANE_CONTROL) 1257 // (- 0x009f) 1258#define INTEL_CURSOR_SIZE (0x00a0 | REGS_NORTH_PLANE_CONTROL) 1259#define CURSOR_ENABLED (1UL << 31) 1260#define CURSOR_FORMAT_2_COLORS (0UL << 24) 1261#define CURSOR_FORMAT_3_COLORS (1UL << 24) 1262#define CURSOR_FORMAT_4_COLORS (2UL << 24) 1263#define CURSOR_FORMAT_ARGB (4UL << 24) 1264#define CURSOR_FORMAT_XRGB (5UL << 24) 1265#define CURSOR_POSITION_NEGATIVE 0x8000 1266#define CURSOR_POSITION_MASK 0x3fff 1267 1268// palette registers 1269#define INTEL_DISPLAY_A_PALETTE (0xa000 | REGS_NORTH_SHARED) 1270#define INTEL_DISPLAY_B_PALETTE (0xa800 | REGS_NORTH_SHARED) 1271 1272// Ironlake PCH reference clk control 1273#define PCH_DREF_CONTROL (0x6200 | REGS_SOUTH_SHARED) 1274#define DREF_CONTROL_MASK 0x7fc3 1275#define DREF_CPU_SOURCE_OUTPUT_DISABLE (0 << 13) 1276#define DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD (2 << 13) 1277#define DREF_CPU_SOURCE_OUTPUT_NONSPREAD (3 << 13) 1278#define DREF_CPU_SOURCE_OUTPUT_MASK (3 << 13) 1279#define DREF_SSC_SOURCE_DISABLE (0 << 11) 1280#define DREF_SSC_SOURCE_ENABLE (2 << 11) 1281#define DREF_SSC_SOURCE_MASK (3 << 11) 1282#define DREF_NONSPREAD_SOURCE_DISABLE (0 << 9) 1283#define DREF_NONSPREAD_CK505_ENABLE (1 << 9) 1284#define DREF_NONSPREAD_SOURCE_ENABLE (2 << 9) 1285#define DREF_NONSPREAD_SOURCE_MASK (3 << 9) 1286#define DREF_SUPERSPREAD_SOURCE_DISABLE (0 << 7) 1287#define DREF_SUPERSPREAD_SOURCE_ENABLE (2 << 7) 1288#define DREF_SUPERSPREAD_SOURCE_MASK (3 << 7) 1289#define DREF_SSC4_DOWNSPREAD (0 << 6) 1290#define DREF_SSC4_CENTERSPREAD (1 << 6) 1291#define DREF_SSC1_DISABLE (0 << 1) 1292#define DREF_SSC1_ENABLE (1 << 1) 1293#define DREF_SSC4_DISABLE (0 << 0) 1294#define DREF_SSC4_ENABLE (1 << 0) 1295 1296#define PCH_RAWCLK_FREQ (0x6204 | REGS_SOUTH_SHARED) 1297#define RAWCLK_FREQ_MASK 0x3ff 1298 1299// PLL registers 1300// Multiplier Divisor 1301#define INTEL_DISPLAY_A_PLL (0x6014 | REGS_SOUTH_SHARED) 1302#define INTEL_DISPLAY_B_PLL (0x6018 | REGS_SOUTH_SHARED) 1303#define INTEL_DISPLAY_A_PLL_MD (0x601C | REGS_SOUTH_SHARED) 1304#define INTEL_DISPLAY_B_PLL_MD (0x6020 | REGS_SOUTH_SHARED) 1305#define CHV_DISPLAY_C_PLL (0x6030 | REGS_SOUTH_SHARED) 1306#define CHV_DISPLAY_B_PLL_MD (0x603C | REGS_SOUTH_SHARED) 1307 1308#define INTEL_DISPLAY_A_PLL_DIVISOR_0 (0x6040 | REGS_SOUTH_SHARED) 1309#define INTEL_DISPLAY_A_PLL_DIVISOR_1 (0x6044 | REGS_SOUTH_SHARED) 1310#define INTEL_DISPLAY_B_PLL_DIVISOR_0 (0x6048 | REGS_SOUTH_SHARED) 1311#define INTEL_DISPLAY_B_PLL_DIVISOR_1 (0x604c | REGS_SOUTH_SHARED) 1312 1313#define SNB_DPLL_SEL (0x7000 | REGS_SOUTH_SHARED) 1314 1315// i2c bit banging interface 1316#define INTEL_I2C_IO_A (0x5010 | REGS_SOUTH_SHARED) 1317#define INTEL_I2C_IO_B (0x5014 | REGS_SOUTH_SHARED) 1318#define INTEL_I2C_IO_C (0x5018 | REGS_SOUTH_SHARED) 1319#define INTEL_I2C_IO_D (0x501c | REGS_SOUTH_SHARED) 1320#define INTEL_I2C_IO_E (0x5020 | REGS_SOUTH_SHARED) 1321#define INTEL_I2C_IO_F (0x5024 | REGS_SOUTH_SHARED) 1322#define INTEL_I2C_IO_G (0x5028 | REGS_SOUTH_SHARED) 1323#define INTEL_I2C_IO_H (0x502c | REGS_SOUTH_SHARED) 1324#define INTEL_I2C_IO_I (0x5030 | REGS_SOUTH_SHARED) 1325#define INTEL_I2C_IO_J (0x5034 | REGS_SOUTH_SHARED) 1326#define INTEL_I2C_IO_K (0x5038 | REGS_SOUTH_SHARED) 1327#define INTEL_I2C_IO_L (0x503c | REGS_SOUTH_SHARED) 1328#define INTEL_I2C_IO_M (0x5040 | REGS_SOUTH_SHARED) 1329#define INTEL_I2C_IO_N (0x5044 | REGS_SOUTH_SHARED) 1330// i2c hardware controller 1331#define INTEL_GMBUS0 (0x5100 | REGS_SOUTH_SHARED) 1332#define INTEL_GMBUS4 (0x5110 | REGS_SOUTH_SHARED) 1333 1334#define I2C_CLOCK_DIRECTION_MASK (1 << 0) 1335#define I2C_CLOCK_DIRECTION_OUT (1 << 1) 1336#define I2C_CLOCK_VALUE_MASK (1 << 2) 1337#define I2C_CLOCK_VALUE_OUT (1 << 3) 1338#define I2C_CLOCK_VALUE_IN (1 << 4) 1339#define I2C_DATA_DIRECTION_MASK (1 << 8) 1340#define I2C_DATA_DIRECTION_OUT (1 << 9) 1341#define I2C_DATA_VALUE_MASK (1 << 10) 1342#define I2C_DATA_VALUE_OUT (1 << 11) 1343#define I2C_DATA_VALUE_IN (1 << 12) 1344#define I2C_RESERVED ((1 << 13) | (1 << 5)) 1345 1346// gpu block clock gating disable bits 1347#define INTEL_DSPCLK_GATE_D (0x2020 | REGS_SOUTH_SHARED) 1348#define PCH_GMBUSUNIT_CLK_GATE_DIS (1UL << 31) 1349#define INTEL_GEN9_CLKGATE_DIS_4 (0x653c | REGS_NORTH_SHARED) 1350#define BXT_GMBUSUNIT_CLK_GATE_DIS (1 << 14) 1351 1352// gpu power wells (confirmed skylake) 1353#define INTEL_PWR_WELL_CTL_1_BIOS (0x5400 | REGS_NORTH_SHARED) 1354#define INTEL_PWR_WELL_CTL_2_DRIVER (0x5404 | REGS_NORTH_SHARED) 1355 1356#define HSW_PWR_WELL_CTL_REQ(i) (0x2 << ((2 * i))) 1357#define HSW_PWR_WELL_CTL_STATE(i) (0x1 << ((2 * i))) 1358 1359#define HSW_PWR_WELL_CTL1 INTEL_PWR_WELL_CTL_1_BIOS 1360#define HSW_PWR_WELL_CTL2 INTEL_PWR_WELL_CTL_2_DRIVER 1361#define HSW_PWR_WELL_CTL3 (0x5408 | REGS_NORTH_SHARED) 1362#define HSW_PWR_WELL_CTL4 (0x540c | REGS_NORTH_SHARED) 1363 1364#define ICL_PWR_WELL_CTL_AUX1 (0x5440 | REGS_NORTH_SHARED) 1365#define ICL_PWR_WELL_CTL_AUX2 (0x5444 | REGS_NORTH_SHARED) 1366#define ICL_PWR_WELL_CTL_AUX4 (0x544c | REGS_NORTH_SHARED) 1367 1368#define ICL_PWR_WELL_CTL_DDI1 (0x5450 | REGS_NORTH_SHARED) 1369#define ICL_PWR_WELL_CTL_DDI2 (0x5454 | REGS_NORTH_SHARED) 1370#define ICL_PWR_WELL_CTL_DDI4 (0x545c | REGS_NORTH_SHARED) 1371 1372// gpu pll enable registers (confirmed skylake) 1373#define INTEL_WRPLL_CTL_1_DPLL2 (0x6040 | REGS_NORTH_SHARED) 1374#define INTEL_WRPLL_CTL_2_DPLL3 (0x6060 | REGS_NORTH_SHARED) 1375#define WRPLL_PLL_ENABLE (1 << 31) 1376 1377// TODO: on IronLake this is in the north shared block at 0x41000 1378#define INTEL_VGA_DISPLAY_CONTROL (0x1400 | REGS_NORTH_PLANE_CONTROL) 1379#define VGA_DISPLAY_DISABLED (1UL << 31) 1380 1381// LVDS panel 1382#define INTEL_PANEL_STATUS (0x1200 | REGS_NORTH_PIPE_AND_PORT) 1383#define INTEL_PANEL_CONTROL (0x1204 | REGS_NORTH_PIPE_AND_PORT) 1384#define INTEL_PANEL_FIT_CONTROL (0x1230 | REGS_NORTH_PIPE_AND_PORT) 1385#define INTEL_PANEL_FIT_RATIOS (0x1234 | REGS_NORTH_PIPE_AND_PORT) 1386 1387// LVDS on IronLake and up 1388#define PCH_PANEL_STATUS (0x7200 | REGS_SOUTH_SHARED) 1389#define PCH_PANEL_CONTROL (0x7204 | REGS_SOUTH_SHARED) 1390#define PCH_PANEL_ON_DELAYS (0x7208 | REGS_SOUTH_SHARED) 1391#define PCH_PANEL_OFF_DELAYS (0x720c | REGS_SOUTH_SHARED) 1392#define PCH_PANEL_DIVISOR (0x7210 | REGS_SOUTH_SHARED) 1393#define PCH_LVDS_DETECTED (1 << 1) 1394 1395#define PANEL_STATUS_POWER_ON (1UL << 31) 1396#define PANEL_CONTROL_POWER_TARGET_OFF (0UL << 0) 1397#define PANEL_CONTROL_POWER_TARGET_ON (1UL << 0) 1398#define PANEL_CONTROL_POWER_TARGET_RST (1UL << 1) 1399#define PANEL_REGISTER_UNLOCK (0xabcd << 16) 1400 1401// PCH_PANEL_ON_DELAYS 1402#define PANEL_DELAY_PORT_SELECT_MASK (3 << 30) 1403#define PANEL_DELAY_PORT_SELECT_LVDS (0 << 30) 1404#define PANEL_DELAY_PORT_SELECT_DPA (1 << 30) 1405#define PANEL_DELAY_PORT_SELECT_DPC (2 << 30) 1406#define PANEL_DELAY_PORT_SELECT_DPD (3 << 30) 1407 1408// PCH_PANEL_DIVISOR 1409#define PANEL_DIVISOR_REFERENCE_DIV_MASK 0xffffff00 1410#define PANEL_DIVISOR_REFERENCE_DIV_SHIFT 8 1411#define PANEL_DIVISOR_POW_CYCLE_DLY_MASK 0x1f 1412#define PANEL_DIVISOR_POW_CYCLE_DLY_SHIFT 0x1f 1413 1414// Backlight control registers 1415// These have moved around, initially they were per pipe, then they were moved in the "north" part 1416// of the PCH with a single backlight control (independant of pipes), and then moved again to the 1417// "south" part of the PCH, with a simplified register layout. 1418#define PCH_BLC_PWM_CTL2 (0x8250 | REGS_NORTH_SHARED) // Linux BLC_PWM_CPU_CTL2 1419#define PCH_BLC_PWM_CTL (0x8254 | REGS_NORTH_SHARED) // Linux BLC_PWM_CPU_CTL 1420 1421// Kaby Lake/Sunrisepoint 1422#define BLC_PWM_PCH_CTL1 (0x8250 | REGS_SOUTH_SHARED) // Enable with bit 31 1423#define BLC_PWM_PCH_CTL2 (0x8254 | REGS_SOUTH_SHARED) // Duty Cycle and Period 1424 1425// Devices after Cannonlake have a new register layout, with separate registers for the period 1426// and duty cycle instead of having two 16bit values in a 32bit register 1427#define PCH_SOUTH_BLC_PWM_CONTROL (0x8250 | REGS_SOUTH_SHARED) // Linux _BXT_BLC_PWM_CTL1 1428#define PCH_SOUTH_BLC_PWM_PERIOD (0x8254 | REGS_SOUTH_SHARED) // Linux _BXT_BLC_PWM_FREQ1 1429#define PCH_SOUTH_BLC_PWM_DUTY_CYCLE (0x8258 | REGS_SOUTH_SHARED) // Linux _BXT_BLC_PWM_DUTY1 1430 1431#define MCH_BLC_PWM_CTL (0x1254 | REGS_NORTH_PIPE_AND_PORT) 1432 // Linux VLV_BLC_PWM_CTL (one register per pipe) or BLC_PWM_CTL (a single register that can be 1433 // programmed for use on either pipe) 1434#define BLM_LEGACY_MODE (1 << 16) 1435 1436// ring buffer commands 1437 1438#define COMMAND_NOOP 0x00 1439#define COMMAND_WAIT_FOR_EVENT (0x03 << 23) 1440#define COMMAND_WAIT_FOR_OVERLAY_FLIP (1 << 16) 1441 1442#define COMMAND_FLUSH (0x04 << 23) 1443 1444// overlay flip 1445#define COMMAND_OVERLAY_FLIP (0x11 << 23) 1446#define COMMAND_OVERLAY_CONTINUE (0 << 21) 1447#define COMMAND_OVERLAY_ON (1 << 21) 1448#define COMMAND_OVERLAY_OFF (2 << 21) 1449#define OVERLAY_UPDATE_COEFFICIENTS 0x1 1450 1451// 2D acceleration 1452#define XY_COMMAND_SOURCE_BLIT 0x54c00006 1453#define XY_COMMAND_COLOR_BLIT 0x54000004 1454#define XY_COMMAND_SETUP_MONO_PATTERN 0x44400007 1455#define XY_COMMAND_SCANLINE_BLIT 0x49400001 1456#define COMMAND_COLOR_BLIT 0x50000003 1457#define COMMAND_BLIT_RGBA 0x00300000 1458 1459#define COMMAND_MODE_SOLID_PATTERN 0x80 1460#define COMMAND_MODE_CMAP8 0x00 1461#define COMMAND_MODE_RGB15 0x02 1462#define COMMAND_MODE_RGB16 0x01 1463#define COMMAND_MODE_RGB32 0x03 1464 1465// overlay 1466#define INTEL_OVERLAY_UPDATE 0x30000 1467#define INTEL_OVERLAY_TEST 0x30004 1468#define INTEL_OVERLAY_STATUS 0x30008 1469#define INTEL_OVERLAY_EXTENDED_STATUS 0x3000c 1470#define INTEL_OVERLAY_GAMMA_5 0x30010 1471#define INTEL_OVERLAY_GAMMA_4 0x30014 1472#define INTEL_OVERLAY_GAMMA_3 0x30018 1473#define INTEL_OVERLAY_GAMMA_2 0x3001c 1474#define INTEL_OVERLAY_GAMMA_1 0x30020 1475#define INTEL_OVERLAY_GAMMA_0 0x30024 1476 1477// FDI - Flexible Display Interface, the interface between the (CPU-internal) 1478// GPU and the PCH display outputs. Proprietary interface, based on DisplayPort 1479// though, so similar link training and all... 1480// There's an FDI transmitter (TX) on the CPU and an FDI receiver (RX) on the 1481// PCH for each display pipe. 1482// FDI receiver A is hooked up to transcoder A, FDI receiver B is hooked up to 1483// transcoder B, so we have the same mapping as with the display pipes. 1484#define _FDI_RXA_CTL 0xf000c 1485#define _FDI_RXB_CTL 0xf100c 1486#define FDI_RX_CTL(pipe) (_FDI_RXA_CTL + (_FDI_RXB_CTL - _FDI_RXA_CTL) * (pipe - INTEL_PIPE_A)) 1487#define _FDI_RXA_MISC 0xf0010 1488#define _FDI_RXB_MISC 0xf1010 1489#define FDI_RX_MISC(pipe) (_FDI_RXA_MISC + (_FDI_RXB_MISC - _FDI_RXA_MISC) * (pipe - INTEL_PIPE_A)) 1490#define _FDI_RXA_IIR 0xf0014 1491#define _FDI_RXB_IIR 0xf1014 1492#define FDI_RX_IIR(pipe) (_FDI_RXA_IIR + (_FDI_RXB_IIR - _FDI_RXA_IIR) * (pipe - INTEL_PIPE_A)) 1493#define _FDI_RXA_IMR 0xf0018 1494#define _FDI_RXB_IMR 0xf1018 1495#define FDI_RX_IMR(pipe) (_FDI_RXA_IMR + (_FDI_RXB_IMR - _FDI_RXA_IMR) * (pipe - INTEL_PIPE_A)) 1496 1497#define FDI_RX_ENABLE (1 << 31) 1498#define FDI_RX_PLL_ENABLED (1 << 13) 1499 1500#define FDI_RX_LINK_COLOR_SHIFT 16 1501#define FDI_RX_LINK_BPC(x) ((x) << FDI_RX_LINK_COLOR_SHIFT) 1502#define FDI_RX_LINK_BPC_MASK (7 << FDI_RX_LINK_COLOR_SHIFT) 1503 1504// Transcoder - same base as FDI_RX 1505#define PCH_TRANS_CONF_A 0x0008 1506#define PCH_TRANS_CONF_B 0x1008 1507#define PCH_TRANS_CONF_C 0x2008 1508 1509// Transcoder - skylake DDI 1510#define DDI_SKL_TRANS_CONF_A (0x0008 | REGS_NORTH_PLANE_CONTROL) 1511#define DDI_SKL_TRANS_CONF_B (0x1008 | REGS_NORTH_PLANE_CONTROL) 1512#define DDI_SKL_TRANS_CONF_C (0x2008 | REGS_NORTH_PLANE_CONTROL) 1513#define DDI_SKL_TRANS_CONF_EDP (0xf008 | REGS_NORTH_PLANE_CONTROL) 1514 1515#define TRANS_ENABLE (1 << 31) 1516#define TRANS_ENABLED (1 << 30) 1517 1518// FDI_tX interrupt register 1519#define FDI_RX_INTER_LANE_ALIGN (1 << 10) 1520#define FDI_RX_SYMBOL_LOCK (1 << 9) 1521#define FDI_RX_BIT_LOCK (1 << 8) 1522#define FDI_RX_TRAIN_PATTERN_2_FAIL (1 << 7) 1523#define FDI_RX_FS_CODE_ERR (1 << 6) 1524#define FDI_RX_FE_CODE_ERR (1 << 5) 1525#define FDI_RX_SYMBOL_ERR_RATE_ABOVE (1 << 4) 1526#define FDI_RX_HDCP_LINK_FAIL (1 << 3) 1527#define FDI_RX_PIXEL_FIFO_OVERFLOW (1 << 2) 1528#define FDI_RX_CROSS_CLOCK_OVERFLOW (1 << 1) 1529#define FDI_RX_SYMBOL_QUEUE_OVERFLOW (1 << 0) 1530 1531#define FDI_FS_ERRC_ENABLE (1 << 27) 1532#define FDI_FE_ERRC_ENABLE (1 << 26) 1533 1534#define _FDI_RXA_TUSIZE1 0xf0030 1535#define _FDI_RXA_TUSIZE2 0xf0038 1536#define _FDI_RXB_TUSIZE1 0xf1030 1537#define _FDI_RXB_TUSIZE2 0xf1038 1538#define FDI_RX_TUSIZE1(pipe) (_FDI_RXA_TUSIZE1 + (_FDI_RXB_TUSIZE1 - _FDI_RXA_TUSIZE1) * (pipe - INTEL_PIPE_A)) 1539#define FDI_RX_TUSIZE2(pipe) (_FDI_RXA_TUSIZE2 + (_FDI_RXB_TUSIZE2 - _FDI_RXA_TUSIZE2) * (pipe - INTEL_PIPE_A)) 1540#define FDI_RX_TRANS_UNIT_SIZE(x) ((x - 1) << 25) 1541#define FDI_RX_TRANS_UNIT_MASK 0x7e000000 1542 1543#define FDI_RX_ENHANCE_FRAME_ENABLE (1 << 6) 1544#define FDI_RX_CLOCK_MASK (1 << 4) 1545#define FDI_RX_CLOCK_RAW (0 << 4) 1546#define FDI_RX_CLOCK_PCD (1 << 4) 1547 1548// FDI RX MISC 1549#define FDI_RX_PWRDN_LANE1_MASK (3 << 26) 1550#define FDI_RX_PWRDN_LANE1_VAL(x) ((x) << 26) 1551#define FDI_RX_PWRDN_LANE0_MASK (3 << 24) 1552#define FDI_RX_PWRDN_LANE0_VAL(x) ((x) << 24) 1553#define FDI_RX_TP1_TO_TP2_48 (2 << 20) 1554#define FDI_RX_TP1_TO_TP2_64 (3 << 20) 1555#define FDI_RX_FDI_DELAY_90 (0x90 << 0) 1556 1557#define _FDI_TXA_CTL (0x0100 | REGS_NORTH_PIPE_AND_PORT) 1558#define _FDI_TXB_CTL (0x1100 | REGS_NORTH_PIPE_AND_PORT) 1559#define FDI_TX_CTL(pipe) (_FDI_TXA_CTL + (_FDI_TXB_CTL - _FDI_TXA_CTL) * (pipe - INTEL_PIPE_A)) 1560#define FDI_TX_ENABLE (1 << 31) 1561#define FDI_LINK_TRAIN_PATTERN_1 (0 << 28) 1562#define FDI_LINK_TRAIN_PATTERN_2 (1 << 28) 1563#define FDI_LINK_TRAIN_PATTERN_IDLE (2 << 28) 1564#define FDI_LINK_TRAIN_NONE (3 << 28) 1565#define FDI_LINK_TRAIN_VOLTAGE_0_4V (0 << 25) 1566#define FDI_LINK_TRAIN_VOLTAGE_0_6V (1 << 25) 1567#define FDI_LINK_TRAIN_VOLTAGE_0_8V (2 << 25) 1568#define FDI_LINK_TRAIN_VOLTAGE_1_2V (3 << 25) 1569#define FDI_LINK_TRAIN_PRE_EMPHASIS_NONE (0 << 22) 1570#define FDI_LINK_TRAIN_PRE_EMPHASIS_1_5X (1 << 22) 1571#define FDI_LINK_TRAIN_PRE_EMPHASIS_2X (2 << 22) 1572#define FDI_LINK_TRAIN_PRE_EMPHASIS_3X (3 << 22) 1573 1574// FDI/PIPE M/N DATA AND LINK VALUES (refreshrate) 1575#define PCH_FDI_PIPE_A_DATA_M1 (0x0030 | REGS_NORTH_PIPE_AND_PORT) 1576#define PCH_FDI_PIPE_A_DATA_M2 (0x0038 | REGS_NORTH_PIPE_AND_PORT) 1577#define PCH_FDI_PIPE_B_DATA_M1 (0x1030 | REGS_NORTH_PIPE_AND_PORT) 1578#define PCH_FDI_PIPE_B_DATA_M2 (0x1038 | REGS_NORTH_PIPE_AND_PORT) 1579#define PCH_FDI_PIPE_C_DATA_M1 (0x2030 | REGS_NORTH_PIPE_AND_PORT) 1580#define PCH_FDI_PIPE_C_DATA_M2 (0x2038 | REGS_NORTH_PIPE_AND_PORT) 1581#define PCH_FDI_PIPE_A_DATA_N1 (0x0034 | REGS_NORTH_PIPE_AND_PORT) 1582#define PCH_FDI_PIPE_A_DATA_N2 (0x003c | REGS_NORTH_PIPE_AND_PORT) 1583#define PCH_FDI_PIPE_B_DATA_N1 (0x1034 | REGS_NORTH_PIPE_AND_PORT) 1584#define PCH_FDI_PIPE_B_DATA_N2 (0x103c | REGS_NORTH_PIPE_AND_PORT) 1585#define PCH_FDI_PIPE_C_DATA_N1 (0x2034 | REGS_NORTH_PIPE_AND_PORT) 1586#define PCH_FDI_PIPE_C_DATA_N2 (0x203c | REGS_NORTH_PIPE_AND_PORT) 1587#define PCH_FDI_PIPE_A_LINK_M1 (0x0040 | REGS_NORTH_PIPE_AND_PORT) 1588#define PCH_FDI_PIPE_A_LINK_M2 (0x0048 | REGS_NORTH_PIPE_AND_PORT) 1589#define PCH_FDI_PIPE_B_LINK_M1 (0x1040 | REGS_NORTH_PIPE_AND_PORT) 1590#define PCH_FDI_PIPE_B_LINK_M2 (0x1048 | REGS_NORTH_PIPE_AND_PORT) 1591#define PCH_FDI_PIPE_C_LINK_M1 (0x2040 | REGS_NORTH_PIPE_AND_PORT) 1592#define PCH_FDI_PIPE_C_LINK_M2 (0x2048 | REGS_NORTH_PIPE_AND_PORT) 1593#define PCH_FDI_PIPE_A_LINK_N1 (0x0044 | REGS_NORTH_PIPE_AND_PORT) 1594#define PCH_FDI_PIPE_A_LINK_N2 (0x004c | REGS_NORTH_PIPE_AND_PORT) 1595#define PCH_FDI_PIPE_B_LINK_N1 (0x1044 | REGS_NORTH_PIPE_AND_PORT) 1596#define PCH_FDI_PIPE_B_LINK_N2 (0x104c | REGS_NORTH_PIPE_AND_PORT) 1597#define PCH_FDI_PIPE_C_LINK_N1 (0x2044 | REGS_NORTH_PIPE_AND_PORT) 1598#define PCH_FDI_PIPE_C_LINK_N2 (0x204c | REGS_NORTH_PIPE_AND_PORT) 1599#define FDI_PIPE_MN_TU_SIZE_MASK (0x3f << 25) 1600#define FDI_PIPE_MN_VALUE_MASK (0xffffff << 0) 1601 1602// SNB A stepping 1603#define FDI_LINK_TRAIN_400MV_0DB_SNB_A (0x38 << 22) 1604#define FDI_LINK_TRAIN_400MV_6DB_SNB_A (0x02 << 22) 1605#define FDI_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01 << 22) 1606#define FDI_LINK_TRAIN_800MV_0DB_SNB_A (0x00 << 22) 1607 1608// SNB B stepping 1609#define FDI_LINK_TRAIN_400MV_0DB_SNB_B (0x00 << 22) 1610#define FDI_LINK_TRAIN_400MV_6DB_SNB_B (0x3a << 22) 1611#define FDI_LINK_TRAIN_600MV_3_5DB_SNB_B (0x39 << 22) 1612#define FDI_LINK_TRAIN_800MV_0DB_SNB_B (0x38 << 22) 1613#define FDI_LINK_TRAIN_VOL_EMP_MASK (0x3f << 22) 1614#define FDI_TX_ENHANCE_FRAME_ENABLE (1 << 18) 1615#define FDI_TX_PLL_ENABLED (1 << 14) 1616 1617#define FDI_DP_PORT_WIDTH_SHIFT 19 1618#define FDI_DP_PORT_WIDTH_MASK (7 << FDI_DP_PORT_WIDTH_SHIFT) 1619#define FDI_DP_PORT_WIDTH(width) (((width) - 1) << FDI_DP_PORT_WIDTH_SHIFT) 1620 1621#define FDI_PLL_BIOS_0 0x46000 1622#define FDI_PLL_FB_CLOCK_MASK 0xff 1623#define FDI_PLL_BIOS_1 0x46004 1624#define FDI_PLL_BIOS_2 0x46008 1625 1626#define FDI_AUTO_TRAINING (1 << 10) 1627#define FDI_AUTO_TRAIN_DONE (1 << 1) 1628 1629#define FDI_LINK_TRAIN_PATTERN_1_CPT (0 << 8) 1630#define FDI_LINK_TRAIN_PATTERN_2_CPT (1 << 8) 1631#define FDI_LINK_TRAIN_PATTERN_IDLE_CPT (2 << 8) 1632#define FDI_LINK_TRAIN_NORMAL_CPT (3 << 8) 1633#define FDI_LINK_TRAIN_PATTERN_MASK_CPT (3 << 8) 1634 1635// IvyBridge changes it up because... they hate developers? 1636#define FDI_LINK_TRAIN_PATTERN_1_IVB (0 << 8) 1637#define FDI_LINK_TRAIN_PATTERN_2_IVB (1 << 8) 1638#define FDI_LINK_TRAIN_PATTERN_IDLE_IVB (2 << 8) 1639#define FDI_LINK_TRAIN_NONE_IVB (3 << 8) 1640 1641#define PCH_FDI_RXA_CHICKEN (0x200c | REGS_SOUTH_SHARED) 1642#define PCH_FDI_RXB_CHICKEN (0x2010 | REGS_SOUTH_SHARED) 1643#define FDI_RX_PHASE_SYNC_POINTER_EN (1 << 0) 1644#define FDI_RX_PHASE_SYNC_POINTER_OVR (1 << 1) 1645 1646#define SFUSE_STRAP (0x2014 | REGS_SOUTH_SHARED) 1647#define SFUSE_STRAP_RAW_FREQUENCY (1 << 8) 1648 1649// CPU Panel Fitters - These are for IronLake and up and are the CPU internal 1650// panel fitters. 1651#define PCH_PANEL_FITTER_BASE_REGISTER 0x68000 1652#define PCH_PANEL_FITTER_PIPE_OFFSET 0x00800 1653 1654#define PCH_PANEL_FITTER_WINDOW_POS 0x70 1655#define PCH_PANEL_FITTER_WINDOW_SIZE 0x74 1656#define PCH_PANEL_FITTER_CONTROL 0x80 1657//not on IvyBridge: 1658#define PCH_PANEL_FITTER_V_SCALE 0x84 1659#define PCH_PANEL_FITTER_H_SCALE 0x90 1660 1661#define PANEL_FITTER_ENABLED (1 << 31) 1662//pipes are hardcoded according to offset on SkyLake and later 1663#define PANEL_FITTER_PIPE_MASK (3 << 29) 1664#define PANEL_FITTER_PIPE_A (0 << 29) 1665#define PANEL_FITTER_PIPE_B (1 << 29) 1666#define PANEL_FITTER_PIPE_C (2 << 29) 1667#define PANEL_FITTER_SCALING_MODE_MASK (7 << 26) 1668#define PANEL_FITTER_FILTER_MASK (3 << 24) 1669 1670struct overlay_scale { 1671 uint32 _reserved0 : 3; 1672 uint32 horizontal_scale_fraction : 12; 1673 uint32 _reserved1 : 1; 1674 uint32 horizontal_downscale_factor : 3; 1675 uint32 _reserved2 : 1; 1676 uint32 vertical_scale_fraction : 12; 1677}; 1678 1679#define OVERLAY_FORMAT_RGB15 0x2 1680#define OVERLAY_FORMAT_RGB16 0x3 1681#define OVERLAY_FORMAT_RGB32 0x1 1682#define OVERLAY_FORMAT_YCbCr422 0x8 1683#define OVERLAY_FORMAT_YCbCr411 0x9 1684#define OVERLAY_FORMAT_YCbCr420 0xc 1685 1686#define OVERLAY_MIRROR_NORMAL 0x0 1687#define OVERLAY_MIRROR_HORIZONTAL 0x1 1688#define OVERLAY_MIRROR_VERTICAL 0x2 1689 1690// The real overlay registers are written to using an update buffer 1691 1692struct overlay_registers { 1693 uint32 buffer_rgb0; 1694 uint32 buffer_rgb1; 1695 uint32 buffer_u0; 1696 uint32 buffer_v0; 1697 uint32 buffer_u1; 1698 uint32 buffer_v1; 1699 // (0x18) OSTRIDE - overlay stride 1700 uint16 stride_rgb; 1701 uint16 stride_uv; 1702 // (0x1c) YRGB_VPH - Y/RGB vertical phase 1703 uint16 vertical_phase0_rgb; 1704 uint16 vertical_phase1_rgb; 1705 // (0x20) UV_VPH - UV vertical phase 1706 uint16 vertical_phase0_uv; 1707 uint16 vertical_phase1_uv; 1708 // (0x24) HORZ_PH - horizontal phase 1709 uint16 horizontal_phase_rgb; 1710 uint16 horizontal_phase_uv; 1711 // (0x28) INIT_PHS - initial phase shift 1712 uint32 initial_vertical_phase0_shift_rgb0 : 4; 1713 uint32 initial_vertical_phase1_shift_rgb0 : 4; 1714 uint32 initial_horizontal_phase_shift_rgb0 : 4; 1715 uint32 initial_vertical_phase0_shift_uv : 4; 1716 uint32 initial_vertical_phase1_shift_uv : 4; 1717 uint32 initial_horizontal_phase_shift_uv : 4; 1718 uint32 _reserved0 : 8; 1719 // (0x2c) DWINPOS - destination window position 1720 uint16 window_left; 1721 uint16 window_top; 1722 // (0x30) DWINSZ - destination window size 1723 uint16 window_width; 1724 uint16 window_height; 1725 // (0x34) SWIDTH - source width 1726 uint16 source_width_rgb; 1727 uint16 source_width_uv; 1728 // (0x38) SWITDHSW - source width in 8 byte steps 1729 uint16 source_bytes_per_row_rgb; 1730 uint16 source_bytes_per_row_uv; 1731 uint16 source_height_rgb; 1732 uint16 source_height_uv; 1733 overlay_scale scale_rgb; 1734 overlay_scale scale_uv; 1735 // (0x48) OCLRC0 - overlay color correction 0 1736 uint32 brightness_correction : 8; // signed, -128 to 127 1737 uint32 _reserved1 : 10; 1738 uint32 contrast_correction : 9; // fixed point: 3.6 bits 1739 uint32 _reserved2 : 5; 1740 // (0x4c) OCLRC1 - overlay color correction 1 1741 uint32 saturation_cos_correction : 10; // fixed point: 3.7 bits 1742 uint32 _reserved3 : 6; 1743 uint32 saturation_sin_correction : 11; // signed fixed point: 3.7 bits 1744 uint32 _reserved4 : 5; 1745 // (0x50) DCLRKV - destination color key value 1746 uint32 color_key_blue : 8; 1747 uint32 color_key_green : 8; 1748 uint32 color_key_red : 8; 1749 uint32 _reserved5 : 8; 1750 // (0x54) DCLRKM - destination color key mask 1751 uint32 color_key_mask_blue : 8; 1752 uint32 color_key_mask_green : 8; 1753 uint32 color_key_mask_red : 8; 1754 uint32 _reserved6 : 7; 1755 uint32 color_key_enabled : 1; 1756 // (0x58) SCHRKVH - source chroma key high value 1757 uint32 source_chroma_key_high_red : 8; 1758 uint32 source_chroma_key_high_blue : 8; 1759 uint32 source_chroma_key_high_green : 8; 1760 uint32 _reserved7 : 8; 1761 // (0x5c) SCHRKVL - source chroma key low value 1762 uint32 source_chroma_key_low_red : 8; 1763 uint32 source_chroma_key_low_blue : 8; 1764 uint32 source_chroma_key_low_green : 8; 1765 uint32 _reserved8 : 8; 1766 // (0x60) SCHRKEN - source chroma key enable 1767 uint32 _reserved9 : 24; 1768 uint32 source_chroma_key_red_enabled : 1; 1769 uint32 source_chroma_key_blue_enabled : 1; 1770 uint32 source_chroma_key_green_enabled : 1; 1771 uint32 _reserved10 : 5; 1772 // (0x64) OCONFIG - overlay configuration 1773 uint32 _reserved11 : 3; 1774 uint32 color_control_output_mode : 1; 1775 uint32 yuv_to_rgb_bypass : 1; 1776 uint32 _reserved12 : 11; 1777 uint32 gamma2_enabled : 1; 1778 uint32 _reserved13 : 1; 1779 uint32 select_pipe : 1; 1780 uint32 slot_time : 8; 1781 uint32 _reserved14 : 5; 1782 // (0x68) OCOMD - overlay command 1783 uint32 overlay_enabled : 1; 1784 uint32 active_field : 1; 1785 uint32 active_buffer : 2; 1786 uint32 test_mode : 1; 1787 uint32 buffer_field_mode : 1; 1788 uint32 _reserved15 : 1; 1789 uint32 tv_flip_field_enabled : 1; 1790 uint32 _reserved16 : 1; 1791 uint32 tv_flip_field_parity : 1; 1792 uint32 source_format : 4; 1793 uint32 ycbcr422_order : 2; 1794 uint32 _reserved18 : 1; 1795 uint32 mirroring_mode : 2; 1796 uint32 _reserved19 : 13; 1797 1798 uint32 _reserved20; 1799 1800 uint32 start_0y; 1801 uint32 start_1y; 1802 uint32 start_0u; 1803 uint32 start_0v; 1804 uint32 start_1u; 1805 uint32 start_1v; 1806 uint32 _reserved21[6]; 1807#if 0 1808 // (0x70) AWINPOS - alpha blend window position 1809 uint32 awinpos; 1810 // (0x74) AWINSZ - alpha blend window size 1811 uint32 awinsz; 1812 1813 uint32 _reserved21[10]; 1814#endif 1815 1816 // (0xa0) FASTHSCALE - fast horizontal downscale (strangely enough, 1817 // the next two registers switch the usual Y/RGB vs. UV order) 1818 uint16 horizontal_scale_uv; 1819 uint16 horizontal_scale_rgb; 1820 // (0xa4) UVSCALEV - vertical downscale 1821 uint16 vertical_scale_uv; 1822 uint16 vertical_scale_rgb; 1823 1824 uint32 _reserved22[86]; 1825 1826 // (0x200) polyphase filter coefficients 1827 uint16 vertical_coefficients_rgb[128]; 1828 uint16 horizontal_coefficients_rgb[128]; 1829 1830 uint32 _reserved23[64]; 1831 1832 // (0x500) 1833 uint16 vertical_coefficients_uv[128]; 1834 uint16 horizontal_coefficients_uv[128]; 1835}; 1836 1837// i965 overlay support is currently realized using its 3D hardware 1838#define INTEL_i965_OVERLAY_STATE_SIZE 36864 1839#define INTEL_i965_3D_CONTEXT_SIZE 32768 1840 1841inline bool 1842intel_uses_physical_overlay(intel_shared_info &info) 1843{ 1844 return !info.device_type.InGroup(INTEL_GROUP_Gxx); 1845} 1846 1847 1848struct hardware_status { 1849 uint32 interrupt_status_register; 1850 uint32 _reserved0[3]; 1851 void* primary_ring_head_storage; 1852 uint32 _reserved1[3]; 1853 void* secondary_ring_0_head_storage; 1854 void* secondary_ring_1_head_storage; 1855 uint32 _reserved2[2]; 1856 void* binning_head_storage; 1857 uint32 _reserved3[3]; 1858 uint32 store[1008]; 1859}; 1860 1861 1862#endif /* INTEL_EXTREME_H */ 1863