| /linux-master/drivers/gpu/drm/radeon/ |
| H A D | cikd.h | 860 #define SDMA0 (1 << 10) macro
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| H A D | cik_sdma.c | 41 * and gfx. There are two DMA engines (SDMA0, SDMA1)
177 ref_and_mask = SDMA0;
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| /linux-master/drivers/gpu/drm/amd/amdgpu/ |
| H A D | amdgpu_amdkfd_arcturus.c | 82 sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA0, 0,
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| H A D | amdgpu_amdkfd_gc_9_4_3.c | 48 SOC15_REG_OFFSET(SDMA0, GET_INST(SDMA0, engine_id),
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| H A D | amdgpu_amdkfd_gfx_v10.c | 165 SOC15_REG_OFFSET(SDMA0, 0,
168 * on SDMA1 base address (dw 0x1860) but based on SDMA0
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| H A D | amdgpu_amdkfd_gfx_v10_3.c | 143 sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA0, 0,
147 sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA0, 0,
151 sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA0, 0,
155 sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA0, 0,
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| H A D | amdgpu_amdkfd_gfx_v11.c | 134 sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA0, 0,
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| H A D | amdgpu_amdkfd_gfx_v9.c | 194 sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA0, 0,
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| H A D | amdgpu_psp.c | 1761 dev_mask = GET_MASK(SDMA0, instance_mask);
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| H A D | nbio_v7_9.c | 83 dev_inst = GET_INST(SDMA0, instance);
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| H A D | nv.c | 343 { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_STATUS_REG)},
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| H A D | sdma_v2_4.c | 81 * and gfx. There are two DMA engines (SDMA0, SDMA1)
277 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA0, 1);
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| H A D | sdma_v3_0.c | 185 * and gfx. There are two DMA engines (SDMA0, SDMA1)
453 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA0, 1);
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| H A D | sdma_v4_0.c | 90 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831d07),
91 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xff000ff0, 0x3f000100),
92 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_IB_CNTL, 0x800f0100, 0x00000100),
93 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
94 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_IB_CNTL, 0x800f0100, 0x00000100),
95 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
96 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_POWER_CNTL, 0x003ff006, 0x0003c000),
97 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_IB_CNTL, 0x800f0100, 0x00000100),
98 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
99 SOC15_REG_GOLDEN_VALUE(SDMA0,
[all...] |
| H A D | sdma_v4_4.c | 60 { "SDMA_MBANK_DATA_BUF0_SED", SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_EDC_COUNTER),
64 { "SDMA_MBANK_DATA_BUF1_SED", SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_EDC_COUNTER),
68 { "SDMA_MBANK_DATA_BUF2_SED", SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_EDC_COUNTER),
72 { "SDMA_MBANK_DATA_BUF3_SED", SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_EDC_COUNTER),
76 { "SDMA_MBANK_DATA_BUF4_SED", SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_EDC_COUNTER),
80 { "SDMA_MBANK_DATA_BUF5_SED", SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_EDC_COUNTER),
84 { "SDMA_MBANK_DATA_BUF6_SED", SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_EDC_COUNTER),
88 { "SDMA_MBANK_DATA_BUF7_SED", SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_EDC_COUNTER),
92 { "SDMA_MBANK_DATA_BUF8_SED", SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_EDC_COUNTER),
96 { "SDMA_MBANK_DATA_BUF9_SED", SOC15_REG_ENTRY(SDMA0,
[all...] |
| H A D | sdma_v4_4_2.c | 64 u32 dev_inst = GET_INST(SDMA0, instance);
1783 data = RREG32(SOC15_REG_OFFSET(SDMA0, GET_INST(SDMA0, 0), regSDMA_CLK_CTRL));
1788 data = RREG32(SOC15_REG_OFFSET(SDMA0, GET_INST(SDMA0, 0), regSDMA_POWER_CNTL));
1886 dev_inst = GET_INST(SDMA0, i);
2082 {AMDGPU_RAS_REG_ENTRY(SDMA0, 0, regSDMA_UE_ERR_STATUS_LO, regSDMA_UE_ERR_STATUS_HI),
2118 uint32_t sdma_dev_inst = GET_INST(SDMA0, sdma_inst);
2156 uint32_t sdma_dev_inst = GET_INST(SDMA0, sdma_inst);
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| H A D | soc15.c | 364 { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_STATUS_REG)},
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| H A D | soc21.c | 263 { SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_STATUS_REG)},
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