Searched refs:SCLK_PWRMGT_CNTL (Results 1 - 22 of 22) sorted by relevance

/linux-master/drivers/gpu/drm/radeon/
H A Drv730d.h83 #define SCLK_PWRMGT_CNTL 0x644 macro
H A Dtrinityd.h175 #define SCLK_PWRMGT_CNTL 0x678 macro
H A Drv770_dpm.c135 WREG32_P(SCLK_PWRMGT_CNTL, DYN_GFX_CLK_OFF_EN, ~DYN_GFX_CLK_OFF_EN);
137 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_GFX_CLK_OFF_EN);
138 WREG32_P(SCLK_PWRMGT_CNTL, GFX_CLK_FORCE_ON, ~GFX_CLK_FORCE_ON);
139 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~GFX_CLK_FORCE_ON);
174 if (RREG32(SCLK_PWRMGT_CNTL) & DYN_GFX_CLK_OFF_EN)
178 WREG32_P(SCLK_PWRMGT_CNTL, DYN_GFX_CLK_OFF_EN, ~DYN_GFX_CLK_OFF_EN);
183 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF);
201 WREG32_P(SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, ~SCLK_PWRMGT_OFF);
855 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_FORCE_TREND_SEL);
857 WREG32_P(SCLK_PWRMGT_CNTL, FIR_FORCE_TREND_SE
[all...]
H A Dr600_dpm.c245 WREG32_P(SCLK_PWRMGT_CNTL, DYN_GFX_CLK_OFF_EN, ~DYN_GFX_CLK_OFF_EN);
247 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_GFX_CLK_OFF_EN);
304 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF);
306 WREG32_P(SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, ~SCLK_PWRMGT_OFF);
359 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_FORCE_TREND_SEL);
361 WREG32_P(SCLK_PWRMGT_CNTL, FIR_FORCE_TREND_SEL, ~FIR_FORCE_TREND_SEL);
363 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_TREND_MODE);
365 WREG32_P(SCLK_PWRMGT_CNTL, FIR_TREND_MODE, ~FIR_TREND_MODE);
H A Dcypress_dpm.c102 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_GFX_CLK_OFF_EN);
103 WREG32_P(SCLK_PWRMGT_CNTL, GFX_CLK_FORCE_ON, ~GFX_CLK_FORCE_ON);
104 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~GFX_CLK_FORCE_ON);
140 WREG32_P(SCLK_PWRMGT_CNTL, DYN_LIGHT_SLEEP_EN, ~DYN_LIGHT_SLEEP_EN);
142 WREG32_P(SCLK_PWRMGT_CNTL, DYN_GFX_CLK_OFF_EN, ~DYN_GFX_CLK_OFF_EN);
144 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_GFX_CLK_OFF_EN);
145 WREG32_P(SCLK_PWRMGT_CNTL, GFX_CLK_FORCE_ON, ~GFX_CLK_FORCE_ON);
146 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~GFX_CLK_FORCE_ON);
150 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_LIGHT_SLEEP_EN);
247 WREG32_P(SCLK_PWRMGT_CNTL,
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H A Dsumo_dpm.c89 WREG32_P(SCLK_PWRMGT_CNTL, DYN_GFX_CLK_OFF_EN, ~DYN_GFX_CLK_OFF_EN);
91 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_GFX_CLK_OFF_EN);
92 WREG32_P(SCLK_PWRMGT_CNTL, GFX_CLK_FORCE_ON, ~GFX_CLK_FORCE_ON);
93 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~GFX_CLK_FORCE_ON);
439 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_FORCE_TREND_SEL);
441 WREG32_P(SCLK_PWRMGT_CNTL, FIR_FORCE_TREND_SEL, ~FIR_FORCE_TREND_SEL);
444 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_TREND_MODE);
447 WREG32_P(SCLK_PWRMGT_CNTL, FIR_TREND_MODE, ~FIR_TREND_MODE);
915 WREG32_P(SCLK_PWRMGT_CNTL, FIR_RESET, ~FIR_RESET);
920 WREG32_P(SCLK_PWRMGT_CNTL,
[all...]
H A Dtrinity_dpm.c398 WREG32_P(SCLK_PWRMGT_CNTL, DYN_GFX_CLK_OFF_EN, ~DYN_GFX_CLK_OFF_EN);
400 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_GFX_CLK_OFF_EN);
401 WREG32_P(SCLK_PWRMGT_CNTL, GFX_CLK_FORCE_ON, ~GFX_CLK_FORCE_ON);
402 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~GFX_CLK_FORCE_ON);
461 WREG32_P(SCLK_PWRMGT_CNTL, DYN_PWR_DOWN_EN, ~DYN_PWR_DOWN_EN);
463 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_PWR_DOWN_EN);
725 if (RREG32(SCLK_PWRMGT_CNTL) & DYNAMIC_PM_EN)
756 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~(RESET_SCLK_CNT | RESET_BUSY_CNT));
761 WREG32_P(SCLK_PWRMGT_CNTL, RESET_SCLK_CNT | RESET_BUSY_CNT,
H A Drv730_dpm.c450 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF);
468 WREG32_P(SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, ~SCLK_PWRMGT_OFF);
H A Dsumod.h152 #define SCLK_PWRMGT_CNTL 0x644 macro
H A Dci_dpm.c1495 tmp = RREG32_SMC(SCLK_PWRMGT_CNTL);
1497 WREG32_SMC(SCLK_PWRMGT_CNTL, tmp);
1556 tmp = RREG32_SMC(SCLK_PWRMGT_CNTL);
1558 WREG32_SMC(SCLK_PWRMGT_CNTL, tmp);
1579 u32 tmp = RREG32_SMC(SCLK_PWRMGT_CNTL);
1585 WREG32_SMC(SCLK_PWRMGT_CNTL, tmp);
2019 tmp = RREG32_SMC(SCLK_PWRMGT_CNTL);
2021 WREG32_SMC(SCLK_PWRMGT_CNTL, tmp);
2037 tmp = RREG32_SMC(SCLK_PWRMGT_CNTL);
2039 WREG32_SMC(SCLK_PWRMGT_CNTL, tm
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H A Drv770d.h158 #define SCLK_PWRMGT_CNTL 0x644 macro
H A Dkv_dpm.c502 u32 sclk_pwrmgt_cntl = RREG32_SMC(SCLK_PWRMGT_CNTL);
507 WREG32_SMC(SCLK_PWRMGT_CNTL, sclk_pwrmgt_cntl);
512 u32 sclk_pwrmgt_cntl = RREG32_SMC(SCLK_PWRMGT_CNTL);
516 WREG32_SMC(SCLK_PWRMGT_CNTL, sclk_pwrmgt_cntl);
H A Dnid.h599 #define SCLK_PWRMGT_CNTL 0x644 macro
H A Dsi_dpm.c3282 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF);
3284 WREG32_P(SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, ~SCLK_PWRMGT_OFF);
3713 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_FORCE_TREND_SEL);
3715 WREG32_P(SCLK_PWRMGT_CNTL, FIR_FORCE_TREND_SEL, ~FIR_FORCE_TREND_SEL);
3718 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_TREND_MODE);
3721 WREG32_P(SCLK_PWRMGT_CNTL, FIR_TREND_MODE, ~FIR_TREND_MODE);
H A Dni_dpm.c1205 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_GFX_CLK_OFF_EN);
1206 WREG32_P(SCLK_PWRMGT_CNTL, GFX_CLK_FORCE_ON, ~GFX_CLK_FORCE_ON);
1207 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~GFX_CLK_FORCE_ON);
H A Dsid.h251 #define SCLK_PWRMGT_CNTL 0x788 macro
H A Dcikd.h109 #define SCLK_PWRMGT_CNTL 0xC0200008 macro
H A Dr600d.h1307 #define SCLK_PWRMGT_CNTL 0x620 macro
H A Devergreend.h137 #define SCLK_PWRMGT_CNTL 0x644 macro
/linux-master/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
H A Dsmu7_hwmgr.c482 SCLK_PWRMGT_CNTL, RESET_SCLK_CNT, 0);
484 SCLK_PWRMGT_CNTL, RESET_BUSY_CNT, 0);
499 SCLK_PWRMGT_CNTL, RESET_SCLK_CNT, 1);
501 SCLK_PWRMGT_CNTL, RESET_BUSY_CNT, 1);
1102 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL,
1272 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL,
1353 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL,
/linux-master/drivers/gpu/drm/amd/pm/legacy-dpm/
H A Dsi_dpm.c3799 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF);
3801 WREG32_P(SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, ~SCLK_PWRMGT_OFF);
4237 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_FORCE_TREND_SEL);
4239 WREG32_P(SCLK_PWRMGT_CNTL, FIR_FORCE_TREND_SEL, ~FIR_FORCE_TREND_SEL);
4242 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_TREND_MODE);
4245 WREG32_P(SCLK_PWRMGT_CNTL, FIR_TREND_MODE, ~FIR_TREND_MODE);
/linux-master/drivers/gpu/drm/amd/amdgpu/
H A Dsid.h252 #define SCLK_PWRMGT_CNTL 0x1e2 macro

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