/linux-master/drivers/gpu/drm/radeon/ |
H A D | rv730d.h | 83 #define SCLK_PWRMGT_CNTL 0x644 macro
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H A D | trinityd.h | 175 #define SCLK_PWRMGT_CNTL 0x678 macro
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H A D | rv770_dpm.c | 135 WREG32_P(SCLK_PWRMGT_CNTL, DYN_GFX_CLK_OFF_EN, ~DYN_GFX_CLK_OFF_EN); 137 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_GFX_CLK_OFF_EN); 138 WREG32_P(SCLK_PWRMGT_CNTL, GFX_CLK_FORCE_ON, ~GFX_CLK_FORCE_ON); 139 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~GFX_CLK_FORCE_ON); 174 if (RREG32(SCLK_PWRMGT_CNTL) & DYN_GFX_CLK_OFF_EN) 178 WREG32_P(SCLK_PWRMGT_CNTL, DYN_GFX_CLK_OFF_EN, ~DYN_GFX_CLK_OFF_EN); 183 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF); 201 WREG32_P(SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, ~SCLK_PWRMGT_OFF); 855 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_FORCE_TREND_SEL); 857 WREG32_P(SCLK_PWRMGT_CNTL, FIR_FORCE_TREND_SE [all...] |
H A D | r600_dpm.c | 245 WREG32_P(SCLK_PWRMGT_CNTL, DYN_GFX_CLK_OFF_EN, ~DYN_GFX_CLK_OFF_EN); 247 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_GFX_CLK_OFF_EN); 304 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF); 306 WREG32_P(SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, ~SCLK_PWRMGT_OFF); 359 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_FORCE_TREND_SEL); 361 WREG32_P(SCLK_PWRMGT_CNTL, FIR_FORCE_TREND_SEL, ~FIR_FORCE_TREND_SEL); 363 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_TREND_MODE); 365 WREG32_P(SCLK_PWRMGT_CNTL, FIR_TREND_MODE, ~FIR_TREND_MODE);
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H A D | cypress_dpm.c | 102 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_GFX_CLK_OFF_EN); 103 WREG32_P(SCLK_PWRMGT_CNTL, GFX_CLK_FORCE_ON, ~GFX_CLK_FORCE_ON); 104 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~GFX_CLK_FORCE_ON); 140 WREG32_P(SCLK_PWRMGT_CNTL, DYN_LIGHT_SLEEP_EN, ~DYN_LIGHT_SLEEP_EN); 142 WREG32_P(SCLK_PWRMGT_CNTL, DYN_GFX_CLK_OFF_EN, ~DYN_GFX_CLK_OFF_EN); 144 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_GFX_CLK_OFF_EN); 145 WREG32_P(SCLK_PWRMGT_CNTL, GFX_CLK_FORCE_ON, ~GFX_CLK_FORCE_ON); 146 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~GFX_CLK_FORCE_ON); 150 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_LIGHT_SLEEP_EN); 247 WREG32_P(SCLK_PWRMGT_CNTL, [all...] |
H A D | sumo_dpm.c | 89 WREG32_P(SCLK_PWRMGT_CNTL, DYN_GFX_CLK_OFF_EN, ~DYN_GFX_CLK_OFF_EN); 91 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_GFX_CLK_OFF_EN); 92 WREG32_P(SCLK_PWRMGT_CNTL, GFX_CLK_FORCE_ON, ~GFX_CLK_FORCE_ON); 93 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~GFX_CLK_FORCE_ON); 439 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_FORCE_TREND_SEL); 441 WREG32_P(SCLK_PWRMGT_CNTL, FIR_FORCE_TREND_SEL, ~FIR_FORCE_TREND_SEL); 444 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_TREND_MODE); 447 WREG32_P(SCLK_PWRMGT_CNTL, FIR_TREND_MODE, ~FIR_TREND_MODE); 915 WREG32_P(SCLK_PWRMGT_CNTL, FIR_RESET, ~FIR_RESET); 920 WREG32_P(SCLK_PWRMGT_CNTL, [all...] |
H A D | trinity_dpm.c | 398 WREG32_P(SCLK_PWRMGT_CNTL, DYN_GFX_CLK_OFF_EN, ~DYN_GFX_CLK_OFF_EN); 400 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_GFX_CLK_OFF_EN); 401 WREG32_P(SCLK_PWRMGT_CNTL, GFX_CLK_FORCE_ON, ~GFX_CLK_FORCE_ON); 402 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~GFX_CLK_FORCE_ON); 461 WREG32_P(SCLK_PWRMGT_CNTL, DYN_PWR_DOWN_EN, ~DYN_PWR_DOWN_EN); 463 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_PWR_DOWN_EN); 725 if (RREG32(SCLK_PWRMGT_CNTL) & DYNAMIC_PM_EN) 756 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~(RESET_SCLK_CNT | RESET_BUSY_CNT)); 761 WREG32_P(SCLK_PWRMGT_CNTL, RESET_SCLK_CNT | RESET_BUSY_CNT,
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H A D | rv730_dpm.c | 450 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF); 468 WREG32_P(SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, ~SCLK_PWRMGT_OFF);
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H A D | sumod.h | 152 #define SCLK_PWRMGT_CNTL 0x644 macro
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H A D | ci_dpm.c | 1495 tmp = RREG32_SMC(SCLK_PWRMGT_CNTL); 1497 WREG32_SMC(SCLK_PWRMGT_CNTL, tmp); 1556 tmp = RREG32_SMC(SCLK_PWRMGT_CNTL); 1558 WREG32_SMC(SCLK_PWRMGT_CNTL, tmp); 1579 u32 tmp = RREG32_SMC(SCLK_PWRMGT_CNTL); 1585 WREG32_SMC(SCLK_PWRMGT_CNTL, tmp); 2019 tmp = RREG32_SMC(SCLK_PWRMGT_CNTL); 2021 WREG32_SMC(SCLK_PWRMGT_CNTL, tmp); 2037 tmp = RREG32_SMC(SCLK_PWRMGT_CNTL); 2039 WREG32_SMC(SCLK_PWRMGT_CNTL, tm [all...] |
H A D | rv770d.h | 158 #define SCLK_PWRMGT_CNTL 0x644 macro
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H A D | kv_dpm.c | 502 u32 sclk_pwrmgt_cntl = RREG32_SMC(SCLK_PWRMGT_CNTL); 507 WREG32_SMC(SCLK_PWRMGT_CNTL, sclk_pwrmgt_cntl); 512 u32 sclk_pwrmgt_cntl = RREG32_SMC(SCLK_PWRMGT_CNTL); 516 WREG32_SMC(SCLK_PWRMGT_CNTL, sclk_pwrmgt_cntl);
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H A D | nid.h | 599 #define SCLK_PWRMGT_CNTL 0x644 macro
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H A D | si_dpm.c | 3282 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF); 3284 WREG32_P(SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, ~SCLK_PWRMGT_OFF); 3713 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_FORCE_TREND_SEL); 3715 WREG32_P(SCLK_PWRMGT_CNTL, FIR_FORCE_TREND_SEL, ~FIR_FORCE_TREND_SEL); 3718 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_TREND_MODE); 3721 WREG32_P(SCLK_PWRMGT_CNTL, FIR_TREND_MODE, ~FIR_TREND_MODE);
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H A D | ni_dpm.c | 1205 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_GFX_CLK_OFF_EN); 1206 WREG32_P(SCLK_PWRMGT_CNTL, GFX_CLK_FORCE_ON, ~GFX_CLK_FORCE_ON); 1207 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~GFX_CLK_FORCE_ON);
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H A D | sid.h | 251 #define SCLK_PWRMGT_CNTL 0x788 macro
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H A D | cikd.h | 109 #define SCLK_PWRMGT_CNTL 0xC0200008 macro
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H A D | r600d.h | 1307 #define SCLK_PWRMGT_CNTL 0x620 macro
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H A D | evergreend.h | 137 #define SCLK_PWRMGT_CNTL 0x644 macro
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/linux-master/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ |
H A D | smu7_hwmgr.c | 482 SCLK_PWRMGT_CNTL, RESET_SCLK_CNT, 0); 484 SCLK_PWRMGT_CNTL, RESET_BUSY_CNT, 0); 499 SCLK_PWRMGT_CNTL, RESET_SCLK_CNT, 1); 501 SCLK_PWRMGT_CNTL, RESET_BUSY_CNT, 1); 1102 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL, 1272 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL, 1353 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL,
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/linux-master/drivers/gpu/drm/amd/pm/legacy-dpm/ |
H A D | si_dpm.c | 3799 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF); 3801 WREG32_P(SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, ~SCLK_PWRMGT_OFF); 4237 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_FORCE_TREND_SEL); 4239 WREG32_P(SCLK_PWRMGT_CNTL, FIR_FORCE_TREND_SEL, ~FIR_FORCE_TREND_SEL); 4242 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_TREND_MODE); 4245 WREG32_P(SCLK_PWRMGT_CNTL, FIR_TREND_MODE, ~FIR_TREND_MODE);
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/linux-master/drivers/gpu/drm/amd/amdgpu/ |
H A D | sid.h | 252 #define SCLK_PWRMGT_CNTL 0x1e2 macro
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