/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
H A D | AArch64PBQPRegAlloc.h | 30 // parity(Rd) == parity(Ra). 32 bool addIntraChainConstraint(PBQPRAGraph &G, unsigned Rd, unsigned Ra); 35 void addInterChainConstraint(PBQPRAGraph &G, unsigned Rd, unsigned Ra);
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H A D | AArch64PBQPRegAlloc.cpp | 158 bool A57ChainingConstraint::addIntraChainConstraint(PBQPRAGraph &G, unsigned Rd, argument 160 if (Rd == Ra) 165 if (Register::isPhysicalRegister(Rd) || Register::isPhysicalRegister(Ra)) { 166 LLVM_DEBUG(dbgs() << "Rd is a physical reg:" 167 << Register::isPhysicalRegister(Rd) << '\n'); 173 PBQPRAGraph::NodeId node1 = G.getMetadata().getNodeIdForVReg(Rd); 186 const LiveInterval &ld = LIs.getInterval(Rd); 242 void A57ChainingConstraint::addInterChainConstraint(PBQPRAGraph &G, unsigned Rd, argument 248 if (Rd != Ra) { 250 << " to " << printReg(Rd, TR 362 Register Rd = MI.getOperand(0).getReg(); local 372 Register Rd = MI.getOperand(0).getReg(); local [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/Disassembler/ |
H A D | AArch64Disassembler.cpp | 845 unsigned Rd = fieldFromInstruction(Insn, 0, 5); local 850 DecodeFPR128RegisterClass(Inst, Rd, Address, Decoder); 853 DecodeGPR64RegisterClass(Inst, Rd, Address, Decoder); 936 unsigned Rd = fieldFromInstruction(insn, 0, 5); local 964 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); 985 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 998 unsigned Rd = fieldFromInstruction(insn, 0, 5); local 1010 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); 1015 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 1507 unsigned Rd local 1564 unsigned Rd = fieldFromInstruction(insn, 0, 5); local 1595 unsigned Rd = fieldFromInstruction(insn, 0, 5); local 1634 unsigned Rd = fieldFromInstruction(insn, 0, 5); local 1651 unsigned Rd = fieldFromInstruction(insn, 0, 5); local 1670 unsigned Rd = fieldFromInstruction(insn, 0, 5); local [all...] |
/freebsd-11-stable/contrib/llvm-project/lldb/source/Plugins/Instruction/ARM/ |
H A D | EmulateInstructionARM.cpp | 1177 uint32_t Rd; // the destination register 1181 Rd = 7; 1185 Rd = Bits32(opcode, 15, 12); 1195 if (Rd == GetFramePointerRegisterNumber()) 1203 if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_r0 + Rd, 1238 uint32_t Rd; // the destination register 1241 Rd = 7; 1244 Rd = 12; 1251 if (Rd == GetFramePointerRegisterNumber()) 1259 if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_r0 + Rd, s 1298 uint32_t Rd; // the destination register local 1386 uint32_t Rd; // the destination register local 1628 uint32_t Rd; // the destination register local 1690 uint32_t Rd; // the destination register local 3165 uint32_t Rd, Rn; local 3231 uint32_t Rd, Rn, Rm; local 3766 uint32_t Rd; // the destination register local 3855 uint32_t Rd; // the destination register local 5830 uint32_t Rd, Rn; local 5900 uint32_t Rd, Rn, Rm; local 5979 uint32_t Rd; local 6047 uint32_t Rd, Rn; local 6123 uint32_t Rd, Rn, Rm; local 6212 uint32_t Rd, Rn; local 6288 uint32_t Rd, Rn, Rm; local 8854 uint32_t Rd, Rn; local 8933 uint32_t Rd, Rn, Rm; local 9023 uint32_t Rd, Rn; local 9100 uint32_t Rd, Rn, Rm; local 9187 uint32_t Rd; // the destination register local 9260 uint32_t Rd; // the destination register local 9338 uint32_t Rd; // the destination register local 9398 uint32_t Rd; // the destination register local 9467 uint32_t Rd; // the destination register local 9536 uint32_t Rd; // the destination register local 9616 uint32_t Rd; // the destination register local 9710 uint32_t Rd; // the destination register local 14259 WriteCoreRegOptionalFlags( Context &context, const uint32_t result, const uint32_t Rd, bool setflags, const uint32_t carry, const uint32_t overflow) argument [all...] |
H A D | EmulateInstructionARM.h | 200 const uint32_t Rd, bool setflags, 205 const uint32_t Rd) { 207 return WriteCoreRegOptionalFlags(context, result, Rd, false); 328 // A8.6.97 MOV (register) -- Rd == r7|ip and Rm == sp 356 // A8.6.212 SUB (immediate, ARM) -- Rd == r7 and Rm == ip 359 // A8.6.215 SUB (SP minus immediate) -- Rd == ip 204 WriteCoreReg(Context &context, const uint32_t result, const uint32_t Rd) argument
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/freebsd-11-stable/contrib/llvm-project/compiler-rt/lib/xray/ |
H A D | xray_mips.cpp | 47 encodeSpecialInstruction(uint32_t Opcode, uint32_t Rs, uint32_t Rt, uint32_t Rd, 49 return (Rs << 21 | Rt << 16 | Rd << 11 | Imm << 6 | Opcode);
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H A D | xray_mips64.cpp | 48 encodeSpecialInstruction(uint32_t Opcode, uint32_t Rs, uint32_t Rt, uint32_t Rd, 50 return (Rs << 21 | Rt << 16 | Rd << 11 | Imm << 6 | Opcode);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/Disassembler/ |
H A D | ARMDisassembler.cpp | 2196 unsigned Rd = fieldFromInstruction(Insn, 12, 4); local 2204 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2422 unsigned Rd = fieldFromInstruction(Insn, 8, 4); local 2431 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 2433 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 2446 unsigned Rd = fieldFromInstruction(Insn, 12, 4); local 2454 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2457 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2473 unsigned Rd = fieldFromInstruction(Insn, 16, 4); local 2482 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Addres 2685 unsigned Rd = fieldFromInstruction(Insn, 12, 4); local 3012 unsigned Rd = fieldFromInstruction(Insn, 12, 4); local 3282 unsigned Rd = fieldFromInstruction(Insn, 12, 4); local 3329 unsigned Rd = fieldFromInstruction(Insn, 12, 4); local 3377 unsigned Rd = fieldFromInstruction(Insn, 12, 4); local 3412 unsigned Rd = fieldFromInstruction(Insn, 12, 4); local 3465 unsigned Rd = fieldFromInstruction(Insn, 12, 4); local 3564 unsigned Rd = fieldFromInstruction(Insn, 12, 4); local 3607 unsigned Rd = fieldFromInstruction(Insn, 12, 4); local 4773 unsigned Rd = fieldFromInstruction(Insn, 12, 4); local 4902 unsigned Rd = fieldFromInstruction(Insn, 12, 4); local 4969 unsigned Rd = fieldFromInstruction(Insn, 12, 4); local 5034 unsigned Rd = fieldFromInstruction(Insn, 12, 4); local 5101 unsigned Rd = fieldFromInstruction(Insn, 12, 4); local 5164 unsigned Rd = fieldFromInstruction(Insn, 12, 4); local 5234 unsigned Rd = fieldFromInstruction(Insn, 12, 4); local 5297 unsigned Rd = fieldFromInstruction(Insn, 12, 4); local 5378 unsigned Rd = fieldFromInstruction(Insn, 12, 4); local 5602 const unsigned Rd = fieldFromInstruction(Insn, 8, 4); local 6623 const unsigned Rd = fieldFromInstruction(Insn, 8, 4); local [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/RISCV/Disassembler/ |
H A D | RISCVDisassembler.cpp | 296 unsigned Rd = fieldFromInstruction(Insn, 7, 5); local 298 DecodeGPRRegisterClass(Inst, Rd, Address, Decoder); 306 unsigned Rd = fieldFromInstruction(Insn, 7, 5); local 308 DecodeGPRRegisterClass(Inst, Rd, Address, Decoder);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
H A D | HexagonConstExtenders.cpp | 325 Register Rd; member in struct:__anon2229::HexagonConstExtenders::ExtDesc 395 OffsetRange getOffsetRange(Register Rd) const; 498 if (ED.Rd.Reg != 0) 499 OS << printReg(ED.Rd.Reg, &HRI, ED.Rd.Sub); 1126 // Get the allowable deviation from the current value of Rd by checking 1127 // all uses of Rd. 1128 OffsetRange HCE::getOffsetRange(Register Rd) const { 1130 for (const MachineOperand &Op : MRI->use_operands(Rd.Reg)) { 1134 if (Rd ! [all...] |
H A D | HexagonFrameLowering.cpp | 143 // Rd = PS_alloca Rs, A 145 // Rd - address of the allocated space 2391 // Rd = alloca Rs, #A 2393 // If Rs and Rd are different registers, use this sequence: 2394 // Rd = sub(r29, Rs) 2396 // Rd = and(Rd, #-A) ; if necessary 2398 // Rd = add(Rd, #CF) ; CF size aligned to at most A 2400 // Rd 2407 unsigned Rd = RdOp.getReg(), Rs = RsOp.getReg(); local [all...] |
H A D | HexagonInstrInfo.cpp | 1234 Register Rd = Op0.getReg(); local 1242 if (Rd != Rs) 1243 BuildMI(MBB, MI, DL, get(Hexagon::A2_tfrpt), Rd) 1244 .addReg(Pu, (Rd == Rt) ? K1 : 0) 1246 if (Rd != Rt) 1247 BuildMI(MBB, MI, DL, get(Hexagon::A2_tfrpf), Rd) 3330 // Rd = Rs 3337 // Rd = #u6 3367 // Rd=#U6 ; jump #r9:2 3368 // Rd [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/MSP430/Disassembler/ |
H A D | MSP430Disassembler.cpp | 194 unsigned Rd = fieldFromInstruction(Insn, 0, 4); local 196 switch (Rd) {
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/AsmParser/ |
H A D | HexagonAsmParser.cpp | 1680 MCOperand &Rd = Inst.getOperand(0); local 1697 TmpInst.addOperand(Rd); 1711 if (Value == 0) { // convert to $Rd = $Rs 1713 MCOperand &Rd = Inst.getOperand(0); local 1715 TmpInst.addOperand(Rd); 1723 MCOperand &Rd = Inst.getOperand(0); local 1725 TmpInst.addOperand(Rd); 1911 MCOperand &Rd = Inst.getOperand(0); local 1914 TmpInst.addOperand(Rd);
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/freebsd-11-stable/contrib/binutils/gas/config/ |
H A D | tc-arm.c | 5161 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */ 5194 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>. 5284 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */ 5292 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */ 6584 inst.instruction |= (inst.operands[0].reg << 12); /* Rd */ 6601 inst.instruction |= (inst.operands[0].reg << 12); /* Rd */ 6816 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>} 6839 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>. 6849 Result unpredicatable if Rd or Rn is R15. */ 7091 as_tsktsk (_("Rd an 8428 int Rd, Rn; local 8444 int Rd, Rs, Rn; local 8669 int Rd, Rs, Rn; local 8752 int Rd, Rs, Rn; local 10125 int Rd, Rs; local [all...] |
/freebsd-11-stable/crypto/openssl/crypto/ec/asm/ |
H A D | ecp_nistz256-x86_64.pl | 1364 my ($ONE,$INDEX,$Ra,$Rb,$Rc,$Rd,$Re,$Rf)=map("%xmm$_",(0..7)); 1403 pxor $Rd, $Rd 1433 por $T0d, $Rd 1444 movdqu $Rd, 16*3($val) 1500 pxor $Rd, $Rd 1524 por $T0d, $Rd 1532 movdqu $Rd, 16*3($val)
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/freebsd-11-stable/contrib/llvm-project/lldb/source/Plugins/Instruction/ARM64/ |
H A D | EmulateInstructionARM64.cpp | 592 // integer d = UInt(Rd); 633 const uint32_t Rd = Bits32(opcode, 4, 0); local 637 const uint32_t d = UInt(Rd);
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/freebsd-11-stable/contrib/binutils/opcodes/ |
H A D | i386-dis.c | 226 #define Rd { OP_R, d_mode } macro 951 { "movL", { Rd, Td } }, 953 { "movL", { Td, Rd } },
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