1/* tc-arm.c -- Assemble for the ARM 2 Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 3 2004, 2005, 2006 4 Free Software Foundation, Inc. 5 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org) 6 Modified by David Taylor (dtaylor@armltd.co.uk) 7 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com) 8 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com) 9 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com) 10 11 This file is part of GAS, the GNU Assembler. 12 13 GAS is free software; you can redistribute it and/or modify 14 it under the terms of the GNU General Public License as published by 15 the Free Software Foundation; either version 2, or (at your option) 16 any later version. 17 18 GAS is distributed in the hope that it will be useful, 19 but WITHOUT ANY WARRANTY; without even the implied warranty of 20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 21 GNU General Public License for more details. 22 23 You should have received a copy of the GNU General Public License 24 along with GAS; see the file COPYING. If not, write to the Free 25 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 26 02110-1301, USA. */ 27 28#include <limits.h> 29#include <stdarg.h> 30#define NO_RELOC 0 31#include "as.h" 32#include "safe-ctype.h" 33#include "subsegs.h" 34#include "obstack.h" 35 36#include "opcode/arm.h" 37 38#ifdef OBJ_ELF 39#include "elf/arm.h" 40#include "dw2gencfi.h" 41#endif 42 43#include "dwarf2dbg.h" 44 45#define WARN_DEPRECATED 1 46 47#ifdef OBJ_ELF 48/* Must be at least the size of the largest unwind opcode (currently two). */ 49#define ARM_OPCODE_CHUNK_SIZE 8 50 51/* This structure holds the unwinding state. */ 52 53static struct 54{ 55 symbolS * proc_start; 56 symbolS * table_entry; 57 symbolS * personality_routine; 58 int personality_index; 59 /* The segment containing the function. */ 60 segT saved_seg; 61 subsegT saved_subseg; 62 /* Opcodes generated from this function. */ 63 unsigned char * opcodes; 64 int opcode_count; 65 int opcode_alloc; 66 /* The number of bytes pushed to the stack. */ 67 offsetT frame_size; 68 /* We don't add stack adjustment opcodes immediately so that we can merge 69 multiple adjustments. We can also omit the final adjustment 70 when using a frame pointer. */ 71 offsetT pending_offset; 72 /* These two fields are set by both unwind_movsp and unwind_setfp. They 73 hold the reg+offset to use when restoring sp from a frame pointer. */ 74 offsetT fp_offset; 75 int fp_reg; 76 /* Nonzero if an unwind_setfp directive has been seen. */ 77 unsigned fp_used:1; 78 /* Nonzero if the last opcode restores sp from fp_reg. */ 79 unsigned sp_restored:1; 80} unwind; 81 82/* Bit N indicates that an R_ARM_NONE relocation has been output for 83 __aeabi_unwind_cpp_prN already if set. This enables dependencies to be 84 emitted only once per section, to save unnecessary bloat. */ 85static unsigned int marked_pr_dependency = 0; 86 87#endif /* OBJ_ELF */ 88 89/* Results from operand parsing worker functions. */ 90 91typedef enum 92{ 93 PARSE_OPERAND_SUCCESS, 94 PARSE_OPERAND_FAIL, 95 PARSE_OPERAND_FAIL_NO_BACKTRACK 96} parse_operand_result; 97 98enum arm_float_abi 99{ 100 ARM_FLOAT_ABI_HARD, 101 ARM_FLOAT_ABI_SOFTFP, 102 ARM_FLOAT_ABI_SOFT 103}; 104 105/* Types of processor to assemble for. */ 106#ifndef CPU_DEFAULT 107#if defined __XSCALE__ 108#define CPU_DEFAULT ARM_ARCH_XSCALE 109#else 110#if defined __thumb__ 111#define CPU_DEFAULT ARM_ARCH_V5T 112#endif 113#endif 114#endif 115 116#ifndef FPU_DEFAULT 117# ifdef TE_LINUX 118# define FPU_DEFAULT FPU_ARCH_FPA 119# elif defined (TE_NetBSD) 120# ifdef OBJ_ELF 121# define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */ 122# else 123 /* Legacy a.out format. */ 124# define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */ 125# endif 126# elif defined (TE_VXWORKS) 127# define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */ 128# else 129 /* For backwards compatibility, default to FPA. */ 130# define FPU_DEFAULT FPU_ARCH_FPA 131# endif 132#endif /* ifndef FPU_DEFAULT */ 133 134#define streq(a, b) (strcmp (a, b) == 0) 135 136static arm_feature_set cpu_variant; 137static arm_feature_set arm_arch_used; 138static arm_feature_set thumb_arch_used; 139 140/* Flags stored in private area of BFD structure. */ 141static int uses_apcs_26 = FALSE; 142static int atpcs = FALSE; 143static int support_interwork = FALSE; 144static int uses_apcs_float = FALSE; 145static int pic_code = FALSE; 146 147/* Variables that we set while parsing command-line options. Once all 148 options have been read we re-process these values to set the real 149 assembly flags. */ 150static const arm_feature_set *legacy_cpu = NULL; 151static const arm_feature_set *legacy_fpu = NULL; 152 153static const arm_feature_set *mcpu_cpu_opt = NULL; 154static const arm_feature_set *mcpu_fpu_opt = NULL; 155static const arm_feature_set *march_cpu_opt = NULL; 156static const arm_feature_set *march_fpu_opt = NULL; 157static const arm_feature_set *mfpu_opt = NULL; 158static const arm_feature_set *object_arch = NULL; 159 160/* Constants for known architecture features. */ 161static const arm_feature_set fpu_default = FPU_DEFAULT; 162static const arm_feature_set fpu_arch_vfp_v1 = FPU_ARCH_VFP_V1; 163static const arm_feature_set fpu_arch_vfp_v2 = FPU_ARCH_VFP_V2; 164static const arm_feature_set fpu_arch_vfp_v3 = FPU_ARCH_VFP_V3; 165static const arm_feature_set fpu_arch_neon_v1 = FPU_ARCH_NEON_V1; 166static const arm_feature_set fpu_arch_fpa = FPU_ARCH_FPA; 167static const arm_feature_set fpu_any_hard = FPU_ANY_HARD; 168static const arm_feature_set fpu_arch_maverick = FPU_ARCH_MAVERICK; 169static const arm_feature_set fpu_endian_pure = FPU_ARCH_ENDIAN_PURE; 170 171#ifdef CPU_DEFAULT 172static const arm_feature_set cpu_default = CPU_DEFAULT; 173#endif 174 175static const arm_feature_set arm_ext_v1 = ARM_FEATURE (ARM_EXT_V1, 0); 176static const arm_feature_set arm_ext_v2 = ARM_FEATURE (ARM_EXT_V1, 0); 177static const arm_feature_set arm_ext_v2s = ARM_FEATURE (ARM_EXT_V2S, 0); 178static const arm_feature_set arm_ext_v3 = ARM_FEATURE (ARM_EXT_V3, 0); 179static const arm_feature_set arm_ext_v3m = ARM_FEATURE (ARM_EXT_V3M, 0); 180static const arm_feature_set arm_ext_v4 = ARM_FEATURE (ARM_EXT_V4, 0); 181static const arm_feature_set arm_ext_v4t = ARM_FEATURE (ARM_EXT_V4T, 0); 182static const arm_feature_set arm_ext_v5 = ARM_FEATURE (ARM_EXT_V5, 0); 183static const arm_feature_set arm_ext_v4t_5 = 184 ARM_FEATURE (ARM_EXT_V4T | ARM_EXT_V5, 0); 185static const arm_feature_set arm_ext_v5t = ARM_FEATURE (ARM_EXT_V5T, 0); 186static const arm_feature_set arm_ext_v5e = ARM_FEATURE (ARM_EXT_V5E, 0); 187static const arm_feature_set arm_ext_v5exp = ARM_FEATURE (ARM_EXT_V5ExP, 0); 188static const arm_feature_set arm_ext_v5j = ARM_FEATURE (ARM_EXT_V5J, 0); 189static const arm_feature_set arm_ext_v6 = ARM_FEATURE (ARM_EXT_V6, 0); 190static const arm_feature_set arm_ext_v6k = ARM_FEATURE (ARM_EXT_V6K, 0); 191static const arm_feature_set arm_ext_v6z = ARM_FEATURE (ARM_EXT_V6Z, 0); 192static const arm_feature_set arm_ext_v6t2 = ARM_FEATURE (ARM_EXT_V6T2, 0); 193static const arm_feature_set arm_ext_v6_notm = ARM_FEATURE (ARM_EXT_V6_NOTM, 0); 194static const arm_feature_set arm_ext_div = ARM_FEATURE (ARM_EXT_DIV, 0); 195static const arm_feature_set arm_ext_v7 = ARM_FEATURE (ARM_EXT_V7, 0); 196static const arm_feature_set arm_ext_v7a = ARM_FEATURE (ARM_EXT_V7A, 0); 197static const arm_feature_set arm_ext_v7r = ARM_FEATURE (ARM_EXT_V7R, 0); 198static const arm_feature_set arm_ext_v7m = ARM_FEATURE (ARM_EXT_V7M, 0); 199 200static const arm_feature_set arm_arch_any = ARM_ANY; 201static const arm_feature_set arm_arch_full = ARM_FEATURE (-1, -1); 202static const arm_feature_set arm_arch_t2 = ARM_ARCH_THUMB2; 203static const arm_feature_set arm_arch_none = ARM_ARCH_NONE; 204 205static const arm_feature_set arm_cext_iwmmxt2 = 206 ARM_FEATURE (0, ARM_CEXT_IWMMXT2); 207static const arm_feature_set arm_cext_iwmmxt = 208 ARM_FEATURE (0, ARM_CEXT_IWMMXT); 209static const arm_feature_set arm_cext_xscale = 210 ARM_FEATURE (0, ARM_CEXT_XSCALE); 211static const arm_feature_set arm_cext_maverick = 212 ARM_FEATURE (0, ARM_CEXT_MAVERICK); 213static const arm_feature_set fpu_fpa_ext_v1 = ARM_FEATURE (0, FPU_FPA_EXT_V1); 214static const arm_feature_set fpu_fpa_ext_v2 = ARM_FEATURE (0, FPU_FPA_EXT_V2); 215static const arm_feature_set fpu_vfp_ext_v1xd = 216 ARM_FEATURE (0, FPU_VFP_EXT_V1xD); 217static const arm_feature_set fpu_vfp_ext_v1 = ARM_FEATURE (0, FPU_VFP_EXT_V1); 218static const arm_feature_set fpu_vfp_ext_v2 = ARM_FEATURE (0, FPU_VFP_EXT_V2); 219static const arm_feature_set fpu_vfp_ext_v3 = ARM_FEATURE (0, FPU_VFP_EXT_V3); 220static const arm_feature_set fpu_neon_ext_v1 = ARM_FEATURE (0, FPU_NEON_EXT_V1); 221static const arm_feature_set fpu_vfp_v3_or_neon_ext = 222 ARM_FEATURE (0, FPU_NEON_EXT_V1 | FPU_VFP_EXT_V3); 223 224static int mfloat_abi_opt = -1; 225/* Record user cpu selection for object attributes. */ 226static arm_feature_set selected_cpu = ARM_ARCH_NONE; 227/* Must be long enough to hold any of the names in arm_cpus. */ 228static char selected_cpu_name[16]; 229#ifdef OBJ_ELF 230# ifdef EABI_DEFAULT 231static int meabi_flags = EABI_DEFAULT; 232# else 233static int meabi_flags = EF_ARM_EABI_UNKNOWN; 234# endif 235 236bfd_boolean 237arm_is_eabi(void) 238{ 239 return (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4); 240} 241#endif 242 243#ifdef OBJ_ELF 244/* Pre-defined "_GLOBAL_OFFSET_TABLE_" */ 245symbolS * GOT_symbol; 246#endif 247 248/* 0: assemble for ARM, 249 1: assemble for Thumb, 250 2: assemble for Thumb even though target CPU does not support thumb 251 instructions. */ 252static int thumb_mode = 0; 253 254/* If unified_syntax is true, we are processing the new unified 255 ARM/Thumb syntax. Important differences from the old ARM mode: 256 257 - Immediate operands do not require a # prefix. 258 - Conditional affixes always appear at the end of the 259 instruction. (For backward compatibility, those instructions 260 that formerly had them in the middle, continue to accept them 261 there.) 262 - The IT instruction may appear, and if it does is validated 263 against subsequent conditional affixes. It does not generate 264 machine code. 265 266 Important differences from the old Thumb mode: 267 268 - Immediate operands do not require a # prefix. 269 - Most of the V6T2 instructions are only available in unified mode. 270 - The .N and .W suffixes are recognized and honored (it is an error 271 if they cannot be honored). 272 - All instructions set the flags if and only if they have an 's' affix. 273 - Conditional affixes may be used. They are validated against 274 preceding IT instructions. Unlike ARM mode, you cannot use a 275 conditional affix except in the scope of an IT instruction. */ 276 277static bfd_boolean unified_syntax = FALSE; 278 279enum neon_el_type 280{ 281 NT_invtype, 282 NT_untyped, 283 NT_integer, 284 NT_float, 285 NT_poly, 286 NT_signed, 287 NT_unsigned 288}; 289 290struct neon_type_el 291{ 292 enum neon_el_type type; 293 unsigned size; 294}; 295 296#define NEON_MAX_TYPE_ELS 4 297 298struct neon_type 299{ 300 struct neon_type_el el[NEON_MAX_TYPE_ELS]; 301 unsigned elems; 302}; 303 304struct arm_it 305{ 306 const char * error; 307 unsigned long instruction; 308 int size; 309 int size_req; 310 int cond; 311 /* "uncond_value" is set to the value in place of the conditional field in 312 unconditional versions of the instruction, or -1 if nothing is 313 appropriate. */ 314 int uncond_value; 315 struct neon_type vectype; 316 /* Set to the opcode if the instruction needs relaxation. 317 Zero if the instruction is not relaxed. */ 318 unsigned long relax; 319 struct 320 { 321 bfd_reloc_code_real_type type; 322 expressionS exp; 323 int pc_rel; 324 } reloc; 325 326 struct 327 { 328 unsigned reg; 329 signed int imm; 330 struct neon_type_el vectype; 331 unsigned present : 1; /* Operand present. */ 332 unsigned isreg : 1; /* Operand was a register. */ 333 unsigned immisreg : 1; /* .imm field is a second register. */ 334 unsigned isscalar : 1; /* Operand is a (Neon) scalar. */ 335 unsigned immisalign : 1; /* Immediate is an alignment specifier. */ 336 unsigned immisfloat : 1; /* Immediate was parsed as a float. */ 337 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV 338 instructions. This allows us to disambiguate ARM <-> vector insns. */ 339 unsigned regisimm : 1; /* 64-bit immediate, reg forms high 32 bits. */ 340 unsigned isvec : 1; /* Is a single, double or quad VFP/Neon reg. */ 341 unsigned isquad : 1; /* Operand is Neon quad-precision register. */ 342 unsigned issingle : 1; /* Operand is VFP single-precision register. */ 343 unsigned hasreloc : 1; /* Operand has relocation suffix. */ 344 unsigned writeback : 1; /* Operand has trailing ! */ 345 unsigned preind : 1; /* Preindexed address. */ 346 unsigned postind : 1; /* Postindexed address. */ 347 unsigned negative : 1; /* Index register was negated. */ 348 unsigned shifted : 1; /* Shift applied to operation. */ 349 unsigned shift_kind : 3; /* Shift operation (enum shift_kind). */ 350 } operands[6]; 351}; 352 353static struct arm_it inst; 354 355#define NUM_FLOAT_VALS 8 356 357const char * fp_const[] = 358{ 359 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0 360}; 361 362/* Number of littlenums required to hold an extended precision number. */ 363#define MAX_LITTLENUMS 6 364 365LITTLENUM_TYPE fp_values[NUM_FLOAT_VALS][MAX_LITTLENUMS]; 366 367#define FAIL (-1) 368#define SUCCESS (0) 369 370#define SUFF_S 1 371#define SUFF_D 2 372#define SUFF_E 3 373#define SUFF_P 4 374 375#define CP_T_X 0x00008000 376#define CP_T_Y 0x00400000 377 378#define CONDS_BIT 0x00100000 379#define LOAD_BIT 0x00100000 380 381#define DOUBLE_LOAD_FLAG 0x00000001 382 383struct asm_cond 384{ 385 const char * template; 386 unsigned long value; 387}; 388 389#define COND_ALWAYS 0xE 390 391struct asm_psr 392{ 393 const char *template; 394 unsigned long field; 395}; 396 397struct asm_barrier_opt 398{ 399 const char *template; 400 unsigned long value; 401}; 402 403/* The bit that distinguishes CPSR and SPSR. */ 404#define SPSR_BIT (1 << 22) 405 406/* The individual PSR flag bits. */ 407#define PSR_c (1 << 16) 408#define PSR_x (1 << 17) 409#define PSR_s (1 << 18) 410#define PSR_f (1 << 19) 411 412struct reloc_entry 413{ 414 char *name; 415 bfd_reloc_code_real_type reloc; 416}; 417 418enum vfp_reg_pos 419{ 420 VFP_REG_Sd, VFP_REG_Sm, VFP_REG_Sn, 421 VFP_REG_Dd, VFP_REG_Dm, VFP_REG_Dn 422}; 423 424enum vfp_ldstm_type 425{ 426 VFP_LDSTMIA, VFP_LDSTMDB, VFP_LDSTMIAX, VFP_LDSTMDBX 427}; 428 429/* Bits for DEFINED field in neon_typed_alias. */ 430#define NTA_HASTYPE 1 431#define NTA_HASINDEX 2 432 433struct neon_typed_alias 434{ 435 unsigned char defined; 436 unsigned char index; 437 struct neon_type_el eltype; 438}; 439 440/* ARM register categories. This includes coprocessor numbers and various 441 architecture extensions' registers. */ 442enum arm_reg_type 443{ 444 REG_TYPE_RN, 445 REG_TYPE_CP, 446 REG_TYPE_CN, 447 REG_TYPE_FN, 448 REG_TYPE_VFS, 449 REG_TYPE_VFD, 450 REG_TYPE_NQ, 451 REG_TYPE_VFSD, 452 REG_TYPE_NDQ, 453 REG_TYPE_NSDQ, 454 REG_TYPE_VFC, 455 REG_TYPE_MVF, 456 REG_TYPE_MVD, 457 REG_TYPE_MVFX, 458 REG_TYPE_MVDX, 459 REG_TYPE_MVAX, 460 REG_TYPE_DSPSC, 461 REG_TYPE_MMXWR, 462 REG_TYPE_MMXWC, 463 REG_TYPE_MMXWCG, 464 REG_TYPE_XSCALE, 465}; 466 467/* Structure for a hash table entry for a register. 468 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra 469 information which states whether a vector type or index is specified (for a 470 register alias created with .dn or .qn). Otherwise NEON should be NULL. */ 471struct reg_entry 472{ 473 const char *name; 474 unsigned char number; 475 unsigned char type; 476 unsigned char builtin; 477 struct neon_typed_alias *neon; 478}; 479 480/* Diagnostics used when we don't get a register of the expected type. */ 481const char *const reg_expected_msgs[] = 482{ 483 N_("ARM register expected"), 484 N_("bad or missing co-processor number"), 485 N_("co-processor register expected"), 486 N_("FPA register expected"), 487 N_("VFP single precision register expected"), 488 N_("VFP/Neon double precision register expected"), 489 N_("Neon quad precision register expected"), 490 N_("VFP single or double precision register expected"), 491 N_("Neon double or quad precision register expected"), 492 N_("VFP single, double or Neon quad precision register expected"), 493 N_("VFP system register expected"), 494 N_("Maverick MVF register expected"), 495 N_("Maverick MVD register expected"), 496 N_("Maverick MVFX register expected"), 497 N_("Maverick MVDX register expected"), 498 N_("Maverick MVAX register expected"), 499 N_("Maverick DSPSC register expected"), 500 N_("iWMMXt data register expected"), 501 N_("iWMMXt control register expected"), 502 N_("iWMMXt scalar register expected"), 503 N_("XScale accumulator register expected"), 504}; 505 506/* Some well known registers that we refer to directly elsewhere. */ 507#define REG_SP 13 508#define REG_LR 14 509#define REG_PC 15 510 511/* ARM instructions take 4bytes in the object file, Thumb instructions 512 take 2: */ 513#define INSN_SIZE 4 514 515struct asm_opcode 516{ 517 /* Basic string to match. */ 518 const char *template; 519 520 /* Parameters to instruction. */ 521 unsigned char operands[8]; 522 523 /* Conditional tag - see opcode_lookup. */ 524 unsigned int tag : 4; 525 526 /* Basic instruction code. */ 527 unsigned int avalue : 28; 528 529 /* Thumb-format instruction code. */ 530 unsigned int tvalue; 531 532 /* Which architecture variant provides this instruction. */ 533 const arm_feature_set *avariant; 534 const arm_feature_set *tvariant; 535 536 /* Function to call to encode instruction in ARM format. */ 537 void (* aencode) (void); 538 539 /* Function to call to encode instruction in Thumb format. */ 540 void (* tencode) (void); 541}; 542 543/* Defines for various bits that we will want to toggle. */ 544#define INST_IMMEDIATE 0x02000000 545#define OFFSET_REG 0x02000000 546#define HWOFFSET_IMM 0x00400000 547#define SHIFT_BY_REG 0x00000010 548#define PRE_INDEX 0x01000000 549#define INDEX_UP 0x00800000 550#define WRITE_BACK 0x00200000 551#define LDM_TYPE_2_OR_3 0x00400000 552#define CPSI_MMOD 0x00020000 553 554#define LITERAL_MASK 0xf000f000 555#define OPCODE_MASK 0xfe1fffff 556#define V4_STR_BIT 0x00000020 557 558#define T2_SUBS_PC_LR 0xf3de8f00 559 560#define DATA_OP_SHIFT 21 561 562#define T2_OPCODE_MASK 0xfe1fffff 563#define T2_DATA_OP_SHIFT 21 564 565/* Codes to distinguish the arithmetic instructions. */ 566#define OPCODE_AND 0 567#define OPCODE_EOR 1 568#define OPCODE_SUB 2 569#define OPCODE_RSB 3 570#define OPCODE_ADD 4 571#define OPCODE_ADC 5 572#define OPCODE_SBC 6 573#define OPCODE_RSC 7 574#define OPCODE_TST 8 575#define OPCODE_TEQ 9 576#define OPCODE_CMP 10 577#define OPCODE_CMN 11 578#define OPCODE_ORR 12 579#define OPCODE_MOV 13 580#define OPCODE_BIC 14 581#define OPCODE_MVN 15 582 583#define T2_OPCODE_AND 0 584#define T2_OPCODE_BIC 1 585#define T2_OPCODE_ORR 2 586#define T2_OPCODE_ORN 3 587#define T2_OPCODE_EOR 4 588#define T2_OPCODE_ADD 8 589#define T2_OPCODE_ADC 10 590#define T2_OPCODE_SBC 11 591#define T2_OPCODE_SUB 13 592#define T2_OPCODE_RSB 14 593 594#define T_OPCODE_MUL 0x4340 595#define T_OPCODE_TST 0x4200 596#define T_OPCODE_CMN 0x42c0 597#define T_OPCODE_NEG 0x4240 598#define T_OPCODE_MVN 0x43c0 599 600#define T_OPCODE_ADD_R3 0x1800 601#define T_OPCODE_SUB_R3 0x1a00 602#define T_OPCODE_ADD_HI 0x4400 603#define T_OPCODE_ADD_ST 0xb000 604#define T_OPCODE_SUB_ST 0xb080 605#define T_OPCODE_ADD_SP 0xa800 606#define T_OPCODE_ADD_PC 0xa000 607#define T_OPCODE_ADD_I8 0x3000 608#define T_OPCODE_SUB_I8 0x3800 609#define T_OPCODE_ADD_I3 0x1c00 610#define T_OPCODE_SUB_I3 0x1e00 611 612#define T_OPCODE_ASR_R 0x4100 613#define T_OPCODE_LSL_R 0x4080 614#define T_OPCODE_LSR_R 0x40c0 615#define T_OPCODE_ROR_R 0x41c0 616#define T_OPCODE_ASR_I 0x1000 617#define T_OPCODE_LSL_I 0x0000 618#define T_OPCODE_LSR_I 0x0800 619 620#define T_OPCODE_MOV_I8 0x2000 621#define T_OPCODE_CMP_I8 0x2800 622#define T_OPCODE_CMP_LR 0x4280 623#define T_OPCODE_MOV_HR 0x4600 624#define T_OPCODE_CMP_HR 0x4500 625 626#define T_OPCODE_LDR_PC 0x4800 627#define T_OPCODE_LDR_SP 0x9800 628#define T_OPCODE_STR_SP 0x9000 629#define T_OPCODE_LDR_IW 0x6800 630#define T_OPCODE_STR_IW 0x6000 631#define T_OPCODE_LDR_IH 0x8800 632#define T_OPCODE_STR_IH 0x8000 633#define T_OPCODE_LDR_IB 0x7800 634#define T_OPCODE_STR_IB 0x7000 635#define T_OPCODE_LDR_RW 0x5800 636#define T_OPCODE_STR_RW 0x5000 637#define T_OPCODE_LDR_RH 0x5a00 638#define T_OPCODE_STR_RH 0x5200 639#define T_OPCODE_LDR_RB 0x5c00 640#define T_OPCODE_STR_RB 0x5400 641 642#define T_OPCODE_PUSH 0xb400 643#define T_OPCODE_POP 0xbc00 644 645#define T_OPCODE_BRANCH 0xe000 646 647#define THUMB_SIZE 2 /* Size of thumb instruction. */ 648#define THUMB_PP_PC_LR 0x0100 649#define THUMB_LOAD_BIT 0x0800 650#define THUMB2_LOAD_BIT 0x00100000 651 652#define BAD_ARGS _("bad arguments to instruction") 653#define BAD_PC _("r15 not allowed here") 654#define BAD_SP _("r13 not allowed here") 655#define BAD_COND _("instruction cannot be conditional") 656#define BAD_OVERLAP _("registers may not be the same") 657#define BAD_HIREG _("lo register required") 658#define BAD_THUMB32 _("instruction not supported in Thumb16 mode") 659#define BAD_ADDR_MODE _("instruction does not accept this addressing mode"); 660#define BAD_BRANCH _("branch must be last instruction in IT block") 661#define BAD_NOT_IT _("instruction not allowed in IT block") 662#define BAD_FPU _("selected FPU does not support instruction") 663#define BAD_VMRS _("APSR_nzcv may only be used with fpscr") 664 665static struct hash_control *arm_ops_hsh; 666static struct hash_control *arm_cond_hsh; 667static struct hash_control *arm_shift_hsh; 668static struct hash_control *arm_psr_hsh; 669static struct hash_control *arm_v7m_psr_hsh; 670static struct hash_control *arm_reg_hsh; 671static struct hash_control *arm_reloc_hsh; 672static struct hash_control *arm_barrier_opt_hsh; 673 674/* Stuff needed to resolve the label ambiguity 675 As: 676 ... 677 label: <insn> 678 may differ from: 679 ... 680 label: 681 <insn> 682*/ 683 684symbolS * last_label_seen; 685static int label_is_thumb_function_name = FALSE; 686 687/* Literal pool structure. Held on a per-section 688 and per-sub-section basis. */ 689 690#define MAX_LITERAL_POOL_SIZE 1024 691typedef struct literal_pool 692{ 693 expressionS literals [MAX_LITERAL_POOL_SIZE]; 694 unsigned int next_free_entry; 695 unsigned int id; 696 symbolS * symbol; 697 segT section; 698 subsegT sub_section; 699 struct literal_pool * next; 700} literal_pool; 701 702/* Pointer to a linked list of literal pools. */ 703literal_pool * list_of_pools = NULL; 704 705/* State variables for IT block handling. */ 706static bfd_boolean current_it_mask = 0; 707static int current_cc; 708 709 710/* Pure syntax. */ 711 712/* This array holds the chars that always start a comment. If the 713 pre-processor is disabled, these aren't very useful. */ 714const char comment_chars[] = "@"; 715 716/* This array holds the chars that only start a comment at the beginning of 717 a line. If the line seems to have the form '# 123 filename' 718 .line and .file directives will appear in the pre-processed output. */ 719/* Note that input_file.c hand checks for '#' at the beginning of the 720 first line of the input file. This is because the compiler outputs 721 #NO_APP at the beginning of its output. */ 722/* Also note that comments like this one will always work. */ 723const char line_comment_chars[] = "#"; 724 725const char line_separator_chars[] = ";"; 726 727/* Chars that can be used to separate mant 728 from exp in floating point numbers. */ 729const char EXP_CHARS[] = "eE"; 730 731/* Chars that mean this number is a floating point constant. */ 732/* As in 0f12.456 */ 733/* or 0d1.2345e12 */ 734 735const char FLT_CHARS[] = "rRsSfFdDxXeEpP"; 736 737/* Prefix characters that indicate the start of an immediate 738 value. */ 739#define is_immediate_prefix(C) ((C) == '#' || (C) == '$') 740 741/* Separator character handling. */ 742 743#define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0) 744 745static inline int 746skip_past_char (char ** str, char c) 747{ 748 if (**str == c) 749 { 750 (*str)++; 751 return SUCCESS; 752 } 753 else 754 return FAIL; 755} 756#define skip_past_comma(str) skip_past_char (str, ',') 757 758/* Arithmetic expressions (possibly involving symbols). */ 759 760/* Return TRUE if anything in the expression is a bignum. */ 761 762static int 763walk_no_bignums (symbolS * sp) 764{ 765 if (symbol_get_value_expression (sp)->X_op == O_big) 766 return 1; 767 768 if (symbol_get_value_expression (sp)->X_add_symbol) 769 { 770 return (walk_no_bignums (symbol_get_value_expression (sp)->X_add_symbol) 771 || (symbol_get_value_expression (sp)->X_op_symbol 772 && walk_no_bignums (symbol_get_value_expression (sp)->X_op_symbol))); 773 } 774 775 return 0; 776} 777 778static int in_my_get_expression = 0; 779 780/* Third argument to my_get_expression. */ 781#define GE_NO_PREFIX 0 782#define GE_IMM_PREFIX 1 783#define GE_OPT_PREFIX 2 784/* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit) 785 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */ 786#define GE_OPT_PREFIX_BIG 3 787 788static int 789my_get_expression (expressionS * ep, char ** str, int prefix_mode) 790{ 791 char * save_in; 792 segT seg; 793 794 /* In unified syntax, all prefixes are optional. */ 795 if (unified_syntax) 796 prefix_mode = (prefix_mode == GE_OPT_PREFIX_BIG) ? prefix_mode 797 : GE_OPT_PREFIX; 798 799 switch (prefix_mode) 800 { 801 case GE_NO_PREFIX: break; 802 case GE_IMM_PREFIX: 803 if (!is_immediate_prefix (**str)) 804 { 805 inst.error = _("immediate expression requires a # prefix"); 806 return FAIL; 807 } 808 (*str)++; 809 break; 810 case GE_OPT_PREFIX: 811 case GE_OPT_PREFIX_BIG: 812 if (is_immediate_prefix (**str)) 813 (*str)++; 814 break; 815 default: abort (); 816 } 817 818 memset (ep, 0, sizeof (expressionS)); 819 820 save_in = input_line_pointer; 821 input_line_pointer = *str; 822 in_my_get_expression = 1; 823 seg = expression (ep); 824 in_my_get_expression = 0; 825 826 if (ep->X_op == O_illegal) 827 { 828 /* We found a bad expression in md_operand(). */ 829 *str = input_line_pointer; 830 input_line_pointer = save_in; 831 if (inst.error == NULL) 832 inst.error = _("bad expression"); 833 return 1; 834 } 835 836#ifdef OBJ_AOUT 837 if (seg != absolute_section 838 && seg != text_section 839 && seg != data_section 840 && seg != bss_section 841 && seg != undefined_section) 842 { 843 inst.error = _("bad segment"); 844 *str = input_line_pointer; 845 input_line_pointer = save_in; 846 return 1; 847 } 848#endif 849 850 /* Get rid of any bignums now, so that we don't generate an error for which 851 we can't establish a line number later on. Big numbers are never valid 852 in instructions, which is where this routine is always called. */ 853 if (prefix_mode != GE_OPT_PREFIX_BIG 854 && (ep->X_op == O_big 855 || (ep->X_add_symbol 856 && (walk_no_bignums (ep->X_add_symbol) 857 || (ep->X_op_symbol 858 && walk_no_bignums (ep->X_op_symbol)))))) 859 { 860 inst.error = _("invalid constant"); 861 *str = input_line_pointer; 862 input_line_pointer = save_in; 863 return 1; 864 } 865 866 *str = input_line_pointer; 867 input_line_pointer = save_in; 868 return 0; 869} 870 871/* Turn a string in input_line_pointer into a floating point constant 872 of type TYPE, and store the appropriate bytes in *LITP. The number 873 of LITTLENUMS emitted is stored in *SIZEP. An error message is 874 returned, or NULL on OK. 875 876 Note that fp constants aren't represent in the normal way on the ARM. 877 In big endian mode, things are as expected. However, in little endian 878 mode fp constants are big-endian word-wise, and little-endian byte-wise 879 within the words. For example, (double) 1.1 in big endian mode is 880 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is 881 the byte sequence 99 99 f1 3f 9a 99 99 99. 882 883 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */ 884 885char * 886md_atof (int type, char * litP, int * sizeP) 887{ 888 int prec; 889 LITTLENUM_TYPE words[MAX_LITTLENUMS]; 890 char *t; 891 int i; 892 893 switch (type) 894 { 895 case 'f': 896 case 'F': 897 case 's': 898 case 'S': 899 prec = 2; 900 break; 901 902 case 'd': 903 case 'D': 904 case 'r': 905 case 'R': 906 prec = 4; 907 break; 908 909 case 'x': 910 case 'X': 911 prec = 6; 912 break; 913 914 case 'p': 915 case 'P': 916 prec = 6; 917 break; 918 919 default: 920 *sizeP = 0; 921 return _("bad call to MD_ATOF()"); 922 } 923 924 t = atof_ieee (input_line_pointer, type, words); 925 if (t) 926 input_line_pointer = t; 927 *sizeP = prec * 2; 928 929 if (target_big_endian) 930 { 931 for (i = 0; i < prec; i++) 932 { 933 md_number_to_chars (litP, (valueT) words[i], 2); 934 litP += 2; 935 } 936 } 937 else 938 { 939 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_endian_pure)) 940 for (i = prec - 1; i >= 0; i--) 941 { 942 md_number_to_chars (litP, (valueT) words[i], 2); 943 litP += 2; 944 } 945 else 946 /* For a 4 byte float the order of elements in `words' is 1 0. 947 For an 8 byte float the order is 1 0 3 2. */ 948 for (i = 0; i < prec; i += 2) 949 { 950 md_number_to_chars (litP, (valueT) words[i + 1], 2); 951 md_number_to_chars (litP + 2, (valueT) words[i], 2); 952 litP += 4; 953 } 954 } 955 956 return 0; 957} 958 959/* We handle all bad expressions here, so that we can report the faulty 960 instruction in the error message. */ 961void 962md_operand (expressionS * expr) 963{ 964 if (in_my_get_expression) 965 expr->X_op = O_illegal; 966} 967 968/* Immediate values. */ 969 970/* Generic immediate-value read function for use in directives. 971 Accepts anything that 'expression' can fold to a constant. 972 *val receives the number. */ 973#ifdef OBJ_ELF 974static int 975immediate_for_directive (int *val) 976{ 977 expressionS exp; 978 exp.X_op = O_illegal; 979 980 if (is_immediate_prefix (*input_line_pointer)) 981 { 982 input_line_pointer++; 983 expression (&exp); 984 } 985 986 if (exp.X_op != O_constant) 987 { 988 as_bad (_("expected #constant")); 989 ignore_rest_of_line (); 990 return FAIL; 991 } 992 *val = exp.X_add_number; 993 return SUCCESS; 994} 995#endif 996 997/* Register parsing. */ 998 999/* Generic register parser. CCP points to what should be the 1000 beginning of a register name. If it is indeed a valid register 1001 name, advance CCP over it and return the reg_entry structure; 1002 otherwise return NULL. Does not issue diagnostics. */ 1003 1004static struct reg_entry * 1005arm_reg_parse_multi (char **ccp) 1006{ 1007 char *start = *ccp; 1008 char *p; 1009 struct reg_entry *reg; 1010 1011#ifdef REGISTER_PREFIX 1012 if (*start != REGISTER_PREFIX) 1013 return NULL; 1014 start++; 1015#endif 1016#ifdef OPTIONAL_REGISTER_PREFIX 1017 if (*start == OPTIONAL_REGISTER_PREFIX) 1018 start++; 1019#endif 1020 1021 p = start; 1022 if (!ISALPHA (*p) || !is_name_beginner (*p)) 1023 return NULL; 1024 1025 do 1026 p++; 1027 while (ISALPHA (*p) || ISDIGIT (*p) || *p == '_'); 1028 1029 reg = (struct reg_entry *) hash_find_n (arm_reg_hsh, start, p - start); 1030 1031 if (!reg) 1032 return NULL; 1033 1034 *ccp = p; 1035 return reg; 1036} 1037 1038static int 1039arm_reg_alt_syntax (char **ccp, char *start, struct reg_entry *reg, 1040 enum arm_reg_type type) 1041{ 1042 /* Alternative syntaxes are accepted for a few register classes. */ 1043 switch (type) 1044 { 1045 case REG_TYPE_MVF: 1046 case REG_TYPE_MVD: 1047 case REG_TYPE_MVFX: 1048 case REG_TYPE_MVDX: 1049 /* Generic coprocessor register names are allowed for these. */ 1050 if (reg && reg->type == REG_TYPE_CN) 1051 return reg->number; 1052 break; 1053 1054 case REG_TYPE_CP: 1055 /* For backward compatibility, a bare number is valid here. */ 1056 { 1057 unsigned long processor = strtoul (start, ccp, 10); 1058 if (*ccp != start && processor <= 15) 1059 return processor; 1060 } 1061 1062 case REG_TYPE_MMXWC: 1063 /* WC includes WCG. ??? I'm not sure this is true for all 1064 instructions that take WC registers. */ 1065 if (reg && reg->type == REG_TYPE_MMXWCG) 1066 return reg->number; 1067 break; 1068 1069 default: 1070 break; 1071 } 1072 1073 return FAIL; 1074} 1075 1076/* As arm_reg_parse_multi, but the register must be of type TYPE, and the 1077 return value is the register number or FAIL. */ 1078 1079static int 1080arm_reg_parse (char **ccp, enum arm_reg_type type) 1081{ 1082 char *start = *ccp; 1083 struct reg_entry *reg = arm_reg_parse_multi (ccp); 1084 int ret; 1085 1086 /* Do not allow a scalar (reg+index) to parse as a register. */ 1087 if (reg && reg->neon && (reg->neon->defined & NTA_HASINDEX)) 1088 return FAIL; 1089 1090 if (reg && reg->type == type) 1091 return reg->number; 1092 1093 if ((ret = arm_reg_alt_syntax (ccp, start, reg, type)) != FAIL) 1094 return ret; 1095 1096 *ccp = start; 1097 return FAIL; 1098} 1099 1100/* Parse a Neon type specifier. *STR should point at the leading '.' 1101 character. Does no verification at this stage that the type fits the opcode 1102 properly. E.g., 1103 1104 .i32.i32.s16 1105 .s32.f32 1106 .u16 1107 1108 Can all be legally parsed by this function. 1109 1110 Fills in neon_type struct pointer with parsed information, and updates STR 1111 to point after the parsed type specifier. Returns SUCCESS if this was a legal 1112 type, FAIL if not. */ 1113 1114static int 1115parse_neon_type (struct neon_type *type, char **str) 1116{ 1117 char *ptr = *str; 1118 1119 if (type) 1120 type->elems = 0; 1121 1122 while (type->elems < NEON_MAX_TYPE_ELS) 1123 { 1124 enum neon_el_type thistype = NT_untyped; 1125 unsigned thissize = -1u; 1126 1127 if (*ptr != '.') 1128 break; 1129 1130 ptr++; 1131 1132 /* Just a size without an explicit type. */ 1133 if (ISDIGIT (*ptr)) 1134 goto parsesize; 1135 1136 switch (TOLOWER (*ptr)) 1137 { 1138 case 'i': thistype = NT_integer; break; 1139 case 'f': thistype = NT_float; break; 1140 case 'p': thistype = NT_poly; break; 1141 case 's': thistype = NT_signed; break; 1142 case 'u': thistype = NT_unsigned; break; 1143 case 'd': 1144 thistype = NT_float; 1145 thissize = 64; 1146 ptr++; 1147 goto done; 1148 default: 1149 as_bad (_("unexpected character `%c' in type specifier"), *ptr); 1150 return FAIL; 1151 } 1152 1153 ptr++; 1154 1155 /* .f is an abbreviation for .f32. */ 1156 if (thistype == NT_float && !ISDIGIT (*ptr)) 1157 thissize = 32; 1158 else 1159 { 1160 parsesize: 1161 thissize = strtoul (ptr, &ptr, 10); 1162 1163 if (thissize != 8 && thissize != 16 && thissize != 32 1164 && thissize != 64) 1165 { 1166 as_bad (_("bad size %d in type specifier"), thissize); 1167 return FAIL; 1168 } 1169 } 1170 1171 done: 1172 if (type) 1173 { 1174 type->el[type->elems].type = thistype; 1175 type->el[type->elems].size = thissize; 1176 type->elems++; 1177 } 1178 } 1179 1180 /* Empty/missing type is not a successful parse. */ 1181 if (type->elems == 0) 1182 return FAIL; 1183 1184 *str = ptr; 1185 1186 return SUCCESS; 1187} 1188 1189/* Errors may be set multiple times during parsing or bit encoding 1190 (particularly in the Neon bits), but usually the earliest error which is set 1191 will be the most meaningful. Avoid overwriting it with later (cascading) 1192 errors by calling this function. */ 1193 1194static void 1195first_error (const char *err) 1196{ 1197 if (!inst.error) 1198 inst.error = err; 1199} 1200 1201/* Parse a single type, e.g. ".s32", leading period included. */ 1202static int 1203parse_neon_operand_type (struct neon_type_el *vectype, char **ccp) 1204{ 1205 char *str = *ccp; 1206 struct neon_type optype; 1207 1208 if (*str == '.') 1209 { 1210 if (parse_neon_type (&optype, &str) == SUCCESS) 1211 { 1212 if (optype.elems == 1) 1213 *vectype = optype.el[0]; 1214 else 1215 { 1216 first_error (_("only one type should be specified for operand")); 1217 return FAIL; 1218 } 1219 } 1220 else 1221 { 1222 first_error (_("vector type expected")); 1223 return FAIL; 1224 } 1225 } 1226 else 1227 return FAIL; 1228 1229 *ccp = str; 1230 1231 return SUCCESS; 1232} 1233 1234/* Special meanings for indices (which have a range of 0-7), which will fit into 1235 a 4-bit integer. */ 1236 1237#define NEON_ALL_LANES 15 1238#define NEON_INTERLEAVE_LANES 14 1239 1240/* Parse either a register or a scalar, with an optional type. Return the 1241 register number, and optionally fill in the actual type of the register 1242 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and 1243 type/index information in *TYPEINFO. */ 1244 1245static int 1246parse_typed_reg_or_scalar (char **ccp, enum arm_reg_type type, 1247 enum arm_reg_type *rtype, 1248 struct neon_typed_alias *typeinfo) 1249{ 1250 char *str = *ccp; 1251 struct reg_entry *reg = arm_reg_parse_multi (&str); 1252 struct neon_typed_alias atype; 1253 struct neon_type_el parsetype; 1254 1255 atype.defined = 0; 1256 atype.index = -1; 1257 atype.eltype.type = NT_invtype; 1258 atype.eltype.size = -1; 1259 1260 /* Try alternate syntax for some types of register. Note these are mutually 1261 exclusive with the Neon syntax extensions. */ 1262 if (reg == NULL) 1263 { 1264 int altreg = arm_reg_alt_syntax (&str, *ccp, reg, type); 1265 if (altreg != FAIL) 1266 *ccp = str; 1267 if (typeinfo) 1268 *typeinfo = atype; 1269 return altreg; 1270 } 1271 1272 /* Undo polymorphism when a set of register types may be accepted. */ 1273 if ((type == REG_TYPE_NDQ 1274 && (reg->type == REG_TYPE_NQ || reg->type == REG_TYPE_VFD)) 1275 || (type == REG_TYPE_VFSD 1276 && (reg->type == REG_TYPE_VFS || reg->type == REG_TYPE_VFD)) 1277 || (type == REG_TYPE_NSDQ 1278 && (reg->type == REG_TYPE_VFS || reg->type == REG_TYPE_VFD 1279 || reg->type == REG_TYPE_NQ)) 1280 || (type == REG_TYPE_MMXWC 1281 && (reg->type == REG_TYPE_MMXWCG))) 1282 type = reg->type; 1283 1284 if (type != reg->type) 1285 return FAIL; 1286 1287 if (reg->neon) 1288 atype = *reg->neon; 1289 1290 if (parse_neon_operand_type (&parsetype, &str) == SUCCESS) 1291 { 1292 if ((atype.defined & NTA_HASTYPE) != 0) 1293 { 1294 first_error (_("can't redefine type for operand")); 1295 return FAIL; 1296 } 1297 atype.defined |= NTA_HASTYPE; 1298 atype.eltype = parsetype; 1299 } 1300 1301 if (skip_past_char (&str, '[') == SUCCESS) 1302 { 1303 if (type != REG_TYPE_VFD) 1304 { 1305 first_error (_("only D registers may be indexed")); 1306 return FAIL; 1307 } 1308 1309 if ((atype.defined & NTA_HASINDEX) != 0) 1310 { 1311 first_error (_("can't change index for operand")); 1312 return FAIL; 1313 } 1314 1315 atype.defined |= NTA_HASINDEX; 1316 1317 if (skip_past_char (&str, ']') == SUCCESS) 1318 atype.index = NEON_ALL_LANES; 1319 else 1320 { 1321 expressionS exp; 1322 1323 my_get_expression (&exp, &str, GE_NO_PREFIX); 1324 1325 if (exp.X_op != O_constant) 1326 { 1327 first_error (_("constant expression required")); 1328 return FAIL; 1329 } 1330 1331 if (skip_past_char (&str, ']') == FAIL) 1332 return FAIL; 1333 1334 atype.index = exp.X_add_number; 1335 } 1336 } 1337 1338 if (typeinfo) 1339 *typeinfo = atype; 1340 1341 if (rtype) 1342 *rtype = type; 1343 1344 *ccp = str; 1345 1346 return reg->number; 1347} 1348 1349/* Like arm_reg_parse, but allow allow the following extra features: 1350 - If RTYPE is non-zero, return the (possibly restricted) type of the 1351 register (e.g. Neon double or quad reg when either has been requested). 1352 - If this is a Neon vector type with additional type information, fill 1353 in the struct pointed to by VECTYPE (if non-NULL). 1354 This function will fault on encountering a scalar. 1355*/ 1356 1357static int 1358arm_typed_reg_parse (char **ccp, enum arm_reg_type type, 1359 enum arm_reg_type *rtype, struct neon_type_el *vectype) 1360{ 1361 struct neon_typed_alias atype; 1362 char *str = *ccp; 1363 int reg = parse_typed_reg_or_scalar (&str, type, rtype, &atype); 1364 1365 if (reg == FAIL) 1366 return FAIL; 1367 1368 /* Do not allow a scalar (reg+index) to parse as a register. */ 1369 if ((atype.defined & NTA_HASINDEX) != 0) 1370 { 1371 first_error (_("register operand expected, but got scalar")); 1372 return FAIL; 1373 } 1374 1375 if (vectype) 1376 *vectype = atype.eltype; 1377 1378 *ccp = str; 1379 1380 return reg; 1381} 1382 1383#define NEON_SCALAR_REG(X) ((X) >> 4) 1384#define NEON_SCALAR_INDEX(X) ((X) & 15) 1385 1386/* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't 1387 have enough information to be able to do a good job bounds-checking. So, we 1388 just do easy checks here, and do further checks later. */ 1389 1390static int 1391parse_scalar (char **ccp, int elsize, struct neon_type_el *type) 1392{ 1393 int reg; 1394 char *str = *ccp; 1395 struct neon_typed_alias atype; 1396 1397 reg = parse_typed_reg_or_scalar (&str, REG_TYPE_VFD, NULL, &atype); 1398 1399 if (reg == FAIL || (atype.defined & NTA_HASINDEX) == 0) 1400 return FAIL; 1401 1402 if (atype.index == NEON_ALL_LANES) 1403 { 1404 first_error (_("scalar must have an index")); 1405 return FAIL; 1406 } 1407 else if (atype.index >= 64 / elsize) 1408 { 1409 first_error (_("scalar index out of range")); 1410 return FAIL; 1411 } 1412 1413 if (type) 1414 *type = atype.eltype; 1415 1416 *ccp = str; 1417 1418 return reg * 16 + atype.index; 1419} 1420 1421/* Parse an ARM register list. Returns the bitmask, or FAIL. */ 1422static long 1423parse_reg_list (char ** strp) 1424{ 1425 char * str = * strp; 1426 long range = 0; 1427 int another_range; 1428 1429 /* We come back here if we get ranges concatenated by '+' or '|'. */ 1430 do 1431 { 1432 another_range = 0; 1433 1434 if (*str == '{') 1435 { 1436 int in_range = 0; 1437 int cur_reg = -1; 1438 1439 str++; 1440 do 1441 { 1442 int reg; 1443 1444 if ((reg = arm_reg_parse (&str, REG_TYPE_RN)) == FAIL) 1445 { 1446 first_error (_(reg_expected_msgs[REG_TYPE_RN])); 1447 return FAIL; 1448 } 1449 1450 if (in_range) 1451 { 1452 int i; 1453 1454 if (reg <= cur_reg) 1455 { 1456 first_error (_("bad range in register list")); 1457 return FAIL; 1458 } 1459 1460 for (i = cur_reg + 1; i < reg; i++) 1461 { 1462 if (range & (1 << i)) 1463 as_tsktsk 1464 (_("Warning: duplicated register (r%d) in register list"), 1465 i); 1466 else 1467 range |= 1 << i; 1468 } 1469 in_range = 0; 1470 } 1471 1472 if (range & (1 << reg)) 1473 as_tsktsk (_("Warning: duplicated register (r%d) in register list"), 1474 reg); 1475 else if (reg <= cur_reg) 1476 as_tsktsk (_("Warning: register range not in ascending order")); 1477 1478 range |= 1 << reg; 1479 cur_reg = reg; 1480 } 1481 while (skip_past_comma (&str) != FAIL 1482 || (in_range = 1, *str++ == '-')); 1483 str--; 1484 1485 if (*str++ != '}') 1486 { 1487 first_error (_("missing `}'")); 1488 return FAIL; 1489 } 1490 } 1491 else 1492 { 1493 expressionS expr; 1494 1495 if (my_get_expression (&expr, &str, GE_NO_PREFIX)) 1496 return FAIL; 1497 1498 if (expr.X_op == O_constant) 1499 { 1500 if (expr.X_add_number 1501 != (expr.X_add_number & 0x0000ffff)) 1502 { 1503 inst.error = _("invalid register mask"); 1504 return FAIL; 1505 } 1506 1507 if ((range & expr.X_add_number) != 0) 1508 { 1509 int regno = range & expr.X_add_number; 1510 1511 regno &= -regno; 1512 regno = (1 << regno) - 1; 1513 as_tsktsk 1514 (_("Warning: duplicated register (r%d) in register list"), 1515 regno); 1516 } 1517 1518 range |= expr.X_add_number; 1519 } 1520 else 1521 { 1522 if (inst.reloc.type != 0) 1523 { 1524 inst.error = _("expression too complex"); 1525 return FAIL; 1526 } 1527 1528 memcpy (&inst.reloc.exp, &expr, sizeof (expressionS)); 1529 inst.reloc.type = BFD_RELOC_ARM_MULTI; 1530 inst.reloc.pc_rel = 0; 1531 } 1532 } 1533 1534 if (*str == '|' || *str == '+') 1535 { 1536 str++; 1537 another_range = 1; 1538 } 1539 } 1540 while (another_range); 1541 1542 *strp = str; 1543 return range; 1544} 1545 1546/* Types of registers in a list. */ 1547 1548enum reg_list_els 1549{ 1550 REGLIST_VFP_S, 1551 REGLIST_VFP_D, 1552 REGLIST_NEON_D 1553}; 1554 1555/* Parse a VFP register list. If the string is invalid return FAIL. 1556 Otherwise return the number of registers, and set PBASE to the first 1557 register. Parses registers of type ETYPE. 1558 If REGLIST_NEON_D is used, several syntax enhancements are enabled: 1559 - Q registers can be used to specify pairs of D registers 1560 - { } can be omitted from around a singleton register list 1561 FIXME: This is not implemented, as it would require backtracking in 1562 some cases, e.g.: 1563 vtbl.8 d3,d4,d5 1564 This could be done (the meaning isn't really ambiguous), but doesn't 1565 fit in well with the current parsing framework. 1566 - 32 D registers may be used (also true for VFPv3). 1567 FIXME: Types are ignored in these register lists, which is probably a 1568 bug. */ 1569 1570static int 1571parse_vfp_reg_list (char **ccp, unsigned int *pbase, enum reg_list_els etype) 1572{ 1573 char *str = *ccp; 1574 int base_reg; 1575 int new_base; 1576 enum arm_reg_type regtype = 0; 1577 int max_regs = 0; 1578 int count = 0; 1579 int warned = 0; 1580 unsigned long mask = 0; 1581 int i; 1582 1583 if (*str != '{') 1584 { 1585 inst.error = _("expecting {"); 1586 return FAIL; 1587 } 1588 1589 str++; 1590 1591 switch (etype) 1592 { 1593 case REGLIST_VFP_S: 1594 regtype = REG_TYPE_VFS; 1595 max_regs = 32; 1596 break; 1597 1598 case REGLIST_VFP_D: 1599 regtype = REG_TYPE_VFD; 1600 break; 1601 1602 case REGLIST_NEON_D: 1603 regtype = REG_TYPE_NDQ; 1604 break; 1605 } 1606 1607 if (etype != REGLIST_VFP_S) 1608 { 1609 /* VFPv3 allows 32 D registers. */ 1610 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v3)) 1611 { 1612 max_regs = 32; 1613 if (thumb_mode) 1614 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, 1615 fpu_vfp_ext_v3); 1616 else 1617 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, 1618 fpu_vfp_ext_v3); 1619 } 1620 else 1621 max_regs = 16; 1622 } 1623 1624 base_reg = max_regs; 1625 1626 do 1627 { 1628 int setmask = 1, addregs = 1; 1629 1630 new_base = arm_typed_reg_parse (&str, regtype, ®type, NULL); 1631 1632 if (new_base == FAIL) 1633 { 1634 first_error (_(reg_expected_msgs[regtype])); 1635 return FAIL; 1636 } 1637 1638 if (new_base >= max_regs) 1639 { 1640 first_error (_("register out of range in list")); 1641 return FAIL; 1642 } 1643 1644 /* Note: a value of 2 * n is returned for the register Q<n>. */ 1645 if (regtype == REG_TYPE_NQ) 1646 { 1647 setmask = 3; 1648 addregs = 2; 1649 } 1650 1651 if (new_base < base_reg) 1652 base_reg = new_base; 1653 1654 if (mask & (setmask << new_base)) 1655 { 1656 first_error (_("invalid register list")); 1657 return FAIL; 1658 } 1659 1660 if ((mask >> new_base) != 0 && ! warned) 1661 { 1662 as_tsktsk (_("register list not in ascending order")); 1663 warned = 1; 1664 } 1665 1666 mask |= setmask << new_base; 1667 count += addregs; 1668 1669 if (*str == '-') /* We have the start of a range expression */ 1670 { 1671 int high_range; 1672 1673 str++; 1674 1675 if ((high_range = arm_typed_reg_parse (&str, regtype, NULL, NULL)) 1676 == FAIL) 1677 { 1678 inst.error = gettext (reg_expected_msgs[regtype]); 1679 return FAIL; 1680 } 1681 1682 if (high_range >= max_regs) 1683 { 1684 first_error (_("register out of range in list")); 1685 return FAIL; 1686 } 1687 1688 if (regtype == REG_TYPE_NQ) 1689 high_range = high_range + 1; 1690 1691 if (high_range <= new_base) 1692 { 1693 inst.error = _("register range not in ascending order"); 1694 return FAIL; 1695 } 1696 1697 for (new_base += addregs; new_base <= high_range; new_base += addregs) 1698 { 1699 if (mask & (setmask << new_base)) 1700 { 1701 inst.error = _("invalid register list"); 1702 return FAIL; 1703 } 1704 1705 mask |= setmask << new_base; 1706 count += addregs; 1707 } 1708 } 1709 } 1710 while (skip_past_comma (&str) != FAIL); 1711 1712 str++; 1713 1714 /* Sanity check -- should have raised a parse error above. */ 1715 if (count == 0 || count > max_regs) 1716 abort (); 1717 1718 *pbase = base_reg; 1719 1720 /* Final test -- the registers must be consecutive. */ 1721 mask >>= base_reg; 1722 for (i = 0; i < count; i++) 1723 { 1724 if ((mask & (1u << i)) == 0) 1725 { 1726 inst.error = _("non-contiguous register range"); 1727 return FAIL; 1728 } 1729 } 1730 1731 *ccp = str; 1732 1733 return count; 1734} 1735 1736/* True if two alias types are the same. */ 1737 1738static int 1739neon_alias_types_same (struct neon_typed_alias *a, struct neon_typed_alias *b) 1740{ 1741 if (!a && !b) 1742 return 1; 1743 1744 if (!a || !b) 1745 return 0; 1746 1747 if (a->defined != b->defined) 1748 return 0; 1749 1750 if ((a->defined & NTA_HASTYPE) != 0 1751 && (a->eltype.type != b->eltype.type 1752 || a->eltype.size != b->eltype.size)) 1753 return 0; 1754 1755 if ((a->defined & NTA_HASINDEX) != 0 1756 && (a->index != b->index)) 1757 return 0; 1758 1759 return 1; 1760} 1761 1762/* Parse element/structure lists for Neon VLD<n> and VST<n> instructions. 1763 The base register is put in *PBASE. 1764 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of 1765 the return value. 1766 The register stride (minus one) is put in bit 4 of the return value. 1767 Bits [6:5] encode the list length (minus one). 1768 The type of the list elements is put in *ELTYPE, if non-NULL. */ 1769 1770#define NEON_LANE(X) ((X) & 0xf) 1771#define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1) 1772#define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1) 1773 1774static int 1775parse_neon_el_struct_list (char **str, unsigned *pbase, 1776 struct neon_type_el *eltype) 1777{ 1778 char *ptr = *str; 1779 int base_reg = -1; 1780 int reg_incr = -1; 1781 int count = 0; 1782 int lane = -1; 1783 int leading_brace = 0; 1784 enum arm_reg_type rtype = REG_TYPE_NDQ; 1785 int addregs = 1; 1786 const char *const incr_error = "register stride must be 1 or 2"; 1787 const char *const type_error = "mismatched element/structure types in list"; 1788 struct neon_typed_alias firsttype; 1789 1790 if (skip_past_char (&ptr, '{') == SUCCESS) 1791 leading_brace = 1; 1792 1793 do 1794 { 1795 struct neon_typed_alias atype; 1796 int getreg = parse_typed_reg_or_scalar (&ptr, rtype, &rtype, &atype); 1797 1798 if (getreg == FAIL) 1799 { 1800 first_error (_(reg_expected_msgs[rtype])); 1801 return FAIL; 1802 } 1803 1804 if (base_reg == -1) 1805 { 1806 base_reg = getreg; 1807 if (rtype == REG_TYPE_NQ) 1808 { 1809 reg_incr = 1; 1810 addregs = 2; 1811 } 1812 firsttype = atype; 1813 } 1814 else if (reg_incr == -1) 1815 { 1816 reg_incr = getreg - base_reg; 1817 if (reg_incr < 1 || reg_incr > 2) 1818 { 1819 first_error (_(incr_error)); 1820 return FAIL; 1821 } 1822 } 1823 else if (getreg != base_reg + reg_incr * count) 1824 { 1825 first_error (_(incr_error)); 1826 return FAIL; 1827 } 1828 1829 if (!neon_alias_types_same (&atype, &firsttype)) 1830 { 1831 first_error (_(type_error)); 1832 return FAIL; 1833 } 1834 1835 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list 1836 modes. */ 1837 if (ptr[0] == '-') 1838 { 1839 struct neon_typed_alias htype; 1840 int hireg, dregs = (rtype == REG_TYPE_NQ) ? 2 : 1; 1841 if (lane == -1) 1842 lane = NEON_INTERLEAVE_LANES; 1843 else if (lane != NEON_INTERLEAVE_LANES) 1844 { 1845 first_error (_(type_error)); 1846 return FAIL; 1847 } 1848 if (reg_incr == -1) 1849 reg_incr = 1; 1850 else if (reg_incr != 1) 1851 { 1852 first_error (_("don't use Rn-Rm syntax with non-unit stride")); 1853 return FAIL; 1854 } 1855 ptr++; 1856 hireg = parse_typed_reg_or_scalar (&ptr, rtype, NULL, &htype); 1857 if (hireg == FAIL) 1858 { 1859 first_error (_(reg_expected_msgs[rtype])); 1860 return FAIL; 1861 } 1862 if (!neon_alias_types_same (&htype, &firsttype)) 1863 { 1864 first_error (_(type_error)); 1865 return FAIL; 1866 } 1867 count += hireg + dregs - getreg; 1868 continue; 1869 } 1870 1871 /* If we're using Q registers, we can't use [] or [n] syntax. */ 1872 if (rtype == REG_TYPE_NQ) 1873 { 1874 count += 2; 1875 continue; 1876 } 1877 1878 if ((atype.defined & NTA_HASINDEX) != 0) 1879 { 1880 if (lane == -1) 1881 lane = atype.index; 1882 else if (lane != atype.index) 1883 { 1884 first_error (_(type_error)); 1885 return FAIL; 1886 } 1887 } 1888 else if (lane == -1) 1889 lane = NEON_INTERLEAVE_LANES; 1890 else if (lane != NEON_INTERLEAVE_LANES) 1891 { 1892 first_error (_(type_error)); 1893 return FAIL; 1894 } 1895 count++; 1896 } 1897 while ((count != 1 || leading_brace) && skip_past_comma (&ptr) != FAIL); 1898 1899 /* No lane set by [x]. We must be interleaving structures. */ 1900 if (lane == -1) 1901 lane = NEON_INTERLEAVE_LANES; 1902 1903 /* Sanity check. */ 1904 if (lane == -1 || base_reg == -1 || count < 1 || count > 4 1905 || (count > 1 && reg_incr == -1)) 1906 { 1907 first_error (_("error parsing element/structure list")); 1908 return FAIL; 1909 } 1910 1911 if ((count > 1 || leading_brace) && skip_past_char (&ptr, '}') == FAIL) 1912 { 1913 first_error (_("expected }")); 1914 return FAIL; 1915 } 1916 1917 if (reg_incr == -1) 1918 reg_incr = 1; 1919 1920 if (eltype) 1921 *eltype = firsttype.eltype; 1922 1923 *pbase = base_reg; 1924 *str = ptr; 1925 1926 return lane | ((reg_incr - 1) << 4) | ((count - 1) << 5); 1927} 1928 1929/* Parse an explicit relocation suffix on an expression. This is 1930 either nothing, or a word in parentheses. Note that if !OBJ_ELF, 1931 arm_reloc_hsh contains no entries, so this function can only 1932 succeed if there is no () after the word. Returns -1 on error, 1933 BFD_RELOC_UNUSED if there wasn't any suffix. */ 1934static int 1935parse_reloc (char **str) 1936{ 1937 struct reloc_entry *r; 1938 char *p, *q; 1939 1940 if (**str != '(') 1941 return BFD_RELOC_UNUSED; 1942 1943 p = *str + 1; 1944 q = p; 1945 1946 while (*q && *q != ')' && *q != ',') 1947 q++; 1948 if (*q != ')') 1949 return -1; 1950 1951 if ((r = hash_find_n (arm_reloc_hsh, p, q - p)) == NULL) 1952 return -1; 1953 1954 *str = q + 1; 1955 return r->reloc; 1956} 1957 1958/* Directives: register aliases. */ 1959 1960static struct reg_entry * 1961insert_reg_alias (char *str, int number, int type) 1962{ 1963 struct reg_entry *new; 1964 const char *name; 1965 1966 if ((new = hash_find (arm_reg_hsh, str)) != 0) 1967 { 1968 if (new->builtin) 1969 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str); 1970 1971 /* Only warn about a redefinition if it's not defined as the 1972 same register. */ 1973 else if (new->number != number || new->type != type) 1974 as_warn (_("ignoring redefinition of register alias '%s'"), str); 1975 1976 return 0; 1977 } 1978 1979 name = xstrdup (str); 1980 new = xmalloc (sizeof (struct reg_entry)); 1981 1982 new->name = name; 1983 new->number = number; 1984 new->type = type; 1985 new->builtin = FALSE; 1986 new->neon = NULL; 1987 1988 if (hash_insert (arm_reg_hsh, name, (PTR) new)) 1989 abort (); 1990 1991 return new; 1992} 1993 1994static void 1995insert_neon_reg_alias (char *str, int number, int type, 1996 struct neon_typed_alias *atype) 1997{ 1998 struct reg_entry *reg = insert_reg_alias (str, number, type); 1999 2000 if (!reg) 2001 { 2002 first_error (_("attempt to redefine typed alias")); 2003 return; 2004 } 2005 2006 if (atype) 2007 { 2008 reg->neon = xmalloc (sizeof (struct neon_typed_alias)); 2009 *reg->neon = *atype; 2010 } 2011} 2012 2013/* Look for the .req directive. This is of the form: 2014 2015 new_register_name .req existing_register_name 2016 2017 If we find one, or if it looks sufficiently like one that we want to 2018 handle any error here, return non-zero. Otherwise return zero. */ 2019 2020static int 2021create_register_alias (char * newname, char *p) 2022{ 2023 struct reg_entry *old; 2024 char *oldname, *nbuf; 2025 size_t nlen; 2026 2027 /* The input scrubber ensures that whitespace after the mnemonic is 2028 collapsed to single spaces. */ 2029 oldname = p; 2030 if (strncmp (oldname, " .req ", 6) != 0) 2031 return 0; 2032 2033 oldname += 6; 2034 if (*oldname == '\0') 2035 return 0; 2036 2037 old = hash_find (arm_reg_hsh, oldname); 2038 if (!old) 2039 { 2040 as_warn (_("unknown register '%s' -- .req ignored"), oldname); 2041 return 1; 2042 } 2043 2044 /* If TC_CASE_SENSITIVE is defined, then newname already points to 2045 the desired alias name, and p points to its end. If not, then 2046 the desired alias name is in the global original_case_string. */ 2047#ifdef TC_CASE_SENSITIVE 2048 nlen = p - newname; 2049#else 2050 newname = original_case_string; 2051 nlen = strlen (newname); 2052#endif 2053 2054 nbuf = alloca (nlen + 1); 2055 memcpy (nbuf, newname, nlen); 2056 nbuf[nlen] = '\0'; 2057 2058 /* Create aliases under the new name as stated; an all-lowercase 2059 version of the new name; and an all-uppercase version of the new 2060 name. */ 2061 insert_reg_alias (nbuf, old->number, old->type); 2062 2063 for (p = nbuf; *p; p++) 2064 *p = TOUPPER (*p); 2065 2066 if (strncmp (nbuf, newname, nlen)) 2067 insert_reg_alias (nbuf, old->number, old->type); 2068 2069 for (p = nbuf; *p; p++) 2070 *p = TOLOWER (*p); 2071 2072 if (strncmp (nbuf, newname, nlen)) 2073 insert_reg_alias (nbuf, old->number, old->type); 2074 2075 return 1; 2076} 2077 2078/* Create a Neon typed/indexed register alias using directives, e.g.: 2079 X .dn d5.s32[1] 2080 Y .qn 6.s16 2081 Z .dn d7 2082 T .dn Z[0] 2083 These typed registers can be used instead of the types specified after the 2084 Neon mnemonic, so long as all operands given have types. Types can also be 2085 specified directly, e.g.: 2086 vadd d0.s32, d1.s32, d2.s32 2087*/ 2088 2089static int 2090create_neon_reg_alias (char *newname, char *p) 2091{ 2092 enum arm_reg_type basetype; 2093 struct reg_entry *basereg; 2094 struct reg_entry mybasereg; 2095 struct neon_type ntype; 2096 struct neon_typed_alias typeinfo; 2097 char *namebuf, *nameend; 2098 int namelen; 2099 2100 typeinfo.defined = 0; 2101 typeinfo.eltype.type = NT_invtype; 2102 typeinfo.eltype.size = -1; 2103 typeinfo.index = -1; 2104 2105 nameend = p; 2106 2107 if (strncmp (p, " .dn ", 5) == 0) 2108 basetype = REG_TYPE_VFD; 2109 else if (strncmp (p, " .qn ", 5) == 0) 2110 basetype = REG_TYPE_NQ; 2111 else 2112 return 0; 2113 2114 p += 5; 2115 2116 if (*p == '\0') 2117 return 0; 2118 2119 basereg = arm_reg_parse_multi (&p); 2120 2121 if (basereg && basereg->type != basetype) 2122 { 2123 as_bad (_("bad type for register")); 2124 return 0; 2125 } 2126 2127 if (basereg == NULL) 2128 { 2129 expressionS exp; 2130 /* Try parsing as an integer. */ 2131 my_get_expression (&exp, &p, GE_NO_PREFIX); 2132 if (exp.X_op != O_constant) 2133 { 2134 as_bad (_("expression must be constant")); 2135 return 0; 2136 } 2137 basereg = &mybasereg; 2138 basereg->number = (basetype == REG_TYPE_NQ) ? exp.X_add_number * 2 2139 : exp.X_add_number; 2140 basereg->neon = 0; 2141 } 2142 2143 if (basereg->neon) 2144 typeinfo = *basereg->neon; 2145 2146 if (parse_neon_type (&ntype, &p) == SUCCESS) 2147 { 2148 /* We got a type. */ 2149 if (typeinfo.defined & NTA_HASTYPE) 2150 { 2151 as_bad (_("can't redefine the type of a register alias")); 2152 return 0; 2153 } 2154 2155 typeinfo.defined |= NTA_HASTYPE; 2156 if (ntype.elems != 1) 2157 { 2158 as_bad (_("you must specify a single type only")); 2159 return 0; 2160 } 2161 typeinfo.eltype = ntype.el[0]; 2162 } 2163 2164 if (skip_past_char (&p, '[') == SUCCESS) 2165 { 2166 expressionS exp; 2167 /* We got a scalar index. */ 2168 2169 if (typeinfo.defined & NTA_HASINDEX) 2170 { 2171 as_bad (_("can't redefine the index of a scalar alias")); 2172 return 0; 2173 } 2174 2175 my_get_expression (&exp, &p, GE_NO_PREFIX); 2176 2177 if (exp.X_op != O_constant) 2178 { 2179 as_bad (_("scalar index must be constant")); 2180 return 0; 2181 } 2182 2183 typeinfo.defined |= NTA_HASINDEX; 2184 typeinfo.index = exp.X_add_number; 2185 2186 if (skip_past_char (&p, ']') == FAIL) 2187 { 2188 as_bad (_("expecting ]")); 2189 return 0; 2190 } 2191 } 2192 2193 namelen = nameend - newname; 2194 namebuf = alloca (namelen + 1); 2195 strncpy (namebuf, newname, namelen); 2196 namebuf[namelen] = '\0'; 2197 2198 insert_neon_reg_alias (namebuf, basereg->number, basetype, 2199 typeinfo.defined != 0 ? &typeinfo : NULL); 2200 2201 /* Insert name in all uppercase. */ 2202 for (p = namebuf; *p; p++) 2203 *p = TOUPPER (*p); 2204 2205 if (strncmp (namebuf, newname, namelen)) 2206 insert_neon_reg_alias (namebuf, basereg->number, basetype, 2207 typeinfo.defined != 0 ? &typeinfo : NULL); 2208 2209 /* Insert name in all lowercase. */ 2210 for (p = namebuf; *p; p++) 2211 *p = TOLOWER (*p); 2212 2213 if (strncmp (namebuf, newname, namelen)) 2214 insert_neon_reg_alias (namebuf, basereg->number, basetype, 2215 typeinfo.defined != 0 ? &typeinfo : NULL); 2216 2217 return 1; 2218} 2219 2220/* Should never be called, as .req goes between the alias and the 2221 register name, not at the beginning of the line. */ 2222static void 2223s_req (int a ATTRIBUTE_UNUSED) 2224{ 2225 as_bad (_("invalid syntax for .req directive")); 2226} 2227 2228static void 2229s_dn (int a ATTRIBUTE_UNUSED) 2230{ 2231 as_bad (_("invalid syntax for .dn directive")); 2232} 2233 2234static void 2235s_qn (int a ATTRIBUTE_UNUSED) 2236{ 2237 as_bad (_("invalid syntax for .qn directive")); 2238} 2239 2240/* The .unreq directive deletes an alias which was previously defined 2241 by .req. For example: 2242 2243 my_alias .req r11 2244 .unreq my_alias */ 2245 2246static void 2247s_unreq (int a ATTRIBUTE_UNUSED) 2248{ 2249 char * name; 2250 char saved_char; 2251 2252 name = input_line_pointer; 2253 2254 while (*input_line_pointer != 0 2255 && *input_line_pointer != ' ' 2256 && *input_line_pointer != '\n') 2257 ++input_line_pointer; 2258 2259 saved_char = *input_line_pointer; 2260 *input_line_pointer = 0; 2261 2262 if (!*name) 2263 as_bad (_("invalid syntax for .unreq directive")); 2264 else 2265 { 2266 struct reg_entry *reg = hash_find (arm_reg_hsh, name); 2267 2268 if (!reg) 2269 as_bad (_("unknown register alias '%s'"), name); 2270 else if (reg->builtin) 2271 as_warn (_("ignoring attempt to undefine built-in register '%s'"), 2272 name); 2273 else 2274 { 2275 hash_delete (arm_reg_hsh, name); 2276 free ((char *) reg->name); 2277 if (reg->neon) 2278 free (reg->neon); 2279 free (reg); 2280 } 2281 } 2282 2283 *input_line_pointer = saved_char; 2284 demand_empty_rest_of_line (); 2285} 2286 2287static void 2288s_inst(int unused ATTRIBUTE_UNUSED) 2289{ 2290 expressionS exp; 2291 2292 if (thumb_mode) { 2293 as_bad(".inst not implemented for Thumb mode"); 2294 ignore_rest_of_line(); 2295 return; 2296 } 2297 2298 if (is_it_end_of_statement()) { 2299 demand_empty_rest_of_line(); 2300 return; 2301 } 2302 2303 do { 2304 expression(&exp); 2305 2306 if (exp.X_op != O_constant) 2307 as_bad("constant expression required"); 2308 else 2309 emit_expr(&exp, 4); 2310 2311 } while (*input_line_pointer++ == ','); 2312 2313 /* Put terminator back into stream. */ 2314 input_line_pointer--; 2315 demand_empty_rest_of_line(); 2316} 2317 2318/* Directives: Instruction set selection. */ 2319 2320#ifdef OBJ_ELF 2321/* This code is to handle mapping symbols as defined in the ARM ELF spec. 2322 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0). 2323 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag), 2324 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */ 2325 2326static enum mstate mapstate = MAP_UNDEFINED; 2327 2328void 2329mapping_state (enum mstate state) 2330{ 2331 symbolS * symbolP; 2332 const char * symname; 2333 int type; 2334 2335 if (mapstate == state) 2336 /* The mapping symbol has already been emitted. 2337 There is nothing else to do. */ 2338 return; 2339 2340 mapstate = state; 2341 2342 switch (state) 2343 { 2344 case MAP_DATA: 2345 symname = "$d"; 2346 type = BSF_NO_FLAGS; 2347 break; 2348 case MAP_ARM: 2349 symname = "$a"; 2350 type = BSF_NO_FLAGS; 2351 break; 2352 case MAP_THUMB: 2353 symname = "$t"; 2354 type = BSF_NO_FLAGS; 2355 break; 2356 case MAP_UNDEFINED: 2357 return; 2358 default: 2359 abort (); 2360 } 2361 2362 seg_info (now_seg)->tc_segment_info_data.mapstate = state; 2363 2364 symbolP = symbol_new (symname, now_seg, (valueT) frag_now_fix (), frag_now); 2365 symbol_table_insert (symbolP); 2366 symbol_get_bfdsym (symbolP)->flags |= type | BSF_LOCAL; 2367 2368 switch (state) 2369 { 2370 case MAP_ARM: 2371 THUMB_SET_FUNC (symbolP, 0); 2372 ARM_SET_THUMB (symbolP, 0); 2373 ARM_SET_INTERWORK (symbolP, support_interwork); 2374 break; 2375 2376 case MAP_THUMB: 2377 THUMB_SET_FUNC (symbolP, 1); 2378 ARM_SET_THUMB (symbolP, 1); 2379 ARM_SET_INTERWORK (symbolP, support_interwork); 2380 break; 2381 2382 case MAP_DATA: 2383 default: 2384 return; 2385 } 2386} 2387#else 2388#define mapping_state(x) /* nothing */ 2389#endif 2390 2391/* Find the real, Thumb encoded start of a Thumb function. */ 2392 2393static symbolS * 2394find_real_start (symbolS * symbolP) 2395{ 2396 char * real_start; 2397 const char * name = S_GET_NAME (symbolP); 2398 symbolS * new_target; 2399 2400 /* This definition must agree with the one in gcc/config/arm/thumb.c. */ 2401#define STUB_NAME ".real_start_of" 2402 2403 if (name == NULL) 2404 abort (); 2405 2406 /* The compiler may generate BL instructions to local labels because 2407 it needs to perform a branch to a far away location. These labels 2408 do not have a corresponding ".real_start_of" label. We check 2409 both for S_IS_LOCAL and for a leading dot, to give a way to bypass 2410 the ".real_start_of" convention for nonlocal branches. */ 2411 if (S_IS_LOCAL (symbolP) || name[0] == '.') 2412 return symbolP; 2413 2414 real_start = ACONCAT ((STUB_NAME, name, NULL)); 2415 new_target = symbol_find (real_start); 2416 2417 if (new_target == NULL) 2418 { 2419 as_warn ("Failed to find real start of function: %s\n", name); 2420 new_target = symbolP; 2421 } 2422 2423 return new_target; 2424} 2425 2426static void 2427opcode_select (int width) 2428{ 2429 switch (width) 2430 { 2431 case 16: 2432 if (! thumb_mode) 2433 { 2434 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t)) 2435 as_bad (_("selected processor does not support THUMB opcodes")); 2436 2437 thumb_mode = 1; 2438 /* No need to force the alignment, since we will have been 2439 coming from ARM mode, which is word-aligned. */ 2440 record_alignment (now_seg, 1); 2441 } 2442 mapping_state (MAP_THUMB); 2443 break; 2444 2445 case 32: 2446 if (thumb_mode) 2447 { 2448 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1)) 2449 as_bad (_("selected processor does not support ARM opcodes")); 2450 2451 thumb_mode = 0; 2452 2453 if (!need_pass_2) 2454 frag_align (2, 0, 0); 2455 2456 record_alignment (now_seg, 1); 2457 } 2458 mapping_state (MAP_ARM); 2459 break; 2460 2461 default: 2462 as_bad (_("invalid instruction size selected (%d)"), width); 2463 } 2464} 2465 2466static void 2467s_arm (int ignore ATTRIBUTE_UNUSED) 2468{ 2469 opcode_select (32); 2470 demand_empty_rest_of_line (); 2471} 2472 2473static void 2474s_thumb (int ignore ATTRIBUTE_UNUSED) 2475{ 2476 opcode_select (16); 2477 demand_empty_rest_of_line (); 2478} 2479 2480static void 2481s_code (int unused ATTRIBUTE_UNUSED) 2482{ 2483 int temp; 2484 2485 temp = get_absolute_expression (); 2486 switch (temp) 2487 { 2488 case 16: 2489 case 32: 2490 opcode_select (temp); 2491 break; 2492 2493 default: 2494 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp); 2495 } 2496} 2497 2498static void 2499s_force_thumb (int ignore ATTRIBUTE_UNUSED) 2500{ 2501 /* If we are not already in thumb mode go into it, EVEN if 2502 the target processor does not support thumb instructions. 2503 This is used by gcc/config/arm/lib1funcs.asm for example 2504 to compile interworking support functions even if the 2505 target processor should not support interworking. */ 2506 if (! thumb_mode) 2507 { 2508 thumb_mode = 2; 2509 record_alignment (now_seg, 1); 2510 } 2511 2512 demand_empty_rest_of_line (); 2513} 2514 2515static void 2516s_thumb_func (int ignore ATTRIBUTE_UNUSED) 2517{ 2518 s_thumb (0); 2519 2520 /* The following label is the name/address of the start of a Thumb function. 2521 We need to know this for the interworking support. */ 2522 label_is_thumb_function_name = TRUE; 2523} 2524 2525/* Perform a .set directive, but also mark the alias as 2526 being a thumb function. */ 2527 2528static void 2529s_thumb_set (int equiv) 2530{ 2531 /* XXX the following is a duplicate of the code for s_set() in read.c 2532 We cannot just call that code as we need to get at the symbol that 2533 is created. */ 2534 char * name; 2535 char delim; 2536 char * end_name; 2537 symbolS * symbolP; 2538 2539 /* Especial apologies for the random logic: 2540 This just grew, and could be parsed much more simply! 2541 Dean - in haste. */ 2542 name = input_line_pointer; 2543 delim = get_symbol_end (); 2544 end_name = input_line_pointer; 2545 *end_name = delim; 2546 2547 if (*input_line_pointer != ',') 2548 { 2549 *end_name = 0; 2550 as_bad (_("expected comma after name \"%s\""), name); 2551 *end_name = delim; 2552 ignore_rest_of_line (); 2553 return; 2554 } 2555 2556 input_line_pointer++; 2557 *end_name = 0; 2558 2559 if (name[0] == '.' && name[1] == '\0') 2560 { 2561 /* XXX - this should not happen to .thumb_set. */ 2562 abort (); 2563 } 2564 2565 if ((symbolP = symbol_find (name)) == NULL 2566 && (symbolP = md_undefined_symbol (name)) == NULL) 2567 { 2568#ifndef NO_LISTING 2569 /* When doing symbol listings, play games with dummy fragments living 2570 outside the normal fragment chain to record the file and line info 2571 for this symbol. */ 2572 if (listing & LISTING_SYMBOLS) 2573 { 2574 extern struct list_info_struct * listing_tail; 2575 fragS * dummy_frag = xmalloc (sizeof (fragS)); 2576 2577 memset (dummy_frag, 0, sizeof (fragS)); 2578 dummy_frag->fr_type = rs_fill; 2579 dummy_frag->line = listing_tail; 2580 symbolP = symbol_new (name, undefined_section, 0, dummy_frag); 2581 dummy_frag->fr_symbol = symbolP; 2582 } 2583 else 2584#endif 2585 symbolP = symbol_new (name, undefined_section, 0, &zero_address_frag); 2586 2587#ifdef OBJ_COFF 2588 /* "set" symbols are local unless otherwise specified. */ 2589 SF_SET_LOCAL (symbolP); 2590#endif /* OBJ_COFF */ 2591 } /* Make a new symbol. */ 2592 2593 symbol_table_insert (symbolP); 2594 2595 * end_name = delim; 2596 2597 if (equiv 2598 && S_IS_DEFINED (symbolP) 2599 && S_GET_SEGMENT (symbolP) != reg_section) 2600 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP)); 2601 2602 pseudo_set (symbolP); 2603 2604 demand_empty_rest_of_line (); 2605 2606 /* XXX Now we come to the Thumb specific bit of code. */ 2607 2608 THUMB_SET_FUNC (symbolP, 1); 2609 ARM_SET_THUMB (symbolP, 1); 2610#if defined OBJ_ELF || defined OBJ_COFF 2611 ARM_SET_INTERWORK (symbolP, support_interwork); 2612#endif 2613} 2614 2615/* Directives: Mode selection. */ 2616 2617/* .syntax [unified|divided] - choose the new unified syntax 2618 (same for Arm and Thumb encoding, modulo slight differences in what 2619 can be represented) or the old divergent syntax for each mode. */ 2620static void 2621s_syntax (int unused ATTRIBUTE_UNUSED) 2622{ 2623 char *name, delim; 2624 2625 name = input_line_pointer; 2626 delim = get_symbol_end (); 2627 2628 if (!strcasecmp (name, "unified")) 2629 unified_syntax = TRUE; 2630 else if (!strcasecmp (name, "divided")) 2631 unified_syntax = FALSE; 2632 else 2633 { 2634 as_bad (_("unrecognized syntax mode \"%s\""), name); 2635 return; 2636 } 2637 *input_line_pointer = delim; 2638 demand_empty_rest_of_line (); 2639} 2640 2641/* Directives: sectioning and alignment. */ 2642 2643/* Same as s_align_ptwo but align 0 => align 2. */ 2644 2645static void 2646s_align (int unused ATTRIBUTE_UNUSED) 2647{ 2648 int temp; 2649 bfd_boolean fill_p; 2650 long temp_fill; 2651 long max_alignment = 15; 2652 2653 temp = get_absolute_expression (); 2654 if (temp > max_alignment) 2655 as_bad (_("alignment too large: %d assumed"), temp = max_alignment); 2656 else if (temp < 0) 2657 { 2658 as_bad (_("alignment negative. 0 assumed.")); 2659 temp = 0; 2660 } 2661 2662 if (*input_line_pointer == ',') 2663 { 2664 input_line_pointer++; 2665 temp_fill = get_absolute_expression (); 2666 fill_p = TRUE; 2667 } 2668 else 2669 { 2670 fill_p = FALSE; 2671 temp_fill = 0; 2672 } 2673 2674 if (!temp) 2675 temp = 2; 2676 2677 /* Only make a frag if we HAVE to. */ 2678 if (temp && !need_pass_2) 2679 { 2680 if (!fill_p && subseg_text_p (now_seg)) 2681 frag_align_code (temp, 0); 2682 else 2683 frag_align (temp, (int) temp_fill, 0); 2684 } 2685 demand_empty_rest_of_line (); 2686 2687 record_alignment (now_seg, temp); 2688} 2689 2690static void 2691s_bss (int ignore ATTRIBUTE_UNUSED) 2692{ 2693 /* We don't support putting frags in the BSS segment, we fake it by 2694 marking in_bss, then looking at s_skip for clues. */ 2695 subseg_set (bss_section, 0); 2696 demand_empty_rest_of_line (); 2697 mapping_state (MAP_DATA); 2698} 2699 2700static void 2701s_even (int ignore ATTRIBUTE_UNUSED) 2702{ 2703 /* Never make frag if expect extra pass. */ 2704 if (!need_pass_2) 2705 frag_align (1, 0, 0); 2706 2707 record_alignment (now_seg, 1); 2708 2709 demand_empty_rest_of_line (); 2710} 2711 2712/* Directives: Literal pools. */ 2713 2714static literal_pool * 2715find_literal_pool (void) 2716{ 2717 literal_pool * pool; 2718 2719 for (pool = list_of_pools; pool != NULL; pool = pool->next) 2720 { 2721 if (pool->section == now_seg 2722 && pool->sub_section == now_subseg) 2723 break; 2724 } 2725 2726 return pool; 2727} 2728 2729static literal_pool * 2730find_or_make_literal_pool (void) 2731{ 2732 /* Next literal pool ID number. */ 2733 static unsigned int latest_pool_num = 1; 2734 literal_pool * pool; 2735 2736 pool = find_literal_pool (); 2737 2738 if (pool == NULL) 2739 { 2740 /* Create a new pool. */ 2741 pool = xmalloc (sizeof (* pool)); 2742 if (! pool) 2743 return NULL; 2744 2745 pool->next_free_entry = 0; 2746 pool->section = now_seg; 2747 pool->sub_section = now_subseg; 2748 pool->next = list_of_pools; 2749 pool->symbol = NULL; 2750 2751 /* Add it to the list. */ 2752 list_of_pools = pool; 2753 } 2754 2755 /* New pools, and emptied pools, will have a NULL symbol. */ 2756 if (pool->symbol == NULL) 2757 { 2758 pool->symbol = symbol_create (FAKE_LABEL_NAME, undefined_section, 2759 (valueT) 0, &zero_address_frag); 2760 pool->id = latest_pool_num ++; 2761 } 2762 2763 /* Done. */ 2764 return pool; 2765} 2766 2767/* Add the literal in the global 'inst' 2768 structure to the relevent literal pool. */ 2769 2770static int 2771add_to_lit_pool (void) 2772{ 2773 literal_pool * pool; 2774 unsigned int entry; 2775 2776 pool = find_or_make_literal_pool (); 2777 2778 /* Check if this literal value is already in the pool. */ 2779 for (entry = 0; entry < pool->next_free_entry; entry ++) 2780 { 2781 if ((pool->literals[entry].X_op == inst.reloc.exp.X_op) 2782 && (inst.reloc.exp.X_op == O_constant) 2783 && (pool->literals[entry].X_add_number 2784 == inst.reloc.exp.X_add_number) 2785 && (pool->literals[entry].X_unsigned 2786 == inst.reloc.exp.X_unsigned)) 2787 break; 2788 2789 if ((pool->literals[entry].X_op == inst.reloc.exp.X_op) 2790 && (inst.reloc.exp.X_op == O_symbol) 2791 && (pool->literals[entry].X_add_number 2792 == inst.reloc.exp.X_add_number) 2793 && (pool->literals[entry].X_add_symbol 2794 == inst.reloc.exp.X_add_symbol) 2795 && (pool->literals[entry].X_op_symbol 2796 == inst.reloc.exp.X_op_symbol)) 2797 break; 2798 } 2799 2800 /* Do we need to create a new entry? */ 2801 if (entry == pool->next_free_entry) 2802 { 2803 if (entry >= MAX_LITERAL_POOL_SIZE) 2804 { 2805 inst.error = _("literal pool overflow"); 2806 return FAIL; 2807 } 2808 2809 pool->literals[entry] = inst.reloc.exp; 2810 pool->next_free_entry += 1; 2811 } 2812 2813 inst.reloc.exp.X_op = O_symbol; 2814 inst.reloc.exp.X_add_number = ((int) entry) * 4; 2815 inst.reloc.exp.X_add_symbol = pool->symbol; 2816 2817 return SUCCESS; 2818} 2819 2820/* Can't use symbol_new here, so have to create a symbol and then at 2821 a later date assign it a value. Thats what these functions do. */ 2822 2823static void 2824symbol_locate (symbolS * symbolP, 2825 const char * name, /* It is copied, the caller can modify. */ 2826 segT segment, /* Segment identifier (SEG_<something>). */ 2827 valueT valu, /* Symbol value. */ 2828 fragS * frag) /* Associated fragment. */ 2829{ 2830 unsigned int name_length; 2831 char * preserved_copy_of_name; 2832 2833 name_length = strlen (name) + 1; /* +1 for \0. */ 2834 obstack_grow (¬es, name, name_length); 2835 preserved_copy_of_name = obstack_finish (¬es); 2836 2837#ifdef tc_canonicalize_symbol_name 2838 preserved_copy_of_name = 2839 tc_canonicalize_symbol_name (preserved_copy_of_name); 2840#endif 2841 2842 S_SET_NAME (symbolP, preserved_copy_of_name); 2843 2844 S_SET_SEGMENT (symbolP, segment); 2845 S_SET_VALUE (symbolP, valu); 2846 symbol_clear_list_pointers (symbolP); 2847 2848 symbol_set_frag (symbolP, frag); 2849 2850 /* Link to end of symbol chain. */ 2851 { 2852 extern int symbol_table_frozen; 2853 2854 if (symbol_table_frozen) 2855 abort (); 2856 } 2857 2858 symbol_append (symbolP, symbol_lastP, & symbol_rootP, & symbol_lastP); 2859 2860 obj_symbol_new_hook (symbolP); 2861 2862#ifdef tc_symbol_new_hook 2863 tc_symbol_new_hook (symbolP); 2864#endif 2865 2866#ifdef DEBUG_SYMS 2867 verify_symbol_chain (symbol_rootP, symbol_lastP); 2868#endif /* DEBUG_SYMS */ 2869} 2870 2871 2872static void 2873s_ltorg (int ignored ATTRIBUTE_UNUSED) 2874{ 2875 unsigned int entry; 2876 literal_pool * pool; 2877 char sym_name[20]; 2878 2879 pool = find_literal_pool (); 2880 if (pool == NULL 2881 || pool->symbol == NULL 2882 || pool->next_free_entry == 0) 2883 return; 2884 2885 mapping_state (MAP_DATA); 2886 2887 /* Align pool as you have word accesses. 2888 Only make a frag if we have to. */ 2889 if (!need_pass_2) 2890 frag_align (2, 0, 0); 2891 2892 record_alignment (now_seg, 2); 2893 2894 sprintf (sym_name, "$$lit_\002%x", pool->id); 2895 2896 symbol_locate (pool->symbol, sym_name, now_seg, 2897 (valueT) frag_now_fix (), frag_now); 2898 symbol_table_insert (pool->symbol); 2899 2900 ARM_SET_THUMB (pool->symbol, thumb_mode); 2901 2902#if defined OBJ_COFF || defined OBJ_ELF 2903 ARM_SET_INTERWORK (pool->symbol, support_interwork); 2904#endif 2905 2906 for (entry = 0; entry < pool->next_free_entry; entry ++) 2907 /* First output the expression in the instruction to the pool. */ 2908 emit_expr (&(pool->literals[entry]), 4); /* .word */ 2909 2910 /* Mark the pool as empty. */ 2911 pool->next_free_entry = 0; 2912 pool->symbol = NULL; 2913} 2914 2915#ifdef OBJ_ELF 2916/* Forward declarations for functions below, in the MD interface 2917 section. */ 2918static void fix_new_arm (fragS *, int, short, expressionS *, int, int); 2919static valueT create_unwind_entry (int); 2920static void start_unwind_section (const segT, int); 2921static void add_unwind_opcode (valueT, int); 2922static void flush_pending_unwind (void); 2923 2924/* Directives: Data. */ 2925 2926static void 2927s_arm_elf_cons (int nbytes) 2928{ 2929 expressionS exp; 2930 2931#ifdef md_flush_pending_output 2932 md_flush_pending_output (); 2933#endif 2934 2935 if (is_it_end_of_statement ()) 2936 { 2937 demand_empty_rest_of_line (); 2938 return; 2939 } 2940 2941#ifdef md_cons_align 2942 md_cons_align (nbytes); 2943#endif 2944 2945 mapping_state (MAP_DATA); 2946 do 2947 { 2948 int reloc; 2949 char *base = input_line_pointer; 2950 2951 expression (& exp); 2952 2953 if (exp.X_op != O_symbol) 2954 emit_expr (&exp, (unsigned int) nbytes); 2955 else 2956 { 2957 char *before_reloc = input_line_pointer; 2958 reloc = parse_reloc (&input_line_pointer); 2959 if (reloc == -1) 2960 { 2961 as_bad (_("unrecognized relocation suffix")); 2962 ignore_rest_of_line (); 2963 return; 2964 } 2965 else if (reloc == BFD_RELOC_UNUSED) 2966 emit_expr (&exp, (unsigned int) nbytes); 2967 else 2968 { 2969 reloc_howto_type *howto = bfd_reloc_type_lookup (stdoutput, reloc); 2970 int size = bfd_get_reloc_size (howto); 2971 2972 if (reloc == BFD_RELOC_ARM_PLT32) 2973 { 2974 as_bad (_("(plt) is only valid on branch targets")); 2975 reloc = BFD_RELOC_UNUSED; 2976 size = 0; 2977 } 2978 2979 if (size > nbytes) 2980 as_bad (_("%s relocations do not fit in %d bytes"), 2981 howto->name, nbytes); 2982 else 2983 { 2984 /* We've parsed an expression stopping at O_symbol. 2985 But there may be more expression left now that we 2986 have parsed the relocation marker. Parse it again. 2987 XXX Surely there is a cleaner way to do this. */ 2988 char *p = input_line_pointer; 2989 int offset; 2990 char *save_buf = alloca (input_line_pointer - base); 2991 memcpy (save_buf, base, input_line_pointer - base); 2992 memmove (base + (input_line_pointer - before_reloc), 2993 base, before_reloc - base); 2994 2995 input_line_pointer = base + (input_line_pointer-before_reloc); 2996 expression (&exp); 2997 memcpy (base, save_buf, p - base); 2998 2999 offset = nbytes - size; 3000 p = frag_more ((int) nbytes); 3001 fix_new_exp (frag_now, p - frag_now->fr_literal + offset, 3002 size, &exp, 0, reloc); 3003 } 3004 } 3005 } 3006 } 3007 while (*input_line_pointer++ == ','); 3008 3009 /* Put terminator back into stream. */ 3010 input_line_pointer --; 3011 demand_empty_rest_of_line (); 3012} 3013 3014 3015/* Parse a .rel31 directive. */ 3016 3017static void 3018s_arm_rel31 (int ignored ATTRIBUTE_UNUSED) 3019{ 3020 expressionS exp; 3021 char *p; 3022 valueT highbit; 3023 3024 highbit = 0; 3025 if (*input_line_pointer == '1') 3026 highbit = 0x80000000; 3027 else if (*input_line_pointer != '0') 3028 as_bad (_("expected 0 or 1")); 3029 3030 input_line_pointer++; 3031 if (*input_line_pointer != ',') 3032 as_bad (_("missing comma")); 3033 input_line_pointer++; 3034 3035#ifdef md_flush_pending_output 3036 md_flush_pending_output (); 3037#endif 3038 3039#ifdef md_cons_align 3040 md_cons_align (4); 3041#endif 3042 3043 mapping_state (MAP_DATA); 3044 3045 expression (&exp); 3046 3047 p = frag_more (4); 3048 md_number_to_chars (p, highbit, 4); 3049 fix_new_arm (frag_now, p - frag_now->fr_literal, 4, &exp, 1, 3050 BFD_RELOC_ARM_PREL31); 3051 3052 demand_empty_rest_of_line (); 3053} 3054 3055/* Directives: AEABI stack-unwind tables. */ 3056 3057/* Parse an unwind_fnstart directive. Simply records the current location. */ 3058 3059static void 3060s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED) 3061{ 3062 demand_empty_rest_of_line (); 3063 /* Mark the start of the function. */ 3064 unwind.proc_start = expr_build_dot (); 3065 3066 /* Reset the rest of the unwind info. */ 3067 unwind.opcode_count = 0; 3068 unwind.table_entry = NULL; 3069 unwind.personality_routine = NULL; 3070 unwind.personality_index = -1; 3071 unwind.frame_size = 0; 3072 unwind.fp_offset = 0; 3073 unwind.fp_reg = 13; 3074 unwind.fp_used = 0; 3075 unwind.sp_restored = 0; 3076} 3077 3078 3079/* Parse a handlerdata directive. Creates the exception handling table entry 3080 for the function. */ 3081 3082static void 3083s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED) 3084{ 3085 demand_empty_rest_of_line (); 3086 if (unwind.table_entry) 3087 as_bad (_("dupicate .handlerdata directive")); 3088 3089 create_unwind_entry (1); 3090} 3091 3092/* Parse an unwind_fnend directive. Generates the index table entry. */ 3093 3094static void 3095s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED) 3096{ 3097 long where; 3098 char *ptr; 3099 valueT val; 3100 3101 demand_empty_rest_of_line (); 3102 3103 /* Add eh table entry. */ 3104 if (unwind.table_entry == NULL) 3105 val = create_unwind_entry (0); 3106 else 3107 val = 0; 3108 3109 /* Add index table entry. This is two words. */ 3110 start_unwind_section (unwind.saved_seg, 1); 3111 frag_align (2, 0, 0); 3112 record_alignment (now_seg, 2); 3113 3114 ptr = frag_more (8); 3115 memset(ptr, 0, 8); 3116 where = frag_now_fix () - 8; 3117 3118 /* Self relative offset of the function start. */ 3119 fix_new (frag_now, where, 4, unwind.proc_start, 0, 1, 3120 BFD_RELOC_ARM_PREL31); 3121 3122 /* Indicate dependency on EHABI-defined personality routines to the 3123 linker, if it hasn't been done already. */ 3124 if (unwind.personality_index >= 0 && unwind.personality_index < 3 3125 && !(marked_pr_dependency & (1 << unwind.personality_index))) 3126 { 3127 static const char *const name[] = { 3128 "__aeabi_unwind_cpp_pr0", 3129 "__aeabi_unwind_cpp_pr1", 3130 "__aeabi_unwind_cpp_pr2" 3131 }; 3132 symbolS *pr = symbol_find_or_make (name[unwind.personality_index]); 3133 fix_new (frag_now, where, 0, pr, 0, 1, BFD_RELOC_NONE); 3134 marked_pr_dependency |= 1 << unwind.personality_index; 3135 seg_info (now_seg)->tc_segment_info_data.marked_pr_dependency 3136 = marked_pr_dependency; 3137 } 3138 3139 if (val) 3140 /* Inline exception table entry. */ 3141 md_number_to_chars (ptr + 4, val, 4); 3142 else 3143 /* Self relative offset of the table entry. */ 3144 fix_new (frag_now, where + 4, 4, unwind.table_entry, 0, 1, 3145 BFD_RELOC_ARM_PREL31); 3146 3147 /* Restore the original section. */ 3148 subseg_set (unwind.saved_seg, unwind.saved_subseg); 3149} 3150 3151 3152/* Parse an unwind_cantunwind directive. */ 3153 3154static void 3155s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED) 3156{ 3157 demand_empty_rest_of_line (); 3158 if (unwind.personality_routine || unwind.personality_index != -1) 3159 as_bad (_("personality routine specified for cantunwind frame")); 3160 3161 unwind.personality_index = -2; 3162} 3163 3164 3165/* Parse a personalityindex directive. */ 3166 3167static void 3168s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED) 3169{ 3170 expressionS exp; 3171 3172 if (unwind.personality_routine || unwind.personality_index != -1) 3173 as_bad (_("duplicate .personalityindex directive")); 3174 3175 expression (&exp); 3176 3177 if (exp.X_op != O_constant 3178 || exp.X_add_number < 0 || exp.X_add_number > 15) 3179 { 3180 as_bad (_("bad personality routine number")); 3181 ignore_rest_of_line (); 3182 return; 3183 } 3184 3185 unwind.personality_index = exp.X_add_number; 3186 3187 demand_empty_rest_of_line (); 3188} 3189 3190 3191/* Parse a personality directive. */ 3192 3193static void 3194s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED) 3195{ 3196 char *name, *p, c; 3197 3198 if (unwind.personality_routine || unwind.personality_index != -1) 3199 as_bad (_("duplicate .personality directive")); 3200 3201 name = input_line_pointer; 3202 c = get_symbol_end (); 3203 p = input_line_pointer; 3204 unwind.personality_routine = symbol_find_or_make (name); 3205 *p = c; 3206 demand_empty_rest_of_line (); 3207} 3208 3209 3210/* Parse a directive saving core registers. */ 3211 3212static void 3213s_arm_unwind_save_core (void) 3214{ 3215 valueT op; 3216 long range; 3217 int n; 3218 3219 range = parse_reg_list (&input_line_pointer); 3220 if (range == FAIL) 3221 { 3222 as_bad (_("expected register list")); 3223 ignore_rest_of_line (); 3224 return; 3225 } 3226 3227 demand_empty_rest_of_line (); 3228 3229 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...} 3230 into .unwind_save {..., sp...}. We aren't bothered about the value of 3231 ip because it is clobbered by calls. */ 3232 if (unwind.sp_restored && unwind.fp_reg == 12 3233 && (range & 0x3000) == 0x1000) 3234 { 3235 unwind.opcode_count--; 3236 unwind.sp_restored = 0; 3237 range = (range | 0x2000) & ~0x1000; 3238 unwind.pending_offset = 0; 3239 } 3240 3241 /* Pop r4-r15. */ 3242 if (range & 0xfff0) 3243 { 3244 /* See if we can use the short opcodes. These pop a block of up to 8 3245 registers starting with r4, plus maybe r14. */ 3246 for (n = 0; n < 8; n++) 3247 { 3248 /* Break at the first non-saved register. */ 3249 if ((range & (1 << (n + 4))) == 0) 3250 break; 3251 } 3252 /* See if there are any other bits set. */ 3253 if (n == 0 || (range & (0xfff0 << n) & 0xbff0) != 0) 3254 { 3255 /* Use the long form. */ 3256 op = 0x8000 | ((range >> 4) & 0xfff); 3257 add_unwind_opcode (op, 2); 3258 } 3259 else 3260 { 3261 /* Use the short form. */ 3262 if (range & 0x4000) 3263 op = 0xa8; /* Pop r14. */ 3264 else 3265 op = 0xa0; /* Do not pop r14. */ 3266 op |= (n - 1); 3267 add_unwind_opcode (op, 1); 3268 } 3269 } 3270 3271 /* Pop r0-r3. */ 3272 if (range & 0xf) 3273 { 3274 op = 0xb100 | (range & 0xf); 3275 add_unwind_opcode (op, 2); 3276 } 3277 3278 /* Record the number of bytes pushed. */ 3279 for (n = 0; n < 16; n++) 3280 { 3281 if (range & (1 << n)) 3282 unwind.frame_size += 4; 3283 } 3284} 3285 3286 3287/* Parse a directive saving FPA registers. */ 3288 3289static void 3290s_arm_unwind_save_fpa (int reg) 3291{ 3292 expressionS exp; 3293 int num_regs; 3294 valueT op; 3295 3296 /* Get Number of registers to transfer. */ 3297 if (skip_past_comma (&input_line_pointer) != FAIL) 3298 expression (&exp); 3299 else 3300 exp.X_op = O_illegal; 3301 3302 if (exp.X_op != O_constant) 3303 { 3304 as_bad (_("expected , <constant>")); 3305 ignore_rest_of_line (); 3306 return; 3307 } 3308 3309 num_regs = exp.X_add_number; 3310 3311 if (num_regs < 1 || num_regs > 4) 3312 { 3313 as_bad (_("number of registers must be in the range [1:4]")); 3314 ignore_rest_of_line (); 3315 return; 3316 } 3317 3318 demand_empty_rest_of_line (); 3319 3320 if (reg == 4) 3321 { 3322 /* Short form. */ 3323 op = 0xb4 | (num_regs - 1); 3324 add_unwind_opcode (op, 1); 3325 } 3326 else 3327 { 3328 /* Long form. */ 3329 op = 0xc800 | (reg << 4) | (num_regs - 1); 3330 add_unwind_opcode (op, 2); 3331 } 3332 unwind.frame_size += num_regs * 12; 3333} 3334 3335 3336/* Parse a directive saving VFP registers for ARMv6 and above. */ 3337 3338static void 3339s_arm_unwind_save_vfp_armv6 (void) 3340{ 3341 int count; 3342 unsigned int start; 3343 valueT op; 3344 int num_vfpv3_regs = 0; 3345 int num_regs_below_16; 3346 3347 count = parse_vfp_reg_list (&input_line_pointer, &start, REGLIST_VFP_D); 3348 if (count == FAIL) 3349 { 3350 as_bad (_("expected register list")); 3351 ignore_rest_of_line (); 3352 return; 3353 } 3354 3355 demand_empty_rest_of_line (); 3356 3357 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather 3358 than FSTMX/FLDMX-style ones). */ 3359 3360 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */ 3361 if (start >= 16) 3362 num_vfpv3_regs = count; 3363 else if (start + count > 16) 3364 num_vfpv3_regs = start + count - 16; 3365 3366 if (num_vfpv3_regs > 0) 3367 { 3368 int start_offset = start > 16 ? start - 16 : 0; 3369 op = 0xc800 | (start_offset << 4) | (num_vfpv3_regs - 1); 3370 add_unwind_opcode (op, 2); 3371 } 3372 3373 /* Generate opcode for registers numbered in the range 0 .. 15. */ 3374 num_regs_below_16 = num_vfpv3_regs > 0 ? 16 - (int) start : count; 3375 assert (num_regs_below_16 + num_vfpv3_regs == count); 3376 if (num_regs_below_16 > 0) 3377 { 3378 op = 0xc900 | (start << 4) | (num_regs_below_16 - 1); 3379 add_unwind_opcode (op, 2); 3380 } 3381 3382 unwind.frame_size += count * 8; 3383} 3384 3385 3386/* Parse a directive saving VFP registers for pre-ARMv6. */ 3387 3388static void 3389s_arm_unwind_save_vfp (void) 3390{ 3391 int count; 3392 unsigned int reg; 3393 valueT op; 3394 3395 count = parse_vfp_reg_list (&input_line_pointer, ®, REGLIST_VFP_D); 3396 if (count == FAIL) 3397 { 3398 as_bad (_("expected register list")); 3399 ignore_rest_of_line (); 3400 return; 3401 } 3402 3403 demand_empty_rest_of_line (); 3404 3405 if (reg == 8) 3406 { 3407 /* Short form. */ 3408 op = 0xb8 | (count - 1); 3409 add_unwind_opcode (op, 1); 3410 } 3411 else 3412 { 3413 /* Long form. */ 3414 op = 0xb300 | (reg << 4) | (count - 1); 3415 add_unwind_opcode (op, 2); 3416 } 3417 unwind.frame_size += count * 8 + 4; 3418} 3419 3420 3421/* Parse a directive saving iWMMXt data registers. */ 3422 3423static void 3424s_arm_unwind_save_mmxwr (void) 3425{ 3426 int reg; 3427 int hi_reg; 3428 int i; 3429 unsigned mask = 0; 3430 valueT op; 3431 3432 if (*input_line_pointer == '{') 3433 input_line_pointer++; 3434 3435 do 3436 { 3437 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR); 3438 3439 if (reg == FAIL) 3440 { 3441 as_bad (_(reg_expected_msgs[REG_TYPE_MMXWR])); 3442 goto error; 3443 } 3444 3445 if (mask >> reg) 3446 as_tsktsk (_("register list not in ascending order")); 3447 mask |= 1 << reg; 3448 3449 if (*input_line_pointer == '-') 3450 { 3451 input_line_pointer++; 3452 hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR); 3453 if (hi_reg == FAIL) 3454 { 3455 as_bad (_(reg_expected_msgs[REG_TYPE_MMXWR])); 3456 goto error; 3457 } 3458 else if (reg >= hi_reg) 3459 { 3460 as_bad (_("bad register range")); 3461 goto error; 3462 } 3463 for (; reg < hi_reg; reg++) 3464 mask |= 1 << reg; 3465 } 3466 } 3467 while (skip_past_comma (&input_line_pointer) != FAIL); 3468 3469 if (*input_line_pointer == '}') 3470 input_line_pointer++; 3471 3472 demand_empty_rest_of_line (); 3473 3474 /* Generate any deferred opcodes because we're going to be looking at 3475 the list. */ 3476 flush_pending_unwind (); 3477 3478 for (i = 0; i < 16; i++) 3479 { 3480 if (mask & (1 << i)) 3481 unwind.frame_size += 8; 3482 } 3483 3484 /* Attempt to combine with a previous opcode. We do this because gcc 3485 likes to output separate unwind directives for a single block of 3486 registers. */ 3487 if (unwind.opcode_count > 0) 3488 { 3489 i = unwind.opcodes[unwind.opcode_count - 1]; 3490 if ((i & 0xf8) == 0xc0) 3491 { 3492 i &= 7; 3493 /* Only merge if the blocks are contiguous. */ 3494 if (i < 6) 3495 { 3496 if ((mask & 0xfe00) == (1 << 9)) 3497 { 3498 mask |= ((1 << (i + 11)) - 1) & 0xfc00; 3499 unwind.opcode_count--; 3500 } 3501 } 3502 else if (i == 6 && unwind.opcode_count >= 2) 3503 { 3504 i = unwind.opcodes[unwind.opcode_count - 2]; 3505 reg = i >> 4; 3506 i &= 0xf; 3507 3508 op = 0xffff << (reg - 1); 3509 if (reg > 0 3510 && ((mask & op) == (1u << (reg - 1)))) 3511 { 3512 op = (1 << (reg + i + 1)) - 1; 3513 op &= ~((1 << reg) - 1); 3514 mask |= op; 3515 unwind.opcode_count -= 2; 3516 } 3517 } 3518 } 3519 } 3520 3521 hi_reg = 15; 3522 /* We want to generate opcodes in the order the registers have been 3523 saved, ie. descending order. */ 3524 for (reg = 15; reg >= -1; reg--) 3525 { 3526 /* Save registers in blocks. */ 3527 if (reg < 0 3528 || !(mask & (1 << reg))) 3529 { 3530 /* We found an unsaved reg. Generate opcodes to save the 3531 preceeding block. */ 3532 if (reg != hi_reg) 3533 { 3534 if (reg == 9) 3535 { 3536 /* Short form. */ 3537 op = 0xc0 | (hi_reg - 10); 3538 add_unwind_opcode (op, 1); 3539 } 3540 else 3541 { 3542 /* Long form. */ 3543 op = 0xc600 | ((reg + 1) << 4) | ((hi_reg - reg) - 1); 3544 add_unwind_opcode (op, 2); 3545 } 3546 } 3547 hi_reg = reg - 1; 3548 } 3549 } 3550 3551 return; 3552error: 3553 ignore_rest_of_line (); 3554} 3555 3556static void 3557s_arm_unwind_save_mmxwcg (void) 3558{ 3559 int reg; 3560 int hi_reg; 3561 unsigned mask = 0; 3562 valueT op; 3563 3564 if (*input_line_pointer == '{') 3565 input_line_pointer++; 3566 3567 do 3568 { 3569 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG); 3570 3571 if (reg == FAIL) 3572 { 3573 as_bad (_(reg_expected_msgs[REG_TYPE_MMXWCG])); 3574 goto error; 3575 } 3576 3577 reg -= 8; 3578 if (mask >> reg) 3579 as_tsktsk (_("register list not in ascending order")); 3580 mask |= 1 << reg; 3581 3582 if (*input_line_pointer == '-') 3583 { 3584 input_line_pointer++; 3585 hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG); 3586 if (hi_reg == FAIL) 3587 { 3588 as_bad (_(reg_expected_msgs[REG_TYPE_MMXWCG])); 3589 goto error; 3590 } 3591 else if (reg >= hi_reg) 3592 { 3593 as_bad (_("bad register range")); 3594 goto error; 3595 } 3596 for (; reg < hi_reg; reg++) 3597 mask |= 1 << reg; 3598 } 3599 } 3600 while (skip_past_comma (&input_line_pointer) != FAIL); 3601 3602 if (*input_line_pointer == '}') 3603 input_line_pointer++; 3604 3605 demand_empty_rest_of_line (); 3606 3607 /* Generate any deferred opcodes because we're going to be looking at 3608 the list. */ 3609 flush_pending_unwind (); 3610 3611 for (reg = 0; reg < 16; reg++) 3612 { 3613 if (mask & (1 << reg)) 3614 unwind.frame_size += 4; 3615 } 3616 op = 0xc700 | mask; 3617 add_unwind_opcode (op, 2); 3618 return; 3619error: 3620 ignore_rest_of_line (); 3621} 3622 3623 3624/* Parse an unwind_save directive. 3625 If the argument is non-zero, this is a .vsave directive. */ 3626 3627static void 3628s_arm_unwind_save (int arch_v6) 3629{ 3630 char *peek; 3631 struct reg_entry *reg; 3632 bfd_boolean had_brace = FALSE; 3633 3634 /* Figure out what sort of save we have. */ 3635 peek = input_line_pointer; 3636 3637 if (*peek == '{') 3638 { 3639 had_brace = TRUE; 3640 peek++; 3641 } 3642 3643 reg = arm_reg_parse_multi (&peek); 3644 3645 if (!reg) 3646 { 3647 as_bad (_("register expected")); 3648 ignore_rest_of_line (); 3649 return; 3650 } 3651 3652 switch (reg->type) 3653 { 3654 case REG_TYPE_FN: 3655 if (had_brace) 3656 { 3657 as_bad (_("FPA .unwind_save does not take a register list")); 3658 ignore_rest_of_line (); 3659 return; 3660 } 3661 s_arm_unwind_save_fpa (reg->number); 3662 return; 3663 3664 case REG_TYPE_RN: s_arm_unwind_save_core (); return; 3665 case REG_TYPE_VFD: 3666 if (arch_v6) 3667 s_arm_unwind_save_vfp_armv6 (); 3668 else 3669 s_arm_unwind_save_vfp (); 3670 return; 3671 case REG_TYPE_MMXWR: s_arm_unwind_save_mmxwr (); return; 3672 case REG_TYPE_MMXWCG: s_arm_unwind_save_mmxwcg (); return; 3673 3674 default: 3675 as_bad (_(".unwind_save does not support this kind of register")); 3676 ignore_rest_of_line (); 3677 } 3678} 3679 3680 3681/* Parse an unwind_movsp directive. */ 3682 3683static void 3684s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED) 3685{ 3686 int reg; 3687 valueT op; 3688 int offset; 3689 3690 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN); 3691 if (reg == FAIL) 3692 { 3693 as_bad (_(reg_expected_msgs[REG_TYPE_RN])); 3694 ignore_rest_of_line (); 3695 return; 3696 } 3697 3698 /* Optional constant. */ 3699 if (skip_past_comma (&input_line_pointer) != FAIL) 3700 { 3701 if (immediate_for_directive (&offset) == FAIL) 3702 return; 3703 } 3704 else 3705 offset = 0; 3706 3707 demand_empty_rest_of_line (); 3708 3709 if (reg == REG_SP || reg == REG_PC) 3710 { 3711 as_bad (_("SP and PC not permitted in .unwind_movsp directive")); 3712 return; 3713 } 3714 3715 if (unwind.fp_reg != REG_SP) 3716 as_bad (_("unexpected .unwind_movsp directive")); 3717 3718 /* Generate opcode to restore the value. */ 3719 op = 0x90 | reg; 3720 add_unwind_opcode (op, 1); 3721 3722 /* Record the information for later. */ 3723 unwind.fp_reg = reg; 3724 unwind.fp_offset = unwind.frame_size - offset; 3725 unwind.sp_restored = 1; 3726} 3727 3728/* Parse an unwind_pad directive. */ 3729 3730static void 3731s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED) 3732{ 3733 int offset; 3734 3735 if (immediate_for_directive (&offset) == FAIL) 3736 return; 3737 3738 if (offset & 3) 3739 { 3740 as_bad (_("stack increment must be multiple of 4")); 3741 ignore_rest_of_line (); 3742 return; 3743 } 3744 3745 /* Don't generate any opcodes, just record the details for later. */ 3746 unwind.frame_size += offset; 3747 unwind.pending_offset += offset; 3748 3749 demand_empty_rest_of_line (); 3750} 3751 3752/* Parse an unwind_setfp directive. */ 3753 3754static void 3755s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED) 3756{ 3757 int sp_reg; 3758 int fp_reg; 3759 int offset; 3760 3761 fp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN); 3762 if (skip_past_comma (&input_line_pointer) == FAIL) 3763 sp_reg = FAIL; 3764 else 3765 sp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN); 3766 3767 if (fp_reg == FAIL || sp_reg == FAIL) 3768 { 3769 as_bad (_("expected <reg>, <reg>")); 3770 ignore_rest_of_line (); 3771 return; 3772 } 3773 3774 /* Optional constant. */ 3775 if (skip_past_comma (&input_line_pointer) != FAIL) 3776 { 3777 if (immediate_for_directive (&offset) == FAIL) 3778 return; 3779 } 3780 else 3781 offset = 0; 3782 3783 demand_empty_rest_of_line (); 3784 3785 if (sp_reg != 13 && sp_reg != unwind.fp_reg) 3786 { 3787 as_bad (_("register must be either sp or set by a previous" 3788 "unwind_movsp directive")); 3789 return; 3790 } 3791 3792 /* Don't generate any opcodes, just record the information for later. */ 3793 unwind.fp_reg = fp_reg; 3794 unwind.fp_used = 1; 3795 if (sp_reg == 13) 3796 unwind.fp_offset = unwind.frame_size - offset; 3797 else 3798 unwind.fp_offset -= offset; 3799} 3800 3801/* Parse an unwind_raw directive. */ 3802 3803static void 3804s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED) 3805{ 3806 expressionS exp; 3807 /* This is an arbitrary limit. */ 3808 unsigned char op[16]; 3809 int count; 3810 3811 expression (&exp); 3812 if (exp.X_op == O_constant 3813 && skip_past_comma (&input_line_pointer) != FAIL) 3814 { 3815 unwind.frame_size += exp.X_add_number; 3816 expression (&exp); 3817 } 3818 else 3819 exp.X_op = O_illegal; 3820 3821 if (exp.X_op != O_constant) 3822 { 3823 as_bad (_("expected <offset>, <opcode>")); 3824 ignore_rest_of_line (); 3825 return; 3826 } 3827 3828 count = 0; 3829 3830 /* Parse the opcode. */ 3831 for (;;) 3832 { 3833 if (count >= 16) 3834 { 3835 as_bad (_("unwind opcode too long")); 3836 ignore_rest_of_line (); 3837 } 3838 if (exp.X_op != O_constant || exp.X_add_number & ~0xff) 3839 { 3840 as_bad (_("invalid unwind opcode")); 3841 ignore_rest_of_line (); 3842 return; 3843 } 3844 op[count++] = exp.X_add_number; 3845 3846 /* Parse the next byte. */ 3847 if (skip_past_comma (&input_line_pointer) == FAIL) 3848 break; 3849 3850 expression (&exp); 3851 } 3852 3853 /* Add the opcode bytes in reverse order. */ 3854 while (count--) 3855 add_unwind_opcode (op[count], 1); 3856 3857 demand_empty_rest_of_line (); 3858} 3859 3860 3861/* Parse a .eabi_attribute directive. */ 3862 3863static void 3864s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED) 3865{ 3866 s_vendor_attribute (OBJ_ATTR_PROC); 3867} 3868#endif /* OBJ_ELF */ 3869 3870static void s_arm_arch (int); 3871static void s_arm_object_arch (int); 3872static void s_arm_cpu (int); 3873static void s_arm_fpu (int); 3874static void s_arm_arch_extension (int); 3875 3876#ifdef TE_PE 3877 3878static void 3879pe_directive_secrel (int dummy ATTRIBUTE_UNUSED) 3880{ 3881 expressionS exp; 3882 3883 do 3884 { 3885 expression (&exp); 3886 if (exp.X_op == O_symbol) 3887 exp.X_op = O_secrel; 3888 3889 emit_expr (&exp, 4); 3890 } 3891 while (*input_line_pointer++ == ','); 3892 3893 input_line_pointer--; 3894 demand_empty_rest_of_line (); 3895} 3896#endif /* TE_PE */ 3897 3898/* This table describes all the machine specific pseudo-ops the assembler 3899 has to support. The fields are: 3900 pseudo-op name without dot 3901 function to call to execute this pseudo-op 3902 Integer arg to pass to the function. */ 3903 3904const pseudo_typeS md_pseudo_table[] = 3905{ 3906 /* Never called because '.req' does not start a line. */ 3907 { "req", s_req, 0 }, 3908 /* Following two are likewise never called. */ 3909 { "dn", s_dn, 0 }, 3910 { "qn", s_qn, 0 }, 3911 { "unreq", s_unreq, 0 }, 3912 { "bss", s_bss, 0 }, 3913 { "align", s_align, 0 }, 3914 { "arm", s_arm, 0 }, 3915 { "thumb", s_thumb, 0 }, 3916 { "code", s_code, 0 }, 3917 { "force_thumb", s_force_thumb, 0 }, 3918 { "thumb_func", s_thumb_func, 0 }, 3919 { "thumb_set", s_thumb_set, 0 }, 3920 { "even", s_even, 0 }, 3921 { "ltorg", s_ltorg, 0 }, 3922 { "pool", s_ltorg, 0 }, 3923 { "syntax", s_syntax, 0 }, 3924 { "cpu", s_arm_cpu, 0 }, 3925 { "arch", s_arm_arch, 0 }, 3926 { "object_arch", s_arm_object_arch, 0 }, 3927 { "fpu", s_arm_fpu, 0 }, 3928 { "arch_extension", s_arm_arch_extension, 0 }, 3929 { "inst", s_inst, 0 }, 3930#ifdef OBJ_ELF 3931 { "word", s_arm_elf_cons, 4 }, 3932 { "long", s_arm_elf_cons, 4 }, 3933 { "rel31", s_arm_rel31, 0 }, 3934 { "fnstart", s_arm_unwind_fnstart, 0 }, 3935 { "fnend", s_arm_unwind_fnend, 0 }, 3936 { "cantunwind", s_arm_unwind_cantunwind, 0 }, 3937 { "personality", s_arm_unwind_personality, 0 }, 3938 { "personalityindex", s_arm_unwind_personalityindex, 0 }, 3939 { "handlerdata", s_arm_unwind_handlerdata, 0 }, 3940 { "save", s_arm_unwind_save, 0 }, 3941 { "vsave", s_arm_unwind_save, 1 }, 3942 { "movsp", s_arm_unwind_movsp, 0 }, 3943 { "pad", s_arm_unwind_pad, 0 }, 3944 { "setfp", s_arm_unwind_setfp, 0 }, 3945 { "unwind_raw", s_arm_unwind_raw, 0 }, 3946 { "eabi_attribute", s_arm_eabi_attribute, 0 }, 3947#else 3948 { "word", cons, 4}, 3949 3950 /* These are used for dwarf. */ 3951 {"2byte", cons, 2}, 3952 {"4byte", cons, 4}, 3953 {"8byte", cons, 8}, 3954 /* These are used for dwarf2. */ 3955 { "file", (void (*) (int)) dwarf2_directive_file, 0 }, 3956 { "loc", dwarf2_directive_loc, 0 }, 3957 { "loc_mark_labels", dwarf2_directive_loc_mark_labels, 0 }, 3958#endif 3959 { "extend", float_cons, 'x' }, 3960 { "ldouble", float_cons, 'x' }, 3961 { "packed", float_cons, 'p' }, 3962#ifdef TE_PE 3963 {"secrel32", pe_directive_secrel, 0}, 3964#endif 3965 { 0, 0, 0 } 3966}; 3967 3968/* Parser functions used exclusively in instruction operands. */ 3969 3970/* Generic immediate-value read function for use in insn parsing. 3971 STR points to the beginning of the immediate (the leading #); 3972 VAL receives the value; if the value is outside [MIN, MAX] 3973 issue an error. PREFIX_OPT is true if the immediate prefix is 3974 optional. */ 3975 3976static int 3977parse_immediate (char **str, int *val, int min, int max, 3978 bfd_boolean prefix_opt) 3979{ 3980 expressionS exp; 3981 my_get_expression (&exp, str, prefix_opt ? GE_OPT_PREFIX : GE_IMM_PREFIX); 3982 if (exp.X_op != O_constant) 3983 { 3984 inst.error = _("constant expression required"); 3985 return FAIL; 3986 } 3987 3988 if (exp.X_add_number < min || exp.X_add_number > max) 3989 { 3990 inst.error = _("immediate value out of range"); 3991 return FAIL; 3992 } 3993 3994 *val = exp.X_add_number; 3995 return SUCCESS; 3996} 3997 3998/* Less-generic immediate-value read function with the possibility of loading a 3999 big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate 4000 instructions. Puts the result directly in inst.operands[i]. */ 4001 4002static int 4003parse_big_immediate (char **str, int i) 4004{ 4005 expressionS exp; 4006 char *ptr = *str; 4007 4008 my_get_expression (&exp, &ptr, GE_OPT_PREFIX_BIG); 4009 4010 if (exp.X_op == O_constant) 4011 { 4012 inst.operands[i].imm = exp.X_add_number & 0xffffffff; 4013 /* If we're on a 64-bit host, then a 64-bit number can be returned using 4014 O_constant. We have to be careful not to break compilation for 4015 32-bit X_add_number, though. */ 4016 if ((exp.X_add_number & ~0xffffffffl) != 0) 4017 { 4018 /* X >> 32 is illegal if sizeof (exp.X_add_number) == 4. */ 4019 inst.operands[i].reg = ((exp.X_add_number >> 16) >> 16) & 0xffffffff; 4020 inst.operands[i].regisimm = 1; 4021 } 4022 } 4023 else if (exp.X_op == O_big 4024 && LITTLENUM_NUMBER_OF_BITS * exp.X_add_number > 32 4025 && LITTLENUM_NUMBER_OF_BITS * exp.X_add_number <= 64) 4026 { 4027 unsigned parts = 32 / LITTLENUM_NUMBER_OF_BITS, j, idx = 0; 4028 /* Bignums have their least significant bits in 4029 generic_bignum[0]. Make sure we put 32 bits in imm and 4030 32 bits in reg, in a (hopefully) portable way. */ 4031 assert (parts != 0); 4032 inst.operands[i].imm = 0; 4033 for (j = 0; j < parts; j++, idx++) 4034 inst.operands[i].imm |= generic_bignum[idx] 4035 << (LITTLENUM_NUMBER_OF_BITS * j); 4036 inst.operands[i].reg = 0; 4037 for (j = 0; j < parts; j++, idx++) 4038 inst.operands[i].reg |= generic_bignum[idx] 4039 << (LITTLENUM_NUMBER_OF_BITS * j); 4040 inst.operands[i].regisimm = 1; 4041 } 4042 else 4043 return FAIL; 4044 4045 *str = ptr; 4046 4047 return SUCCESS; 4048} 4049 4050/* Returns the pseudo-register number of an FPA immediate constant, 4051 or FAIL if there isn't a valid constant here. */ 4052 4053static int 4054parse_fpa_immediate (char ** str) 4055{ 4056 LITTLENUM_TYPE words[MAX_LITTLENUMS]; 4057 char * save_in; 4058 expressionS exp; 4059 int i; 4060 int j; 4061 4062 /* First try and match exact strings, this is to guarantee 4063 that some formats will work even for cross assembly. */ 4064 4065 for (i = 0; fp_const[i]; i++) 4066 { 4067 if (strncmp (*str, fp_const[i], strlen (fp_const[i])) == 0) 4068 { 4069 char *start = *str; 4070 4071 *str += strlen (fp_const[i]); 4072 if (is_end_of_line[(unsigned char) **str]) 4073 return i + 8; 4074 *str = start; 4075 } 4076 } 4077 4078 /* Just because we didn't get a match doesn't mean that the constant 4079 isn't valid, just that it is in a format that we don't 4080 automatically recognize. Try parsing it with the standard 4081 expression routines. */ 4082 4083 memset (words, 0, MAX_LITTLENUMS * sizeof (LITTLENUM_TYPE)); 4084 4085 /* Look for a raw floating point number. */ 4086 if ((save_in = atof_ieee (*str, 'x', words)) != NULL 4087 && is_end_of_line[(unsigned char) *save_in]) 4088 { 4089 for (i = 0; i < NUM_FLOAT_VALS; i++) 4090 { 4091 for (j = 0; j < MAX_LITTLENUMS; j++) 4092 { 4093 if (words[j] != fp_values[i][j]) 4094 break; 4095 } 4096 4097 if (j == MAX_LITTLENUMS) 4098 { 4099 *str = save_in; 4100 return i + 8; 4101 } 4102 } 4103 } 4104 4105 /* Try and parse a more complex expression, this will probably fail 4106 unless the code uses a floating point prefix (eg "0f"). */ 4107 save_in = input_line_pointer; 4108 input_line_pointer = *str; 4109 if (expression (&exp) == absolute_section 4110 && exp.X_op == O_big 4111 && exp.X_add_number < 0) 4112 { 4113 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it. 4114 Ditto for 15. */ 4115 if (gen_to_words (words, 5, (long) 15) == 0) 4116 { 4117 for (i = 0; i < NUM_FLOAT_VALS; i++) 4118 { 4119 for (j = 0; j < MAX_LITTLENUMS; j++) 4120 { 4121 if (words[j] != fp_values[i][j]) 4122 break; 4123 } 4124 4125 if (j == MAX_LITTLENUMS) 4126 { 4127 *str = input_line_pointer; 4128 input_line_pointer = save_in; 4129 return i + 8; 4130 } 4131 } 4132 } 4133 } 4134 4135 *str = input_line_pointer; 4136 input_line_pointer = save_in; 4137 inst.error = _("invalid FPA immediate expression"); 4138 return FAIL; 4139} 4140 4141/* Returns 1 if a number has "quarter-precision" float format 4142 0baBbbbbbc defgh000 00000000 00000000. */ 4143 4144static int 4145is_quarter_float (unsigned imm) 4146{ 4147 int bs = (imm & 0x20000000) ? 0x3e000000 : 0x40000000; 4148 return (imm & 0x7ffff) == 0 && ((imm & 0x7e000000) ^ bs) == 0; 4149} 4150 4151/* Parse an 8-bit "quarter-precision" floating point number of the form: 4152 0baBbbbbbc defgh000 00000000 00000000. 4153 The zero and minus-zero cases need special handling, since they can't be 4154 encoded in the "quarter-precision" float format, but can nonetheless be 4155 loaded as integer constants. */ 4156 4157static unsigned 4158parse_qfloat_immediate (char **ccp, int *immed) 4159{ 4160 char *str = *ccp; 4161 char *fpnum; 4162 LITTLENUM_TYPE words[MAX_LITTLENUMS]; 4163 int found_fpchar = 0; 4164 4165 skip_past_char (&str, '#'); 4166 4167 /* We must not accidentally parse an integer as a floating-point number. Make 4168 sure that the value we parse is not an integer by checking for special 4169 characters '.' or 'e'. 4170 FIXME: This is a horrible hack, but doing better is tricky because type 4171 information isn't in a very usable state at parse time. */ 4172 fpnum = str; 4173 skip_whitespace (fpnum); 4174 4175 if (strncmp (fpnum, "0x", 2) == 0) 4176 return FAIL; 4177 else 4178 { 4179 for (; *fpnum != '\0' && *fpnum != ' ' && *fpnum != '\n'; fpnum++) 4180 if (*fpnum == '.' || *fpnum == 'e' || *fpnum == 'E') 4181 { 4182 found_fpchar = 1; 4183 break; 4184 } 4185 4186 if (!found_fpchar) 4187 return FAIL; 4188 } 4189 4190 if ((str = atof_ieee (str, 's', words)) != NULL) 4191 { 4192 unsigned fpword = 0; 4193 int i; 4194 4195 /* Our FP word must be 32 bits (single-precision FP). */ 4196 for (i = 0; i < 32 / LITTLENUM_NUMBER_OF_BITS; i++) 4197 { 4198 fpword <<= LITTLENUM_NUMBER_OF_BITS; 4199 fpword |= words[i]; 4200 } 4201 4202 if (is_quarter_float (fpword) || (fpword & 0x7fffffff) == 0) 4203 *immed = fpword; 4204 else 4205 return FAIL; 4206 4207 *ccp = str; 4208 4209 return SUCCESS; 4210 } 4211 4212 return FAIL; 4213} 4214 4215/* Shift operands. */ 4216enum shift_kind 4217{ 4218 SHIFT_LSL, SHIFT_LSR, SHIFT_ASR, SHIFT_ROR, SHIFT_RRX 4219}; 4220 4221struct asm_shift_name 4222{ 4223 const char *name; 4224 enum shift_kind kind; 4225}; 4226 4227/* Third argument to parse_shift. */ 4228enum parse_shift_mode 4229{ 4230 NO_SHIFT_RESTRICT, /* Any kind of shift is accepted. */ 4231 SHIFT_IMMEDIATE, /* Shift operand must be an immediate. */ 4232 SHIFT_LSL_OR_ASR_IMMEDIATE, /* Shift must be LSL or ASR immediate. */ 4233 SHIFT_ASR_IMMEDIATE, /* Shift must be ASR immediate. */ 4234 SHIFT_LSL_IMMEDIATE, /* Shift must be LSL immediate. */ 4235}; 4236 4237/* Parse a <shift> specifier on an ARM data processing instruction. 4238 This has three forms: 4239 4240 (LSL|LSR|ASL|ASR|ROR) Rs 4241 (LSL|LSR|ASL|ASR|ROR) #imm 4242 RRX 4243 4244 Note that ASL is assimilated to LSL in the instruction encoding, and 4245 RRX to ROR #0 (which cannot be written as such). */ 4246 4247static int 4248parse_shift (char **str, int i, enum parse_shift_mode mode) 4249{ 4250 const struct asm_shift_name *shift_name; 4251 enum shift_kind shift; 4252 char *s = *str; 4253 char *p = s; 4254 int reg; 4255 4256 for (p = *str; ISALPHA (*p); p++) 4257 ; 4258 4259 if (p == *str) 4260 { 4261 inst.error = _("shift expression expected"); 4262 return FAIL; 4263 } 4264 4265 shift_name = hash_find_n (arm_shift_hsh, *str, p - *str); 4266 4267 if (shift_name == NULL) 4268 { 4269 inst.error = _("shift expression expected"); 4270 return FAIL; 4271 } 4272 4273 shift = shift_name->kind; 4274 4275 switch (mode) 4276 { 4277 case NO_SHIFT_RESTRICT: 4278 case SHIFT_IMMEDIATE: break; 4279 4280 case SHIFT_LSL_OR_ASR_IMMEDIATE: 4281 if (shift != SHIFT_LSL && shift != SHIFT_ASR) 4282 { 4283 inst.error = _("'LSL' or 'ASR' required"); 4284 return FAIL; 4285 } 4286 break; 4287 4288 case SHIFT_LSL_IMMEDIATE: 4289 if (shift != SHIFT_LSL) 4290 { 4291 inst.error = _("'LSL' required"); 4292 return FAIL; 4293 } 4294 break; 4295 4296 case SHIFT_ASR_IMMEDIATE: 4297 if (shift != SHIFT_ASR) 4298 { 4299 inst.error = _("'ASR' required"); 4300 return FAIL; 4301 } 4302 break; 4303 4304 default: abort (); 4305 } 4306 4307 if (shift != SHIFT_RRX) 4308 { 4309 /* Whitespace can appear here if the next thing is a bare digit. */ 4310 skip_whitespace (p); 4311 4312 if (mode == NO_SHIFT_RESTRICT 4313 && (reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL) 4314 { 4315 inst.operands[i].imm = reg; 4316 inst.operands[i].immisreg = 1; 4317 } 4318 else if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX)) 4319 return FAIL; 4320 } 4321 inst.operands[i].shift_kind = shift; 4322 inst.operands[i].shifted = 1; 4323 *str = p; 4324 return SUCCESS; 4325} 4326 4327/* Parse a <shifter_operand> for an ARM data processing instruction: 4328 4329 #<immediate> 4330 #<immediate>, <rotate> 4331 <Rm> 4332 <Rm>, <shift> 4333 4334 where <shift> is defined by parse_shift above, and <rotate> is a 4335 multiple of 2 between 0 and 30. Validation of immediate operands 4336 is deferred to md_apply_fix. */ 4337 4338static int 4339parse_shifter_operand (char **str, int i) 4340{ 4341 int value; 4342 expressionS expr; 4343 4344 if ((value = arm_reg_parse (str, REG_TYPE_RN)) != FAIL) 4345 { 4346 inst.operands[i].reg = value; 4347 inst.operands[i].isreg = 1; 4348 4349 /* parse_shift will override this if appropriate */ 4350 inst.reloc.exp.X_op = O_constant; 4351 inst.reloc.exp.X_add_number = 0; 4352 4353 if (skip_past_comma (str) == FAIL) 4354 return SUCCESS; 4355 4356 /* Shift operation on register. */ 4357 return parse_shift (str, i, NO_SHIFT_RESTRICT); 4358 } 4359 4360 if (my_get_expression (&inst.reloc.exp, str, GE_IMM_PREFIX)) 4361 return FAIL; 4362 4363 if (skip_past_comma (str) == SUCCESS) 4364 { 4365 /* #x, y -- ie explicit rotation by Y. */ 4366 if (my_get_expression (&expr, str, GE_NO_PREFIX)) 4367 return FAIL; 4368 4369 if (expr.X_op != O_constant || inst.reloc.exp.X_op != O_constant) 4370 { 4371 inst.error = _("constant expression expected"); 4372 return FAIL; 4373 } 4374 4375 value = expr.X_add_number; 4376 if (value < 0 || value > 30 || value % 2 != 0) 4377 { 4378 inst.error = _("invalid rotation"); 4379 return FAIL; 4380 } 4381 if (inst.reloc.exp.X_add_number < 0 || inst.reloc.exp.X_add_number > 255) 4382 { 4383 inst.error = _("invalid constant"); 4384 return FAIL; 4385 } 4386 4387 /* Convert to decoded value. md_apply_fix will put it back. */ 4388 inst.reloc.exp.X_add_number 4389 = (((inst.reloc.exp.X_add_number << (32 - value)) 4390 | (inst.reloc.exp.X_add_number >> value)) & 0xffffffff); 4391 } 4392 4393 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE; 4394 inst.reloc.pc_rel = 0; 4395 return SUCCESS; 4396} 4397 4398/* Group relocation information. Each entry in the table contains the 4399 textual name of the relocation as may appear in assembler source 4400 and must end with a colon. 4401 Along with this textual name are the relocation codes to be used if 4402 the corresponding instruction is an ALU instruction (ADD or SUB only), 4403 an LDR, an LDRS, or an LDC. */ 4404 4405struct group_reloc_table_entry 4406{ 4407 const char *name; 4408 int alu_code; 4409 int ldr_code; 4410 int ldrs_code; 4411 int ldc_code; 4412}; 4413 4414typedef enum 4415{ 4416 /* Varieties of non-ALU group relocation. */ 4417 4418 GROUP_LDR, 4419 GROUP_LDRS, 4420 GROUP_LDC 4421} group_reloc_type; 4422 4423static struct group_reloc_table_entry group_reloc_table[] = 4424 { /* Program counter relative: */ 4425 { "pc_g0_nc", 4426 BFD_RELOC_ARM_ALU_PC_G0_NC, /* ALU */ 4427 0, /* LDR */ 4428 0, /* LDRS */ 4429 0 }, /* LDC */ 4430 { "pc_g0", 4431 BFD_RELOC_ARM_ALU_PC_G0, /* ALU */ 4432 BFD_RELOC_ARM_LDR_PC_G0, /* LDR */ 4433 BFD_RELOC_ARM_LDRS_PC_G0, /* LDRS */ 4434 BFD_RELOC_ARM_LDC_PC_G0 }, /* LDC */ 4435 { "pc_g1_nc", 4436 BFD_RELOC_ARM_ALU_PC_G1_NC, /* ALU */ 4437 0, /* LDR */ 4438 0, /* LDRS */ 4439 0 }, /* LDC */ 4440 { "pc_g1", 4441 BFD_RELOC_ARM_ALU_PC_G1, /* ALU */ 4442 BFD_RELOC_ARM_LDR_PC_G1, /* LDR */ 4443 BFD_RELOC_ARM_LDRS_PC_G1, /* LDRS */ 4444 BFD_RELOC_ARM_LDC_PC_G1 }, /* LDC */ 4445 { "pc_g2", 4446 BFD_RELOC_ARM_ALU_PC_G2, /* ALU */ 4447 BFD_RELOC_ARM_LDR_PC_G2, /* LDR */ 4448 BFD_RELOC_ARM_LDRS_PC_G2, /* LDRS */ 4449 BFD_RELOC_ARM_LDC_PC_G2 }, /* LDC */ 4450 /* Section base relative */ 4451 { "sb_g0_nc", 4452 BFD_RELOC_ARM_ALU_SB_G0_NC, /* ALU */ 4453 0, /* LDR */ 4454 0, /* LDRS */ 4455 0 }, /* LDC */ 4456 { "sb_g0", 4457 BFD_RELOC_ARM_ALU_SB_G0, /* ALU */ 4458 BFD_RELOC_ARM_LDR_SB_G0, /* LDR */ 4459 BFD_RELOC_ARM_LDRS_SB_G0, /* LDRS */ 4460 BFD_RELOC_ARM_LDC_SB_G0 }, /* LDC */ 4461 { "sb_g1_nc", 4462 BFD_RELOC_ARM_ALU_SB_G1_NC, /* ALU */ 4463 0, /* LDR */ 4464 0, /* LDRS */ 4465 0 }, /* LDC */ 4466 { "sb_g1", 4467 BFD_RELOC_ARM_ALU_SB_G1, /* ALU */ 4468 BFD_RELOC_ARM_LDR_SB_G1, /* LDR */ 4469 BFD_RELOC_ARM_LDRS_SB_G1, /* LDRS */ 4470 BFD_RELOC_ARM_LDC_SB_G1 }, /* LDC */ 4471 { "sb_g2", 4472 BFD_RELOC_ARM_ALU_SB_G2, /* ALU */ 4473 BFD_RELOC_ARM_LDR_SB_G2, /* LDR */ 4474 BFD_RELOC_ARM_LDRS_SB_G2, /* LDRS */ 4475 BFD_RELOC_ARM_LDC_SB_G2 } }; /* LDC */ 4476 4477/* Given the address of a pointer pointing to the textual name of a group 4478 relocation as may appear in assembler source, attempt to find its details 4479 in group_reloc_table. The pointer will be updated to the character after 4480 the trailing colon. On failure, FAIL will be returned; SUCCESS 4481 otherwise. On success, *entry will be updated to point at the relevant 4482 group_reloc_table entry. */ 4483 4484static int 4485find_group_reloc_table_entry (char **str, struct group_reloc_table_entry **out) 4486{ 4487 unsigned int i; 4488 for (i = 0; i < ARRAY_SIZE (group_reloc_table); i++) 4489 { 4490 int length = strlen (group_reloc_table[i].name); 4491 4492 if (strncasecmp (group_reloc_table[i].name, *str, length) == 0 && 4493 (*str)[length] == ':') 4494 { 4495 *out = &group_reloc_table[i]; 4496 *str += (length + 1); 4497 return SUCCESS; 4498 } 4499 } 4500 4501 return FAIL; 4502} 4503 4504/* Parse a <shifter_operand> for an ARM data processing instruction 4505 (as for parse_shifter_operand) where group relocations are allowed: 4506 4507 #<immediate> 4508 #<immediate>, <rotate> 4509 #:<group_reloc>:<expression> 4510 <Rm> 4511 <Rm>, <shift> 4512 4513 where <group_reloc> is one of the strings defined in group_reloc_table. 4514 The hashes are optional. 4515 4516 Everything else is as for parse_shifter_operand. */ 4517 4518static parse_operand_result 4519parse_shifter_operand_group_reloc (char **str, int i) 4520{ 4521 /* Determine if we have the sequence of characters #: or just : 4522 coming next. If we do, then we check for a group relocation. 4523 If we don't, punt the whole lot to parse_shifter_operand. */ 4524 4525 if (((*str)[0] == '#' && (*str)[1] == ':') 4526 || (*str)[0] == ':') 4527 { 4528 struct group_reloc_table_entry *entry; 4529 4530 if ((*str)[0] == '#') 4531 (*str) += 2; 4532 else 4533 (*str)++; 4534 4535 /* Try to parse a group relocation. Anything else is an error. */ 4536 if (find_group_reloc_table_entry (str, &entry) == FAIL) 4537 { 4538 inst.error = _("unknown group relocation"); 4539 return PARSE_OPERAND_FAIL_NO_BACKTRACK; 4540 } 4541 4542 /* We now have the group relocation table entry corresponding to 4543 the name in the assembler source. Next, we parse the expression. */ 4544 if (my_get_expression (&inst.reloc.exp, str, GE_NO_PREFIX)) 4545 return PARSE_OPERAND_FAIL_NO_BACKTRACK; 4546 4547 /* Record the relocation type (always the ALU variant here). */ 4548 inst.reloc.type = entry->alu_code; 4549 assert (inst.reloc.type != 0); 4550 4551 return PARSE_OPERAND_SUCCESS; 4552 } 4553 else 4554 return parse_shifter_operand (str, i) == SUCCESS 4555 ? PARSE_OPERAND_SUCCESS : PARSE_OPERAND_FAIL; 4556 4557 /* Never reached. */ 4558} 4559 4560/* Parse all forms of an ARM address expression. Information is written 4561 to inst.operands[i] and/or inst.reloc. 4562 4563 Preindexed addressing (.preind=1): 4564 4565 [Rn, #offset] .reg=Rn .reloc.exp=offset 4566 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1 4567 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1 4568 .shift_kind=shift .reloc.exp=shift_imm 4569 4570 These three may have a trailing ! which causes .writeback to be set also. 4571 4572 Postindexed addressing (.postind=1, .writeback=1): 4573 4574 [Rn], #offset .reg=Rn .reloc.exp=offset 4575 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1 4576 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1 4577 .shift_kind=shift .reloc.exp=shift_imm 4578 4579 Unindexed addressing (.preind=0, .postind=0): 4580 4581 [Rn], {option} .reg=Rn .imm=option .immisreg=0 4582 4583 Other: 4584 4585 [Rn]{!} shorthand for [Rn,#0]{!} 4586 =immediate .isreg=0 .reloc.exp=immediate 4587 label .reg=PC .reloc.pc_rel=1 .reloc.exp=label 4588 4589 It is the caller's responsibility to check for addressing modes not 4590 supported by the instruction, and to set inst.reloc.type. */ 4591 4592static parse_operand_result 4593parse_address_main (char **str, int i, int group_relocations, 4594 group_reloc_type group_type) 4595{ 4596 char *p = *str; 4597 int reg; 4598 4599 if (skip_past_char (&p, '[') == FAIL) 4600 { 4601 if (skip_past_char (&p, '=') == FAIL) 4602 { 4603 /* bare address - translate to PC-relative offset */ 4604 inst.reloc.pc_rel = 1; 4605 inst.operands[i].reg = REG_PC; 4606 inst.operands[i].isreg = 1; 4607 inst.operands[i].preind = 1; 4608 } 4609 /* else a load-constant pseudo op, no special treatment needed here */ 4610 4611 if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX)) 4612 return PARSE_OPERAND_FAIL; 4613 4614 *str = p; 4615 return PARSE_OPERAND_SUCCESS; 4616 } 4617 4618 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL) 4619 { 4620 inst.error = _(reg_expected_msgs[REG_TYPE_RN]); 4621 return PARSE_OPERAND_FAIL; 4622 } 4623 inst.operands[i].reg = reg; 4624 inst.operands[i].isreg = 1; 4625 4626 if (skip_past_comma (&p) == SUCCESS) 4627 { 4628 inst.operands[i].preind = 1; 4629 4630 if (*p == '+') p++; 4631 else if (*p == '-') p++, inst.operands[i].negative = 1; 4632 4633 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL) 4634 { 4635 inst.operands[i].imm = reg; 4636 inst.operands[i].immisreg = 1; 4637 4638 if (skip_past_comma (&p) == SUCCESS) 4639 if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL) 4640 return PARSE_OPERAND_FAIL; 4641 } 4642 else if (skip_past_char (&p, ':') == SUCCESS) 4643 { 4644 /* FIXME: '@' should be used here, but it's filtered out by generic 4645 code before we get to see it here. This may be subject to 4646 change. */ 4647 expressionS exp; 4648 my_get_expression (&exp, &p, GE_NO_PREFIX); 4649 if (exp.X_op != O_constant) 4650 { 4651 inst.error = _("alignment must be constant"); 4652 return PARSE_OPERAND_FAIL; 4653 } 4654 inst.operands[i].imm = exp.X_add_number << 8; 4655 inst.operands[i].immisalign = 1; 4656 /* Alignments are not pre-indexes. */ 4657 inst.operands[i].preind = 0; 4658 } 4659 else 4660 { 4661 if (inst.operands[i].negative) 4662 { 4663 inst.operands[i].negative = 0; 4664 p--; 4665 } 4666 4667 if (group_relocations && 4668 ((*p == '#' && *(p + 1) == ':') || *p == ':')) 4669 4670 { 4671 struct group_reloc_table_entry *entry; 4672 4673 /* Skip over the #: or : sequence. */ 4674 if (*p == '#') 4675 p += 2; 4676 else 4677 p++; 4678 4679 /* Try to parse a group relocation. Anything else is an 4680 error. */ 4681 if (find_group_reloc_table_entry (&p, &entry) == FAIL) 4682 { 4683 inst.error = _("unknown group relocation"); 4684 return PARSE_OPERAND_FAIL_NO_BACKTRACK; 4685 } 4686 4687 /* We now have the group relocation table entry corresponding to 4688 the name in the assembler source. Next, we parse the 4689 expression. */ 4690 if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX)) 4691 return PARSE_OPERAND_FAIL_NO_BACKTRACK; 4692 4693 /* Record the relocation type. */ 4694 switch (group_type) 4695 { 4696 case GROUP_LDR: 4697 inst.reloc.type = entry->ldr_code; 4698 break; 4699 4700 case GROUP_LDRS: 4701 inst.reloc.type = entry->ldrs_code; 4702 break; 4703 4704 case GROUP_LDC: 4705 inst.reloc.type = entry->ldc_code; 4706 break; 4707 4708 default: 4709 assert (0); 4710 } 4711 4712 if (inst.reloc.type == 0) 4713 { 4714 inst.error = _("this group relocation is not allowed on this instruction"); 4715 return PARSE_OPERAND_FAIL_NO_BACKTRACK; 4716 } 4717 } 4718 else 4719 if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX)) 4720 return PARSE_OPERAND_FAIL; 4721 } 4722 } 4723 else if (skip_past_char (&p, ':') == SUCCESS) 4724 { 4725 /* FIXME: '@' should be used here, but it's filtered out by generic 4726 code before we get to see it here. This may be subject to 4727 change. */ 4728 expressionS exp; 4729 my_get_expression (&exp, &p, GE_NO_PREFIX); 4730 if (exp.X_op != O_constant) 4731 { 4732 inst.error = _("alignment must be constant"); 4733 return PARSE_OPERAND_FAIL; 4734 } 4735 inst.operands[i].imm = exp.X_add_number << 8; 4736 inst.operands[i].immisalign = 1; 4737 /* Alignments are not pre-indexes. */ 4738 inst.operands[i].preind = 0; 4739 } 4740 4741 if (skip_past_char (&p, ']') == FAIL) 4742 { 4743 inst.error = _("']' expected"); 4744 return PARSE_OPERAND_FAIL; 4745 } 4746 4747 if (skip_past_char (&p, '!') == SUCCESS) 4748 inst.operands[i].writeback = 1; 4749 4750 else if (skip_past_comma (&p) == SUCCESS) 4751 { 4752 if (skip_past_char (&p, '{') == SUCCESS) 4753 { 4754 /* [Rn], {expr} - unindexed, with option */ 4755 if (parse_immediate (&p, &inst.operands[i].imm, 4756 0, 255, TRUE) == FAIL) 4757 return PARSE_OPERAND_FAIL; 4758 4759 if (skip_past_char (&p, '}') == FAIL) 4760 { 4761 inst.error = _("'}' expected at end of 'option' field"); 4762 return PARSE_OPERAND_FAIL; 4763 } 4764 if (inst.operands[i].preind) 4765 { 4766 inst.error = _("cannot combine index with option"); 4767 return PARSE_OPERAND_FAIL; 4768 } 4769 *str = p; 4770 return PARSE_OPERAND_SUCCESS; 4771 } 4772 else 4773 { 4774 inst.operands[i].postind = 1; 4775 inst.operands[i].writeback = 1; 4776 4777 if (inst.operands[i].preind) 4778 { 4779 inst.error = _("cannot combine pre- and post-indexing"); 4780 return PARSE_OPERAND_FAIL; 4781 } 4782 4783 if (*p == '+') p++; 4784 else if (*p == '-') p++, inst.operands[i].negative = 1; 4785 4786 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL) 4787 { 4788 /* We might be using the immediate for alignment already. If we 4789 are, OR the register number into the low-order bits. */ 4790 if (inst.operands[i].immisalign) 4791 inst.operands[i].imm |= reg; 4792 else 4793 inst.operands[i].imm = reg; 4794 inst.operands[i].immisreg = 1; 4795 4796 if (skip_past_comma (&p) == SUCCESS) 4797 if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL) 4798 return PARSE_OPERAND_FAIL; 4799 } 4800 else 4801 { 4802 if (inst.operands[i].negative) 4803 { 4804 inst.operands[i].negative = 0; 4805 p--; 4806 } 4807 if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX)) 4808 return PARSE_OPERAND_FAIL; 4809 } 4810 } 4811 } 4812 4813 /* If at this point neither .preind nor .postind is set, we have a 4814 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */ 4815 if (inst.operands[i].preind == 0 && inst.operands[i].postind == 0) 4816 { 4817 inst.operands[i].preind = 1; 4818 inst.reloc.exp.X_op = O_constant; 4819 inst.reloc.exp.X_add_number = 0; 4820 } 4821 *str = p; 4822 return PARSE_OPERAND_SUCCESS; 4823} 4824 4825static int 4826parse_address (char **str, int i) 4827{ 4828 return parse_address_main (str, i, 0, 0) == PARSE_OPERAND_SUCCESS 4829 ? SUCCESS : FAIL; 4830} 4831 4832static parse_operand_result 4833parse_address_group_reloc (char **str, int i, group_reloc_type type) 4834{ 4835 return parse_address_main (str, i, 1, type); 4836} 4837 4838/* Parse an operand for a MOVW or MOVT instruction. */ 4839static int 4840parse_half (char **str) 4841{ 4842 char * p; 4843 4844 p = *str; 4845 skip_past_char (&p, '#'); 4846 if (strncasecmp (p, ":lower16:", 9) == 0) 4847 inst.reloc.type = BFD_RELOC_ARM_MOVW; 4848 else if (strncasecmp (p, ":upper16:", 9) == 0) 4849 inst.reloc.type = BFD_RELOC_ARM_MOVT; 4850 4851 if (inst.reloc.type != BFD_RELOC_UNUSED) 4852 { 4853 p += 9; 4854 skip_whitespace(p); 4855 } 4856 4857 if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX)) 4858 return FAIL; 4859 4860 if (inst.reloc.type == BFD_RELOC_UNUSED) 4861 { 4862 if (inst.reloc.exp.X_op != O_constant) 4863 { 4864 inst.error = _("constant expression expected"); 4865 return FAIL; 4866 } 4867 if (inst.reloc.exp.X_add_number < 0 4868 || inst.reloc.exp.X_add_number > 0xffff) 4869 { 4870 inst.error = _("immediate value out of range"); 4871 return FAIL; 4872 } 4873 } 4874 *str = p; 4875 return SUCCESS; 4876} 4877 4878/* Miscellaneous. */ 4879 4880/* Parse a PSR flag operand. The value returned is FAIL on syntax error, 4881 or a bitmask suitable to be or-ed into the ARM msr instruction. */ 4882static int 4883parse_psr (char **str) 4884{ 4885 char *p; 4886 unsigned long psr_field; 4887 const struct asm_psr *psr; 4888 char *start; 4889 4890 /* CPSR's and SPSR's can now be lowercase. This is just a convenience 4891 feature for ease of use and backwards compatibility. */ 4892 p = *str; 4893 if (strncasecmp (p, "SPSR", 4) == 0) 4894 psr_field = SPSR_BIT; 4895 else if (strncasecmp (p, "CPSR", 4) == 0) 4896 psr_field = 0; 4897 else 4898 { 4899 start = p; 4900 do 4901 p++; 4902 while (ISALNUM (*p) || *p == '_'); 4903 4904 psr = hash_find_n (arm_v7m_psr_hsh, start, p - start); 4905 if (!psr) 4906 return FAIL; 4907 4908 *str = p; 4909 return psr->field; 4910 } 4911 4912 p += 4; 4913 if (*p == '_') 4914 { 4915 /* A suffix follows. */ 4916 p++; 4917 start = p; 4918 4919 do 4920 p++; 4921 while (ISALNUM (*p) || *p == '_'); 4922 4923 psr = hash_find_n (arm_psr_hsh, start, p - start); 4924 if (!psr) 4925 goto error; 4926 4927 psr_field |= psr->field; 4928 } 4929 else 4930 { 4931 if (ISALNUM (*p)) 4932 goto error; /* Garbage after "[CS]PSR". */ 4933 4934 psr_field |= (PSR_c | PSR_f); 4935 } 4936 *str = p; 4937 return psr_field; 4938 4939 error: 4940 inst.error = _("flag for {c}psr instruction expected"); 4941 return FAIL; 4942} 4943 4944/* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a 4945 value suitable for splatting into the AIF field of the instruction. */ 4946 4947static int 4948parse_cps_flags (char **str) 4949{ 4950 int val = 0; 4951 int saw_a_flag = 0; 4952 char *s = *str; 4953 4954 for (;;) 4955 switch (*s++) 4956 { 4957 case '\0': case ',': 4958 goto done; 4959 4960 case 'a': case 'A': saw_a_flag = 1; val |= 0x4; break; 4961 case 'i': case 'I': saw_a_flag = 1; val |= 0x2; break; 4962 case 'f': case 'F': saw_a_flag = 1; val |= 0x1; break; 4963 4964 default: 4965 inst.error = _("unrecognized CPS flag"); 4966 return FAIL; 4967 } 4968 4969 done: 4970 if (saw_a_flag == 0) 4971 { 4972 inst.error = _("missing CPS flags"); 4973 return FAIL; 4974 } 4975 4976 *str = s - 1; 4977 return val; 4978} 4979 4980/* Parse an endian specifier ("BE" or "LE", case insensitive); 4981 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */ 4982 4983static int 4984parse_endian_specifier (char **str) 4985{ 4986 int little_endian; 4987 char *s = *str; 4988 4989 if (strncasecmp (s, "BE", 2)) 4990 little_endian = 0; 4991 else if (strncasecmp (s, "LE", 2)) 4992 little_endian = 1; 4993 else 4994 { 4995 inst.error = _("valid endian specifiers are be or le"); 4996 return FAIL; 4997 } 4998 4999 if (ISALNUM (s[2]) || s[2] == '_') 5000 { 5001 inst.error = _("valid endian specifiers are be or le"); 5002 return FAIL; 5003 } 5004 5005 *str = s + 2; 5006 return little_endian; 5007} 5008 5009/* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a 5010 value suitable for poking into the rotate field of an sxt or sxta 5011 instruction, or FAIL on error. */ 5012 5013static int 5014parse_ror (char **str) 5015{ 5016 int rot; 5017 char *s = *str; 5018 5019 if (strncasecmp (s, "ROR", 3) == 0) 5020 s += 3; 5021 else 5022 { 5023 inst.error = _("missing rotation field after comma"); 5024 return FAIL; 5025 } 5026 5027 if (parse_immediate (&s, &rot, 0, 24, FALSE) == FAIL) 5028 return FAIL; 5029 5030 switch (rot) 5031 { 5032 case 0: *str = s; return 0x0; 5033 case 8: *str = s; return 0x1; 5034 case 16: *str = s; return 0x2; 5035 case 24: *str = s; return 0x3; 5036 5037 default: 5038 inst.error = _("rotation can only be 0, 8, 16, or 24"); 5039 return FAIL; 5040 } 5041} 5042 5043/* Parse a conditional code (from conds[] below). The value returned is in the 5044 range 0 .. 14, or FAIL. */ 5045static int 5046parse_cond (char **str) 5047{ 5048 char *p, *q; 5049 const struct asm_cond *c; 5050 5051 p = q = *str; 5052 while (ISALPHA (*q)) 5053 q++; 5054 5055 c = hash_find_n (arm_cond_hsh, p, q - p); 5056 if (!c) 5057 { 5058 inst.error = _("condition required"); 5059 return FAIL; 5060 } 5061 5062 *str = q; 5063 return c->value; 5064} 5065 5066/* Parse an option for a barrier instruction. Returns the encoding for the 5067 option, or FAIL. */ 5068static int 5069parse_barrier (char **str) 5070{ 5071 char *p, *q; 5072 const struct asm_barrier_opt *o; 5073 5074 p = q = *str; 5075 while (ISALPHA (*q)) 5076 q++; 5077 5078 o = hash_find_n (arm_barrier_opt_hsh, p, q - p); 5079 if (!o) 5080 return FAIL; 5081 5082 *str = q; 5083 return o->value; 5084} 5085 5086/* Parse the operands of a table branch instruction. Similar to a memory 5087 operand. */ 5088static int 5089parse_tb (char **str) 5090{ 5091 char * p = *str; 5092 int reg; 5093 5094 if (skip_past_char (&p, '[') == FAIL) 5095 { 5096 inst.error = _("'[' expected"); 5097 return FAIL; 5098 } 5099 5100 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL) 5101 { 5102 inst.error = _(reg_expected_msgs[REG_TYPE_RN]); 5103 return FAIL; 5104 } 5105 inst.operands[0].reg = reg; 5106 5107 if (skip_past_comma (&p) == FAIL) 5108 { 5109 inst.error = _("',' expected"); 5110 return FAIL; 5111 } 5112 5113 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL) 5114 { 5115 inst.error = _(reg_expected_msgs[REG_TYPE_RN]); 5116 return FAIL; 5117 } 5118 inst.operands[0].imm = reg; 5119 5120 if (skip_past_comma (&p) == SUCCESS) 5121 { 5122 if (parse_shift (&p, 0, SHIFT_LSL_IMMEDIATE) == FAIL) 5123 return FAIL; 5124 if (inst.reloc.exp.X_add_number != 1) 5125 { 5126 inst.error = _("invalid shift"); 5127 return FAIL; 5128 } 5129 inst.operands[0].shifted = 1; 5130 } 5131 5132 if (skip_past_char (&p, ']') == FAIL) 5133 { 5134 inst.error = _("']' expected"); 5135 return FAIL; 5136 } 5137 *str = p; 5138 return SUCCESS; 5139} 5140 5141/* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more 5142 information on the types the operands can take and how they are encoded. 5143 Up to four operands may be read; this function handles setting the 5144 ".present" field for each read operand itself. 5145 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS, 5146 else returns FAIL. */ 5147 5148static int 5149parse_neon_mov (char **str, int *which_operand) 5150{ 5151 int i = *which_operand, val; 5152 enum arm_reg_type rtype; 5153 char *ptr = *str; 5154 struct neon_type_el optype; 5155 5156 if ((val = parse_scalar (&ptr, 8, &optype)) != FAIL) 5157 { 5158 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */ 5159 inst.operands[i].reg = val; 5160 inst.operands[i].isscalar = 1; 5161 inst.operands[i].vectype = optype; 5162 inst.operands[i++].present = 1; 5163 5164 if (skip_past_comma (&ptr) == FAIL) 5165 goto wanted_comma; 5166 5167 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL) 5168 goto wanted_arm; 5169 5170 inst.operands[i].reg = val; 5171 inst.operands[i].isreg = 1; 5172 inst.operands[i].present = 1; 5173 } 5174 else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_NSDQ, &rtype, &optype)) 5175 != FAIL) 5176 { 5177 /* Cases 0, 1, 2, 3, 5 (D only). */ 5178 if (skip_past_comma (&ptr) == FAIL) 5179 goto wanted_comma; 5180 5181 inst.operands[i].reg = val; 5182 inst.operands[i].isreg = 1; 5183 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); 5184 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); 5185 inst.operands[i].isvec = 1; 5186 inst.operands[i].vectype = optype; 5187 inst.operands[i++].present = 1; 5188 5189 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL) 5190 { 5191 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>. 5192 Case 13: VMOV <Sd>, <Rm> */ 5193 inst.operands[i].reg = val; 5194 inst.operands[i].isreg = 1; 5195 inst.operands[i].present = 1; 5196 5197 if (rtype == REG_TYPE_NQ) 5198 { 5199 first_error (_("can't use Neon quad register here")); 5200 return FAIL; 5201 } 5202 else if (rtype != REG_TYPE_VFS) 5203 { 5204 i++; 5205 if (skip_past_comma (&ptr) == FAIL) 5206 goto wanted_comma; 5207 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL) 5208 goto wanted_arm; 5209 inst.operands[i].reg = val; 5210 inst.operands[i].isreg = 1; 5211 inst.operands[i].present = 1; 5212 } 5213 } 5214 else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_NSDQ, &rtype, 5215 &optype)) != FAIL) 5216 { 5217 /* Case 0: VMOV<c><q> <Qd>, <Qm> 5218 Case 1: VMOV<c><q> <Dd>, <Dm> 5219 Case 8: VMOV.F32 <Sd>, <Sm> 5220 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */ 5221 5222 inst.operands[i].reg = val; 5223 inst.operands[i].isreg = 1; 5224 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); 5225 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); 5226 inst.operands[i].isvec = 1; 5227 inst.operands[i].vectype = optype; 5228 inst.operands[i].present = 1; 5229 5230 if (skip_past_comma (&ptr) == SUCCESS) 5231 { 5232 /* Case 15. */ 5233 i++; 5234 5235 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL) 5236 goto wanted_arm; 5237 5238 inst.operands[i].reg = val; 5239 inst.operands[i].isreg = 1; 5240 inst.operands[i++].present = 1; 5241 5242 if (skip_past_comma (&ptr) == FAIL) 5243 goto wanted_comma; 5244 5245 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL) 5246 goto wanted_arm; 5247 5248 inst.operands[i].reg = val; 5249 inst.operands[i].isreg = 1; 5250 inst.operands[i].present = 1; 5251 } 5252 } 5253 else if (parse_qfloat_immediate (&ptr, &inst.operands[i].imm) == SUCCESS) 5254 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm> 5255 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm> 5256 Case 10: VMOV.F32 <Sd>, #<imm> 5257 Case 11: VMOV.F64 <Dd>, #<imm> */ 5258 inst.operands[i].immisfloat = 1; 5259 else if (parse_big_immediate (&ptr, i) == SUCCESS) 5260 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm> 5261 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */ 5262 ; 5263 else 5264 { 5265 first_error (_("expected <Rm> or <Dm> or <Qm> operand")); 5266 return FAIL; 5267 } 5268 } 5269 else if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL) 5270 { 5271 /* Cases 6, 7. */ 5272 inst.operands[i].reg = val; 5273 inst.operands[i].isreg = 1; 5274 inst.operands[i++].present = 1; 5275 5276 if (skip_past_comma (&ptr) == FAIL) 5277 goto wanted_comma; 5278 5279 if ((val = parse_scalar (&ptr, 8, &optype)) != FAIL) 5280 { 5281 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */ 5282 inst.operands[i].reg = val; 5283 inst.operands[i].isscalar = 1; 5284 inst.operands[i].present = 1; 5285 inst.operands[i].vectype = optype; 5286 } 5287 else if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL) 5288 { 5289 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */ 5290 inst.operands[i].reg = val; 5291 inst.operands[i].isreg = 1; 5292 inst.operands[i++].present = 1; 5293 5294 if (skip_past_comma (&ptr) == FAIL) 5295 goto wanted_comma; 5296 5297 if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFSD, &rtype, &optype)) 5298 == FAIL) 5299 { 5300 first_error (_(reg_expected_msgs[REG_TYPE_VFSD])); 5301 return FAIL; 5302 } 5303 5304 inst.operands[i].reg = val; 5305 inst.operands[i].isreg = 1; 5306 inst.operands[i].isvec = 1; 5307 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); 5308 inst.operands[i].vectype = optype; 5309 inst.operands[i].present = 1; 5310 5311 if (rtype == REG_TYPE_VFS) 5312 { 5313 /* Case 14. */ 5314 i++; 5315 if (skip_past_comma (&ptr) == FAIL) 5316 goto wanted_comma; 5317 if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFS, NULL, 5318 &optype)) == FAIL) 5319 { 5320 first_error (_(reg_expected_msgs[REG_TYPE_VFS])); 5321 return FAIL; 5322 } 5323 inst.operands[i].reg = val; 5324 inst.operands[i].isreg = 1; 5325 inst.operands[i].isvec = 1; 5326 inst.operands[i].issingle = 1; 5327 inst.operands[i].vectype = optype; 5328 inst.operands[i].present = 1; 5329 } 5330 } 5331 else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFS, NULL, &optype)) 5332 != FAIL) 5333 { 5334 /* Case 13. */ 5335 inst.operands[i].reg = val; 5336 inst.operands[i].isreg = 1; 5337 inst.operands[i].isvec = 1; 5338 inst.operands[i].issingle = 1; 5339 inst.operands[i].vectype = optype; 5340 inst.operands[i].present = 1; 5341 } 5342 } 5343 else 5344 { 5345 first_error (_("parse error")); 5346 return FAIL; 5347 } 5348 5349 /* Successfully parsed the operands. Update args. */ 5350 *which_operand = i; 5351 *str = ptr; 5352 return SUCCESS; 5353 5354 wanted_comma: 5355 first_error (_("expected comma")); 5356 return FAIL; 5357 5358 wanted_arm: 5359 first_error (_(reg_expected_msgs[REG_TYPE_RN])); 5360 return FAIL; 5361} 5362 5363/* Matcher codes for parse_operands. */ 5364enum operand_parse_code 5365{ 5366 OP_stop, /* end of line */ 5367 5368 OP_RR, /* ARM register */ 5369 OP_RRnpc, /* ARM register, not r15 */ 5370 OP_RRnpcb, /* ARM register, not r15, in square brackets */ 5371 OP_RRw, /* ARM register, not r15, optional trailing ! */ 5372 OP_RCP, /* Coprocessor number */ 5373 OP_RCN, /* Coprocessor register */ 5374 OP_RF, /* FPA register */ 5375 OP_RVS, /* VFP single precision register */ 5376 OP_RVD, /* VFP double precision register (0..15) */ 5377 OP_RND, /* Neon double precision register (0..31) */ 5378 OP_RNQ, /* Neon quad precision register */ 5379 OP_RVSD, /* VFP single or double precision register */ 5380 OP_RNDQ, /* Neon double or quad precision register */ 5381 OP_RNSDQ, /* Neon single, double or quad precision register */ 5382 OP_RNSC, /* Neon scalar D[X] */ 5383 OP_RVC, /* VFP control register */ 5384 OP_RMF, /* Maverick F register */ 5385 OP_RMD, /* Maverick D register */ 5386 OP_RMFX, /* Maverick FX register */ 5387 OP_RMDX, /* Maverick DX register */ 5388 OP_RMAX, /* Maverick AX register */ 5389 OP_RMDS, /* Maverick DSPSC register */ 5390 OP_RIWR, /* iWMMXt wR register */ 5391 OP_RIWC, /* iWMMXt wC register */ 5392 OP_RIWG, /* iWMMXt wCG register */ 5393 OP_RXA, /* XScale accumulator register */ 5394 5395 OP_REGLST, /* ARM register list */ 5396 OP_VRSLST, /* VFP single-precision register list */ 5397 OP_VRDLST, /* VFP double-precision register list */ 5398 OP_VRSDLST, /* VFP single or double-precision register list (& quad) */ 5399 OP_NRDLST, /* Neon double-precision register list (d0-d31, qN aliases) */ 5400 OP_NSTRLST, /* Neon element/structure list */ 5401 5402 OP_NILO, /* Neon immediate/logic operands 2 or 2+3. (VBIC, VORR...) */ 5403 OP_RNDQ_I0, /* Neon D or Q reg, or immediate zero. */ 5404 OP_RVSD_I0, /* VFP S or D reg, or immediate zero. */ 5405 OP_RR_RNSC, /* ARM reg or Neon scalar. */ 5406 OP_RNSDQ_RNSC, /* Vector S, D or Q reg, or Neon scalar. */ 5407 OP_RNDQ_RNSC, /* Neon D or Q reg, or Neon scalar. */ 5408 OP_RND_RNSC, /* Neon D reg, or Neon scalar. */ 5409 OP_VMOV, /* Neon VMOV operands. */ 5410 OP_RNDQ_IMVNb,/* Neon D or Q reg, or immediate good for VMVN. */ 5411 OP_RNDQ_I63b, /* Neon D or Q reg, or immediate for shift. */ 5412 OP_RIWR_I32z, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */ 5413 5414 OP_I0, /* immediate zero */ 5415 OP_I7, /* immediate value 0 .. 7 */ 5416 OP_I15, /* 0 .. 15 */ 5417 OP_I16, /* 1 .. 16 */ 5418 OP_I16z, /* 0 .. 16 */ 5419 OP_I31, /* 0 .. 31 */ 5420 OP_I31w, /* 0 .. 31, optional trailing ! */ 5421 OP_I32, /* 1 .. 32 */ 5422 OP_I32z, /* 0 .. 32 */ 5423 OP_I63, /* 0 .. 63 */ 5424 OP_I63s, /* -64 .. 63 */ 5425 OP_I64, /* 1 .. 64 */ 5426 OP_I64z, /* 0 .. 64 */ 5427 OP_I255, /* 0 .. 255 */ 5428 5429 OP_I4b, /* immediate, prefix optional, 1 .. 4 */ 5430 OP_I7b, /* 0 .. 7 */ 5431 OP_I15b, /* 0 .. 15 */ 5432 OP_I31b, /* 0 .. 31 */ 5433 5434 OP_SH, /* shifter operand */ 5435 OP_SHG, /* shifter operand with possible group relocation */ 5436 OP_ADDR, /* Memory address expression (any mode) */ 5437 OP_ADDRGLDR, /* Mem addr expr (any mode) with possible LDR group reloc */ 5438 OP_ADDRGLDRS, /* Mem addr expr (any mode) with possible LDRS group reloc */ 5439 OP_ADDRGLDC, /* Mem addr expr (any mode) with possible LDC group reloc */ 5440 OP_EXP, /* arbitrary expression */ 5441 OP_EXPi, /* same, with optional immediate prefix */ 5442 OP_EXPr, /* same, with optional relocation suffix */ 5443 OP_HALF, /* 0 .. 65535 or low/high reloc. */ 5444 5445 OP_CPSF, /* CPS flags */ 5446 OP_ENDI, /* Endianness specifier */ 5447 OP_PSR, /* CPSR/SPSR mask for msr */ 5448 OP_COND, /* conditional code */ 5449 OP_TB, /* Table branch. */ 5450 5451 OP_RVC_PSR, /* CPSR/SPSR mask for msr, or VFP control register. */ 5452 OP_APSR_RR, /* ARM register or "APSR_nzcv". */ 5453 5454 OP_RRnpc_I0, /* ARM register or literal 0 */ 5455 OP_RR_EXr, /* ARM register or expression with opt. reloc suff. */ 5456 OP_RR_EXi, /* ARM register or expression with imm prefix */ 5457 OP_RF_IF, /* FPA register or immediate */ 5458 OP_RIWR_RIWC, /* iWMMXt R or C reg */ 5459 OP_RIWC_RIWG, /* iWMMXt wC or wCG reg */ 5460 5461 /* Optional operands. */ 5462 OP_oI7b, /* immediate, prefix optional, 0 .. 7 */ 5463 OP_oI31b, /* 0 .. 31 */ 5464 OP_oI32b, /* 1 .. 32 */ 5465 OP_oIffffb, /* 0 .. 65535 */ 5466 OP_oI255c, /* curly-brace enclosed, 0 .. 255 */ 5467 5468 OP_oRR, /* ARM register */ 5469 OP_oRRnpc, /* ARM register, not the PC */ 5470 OP_oRRw, /* ARM register, not r15, optional trailing ! */ 5471 OP_oRND, /* Optional Neon double precision register */ 5472 OP_oRNQ, /* Optional Neon quad precision register */ 5473 OP_oRNDQ, /* Optional Neon double or quad precision register */ 5474 OP_oRNSDQ, /* Optional single, double or quad precision vector register */ 5475 OP_oSHll, /* LSL immediate */ 5476 OP_oSHar, /* ASR immediate */ 5477 OP_oSHllar, /* LSL or ASR immediate */ 5478 OP_oROR, /* ROR 0/8/16/24 */ 5479 OP_oBARRIER, /* Option argument for a barrier instruction. */ 5480 5481 OP_FIRST_OPTIONAL = OP_oI7b 5482}; 5483 5484/* Generic instruction operand parser. This does no encoding and no 5485 semantic validation; it merely squirrels values away in the inst 5486 structure. Returns SUCCESS or FAIL depending on whether the 5487 specified grammar matched. */ 5488static int 5489parse_operands (char *str, const unsigned char *pattern) 5490{ 5491 unsigned const char *upat = pattern; 5492 char *backtrack_pos = 0; 5493 const char *backtrack_error = 0; 5494 int i, val, backtrack_index = 0; 5495 enum arm_reg_type rtype; 5496 parse_operand_result result; 5497 5498#define po_char_or_fail(chr) do { \ 5499 if (skip_past_char (&str, chr) == FAIL) \ 5500 goto bad_args; \ 5501} while (0) 5502 5503#define po_reg_or_fail(regtype) do { \ 5504 val = arm_typed_reg_parse (&str, regtype, &rtype, \ 5505 &inst.operands[i].vectype); \ 5506 if (val == FAIL) \ 5507 { \ 5508 first_error (_(reg_expected_msgs[regtype])); \ 5509 goto failure; \ 5510 } \ 5511 inst.operands[i].reg = val; \ 5512 inst.operands[i].isreg = 1; \ 5513 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \ 5514 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \ 5515 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \ 5516 || rtype == REG_TYPE_VFD \ 5517 || rtype == REG_TYPE_NQ); \ 5518} while (0) 5519 5520#define po_reg_or_goto(regtype, label) do { \ 5521 val = arm_typed_reg_parse (&str, regtype, &rtype, \ 5522 &inst.operands[i].vectype); \ 5523 if (val == FAIL) \ 5524 goto label; \ 5525 \ 5526 inst.operands[i].reg = val; \ 5527 inst.operands[i].isreg = 1; \ 5528 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \ 5529 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \ 5530 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \ 5531 || rtype == REG_TYPE_VFD \ 5532 || rtype == REG_TYPE_NQ); \ 5533} while (0) 5534 5535#define po_imm_or_fail(min, max, popt) do { \ 5536 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \ 5537 goto failure; \ 5538 inst.operands[i].imm = val; \ 5539} while (0) 5540 5541#define po_scalar_or_goto(elsz, label) do { \ 5542 val = parse_scalar (&str, elsz, &inst.operands[i].vectype); \ 5543 if (val == FAIL) \ 5544 goto label; \ 5545 inst.operands[i].reg = val; \ 5546 inst.operands[i].isscalar = 1; \ 5547} while (0) 5548 5549#define po_misc_or_fail(expr) do { \ 5550 if (expr) \ 5551 goto failure; \ 5552} while (0) 5553 5554#define po_misc_or_fail_no_backtrack(expr) do { \ 5555 result = expr; \ 5556 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK)\ 5557 backtrack_pos = 0; \ 5558 if (result != PARSE_OPERAND_SUCCESS) \ 5559 goto failure; \ 5560} while (0) 5561 5562 skip_whitespace (str); 5563 5564 for (i = 0; upat[i] != OP_stop; i++) 5565 { 5566 if (upat[i] >= OP_FIRST_OPTIONAL) 5567 { 5568 /* Remember where we are in case we need to backtrack. */ 5569 assert (!backtrack_pos); 5570 backtrack_pos = str; 5571 backtrack_error = inst.error; 5572 backtrack_index = i; 5573 } 5574 5575 if (i > 0 && (i > 1 || inst.operands[0].present)) 5576 po_char_or_fail (','); 5577 5578 switch (upat[i]) 5579 { 5580 /* Registers */ 5581 case OP_oRRnpc: 5582 case OP_RRnpc: 5583 case OP_oRR: 5584 case OP_RR: po_reg_or_fail (REG_TYPE_RN); break; 5585 case OP_RCP: po_reg_or_fail (REG_TYPE_CP); break; 5586 case OP_RCN: po_reg_or_fail (REG_TYPE_CN); break; 5587 case OP_RF: po_reg_or_fail (REG_TYPE_FN); break; 5588 case OP_RVS: po_reg_or_fail (REG_TYPE_VFS); break; 5589 case OP_RVD: po_reg_or_fail (REG_TYPE_VFD); break; 5590 case OP_oRND: 5591 case OP_RND: po_reg_or_fail (REG_TYPE_VFD); break; 5592 case OP_RVC: 5593 po_reg_or_goto (REG_TYPE_VFC, coproc_reg); 5594 break; 5595 /* Also accept generic coprocessor regs for unknown registers. */ 5596 coproc_reg: 5597 po_reg_or_fail (REG_TYPE_CN); 5598 break; 5599 case OP_RMF: po_reg_or_fail (REG_TYPE_MVF); break; 5600 case OP_RMD: po_reg_or_fail (REG_TYPE_MVD); break; 5601 case OP_RMFX: po_reg_or_fail (REG_TYPE_MVFX); break; 5602 case OP_RMDX: po_reg_or_fail (REG_TYPE_MVDX); break; 5603 case OP_RMAX: po_reg_or_fail (REG_TYPE_MVAX); break; 5604 case OP_RMDS: po_reg_or_fail (REG_TYPE_DSPSC); break; 5605 case OP_RIWR: po_reg_or_fail (REG_TYPE_MMXWR); break; 5606 case OP_RIWC: po_reg_or_fail (REG_TYPE_MMXWC); break; 5607 case OP_RIWG: po_reg_or_fail (REG_TYPE_MMXWCG); break; 5608 case OP_RXA: po_reg_or_fail (REG_TYPE_XSCALE); break; 5609 case OP_oRNQ: 5610 case OP_RNQ: po_reg_or_fail (REG_TYPE_NQ); break; 5611 case OP_oRNDQ: 5612 case OP_RNDQ: po_reg_or_fail (REG_TYPE_NDQ); break; 5613 case OP_RVSD: po_reg_or_fail (REG_TYPE_VFSD); break; 5614 case OP_oRNSDQ: 5615 case OP_RNSDQ: po_reg_or_fail (REG_TYPE_NSDQ); break; 5616 5617 /* Neon scalar. Using an element size of 8 means that some invalid 5618 scalars are accepted here, so deal with those in later code. */ 5619 case OP_RNSC: po_scalar_or_goto (8, failure); break; 5620 5621 /* WARNING: We can expand to two operands here. This has the potential 5622 to totally confuse the backtracking mechanism! It will be OK at 5623 least as long as we don't try to use optional args as well, 5624 though. */ 5625 case OP_NILO: 5626 { 5627 po_reg_or_goto (REG_TYPE_NDQ, try_imm); 5628 inst.operands[i].present = 1; 5629 i++; 5630 skip_past_comma (&str); 5631 po_reg_or_goto (REG_TYPE_NDQ, one_reg_only); 5632 break; 5633 one_reg_only: 5634 /* Optional register operand was omitted. Unfortunately, it's in 5635 operands[i-1] and we need it to be in inst.operands[i]. Fix that 5636 here (this is a bit grotty). */ 5637 inst.operands[i] = inst.operands[i-1]; 5638 inst.operands[i-1].present = 0; 5639 break; 5640 try_imm: 5641 /* There's a possibility of getting a 64-bit immediate here, so 5642 we need special handling. */ 5643 if (parse_big_immediate (&str, i) == FAIL) 5644 { 5645 inst.error = _("immediate value is out of range"); 5646 goto failure; 5647 } 5648 } 5649 break; 5650 5651 case OP_RNDQ_I0: 5652 { 5653 po_reg_or_goto (REG_TYPE_NDQ, try_imm0); 5654 break; 5655 try_imm0: 5656 po_imm_or_fail (0, 0, TRUE); 5657 } 5658 break; 5659 5660 case OP_RVSD_I0: 5661 po_reg_or_goto (REG_TYPE_VFSD, try_imm0); 5662 break; 5663 5664 case OP_RR_RNSC: 5665 { 5666 po_scalar_or_goto (8, try_rr); 5667 break; 5668 try_rr: 5669 po_reg_or_fail (REG_TYPE_RN); 5670 } 5671 break; 5672 5673 case OP_RNSDQ_RNSC: 5674 { 5675 po_scalar_or_goto (8, try_nsdq); 5676 break; 5677 try_nsdq: 5678 po_reg_or_fail (REG_TYPE_NSDQ); 5679 } 5680 break; 5681 5682 case OP_RNDQ_RNSC: 5683 { 5684 po_scalar_or_goto (8, try_ndq); 5685 break; 5686 try_ndq: 5687 po_reg_or_fail (REG_TYPE_NDQ); 5688 } 5689 break; 5690 5691 case OP_RND_RNSC: 5692 { 5693 po_scalar_or_goto (8, try_vfd); 5694 break; 5695 try_vfd: 5696 po_reg_or_fail (REG_TYPE_VFD); 5697 } 5698 break; 5699 5700 case OP_VMOV: 5701 /* WARNING: parse_neon_mov can move the operand counter, i. If we're 5702 not careful then bad things might happen. */ 5703 po_misc_or_fail (parse_neon_mov (&str, &i) == FAIL); 5704 break; 5705 5706 case OP_RNDQ_IMVNb: 5707 { 5708 po_reg_or_goto (REG_TYPE_NDQ, try_mvnimm); 5709 break; 5710 try_mvnimm: 5711 /* There's a possibility of getting a 64-bit immediate here, so 5712 we need special handling. */ 5713 if (parse_big_immediate (&str, i) == FAIL) 5714 { 5715 inst.error = _("immediate value is out of range"); 5716 goto failure; 5717 } 5718 } 5719 break; 5720 5721 case OP_RNDQ_I63b: 5722 { 5723 po_reg_or_goto (REG_TYPE_NDQ, try_shimm); 5724 break; 5725 try_shimm: 5726 po_imm_or_fail (0, 63, TRUE); 5727 } 5728 break; 5729 5730 case OP_RRnpcb: 5731 po_char_or_fail ('['); 5732 po_reg_or_fail (REG_TYPE_RN); 5733 po_char_or_fail (']'); 5734 break; 5735 5736 case OP_RRw: 5737 case OP_oRRw: 5738 po_reg_or_fail (REG_TYPE_RN); 5739 if (skip_past_char (&str, '!') == SUCCESS) 5740 inst.operands[i].writeback = 1; 5741 break; 5742 5743 /* Immediates */ 5744 case OP_I7: po_imm_or_fail ( 0, 7, FALSE); break; 5745 case OP_I15: po_imm_or_fail ( 0, 15, FALSE); break; 5746 case OP_I16: po_imm_or_fail ( 1, 16, FALSE); break; 5747 case OP_I16z: po_imm_or_fail ( 0, 16, FALSE); break; 5748 case OP_I31: po_imm_or_fail ( 0, 31, FALSE); break; 5749 case OP_I32: po_imm_or_fail ( 1, 32, FALSE); break; 5750 case OP_I32z: po_imm_or_fail ( 0, 32, FALSE); break; 5751 case OP_I63s: po_imm_or_fail (-64, 63, FALSE); break; 5752 case OP_I63: po_imm_or_fail ( 0, 63, FALSE); break; 5753 case OP_I64: po_imm_or_fail ( 1, 64, FALSE); break; 5754 case OP_I64z: po_imm_or_fail ( 0, 64, FALSE); break; 5755 case OP_I255: po_imm_or_fail ( 0, 255, FALSE); break; 5756 5757 case OP_I4b: po_imm_or_fail ( 1, 4, TRUE); break; 5758 case OP_oI7b: 5759 case OP_I7b: po_imm_or_fail ( 0, 7, TRUE); break; 5760 case OP_I15b: po_imm_or_fail ( 0, 15, TRUE); break; 5761 case OP_oI31b: 5762 case OP_I31b: po_imm_or_fail ( 0, 31, TRUE); break; 5763 case OP_oI32b: po_imm_or_fail ( 1, 32, TRUE); break; 5764 case OP_oIffffb: po_imm_or_fail ( 0, 0xffff, TRUE); break; 5765 5766 /* Immediate variants */ 5767 case OP_oI255c: 5768 po_char_or_fail ('{'); 5769 po_imm_or_fail (0, 255, TRUE); 5770 po_char_or_fail ('}'); 5771 break; 5772 5773 case OP_I31w: 5774 /* The expression parser chokes on a trailing !, so we have 5775 to find it first and zap it. */ 5776 { 5777 char *s = str; 5778 while (*s && *s != ',') 5779 s++; 5780 if (s[-1] == '!') 5781 { 5782 s[-1] = '\0'; 5783 inst.operands[i].writeback = 1; 5784 } 5785 po_imm_or_fail (0, 31, TRUE); 5786 if (str == s - 1) 5787 str = s; 5788 } 5789 break; 5790 5791 /* Expressions */ 5792 case OP_EXPi: EXPi: 5793 po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str, 5794 GE_OPT_PREFIX)); 5795 break; 5796 5797 case OP_EXP: 5798 po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str, 5799 GE_NO_PREFIX)); 5800 break; 5801 5802 case OP_EXPr: EXPr: 5803 po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str, 5804 GE_NO_PREFIX)); 5805 if (inst.reloc.exp.X_op == O_symbol) 5806 { 5807 val = parse_reloc (&str); 5808 if (val == -1) 5809 { 5810 inst.error = _("unrecognized relocation suffix"); 5811 goto failure; 5812 } 5813 else if (val != BFD_RELOC_UNUSED) 5814 { 5815 inst.operands[i].imm = val; 5816 inst.operands[i].hasreloc = 1; 5817 } 5818 } 5819 break; 5820 5821 /* Operand for MOVW or MOVT. */ 5822 case OP_HALF: 5823 po_misc_or_fail (parse_half (&str)); 5824 break; 5825 5826 /* Register or expression */ 5827 case OP_RR_EXr: po_reg_or_goto (REG_TYPE_RN, EXPr); break; 5828 case OP_RR_EXi: po_reg_or_goto (REG_TYPE_RN, EXPi); break; 5829 5830 /* Register or immediate */ 5831 case OP_RRnpc_I0: po_reg_or_goto (REG_TYPE_RN, I0); break; 5832 I0: po_imm_or_fail (0, 0, FALSE); break; 5833 5834 case OP_RF_IF: po_reg_or_goto (REG_TYPE_FN, IF); break; 5835 IF: 5836 if (!is_immediate_prefix (*str)) 5837 goto bad_args; 5838 str++; 5839 val = parse_fpa_immediate (&str); 5840 if (val == FAIL) 5841 goto failure; 5842 /* FPA immediates are encoded as registers 8-15. 5843 parse_fpa_immediate has already applied the offset. */ 5844 inst.operands[i].reg = val; 5845 inst.operands[i].isreg = 1; 5846 break; 5847 5848 case OP_RIWR_I32z: po_reg_or_goto (REG_TYPE_MMXWR, I32z); break; 5849 I32z: po_imm_or_fail (0, 32, FALSE); break; 5850 5851 /* Two kinds of register */ 5852 case OP_RIWR_RIWC: 5853 { 5854 struct reg_entry *rege = arm_reg_parse_multi (&str); 5855 if (!rege 5856 || (rege->type != REG_TYPE_MMXWR 5857 && rege->type != REG_TYPE_MMXWC 5858 && rege->type != REG_TYPE_MMXWCG)) 5859 { 5860 inst.error = _("iWMMXt data or control register expected"); 5861 goto failure; 5862 } 5863 inst.operands[i].reg = rege->number; 5864 inst.operands[i].isreg = (rege->type == REG_TYPE_MMXWR); 5865 } 5866 break; 5867 5868 case OP_RIWC_RIWG: 5869 { 5870 struct reg_entry *rege = arm_reg_parse_multi (&str); 5871 if (!rege 5872 || (rege->type != REG_TYPE_MMXWC 5873 && rege->type != REG_TYPE_MMXWCG)) 5874 { 5875 inst.error = _("iWMMXt control register expected"); 5876 goto failure; 5877 } 5878 inst.operands[i].reg = rege->number; 5879 inst.operands[i].isreg = 1; 5880 } 5881 break; 5882 5883 /* Misc */ 5884 case OP_CPSF: val = parse_cps_flags (&str); break; 5885 case OP_ENDI: val = parse_endian_specifier (&str); break; 5886 case OP_oROR: val = parse_ror (&str); break; 5887 case OP_PSR: val = parse_psr (&str); break; 5888 case OP_COND: val = parse_cond (&str); break; 5889 case OP_oBARRIER:val = parse_barrier (&str); break; 5890 5891 case OP_RVC_PSR: 5892 po_reg_or_goto (REG_TYPE_VFC, try_psr); 5893 inst.operands[i].isvec = 1; /* Mark VFP control reg as vector. */ 5894 break; 5895 try_psr: 5896 val = parse_psr (&str); 5897 break; 5898 5899 case OP_APSR_RR: 5900 po_reg_or_goto (REG_TYPE_RN, try_apsr); 5901 break; 5902 try_apsr: 5903 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS 5904 instruction). */ 5905 if (strncasecmp (str, "APSR_", 5) == 0) 5906 { 5907 unsigned found = 0; 5908 str += 5; 5909 while (found < 15) 5910 switch (*str++) 5911 { 5912 case 'c': found = (found & 1) ? 16 : found | 1; break; 5913 case 'n': found = (found & 2) ? 16 : found | 2; break; 5914 case 'z': found = (found & 4) ? 16 : found | 4; break; 5915 case 'v': found = (found & 8) ? 16 : found | 8; break; 5916 default: found = 16; 5917 } 5918 if (found != 15) 5919 goto failure; 5920 inst.operands[i].isvec = 1; 5921 } 5922 else 5923 goto failure; 5924 break; 5925 5926 case OP_TB: 5927 po_misc_or_fail (parse_tb (&str)); 5928 break; 5929 5930 /* Register lists */ 5931 case OP_REGLST: 5932 val = parse_reg_list (&str); 5933 if (*str == '^') 5934 { 5935 inst.operands[1].writeback = 1; 5936 str++; 5937 } 5938 break; 5939 5940 case OP_VRSLST: 5941 val = parse_vfp_reg_list (&str, &inst.operands[i].reg, REGLIST_VFP_S); 5942 break; 5943 5944 case OP_VRDLST: 5945 val = parse_vfp_reg_list (&str, &inst.operands[i].reg, REGLIST_VFP_D); 5946 break; 5947 5948 case OP_VRSDLST: 5949 /* Allow Q registers too. */ 5950 val = parse_vfp_reg_list (&str, &inst.operands[i].reg, 5951 REGLIST_NEON_D); 5952 if (val == FAIL) 5953 { 5954 inst.error = NULL; 5955 val = parse_vfp_reg_list (&str, &inst.operands[i].reg, 5956 REGLIST_VFP_S); 5957 inst.operands[i].issingle = 1; 5958 } 5959 break; 5960 5961 case OP_NRDLST: 5962 val = parse_vfp_reg_list (&str, &inst.operands[i].reg, 5963 REGLIST_NEON_D); 5964 break; 5965 5966 case OP_NSTRLST: 5967 val = parse_neon_el_struct_list (&str, &inst.operands[i].reg, 5968 &inst.operands[i].vectype); 5969 break; 5970 5971 /* Addressing modes */ 5972 case OP_ADDR: 5973 po_misc_or_fail (parse_address (&str, i)); 5974 break; 5975 5976 case OP_ADDRGLDR: 5977 po_misc_or_fail_no_backtrack ( 5978 parse_address_group_reloc (&str, i, GROUP_LDR)); 5979 break; 5980 5981 case OP_ADDRGLDRS: 5982 po_misc_or_fail_no_backtrack ( 5983 parse_address_group_reloc (&str, i, GROUP_LDRS)); 5984 break; 5985 5986 case OP_ADDRGLDC: 5987 po_misc_or_fail_no_backtrack ( 5988 parse_address_group_reloc (&str, i, GROUP_LDC)); 5989 break; 5990 5991 case OP_SH: 5992 po_misc_or_fail (parse_shifter_operand (&str, i)); 5993 break; 5994 5995 case OP_SHG: 5996 po_misc_or_fail_no_backtrack ( 5997 parse_shifter_operand_group_reloc (&str, i)); 5998 break; 5999 6000 case OP_oSHll: 6001 po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_IMMEDIATE)); 6002 break; 6003 6004 case OP_oSHar: 6005 po_misc_or_fail (parse_shift (&str, i, SHIFT_ASR_IMMEDIATE)); 6006 break; 6007 6008 case OP_oSHllar: 6009 po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_OR_ASR_IMMEDIATE)); 6010 break; 6011 6012 default: 6013 as_fatal ("unhandled operand code %d", upat[i]); 6014 } 6015 6016 /* Various value-based sanity checks and shared operations. We 6017 do not signal immediate failures for the register constraints; 6018 this allows a syntax error to take precedence. */ 6019 switch (upat[i]) 6020 { 6021 case OP_oRRnpc: 6022 case OP_RRnpc: 6023 case OP_RRnpcb: 6024 case OP_RRw: 6025 case OP_oRRw: 6026 case OP_RRnpc_I0: 6027 if (inst.operands[i].isreg && inst.operands[i].reg == REG_PC) 6028 inst.error = BAD_PC; 6029 break; 6030 6031 case OP_CPSF: 6032 case OP_ENDI: 6033 case OP_oROR: 6034 case OP_PSR: 6035 case OP_RVC_PSR: 6036 case OP_COND: 6037 case OP_oBARRIER: 6038 case OP_REGLST: 6039 case OP_VRSLST: 6040 case OP_VRDLST: 6041 case OP_VRSDLST: 6042 case OP_NRDLST: 6043 case OP_NSTRLST: 6044 if (val == FAIL) 6045 goto failure; 6046 inst.operands[i].imm = val; 6047 break; 6048 6049 default: 6050 break; 6051 } 6052 6053 /* If we get here, this operand was successfully parsed. */ 6054 inst.operands[i].present = 1; 6055 continue; 6056 6057 bad_args: 6058 inst.error = BAD_ARGS; 6059 6060 failure: 6061 if (!backtrack_pos) 6062 { 6063 /* The parse routine should already have set inst.error, but set a 6064 defaut here just in case. */ 6065 if (!inst.error) 6066 inst.error = _("syntax error"); 6067 return FAIL; 6068 } 6069 6070 /* Do not backtrack over a trailing optional argument that 6071 absorbed some text. We will only fail again, with the 6072 'garbage following instruction' error message, which is 6073 probably less helpful than the current one. */ 6074 if (backtrack_index == i && backtrack_pos != str 6075 && upat[i+1] == OP_stop) 6076 { 6077 if (!inst.error) 6078 inst.error = _("syntax error"); 6079 return FAIL; 6080 } 6081 6082 /* Try again, skipping the optional argument at backtrack_pos. */ 6083 str = backtrack_pos; 6084 inst.error = backtrack_error; 6085 inst.operands[backtrack_index].present = 0; 6086 i = backtrack_index; 6087 backtrack_pos = 0; 6088 } 6089 6090 /* Check that we have parsed all the arguments. */ 6091 if (*str != '\0' && !inst.error) 6092 inst.error = _("garbage following instruction"); 6093 6094 return inst.error ? FAIL : SUCCESS; 6095} 6096 6097#undef po_char_or_fail 6098#undef po_reg_or_fail 6099#undef po_reg_or_goto 6100#undef po_imm_or_fail 6101#undef po_scalar_or_fail 6102 6103/* Shorthand macro for instruction encoding functions issuing errors. */ 6104#define constraint(expr, err) do { \ 6105 if (expr) \ 6106 { \ 6107 inst.error = err; \ 6108 return; \ 6109 } \ 6110} while (0) 6111 6112/* Functions for operand encoding. ARM, then Thumb. */ 6113 6114#define rotate_left(v, n) (v << (n % 32) | v >> ((32 - n) % 32)) 6115 6116/* If VAL can be encoded in the immediate field of an ARM instruction, 6117 return the encoded form. Otherwise, return FAIL. */ 6118 6119static unsigned int 6120encode_arm_immediate (unsigned int val) 6121{ 6122 unsigned int a, i; 6123 6124 for (i = 0; i < 32; i += 2) 6125 if ((a = rotate_left (val, i)) <= 0xff) 6126 return a | (i << 7); /* 12-bit pack: [shift-cnt,const]. */ 6127 6128 return FAIL; 6129} 6130 6131/* If VAL can be encoded in the immediate field of a Thumb32 instruction, 6132 return the encoded form. Otherwise, return FAIL. */ 6133static unsigned int 6134encode_thumb32_immediate (unsigned int val) 6135{ 6136 unsigned int a, i; 6137 6138 if (val <= 0xff) 6139 return val; 6140 6141 for (i = 1; i <= 24; i++) 6142 { 6143 a = val >> i; 6144 if ((val & ~(0xff << i)) == 0) 6145 return ((val >> i) & 0x7f) | ((32 - i) << 7); 6146 } 6147 6148 a = val & 0xff; 6149 if (val == ((a << 16) | a)) 6150 return 0x100 | a; 6151 if (val == ((a << 24) | (a << 16) | (a << 8) | a)) 6152 return 0x300 | a; 6153 6154 a = val & 0xff00; 6155 if (val == ((a << 16) | a)) 6156 return 0x200 | (a >> 8); 6157 6158 return FAIL; 6159} 6160/* Encode a VFP SP or DP register number into inst.instruction. */ 6161 6162static void 6163encode_arm_vfp_reg (int reg, enum vfp_reg_pos pos) 6164{ 6165 if ((pos == VFP_REG_Dd || pos == VFP_REG_Dn || pos == VFP_REG_Dm) 6166 && reg > 15) 6167 { 6168 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v3)) 6169 { 6170 if (thumb_mode) 6171 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, 6172 fpu_vfp_ext_v3); 6173 else 6174 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, 6175 fpu_vfp_ext_v3); 6176 } 6177 else 6178 { 6179 first_error (_("D register out of range for selected VFP version")); 6180 return; 6181 } 6182 } 6183 6184 switch (pos) 6185 { 6186 case VFP_REG_Sd: 6187 inst.instruction |= ((reg >> 1) << 12) | ((reg & 1) << 22); 6188 break; 6189 6190 case VFP_REG_Sn: 6191 inst.instruction |= ((reg >> 1) << 16) | ((reg & 1) << 7); 6192 break; 6193 6194 case VFP_REG_Sm: 6195 inst.instruction |= ((reg >> 1) << 0) | ((reg & 1) << 5); 6196 break; 6197 6198 case VFP_REG_Dd: 6199 inst.instruction |= ((reg & 15) << 12) | ((reg >> 4) << 22); 6200 break; 6201 6202 case VFP_REG_Dn: 6203 inst.instruction |= ((reg & 15) << 16) | ((reg >> 4) << 7); 6204 break; 6205 6206 case VFP_REG_Dm: 6207 inst.instruction |= (reg & 15) | ((reg >> 4) << 5); 6208 break; 6209 6210 default: 6211 abort (); 6212 } 6213} 6214 6215/* Encode a <shift> in an ARM-format instruction. The immediate, 6216 if any, is handled by md_apply_fix. */ 6217static void 6218encode_arm_shift (int i) 6219{ 6220 if (inst.operands[i].shift_kind == SHIFT_RRX) 6221 inst.instruction |= SHIFT_ROR << 5; 6222 else 6223 { 6224 inst.instruction |= inst.operands[i].shift_kind << 5; 6225 if (inst.operands[i].immisreg) 6226 { 6227 inst.instruction |= SHIFT_BY_REG; 6228 inst.instruction |= inst.operands[i].imm << 8; 6229 } 6230 else 6231 inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM; 6232 } 6233} 6234 6235static void 6236encode_arm_shifter_operand (int i) 6237{ 6238 if (inst.operands[i].isreg) 6239 { 6240 inst.instruction |= inst.operands[i].reg; 6241 encode_arm_shift (i); 6242 } 6243 else 6244 inst.instruction |= INST_IMMEDIATE; 6245} 6246 6247/* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */ 6248static void 6249encode_arm_addr_mode_common (int i, bfd_boolean is_t) 6250{ 6251 assert (inst.operands[i].isreg); 6252 inst.instruction |= inst.operands[i].reg << 16; 6253 6254 if (inst.operands[i].preind) 6255 { 6256 if (is_t) 6257 { 6258 inst.error = _("instruction does not accept preindexed addressing"); 6259 return; 6260 } 6261 inst.instruction |= PRE_INDEX; 6262 if (inst.operands[i].writeback) 6263 inst.instruction |= WRITE_BACK; 6264 6265 } 6266 else if (inst.operands[i].postind) 6267 { 6268 assert (inst.operands[i].writeback); 6269 if (is_t) 6270 inst.instruction |= WRITE_BACK; 6271 } 6272 else /* unindexed - only for coprocessor */ 6273 { 6274 inst.error = _("instruction does not accept unindexed addressing"); 6275 return; 6276 } 6277 6278 if (((inst.instruction & WRITE_BACK) || !(inst.instruction & PRE_INDEX)) 6279 && (((inst.instruction & 0x000f0000) >> 16) 6280 == ((inst.instruction & 0x0000f000) >> 12))) 6281 as_warn ((inst.instruction & LOAD_BIT) 6282 ? _("destination register same as write-back base") 6283 : _("source register same as write-back base")); 6284} 6285 6286/* inst.operands[i] was set up by parse_address. Encode it into an 6287 ARM-format mode 2 load or store instruction. If is_t is true, 6288 reject forms that cannot be used with a T instruction (i.e. not 6289 post-indexed). */ 6290static void 6291encode_arm_addr_mode_2 (int i, bfd_boolean is_t) 6292{ 6293 encode_arm_addr_mode_common (i, is_t); 6294 6295 if (inst.operands[i].immisreg) 6296 { 6297 inst.instruction |= INST_IMMEDIATE; /* yes, this is backwards */ 6298 inst.instruction |= inst.operands[i].imm; 6299 if (!inst.operands[i].negative) 6300 inst.instruction |= INDEX_UP; 6301 if (inst.operands[i].shifted) 6302 { 6303 if (inst.operands[i].shift_kind == SHIFT_RRX) 6304 inst.instruction |= SHIFT_ROR << 5; 6305 else 6306 { 6307 inst.instruction |= inst.operands[i].shift_kind << 5; 6308 inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM; 6309 } 6310 } 6311 } 6312 else /* immediate offset in inst.reloc */ 6313 { 6314 if (inst.reloc.type == BFD_RELOC_UNUSED) 6315 inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM; 6316 } 6317} 6318 6319/* inst.operands[i] was set up by parse_address. Encode it into an 6320 ARM-format mode 3 load or store instruction. Reject forms that 6321 cannot be used with such instructions. If is_t is true, reject 6322 forms that cannot be used with a T instruction (i.e. not 6323 post-indexed). */ 6324static void 6325encode_arm_addr_mode_3 (int i, bfd_boolean is_t) 6326{ 6327 if (inst.operands[i].immisreg && inst.operands[i].shifted) 6328 { 6329 inst.error = _("instruction does not accept scaled register index"); 6330 return; 6331 } 6332 6333 encode_arm_addr_mode_common (i, is_t); 6334 6335 if (inst.operands[i].immisreg) 6336 { 6337 inst.instruction |= inst.operands[i].imm; 6338 if (!inst.operands[i].negative) 6339 inst.instruction |= INDEX_UP; 6340 } 6341 else /* immediate offset in inst.reloc */ 6342 { 6343 inst.instruction |= HWOFFSET_IMM; 6344 if (inst.reloc.type == BFD_RELOC_UNUSED) 6345 inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM8; 6346 } 6347} 6348 6349/* inst.operands[i] was set up by parse_address. Encode it into an 6350 ARM-format instruction. Reject all forms which cannot be encoded 6351 into a coprocessor load/store instruction. If wb_ok is false, 6352 reject use of writeback; if unind_ok is false, reject use of 6353 unindexed addressing. If reloc_override is not 0, use it instead 6354 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one 6355 (in which case it is preserved). */ 6356 6357static int 6358encode_arm_cp_address (int i, int wb_ok, int unind_ok, int reloc_override) 6359{ 6360 inst.instruction |= inst.operands[i].reg << 16; 6361 6362 assert (!(inst.operands[i].preind && inst.operands[i].postind)); 6363 6364 if (!inst.operands[i].preind && !inst.operands[i].postind) /* unindexed */ 6365 { 6366 assert (!inst.operands[i].writeback); 6367 if (!unind_ok) 6368 { 6369 inst.error = _("instruction does not support unindexed addressing"); 6370 return FAIL; 6371 } 6372 inst.instruction |= inst.operands[i].imm; 6373 inst.instruction |= INDEX_UP; 6374 return SUCCESS; 6375 } 6376 6377 if (inst.operands[i].preind) 6378 inst.instruction |= PRE_INDEX; 6379 6380 if (inst.operands[i].writeback) 6381 { 6382 if (inst.operands[i].reg == REG_PC) 6383 { 6384 inst.error = _("pc may not be used with write-back"); 6385 return FAIL; 6386 } 6387 if (!wb_ok) 6388 { 6389 inst.error = _("instruction does not support writeback"); 6390 return FAIL; 6391 } 6392 inst.instruction |= WRITE_BACK; 6393 } 6394 6395 if (reloc_override) 6396 inst.reloc.type = reloc_override; 6397 else if ((inst.reloc.type < BFD_RELOC_ARM_ALU_PC_G0_NC 6398 || inst.reloc.type > BFD_RELOC_ARM_LDC_SB_G2) 6399 && inst.reloc.type != BFD_RELOC_ARM_LDR_PC_G0) 6400 { 6401 if (thumb_mode) 6402 inst.reloc.type = BFD_RELOC_ARM_T32_CP_OFF_IMM; 6403 else 6404 inst.reloc.type = BFD_RELOC_ARM_CP_OFF_IMM; 6405 } 6406 6407 return SUCCESS; 6408} 6409 6410/* inst.reloc.exp describes an "=expr" load pseudo-operation. 6411 Determine whether it can be performed with a move instruction; if 6412 it can, convert inst.instruction to that move instruction and 6413 return 1; if it can't, convert inst.instruction to a literal-pool 6414 load and return 0. If this is not a valid thing to do in the 6415 current context, set inst.error and return 1. 6416 6417 inst.operands[i] describes the destination register. */ 6418 6419static int 6420move_or_literal_pool (int i, bfd_boolean thumb_p, bfd_boolean mode_3) 6421{ 6422 unsigned long tbit; 6423 6424 if (thumb_p) 6425 tbit = (inst.instruction > 0xffff) ? THUMB2_LOAD_BIT : THUMB_LOAD_BIT; 6426 else 6427 tbit = LOAD_BIT; 6428 6429 if ((inst.instruction & tbit) == 0) 6430 { 6431 inst.error = _("invalid pseudo operation"); 6432 return 1; 6433 } 6434 if (inst.reloc.exp.X_op != O_constant && inst.reloc.exp.X_op != O_symbol) 6435 { 6436 inst.error = _("constant expression expected"); 6437 return 1; 6438 } 6439 if (inst.reloc.exp.X_op == O_constant) 6440 { 6441 if (thumb_p) 6442 { 6443 if (!unified_syntax && (inst.reloc.exp.X_add_number & ~0xFF) == 0) 6444 { 6445 /* This can be done with a mov(1) instruction. */ 6446 inst.instruction = T_OPCODE_MOV_I8 | (inst.operands[i].reg << 8); 6447 inst.instruction |= inst.reloc.exp.X_add_number; 6448 return 1; 6449 } 6450 } 6451 else 6452 { 6453 int value = encode_arm_immediate (inst.reloc.exp.X_add_number); 6454 if (value != FAIL) 6455 { 6456 /* This can be done with a mov instruction. */ 6457 inst.instruction &= LITERAL_MASK; 6458 inst.instruction |= INST_IMMEDIATE | (OPCODE_MOV << DATA_OP_SHIFT); 6459 inst.instruction |= value & 0xfff; 6460 return 1; 6461 } 6462 6463 value = encode_arm_immediate (~inst.reloc.exp.X_add_number); 6464 if (value != FAIL) 6465 { 6466 /* This can be done with a mvn instruction. */ 6467 inst.instruction &= LITERAL_MASK; 6468 inst.instruction |= INST_IMMEDIATE | (OPCODE_MVN << DATA_OP_SHIFT); 6469 inst.instruction |= value & 0xfff; 6470 return 1; 6471 } 6472 } 6473 } 6474 6475 if (add_to_lit_pool () == FAIL) 6476 { 6477 inst.error = _("literal pool insertion failed"); 6478 return 1; 6479 } 6480 inst.operands[1].reg = REG_PC; 6481 inst.operands[1].isreg = 1; 6482 inst.operands[1].preind = 1; 6483 inst.reloc.pc_rel = 1; 6484 inst.reloc.type = (thumb_p 6485 ? BFD_RELOC_ARM_THUMB_OFFSET 6486 : (mode_3 6487 ? BFD_RELOC_ARM_HWLITERAL 6488 : BFD_RELOC_ARM_LITERAL)); 6489 return 0; 6490} 6491 6492/* Functions for instruction encoding, sorted by subarchitecture. 6493 First some generics; their names are taken from the conventional 6494 bit positions for register arguments in ARM format instructions. */ 6495 6496static void 6497do_noargs (void) 6498{ 6499} 6500 6501static void 6502do_rd (void) 6503{ 6504 inst.instruction |= inst.operands[0].reg << 12; 6505} 6506 6507static void 6508do_rd_rm (void) 6509{ 6510 inst.instruction |= inst.operands[0].reg << 12; 6511 inst.instruction |= inst.operands[1].reg; 6512} 6513 6514static void 6515do_rd_rn (void) 6516{ 6517 inst.instruction |= inst.operands[0].reg << 12; 6518 inst.instruction |= inst.operands[1].reg << 16; 6519} 6520 6521static void 6522do_rn_rd (void) 6523{ 6524 inst.instruction |= inst.operands[0].reg << 16; 6525 inst.instruction |= inst.operands[1].reg << 12; 6526} 6527 6528static void 6529do_rd_rm_rn (void) 6530{ 6531 unsigned Rn = inst.operands[2].reg; 6532 /* Enforce restrictions on SWP instruction. */ 6533 if ((inst.instruction & 0x0fbfffff) == 0x01000090) 6534 constraint (Rn == inst.operands[0].reg || Rn == inst.operands[1].reg, 6535 _("Rn must not overlap other operands")); 6536 inst.instruction |= inst.operands[0].reg << 12; 6537 inst.instruction |= inst.operands[1].reg; 6538 inst.instruction |= Rn << 16; 6539} 6540 6541static void 6542do_rd_rn_rm (void) 6543{ 6544 inst.instruction |= inst.operands[0].reg << 12; 6545 inst.instruction |= inst.operands[1].reg << 16; 6546 inst.instruction |= inst.operands[2].reg; 6547} 6548 6549static void 6550do_rm_rd_rn (void) 6551{ 6552 inst.instruction |= inst.operands[0].reg; 6553 inst.instruction |= inst.operands[1].reg << 12; 6554 inst.instruction |= inst.operands[2].reg << 16; 6555} 6556 6557static void 6558do_imm0 (void) 6559{ 6560 inst.instruction |= inst.operands[0].imm; 6561} 6562 6563static void 6564do_rd_cpaddr (void) 6565{ 6566 inst.instruction |= inst.operands[0].reg << 12; 6567 encode_arm_cp_address (1, TRUE, TRUE, 0); 6568} 6569 6570/* ARM instructions, in alphabetical order by function name (except 6571 that wrapper functions appear immediately after the function they 6572 wrap). */ 6573 6574/* This is a pseudo-op of the form "adr rd, label" to be converted 6575 into a relative address of the form "add rd, pc, #label-.-8". */ 6576 6577static void 6578do_adr (void) 6579{ 6580 inst.instruction |= (inst.operands[0].reg << 12); /* Rd */ 6581 6582 /* Frag hacking will turn this into a sub instruction if the offset turns 6583 out to be negative. */ 6584 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE; 6585 inst.reloc.pc_rel = 1; 6586 inst.reloc.exp.X_add_number -= 8; 6587} 6588 6589/* This is a pseudo-op of the form "adrl rd, label" to be converted 6590 into a relative address of the form: 6591 add rd, pc, #low(label-.-8)" 6592 add rd, rd, #high(label-.-8)" */ 6593 6594static void 6595do_adrl (void) 6596{ 6597 inst.instruction |= (inst.operands[0].reg << 12); /* Rd */ 6598 6599 /* Frag hacking will turn this into a sub instruction if the offset turns 6600 out to be negative. */ 6601 inst.reloc.type = BFD_RELOC_ARM_ADRL_IMMEDIATE; 6602 inst.reloc.pc_rel = 1; 6603 inst.size = INSN_SIZE * 2; 6604 inst.reloc.exp.X_add_number -= 8; 6605} 6606 6607static void 6608do_arit (void) 6609{ 6610 if (!inst.operands[1].present) 6611 inst.operands[1].reg = inst.operands[0].reg; 6612 inst.instruction |= inst.operands[0].reg << 12; 6613 inst.instruction |= inst.operands[1].reg << 16; 6614 encode_arm_shifter_operand (2); 6615} 6616 6617static void 6618do_barrier (void) 6619{ 6620 if (inst.operands[0].present) 6621 { 6622 constraint ((inst.instruction & 0xf0) != 0x40 6623 && (inst.instruction & 0xf0) != 0x50 6624 && inst.operands[0].imm != 0xf, 6625 "bad barrier type"); 6626 inst.instruction |= inst.operands[0].imm; 6627 } 6628 else 6629 inst.instruction |= 0xf; 6630} 6631 6632static void 6633do_bfc (void) 6634{ 6635 unsigned int msb = inst.operands[1].imm + inst.operands[2].imm; 6636 constraint (msb > 32, _("bit-field extends past end of register")); 6637 /* The instruction encoding stores the LSB and MSB, 6638 not the LSB and width. */ 6639 inst.instruction |= inst.operands[0].reg << 12; 6640 inst.instruction |= inst.operands[1].imm << 7; 6641 inst.instruction |= (msb - 1) << 16; 6642} 6643 6644static void 6645do_bfi (void) 6646{ 6647 unsigned int msb; 6648 6649 /* #0 in second position is alternative syntax for bfc, which is 6650 the same instruction but with REG_PC in the Rm field. */ 6651 if (!inst.operands[1].isreg) 6652 inst.operands[1].reg = REG_PC; 6653 6654 msb = inst.operands[2].imm + inst.operands[3].imm; 6655 constraint (msb > 32, _("bit-field extends past end of register")); 6656 /* The instruction encoding stores the LSB and MSB, 6657 not the LSB and width. */ 6658 inst.instruction |= inst.operands[0].reg << 12; 6659 inst.instruction |= inst.operands[1].reg; 6660 inst.instruction |= inst.operands[2].imm << 7; 6661 inst.instruction |= (msb - 1) << 16; 6662} 6663 6664static void 6665do_bfx (void) 6666{ 6667 constraint (inst.operands[2].imm + inst.operands[3].imm > 32, 6668 _("bit-field extends past end of register")); 6669 inst.instruction |= inst.operands[0].reg << 12; 6670 inst.instruction |= inst.operands[1].reg; 6671 inst.instruction |= inst.operands[2].imm << 7; 6672 inst.instruction |= (inst.operands[3].imm - 1) << 16; 6673} 6674 6675/* ARM V5 breakpoint instruction (argument parse) 6676 BKPT <16 bit unsigned immediate> 6677 Instruction is not conditional. 6678 The bit pattern given in insns[] has the COND_ALWAYS condition, 6679 and it is an error if the caller tried to override that. */ 6680 6681static void 6682do_bkpt (void) 6683{ 6684 /* Top 12 of 16 bits to bits 19:8. */ 6685 inst.instruction |= (inst.operands[0].imm & 0xfff0) << 4; 6686 6687 /* Bottom 4 of 16 bits to bits 3:0. */ 6688 inst.instruction |= inst.operands[0].imm & 0xf; 6689} 6690 6691static void 6692encode_branch (int default_reloc) 6693{ 6694 if (inst.operands[0].hasreloc) 6695 { 6696 constraint (inst.operands[0].imm != BFD_RELOC_ARM_PLT32, 6697 _("the only suffix valid here is '(plt)'")); 6698 inst.reloc.type = BFD_RELOC_ARM_PLT32; 6699 } 6700 else 6701 { 6702 inst.reloc.type = default_reloc; 6703 } 6704 inst.reloc.pc_rel = 1; 6705} 6706 6707static void 6708do_branch (void) 6709{ 6710#ifdef OBJ_ELF 6711 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4) 6712 encode_branch (BFD_RELOC_ARM_PCREL_JUMP); 6713 else 6714#endif 6715 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH); 6716} 6717 6718static void 6719do_bl (void) 6720{ 6721#ifdef OBJ_ELF 6722 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4) 6723 { 6724 if (inst.cond == COND_ALWAYS) 6725 encode_branch (BFD_RELOC_ARM_PCREL_CALL); 6726 else 6727 encode_branch (BFD_RELOC_ARM_PCREL_JUMP); 6728 } 6729 else 6730#endif 6731 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH); 6732} 6733 6734/* ARM V5 branch-link-exchange instruction (argument parse) 6735 BLX <target_addr> ie BLX(1) 6736 BLX{<condition>} <Rm> ie BLX(2) 6737 Unfortunately, there are two different opcodes for this mnemonic. 6738 So, the insns[].value is not used, and the code here zaps values 6739 into inst.instruction. 6740 Also, the <target_addr> can be 25 bits, hence has its own reloc. */ 6741 6742static void 6743do_blx (void) 6744{ 6745 if (inst.operands[0].isreg) 6746 { 6747 /* Arg is a register; the opcode provided by insns[] is correct. 6748 It is not illegal to do "blx pc", just useless. */ 6749 if (inst.operands[0].reg == REG_PC) 6750 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful")); 6751 6752 inst.instruction |= inst.operands[0].reg; 6753 } 6754 else 6755 { 6756 /* Arg is an address; this instruction cannot be executed 6757 conditionally, and the opcode must be adjusted. */ 6758 constraint (inst.cond != COND_ALWAYS, BAD_COND); 6759 inst.instruction = 0xfa000000; 6760#ifdef OBJ_ELF 6761 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4) 6762 encode_branch (BFD_RELOC_ARM_PCREL_CALL); 6763 else 6764#endif 6765 encode_branch (BFD_RELOC_ARM_PCREL_BLX); 6766 } 6767} 6768 6769static void 6770do_bx (void) 6771{ 6772 if (inst.operands[0].reg == REG_PC) 6773 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful")); 6774 6775 inst.instruction |= inst.operands[0].reg; 6776} 6777 6778 6779/* ARM v5TEJ. Jump to Jazelle code. */ 6780 6781static void 6782do_bxj (void) 6783{ 6784 if (inst.operands[0].reg == REG_PC) 6785 as_tsktsk (_("use of r15 in bxj is not really useful")); 6786 6787 inst.instruction |= inst.operands[0].reg; 6788} 6789 6790/* Co-processor data operation: 6791 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} 6792 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */ 6793static void 6794do_cdp (void) 6795{ 6796 inst.instruction |= inst.operands[0].reg << 8; 6797 inst.instruction |= inst.operands[1].imm << 20; 6798 inst.instruction |= inst.operands[2].reg << 12; 6799 inst.instruction |= inst.operands[3].reg << 16; 6800 inst.instruction |= inst.operands[4].reg; 6801 inst.instruction |= inst.operands[5].imm << 5; 6802} 6803 6804static void 6805do_cmp (void) 6806{ 6807 inst.instruction |= inst.operands[0].reg << 16; 6808 encode_arm_shifter_operand (1); 6809} 6810 6811/* Transfer between coprocessor and ARM registers. 6812 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>} 6813 MRC2 6814 MCR{cond} 6815 MCR2 6816 6817 No special properties. */ 6818 6819static void 6820do_co_reg (void) 6821{ 6822 inst.instruction |= inst.operands[0].reg << 8; 6823 inst.instruction |= inst.operands[1].imm << 21; 6824 /* If this is a vector we are using the APSR_nzcv syntax, encode as r15 */ 6825 if (inst.operands[2].isvec != 0) 6826 inst.instruction |= 15 << 12; 6827 else 6828 inst.instruction |= inst.operands[2].reg << 12; 6829 inst.instruction |= inst.operands[3].reg << 16; 6830 inst.instruction |= inst.operands[4].reg; 6831 inst.instruction |= inst.operands[5].imm << 5; 6832} 6833 6834/* Transfer between coprocessor register and pair of ARM registers. 6835 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>. 6836 MCRR2 6837 MRRC{cond} 6838 MRRC2 6839 6840 Two XScale instructions are special cases of these: 6841 6842 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0 6843 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0 6844 6845 Result unpredicatable if Rd or Rn is R15. */ 6846 6847static void 6848do_co_reg2c (void) 6849{ 6850 inst.instruction |= inst.operands[0].reg << 8; 6851 inst.instruction |= inst.operands[1].imm << 4; 6852 inst.instruction |= inst.operands[2].reg << 12; 6853 inst.instruction |= inst.operands[3].reg << 16; 6854 inst.instruction |= inst.operands[4].reg; 6855} 6856 6857static void 6858do_cpsi (void) 6859{ 6860 inst.instruction |= inst.operands[0].imm << 6; 6861 if (inst.operands[1].present) 6862 { 6863 inst.instruction |= CPSI_MMOD; 6864 inst.instruction |= inst.operands[1].imm; 6865 } 6866} 6867 6868static void 6869do_dbg (void) 6870{ 6871 inst.instruction |= inst.operands[0].imm; 6872} 6873 6874static void 6875do_it (void) 6876{ 6877 /* There is no IT instruction in ARM mode. We 6878 process it but do not generate code for it. */ 6879 inst.size = 0; 6880} 6881 6882static void 6883do_ldmstm (void) 6884{ 6885 int base_reg = inst.operands[0].reg; 6886 int range = inst.operands[1].imm; 6887 6888 inst.instruction |= base_reg << 16; 6889 inst.instruction |= range; 6890 6891 if (inst.operands[1].writeback) 6892 inst.instruction |= LDM_TYPE_2_OR_3; 6893 6894 if (inst.operands[0].writeback) 6895 { 6896 inst.instruction |= WRITE_BACK; 6897 /* Check for unpredictable uses of writeback. */ 6898 if (inst.instruction & LOAD_BIT) 6899 { 6900 /* Not allowed in LDM type 2. */ 6901 if ((inst.instruction & LDM_TYPE_2_OR_3) 6902 && ((range & (1 << REG_PC)) == 0)) 6903 as_warn (_("writeback of base register is UNPREDICTABLE")); 6904 /* Only allowed if base reg not in list for other types. */ 6905 else if (range & (1 << base_reg)) 6906 as_warn (_("writeback of base register when in register list is UNPREDICTABLE")); 6907 } 6908 else /* STM. */ 6909 { 6910 /* Not allowed for type 2. */ 6911 if (inst.instruction & LDM_TYPE_2_OR_3) 6912 as_warn (_("writeback of base register is UNPREDICTABLE")); 6913 /* Only allowed if base reg not in list, or first in list. */ 6914 else if ((range & (1 << base_reg)) 6915 && (range & ((1 << base_reg) - 1))) 6916 as_warn (_("if writeback register is in list, it must be the lowest reg in the list")); 6917 } 6918 } 6919} 6920 6921/* ARMv5TE load-consecutive (argument parse) 6922 Mode is like LDRH. 6923 6924 LDRccD R, mode 6925 STRccD R, mode. */ 6926 6927static void 6928do_ldrd (void) 6929{ 6930 constraint (inst.operands[0].reg % 2 != 0, 6931 _("first destination register must be even")); 6932 constraint (inst.operands[1].present 6933 && inst.operands[1].reg != inst.operands[0].reg + 1, 6934 _("can only load two consecutive registers")); 6935 constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here")); 6936 constraint (!inst.operands[2].isreg, _("'[' expected")); 6937 6938 if (!inst.operands[1].present) 6939 inst.operands[1].reg = inst.operands[0].reg + 1; 6940 6941 if (inst.instruction & LOAD_BIT) 6942 { 6943 /* encode_arm_addr_mode_3 will diagnose overlap between the base 6944 register and the first register written; we have to diagnose 6945 overlap between the base and the second register written here. */ 6946 6947 if (inst.operands[2].reg == inst.operands[1].reg 6948 && (inst.operands[2].writeback || inst.operands[2].postind)) 6949 as_warn (_("base register written back, and overlaps " 6950 "second destination register")); 6951 6952 /* For an index-register load, the index register must not overlap the 6953 destination (even if not write-back). */ 6954 else if (inst.operands[2].immisreg 6955 && ((unsigned) inst.operands[2].imm == inst.operands[0].reg 6956 || (unsigned) inst.operands[2].imm == inst.operands[1].reg)) 6957 as_warn (_("index register overlaps destination register")); 6958 } 6959 6960 inst.instruction |= inst.operands[0].reg << 12; 6961 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE); 6962} 6963 6964static void 6965do_ldrex (void) 6966{ 6967 constraint (!inst.operands[1].isreg || !inst.operands[1].preind 6968 || inst.operands[1].postind || inst.operands[1].writeback 6969 || inst.operands[1].immisreg || inst.operands[1].shifted 6970 || inst.operands[1].negative 6971 /* This can arise if the programmer has written 6972 strex rN, rM, foo 6973 or if they have mistakenly used a register name as the last 6974 operand, eg: 6975 strex rN, rM, rX 6976 It is very difficult to distinguish between these two cases 6977 because "rX" might actually be a label. ie the register 6978 name has been occluded by a symbol of the same name. So we 6979 just generate a general 'bad addressing mode' type error 6980 message and leave it up to the programmer to discover the 6981 true cause and fix their mistake. */ 6982 || (inst.operands[1].reg == REG_PC), 6983 BAD_ADDR_MODE); 6984 6985 constraint (inst.reloc.exp.X_op != O_constant 6986 || inst.reloc.exp.X_add_number != 0, 6987 _("offset must be zero in ARM encoding")); 6988 6989 inst.instruction |= inst.operands[0].reg << 12; 6990 inst.instruction |= inst.operands[1].reg << 16; 6991 inst.reloc.type = BFD_RELOC_UNUSED; 6992} 6993 6994static void 6995do_ldrexd (void) 6996{ 6997 constraint (inst.operands[0].reg % 2 != 0, 6998 _("even register required")); 6999 constraint (inst.operands[1].present 7000 && inst.operands[1].reg != inst.operands[0].reg + 1, 7001 _("can only load two consecutive registers")); 7002 /* If op 1 were present and equal to PC, this function wouldn't 7003 have been called in the first place. */ 7004 constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here")); 7005 7006 inst.instruction |= inst.operands[0].reg << 12; 7007 inst.instruction |= inst.operands[2].reg << 16; 7008} 7009 7010static void 7011do_ldst (void) 7012{ 7013 inst.instruction |= inst.operands[0].reg << 12; 7014 if (!inst.operands[1].isreg) 7015 if (move_or_literal_pool (0, /*thumb_p=*/FALSE, /*mode_3=*/FALSE)) 7016 return; 7017 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE); 7018} 7019 7020static void 7021do_ldstt (void) 7022{ 7023 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and 7024 reject [Rn,...]. */ 7025 if (inst.operands[1].preind) 7026 { 7027 constraint (inst.reloc.exp.X_op != O_constant || 7028 inst.reloc.exp.X_add_number != 0, 7029 _("this instruction requires a post-indexed address")); 7030 7031 inst.operands[1].preind = 0; 7032 inst.operands[1].postind = 1; 7033 inst.operands[1].writeback = 1; 7034 } 7035 inst.instruction |= inst.operands[0].reg << 12; 7036 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE); 7037} 7038 7039/* Halfword and signed-byte load/store operations. */ 7040 7041static void 7042do_ldstv4 (void) 7043{ 7044 inst.instruction |= inst.operands[0].reg << 12; 7045 if (!inst.operands[1].isreg) 7046 if (move_or_literal_pool (0, /*thumb_p=*/FALSE, /*mode_3=*/TRUE)) 7047 return; 7048 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE); 7049} 7050 7051static void 7052do_ldsttv4 (void) 7053{ 7054 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and 7055 reject [Rn,...]. */ 7056 if (inst.operands[1].preind) 7057 { 7058 constraint (inst.reloc.exp.X_op != O_constant || 7059 inst.reloc.exp.X_add_number != 0, 7060 _("this instruction requires a post-indexed address")); 7061 7062 inst.operands[1].preind = 0; 7063 inst.operands[1].postind = 1; 7064 inst.operands[1].writeback = 1; 7065 } 7066 inst.instruction |= inst.operands[0].reg << 12; 7067 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE); 7068} 7069 7070/* Co-processor register load/store. 7071 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */ 7072static void 7073do_lstc (void) 7074{ 7075 inst.instruction |= inst.operands[0].reg << 8; 7076 inst.instruction |= inst.operands[1].reg << 12; 7077 encode_arm_cp_address (2, TRUE, TRUE, 0); 7078} 7079 7080static void 7081do_mlas (void) 7082{ 7083 /* This restriction does not apply to mls (nor to mla in v6 or later). */ 7084 if (inst.operands[0].reg == inst.operands[1].reg 7085 && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6) 7086 && !(inst.instruction & 0x00400000)) 7087 as_tsktsk (_("Rd and Rm should be different in mla")); 7088 7089 inst.instruction |= inst.operands[0].reg << 16; 7090 inst.instruction |= inst.operands[1].reg; 7091 inst.instruction |= inst.operands[2].reg << 8; 7092 inst.instruction |= inst.operands[3].reg << 12; 7093} 7094 7095static void 7096do_mov (void) 7097{ 7098 inst.instruction |= inst.operands[0].reg << 12; 7099 encode_arm_shifter_operand (1); 7100} 7101 7102/* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */ 7103static void 7104do_mov16 (void) 7105{ 7106 bfd_vma imm; 7107 bfd_boolean top; 7108 7109 top = (inst.instruction & 0x00400000) != 0; 7110 constraint (top && inst.reloc.type == BFD_RELOC_ARM_MOVW, 7111 _(":lower16: not allowed this instruction")); 7112 constraint (!top && inst.reloc.type == BFD_RELOC_ARM_MOVT, 7113 _(":upper16: not allowed instruction")); 7114 inst.instruction |= inst.operands[0].reg << 12; 7115 if (inst.reloc.type == BFD_RELOC_UNUSED) 7116 { 7117 imm = inst.reloc.exp.X_add_number; 7118 /* The value is in two pieces: 0:11, 16:19. */ 7119 inst.instruction |= (imm & 0x00000fff); 7120 inst.instruction |= (imm & 0x0000f000) << 4; 7121 } 7122} 7123 7124static void do_vfp_nsyn_opcode (const char *); 7125 7126static int 7127do_vfp_nsyn_mrs (void) 7128{ 7129 if (inst.operands[0].isvec) 7130 { 7131 if (inst.operands[1].reg != 1) 7132 first_error (_("operand 1 must be FPSCR")); 7133 memset (&inst.operands[0], '\0', sizeof (inst.operands[0])); 7134 memset (&inst.operands[1], '\0', sizeof (inst.operands[1])); 7135 do_vfp_nsyn_opcode ("fmstat"); 7136 } 7137 else if (inst.operands[1].isvec) 7138 do_vfp_nsyn_opcode ("fmrx"); 7139 else 7140 return FAIL; 7141 7142 return SUCCESS; 7143} 7144 7145static int 7146do_vfp_nsyn_msr (void) 7147{ 7148 if (inst.operands[0].isvec) 7149 do_vfp_nsyn_opcode ("fmxr"); 7150 else 7151 return FAIL; 7152 7153 return SUCCESS; 7154} 7155 7156static void 7157do_vfp_vmrs (void) 7158{ 7159 int rt; 7160 7161 /* The destination register can be r0-r14 or APSR_nzcv */ 7162 if (inst.operands[0].reg > 14) 7163 { 7164 inst.error = BAD_PC; 7165 return; 7166 } 7167 7168 /* If the destination is r13 and not in ARM mode then unprefictable */ 7169 if (thumb_mode && inst.operands[0].reg == REG_SP) 7170 { 7171 inst.error = BAD_SP; 7172 return; 7173 } 7174 7175 /* If the destination is APSR_nzcv */ 7176 if (inst.operands[0].isvec && inst.operands[1].reg != 1) 7177 { 7178 inst.error = BAD_VMRS; 7179 return; 7180 } 7181 7182 if (inst.operands[0].isvec) 7183 rt = 15; 7184 else 7185 rt = inst.operands[0].reg; 7186 7187 /* Or in the registers to use */ 7188 inst.instruction |= rt << 12; 7189 inst.instruction |= inst.operands[1].reg << 16; 7190} 7191 7192static void 7193do_vfp_vmsr (void) 7194{ 7195 /* The destination register can be r0-r14 or APSR_nzcv */ 7196 if (inst.operands[1].reg > 14) 7197 { 7198 inst.error = BAD_PC; 7199 return; 7200 } 7201 7202 /* If the destination is r13 and not in ARM mode then unprefictable */ 7203 if (thumb_mode && inst.operands[0].reg == REG_SP) 7204 { 7205 inst.error = BAD_SP; 7206 return; 7207 } 7208 7209 /* Or in the registers to use */ 7210 inst.instruction |= inst.operands[1].reg << 12; 7211 inst.instruction |= inst.operands[0].reg << 16; 7212} 7213 7214static void 7215do_mrs (void) 7216{ 7217 if (do_vfp_nsyn_mrs () == SUCCESS) 7218 return; 7219 7220 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */ 7221 constraint ((inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f)) 7222 != (PSR_c|PSR_f), 7223 _("'CPSR' or 'SPSR' expected")); 7224 inst.instruction |= inst.operands[0].reg << 12; 7225 inst.instruction |= (inst.operands[1].imm & SPSR_BIT); 7226} 7227 7228/* Two possible forms: 7229 "{C|S}PSR_<field>, Rm", 7230 "{C|S}PSR_f, #expression". */ 7231 7232static void 7233do_msr (void) 7234{ 7235 if (do_vfp_nsyn_msr () == SUCCESS) 7236 return; 7237 7238 inst.instruction |= inst.operands[0].imm; 7239 if (inst.operands[1].isreg) 7240 inst.instruction |= inst.operands[1].reg; 7241 else 7242 { 7243 inst.instruction |= INST_IMMEDIATE; 7244 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE; 7245 inst.reloc.pc_rel = 0; 7246 } 7247} 7248 7249static void 7250do_mul (void) 7251{ 7252 if (!inst.operands[2].present) 7253 inst.operands[2].reg = inst.operands[0].reg; 7254 inst.instruction |= inst.operands[0].reg << 16; 7255 inst.instruction |= inst.operands[1].reg; 7256 inst.instruction |= inst.operands[2].reg << 8; 7257 7258 if (inst.operands[0].reg == inst.operands[1].reg 7259 && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6)) 7260 as_tsktsk (_("Rd and Rm should be different in mul")); 7261} 7262 7263/* Long Multiply Parser 7264 UMULL RdLo, RdHi, Rm, Rs 7265 SMULL RdLo, RdHi, Rm, Rs 7266 UMLAL RdLo, RdHi, Rm, Rs 7267 SMLAL RdLo, RdHi, Rm, Rs. */ 7268 7269static void 7270do_mull (void) 7271{ 7272 inst.instruction |= inst.operands[0].reg << 12; 7273 inst.instruction |= inst.operands[1].reg << 16; 7274 inst.instruction |= inst.operands[2].reg; 7275 inst.instruction |= inst.operands[3].reg << 8; 7276 7277 /* rdhi, rdlo and rm must all be different prior to ARMv6. */ 7278 if (inst.operands[0].reg == inst.operands[1].reg 7279 || ((inst.operands[0].reg == inst.operands[2].reg 7280 || inst.operands[1].reg == inst.operands[2].reg) 7281 && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6))) 7282 as_tsktsk (_("rdhi, rdlo and rm must all be different")); 7283} 7284 7285static void 7286do_nop (void) 7287{ 7288 if (inst.operands[0].present) 7289 { 7290 /* Architectural NOP hints are CPSR sets with no bits selected. */ 7291 inst.instruction &= 0xf0000000; 7292 inst.instruction |= 0x0320f000 + inst.operands[0].imm; 7293 } 7294} 7295 7296/* ARM V6 Pack Halfword Bottom Top instruction (argument parse). 7297 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>} 7298 Condition defaults to COND_ALWAYS. 7299 Error if Rd, Rn or Rm are R15. */ 7300 7301static void 7302do_pkhbt (void) 7303{ 7304 inst.instruction |= inst.operands[0].reg << 12; 7305 inst.instruction |= inst.operands[1].reg << 16; 7306 inst.instruction |= inst.operands[2].reg; 7307 if (inst.operands[3].present) 7308 encode_arm_shift (3); 7309} 7310 7311/* ARM V6 PKHTB (Argument Parse). */ 7312 7313static void 7314do_pkhtb (void) 7315{ 7316 if (!inst.operands[3].present) 7317 { 7318 /* If the shift specifier is omitted, turn the instruction 7319 into pkhbt rd, rm, rn. */ 7320 inst.instruction &= 0xfff00010; 7321 inst.instruction |= inst.operands[0].reg << 12; 7322 inst.instruction |= inst.operands[1].reg; 7323 inst.instruction |= inst.operands[2].reg << 16; 7324 } 7325 else 7326 { 7327 inst.instruction |= inst.operands[0].reg << 12; 7328 inst.instruction |= inst.operands[1].reg << 16; 7329 inst.instruction |= inst.operands[2].reg; 7330 encode_arm_shift (3); 7331 } 7332} 7333 7334/* ARMv5TE: Preload-Cache 7335 7336 PLD <addr_mode> 7337 7338 Syntactically, like LDR with B=1, W=0, L=1. */ 7339 7340static void 7341do_pld (void) 7342{ 7343 constraint (!inst.operands[0].isreg, 7344 _("'[' expected after PLD mnemonic")); 7345 constraint (inst.operands[0].postind, 7346 _("post-indexed expression used in preload instruction")); 7347 constraint (inst.operands[0].writeback, 7348 _("writeback used in preload instruction")); 7349 constraint (!inst.operands[0].preind, 7350 _("unindexed addressing used in preload instruction")); 7351 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE); 7352} 7353 7354/* ARMv7: PLI <addr_mode> */ 7355static void 7356do_pli (void) 7357{ 7358 constraint (!inst.operands[0].isreg, 7359 _("'[' expected after PLI mnemonic")); 7360 constraint (inst.operands[0].postind, 7361 _("post-indexed expression used in preload instruction")); 7362 constraint (inst.operands[0].writeback, 7363 _("writeback used in preload instruction")); 7364 constraint (!inst.operands[0].preind, 7365 _("unindexed addressing used in preload instruction")); 7366 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE); 7367 inst.instruction &= ~PRE_INDEX; 7368} 7369 7370static void 7371do_push_pop (void) 7372{ 7373 inst.operands[1] = inst.operands[0]; 7374 memset (&inst.operands[0], 0, sizeof inst.operands[0]); 7375 inst.operands[0].isreg = 1; 7376 inst.operands[0].writeback = 1; 7377 inst.operands[0].reg = REG_SP; 7378 do_ldmstm (); 7379} 7380 7381/* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the 7382 word at the specified address and the following word 7383 respectively. 7384 Unconditionally executed. 7385 Error if Rn is R15. */ 7386 7387static void 7388do_rfe (void) 7389{ 7390 inst.instruction |= inst.operands[0].reg << 16; 7391 if (inst.operands[0].writeback) 7392 inst.instruction |= WRITE_BACK; 7393} 7394 7395/* ARM V6 ssat (argument parse). */ 7396 7397static void 7398do_ssat (void) 7399{ 7400 inst.instruction |= inst.operands[0].reg << 12; 7401 inst.instruction |= (inst.operands[1].imm - 1) << 16; 7402 inst.instruction |= inst.operands[2].reg; 7403 7404 if (inst.operands[3].present) 7405 encode_arm_shift (3); 7406} 7407 7408/* ARM V6 usat (argument parse). */ 7409 7410static void 7411do_usat (void) 7412{ 7413 inst.instruction |= inst.operands[0].reg << 12; 7414 inst.instruction |= inst.operands[1].imm << 16; 7415 inst.instruction |= inst.operands[2].reg; 7416 7417 if (inst.operands[3].present) 7418 encode_arm_shift (3); 7419} 7420 7421/* ARM V6 ssat16 (argument parse). */ 7422 7423static void 7424do_ssat16 (void) 7425{ 7426 inst.instruction |= inst.operands[0].reg << 12; 7427 inst.instruction |= ((inst.operands[1].imm - 1) << 16); 7428 inst.instruction |= inst.operands[2].reg; 7429} 7430 7431static void 7432do_usat16 (void) 7433{ 7434 inst.instruction |= inst.operands[0].reg << 12; 7435 inst.instruction |= inst.operands[1].imm << 16; 7436 inst.instruction |= inst.operands[2].reg; 7437} 7438 7439/* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while 7440 preserving the other bits. 7441 7442 setend <endian_specifier>, where <endian_specifier> is either 7443 BE or LE. */ 7444 7445static void 7446do_setend (void) 7447{ 7448 if (inst.operands[0].imm) 7449 inst.instruction |= 0x200; 7450} 7451 7452static void 7453do_shift (void) 7454{ 7455 unsigned int Rm = (inst.operands[1].present 7456 ? inst.operands[1].reg 7457 : inst.operands[0].reg); 7458 7459 inst.instruction |= inst.operands[0].reg << 12; 7460 inst.instruction |= Rm; 7461 if (inst.operands[2].isreg) /* Rd, {Rm,} Rs */ 7462 { 7463 inst.instruction |= inst.operands[2].reg << 8; 7464 inst.instruction |= SHIFT_BY_REG; 7465 } 7466 else 7467 inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM; 7468} 7469 7470static void 7471do_smc (void) 7472{ 7473 inst.reloc.type = BFD_RELOC_ARM_SMC; 7474 inst.reloc.pc_rel = 0; 7475} 7476 7477static void 7478do_swi (void) 7479{ 7480 inst.reloc.type = BFD_RELOC_ARM_SWI; 7481 inst.reloc.pc_rel = 0; 7482} 7483 7484/* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse) 7485 SMLAxy{cond} Rd,Rm,Rs,Rn 7486 SMLAWy{cond} Rd,Rm,Rs,Rn 7487 Error if any register is R15. */ 7488 7489static void 7490do_smla (void) 7491{ 7492 inst.instruction |= inst.operands[0].reg << 16; 7493 inst.instruction |= inst.operands[1].reg; 7494 inst.instruction |= inst.operands[2].reg << 8; 7495 inst.instruction |= inst.operands[3].reg << 12; 7496} 7497 7498/* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse) 7499 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs 7500 Error if any register is R15. 7501 Warning if Rdlo == Rdhi. */ 7502 7503static void 7504do_smlal (void) 7505{ 7506 inst.instruction |= inst.operands[0].reg << 12; 7507 inst.instruction |= inst.operands[1].reg << 16; 7508 inst.instruction |= inst.operands[2].reg; 7509 inst.instruction |= inst.operands[3].reg << 8; 7510 7511 if (inst.operands[0].reg == inst.operands[1].reg) 7512 as_tsktsk (_("rdhi and rdlo must be different")); 7513} 7514 7515/* ARM V5E (El Segundo) signed-multiply (argument parse) 7516 SMULxy{cond} Rd,Rm,Rs 7517 Error if any register is R15. */ 7518 7519static void 7520do_smul (void) 7521{ 7522 inst.instruction |= inst.operands[0].reg << 16; 7523 inst.instruction |= inst.operands[1].reg; 7524 inst.instruction |= inst.operands[2].reg << 8; 7525} 7526 7527/* ARM V6 srs (argument parse). The variable fields in the encoding are 7528 the same for both ARM and Thumb-2. */ 7529 7530static void 7531do_srs (void) 7532{ 7533 int reg; 7534 7535 if (inst.operands[0].present) 7536 { 7537 reg = inst.operands[0].reg; 7538 constraint (reg != 13, _("SRS base register must be r13")); 7539 } 7540 else 7541 reg = 13; 7542 7543 inst.instruction |= reg << 16; 7544 inst.instruction |= inst.operands[1].imm; 7545 if (inst.operands[0].writeback || inst.operands[1].writeback) 7546 inst.instruction |= WRITE_BACK; 7547} 7548 7549/* ARM V6 strex (argument parse). */ 7550 7551static void 7552do_strex (void) 7553{ 7554 constraint (!inst.operands[2].isreg || !inst.operands[2].preind 7555 || inst.operands[2].postind || inst.operands[2].writeback 7556 || inst.operands[2].immisreg || inst.operands[2].shifted 7557 || inst.operands[2].negative 7558 /* See comment in do_ldrex(). */ 7559 || (inst.operands[2].reg == REG_PC), 7560 BAD_ADDR_MODE); 7561 7562 constraint (inst.operands[0].reg == inst.operands[1].reg 7563 || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP); 7564 7565 constraint (inst.reloc.exp.X_op != O_constant 7566 || inst.reloc.exp.X_add_number != 0, 7567 _("offset must be zero in ARM encoding")); 7568 7569 inst.instruction |= inst.operands[0].reg << 12; 7570 inst.instruction |= inst.operands[1].reg; 7571 inst.instruction |= inst.operands[2].reg << 16; 7572 inst.reloc.type = BFD_RELOC_UNUSED; 7573} 7574 7575static void 7576do_strexd (void) 7577{ 7578 constraint (inst.operands[1].reg % 2 != 0, 7579 _("even register required")); 7580 constraint (inst.operands[2].present 7581 && inst.operands[2].reg != inst.operands[1].reg + 1, 7582 _("can only store two consecutive registers")); 7583 /* If op 2 were present and equal to PC, this function wouldn't 7584 have been called in the first place. */ 7585 constraint (inst.operands[1].reg == REG_LR, _("r14 not allowed here")); 7586 7587 constraint (inst.operands[0].reg == inst.operands[1].reg 7588 || inst.operands[0].reg == inst.operands[1].reg + 1 7589 || inst.operands[0].reg == inst.operands[3].reg, 7590 BAD_OVERLAP); 7591 7592 inst.instruction |= inst.operands[0].reg << 12; 7593 inst.instruction |= inst.operands[1].reg; 7594 inst.instruction |= inst.operands[3].reg << 16; 7595} 7596 7597/* ARM V6 SXTAH extracts a 16-bit value from a register, sign 7598 extends it to 32-bits, and adds the result to a value in another 7599 register. You can specify a rotation by 0, 8, 16, or 24 bits 7600 before extracting the 16-bit value. 7601 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>} 7602 Condition defaults to COND_ALWAYS. 7603 Error if any register uses R15. */ 7604 7605static void 7606do_sxtah (void) 7607{ 7608 inst.instruction |= inst.operands[0].reg << 12; 7609 inst.instruction |= inst.operands[1].reg << 16; 7610 inst.instruction |= inst.operands[2].reg; 7611 inst.instruction |= inst.operands[3].imm << 10; 7612} 7613 7614/* ARM V6 SXTH. 7615 7616 SXTH {<cond>} <Rd>, <Rm>{, <rotation>} 7617 Condition defaults to COND_ALWAYS. 7618 Error if any register uses R15. */ 7619 7620static void 7621do_sxth (void) 7622{ 7623 inst.instruction |= inst.operands[0].reg << 12; 7624 inst.instruction |= inst.operands[1].reg; 7625 inst.instruction |= inst.operands[2].imm << 10; 7626} 7627 7628/* VFP instructions. In a logical order: SP variant first, monad 7629 before dyad, arithmetic then move then load/store. */ 7630 7631static void 7632do_vfp_sp_monadic (void) 7633{ 7634 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); 7635 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm); 7636} 7637 7638static void 7639do_vfp_sp_dyadic (void) 7640{ 7641 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); 7642 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sn); 7643 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Sm); 7644} 7645 7646static void 7647do_vfp_sp_compare_z (void) 7648{ 7649 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); 7650} 7651 7652static void 7653do_vfp_dp_sp_cvt (void) 7654{ 7655 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); 7656 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm); 7657} 7658 7659static void 7660do_vfp_sp_dp_cvt (void) 7661{ 7662 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); 7663 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dm); 7664} 7665 7666static void 7667do_vfp_reg_from_sp (void) 7668{ 7669 inst.instruction |= inst.operands[0].reg << 12; 7670 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sn); 7671} 7672 7673static void 7674do_vfp_reg2_from_sp2 (void) 7675{ 7676 constraint (inst.operands[2].imm != 2, 7677 _("only two consecutive VFP SP registers allowed here")); 7678 inst.instruction |= inst.operands[0].reg << 12; 7679 inst.instruction |= inst.operands[1].reg << 16; 7680 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Sm); 7681} 7682 7683static void 7684do_vfp_sp_from_reg (void) 7685{ 7686 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sn); 7687 inst.instruction |= inst.operands[1].reg << 12; 7688} 7689 7690static void 7691do_vfp_sp2_from_reg2 (void) 7692{ 7693 constraint (inst.operands[0].imm != 2, 7694 _("only two consecutive VFP SP registers allowed here")); 7695 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sm); 7696 inst.instruction |= inst.operands[1].reg << 12; 7697 inst.instruction |= inst.operands[2].reg << 16; 7698} 7699 7700static void 7701do_vfp_sp_ldst (void) 7702{ 7703 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); 7704 encode_arm_cp_address (1, FALSE, TRUE, 0); 7705} 7706 7707static void 7708do_vfp_dp_ldst (void) 7709{ 7710 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); 7711 encode_arm_cp_address (1, FALSE, TRUE, 0); 7712} 7713 7714 7715static void 7716vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type) 7717{ 7718 if (inst.operands[0].writeback) 7719 inst.instruction |= WRITE_BACK; 7720 else 7721 constraint (ldstm_type != VFP_LDSTMIA, 7722 _("this addressing mode requires base-register writeback")); 7723 inst.instruction |= inst.operands[0].reg << 16; 7724 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sd); 7725 inst.instruction |= inst.operands[1].imm; 7726} 7727 7728static void 7729vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type) 7730{ 7731 int count; 7732 7733 if (inst.operands[0].writeback) 7734 inst.instruction |= WRITE_BACK; 7735 else 7736 constraint (ldstm_type != VFP_LDSTMIA && ldstm_type != VFP_LDSTMIAX, 7737 _("this addressing mode requires base-register writeback")); 7738 7739 inst.instruction |= inst.operands[0].reg << 16; 7740 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd); 7741 7742 count = inst.operands[1].imm << 1; 7743 if (ldstm_type == VFP_LDSTMIAX || ldstm_type == VFP_LDSTMDBX) 7744 count += 1; 7745 7746 inst.instruction |= count; 7747} 7748 7749static void 7750do_vfp_sp_ldstmia (void) 7751{ 7752 vfp_sp_ldstm (VFP_LDSTMIA); 7753} 7754 7755static void 7756do_vfp_sp_ldstmdb (void) 7757{ 7758 vfp_sp_ldstm (VFP_LDSTMDB); 7759} 7760 7761static void 7762do_vfp_dp_ldstmia (void) 7763{ 7764 vfp_dp_ldstm (VFP_LDSTMIA); 7765} 7766 7767static void 7768do_vfp_dp_ldstmdb (void) 7769{ 7770 vfp_dp_ldstm (VFP_LDSTMDB); 7771} 7772 7773static void 7774do_vfp_xp_ldstmia (void) 7775{ 7776 vfp_dp_ldstm (VFP_LDSTMIAX); 7777} 7778 7779static void 7780do_vfp_xp_ldstmdb (void) 7781{ 7782 vfp_dp_ldstm (VFP_LDSTMDBX); 7783} 7784 7785static void 7786do_vfp_dp_rd_rm (void) 7787{ 7788 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); 7789 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dm); 7790} 7791 7792static void 7793do_vfp_dp_rn_rd (void) 7794{ 7795 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dn); 7796 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd); 7797} 7798 7799static void 7800do_vfp_dp_rd_rn (void) 7801{ 7802 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); 7803 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dn); 7804} 7805 7806static void 7807do_vfp_dp_rd_rn_rm (void) 7808{ 7809 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); 7810 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dn); 7811 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Dm); 7812} 7813 7814static void 7815do_vfp_dp_rd (void) 7816{ 7817 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); 7818} 7819 7820static void 7821do_vfp_dp_rm_rd_rn (void) 7822{ 7823 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dm); 7824 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd); 7825 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Dn); 7826} 7827 7828/* VFPv3 instructions. */ 7829static void 7830do_vfp_sp_const (void) 7831{ 7832 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); 7833 inst.instruction |= (inst.operands[1].imm & 0xf0) << 12; 7834 inst.instruction |= (inst.operands[1].imm & 0x0f); 7835} 7836 7837static void 7838do_vfp_dp_const (void) 7839{ 7840 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); 7841 inst.instruction |= (inst.operands[1].imm & 0xf0) << 12; 7842 inst.instruction |= (inst.operands[1].imm & 0x0f); 7843} 7844 7845static void 7846vfp_conv (int srcsize) 7847{ 7848 unsigned immbits = srcsize - inst.operands[1].imm; 7849 inst.instruction |= (immbits & 1) << 5; 7850 inst.instruction |= (immbits >> 1); 7851} 7852 7853static void 7854do_vfp_sp_conv_16 (void) 7855{ 7856 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); 7857 vfp_conv (16); 7858} 7859 7860static void 7861do_vfp_dp_conv_16 (void) 7862{ 7863 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); 7864 vfp_conv (16); 7865} 7866 7867static void 7868do_vfp_sp_conv_32 (void) 7869{ 7870 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); 7871 vfp_conv (32); 7872} 7873 7874static void 7875do_vfp_dp_conv_32 (void) 7876{ 7877 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); 7878 vfp_conv (32); 7879} 7880 7881 7882/* FPA instructions. Also in a logical order. */ 7883 7884static void 7885do_fpa_cmp (void) 7886{ 7887 inst.instruction |= inst.operands[0].reg << 16; 7888 inst.instruction |= inst.operands[1].reg; 7889} 7890 7891static void 7892do_fpa_ldmstm (void) 7893{ 7894 inst.instruction |= inst.operands[0].reg << 12; 7895 switch (inst.operands[1].imm) 7896 { 7897 case 1: inst.instruction |= CP_T_X; break; 7898 case 2: inst.instruction |= CP_T_Y; break; 7899 case 3: inst.instruction |= CP_T_Y | CP_T_X; break; 7900 case 4: break; 7901 default: abort (); 7902 } 7903 7904 if (inst.instruction & (PRE_INDEX | INDEX_UP)) 7905 { 7906 /* The instruction specified "ea" or "fd", so we can only accept 7907 [Rn]{!}. The instruction does not really support stacking or 7908 unstacking, so we have to emulate these by setting appropriate 7909 bits and offsets. */ 7910 constraint (inst.reloc.exp.X_op != O_constant 7911 || inst.reloc.exp.X_add_number != 0, 7912 _("this instruction does not support indexing")); 7913 7914 if ((inst.instruction & PRE_INDEX) || inst.operands[2].writeback) 7915 inst.reloc.exp.X_add_number = 12 * inst.operands[1].imm; 7916 7917 if (!(inst.instruction & INDEX_UP)) 7918 inst.reloc.exp.X_add_number = -inst.reloc.exp.X_add_number; 7919 7920 if (!(inst.instruction & PRE_INDEX) && inst.operands[2].writeback) 7921 { 7922 inst.operands[2].preind = 0; 7923 inst.operands[2].postind = 1; 7924 } 7925 } 7926 7927 encode_arm_cp_address (2, TRUE, TRUE, 0); 7928} 7929 7930 7931/* iWMMXt instructions: strictly in alphabetical order. */ 7932 7933static void 7934do_iwmmxt_tandorc (void) 7935{ 7936 constraint (inst.operands[0].reg != REG_PC, _("only r15 allowed here")); 7937} 7938 7939static void 7940do_iwmmxt_textrc (void) 7941{ 7942 inst.instruction |= inst.operands[0].reg << 12; 7943 inst.instruction |= inst.operands[1].imm; 7944} 7945 7946static void 7947do_iwmmxt_textrm (void) 7948{ 7949 inst.instruction |= inst.operands[0].reg << 12; 7950 inst.instruction |= inst.operands[1].reg << 16; 7951 inst.instruction |= inst.operands[2].imm; 7952} 7953 7954static void 7955do_iwmmxt_tinsr (void) 7956{ 7957 inst.instruction |= inst.operands[0].reg << 16; 7958 inst.instruction |= inst.operands[1].reg << 12; 7959 inst.instruction |= inst.operands[2].imm; 7960} 7961 7962static void 7963do_iwmmxt_tmia (void) 7964{ 7965 inst.instruction |= inst.operands[0].reg << 5; 7966 inst.instruction |= inst.operands[1].reg; 7967 inst.instruction |= inst.operands[2].reg << 12; 7968} 7969 7970static void 7971do_iwmmxt_waligni (void) 7972{ 7973 inst.instruction |= inst.operands[0].reg << 12; 7974 inst.instruction |= inst.operands[1].reg << 16; 7975 inst.instruction |= inst.operands[2].reg; 7976 inst.instruction |= inst.operands[3].imm << 20; 7977} 7978 7979static void 7980do_iwmmxt_wmerge (void) 7981{ 7982 inst.instruction |= inst.operands[0].reg << 12; 7983 inst.instruction |= inst.operands[1].reg << 16; 7984 inst.instruction |= inst.operands[2].reg; 7985 inst.instruction |= inst.operands[3].imm << 21; 7986} 7987 7988static void 7989do_iwmmxt_wmov (void) 7990{ 7991 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */ 7992 inst.instruction |= inst.operands[0].reg << 12; 7993 inst.instruction |= inst.operands[1].reg << 16; 7994 inst.instruction |= inst.operands[1].reg; 7995} 7996 7997static void 7998do_iwmmxt_wldstbh (void) 7999{ 8000 int reloc; 8001 inst.instruction |= inst.operands[0].reg << 12; 8002 if (thumb_mode) 8003 reloc = BFD_RELOC_ARM_T32_CP_OFF_IMM_S2; 8004 else 8005 reloc = BFD_RELOC_ARM_CP_OFF_IMM_S2; 8006 encode_arm_cp_address (1, TRUE, FALSE, reloc); 8007} 8008 8009static void 8010do_iwmmxt_wldstw (void) 8011{ 8012 /* RIWR_RIWC clears .isreg for a control register. */ 8013 if (!inst.operands[0].isreg) 8014 { 8015 constraint (inst.cond != COND_ALWAYS, BAD_COND); 8016 inst.instruction |= 0xf0000000; 8017 } 8018 8019 inst.instruction |= inst.operands[0].reg << 12; 8020 encode_arm_cp_address (1, TRUE, TRUE, 0); 8021} 8022 8023static void 8024do_iwmmxt_wldstd (void) 8025{ 8026 inst.instruction |= inst.operands[0].reg << 12; 8027 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2) 8028 && inst.operands[1].immisreg) 8029 { 8030 inst.instruction &= ~0x1a000ff; 8031 inst.instruction |= (0xf << 28); 8032 if (inst.operands[1].preind) 8033 inst.instruction |= PRE_INDEX; 8034 if (!inst.operands[1].negative) 8035 inst.instruction |= INDEX_UP; 8036 if (inst.operands[1].writeback) 8037 inst.instruction |= WRITE_BACK; 8038 inst.instruction |= inst.operands[1].reg << 16; 8039 inst.instruction |= inst.reloc.exp.X_add_number << 4; 8040 inst.instruction |= inst.operands[1].imm; 8041 } 8042 else 8043 encode_arm_cp_address (1, TRUE, FALSE, 0); 8044} 8045 8046static void 8047do_iwmmxt_wshufh (void) 8048{ 8049 inst.instruction |= inst.operands[0].reg << 12; 8050 inst.instruction |= inst.operands[1].reg << 16; 8051 inst.instruction |= ((inst.operands[2].imm & 0xf0) << 16); 8052 inst.instruction |= (inst.operands[2].imm & 0x0f); 8053} 8054 8055static void 8056do_iwmmxt_wzero (void) 8057{ 8058 /* WZERO reg is an alias for WANDN reg, reg, reg. */ 8059 inst.instruction |= inst.operands[0].reg; 8060 inst.instruction |= inst.operands[0].reg << 12; 8061 inst.instruction |= inst.operands[0].reg << 16; 8062} 8063 8064static void 8065do_iwmmxt_wrwrwr_or_imm5 (void) 8066{ 8067 if (inst.operands[2].isreg) 8068 do_rd_rn_rm (); 8069 else { 8070 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2), 8071 _("immediate operand requires iWMMXt2")); 8072 do_rd_rn (); 8073 if (inst.operands[2].imm == 0) 8074 { 8075 switch ((inst.instruction >> 20) & 0xf) 8076 { 8077 case 4: 8078 case 5: 8079 case 6: 8080 case 7: 8081 /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */ 8082 inst.operands[2].imm = 16; 8083 inst.instruction = (inst.instruction & 0xff0fffff) | (0x7 << 20); 8084 break; 8085 case 8: 8086 case 9: 8087 case 10: 8088 case 11: 8089 /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */ 8090 inst.operands[2].imm = 32; 8091 inst.instruction = (inst.instruction & 0xff0fffff) | (0xb << 20); 8092 break; 8093 case 12: 8094 case 13: 8095 case 14: 8096 case 15: 8097 { 8098 /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */ 8099 unsigned long wrn; 8100 wrn = (inst.instruction >> 16) & 0xf; 8101 inst.instruction &= 0xff0fff0f; 8102 inst.instruction |= wrn; 8103 /* Bail out here; the instruction is now assembled. */ 8104 return; 8105 } 8106 } 8107 } 8108 /* Map 32 -> 0, etc. */ 8109 inst.operands[2].imm &= 0x1f; 8110 inst.instruction |= (0xf << 28) | ((inst.operands[2].imm & 0x10) << 4) | (inst.operands[2].imm & 0xf); 8111 } 8112} 8113 8114/* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register 8115 operations first, then control, shift, and load/store. */ 8116 8117/* Insns like "foo X,Y,Z". */ 8118 8119static void 8120do_mav_triple (void) 8121{ 8122 inst.instruction |= inst.operands[0].reg << 16; 8123 inst.instruction |= inst.operands[1].reg; 8124 inst.instruction |= inst.operands[2].reg << 12; 8125} 8126 8127/* Insns like "foo W,X,Y,Z". 8128 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */ 8129 8130static void 8131do_mav_quad (void) 8132{ 8133 inst.instruction |= inst.operands[0].reg << 5; 8134 inst.instruction |= inst.operands[1].reg << 12; 8135 inst.instruction |= inst.operands[2].reg << 16; 8136 inst.instruction |= inst.operands[3].reg; 8137} 8138 8139/* cfmvsc32<cond> DSPSC,MVDX[15:0]. */ 8140static void 8141do_mav_dspsc (void) 8142{ 8143 inst.instruction |= inst.operands[1].reg << 12; 8144} 8145 8146/* Maverick shift immediate instructions. 8147 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0]. 8148 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */ 8149 8150static void 8151do_mav_shift (void) 8152{ 8153 int imm = inst.operands[2].imm; 8154 8155 inst.instruction |= inst.operands[0].reg << 12; 8156 inst.instruction |= inst.operands[1].reg << 16; 8157 8158 /* Bits 0-3 of the insn should have bits 0-3 of the immediate. 8159 Bits 5-7 of the insn should have bits 4-6 of the immediate. 8160 Bit 4 should be 0. */ 8161 imm = (imm & 0xf) | ((imm & 0x70) << 1); 8162 8163 inst.instruction |= imm; 8164} 8165 8166/* XScale instructions. Also sorted arithmetic before move. */ 8167 8168/* Xscale multiply-accumulate (argument parse) 8169 MIAcc acc0,Rm,Rs 8170 MIAPHcc acc0,Rm,Rs 8171 MIAxycc acc0,Rm,Rs. */ 8172 8173static void 8174do_xsc_mia (void) 8175{ 8176 inst.instruction |= inst.operands[1].reg; 8177 inst.instruction |= inst.operands[2].reg << 12; 8178} 8179 8180/* Xscale move-accumulator-register (argument parse) 8181 8182 MARcc acc0,RdLo,RdHi. */ 8183 8184static void 8185do_xsc_mar (void) 8186{ 8187 inst.instruction |= inst.operands[1].reg << 12; 8188 inst.instruction |= inst.operands[2].reg << 16; 8189} 8190 8191/* Xscale move-register-accumulator (argument parse) 8192 8193 MRAcc RdLo,RdHi,acc0. */ 8194 8195static void 8196do_xsc_mra (void) 8197{ 8198 constraint (inst.operands[0].reg == inst.operands[1].reg, BAD_OVERLAP); 8199 inst.instruction |= inst.operands[0].reg << 12; 8200 inst.instruction |= inst.operands[1].reg << 16; 8201} 8202 8203/* Encoding functions relevant only to Thumb. */ 8204 8205/* inst.operands[i] is a shifted-register operand; encode 8206 it into inst.instruction in the format used by Thumb32. */ 8207 8208static void 8209encode_thumb32_shifted_operand (int i) 8210{ 8211 unsigned int value = inst.reloc.exp.X_add_number; 8212 unsigned int shift = inst.operands[i].shift_kind; 8213 8214 constraint (inst.operands[i].immisreg, 8215 _("shift by register not allowed in thumb mode")); 8216 inst.instruction |= inst.operands[i].reg; 8217 if (shift == SHIFT_RRX) 8218 inst.instruction |= SHIFT_ROR << 4; 8219 else 8220 { 8221 constraint (inst.reloc.exp.X_op != O_constant, 8222 _("expression too complex")); 8223 8224 constraint (value > 32 8225 || (value == 32 && (shift == SHIFT_LSL 8226 || shift == SHIFT_ROR)), 8227 _("shift expression is too large")); 8228 8229 if (value == 0) 8230 shift = SHIFT_LSL; 8231 else if (value == 32) 8232 value = 0; 8233 8234 inst.instruction |= shift << 4; 8235 inst.instruction |= (value & 0x1c) << 10; 8236 inst.instruction |= (value & 0x03) << 6; 8237 } 8238} 8239 8240 8241/* inst.operands[i] was set up by parse_address. Encode it into a 8242 Thumb32 format load or store instruction. Reject forms that cannot 8243 be used with such instructions. If is_t is true, reject forms that 8244 cannot be used with a T instruction; if is_d is true, reject forms 8245 that cannot be used with a D instruction. */ 8246 8247static void 8248encode_thumb32_addr_mode (int i, bfd_boolean is_t, bfd_boolean is_d) 8249{ 8250 bfd_boolean is_pc = (inst.operands[i].reg == REG_PC); 8251 8252 constraint (!inst.operands[i].isreg, 8253 _("Instruction does not support =N addresses")); 8254 8255 inst.instruction |= inst.operands[i].reg << 16; 8256 if (inst.operands[i].immisreg) 8257 { 8258 constraint (is_pc, _("cannot use register index with PC-relative addressing")); 8259 constraint (is_t || is_d, _("cannot use register index with this instruction")); 8260 constraint (inst.operands[i].negative, 8261 _("Thumb does not support negative register indexing")); 8262 constraint (inst.operands[i].postind, 8263 _("Thumb does not support register post-indexing")); 8264 constraint (inst.operands[i].writeback, 8265 _("Thumb does not support register indexing with writeback")); 8266 constraint (inst.operands[i].shifted && inst.operands[i].shift_kind != SHIFT_LSL, 8267 _("Thumb supports only LSL in shifted register indexing")); 8268 8269 inst.instruction |= inst.operands[i].imm; 8270 if (inst.operands[i].shifted) 8271 { 8272 constraint (inst.reloc.exp.X_op != O_constant, 8273 _("expression too complex")); 8274 constraint (inst.reloc.exp.X_add_number < 0 8275 || inst.reloc.exp.X_add_number > 3, 8276 _("shift out of range")); 8277 inst.instruction |= inst.reloc.exp.X_add_number << 4; 8278 } 8279 inst.reloc.type = BFD_RELOC_UNUSED; 8280 } 8281 else if (inst.operands[i].preind) 8282 { 8283 constraint (is_pc && inst.operands[i].writeback, 8284 _("cannot use writeback with PC-relative addressing")); 8285 constraint (is_t && inst.operands[i].writeback, 8286 _("cannot use writeback with this instruction")); 8287 8288 if (is_d) 8289 { 8290 inst.instruction |= 0x01000000; 8291 if (inst.operands[i].writeback) 8292 inst.instruction |= 0x00200000; 8293 } 8294 else 8295 { 8296 inst.instruction |= 0x00000c00; 8297 if (inst.operands[i].writeback) 8298 inst.instruction |= 0x00000100; 8299 } 8300 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_IMM; 8301 } 8302 else if (inst.operands[i].postind) 8303 { 8304 assert (inst.operands[i].writeback); 8305 constraint (is_pc, _("cannot use post-indexing with PC-relative addressing")); 8306 constraint (is_t, _("cannot use post-indexing with this instruction")); 8307 8308 if (is_d) 8309 inst.instruction |= 0x00200000; 8310 else 8311 inst.instruction |= 0x00000900; 8312 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_IMM; 8313 } 8314 else /* unindexed - only for coprocessor */ 8315 inst.error = _("instruction does not accept unindexed addressing"); 8316} 8317 8318/* Table of Thumb instructions which exist in both 16- and 32-bit 8319 encodings (the latter only in post-V6T2 cores). The index is the 8320 value used in the insns table below. When there is more than one 8321 possible 16-bit encoding for the instruction, this table always 8322 holds variant (1). 8323 Also contains several pseudo-instructions used during relaxation. */ 8324#define T16_32_TAB \ 8325 X(adc, 4140, eb400000), \ 8326 X(adcs, 4140, eb500000), \ 8327 X(add, 1c00, eb000000), \ 8328 X(adds, 1c00, eb100000), \ 8329 X(addi, 0000, f1000000), \ 8330 X(addis, 0000, f1100000), \ 8331 X(add_pc,000f, f20f0000), \ 8332 X(add_sp,000d, f10d0000), \ 8333 X(adr, 000f, f20f0000), \ 8334 X(and, 4000, ea000000), \ 8335 X(ands, 4000, ea100000), \ 8336 X(asr, 1000, fa40f000), \ 8337 X(asrs, 1000, fa50f000), \ 8338 X(b, e000, f000b000), \ 8339 X(bcond, d000, f0008000), \ 8340 X(bic, 4380, ea200000), \ 8341 X(bics, 4380, ea300000), \ 8342 X(cmn, 42c0, eb100f00), \ 8343 X(cmp, 2800, ebb00f00), \ 8344 X(cpsie, b660, f3af8400), \ 8345 X(cpsid, b670, f3af8600), \ 8346 X(cpy, 4600, ea4f0000), \ 8347 X(dec_sp,80dd, f1ad0d00), \ 8348 X(eor, 4040, ea800000), \ 8349 X(eors, 4040, ea900000), \ 8350 X(inc_sp,00dd, f10d0d00), \ 8351 X(ldmia, c800, e8900000), \ 8352 X(ldr, 6800, f8500000), \ 8353 X(ldrb, 7800, f8100000), \ 8354 X(ldrh, 8800, f8300000), \ 8355 X(ldrsb, 5600, f9100000), \ 8356 X(ldrsh, 5e00, f9300000), \ 8357 X(ldr_pc,4800, f85f0000), \ 8358 X(ldr_pc2,4800, f85f0000), \ 8359 X(ldr_sp,9800, f85d0000), \ 8360 X(lsl, 0000, fa00f000), \ 8361 X(lsls, 0000, fa10f000), \ 8362 X(lsr, 0800, fa20f000), \ 8363 X(lsrs, 0800, fa30f000), \ 8364 X(mov, 2000, ea4f0000), \ 8365 X(movs, 2000, ea5f0000), \ 8366 X(mul, 4340, fb00f000), \ 8367 X(muls, 4340, ffffffff), /* no 32b muls */ \ 8368 X(mvn, 43c0, ea6f0000), \ 8369 X(mvns, 43c0, ea7f0000), \ 8370 X(neg, 4240, f1c00000), /* rsb #0 */ \ 8371 X(negs, 4240, f1d00000), /* rsbs #0 */ \ 8372 X(orr, 4300, ea400000), \ 8373 X(orrs, 4300, ea500000), \ 8374 X(pop, bc00, e8bd0000), /* ldmia sp!,... */ \ 8375 X(push, b400, e92d0000), /* stmdb sp!,... */ \ 8376 X(rev, ba00, fa90f080), \ 8377 X(rev16, ba40, fa90f090), \ 8378 X(revsh, bac0, fa90f0b0), \ 8379 X(ror, 41c0, fa60f000), \ 8380 X(rors, 41c0, fa70f000), \ 8381 X(sbc, 4180, eb600000), \ 8382 X(sbcs, 4180, eb700000), \ 8383 X(stmia, c000, e8800000), \ 8384 X(str, 6000, f8400000), \ 8385 X(strb, 7000, f8000000), \ 8386 X(strh, 8000, f8200000), \ 8387 X(str_sp,9000, f84d0000), \ 8388 X(sub, 1e00, eba00000), \ 8389 X(subs, 1e00, ebb00000), \ 8390 X(subi, 8000, f1a00000), \ 8391 X(subis, 8000, f1b00000), \ 8392 X(sxtb, b240, fa4ff080), \ 8393 X(sxth, b200, fa0ff080), \ 8394 X(tst, 4200, ea100f00), \ 8395 X(uxtb, b2c0, fa5ff080), \ 8396 X(uxth, b280, fa1ff080), \ 8397 X(nop, bf00, f3af8000), \ 8398 X(yield, bf10, f3af8001), \ 8399 X(wfe, bf20, f3af8002), \ 8400 X(wfi, bf30, f3af8003), \ 8401 X(sev, bf40, f3af9004), /* typo, 8004? */ 8402 8403/* To catch errors in encoding functions, the codes are all offset by 8404 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined 8405 as 16-bit instructions. */ 8406#define X(a,b,c) T_MNEM_##a 8407enum t16_32_codes { T16_32_OFFSET = 0xF7FF, T16_32_TAB }; 8408#undef X 8409 8410#define X(a,b,c) 0x##b 8411static const unsigned short thumb_op16[] = { T16_32_TAB }; 8412#define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)]) 8413#undef X 8414 8415#define X(a,b,c) 0x##c 8416static const unsigned int thumb_op32[] = { T16_32_TAB }; 8417#define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)]) 8418#define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000) 8419#undef X 8420#undef T16_32_TAB 8421 8422/* Thumb instruction encoders, in alphabetical order. */ 8423 8424/* ADDW or SUBW. */ 8425static void 8426do_t_add_sub_w (void) 8427{ 8428 int Rd, Rn; 8429 8430 Rd = inst.operands[0].reg; 8431 Rn = inst.operands[1].reg; 8432 8433 constraint (Rd == 15, _("PC not allowed as destination")); 8434 inst.instruction |= (Rn << 16) | (Rd << 8); 8435 inst.reloc.type = BFD_RELOC_ARM_T32_IMM12; 8436} 8437 8438/* Parse an add or subtract instruction. We get here with inst.instruction 8439 equalling any of THUMB_OPCODE_add, adds, sub, or subs. */ 8440 8441static void 8442do_t_add_sub (void) 8443{ 8444 int Rd, Rs, Rn; 8445 8446 Rd = inst.operands[0].reg; 8447 Rs = (inst.operands[1].present 8448 ? inst.operands[1].reg /* Rd, Rs, foo */ 8449 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */ 8450 8451 if (unified_syntax) 8452 { 8453 bfd_boolean flags; 8454 bfd_boolean narrow; 8455 int opcode; 8456 8457 flags = (inst.instruction == T_MNEM_adds 8458 || inst.instruction == T_MNEM_subs); 8459 if (flags) 8460 narrow = (current_it_mask == 0); 8461 else 8462 narrow = (current_it_mask != 0); 8463 if (!inst.operands[2].isreg) 8464 { 8465 int add; 8466 8467 add = (inst.instruction == T_MNEM_add 8468 || inst.instruction == T_MNEM_adds); 8469 opcode = 0; 8470 if (inst.size_req != 4) 8471 { 8472 /* Attempt to use a narrow opcode, with relaxation if 8473 appropriate. */ 8474 if (Rd == REG_SP && Rs == REG_SP && !flags) 8475 opcode = add ? T_MNEM_inc_sp : T_MNEM_dec_sp; 8476 else if (Rd <= 7 && Rs == REG_SP && add && !flags) 8477 opcode = T_MNEM_add_sp; 8478 else if (Rd <= 7 && Rs == REG_PC && add && !flags) 8479 opcode = T_MNEM_add_pc; 8480 else if (Rd <= 7 && Rs <= 7 && narrow) 8481 { 8482 if (flags) 8483 opcode = add ? T_MNEM_addis : T_MNEM_subis; 8484 else 8485 opcode = add ? T_MNEM_addi : T_MNEM_subi; 8486 } 8487 if (opcode) 8488 { 8489 inst.instruction = THUMB_OP16(opcode); 8490 inst.instruction |= (Rd << 4) | Rs; 8491 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD; 8492 if (inst.size_req != 2) 8493 inst.relax = opcode; 8494 } 8495 else 8496 constraint (inst.size_req == 2, BAD_HIREG); 8497 } 8498 if (inst.size_req == 4 8499 || (inst.size_req != 2 && !opcode)) 8500 { 8501 if (Rd == REG_PC) 8502 { 8503 constraint (Rs != REG_LR || inst.instruction != T_MNEM_subs, 8504 _("only SUBS PC, LR, #const allowed")); 8505 constraint (inst.reloc.exp.X_op != O_constant, 8506 _("expression too complex")); 8507 constraint (inst.reloc.exp.X_add_number < 0 8508 || inst.reloc.exp.X_add_number > 0xff, 8509 _("immediate value out of range")); 8510 inst.instruction = T2_SUBS_PC_LR 8511 | inst.reloc.exp.X_add_number; 8512 inst.reloc.type = BFD_RELOC_UNUSED; 8513 return; 8514 } 8515 else if (Rs == REG_PC) 8516 { 8517 /* Always use addw/subw. */ 8518 inst.instruction = add ? 0xf20f0000 : 0xf2af0000; 8519 inst.reloc.type = BFD_RELOC_ARM_T32_IMM12; 8520 } 8521 else 8522 { 8523 inst.instruction = THUMB_OP32 (inst.instruction); 8524 inst.instruction = (inst.instruction & 0xe1ffffff) 8525 | 0x10000000; 8526 if (flags) 8527 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; 8528 else 8529 inst.reloc.type = BFD_RELOC_ARM_T32_ADD_IMM; 8530 } 8531 inst.instruction |= Rd << 8; 8532 inst.instruction |= Rs << 16; 8533 } 8534 } 8535 else 8536 { 8537 Rn = inst.operands[2].reg; 8538 /* See if we can do this with a 16-bit instruction. */ 8539 if (!inst.operands[2].shifted && inst.size_req != 4) 8540 { 8541 if (Rd > 7 || Rs > 7 || Rn > 7) 8542 narrow = FALSE; 8543 8544 if (narrow) 8545 { 8546 inst.instruction = ((inst.instruction == T_MNEM_adds 8547 || inst.instruction == T_MNEM_add) 8548 ? T_OPCODE_ADD_R3 8549 : T_OPCODE_SUB_R3); 8550 inst.instruction |= Rd | (Rs << 3) | (Rn << 6); 8551 return; 8552 } 8553 8554 if (inst.instruction == T_MNEM_add) 8555 { 8556 if (Rd == Rs) 8557 { 8558 inst.instruction = T_OPCODE_ADD_HI; 8559 inst.instruction |= (Rd & 8) << 4; 8560 inst.instruction |= (Rd & 7); 8561 inst.instruction |= Rn << 3; 8562 return; 8563 } 8564 /* ... because addition is commutative! */ 8565 else if (Rd == Rn) 8566 { 8567 inst.instruction = T_OPCODE_ADD_HI; 8568 inst.instruction |= (Rd & 8) << 4; 8569 inst.instruction |= (Rd & 7); 8570 inst.instruction |= Rs << 3; 8571 return; 8572 } 8573 } 8574 } 8575 /* If we get here, it can't be done in 16 bits. */ 8576 constraint (inst.operands[2].shifted && inst.operands[2].immisreg, 8577 _("shift must be constant")); 8578 inst.instruction = THUMB_OP32 (inst.instruction); 8579 inst.instruction |= Rd << 8; 8580 inst.instruction |= Rs << 16; 8581 encode_thumb32_shifted_operand (2); 8582 } 8583 } 8584 else 8585 { 8586 constraint (inst.instruction == T_MNEM_adds 8587 || inst.instruction == T_MNEM_subs, 8588 BAD_THUMB32); 8589 8590 if (!inst.operands[2].isreg) /* Rd, Rs, #imm */ 8591 { 8592 constraint ((Rd > 7 && (Rd != REG_SP || Rs != REG_SP)) 8593 || (Rs > 7 && Rs != REG_SP && Rs != REG_PC), 8594 BAD_HIREG); 8595 8596 inst.instruction = (inst.instruction == T_MNEM_add 8597 ? 0x0000 : 0x8000); 8598 inst.instruction |= (Rd << 4) | Rs; 8599 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD; 8600 return; 8601 } 8602 8603 Rn = inst.operands[2].reg; 8604 constraint (inst.operands[2].shifted, _("unshifted register required")); 8605 8606 /* We now have Rd, Rs, and Rn set to registers. */ 8607 if (Rd > 7 || Rs > 7 || Rn > 7) 8608 { 8609 /* Can't do this for SUB. */ 8610 constraint (inst.instruction == T_MNEM_sub, BAD_HIREG); 8611 inst.instruction = T_OPCODE_ADD_HI; 8612 inst.instruction |= (Rd & 8) << 4; 8613 inst.instruction |= (Rd & 7); 8614 if (Rs == Rd) 8615 inst.instruction |= Rn << 3; 8616 else if (Rn == Rd) 8617 inst.instruction |= Rs << 3; 8618 else 8619 constraint (1, _("dest must overlap one source register")); 8620 } 8621 else 8622 { 8623 inst.instruction = (inst.instruction == T_MNEM_add 8624 ? T_OPCODE_ADD_R3 : T_OPCODE_SUB_R3); 8625 inst.instruction |= Rd | (Rs << 3) | (Rn << 6); 8626 } 8627 } 8628} 8629 8630static void 8631do_t_adr (void) 8632{ 8633 if (unified_syntax && inst.size_req == 0 && inst.operands[0].reg <= 7) 8634 { 8635 /* Defer to section relaxation. */ 8636 inst.relax = inst.instruction; 8637 inst.instruction = THUMB_OP16 (inst.instruction); 8638 inst.instruction |= inst.operands[0].reg << 4; 8639 } 8640 else if (unified_syntax && inst.size_req != 2) 8641 { 8642 /* Generate a 32-bit opcode. */ 8643 inst.instruction = THUMB_OP32 (inst.instruction); 8644 inst.instruction |= inst.operands[0].reg << 8; 8645 inst.reloc.type = BFD_RELOC_ARM_T32_ADD_PC12; 8646 inst.reloc.pc_rel = 1; 8647 } 8648 else 8649 { 8650 /* Generate a 16-bit opcode. */ 8651 inst.instruction = THUMB_OP16 (inst.instruction); 8652 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD; 8653 inst.reloc.exp.X_add_number -= 4; /* PC relative adjust. */ 8654 inst.reloc.pc_rel = 1; 8655 8656 inst.instruction |= inst.operands[0].reg << 4; 8657 } 8658} 8659 8660/* Arithmetic instructions for which there is just one 16-bit 8661 instruction encoding, and it allows only two low registers. 8662 For maximal compatibility with ARM syntax, we allow three register 8663 operands even when Thumb-32 instructions are not available, as long 8664 as the first two are identical. For instance, both "sbc r0,r1" and 8665 "sbc r0,r0,r1" are allowed. */ 8666static void 8667do_t_arit3 (void) 8668{ 8669 int Rd, Rs, Rn; 8670 8671 Rd = inst.operands[0].reg; 8672 Rs = (inst.operands[1].present 8673 ? inst.operands[1].reg /* Rd, Rs, foo */ 8674 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */ 8675 Rn = inst.operands[2].reg; 8676 8677 if (unified_syntax) 8678 { 8679 if (!inst.operands[2].isreg) 8680 { 8681 /* For an immediate, we always generate a 32-bit opcode; 8682 section relaxation will shrink it later if possible. */ 8683 inst.instruction = THUMB_OP32 (inst.instruction); 8684 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000; 8685 inst.instruction |= Rd << 8; 8686 inst.instruction |= Rs << 16; 8687 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; 8688 } 8689 else 8690 { 8691 bfd_boolean narrow; 8692 8693 /* See if we can do this with a 16-bit instruction. */ 8694 if (THUMB_SETS_FLAGS (inst.instruction)) 8695 narrow = current_it_mask == 0; 8696 else 8697 narrow = current_it_mask != 0; 8698 8699 if (Rd > 7 || Rn > 7 || Rs > 7) 8700 narrow = FALSE; 8701 if (inst.operands[2].shifted) 8702 narrow = FALSE; 8703 if (inst.size_req == 4) 8704 narrow = FALSE; 8705 8706 if (narrow 8707 && Rd == Rs) 8708 { 8709 inst.instruction = THUMB_OP16 (inst.instruction); 8710 inst.instruction |= Rd; 8711 inst.instruction |= Rn << 3; 8712 return; 8713 } 8714 8715 /* If we get here, it can't be done in 16 bits. */ 8716 constraint (inst.operands[2].shifted 8717 && inst.operands[2].immisreg, 8718 _("shift must be constant")); 8719 inst.instruction = THUMB_OP32 (inst.instruction); 8720 inst.instruction |= Rd << 8; 8721 inst.instruction |= Rs << 16; 8722 encode_thumb32_shifted_operand (2); 8723 } 8724 } 8725 else 8726 { 8727 /* On its face this is a lie - the instruction does set the 8728 flags. However, the only supported mnemonic in this mode 8729 says it doesn't. */ 8730 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32); 8731 8732 constraint (!inst.operands[2].isreg || inst.operands[2].shifted, 8733 _("unshifted register required")); 8734 constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG); 8735 constraint (Rd != Rs, 8736 _("dest and source1 must be the same register")); 8737 8738 inst.instruction = THUMB_OP16 (inst.instruction); 8739 inst.instruction |= Rd; 8740 inst.instruction |= Rn << 3; 8741 } 8742} 8743 8744/* Similarly, but for instructions where the arithmetic operation is 8745 commutative, so we can allow either of them to be different from 8746 the destination operand in a 16-bit instruction. For instance, all 8747 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are 8748 accepted. */ 8749static void 8750do_t_arit3c (void) 8751{ 8752 int Rd, Rs, Rn; 8753 8754 Rd = inst.operands[0].reg; 8755 Rs = (inst.operands[1].present 8756 ? inst.operands[1].reg /* Rd, Rs, foo */ 8757 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */ 8758 Rn = inst.operands[2].reg; 8759 8760 if (unified_syntax) 8761 { 8762 if (!inst.operands[2].isreg) 8763 { 8764 /* For an immediate, we always generate a 32-bit opcode; 8765 section relaxation will shrink it later if possible. */ 8766 inst.instruction = THUMB_OP32 (inst.instruction); 8767 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000; 8768 inst.instruction |= Rd << 8; 8769 inst.instruction |= Rs << 16; 8770 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; 8771 } 8772 else 8773 { 8774 bfd_boolean narrow; 8775 8776 /* See if we can do this with a 16-bit instruction. */ 8777 if (THUMB_SETS_FLAGS (inst.instruction)) 8778 narrow = current_it_mask == 0; 8779 else 8780 narrow = current_it_mask != 0; 8781 8782 if (Rd > 7 || Rn > 7 || Rs > 7) 8783 narrow = FALSE; 8784 if (inst.operands[2].shifted) 8785 narrow = FALSE; 8786 if (inst.size_req == 4) 8787 narrow = FALSE; 8788 8789 if (narrow) 8790 { 8791 if (Rd == Rs) 8792 { 8793 inst.instruction = THUMB_OP16 (inst.instruction); 8794 inst.instruction |= Rd; 8795 inst.instruction |= Rn << 3; 8796 return; 8797 } 8798 if (Rd == Rn) 8799 { 8800 inst.instruction = THUMB_OP16 (inst.instruction); 8801 inst.instruction |= Rd; 8802 inst.instruction |= Rs << 3; 8803 return; 8804 } 8805 } 8806 8807 /* If we get here, it can't be done in 16 bits. */ 8808 constraint (inst.operands[2].shifted 8809 && inst.operands[2].immisreg, 8810 _("shift must be constant")); 8811 inst.instruction = THUMB_OP32 (inst.instruction); 8812 inst.instruction |= Rd << 8; 8813 inst.instruction |= Rs << 16; 8814 encode_thumb32_shifted_operand (2); 8815 } 8816 } 8817 else 8818 { 8819 /* On its face this is a lie - the instruction does set the 8820 flags. However, the only supported mnemonic in this mode 8821 says it doesn't. */ 8822 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32); 8823 8824 constraint (!inst.operands[2].isreg || inst.operands[2].shifted, 8825 _("unshifted register required")); 8826 constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG); 8827 8828 inst.instruction = THUMB_OP16 (inst.instruction); 8829 inst.instruction |= Rd; 8830 8831 if (Rd == Rs) 8832 inst.instruction |= Rn << 3; 8833 else if (Rd == Rn) 8834 inst.instruction |= Rs << 3; 8835 else 8836 constraint (1, _("dest must overlap one source register")); 8837 } 8838} 8839 8840static void 8841do_t_barrier (void) 8842{ 8843 if (inst.operands[0].present) 8844 { 8845 constraint ((inst.instruction & 0xf0) != 0x40 8846 && inst.operands[0].imm != 0xf, 8847 "bad barrier type"); 8848 inst.instruction |= inst.operands[0].imm; 8849 } 8850 else 8851 inst.instruction |= 0xf; 8852} 8853 8854static void 8855do_t_bfc (void) 8856{ 8857 unsigned int msb = inst.operands[1].imm + inst.operands[2].imm; 8858 constraint (msb > 32, _("bit-field extends past end of register")); 8859 /* The instruction encoding stores the LSB and MSB, 8860 not the LSB and width. */ 8861 inst.instruction |= inst.operands[0].reg << 8; 8862 inst.instruction |= (inst.operands[1].imm & 0x1c) << 10; 8863 inst.instruction |= (inst.operands[1].imm & 0x03) << 6; 8864 inst.instruction |= msb - 1; 8865} 8866 8867static void 8868do_t_bfi (void) 8869{ 8870 unsigned int msb; 8871 8872 /* #0 in second position is alternative syntax for bfc, which is 8873 the same instruction but with REG_PC in the Rm field. */ 8874 if (!inst.operands[1].isreg) 8875 inst.operands[1].reg = REG_PC; 8876 8877 msb = inst.operands[2].imm + inst.operands[3].imm; 8878 constraint (msb > 32, _("bit-field extends past end of register")); 8879 /* The instruction encoding stores the LSB and MSB, 8880 not the LSB and width. */ 8881 inst.instruction |= inst.operands[0].reg << 8; 8882 inst.instruction |= inst.operands[1].reg << 16; 8883 inst.instruction |= (inst.operands[2].imm & 0x1c) << 10; 8884 inst.instruction |= (inst.operands[2].imm & 0x03) << 6; 8885 inst.instruction |= msb - 1; 8886} 8887 8888static void 8889do_t_bfx (void) 8890{ 8891 constraint (inst.operands[2].imm + inst.operands[3].imm > 32, 8892 _("bit-field extends past end of register")); 8893 inst.instruction |= inst.operands[0].reg << 8; 8894 inst.instruction |= inst.operands[1].reg << 16; 8895 inst.instruction |= (inst.operands[2].imm & 0x1c) << 10; 8896 inst.instruction |= (inst.operands[2].imm & 0x03) << 6; 8897 inst.instruction |= inst.operands[3].imm - 1; 8898} 8899 8900/* ARM V5 Thumb BLX (argument parse) 8901 BLX <target_addr> which is BLX(1) 8902 BLX <Rm> which is BLX(2) 8903 Unfortunately, there are two different opcodes for this mnemonic. 8904 So, the insns[].value is not used, and the code here zaps values 8905 into inst.instruction. 8906 8907 ??? How to take advantage of the additional two bits of displacement 8908 available in Thumb32 mode? Need new relocation? */ 8909 8910static void 8911do_t_blx (void) 8912{ 8913 constraint (current_it_mask && current_it_mask != 0x10, BAD_BRANCH); 8914 if (inst.operands[0].isreg) 8915 /* We have a register, so this is BLX(2). */ 8916 inst.instruction |= inst.operands[0].reg << 3; 8917 else 8918 { 8919 /* No register. This must be BLX(1). */ 8920 inst.instruction = 0xf000e800; 8921#ifdef OBJ_ELF 8922 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4) 8923 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH23; 8924 else 8925#endif 8926 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BLX; 8927 inst.reloc.pc_rel = 1; 8928 } 8929} 8930 8931static void 8932do_t_branch (void) 8933{ 8934 int opcode; 8935 int cond; 8936 8937 if (current_it_mask) 8938 { 8939 /* Conditional branches inside IT blocks are encoded as unconditional 8940 branches. */ 8941 cond = COND_ALWAYS; 8942 /* A branch must be the last instruction in an IT block. */ 8943 constraint (current_it_mask != 0x10, BAD_BRANCH); 8944 } 8945 else 8946 cond = inst.cond; 8947 8948 if (cond != COND_ALWAYS) 8949 opcode = T_MNEM_bcond; 8950 else 8951 opcode = inst.instruction; 8952 8953 if (unified_syntax && inst.size_req == 4) 8954 { 8955 inst.instruction = THUMB_OP32(opcode); 8956 if (cond == COND_ALWAYS) 8957 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH25; 8958 else 8959 { 8960 assert (cond != 0xF); 8961 inst.instruction |= cond << 22; 8962 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH20; 8963 } 8964 } 8965 else 8966 { 8967 inst.instruction = THUMB_OP16(opcode); 8968 if (cond == COND_ALWAYS) 8969 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH12; 8970 else 8971 { 8972 inst.instruction |= cond << 8; 8973 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH9; 8974 } 8975 /* Allow section relaxation. */ 8976 if (unified_syntax && inst.size_req != 2) 8977 inst.relax = opcode; 8978 } 8979 8980 inst.reloc.pc_rel = 1; 8981} 8982 8983static void 8984do_t_bkpt (void) 8985{ 8986 constraint (inst.cond != COND_ALWAYS, 8987 _("instruction is always unconditional")); 8988 if (inst.operands[0].present) 8989 { 8990 constraint (inst.operands[0].imm > 255, 8991 _("immediate value out of range")); 8992 inst.instruction |= inst.operands[0].imm; 8993 } 8994} 8995 8996static void 8997do_t_branch23 (void) 8998{ 8999 constraint (current_it_mask && current_it_mask != 0x10, BAD_BRANCH); 9000 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH23; 9001 inst.reloc.pc_rel = 1; 9002 9003 /* If the destination of the branch is a defined symbol which does not have 9004 the THUMB_FUNC attribute, then we must be calling a function which has 9005 the (interfacearm) attribute. We look for the Thumb entry point to that 9006 function and change the branch to refer to that function instead. */ 9007 if ( inst.reloc.exp.X_op == O_symbol 9008 && inst.reloc.exp.X_add_symbol != NULL 9009 && S_IS_DEFINED (inst.reloc.exp.X_add_symbol) 9010 && ! THUMB_IS_FUNC (inst.reloc.exp.X_add_symbol)) 9011 inst.reloc.exp.X_add_symbol = 9012 find_real_start (inst.reloc.exp.X_add_symbol); 9013} 9014 9015static void 9016do_t_bx (void) 9017{ 9018 constraint (current_it_mask && current_it_mask != 0x10, BAD_BRANCH); 9019 inst.instruction |= inst.operands[0].reg << 3; 9020 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc 9021 should cause the alignment to be checked once it is known. This is 9022 because BX PC only works if the instruction is word aligned. */ 9023} 9024 9025static void 9026do_t_bxj (void) 9027{ 9028 constraint (current_it_mask && current_it_mask != 0x10, BAD_BRANCH); 9029 if (inst.operands[0].reg == REG_PC) 9030 as_tsktsk (_("use of r15 in bxj is not really useful")); 9031 9032 inst.instruction |= inst.operands[0].reg << 16; 9033} 9034 9035static void 9036do_t_clz (void) 9037{ 9038 inst.instruction |= inst.operands[0].reg << 8; 9039 inst.instruction |= inst.operands[1].reg << 16; 9040 inst.instruction |= inst.operands[1].reg; 9041} 9042 9043static void 9044do_t_cps (void) 9045{ 9046 constraint (current_it_mask, BAD_NOT_IT); 9047 inst.instruction |= inst.operands[0].imm; 9048} 9049 9050static void 9051do_t_cpsi (void) 9052{ 9053 constraint (current_it_mask, BAD_NOT_IT); 9054 if (unified_syntax 9055 && (inst.operands[1].present || inst.size_req == 4) 9056 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6_notm)) 9057 { 9058 unsigned int imod = (inst.instruction & 0x0030) >> 4; 9059 inst.instruction = 0xf3af8000; 9060 inst.instruction |= imod << 9; 9061 inst.instruction |= inst.operands[0].imm << 5; 9062 if (inst.operands[1].present) 9063 inst.instruction |= 0x100 | inst.operands[1].imm; 9064 } 9065 else 9066 { 9067 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1) 9068 && (inst.operands[0].imm & 4), 9069 _("selected processor does not support 'A' form " 9070 "of this instruction")); 9071 constraint (inst.operands[1].present || inst.size_req == 4, 9072 _("Thumb does not support the 2-argument " 9073 "form of this instruction")); 9074 inst.instruction |= inst.operands[0].imm; 9075 } 9076} 9077 9078/* THUMB CPY instruction (argument parse). */ 9079 9080static void 9081do_t_cpy (void) 9082{ 9083 if (inst.size_req == 4) 9084 { 9085 inst.instruction = THUMB_OP32 (T_MNEM_mov); 9086 inst.instruction |= inst.operands[0].reg << 8; 9087 inst.instruction |= inst.operands[1].reg; 9088 } 9089 else 9090 { 9091 inst.instruction |= (inst.operands[0].reg & 0x8) << 4; 9092 inst.instruction |= (inst.operands[0].reg & 0x7); 9093 inst.instruction |= inst.operands[1].reg << 3; 9094 } 9095} 9096 9097static void 9098do_t_cbz (void) 9099{ 9100 constraint (current_it_mask, BAD_NOT_IT); 9101 constraint (inst.operands[0].reg > 7, BAD_HIREG); 9102 inst.instruction |= inst.operands[0].reg; 9103 inst.reloc.pc_rel = 1; 9104 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH7; 9105} 9106 9107static void 9108do_t_dbg (void) 9109{ 9110 inst.instruction |= inst.operands[0].imm; 9111} 9112 9113static void 9114do_t_div (void) 9115{ 9116 if (!inst.operands[1].present) 9117 inst.operands[1].reg = inst.operands[0].reg; 9118 inst.instruction |= inst.operands[0].reg << 8; 9119 inst.instruction |= inst.operands[1].reg << 16; 9120 inst.instruction |= inst.operands[2].reg; 9121} 9122 9123static void 9124do_t_hint (void) 9125{ 9126 if (unified_syntax && inst.size_req == 4) 9127 inst.instruction = THUMB_OP32 (inst.instruction); 9128 else 9129 inst.instruction = THUMB_OP16 (inst.instruction); 9130} 9131 9132static void 9133do_t_it (void) 9134{ 9135 unsigned int cond = inst.operands[0].imm; 9136 9137 constraint (current_it_mask, BAD_NOT_IT); 9138 current_it_mask = (inst.instruction & 0xf) | 0x10; 9139 current_cc = cond; 9140 9141 /* If the condition is a negative condition, invert the mask. */ 9142 if ((cond & 0x1) == 0x0) 9143 { 9144 unsigned int mask = inst.instruction & 0x000f; 9145 9146 if ((mask & 0x7) == 0) 9147 /* no conversion needed */; 9148 else if ((mask & 0x3) == 0) 9149 mask ^= 0x8; 9150 else if ((mask & 0x1) == 0) 9151 mask ^= 0xC; 9152 else 9153 mask ^= 0xE; 9154 9155 inst.instruction &= 0xfff0; 9156 inst.instruction |= mask; 9157 } 9158 9159 inst.instruction |= cond << 4; 9160} 9161 9162/* Helper function used for both push/pop and ldm/stm. */ 9163static void 9164encode_thumb2_ldmstm (int base, unsigned mask, bfd_boolean writeback) 9165{ 9166 bfd_boolean load; 9167 9168 load = (inst.instruction & (1 << 20)) != 0; 9169 9170 if (mask & (1 << 13)) 9171 inst.error = _("SP not allowed in register list"); 9172 if (load) 9173 { 9174 if (mask & (1 << 14) 9175 && mask & (1 << 15)) 9176 inst.error = _("LR and PC should not both be in register list"); 9177 9178 if ((mask & (1 << base)) != 0 9179 && writeback) 9180 as_warn (_("base register should not be in register list " 9181 "when written back")); 9182 } 9183 else 9184 { 9185 if (mask & (1 << 15)) 9186 inst.error = _("PC not allowed in register list"); 9187 9188 if (mask & (1 << base)) 9189 as_warn (_("value stored for r%d is UNPREDICTABLE"), base); 9190 } 9191 9192 if ((mask & (mask - 1)) == 0) 9193 { 9194 /* Single register transfers implemented as str/ldr. */ 9195 if (writeback) 9196 { 9197 if (inst.instruction & (1 << 23)) 9198 inst.instruction = 0x00000b04; /* ia! -> [base], #4 */ 9199 else 9200 inst.instruction = 0x00000d04; /* db! -> [base, #-4]! */ 9201 } 9202 else 9203 { 9204 if (inst.instruction & (1 << 23)) 9205 inst.instruction = 0x00800000; /* ia -> [base] */ 9206 else 9207 inst.instruction = 0x00000c04; /* db -> [base, #-4] */ 9208 } 9209 9210 inst.instruction |= 0xf8400000; 9211 if (load) 9212 inst.instruction |= 0x00100000; 9213 9214 mask = ffs(mask) - 1; 9215 mask <<= 12; 9216 } 9217 else if (writeback) 9218 inst.instruction |= WRITE_BACK; 9219 9220 inst.instruction |= mask; 9221 inst.instruction |= base << 16; 9222} 9223 9224static void 9225do_t_ldmstm (void) 9226{ 9227 /* This really doesn't seem worth it. */ 9228 constraint (inst.reloc.type != BFD_RELOC_UNUSED, 9229 _("expression too complex")); 9230 constraint (inst.operands[1].writeback, 9231 _("Thumb load/store multiple does not support {reglist}^")); 9232 9233 if (unified_syntax) 9234 { 9235 bfd_boolean narrow; 9236 unsigned mask; 9237 9238 narrow = FALSE; 9239 /* See if we can use a 16-bit instruction. */ 9240 if (inst.instruction < 0xffff /* not ldmdb/stmdb */ 9241 && inst.size_req != 4 9242 && !(inst.operands[1].imm & ~0xff)) 9243 { 9244 mask = 1 << inst.operands[0].reg; 9245 9246 if (inst.operands[0].reg <= 7 9247 && (inst.instruction == T_MNEM_stmia 9248 ? inst.operands[0].writeback 9249 : (inst.operands[0].writeback 9250 == !(inst.operands[1].imm & mask)))) 9251 { 9252 if (inst.instruction == T_MNEM_stmia 9253 && (inst.operands[1].imm & mask) 9254 && (inst.operands[1].imm & (mask - 1))) 9255 as_warn (_("value stored for r%d is UNPREDICTABLE"), 9256 inst.operands[0].reg); 9257 9258 inst.instruction = THUMB_OP16 (inst.instruction); 9259 inst.instruction |= inst.operands[0].reg << 8; 9260 inst.instruction |= inst.operands[1].imm; 9261 narrow = TRUE; 9262 } 9263 else if (inst.operands[0] .reg == REG_SP 9264 && inst.operands[0].writeback) 9265 { 9266 inst.instruction = THUMB_OP16 (inst.instruction == T_MNEM_stmia 9267 ? T_MNEM_push : T_MNEM_pop); 9268 inst.instruction |= inst.operands[1].imm; 9269 narrow = TRUE; 9270 } 9271 } 9272 9273 if (!narrow) 9274 { 9275 if (inst.instruction < 0xffff) 9276 inst.instruction = THUMB_OP32 (inst.instruction); 9277 9278 encode_thumb2_ldmstm(inst.operands[0].reg, inst.operands[1].imm, 9279 inst.operands[0].writeback); 9280 } 9281 } 9282 else 9283 { 9284 constraint (inst.operands[0].reg > 7 9285 || (inst.operands[1].imm & ~0xff), BAD_HIREG); 9286 constraint (inst.instruction != T_MNEM_ldmia 9287 && inst.instruction != T_MNEM_stmia, 9288 _("Thumb-2 instruction only valid in unified syntax")); 9289 if (inst.instruction == T_MNEM_stmia) 9290 { 9291 if (!inst.operands[0].writeback) 9292 as_warn (_("this instruction will write back the base register")); 9293 if ((inst.operands[1].imm & (1 << inst.operands[0].reg)) 9294 && (inst.operands[1].imm & ((1 << inst.operands[0].reg) - 1))) 9295 as_warn (_("value stored for r%d is UNPREDICTABLE"), 9296 inst.operands[0].reg); 9297 } 9298 else 9299 { 9300 if (!inst.operands[0].writeback 9301 && !(inst.operands[1].imm & (1 << inst.operands[0].reg))) 9302 as_warn (_("this instruction will write back the base register")); 9303 else if (inst.operands[0].writeback 9304 && (inst.operands[1].imm & (1 << inst.operands[0].reg))) 9305 as_warn (_("this instruction will not write back the base register")); 9306 } 9307 9308 inst.instruction = THUMB_OP16 (inst.instruction); 9309 inst.instruction |= inst.operands[0].reg << 8; 9310 inst.instruction |= inst.operands[1].imm; 9311 } 9312} 9313 9314static void 9315do_t_ldrex (void) 9316{ 9317 constraint (!inst.operands[1].isreg || !inst.operands[1].preind 9318 || inst.operands[1].postind || inst.operands[1].writeback 9319 || inst.operands[1].immisreg || inst.operands[1].shifted 9320 || inst.operands[1].negative, 9321 BAD_ADDR_MODE); 9322 9323 inst.instruction |= inst.operands[0].reg << 12; 9324 inst.instruction |= inst.operands[1].reg << 16; 9325 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_U8; 9326} 9327 9328static void 9329do_t_ldrexd (void) 9330{ 9331 if (!inst.operands[1].present) 9332 { 9333 constraint (inst.operands[0].reg == REG_LR, 9334 _("r14 not allowed as first register " 9335 "when second register is omitted")); 9336 inst.operands[1].reg = inst.operands[0].reg + 1; 9337 } 9338 constraint (inst.operands[0].reg == inst.operands[1].reg, 9339 BAD_OVERLAP); 9340 9341 inst.instruction |= inst.operands[0].reg << 12; 9342 inst.instruction |= inst.operands[1].reg << 8; 9343 inst.instruction |= inst.operands[2].reg << 16; 9344} 9345 9346static void 9347do_t_ldst (void) 9348{ 9349 unsigned long opcode; 9350 int Rn; 9351 9352 opcode = inst.instruction; 9353 if (unified_syntax) 9354 { 9355 if (!inst.operands[1].isreg) 9356 { 9357 if (opcode <= 0xffff) 9358 inst.instruction = THUMB_OP32 (opcode); 9359 if (move_or_literal_pool (0, /*thumb_p=*/TRUE, /*mode_3=*/FALSE)) 9360 return; 9361 } 9362 if (inst.operands[1].isreg 9363 && !inst.operands[1].writeback 9364 && !inst.operands[1].shifted && !inst.operands[1].postind 9365 && !inst.operands[1].negative && inst.operands[0].reg <= 7 9366 && opcode <= 0xffff 9367 && inst.size_req != 4) 9368 { 9369 /* Insn may have a 16-bit form. */ 9370 Rn = inst.operands[1].reg; 9371 if (inst.operands[1].immisreg) 9372 { 9373 inst.instruction = THUMB_OP16 (opcode); 9374 /* [Rn, Ri] */ 9375 if (Rn <= 7 && inst.operands[1].imm <= 7) 9376 goto op16; 9377 } 9378 else if ((Rn <= 7 && opcode != T_MNEM_ldrsh 9379 && opcode != T_MNEM_ldrsb) 9380 || ((Rn == REG_PC || Rn == REG_SP) && opcode == T_MNEM_ldr) 9381 || (Rn == REG_SP && opcode == T_MNEM_str)) 9382 { 9383 /* [Rn, #const] */ 9384 if (Rn > 7) 9385 { 9386 if (Rn == REG_PC) 9387 { 9388 if (inst.reloc.pc_rel) 9389 opcode = T_MNEM_ldr_pc2; 9390 else 9391 opcode = T_MNEM_ldr_pc; 9392 } 9393 else 9394 { 9395 if (opcode == T_MNEM_ldr) 9396 opcode = T_MNEM_ldr_sp; 9397 else 9398 opcode = T_MNEM_str_sp; 9399 } 9400 inst.instruction = inst.operands[0].reg << 8; 9401 } 9402 else 9403 { 9404 inst.instruction = inst.operands[0].reg; 9405 inst.instruction |= inst.operands[1].reg << 3; 9406 } 9407 inst.instruction |= THUMB_OP16 (opcode); 9408 if (inst.size_req == 2) 9409 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET; 9410 else 9411 inst.relax = opcode; 9412 return; 9413 } 9414 } 9415 /* Definitely a 32-bit variant. */ 9416 inst.instruction = THUMB_OP32 (opcode); 9417 inst.instruction |= inst.operands[0].reg << 12; 9418 encode_thumb32_addr_mode (1, /*is_t=*/FALSE, /*is_d=*/FALSE); 9419 return; 9420 } 9421 9422 constraint (inst.operands[0].reg > 7, BAD_HIREG); 9423 9424 if (inst.instruction == T_MNEM_ldrsh || inst.instruction == T_MNEM_ldrsb) 9425 { 9426 /* Only [Rn,Rm] is acceptable. */ 9427 constraint (inst.operands[1].reg > 7 || inst.operands[1].imm > 7, BAD_HIREG); 9428 constraint (!inst.operands[1].isreg || !inst.operands[1].immisreg 9429 || inst.operands[1].postind || inst.operands[1].shifted 9430 || inst.operands[1].negative, 9431 _("Thumb does not support this addressing mode")); 9432 inst.instruction = THUMB_OP16 (inst.instruction); 9433 goto op16; 9434 } 9435 9436 inst.instruction = THUMB_OP16 (inst.instruction); 9437 if (!inst.operands[1].isreg) 9438 if (move_or_literal_pool (0, /*thumb_p=*/TRUE, /*mode_3=*/FALSE)) 9439 return; 9440 9441 constraint (!inst.operands[1].preind 9442 || inst.operands[1].shifted 9443 || inst.operands[1].writeback, 9444 _("Thumb does not support this addressing mode")); 9445 if (inst.operands[1].reg == REG_PC || inst.operands[1].reg == REG_SP) 9446 { 9447 constraint (inst.instruction & 0x0600, 9448 _("byte or halfword not valid for base register")); 9449 constraint (inst.operands[1].reg == REG_PC 9450 && !(inst.instruction & THUMB_LOAD_BIT), 9451 _("r15 based store not allowed")); 9452 constraint (inst.operands[1].immisreg, 9453 _("invalid base register for register offset")); 9454 9455 if (inst.operands[1].reg == REG_PC) 9456 inst.instruction = T_OPCODE_LDR_PC; 9457 else if (inst.instruction & THUMB_LOAD_BIT) 9458 inst.instruction = T_OPCODE_LDR_SP; 9459 else 9460 inst.instruction = T_OPCODE_STR_SP; 9461 9462 inst.instruction |= inst.operands[0].reg << 8; 9463 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET; 9464 return; 9465 } 9466 9467 constraint (inst.operands[1].reg > 7, BAD_HIREG); 9468 if (!inst.operands[1].immisreg) 9469 { 9470 /* Immediate offset. */ 9471 inst.instruction |= inst.operands[0].reg; 9472 inst.instruction |= inst.operands[1].reg << 3; 9473 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET; 9474 return; 9475 } 9476 9477 /* Register offset. */ 9478 constraint (inst.operands[1].imm > 7, BAD_HIREG); 9479 constraint (inst.operands[1].negative, 9480 _("Thumb does not support this addressing mode")); 9481 9482 op16: 9483 switch (inst.instruction) 9484 { 9485 case T_OPCODE_STR_IW: inst.instruction = T_OPCODE_STR_RW; break; 9486 case T_OPCODE_STR_IH: inst.instruction = T_OPCODE_STR_RH; break; 9487 case T_OPCODE_STR_IB: inst.instruction = T_OPCODE_STR_RB; break; 9488 case T_OPCODE_LDR_IW: inst.instruction = T_OPCODE_LDR_RW; break; 9489 case T_OPCODE_LDR_IH: inst.instruction = T_OPCODE_LDR_RH; break; 9490 case T_OPCODE_LDR_IB: inst.instruction = T_OPCODE_LDR_RB; break; 9491 case 0x5600 /* ldrsb */: 9492 case 0x5e00 /* ldrsh */: break; 9493 default: abort (); 9494 } 9495 9496 inst.instruction |= inst.operands[0].reg; 9497 inst.instruction |= inst.operands[1].reg << 3; 9498 inst.instruction |= inst.operands[1].imm << 6; 9499} 9500 9501static void 9502do_t_ldstd (void) 9503{ 9504 if (!inst.operands[1].present) 9505 { 9506 inst.operands[1].reg = inst.operands[0].reg + 1; 9507 constraint (inst.operands[0].reg == REG_LR, 9508 _("r14 not allowed here")); 9509 } 9510 inst.instruction |= inst.operands[0].reg << 12; 9511 inst.instruction |= inst.operands[1].reg << 8; 9512 encode_thumb32_addr_mode (2, /*is_t=*/FALSE, /*is_d=*/TRUE); 9513 9514} 9515 9516static void 9517do_t_ldstt (void) 9518{ 9519 inst.instruction |= inst.operands[0].reg << 12; 9520 encode_thumb32_addr_mode (1, /*is_t=*/TRUE, /*is_d=*/FALSE); 9521} 9522 9523static void 9524do_t_mla (void) 9525{ 9526 inst.instruction |= inst.operands[0].reg << 8; 9527 inst.instruction |= inst.operands[1].reg << 16; 9528 inst.instruction |= inst.operands[2].reg; 9529 inst.instruction |= inst.operands[3].reg << 12; 9530} 9531 9532static void 9533do_t_mlal (void) 9534{ 9535 inst.instruction |= inst.operands[0].reg << 12; 9536 inst.instruction |= inst.operands[1].reg << 8; 9537 inst.instruction |= inst.operands[2].reg << 16; 9538 inst.instruction |= inst.operands[3].reg; 9539} 9540 9541static void 9542do_t_mov_cmp (void) 9543{ 9544 if (unified_syntax) 9545 { 9546 int r0off = (inst.instruction == T_MNEM_mov 9547 || inst.instruction == T_MNEM_movs) ? 8 : 16; 9548 unsigned long opcode; 9549 bfd_boolean narrow; 9550 bfd_boolean low_regs; 9551 9552 low_regs = (inst.operands[0].reg <= 7 && inst.operands[1].reg <= 7); 9553 opcode = inst.instruction; 9554 if (current_it_mask) 9555 narrow = opcode != T_MNEM_movs; 9556 else 9557 narrow = opcode != T_MNEM_movs || low_regs; 9558 if (inst.size_req == 4 9559 || inst.operands[1].shifted) 9560 narrow = FALSE; 9561 9562 /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */ 9563 if (opcode == T_MNEM_movs && inst.operands[1].isreg 9564 && !inst.operands[1].shifted 9565 && inst.operands[0].reg == REG_PC 9566 && inst.operands[1].reg == REG_LR) 9567 { 9568 inst.instruction = T2_SUBS_PC_LR; 9569 return; 9570 } 9571 9572 if (!inst.operands[1].isreg) 9573 { 9574 /* Immediate operand. */ 9575 if (current_it_mask == 0 && opcode == T_MNEM_mov) 9576 narrow = 0; 9577 if (low_regs && narrow) 9578 { 9579 inst.instruction = THUMB_OP16 (opcode); 9580 inst.instruction |= inst.operands[0].reg << 8; 9581 if (inst.size_req == 2) 9582 inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM; 9583 else 9584 inst.relax = opcode; 9585 } 9586 else 9587 { 9588 inst.instruction = THUMB_OP32 (inst.instruction); 9589 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000; 9590 inst.instruction |= inst.operands[0].reg << r0off; 9591 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; 9592 } 9593 } 9594 else if (inst.operands[1].shifted && inst.operands[1].immisreg 9595 && (inst.instruction == T_MNEM_mov 9596 || inst.instruction == T_MNEM_movs)) 9597 { 9598 /* Register shifts are encoded as separate shift instructions. */ 9599 bfd_boolean flags = (inst.instruction == T_MNEM_movs); 9600 9601 if (current_it_mask) 9602 narrow = !flags; 9603 else 9604 narrow = flags; 9605 9606 if (inst.size_req == 4) 9607 narrow = FALSE; 9608 9609 if (!low_regs || inst.operands[1].imm > 7) 9610 narrow = FALSE; 9611 9612 if (inst.operands[0].reg != inst.operands[1].reg) 9613 narrow = FALSE; 9614 9615 switch (inst.operands[1].shift_kind) 9616 { 9617 case SHIFT_LSL: 9618 opcode = narrow ? T_OPCODE_LSL_R : THUMB_OP32 (T_MNEM_lsl); 9619 break; 9620 case SHIFT_ASR: 9621 opcode = narrow ? T_OPCODE_ASR_R : THUMB_OP32 (T_MNEM_asr); 9622 break; 9623 case SHIFT_LSR: 9624 opcode = narrow ? T_OPCODE_LSR_R : THUMB_OP32 (T_MNEM_lsr); 9625 break; 9626 case SHIFT_ROR: 9627 opcode = narrow ? T_OPCODE_ROR_R : THUMB_OP32 (T_MNEM_ror); 9628 break; 9629 default: 9630 abort(); 9631 } 9632 9633 inst.instruction = opcode; 9634 if (narrow) 9635 { 9636 inst.instruction |= inst.operands[0].reg; 9637 inst.instruction |= inst.operands[1].imm << 3; 9638 } 9639 else 9640 { 9641 if (flags) 9642 inst.instruction |= CONDS_BIT; 9643 9644 inst.instruction |= inst.operands[0].reg << 8; 9645 inst.instruction |= inst.operands[1].reg << 16; 9646 inst.instruction |= inst.operands[1].imm; 9647 } 9648 } 9649 else if (!narrow) 9650 { 9651 /* Some mov with immediate shift have narrow variants. 9652 Register shifts are handled above. */ 9653 if (low_regs && inst.operands[1].shifted 9654 && (inst.instruction == T_MNEM_mov 9655 || inst.instruction == T_MNEM_movs)) 9656 { 9657 if (current_it_mask) 9658 narrow = (inst.instruction == T_MNEM_mov); 9659 else 9660 narrow = (inst.instruction == T_MNEM_movs); 9661 } 9662 9663 if (narrow) 9664 { 9665 switch (inst.operands[1].shift_kind) 9666 { 9667 case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_I; break; 9668 case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_I; break; 9669 case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_I; break; 9670 default: narrow = FALSE; break; 9671 } 9672 } 9673 9674 if (narrow) 9675 { 9676 inst.instruction |= inst.operands[0].reg; 9677 inst.instruction |= inst.operands[1].reg << 3; 9678 inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT; 9679 } 9680 else 9681 { 9682 inst.instruction = THUMB_OP32 (inst.instruction); 9683 inst.instruction |= inst.operands[0].reg << r0off; 9684 encode_thumb32_shifted_operand (1); 9685 } 9686 } 9687 else 9688 switch (inst.instruction) 9689 { 9690 case T_MNEM_mov: 9691 inst.instruction = T_OPCODE_MOV_HR; 9692 inst.instruction |= (inst.operands[0].reg & 0x8) << 4; 9693 inst.instruction |= (inst.operands[0].reg & 0x7); 9694 inst.instruction |= inst.operands[1].reg << 3; 9695 break; 9696 9697 case T_MNEM_movs: 9698 /* We know we have low registers at this point. 9699 Generate ADD Rd, Rs, #0. */ 9700 inst.instruction = T_OPCODE_ADD_I3; 9701 inst.instruction |= inst.operands[0].reg; 9702 inst.instruction |= inst.operands[1].reg << 3; 9703 break; 9704 9705 case T_MNEM_cmp: 9706 if (low_regs) 9707 { 9708 inst.instruction = T_OPCODE_CMP_LR; 9709 inst.instruction |= inst.operands[0].reg; 9710 inst.instruction |= inst.operands[1].reg << 3; 9711 } 9712 else 9713 { 9714 inst.instruction = T_OPCODE_CMP_HR; 9715 inst.instruction |= (inst.operands[0].reg & 0x8) << 4; 9716 inst.instruction |= (inst.operands[0].reg & 0x7); 9717 inst.instruction |= inst.operands[1].reg << 3; 9718 } 9719 break; 9720 } 9721 return; 9722 } 9723 9724 inst.instruction = THUMB_OP16 (inst.instruction); 9725 if (inst.operands[1].isreg) 9726 { 9727 if (inst.operands[0].reg < 8 && inst.operands[1].reg < 8) 9728 { 9729 /* A move of two lowregs is encoded as ADD Rd, Rs, #0 9730 since a MOV instruction produces unpredictable results. */ 9731 if (inst.instruction == T_OPCODE_MOV_I8) 9732 inst.instruction = T_OPCODE_ADD_I3; 9733 else 9734 inst.instruction = T_OPCODE_CMP_LR; 9735 9736 inst.instruction |= inst.operands[0].reg; 9737 inst.instruction |= inst.operands[1].reg << 3; 9738 } 9739 else 9740 { 9741 if (inst.instruction == T_OPCODE_MOV_I8) 9742 inst.instruction = T_OPCODE_MOV_HR; 9743 else 9744 inst.instruction = T_OPCODE_CMP_HR; 9745 do_t_cpy (); 9746 } 9747 } 9748 else 9749 { 9750 constraint (inst.operands[0].reg > 7, 9751 _("only lo regs allowed with immediate")); 9752 inst.instruction |= inst.operands[0].reg << 8; 9753 inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM; 9754 } 9755} 9756 9757static void 9758do_t_mov16 (void) 9759{ 9760 bfd_vma imm; 9761 bfd_boolean top; 9762 9763 top = (inst.instruction & 0x00800000) != 0; 9764 if (inst.reloc.type == BFD_RELOC_ARM_MOVW) 9765 { 9766 constraint (top, _(":lower16: not allowed this instruction")); 9767 inst.reloc.type = BFD_RELOC_ARM_THUMB_MOVW; 9768 } 9769 else if (inst.reloc.type == BFD_RELOC_ARM_MOVT) 9770 { 9771 constraint (!top, _(":upper16: not allowed this instruction")); 9772 inst.reloc.type = BFD_RELOC_ARM_THUMB_MOVT; 9773 } 9774 9775 inst.instruction |= inst.operands[0].reg << 8; 9776 if (inst.reloc.type == BFD_RELOC_UNUSED) 9777 { 9778 imm = inst.reloc.exp.X_add_number; 9779 inst.instruction |= (imm & 0xf000) << 4; 9780 inst.instruction |= (imm & 0x0800) << 15; 9781 inst.instruction |= (imm & 0x0700) << 4; 9782 inst.instruction |= (imm & 0x00ff); 9783 } 9784} 9785 9786static void 9787do_t_mvn_tst (void) 9788{ 9789 if (unified_syntax) 9790 { 9791 int r0off = (inst.instruction == T_MNEM_mvn 9792 || inst.instruction == T_MNEM_mvns) ? 8 : 16; 9793 bfd_boolean narrow; 9794 9795 if (inst.size_req == 4 9796 || inst.instruction > 0xffff 9797 || inst.operands[1].shifted 9798 || inst.operands[0].reg > 7 || inst.operands[1].reg > 7) 9799 narrow = FALSE; 9800 else if (inst.instruction == T_MNEM_cmn) 9801 narrow = TRUE; 9802 else if (THUMB_SETS_FLAGS (inst.instruction)) 9803 narrow = (current_it_mask == 0); 9804 else 9805 narrow = (current_it_mask != 0); 9806 9807 if (!inst.operands[1].isreg) 9808 { 9809 /* For an immediate, we always generate a 32-bit opcode; 9810 section relaxation will shrink it later if possible. */ 9811 if (inst.instruction < 0xffff) 9812 inst.instruction = THUMB_OP32 (inst.instruction); 9813 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000; 9814 inst.instruction |= inst.operands[0].reg << r0off; 9815 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; 9816 } 9817 else 9818 { 9819 /* See if we can do this with a 16-bit instruction. */ 9820 if (narrow) 9821 { 9822 inst.instruction = THUMB_OP16 (inst.instruction); 9823 inst.instruction |= inst.operands[0].reg; 9824 inst.instruction |= inst.operands[1].reg << 3; 9825 } 9826 else 9827 { 9828 constraint (inst.operands[1].shifted 9829 && inst.operands[1].immisreg, 9830 _("shift must be constant")); 9831 if (inst.instruction < 0xffff) 9832 inst.instruction = THUMB_OP32 (inst.instruction); 9833 inst.instruction |= inst.operands[0].reg << r0off; 9834 encode_thumb32_shifted_operand (1); 9835 } 9836 } 9837 } 9838 else 9839 { 9840 constraint (inst.instruction > 0xffff 9841 || inst.instruction == T_MNEM_mvns, BAD_THUMB32); 9842 constraint (!inst.operands[1].isreg || inst.operands[1].shifted, 9843 _("unshifted register required")); 9844 constraint (inst.operands[0].reg > 7 || inst.operands[1].reg > 7, 9845 BAD_HIREG); 9846 9847 inst.instruction = THUMB_OP16 (inst.instruction); 9848 inst.instruction |= inst.operands[0].reg; 9849 inst.instruction |= inst.operands[1].reg << 3; 9850 } 9851} 9852 9853static void 9854do_t_mrs (void) 9855{ 9856 int flags; 9857 9858 if (do_vfp_nsyn_mrs () == SUCCESS) 9859 return; 9860 9861 flags = inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f|SPSR_BIT); 9862 if (flags == 0) 9863 { 9864 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7m), 9865 _("selected processor does not support " 9866 "requested special purpose register")); 9867 } 9868 else 9869 { 9870 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1), 9871 _("selected processor does not support " 9872 "requested special purpose register %x")); 9873 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */ 9874 constraint ((flags & ~SPSR_BIT) != (PSR_c|PSR_f), 9875 _("'CPSR' or 'SPSR' expected")); 9876 } 9877 9878 inst.instruction |= inst.operands[0].reg << 8; 9879 inst.instruction |= (flags & SPSR_BIT) >> 2; 9880 inst.instruction |= inst.operands[1].imm & 0xff; 9881} 9882 9883static void 9884do_t_msr (void) 9885{ 9886 int flags; 9887 9888 if (do_vfp_nsyn_msr () == SUCCESS) 9889 return; 9890 9891 constraint (!inst.operands[1].isreg, 9892 _("Thumb encoding does not support an immediate here")); 9893 flags = inst.operands[0].imm; 9894 if (flags & ~0xff) 9895 { 9896 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1), 9897 _("selected processor does not support " 9898 "requested special purpose register")); 9899 } 9900 else 9901 { 9902 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7m), 9903 _("selected processor does not support " 9904 "requested special purpose register")); 9905 flags |= PSR_f; 9906 } 9907 inst.instruction |= (flags & SPSR_BIT) >> 2; 9908 inst.instruction |= (flags & ~SPSR_BIT) >> 8; 9909 inst.instruction |= (flags & 0xff); 9910 inst.instruction |= inst.operands[1].reg << 16; 9911} 9912 9913static void 9914do_t_mul (void) 9915{ 9916 if (!inst.operands[2].present) 9917 inst.operands[2].reg = inst.operands[0].reg; 9918 9919 /* There is no 32-bit MULS and no 16-bit MUL. */ 9920 if (unified_syntax && inst.instruction == T_MNEM_mul) 9921 { 9922 inst.instruction = THUMB_OP32 (inst.instruction); 9923 inst.instruction |= inst.operands[0].reg << 8; 9924 inst.instruction |= inst.operands[1].reg << 16; 9925 inst.instruction |= inst.operands[2].reg << 0; 9926 } 9927 else 9928 { 9929 constraint (!unified_syntax 9930 && inst.instruction == T_MNEM_muls, BAD_THUMB32); 9931 constraint (inst.operands[0].reg > 7 || inst.operands[1].reg > 7, 9932 BAD_HIREG); 9933 9934 inst.instruction = THUMB_OP16 (inst.instruction); 9935 inst.instruction |= inst.operands[0].reg; 9936 9937 if (inst.operands[0].reg == inst.operands[1].reg) 9938 inst.instruction |= inst.operands[2].reg << 3; 9939 else if (inst.operands[0].reg == inst.operands[2].reg) 9940 inst.instruction |= inst.operands[1].reg << 3; 9941 else 9942 constraint (1, _("dest must overlap one source register")); 9943 } 9944} 9945 9946static void 9947do_t_mull (void) 9948{ 9949 inst.instruction |= inst.operands[0].reg << 12; 9950 inst.instruction |= inst.operands[1].reg << 8; 9951 inst.instruction |= inst.operands[2].reg << 16; 9952 inst.instruction |= inst.operands[3].reg; 9953 9954 if (inst.operands[0].reg == inst.operands[1].reg) 9955 as_tsktsk (_("rdhi and rdlo must be different")); 9956} 9957 9958static void 9959do_t_nop (void) 9960{ 9961 if (unified_syntax) 9962 { 9963 if (inst.size_req == 4 || inst.operands[0].imm > 15) 9964 { 9965 inst.instruction = THUMB_OP32 (inst.instruction); 9966 inst.instruction |= inst.operands[0].imm; 9967 } 9968 else 9969 { 9970 inst.instruction = THUMB_OP16 (inst.instruction); 9971 inst.instruction |= inst.operands[0].imm << 4; 9972 } 9973 } 9974 else 9975 { 9976 constraint (inst.operands[0].present, 9977 _("Thumb does not support NOP with hints")); 9978 inst.instruction = 0x46c0; 9979 } 9980} 9981 9982static void 9983do_t_neg (void) 9984{ 9985 if (unified_syntax) 9986 { 9987 bfd_boolean narrow; 9988 9989 if (THUMB_SETS_FLAGS (inst.instruction)) 9990 narrow = (current_it_mask == 0); 9991 else 9992 narrow = (current_it_mask != 0); 9993 if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7) 9994 narrow = FALSE; 9995 if (inst.size_req == 4) 9996 narrow = FALSE; 9997 9998 if (!narrow) 9999 { 10000 inst.instruction = THUMB_OP32 (inst.instruction); 10001 inst.instruction |= inst.operands[0].reg << 8; 10002 inst.instruction |= inst.operands[1].reg << 16; 10003 } 10004 else 10005 { 10006 inst.instruction = THUMB_OP16 (inst.instruction); 10007 inst.instruction |= inst.operands[0].reg; 10008 inst.instruction |= inst.operands[1].reg << 3; 10009 } 10010 } 10011 else 10012 { 10013 constraint (inst.operands[0].reg > 7 || inst.operands[1].reg > 7, 10014 BAD_HIREG); 10015 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32); 10016 10017 inst.instruction = THUMB_OP16 (inst.instruction); 10018 inst.instruction |= inst.operands[0].reg; 10019 inst.instruction |= inst.operands[1].reg << 3; 10020 } 10021} 10022 10023static void 10024do_t_pkhbt (void) 10025{ 10026 inst.instruction |= inst.operands[0].reg << 8; 10027 inst.instruction |= inst.operands[1].reg << 16; 10028 inst.instruction |= inst.operands[2].reg; 10029 if (inst.operands[3].present) 10030 { 10031 unsigned int val = inst.reloc.exp.X_add_number; 10032 constraint (inst.reloc.exp.X_op != O_constant, 10033 _("expression too complex")); 10034 inst.instruction |= (val & 0x1c) << 10; 10035 inst.instruction |= (val & 0x03) << 6; 10036 } 10037} 10038 10039static void 10040do_t_pkhtb (void) 10041{ 10042 if (!inst.operands[3].present) 10043 inst.instruction &= ~0x00000020; 10044 do_t_pkhbt (); 10045} 10046 10047static void 10048do_t_pld (void) 10049{ 10050 encode_thumb32_addr_mode (0, /*is_t=*/FALSE, /*is_d=*/FALSE); 10051} 10052 10053static void 10054do_t_push_pop (void) 10055{ 10056 unsigned mask; 10057 10058 constraint (inst.operands[0].writeback, 10059 _("push/pop do not support {reglist}^")); 10060 constraint (inst.reloc.type != BFD_RELOC_UNUSED, 10061 _("expression too complex")); 10062 10063 mask = inst.operands[0].imm; 10064 if ((mask & ~0xff) == 0) 10065 inst.instruction = THUMB_OP16 (inst.instruction) | mask; 10066 else if ((inst.instruction == T_MNEM_push 10067 && (mask & ~0xff) == 1 << REG_LR) 10068 || (inst.instruction == T_MNEM_pop 10069 && (mask & ~0xff) == 1 << REG_PC)) 10070 { 10071 inst.instruction = THUMB_OP16 (inst.instruction); 10072 inst.instruction |= THUMB_PP_PC_LR; 10073 inst.instruction |= mask & 0xff; 10074 } 10075 else if (unified_syntax) 10076 { 10077 inst.instruction = THUMB_OP32 (inst.instruction); 10078 encode_thumb2_ldmstm(13, mask, TRUE); 10079 } 10080 else 10081 { 10082 inst.error = _("invalid register list to push/pop instruction"); 10083 return; 10084 } 10085} 10086 10087static void 10088do_t_rbit (void) 10089{ 10090 inst.instruction |= inst.operands[0].reg << 8; 10091 inst.instruction |= inst.operands[1].reg << 16; 10092} 10093 10094static void 10095do_t_rd_rm (void) 10096{ 10097 inst.instruction |= inst.operands[0].reg << 8; 10098 inst.instruction |= inst.operands[1].reg; 10099} 10100 10101static void 10102do_t_rev (void) 10103{ 10104 if (inst.operands[0].reg <= 7 && inst.operands[1].reg <= 7 10105 && inst.size_req != 4) 10106 { 10107 inst.instruction = THUMB_OP16 (inst.instruction); 10108 inst.instruction |= inst.operands[0].reg; 10109 inst.instruction |= inst.operands[1].reg << 3; 10110 } 10111 else if (unified_syntax) 10112 { 10113 inst.instruction = THUMB_OP32 (inst.instruction); 10114 inst.instruction |= inst.operands[0].reg << 8; 10115 inst.instruction |= inst.operands[1].reg << 16; 10116 inst.instruction |= inst.operands[1].reg; 10117 } 10118 else 10119 inst.error = BAD_HIREG; 10120} 10121 10122static void 10123do_t_rsb (void) 10124{ 10125 int Rd, Rs; 10126 10127 Rd = inst.operands[0].reg; 10128 Rs = (inst.operands[1].present 10129 ? inst.operands[1].reg /* Rd, Rs, foo */ 10130 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */ 10131 10132 inst.instruction |= Rd << 8; 10133 inst.instruction |= Rs << 16; 10134 if (!inst.operands[2].isreg) 10135 { 10136 bfd_boolean narrow; 10137 10138 if ((inst.instruction & 0x00100000) != 0) 10139 narrow = (current_it_mask == 0); 10140 else 10141 narrow = (current_it_mask != 0); 10142 10143 if (Rd > 7 || Rs > 7) 10144 narrow = FALSE; 10145 10146 if (inst.size_req == 4 || !unified_syntax) 10147 narrow = FALSE; 10148 10149 if (inst.reloc.exp.X_op != O_constant 10150 || inst.reloc.exp.X_add_number != 0) 10151 narrow = FALSE; 10152 10153 /* Turn rsb #0 into 16-bit neg. We should probably do this via 10154 relaxation, but it doesn't seem worth the hassle. */ 10155 if (narrow) 10156 { 10157 inst.reloc.type = BFD_RELOC_UNUSED; 10158 inst.instruction = THUMB_OP16 (T_MNEM_negs); 10159 inst.instruction |= Rs << 3; 10160 inst.instruction |= Rd; 10161 } 10162 else 10163 { 10164 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000; 10165 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; 10166 } 10167 } 10168 else 10169 encode_thumb32_shifted_operand (2); 10170} 10171 10172static void 10173do_t_setend (void) 10174{ 10175 constraint (current_it_mask, BAD_NOT_IT); 10176 if (inst.operands[0].imm) 10177 inst.instruction |= 0x8; 10178} 10179 10180static void 10181do_t_shift (void) 10182{ 10183 if (!inst.operands[1].present) 10184 inst.operands[1].reg = inst.operands[0].reg; 10185 10186 if (unified_syntax) 10187 { 10188 bfd_boolean narrow; 10189 int shift_kind; 10190 10191 switch (inst.instruction) 10192 { 10193 case T_MNEM_asr: 10194 case T_MNEM_asrs: shift_kind = SHIFT_ASR; break; 10195 case T_MNEM_lsl: 10196 case T_MNEM_lsls: shift_kind = SHIFT_LSL; break; 10197 case T_MNEM_lsr: 10198 case T_MNEM_lsrs: shift_kind = SHIFT_LSR; break; 10199 case T_MNEM_ror: 10200 case T_MNEM_rors: shift_kind = SHIFT_ROR; break; 10201 default: abort (); 10202 } 10203 10204 if (THUMB_SETS_FLAGS (inst.instruction)) 10205 narrow = (current_it_mask == 0); 10206 else 10207 narrow = (current_it_mask != 0); 10208 if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7) 10209 narrow = FALSE; 10210 if (!inst.operands[2].isreg && shift_kind == SHIFT_ROR) 10211 narrow = FALSE; 10212 if (inst.operands[2].isreg 10213 && (inst.operands[1].reg != inst.operands[0].reg 10214 || inst.operands[2].reg > 7)) 10215 narrow = FALSE; 10216 if (inst.size_req == 4) 10217 narrow = FALSE; 10218 10219 if (!narrow) 10220 { 10221 if (inst.operands[2].isreg) 10222 { 10223 inst.instruction = THUMB_OP32 (inst.instruction); 10224 inst.instruction |= inst.operands[0].reg << 8; 10225 inst.instruction |= inst.operands[1].reg << 16; 10226 inst.instruction |= inst.operands[2].reg; 10227 } 10228 else 10229 { 10230 inst.operands[1].shifted = 1; 10231 inst.operands[1].shift_kind = shift_kind; 10232 inst.instruction = THUMB_OP32 (THUMB_SETS_FLAGS (inst.instruction) 10233 ? T_MNEM_movs : T_MNEM_mov); 10234 inst.instruction |= inst.operands[0].reg << 8; 10235 encode_thumb32_shifted_operand (1); 10236 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */ 10237 inst.reloc.type = BFD_RELOC_UNUSED; 10238 } 10239 } 10240 else 10241 { 10242 if (inst.operands[2].isreg) 10243 { 10244 switch (shift_kind) 10245 { 10246 case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_R; break; 10247 case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_R; break; 10248 case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_R; break; 10249 case SHIFT_ROR: inst.instruction = T_OPCODE_ROR_R; break; 10250 default: abort (); 10251 } 10252 10253 inst.instruction |= inst.operands[0].reg; 10254 inst.instruction |= inst.operands[2].reg << 3; 10255 } 10256 else 10257 { 10258 switch (shift_kind) 10259 { 10260 case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_I; break; 10261 case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_I; break; 10262 case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_I; break; 10263 default: abort (); 10264 } 10265 inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT; 10266 inst.instruction |= inst.operands[0].reg; 10267 inst.instruction |= inst.operands[1].reg << 3; 10268 } 10269 } 10270 } 10271 else 10272 { 10273 constraint (inst.operands[0].reg > 7 10274 || inst.operands[1].reg > 7, BAD_HIREG); 10275 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32); 10276 10277 if (inst.operands[2].isreg) /* Rd, {Rs,} Rn */ 10278 { 10279 constraint (inst.operands[2].reg > 7, BAD_HIREG); 10280 constraint (inst.operands[0].reg != inst.operands[1].reg, 10281 _("source1 and dest must be same register")); 10282 10283 switch (inst.instruction) 10284 { 10285 case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_R; break; 10286 case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_R; break; 10287 case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_R; break; 10288 case T_MNEM_ror: inst.instruction = T_OPCODE_ROR_R; break; 10289 default: abort (); 10290 } 10291 10292 inst.instruction |= inst.operands[0].reg; 10293 inst.instruction |= inst.operands[2].reg << 3; 10294 } 10295 else 10296 { 10297 switch (inst.instruction) 10298 { 10299 case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_I; break; 10300 case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_I; break; 10301 case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_I; break; 10302 case T_MNEM_ror: inst.error = _("ror #imm not supported"); return; 10303 default: abort (); 10304 } 10305 inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT; 10306 inst.instruction |= inst.operands[0].reg; 10307 inst.instruction |= inst.operands[1].reg << 3; 10308 } 10309 } 10310} 10311 10312static void 10313do_t_simd (void) 10314{ 10315 inst.instruction |= inst.operands[0].reg << 8; 10316 inst.instruction |= inst.operands[1].reg << 16; 10317 inst.instruction |= inst.operands[2].reg; 10318} 10319 10320static void 10321do_t_smc (void) 10322{ 10323 unsigned int value = inst.reloc.exp.X_add_number; 10324 constraint (inst.reloc.exp.X_op != O_constant, 10325 _("expression too complex")); 10326 inst.reloc.type = BFD_RELOC_UNUSED; 10327 inst.instruction |= (value & 0xf000) >> 12; 10328 inst.instruction |= (value & 0x0ff0); 10329 inst.instruction |= (value & 0x000f) << 16; 10330} 10331 10332static void 10333do_t_ssat (void) 10334{ 10335 inst.instruction |= inst.operands[0].reg << 8; 10336 inst.instruction |= inst.operands[1].imm - 1; 10337 inst.instruction |= inst.operands[2].reg << 16; 10338 10339 if (inst.operands[3].present) 10340 { 10341 constraint (inst.reloc.exp.X_op != O_constant, 10342 _("expression too complex")); 10343 10344 if (inst.reloc.exp.X_add_number != 0) 10345 { 10346 if (inst.operands[3].shift_kind == SHIFT_ASR) 10347 inst.instruction |= 0x00200000; /* sh bit */ 10348 inst.instruction |= (inst.reloc.exp.X_add_number & 0x1c) << 10; 10349 inst.instruction |= (inst.reloc.exp.X_add_number & 0x03) << 6; 10350 } 10351 inst.reloc.type = BFD_RELOC_UNUSED; 10352 } 10353} 10354 10355static void 10356do_t_ssat16 (void) 10357{ 10358 inst.instruction |= inst.operands[0].reg << 8; 10359 inst.instruction |= inst.operands[1].imm - 1; 10360 inst.instruction |= inst.operands[2].reg << 16; 10361} 10362 10363static void 10364do_t_strex (void) 10365{ 10366 constraint (!inst.operands[2].isreg || !inst.operands[2].preind 10367 || inst.operands[2].postind || inst.operands[2].writeback 10368 || inst.operands[2].immisreg || inst.operands[2].shifted 10369 || inst.operands[2].negative, 10370 BAD_ADDR_MODE); 10371 10372 inst.instruction |= inst.operands[0].reg << 8; 10373 inst.instruction |= inst.operands[1].reg << 12; 10374 inst.instruction |= inst.operands[2].reg << 16; 10375 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_U8; 10376} 10377 10378static void 10379do_t_strexd (void) 10380{ 10381 if (!inst.operands[2].present) 10382 inst.operands[2].reg = inst.operands[1].reg + 1; 10383 10384 constraint (inst.operands[0].reg == inst.operands[1].reg 10385 || inst.operands[0].reg == inst.operands[2].reg 10386 || inst.operands[0].reg == inst.operands[3].reg 10387 || inst.operands[1].reg == inst.operands[2].reg, 10388 BAD_OVERLAP); 10389 10390 inst.instruction |= inst.operands[0].reg; 10391 inst.instruction |= inst.operands[1].reg << 12; 10392 inst.instruction |= inst.operands[2].reg << 8; 10393 inst.instruction |= inst.operands[3].reg << 16; 10394} 10395 10396static void 10397do_t_sxtah (void) 10398{ 10399 inst.instruction |= inst.operands[0].reg << 8; 10400 inst.instruction |= inst.operands[1].reg << 16; 10401 inst.instruction |= inst.operands[2].reg; 10402 inst.instruction |= inst.operands[3].imm << 4; 10403} 10404 10405static void 10406do_t_sxth (void) 10407{ 10408 if (inst.instruction <= 0xffff && inst.size_req != 4 10409 && inst.operands[0].reg <= 7 && inst.operands[1].reg <= 7 10410 && (!inst.operands[2].present || inst.operands[2].imm == 0)) 10411 { 10412 inst.instruction = THUMB_OP16 (inst.instruction); 10413 inst.instruction |= inst.operands[0].reg; 10414 inst.instruction |= inst.operands[1].reg << 3; 10415 } 10416 else if (unified_syntax) 10417 { 10418 if (inst.instruction <= 0xffff) 10419 inst.instruction = THUMB_OP32 (inst.instruction); 10420 inst.instruction |= inst.operands[0].reg << 8; 10421 inst.instruction |= inst.operands[1].reg; 10422 inst.instruction |= inst.operands[2].imm << 4; 10423 } 10424 else 10425 { 10426 constraint (inst.operands[2].present && inst.operands[2].imm != 0, 10427 _("Thumb encoding does not support rotation")); 10428 constraint (1, BAD_HIREG); 10429 } 10430} 10431 10432static void 10433do_t_swi (void) 10434{ 10435 inst.reloc.type = BFD_RELOC_ARM_SWI; 10436} 10437 10438static void 10439do_t_tb (void) 10440{ 10441 int half; 10442 10443 half = (inst.instruction & 0x10) != 0; 10444 constraint (current_it_mask && current_it_mask != 0x10, BAD_BRANCH); 10445 constraint (inst.operands[0].immisreg, 10446 _("instruction requires register index")); 10447 constraint (inst.operands[0].imm == 15, 10448 _("PC is not a valid index register")); 10449 constraint (!half && inst.operands[0].shifted, 10450 _("instruction does not allow shifted index")); 10451 inst.instruction |= (inst.operands[0].reg << 16) | inst.operands[0].imm; 10452} 10453 10454static void 10455do_t_usat (void) 10456{ 10457 inst.instruction |= inst.operands[0].reg << 8; 10458 inst.instruction |= inst.operands[1].imm; 10459 inst.instruction |= inst.operands[2].reg << 16; 10460 10461 if (inst.operands[3].present) 10462 { 10463 constraint (inst.reloc.exp.X_op != O_constant, 10464 _("expression too complex")); 10465 if (inst.reloc.exp.X_add_number != 0) 10466 { 10467 if (inst.operands[3].shift_kind == SHIFT_ASR) 10468 inst.instruction |= 0x00200000; /* sh bit */ 10469 10470 inst.instruction |= (inst.reloc.exp.X_add_number & 0x1c) << 10; 10471 inst.instruction |= (inst.reloc.exp.X_add_number & 0x03) << 6; 10472 } 10473 inst.reloc.type = BFD_RELOC_UNUSED; 10474 } 10475} 10476 10477static void 10478do_t_usat16 (void) 10479{ 10480 inst.instruction |= inst.operands[0].reg << 8; 10481 inst.instruction |= inst.operands[1].imm; 10482 inst.instruction |= inst.operands[2].reg << 16; 10483} 10484 10485/* Neon instruction encoder helpers. */ 10486 10487/* Encodings for the different types for various Neon opcodes. */ 10488 10489/* An "invalid" code for the following tables. */ 10490#define N_INV -1u 10491 10492struct neon_tab_entry 10493{ 10494 unsigned integer; 10495 unsigned float_or_poly; 10496 unsigned scalar_or_imm; 10497}; 10498 10499/* Map overloaded Neon opcodes to their respective encodings. */ 10500#define NEON_ENC_TAB \ 10501 X(vabd, 0x0000700, 0x1200d00, N_INV), \ 10502 X(vmax, 0x0000600, 0x0000f00, N_INV), \ 10503 X(vmin, 0x0000610, 0x0200f00, N_INV), \ 10504 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \ 10505 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \ 10506 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \ 10507 X(vadd, 0x0000800, 0x0000d00, N_INV), \ 10508 X(vsub, 0x1000800, 0x0200d00, N_INV), \ 10509 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \ 10510 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \ 10511 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \ 10512 /* Register variants of the following two instructions are encoded as 10513 vcge / vcgt with the operands reversed. */ \ 10514 X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \ 10515 X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \ 10516 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \ 10517 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \ 10518 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \ 10519 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \ 10520 X(vmlal, 0x0800800, N_INV, 0x0800240), \ 10521 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \ 10522 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \ 10523 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \ 10524 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \ 10525 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \ 10526 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \ 10527 X(vshl, 0x0000400, N_INV, 0x0800510), \ 10528 X(vqshl, 0x0000410, N_INV, 0x0800710), \ 10529 X(vand, 0x0000110, N_INV, 0x0800030), \ 10530 X(vbic, 0x0100110, N_INV, 0x0800030), \ 10531 X(veor, 0x1000110, N_INV, N_INV), \ 10532 X(vorn, 0x0300110, N_INV, 0x0800010), \ 10533 X(vorr, 0x0200110, N_INV, 0x0800010), \ 10534 X(vmvn, 0x1b00580, N_INV, 0x0800030), \ 10535 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \ 10536 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \ 10537 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \ 10538 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \ 10539 X(vst1, 0x0000000, 0x0800000, N_INV), \ 10540 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \ 10541 X(vst2, 0x0000100, 0x0800100, N_INV), \ 10542 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \ 10543 X(vst3, 0x0000200, 0x0800200, N_INV), \ 10544 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \ 10545 X(vst4, 0x0000300, 0x0800300, N_INV), \ 10546 X(vmovn, 0x1b20200, N_INV, N_INV), \ 10547 X(vtrn, 0x1b20080, N_INV, N_INV), \ 10548 X(vqmovn, 0x1b20200, N_INV, N_INV), \ 10549 X(vqmovun, 0x1b20240, N_INV, N_INV), \ 10550 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \ 10551 X(vnmla, 0xe000a40, 0xe000b40, N_INV), \ 10552 X(vnmls, 0xe100a40, 0xe100b40, N_INV), \ 10553 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \ 10554 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \ 10555 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \ 10556 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV) 10557 10558enum neon_opc 10559{ 10560#define X(OPC,I,F,S) N_MNEM_##OPC 10561NEON_ENC_TAB 10562#undef X 10563}; 10564 10565static const struct neon_tab_entry neon_enc_tab[] = 10566{ 10567#define X(OPC,I,F,S) { (I), (F), (S) } 10568NEON_ENC_TAB 10569#undef X 10570}; 10571 10572#define NEON_ENC_INTEGER(X) (neon_enc_tab[(X) & 0x0fffffff].integer) 10573#define NEON_ENC_ARMREG(X) (neon_enc_tab[(X) & 0x0fffffff].integer) 10574#define NEON_ENC_POLY(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly) 10575#define NEON_ENC_FLOAT(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly) 10576#define NEON_ENC_SCALAR(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm) 10577#define NEON_ENC_IMMED(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm) 10578#define NEON_ENC_INTERLV(X) (neon_enc_tab[(X) & 0x0fffffff].integer) 10579#define NEON_ENC_LANE(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly) 10580#define NEON_ENC_DUP(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm) 10581#define NEON_ENC_SINGLE(X) \ 10582 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000)) 10583#define NEON_ENC_DOUBLE(X) \ 10584 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000)) 10585 10586/* Define shapes for instruction operands. The following mnemonic characters 10587 are used in this table: 10588 10589 F - VFP S<n> register 10590 D - Neon D<n> register 10591 Q - Neon Q<n> register 10592 I - Immediate 10593 S - Scalar 10594 R - ARM register 10595 L - D<n> register list 10596 10597 This table is used to generate various data: 10598 - enumerations of the form NS_DDR to be used as arguments to 10599 neon_select_shape. 10600 - a table classifying shapes into single, double, quad, mixed. 10601 - a table used to drive neon_select_shape. 10602*/ 10603 10604#define NEON_SHAPE_DEF \ 10605 X(3, (D, D, D), DOUBLE), \ 10606 X(3, (Q, Q, Q), QUAD), \ 10607 X(3, (D, D, I), DOUBLE), \ 10608 X(3, (Q, Q, I), QUAD), \ 10609 X(3, (D, D, S), DOUBLE), \ 10610 X(3, (Q, Q, S), QUAD), \ 10611 X(2, (D, D), DOUBLE), \ 10612 X(2, (Q, Q), QUAD), \ 10613 X(2, (D, S), DOUBLE), \ 10614 X(2, (Q, S), QUAD), \ 10615 X(2, (D, R), DOUBLE), \ 10616 X(2, (Q, R), QUAD), \ 10617 X(2, (D, I), DOUBLE), \ 10618 X(2, (Q, I), QUAD), \ 10619 X(3, (D, L, D), DOUBLE), \ 10620 X(2, (D, Q), MIXED), \ 10621 X(2, (Q, D), MIXED), \ 10622 X(3, (D, Q, I), MIXED), \ 10623 X(3, (Q, D, I), MIXED), \ 10624 X(3, (Q, D, D), MIXED), \ 10625 X(3, (D, Q, Q), MIXED), \ 10626 X(3, (Q, Q, D), MIXED), \ 10627 X(3, (Q, D, S), MIXED), \ 10628 X(3, (D, Q, S), MIXED), \ 10629 X(4, (D, D, D, I), DOUBLE), \ 10630 X(4, (Q, Q, Q, I), QUAD), \ 10631 X(2, (F, F), SINGLE), \ 10632 X(3, (F, F, F), SINGLE), \ 10633 X(2, (F, I), SINGLE), \ 10634 X(2, (F, D), MIXED), \ 10635 X(2, (D, F), MIXED), \ 10636 X(3, (F, F, I), MIXED), \ 10637 X(4, (R, R, F, F), SINGLE), \ 10638 X(4, (F, F, R, R), SINGLE), \ 10639 X(3, (D, R, R), DOUBLE), \ 10640 X(3, (R, R, D), DOUBLE), \ 10641 X(2, (S, R), SINGLE), \ 10642 X(2, (R, S), SINGLE), \ 10643 X(2, (F, R), SINGLE), \ 10644 X(2, (R, F), SINGLE) 10645 10646#define S2(A,B) NS_##A##B 10647#define S3(A,B,C) NS_##A##B##C 10648#define S4(A,B,C,D) NS_##A##B##C##D 10649 10650#define X(N, L, C) S##N L 10651 10652enum neon_shape 10653{ 10654 NEON_SHAPE_DEF, 10655 NS_NULL 10656}; 10657 10658#undef X 10659#undef S2 10660#undef S3 10661#undef S4 10662 10663enum neon_shape_class 10664{ 10665 SC_SINGLE, 10666 SC_DOUBLE, 10667 SC_QUAD, 10668 SC_MIXED 10669}; 10670 10671#define X(N, L, C) SC_##C 10672 10673static enum neon_shape_class neon_shape_class[] = 10674{ 10675 NEON_SHAPE_DEF 10676}; 10677 10678#undef X 10679 10680enum neon_shape_el 10681{ 10682 SE_F, 10683 SE_D, 10684 SE_Q, 10685 SE_I, 10686 SE_S, 10687 SE_R, 10688 SE_L 10689}; 10690 10691/* Register widths of above. */ 10692static unsigned neon_shape_el_size[] = 10693{ 10694 32, 10695 64, 10696 128, 10697 0, 10698 32, 10699 32, 10700 0 10701}; 10702 10703struct neon_shape_info 10704{ 10705 unsigned els; 10706 enum neon_shape_el el[NEON_MAX_TYPE_ELS]; 10707}; 10708 10709#define S2(A,B) { SE_##A, SE_##B } 10710#define S3(A,B,C) { SE_##A, SE_##B, SE_##C } 10711#define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D } 10712 10713#define X(N, L, C) { N, S##N L } 10714 10715static struct neon_shape_info neon_shape_tab[] = 10716{ 10717 NEON_SHAPE_DEF 10718}; 10719 10720#undef X 10721#undef S2 10722#undef S3 10723#undef S4 10724 10725/* Bit masks used in type checking given instructions. 10726 'N_EQK' means the type must be the same as (or based on in some way) the key 10727 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is 10728 set, various other bits can be set as well in order to modify the meaning of 10729 the type constraint. */ 10730 10731enum neon_type_mask 10732{ 10733 N_S8 = 0x000001, 10734 N_S16 = 0x000002, 10735 N_S32 = 0x000004, 10736 N_S64 = 0x000008, 10737 N_U8 = 0x000010, 10738 N_U16 = 0x000020, 10739 N_U32 = 0x000040, 10740 N_U64 = 0x000080, 10741 N_I8 = 0x000100, 10742 N_I16 = 0x000200, 10743 N_I32 = 0x000400, 10744 N_I64 = 0x000800, 10745 N_8 = 0x001000, 10746 N_16 = 0x002000, 10747 N_32 = 0x004000, 10748 N_64 = 0x008000, 10749 N_P8 = 0x010000, 10750 N_P16 = 0x020000, 10751 N_F32 = 0x040000, 10752 N_F64 = 0x080000, 10753 N_KEY = 0x100000, /* key element (main type specifier). */ 10754 N_EQK = 0x200000, /* given operand has the same type & size as the key. */ 10755 N_VFP = 0x400000, /* VFP mode: operand size must match register width. */ 10756 N_DBL = 0x000001, /* if N_EQK, this operand is twice the size. */ 10757 N_HLF = 0x000002, /* if N_EQK, this operand is half the size. */ 10758 N_SGN = 0x000004, /* if N_EQK, this operand is forced to be signed. */ 10759 N_UNS = 0x000008, /* if N_EQK, this operand is forced to be unsigned. */ 10760 N_INT = 0x000010, /* if N_EQK, this operand is forced to be integer. */ 10761 N_FLT = 0x000020, /* if N_EQK, this operand is forced to be float. */ 10762 N_SIZ = 0x000040, /* if N_EQK, this operand is forced to be size-only. */ 10763 N_UTYP = 0, 10764 N_MAX_NONSPECIAL = N_F64 10765}; 10766 10767#define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ) 10768 10769#define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64) 10770#define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32) 10771#define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64) 10772#define N_SUF_32 (N_SU_32 | N_F32) 10773#define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64) 10774#define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F32) 10775 10776/* Pass this as the first type argument to neon_check_type to ignore types 10777 altogether. */ 10778#define N_IGNORE_TYPE (N_KEY | N_EQK) 10779 10780/* Select a "shape" for the current instruction (describing register types or 10781 sizes) from a list of alternatives. Return NS_NULL if the current instruction 10782 doesn't fit. For non-polymorphic shapes, checking is usually done as a 10783 function of operand parsing, so this function doesn't need to be called. 10784 Shapes should be listed in order of decreasing length. */ 10785 10786static enum neon_shape 10787neon_select_shape (enum neon_shape shape, ...) 10788{ 10789 va_list ap; 10790 enum neon_shape first_shape = shape; 10791 10792 /* Fix missing optional operands. FIXME: we don't know at this point how 10793 many arguments we should have, so this makes the assumption that we have 10794 > 1. This is true of all current Neon opcodes, I think, but may not be 10795 true in the future. */ 10796 if (!inst.operands[1].present) 10797 inst.operands[1] = inst.operands[0]; 10798 10799 va_start (ap, shape); 10800 10801 for (; shape != NS_NULL; shape = va_arg (ap, int)) 10802 { 10803 unsigned j; 10804 int matches = 1; 10805 10806 for (j = 0; j < neon_shape_tab[shape].els; j++) 10807 { 10808 if (!inst.operands[j].present) 10809 { 10810 matches = 0; 10811 break; 10812 } 10813 10814 switch (neon_shape_tab[shape].el[j]) 10815 { 10816 case SE_F: 10817 if (!(inst.operands[j].isreg 10818 && inst.operands[j].isvec 10819 && inst.operands[j].issingle 10820 && !inst.operands[j].isquad)) 10821 matches = 0; 10822 break; 10823 10824 case SE_D: 10825 if (!(inst.operands[j].isreg 10826 && inst.operands[j].isvec 10827 && !inst.operands[j].isquad 10828 && !inst.operands[j].issingle)) 10829 matches = 0; 10830 break; 10831 10832 case SE_R: 10833 if (!(inst.operands[j].isreg 10834 && !inst.operands[j].isvec)) 10835 matches = 0; 10836 break; 10837 10838 case SE_Q: 10839 if (!(inst.operands[j].isreg 10840 && inst.operands[j].isvec 10841 && inst.operands[j].isquad 10842 && !inst.operands[j].issingle)) 10843 matches = 0; 10844 break; 10845 10846 case SE_I: 10847 if (!(!inst.operands[j].isreg 10848 && !inst.operands[j].isscalar)) 10849 matches = 0; 10850 break; 10851 10852 case SE_S: 10853 if (!(!inst.operands[j].isreg 10854 && inst.operands[j].isscalar)) 10855 matches = 0; 10856 break; 10857 10858 case SE_L: 10859 break; 10860 } 10861 } 10862 if (matches) 10863 break; 10864 } 10865 10866 va_end (ap); 10867 10868 if (shape == NS_NULL && first_shape != NS_NULL) 10869 first_error (_("invalid instruction shape")); 10870 10871 return shape; 10872} 10873 10874/* True if SHAPE is predominantly a quadword operation (most of the time, this 10875 means the Q bit should be set). */ 10876 10877static int 10878neon_quad (enum neon_shape shape) 10879{ 10880 return neon_shape_class[shape] == SC_QUAD; 10881} 10882 10883static void 10884neon_modify_type_size (unsigned typebits, enum neon_el_type *g_type, 10885 unsigned *g_size) 10886{ 10887 /* Allow modification to be made to types which are constrained to be 10888 based on the key element, based on bits set alongside N_EQK. */ 10889 if ((typebits & N_EQK) != 0) 10890 { 10891 if ((typebits & N_HLF) != 0) 10892 *g_size /= 2; 10893 else if ((typebits & N_DBL) != 0) 10894 *g_size *= 2; 10895 if ((typebits & N_SGN) != 0) 10896 *g_type = NT_signed; 10897 else if ((typebits & N_UNS) != 0) 10898 *g_type = NT_unsigned; 10899 else if ((typebits & N_INT) != 0) 10900 *g_type = NT_integer; 10901 else if ((typebits & N_FLT) != 0) 10902 *g_type = NT_float; 10903 else if ((typebits & N_SIZ) != 0) 10904 *g_type = NT_untyped; 10905 } 10906} 10907 10908/* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key" 10909 operand type, i.e. the single type specified in a Neon instruction when it 10910 is the only one given. */ 10911 10912static struct neon_type_el 10913neon_type_promote (struct neon_type_el *key, unsigned thisarg) 10914{ 10915 struct neon_type_el dest = *key; 10916 10917 assert ((thisarg & N_EQK) != 0); 10918 10919 neon_modify_type_size (thisarg, &dest.type, &dest.size); 10920 10921 return dest; 10922} 10923 10924/* Convert Neon type and size into compact bitmask representation. */ 10925 10926static enum neon_type_mask 10927type_chk_of_el_type (enum neon_el_type type, unsigned size) 10928{ 10929 switch (type) 10930 { 10931 case NT_untyped: 10932 switch (size) 10933 { 10934 case 8: return N_8; 10935 case 16: return N_16; 10936 case 32: return N_32; 10937 case 64: return N_64; 10938 default: ; 10939 } 10940 break; 10941 10942 case NT_integer: 10943 switch (size) 10944 { 10945 case 8: return N_I8; 10946 case 16: return N_I16; 10947 case 32: return N_I32; 10948 case 64: return N_I64; 10949 default: ; 10950 } 10951 break; 10952 10953 case NT_float: 10954 switch (size) 10955 { 10956 case 32: return N_F32; 10957 case 64: return N_F64; 10958 default: ; 10959 } 10960 break; 10961 10962 case NT_poly: 10963 switch (size) 10964 { 10965 case 8: return N_P8; 10966 case 16: return N_P16; 10967 default: ; 10968 } 10969 break; 10970 10971 case NT_signed: 10972 switch (size) 10973 { 10974 case 8: return N_S8; 10975 case 16: return N_S16; 10976 case 32: return N_S32; 10977 case 64: return N_S64; 10978 default: ; 10979 } 10980 break; 10981 10982 case NT_unsigned: 10983 switch (size) 10984 { 10985 case 8: return N_U8; 10986 case 16: return N_U16; 10987 case 32: return N_U32; 10988 case 64: return N_U64; 10989 default: ; 10990 } 10991 break; 10992 10993 default: ; 10994 } 10995 10996 return N_UTYP; 10997} 10998 10999/* Convert compact Neon bitmask type representation to a type and size. Only 11000 handles the case where a single bit is set in the mask. */ 11001 11002static int 11003el_type_of_type_chk (enum neon_el_type *type, unsigned *size, 11004 enum neon_type_mask mask) 11005{ 11006 if ((mask & N_EQK) != 0) 11007 return FAIL; 11008 11009 if ((mask & (N_S8 | N_U8 | N_I8 | N_8 | N_P8)) != 0) 11010 *size = 8; 11011 else if ((mask & (N_S16 | N_U16 | N_I16 | N_16 | N_P16)) != 0) 11012 *size = 16; 11013 else if ((mask & (N_S32 | N_U32 | N_I32 | N_32 | N_F32)) != 0) 11014 *size = 32; 11015 else if ((mask & (N_S64 | N_U64 | N_I64 | N_64 | N_F64)) != 0) 11016 *size = 64; 11017 else 11018 return FAIL; 11019 11020 if ((mask & (N_S8 | N_S16 | N_S32 | N_S64)) != 0) 11021 *type = NT_signed; 11022 else if ((mask & (N_U8 | N_U16 | N_U32 | N_U64)) != 0) 11023 *type = NT_unsigned; 11024 else if ((mask & (N_I8 | N_I16 | N_I32 | N_I64)) != 0) 11025 *type = NT_integer; 11026 else if ((mask & (N_8 | N_16 | N_32 | N_64)) != 0) 11027 *type = NT_untyped; 11028 else if ((mask & (N_P8 | N_P16)) != 0) 11029 *type = NT_poly; 11030 else if ((mask & (N_F32 | N_F64)) != 0) 11031 *type = NT_float; 11032 else 11033 return FAIL; 11034 11035 return SUCCESS; 11036} 11037 11038/* Modify a bitmask of allowed types. This is only needed for type 11039 relaxation. */ 11040 11041static unsigned 11042modify_types_allowed (unsigned allowed, unsigned mods) 11043{ 11044 unsigned size; 11045 enum neon_el_type type; 11046 unsigned destmask; 11047 int i; 11048 11049 destmask = 0; 11050 11051 for (i = 1; i <= N_MAX_NONSPECIAL; i <<= 1) 11052 { 11053 if (el_type_of_type_chk (&type, &size, allowed & i) == SUCCESS) 11054 { 11055 neon_modify_type_size (mods, &type, &size); 11056 destmask |= type_chk_of_el_type (type, size); 11057 } 11058 } 11059 11060 return destmask; 11061} 11062 11063/* Check type and return type classification. 11064 The manual states (paraphrase): If one datatype is given, it indicates the 11065 type given in: 11066 - the second operand, if there is one 11067 - the operand, if there is no second operand 11068 - the result, if there are no operands. 11069 This isn't quite good enough though, so we use a concept of a "key" datatype 11070 which is set on a per-instruction basis, which is the one which matters when 11071 only one data type is written. 11072 Note: this function has side-effects (e.g. filling in missing operands). All 11073 Neon instructions should call it before performing bit encoding. */ 11074 11075static struct neon_type_el 11076neon_check_type (unsigned els, enum neon_shape ns, ...) 11077{ 11078 va_list ap; 11079 unsigned i, pass, key_el = 0; 11080 unsigned types[NEON_MAX_TYPE_ELS]; 11081 enum neon_el_type k_type = NT_invtype; 11082 unsigned k_size = -1u; 11083 struct neon_type_el badtype = {NT_invtype, -1}; 11084 unsigned key_allowed = 0; 11085 11086 /* Optional registers in Neon instructions are always (not) in operand 1. 11087 Fill in the missing operand here, if it was omitted. */ 11088 if (els > 1 && !inst.operands[1].present) 11089 inst.operands[1] = inst.operands[0]; 11090 11091 /* Suck up all the varargs. */ 11092 va_start (ap, ns); 11093 for (i = 0; i < els; i++) 11094 { 11095 unsigned thisarg = va_arg (ap, unsigned); 11096 if (thisarg == N_IGNORE_TYPE) 11097 { 11098 va_end (ap); 11099 return badtype; 11100 } 11101 types[i] = thisarg; 11102 if ((thisarg & N_KEY) != 0) 11103 key_el = i; 11104 } 11105 va_end (ap); 11106 11107 if (inst.vectype.elems > 0) 11108 for (i = 0; i < els; i++) 11109 if (inst.operands[i].vectype.type != NT_invtype) 11110 { 11111 first_error (_("types specified in both the mnemonic and operands")); 11112 return badtype; 11113 } 11114 11115 /* Duplicate inst.vectype elements here as necessary. 11116 FIXME: No idea if this is exactly the same as the ARM assembler, 11117 particularly when an insn takes one register and one non-register 11118 operand. */ 11119 if (inst.vectype.elems == 1 && els > 1) 11120 { 11121 unsigned j; 11122 inst.vectype.elems = els; 11123 inst.vectype.el[key_el] = inst.vectype.el[0]; 11124 for (j = 0; j < els; j++) 11125 if (j != key_el) 11126 inst.vectype.el[j] = neon_type_promote (&inst.vectype.el[key_el], 11127 types[j]); 11128 } 11129 else if (inst.vectype.elems == 0 && els > 0) 11130 { 11131 unsigned j; 11132 /* No types were given after the mnemonic, so look for types specified 11133 after each operand. We allow some flexibility here; as long as the 11134 "key" operand has a type, we can infer the others. */ 11135 for (j = 0; j < els; j++) 11136 if (inst.operands[j].vectype.type != NT_invtype) 11137 inst.vectype.el[j] = inst.operands[j].vectype; 11138 11139 if (inst.operands[key_el].vectype.type != NT_invtype) 11140 { 11141 for (j = 0; j < els; j++) 11142 if (inst.operands[j].vectype.type == NT_invtype) 11143 inst.vectype.el[j] = neon_type_promote (&inst.vectype.el[key_el], 11144 types[j]); 11145 } 11146 else 11147 { 11148 first_error (_("operand types can't be inferred")); 11149 return badtype; 11150 } 11151 } 11152 else if (inst.vectype.elems != els) 11153 { 11154 first_error (_("type specifier has the wrong number of parts")); 11155 return badtype; 11156 } 11157 11158 for (pass = 0; pass < 2; pass++) 11159 { 11160 for (i = 0; i < els; i++) 11161 { 11162 unsigned thisarg = types[i]; 11163 unsigned types_allowed = ((thisarg & N_EQK) != 0 && pass != 0) 11164 ? modify_types_allowed (key_allowed, thisarg) : thisarg; 11165 enum neon_el_type g_type = inst.vectype.el[i].type; 11166 unsigned g_size = inst.vectype.el[i].size; 11167 11168 /* Decay more-specific signed & unsigned types to sign-insensitive 11169 integer types if sign-specific variants are unavailable. */ 11170 if ((g_type == NT_signed || g_type == NT_unsigned) 11171 && (types_allowed & N_SU_ALL) == 0) 11172 g_type = NT_integer; 11173 11174 /* If only untyped args are allowed, decay any more specific types to 11175 them. Some instructions only care about signs for some element 11176 sizes, so handle that properly. */ 11177 if ((g_size == 8 && (types_allowed & N_8) != 0) 11178 || (g_size == 16 && (types_allowed & N_16) != 0) 11179 || (g_size == 32 && (types_allowed & N_32) != 0) 11180 || (g_size == 64 && (types_allowed & N_64) != 0)) 11181 g_type = NT_untyped; 11182 11183 if (pass == 0) 11184 { 11185 if ((thisarg & N_KEY) != 0) 11186 { 11187 k_type = g_type; 11188 k_size = g_size; 11189 key_allowed = thisarg & ~N_KEY; 11190 } 11191 } 11192 else 11193 { 11194 if ((thisarg & N_VFP) != 0) 11195 { 11196 enum neon_shape_el regshape = neon_shape_tab[ns].el[i]; 11197 unsigned regwidth = neon_shape_el_size[regshape], match; 11198 11199 /* In VFP mode, operands must match register widths. If we 11200 have a key operand, use its width, else use the width of 11201 the current operand. */ 11202 if (k_size != -1u) 11203 match = k_size; 11204 else 11205 match = g_size; 11206 11207 if (regwidth != match) 11208 { 11209 first_error (_("operand size must match register width")); 11210 return badtype; 11211 } 11212 } 11213 11214 if ((thisarg & N_EQK) == 0) 11215 { 11216 unsigned given_type = type_chk_of_el_type (g_type, g_size); 11217 11218 if ((given_type & types_allowed) == 0) 11219 { 11220 first_error (_("bad type in Neon instruction")); 11221 return badtype; 11222 } 11223 } 11224 else 11225 { 11226 enum neon_el_type mod_k_type = k_type; 11227 unsigned mod_k_size = k_size; 11228 neon_modify_type_size (thisarg, &mod_k_type, &mod_k_size); 11229 if (g_type != mod_k_type || g_size != mod_k_size) 11230 { 11231 first_error (_("inconsistent types in Neon instruction")); 11232 return badtype; 11233 } 11234 } 11235 } 11236 } 11237 } 11238 11239 return inst.vectype.el[key_el]; 11240} 11241 11242/* Neon-style VFP instruction forwarding. */ 11243 11244/* Thumb VFP instructions have 0xE in the condition field. */ 11245 11246static void 11247do_vfp_cond_or_thumb (void) 11248{ 11249 if (thumb_mode) 11250 inst.instruction |= 0xe0000000; 11251 else 11252 inst.instruction |= inst.cond << 28; 11253} 11254 11255/* Look up and encode a simple mnemonic, for use as a helper function for the 11256 Neon-style VFP syntax. This avoids duplication of bits of the insns table, 11257 etc. It is assumed that operand parsing has already been done, and that the 11258 operands are in the form expected by the given opcode (this isn't necessarily 11259 the same as the form in which they were parsed, hence some massaging must 11260 take place before this function is called). 11261 Checks current arch version against that in the looked-up opcode. */ 11262 11263static void 11264do_vfp_nsyn_opcode (const char *opname) 11265{ 11266 const struct asm_opcode *opcode; 11267 11268 opcode = hash_find (arm_ops_hsh, opname); 11269 11270 if (!opcode) 11271 abort (); 11272 11273 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, 11274 thumb_mode ? *opcode->tvariant : *opcode->avariant), 11275 _(BAD_FPU)); 11276 11277 if (thumb_mode) 11278 { 11279 inst.instruction = opcode->tvalue; 11280 opcode->tencode (); 11281 } 11282 else 11283 { 11284 inst.instruction = (inst.cond << 28) | opcode->avalue; 11285 opcode->aencode (); 11286 } 11287} 11288 11289static void 11290do_vfp_nsyn_add_sub (enum neon_shape rs) 11291{ 11292 int is_add = (inst.instruction & 0x0fffffff) == N_MNEM_vadd; 11293 11294 if (rs == NS_FFF) 11295 { 11296 if (is_add) 11297 do_vfp_nsyn_opcode ("fadds"); 11298 else 11299 do_vfp_nsyn_opcode ("fsubs"); 11300 } 11301 else 11302 { 11303 if (is_add) 11304 do_vfp_nsyn_opcode ("faddd"); 11305 else 11306 do_vfp_nsyn_opcode ("fsubd"); 11307 } 11308} 11309 11310/* Check operand types to see if this is a VFP instruction, and if so call 11311 PFN (). */ 11312 11313static int 11314try_vfp_nsyn (int args, void (*pfn) (enum neon_shape)) 11315{ 11316 enum neon_shape rs; 11317 struct neon_type_el et; 11318 11319 switch (args) 11320 { 11321 case 2: 11322 rs = neon_select_shape (NS_FF, NS_DD, NS_NULL); 11323 et = neon_check_type (2, rs, 11324 N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP); 11325 break; 11326 11327 case 3: 11328 rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL); 11329 et = neon_check_type (3, rs, 11330 N_EQK | N_VFP, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP); 11331 break; 11332 11333 default: 11334 abort (); 11335 } 11336 11337 if (et.type != NT_invtype) 11338 { 11339 pfn (rs); 11340 return SUCCESS; 11341 } 11342 else 11343 inst.error = NULL; 11344 11345 return FAIL; 11346} 11347 11348static void 11349do_vfp_nsyn_mla_mls (enum neon_shape rs) 11350{ 11351 int is_mla = (inst.instruction & 0x0fffffff) == N_MNEM_vmla; 11352 11353 if (rs == NS_FFF) 11354 { 11355 if (is_mla) 11356 do_vfp_nsyn_opcode ("fmacs"); 11357 else 11358 do_vfp_nsyn_opcode ("fmscs"); 11359 } 11360 else 11361 { 11362 if (is_mla) 11363 do_vfp_nsyn_opcode ("fmacd"); 11364 else 11365 do_vfp_nsyn_opcode ("fmscd"); 11366 } 11367} 11368 11369static void 11370do_vfp_nsyn_mul (enum neon_shape rs) 11371{ 11372 if (rs == NS_FFF) 11373 do_vfp_nsyn_opcode ("fmuls"); 11374 else 11375 do_vfp_nsyn_opcode ("fmuld"); 11376} 11377 11378static void 11379do_vfp_nsyn_abs_neg (enum neon_shape rs) 11380{ 11381 int is_neg = (inst.instruction & 0x80) != 0; 11382 neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_VFP | N_KEY); 11383 11384 if (rs == NS_FF) 11385 { 11386 if (is_neg) 11387 do_vfp_nsyn_opcode ("fnegs"); 11388 else 11389 do_vfp_nsyn_opcode ("fabss"); 11390 } 11391 else 11392 { 11393 if (is_neg) 11394 do_vfp_nsyn_opcode ("fnegd"); 11395 else 11396 do_vfp_nsyn_opcode ("fabsd"); 11397 } 11398} 11399 11400/* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision 11401 insns belong to Neon, and are handled elsewhere. */ 11402 11403static void 11404do_vfp_nsyn_ldm_stm (int is_dbmode) 11405{ 11406 int is_ldm = (inst.instruction & (1 << 20)) != 0; 11407 if (is_ldm) 11408 { 11409 if (is_dbmode) 11410 do_vfp_nsyn_opcode ("fldmdbs"); 11411 else 11412 do_vfp_nsyn_opcode ("fldmias"); 11413 } 11414 else 11415 { 11416 if (is_dbmode) 11417 do_vfp_nsyn_opcode ("fstmdbs"); 11418 else 11419 do_vfp_nsyn_opcode ("fstmias"); 11420 } 11421} 11422 11423static void 11424do_vfp_nsyn_sqrt (void) 11425{ 11426 enum neon_shape rs = neon_select_shape (NS_FF, NS_DD, NS_NULL); 11427 neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP); 11428 11429 if (rs == NS_FF) 11430 do_vfp_nsyn_opcode ("fsqrts"); 11431 else 11432 do_vfp_nsyn_opcode ("fsqrtd"); 11433} 11434 11435static void 11436do_vfp_nsyn_div (void) 11437{ 11438 enum neon_shape rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL); 11439 neon_check_type (3, rs, N_EQK | N_VFP, N_EQK | N_VFP, 11440 N_F32 | N_F64 | N_KEY | N_VFP); 11441 11442 if (rs == NS_FFF) 11443 do_vfp_nsyn_opcode ("fdivs"); 11444 else 11445 do_vfp_nsyn_opcode ("fdivd"); 11446} 11447 11448static void 11449do_vfp_nsyn_nmul (void) 11450{ 11451 enum neon_shape rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL); 11452 neon_check_type (3, rs, N_EQK | N_VFP, N_EQK | N_VFP, 11453 N_F32 | N_F64 | N_KEY | N_VFP); 11454 11455 if (rs == NS_FFF) 11456 { 11457 inst.instruction = NEON_ENC_SINGLE (inst.instruction); 11458 do_vfp_sp_dyadic (); 11459 } 11460 else 11461 { 11462 inst.instruction = NEON_ENC_DOUBLE (inst.instruction); 11463 do_vfp_dp_rd_rn_rm (); 11464 } 11465 do_vfp_cond_or_thumb (); 11466} 11467 11468static void 11469do_vfp_nsyn_cmp (void) 11470{ 11471 if (inst.operands[1].isreg) 11472 { 11473 enum neon_shape rs = neon_select_shape (NS_FF, NS_DD, NS_NULL); 11474 neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP); 11475 11476 if (rs == NS_FF) 11477 { 11478 inst.instruction = NEON_ENC_SINGLE (inst.instruction); 11479 do_vfp_sp_monadic (); 11480 } 11481 else 11482 { 11483 inst.instruction = NEON_ENC_DOUBLE (inst.instruction); 11484 do_vfp_dp_rd_rm (); 11485 } 11486 } 11487 else 11488 { 11489 enum neon_shape rs = neon_select_shape (NS_FI, NS_DI, NS_NULL); 11490 neon_check_type (2, rs, N_F32 | N_F64 | N_KEY | N_VFP, N_EQK); 11491 11492 switch (inst.instruction & 0x0fffffff) 11493 { 11494 case N_MNEM_vcmp: 11495 inst.instruction += N_MNEM_vcmpz - N_MNEM_vcmp; 11496 break; 11497 case N_MNEM_vcmpe: 11498 inst.instruction += N_MNEM_vcmpez - N_MNEM_vcmpe; 11499 break; 11500 default: 11501 abort (); 11502 } 11503 11504 if (rs == NS_FI) 11505 { 11506 inst.instruction = NEON_ENC_SINGLE (inst.instruction); 11507 do_vfp_sp_compare_z (); 11508 } 11509 else 11510 { 11511 inst.instruction = NEON_ENC_DOUBLE (inst.instruction); 11512 do_vfp_dp_rd (); 11513 } 11514 } 11515 do_vfp_cond_or_thumb (); 11516} 11517 11518static void 11519nsyn_insert_sp (void) 11520{ 11521 inst.operands[1] = inst.operands[0]; 11522 memset (&inst.operands[0], '\0', sizeof (inst.operands[0])); 11523 inst.operands[0].reg = 13; 11524 inst.operands[0].isreg = 1; 11525 inst.operands[0].writeback = 1; 11526 inst.operands[0].present = 1; 11527} 11528 11529static void 11530do_vfp_nsyn_push (void) 11531{ 11532 nsyn_insert_sp (); 11533 if (inst.operands[1].issingle) 11534 do_vfp_nsyn_opcode ("fstmdbs"); 11535 else 11536 do_vfp_nsyn_opcode ("fstmdbd"); 11537} 11538 11539static void 11540do_vfp_nsyn_pop (void) 11541{ 11542 nsyn_insert_sp (); 11543 if (inst.operands[1].issingle) 11544 do_vfp_nsyn_opcode ("fldmias"); 11545 else 11546 do_vfp_nsyn_opcode ("fldmiad"); 11547} 11548 11549/* Fix up Neon data-processing instructions, ORing in the correct bits for 11550 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */ 11551 11552static unsigned 11553neon_dp_fixup (unsigned i) 11554{ 11555 if (thumb_mode) 11556 { 11557 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */ 11558 if (i & (1 << 24)) 11559 i |= 1 << 28; 11560 11561 i &= ~(1 << 24); 11562 11563 i |= 0xef000000; 11564 } 11565 else 11566 i |= 0xf2000000; 11567 11568 return i; 11569} 11570 11571/* Turn a size (8, 16, 32, 64) into the respective bit number minus 3 11572 (0, 1, 2, 3). */ 11573 11574static unsigned 11575neon_logbits (unsigned x) 11576{ 11577 return ffs (x) - 4; 11578} 11579 11580#define LOW4(R) ((R) & 0xf) 11581#define HI1(R) (((R) >> 4) & 1) 11582 11583/* Encode insns with bit pattern: 11584 11585 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0| 11586 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm | 11587 11588 SIZE is passed in bits. -1 means size field isn't changed, in case it has a 11589 different meaning for some instruction. */ 11590 11591static void 11592neon_three_same (int isquad, int ubit, int size) 11593{ 11594 inst.instruction |= LOW4 (inst.operands[0].reg) << 12; 11595 inst.instruction |= HI1 (inst.operands[0].reg) << 22; 11596 inst.instruction |= LOW4 (inst.operands[1].reg) << 16; 11597 inst.instruction |= HI1 (inst.operands[1].reg) << 7; 11598 inst.instruction |= LOW4 (inst.operands[2].reg); 11599 inst.instruction |= HI1 (inst.operands[2].reg) << 5; 11600 inst.instruction |= (isquad != 0) << 6; 11601 inst.instruction |= (ubit != 0) << 24; 11602 if (size != -1) 11603 inst.instruction |= neon_logbits (size) << 20; 11604 11605 inst.instruction = neon_dp_fixup (inst.instruction); 11606} 11607 11608/* Encode instructions of the form: 11609 11610 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0| 11611 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm | 11612 11613 Don't write size if SIZE == -1. */ 11614 11615static void 11616neon_two_same (int qbit, int ubit, int size) 11617{ 11618 inst.instruction |= LOW4 (inst.operands[0].reg) << 12; 11619 inst.instruction |= HI1 (inst.operands[0].reg) << 22; 11620 inst.instruction |= LOW4 (inst.operands[1].reg); 11621 inst.instruction |= HI1 (inst.operands[1].reg) << 5; 11622 inst.instruction |= (qbit != 0) << 6; 11623 inst.instruction |= (ubit != 0) << 24; 11624 11625 if (size != -1) 11626 inst.instruction |= neon_logbits (size) << 18; 11627 11628 inst.instruction = neon_dp_fixup (inst.instruction); 11629} 11630 11631/* Neon instruction encoders, in approximate order of appearance. */ 11632 11633static void 11634do_neon_dyadic_i_su (void) 11635{ 11636 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); 11637 struct neon_type_el et = neon_check_type (3, rs, 11638 N_EQK, N_EQK, N_SU_32 | N_KEY); 11639 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size); 11640} 11641 11642static void 11643do_neon_dyadic_i64_su (void) 11644{ 11645 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); 11646 struct neon_type_el et = neon_check_type (3, rs, 11647 N_EQK, N_EQK, N_SU_ALL | N_KEY); 11648 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size); 11649} 11650 11651static void 11652neon_imm_shift (int write_ubit, int uval, int isquad, struct neon_type_el et, 11653 unsigned immbits) 11654{ 11655 unsigned size = et.size >> 3; 11656 inst.instruction |= LOW4 (inst.operands[0].reg) << 12; 11657 inst.instruction |= HI1 (inst.operands[0].reg) << 22; 11658 inst.instruction |= LOW4 (inst.operands[1].reg); 11659 inst.instruction |= HI1 (inst.operands[1].reg) << 5; 11660 inst.instruction |= (isquad != 0) << 6; 11661 inst.instruction |= immbits << 16; 11662 inst.instruction |= (size >> 3) << 7; 11663 inst.instruction |= (size & 0x7) << 19; 11664 if (write_ubit) 11665 inst.instruction |= (uval != 0) << 24; 11666 11667 inst.instruction = neon_dp_fixup (inst.instruction); 11668} 11669 11670static void 11671do_neon_shl_imm (void) 11672{ 11673 if (!inst.operands[2].isreg) 11674 { 11675 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); 11676 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_KEY | N_I_ALL); 11677 inst.instruction = NEON_ENC_IMMED (inst.instruction); 11678 neon_imm_shift (FALSE, 0, neon_quad (rs), et, inst.operands[2].imm); 11679 } 11680 else 11681 { 11682 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); 11683 struct neon_type_el et = neon_check_type (3, rs, 11684 N_EQK, N_SU_ALL | N_KEY, N_EQK | N_SGN); 11685 unsigned int tmp; 11686 11687 /* VSHL/VQSHL 3-register variants have syntax such as: 11688 vshl.xx Dd, Dm, Dn 11689 whereas other 3-register operations encoded by neon_three_same have 11690 syntax like: 11691 vadd.xx Dd, Dn, Dm 11692 (i.e. with Dn & Dm reversed). Swap operands[1].reg and operands[2].reg 11693 here. */ 11694 tmp = inst.operands[2].reg; 11695 inst.operands[2].reg = inst.operands[1].reg; 11696 inst.operands[1].reg = tmp; 11697 inst.instruction = NEON_ENC_INTEGER (inst.instruction); 11698 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size); 11699 } 11700} 11701 11702static void 11703do_neon_qshl_imm (void) 11704{ 11705 if (!inst.operands[2].isreg) 11706 { 11707 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); 11708 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_ALL | N_KEY); 11709 11710 inst.instruction = NEON_ENC_IMMED (inst.instruction); 11711 neon_imm_shift (TRUE, et.type == NT_unsigned, neon_quad (rs), et, 11712 inst.operands[2].imm); 11713 } 11714 else 11715 { 11716 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); 11717 struct neon_type_el et = neon_check_type (3, rs, 11718 N_EQK, N_SU_ALL | N_KEY, N_EQK | N_SGN); 11719 unsigned int tmp; 11720 11721 /* See note in do_neon_shl_imm. */ 11722 tmp = inst.operands[2].reg; 11723 inst.operands[2].reg = inst.operands[1].reg; 11724 inst.operands[1].reg = tmp; 11725 inst.instruction = NEON_ENC_INTEGER (inst.instruction); 11726 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size); 11727 } 11728} 11729 11730static void 11731do_neon_rshl (void) 11732{ 11733 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); 11734 struct neon_type_el et = neon_check_type (3, rs, 11735 N_EQK, N_EQK, N_SU_ALL | N_KEY); 11736 unsigned int tmp; 11737 11738 tmp = inst.operands[2].reg; 11739 inst.operands[2].reg = inst.operands[1].reg; 11740 inst.operands[1].reg = tmp; 11741 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size); 11742} 11743 11744static int 11745neon_cmode_for_logic_imm (unsigned immediate, unsigned *immbits, int size) 11746{ 11747 /* Handle .I8 pseudo-instructions. */ 11748 if (size == 8) 11749 { 11750 /* Unfortunately, this will make everything apart from zero out-of-range. 11751 FIXME is this the intended semantics? There doesn't seem much point in 11752 accepting .I8 if so. */ 11753 immediate |= immediate << 8; 11754 size = 16; 11755 } 11756 11757 if (size >= 32) 11758 { 11759 if (immediate == (immediate & 0x000000ff)) 11760 { 11761 *immbits = immediate; 11762 return 0x1; 11763 } 11764 else if (immediate == (immediate & 0x0000ff00)) 11765 { 11766 *immbits = immediate >> 8; 11767 return 0x3; 11768 } 11769 else if (immediate == (immediate & 0x00ff0000)) 11770 { 11771 *immbits = immediate >> 16; 11772 return 0x5; 11773 } 11774 else if (immediate == (immediate & 0xff000000)) 11775 { 11776 *immbits = immediate >> 24; 11777 return 0x7; 11778 } 11779 if ((immediate & 0xffff) != (immediate >> 16)) 11780 goto bad_immediate; 11781 immediate &= 0xffff; 11782 } 11783 11784 if (immediate == (immediate & 0x000000ff)) 11785 { 11786 *immbits = immediate; 11787 return 0x9; 11788 } 11789 else if (immediate == (immediate & 0x0000ff00)) 11790 { 11791 *immbits = immediate >> 8; 11792 return 0xb; 11793 } 11794 11795 bad_immediate: 11796 first_error (_("immediate value out of range")); 11797 return FAIL; 11798} 11799 11800/* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits 11801 A, B, C, D. */ 11802 11803static int 11804neon_bits_same_in_bytes (unsigned imm) 11805{ 11806 return ((imm & 0x000000ff) == 0 || (imm & 0x000000ff) == 0x000000ff) 11807 && ((imm & 0x0000ff00) == 0 || (imm & 0x0000ff00) == 0x0000ff00) 11808 && ((imm & 0x00ff0000) == 0 || (imm & 0x00ff0000) == 0x00ff0000) 11809 && ((imm & 0xff000000) == 0 || (imm & 0xff000000) == 0xff000000); 11810} 11811 11812/* For immediate of above form, return 0bABCD. */ 11813 11814static unsigned 11815neon_squash_bits (unsigned imm) 11816{ 11817 return (imm & 0x01) | ((imm & 0x0100) >> 7) | ((imm & 0x010000) >> 14) 11818 | ((imm & 0x01000000) >> 21); 11819} 11820 11821/* Compress quarter-float representation to 0b...000 abcdefgh. */ 11822 11823static unsigned 11824neon_qfloat_bits (unsigned imm) 11825{ 11826 return ((imm >> 19) & 0x7f) | ((imm >> 24) & 0x80); 11827} 11828 11829/* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into 11830 the instruction. *OP is passed as the initial value of the op field, and 11831 may be set to a different value depending on the constant (i.e. 11832 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not 11833 MVN). If the immediate looks like a repeated parttern then also 11834 try smaller element sizes. */ 11835 11836static int 11837neon_cmode_for_move_imm (unsigned immlo, unsigned immhi, int float_p, 11838 unsigned *immbits, int *op, int size, 11839 enum neon_el_type type) 11840{ 11841 /* Only permit float immediates (including 0.0/-0.0) if the operand type is 11842 float. */ 11843 if (type == NT_float && !float_p) 11844 return FAIL; 11845 11846 if (type == NT_float && is_quarter_float (immlo) && immhi == 0) 11847 { 11848 if (size != 32 || *op == 1) 11849 return FAIL; 11850 *immbits = neon_qfloat_bits (immlo); 11851 return 0xf; 11852 } 11853 11854 if (size == 64) 11855 { 11856 if (neon_bits_same_in_bytes (immhi) 11857 && neon_bits_same_in_bytes (immlo)) 11858 { 11859 if (*op == 1) 11860 return FAIL; 11861 *immbits = (neon_squash_bits (immhi) << 4) 11862 | neon_squash_bits (immlo); 11863 *op = 1; 11864 return 0xe; 11865 } 11866 11867 if (immhi != immlo) 11868 return FAIL; 11869 } 11870 11871 if (size >= 32) 11872 { 11873 if (immlo == (immlo & 0x000000ff)) 11874 { 11875 *immbits = immlo; 11876 return 0x0; 11877 } 11878 else if (immlo == (immlo & 0x0000ff00)) 11879 { 11880 *immbits = immlo >> 8; 11881 return 0x2; 11882 } 11883 else if (immlo == (immlo & 0x00ff0000)) 11884 { 11885 *immbits = immlo >> 16; 11886 return 0x4; 11887 } 11888 else if (immlo == (immlo & 0xff000000)) 11889 { 11890 *immbits = immlo >> 24; 11891 return 0x6; 11892 } 11893 else if (immlo == ((immlo & 0x0000ff00) | 0x000000ff)) 11894 { 11895 *immbits = (immlo >> 8) & 0xff; 11896 return 0xc; 11897 } 11898 else if (immlo == ((immlo & 0x00ff0000) | 0x0000ffff)) 11899 { 11900 *immbits = (immlo >> 16) & 0xff; 11901 return 0xd; 11902 } 11903 11904 if ((immlo & 0xffff) != (immlo >> 16)) 11905 return FAIL; 11906 immlo &= 0xffff; 11907 } 11908 11909 if (size >= 16) 11910 { 11911 if (immlo == (immlo & 0x000000ff)) 11912 { 11913 *immbits = immlo; 11914 return 0x8; 11915 } 11916 else if (immlo == (immlo & 0x0000ff00)) 11917 { 11918 *immbits = immlo >> 8; 11919 return 0xa; 11920 } 11921 11922 if ((immlo & 0xff) != (immlo >> 8)) 11923 return FAIL; 11924 immlo &= 0xff; 11925 } 11926 11927 if (immlo == (immlo & 0x000000ff)) 11928 { 11929 /* Don't allow MVN with 8-bit immediate. */ 11930 if (*op == 1) 11931 return FAIL; 11932 *immbits = immlo; 11933 return 0xe; 11934 } 11935 11936 return FAIL; 11937} 11938 11939/* Write immediate bits [7:0] to the following locations: 11940 11941 |28/24|23 19|18 16|15 4|3 0| 11942 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h| 11943 11944 This function is used by VMOV/VMVN/VORR/VBIC. */ 11945 11946static void 11947neon_write_immbits (unsigned immbits) 11948{ 11949 inst.instruction |= immbits & 0xf; 11950 inst.instruction |= ((immbits >> 4) & 0x7) << 16; 11951 inst.instruction |= ((immbits >> 7) & 0x1) << 24; 11952} 11953 11954/* Invert low-order SIZE bits of XHI:XLO. */ 11955 11956static void 11957neon_invert_size (unsigned *xlo, unsigned *xhi, int size) 11958{ 11959 unsigned immlo = xlo ? *xlo : 0; 11960 unsigned immhi = xhi ? *xhi : 0; 11961 11962 switch (size) 11963 { 11964 case 8: 11965 immlo = (~immlo) & 0xff; 11966 break; 11967 11968 case 16: 11969 immlo = (~immlo) & 0xffff; 11970 break; 11971 11972 case 64: 11973 immhi = (~immhi) & 0xffffffff; 11974 /* fall through. */ 11975 11976 case 32: 11977 immlo = (~immlo) & 0xffffffff; 11978 break; 11979 11980 default: 11981 abort (); 11982 } 11983 11984 if (xlo) 11985 *xlo = immlo; 11986 11987 if (xhi) 11988 *xhi = immhi; 11989} 11990 11991static void 11992do_neon_logic (void) 11993{ 11994 if (inst.operands[2].present && inst.operands[2].isreg) 11995 { 11996 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); 11997 neon_check_type (3, rs, N_IGNORE_TYPE); 11998 /* U bit and size field were set as part of the bitmask. */ 11999 inst.instruction = NEON_ENC_INTEGER (inst.instruction); 12000 neon_three_same (neon_quad (rs), 0, -1); 12001 } 12002 else 12003 { 12004 enum neon_shape rs = neon_select_shape (NS_DI, NS_QI, NS_NULL); 12005 struct neon_type_el et = neon_check_type (2, rs, 12006 N_I8 | N_I16 | N_I32 | N_I64 | N_F32 | N_KEY, N_EQK); 12007 enum neon_opc opcode = inst.instruction & 0x0fffffff; 12008 unsigned immbits; 12009 int cmode; 12010 12011 if (et.type == NT_invtype) 12012 return; 12013 12014 inst.instruction = NEON_ENC_IMMED (inst.instruction); 12015 12016 immbits = inst.operands[1].imm; 12017 if (et.size == 64) 12018 { 12019 /* .i64 is a pseudo-op, so the immediate must be a repeating 12020 pattern. */ 12021 if (immbits != (inst.operands[1].regisimm ? 12022 inst.operands[1].reg : 0)) 12023 { 12024 /* Set immbits to an invalid constant. */ 12025 immbits = 0xdeadbeef; 12026 } 12027 } 12028 12029 switch (opcode) 12030 { 12031 case N_MNEM_vbic: 12032 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size); 12033 break; 12034 12035 case N_MNEM_vorr: 12036 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size); 12037 break; 12038 12039 case N_MNEM_vand: 12040 /* Pseudo-instruction for VBIC. */ 12041 neon_invert_size (&immbits, 0, et.size); 12042 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size); 12043 break; 12044 12045 case N_MNEM_vorn: 12046 /* Pseudo-instruction for VORR. */ 12047 neon_invert_size (&immbits, 0, et.size); 12048 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size); 12049 break; 12050 12051 default: 12052 abort (); 12053 } 12054 12055 if (cmode == FAIL) 12056 return; 12057 12058 inst.instruction |= neon_quad (rs) << 6; 12059 inst.instruction |= LOW4 (inst.operands[0].reg) << 12; 12060 inst.instruction |= HI1 (inst.operands[0].reg) << 22; 12061 inst.instruction |= cmode << 8; 12062 neon_write_immbits (immbits); 12063 12064 inst.instruction = neon_dp_fixup (inst.instruction); 12065 } 12066} 12067 12068static void 12069do_neon_bitfield (void) 12070{ 12071 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); 12072 neon_check_type (3, rs, N_IGNORE_TYPE); 12073 neon_three_same (neon_quad (rs), 0, -1); 12074} 12075 12076static void 12077neon_dyadic_misc (enum neon_el_type ubit_meaning, unsigned types, 12078 unsigned destbits) 12079{ 12080 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); 12081 struct neon_type_el et = neon_check_type (3, rs, N_EQK | destbits, N_EQK, 12082 types | N_KEY); 12083 if (et.type == NT_float) 12084 { 12085 inst.instruction = NEON_ENC_FLOAT (inst.instruction); 12086 neon_three_same (neon_quad (rs), 0, -1); 12087 } 12088 else 12089 { 12090 inst.instruction = NEON_ENC_INTEGER (inst.instruction); 12091 neon_three_same (neon_quad (rs), et.type == ubit_meaning, et.size); 12092 } 12093} 12094 12095static void 12096do_neon_dyadic_if_su (void) 12097{ 12098 neon_dyadic_misc (NT_unsigned, N_SUF_32, 0); 12099} 12100 12101static void 12102do_neon_dyadic_if_su_d (void) 12103{ 12104 /* This version only allow D registers, but that constraint is enforced during 12105 operand parsing so we don't need to do anything extra here. */ 12106 neon_dyadic_misc (NT_unsigned, N_SUF_32, 0); 12107} 12108 12109static void 12110do_neon_dyadic_if_i_d (void) 12111{ 12112 /* The "untyped" case can't happen. Do this to stop the "U" bit being 12113 affected if we specify unsigned args. */ 12114 neon_dyadic_misc (NT_untyped, N_IF_32, 0); 12115} 12116 12117enum vfp_or_neon_is_neon_bits 12118{ 12119 NEON_CHECK_CC = 1, 12120 NEON_CHECK_ARCH = 2 12121}; 12122 12123/* Call this function if an instruction which may have belonged to the VFP or 12124 Neon instruction sets, but turned out to be a Neon instruction (due to the 12125 operand types involved, etc.). We have to check and/or fix-up a couple of 12126 things: 12127 12128 - Make sure the user hasn't attempted to make a Neon instruction 12129 conditional. 12130 - Alter the value in the condition code field if necessary. 12131 - Make sure that the arch supports Neon instructions. 12132 12133 Which of these operations take place depends on bits from enum 12134 vfp_or_neon_is_neon_bits. 12135 12136 WARNING: This function has side effects! If NEON_CHECK_CC is used and the 12137 current instruction's condition is COND_ALWAYS, the condition field is 12138 changed to inst.uncond_value. This is necessary because instructions shared 12139 between VFP and Neon may be conditional for the VFP variants only, and the 12140 unconditional Neon version must have, e.g., 0xF in the condition field. */ 12141 12142static int 12143vfp_or_neon_is_neon (unsigned check) 12144{ 12145 /* Conditions are always legal in Thumb mode (IT blocks). */ 12146 if (!thumb_mode && (check & NEON_CHECK_CC)) 12147 { 12148 if (inst.cond != COND_ALWAYS) 12149 { 12150 first_error (_(BAD_COND)); 12151 return FAIL; 12152 } 12153 if (inst.uncond_value != -1) 12154 inst.instruction |= inst.uncond_value << 28; 12155 } 12156 12157 if ((check & NEON_CHECK_ARCH) 12158 && !ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1)) 12159 { 12160 first_error (_(BAD_FPU)); 12161 return FAIL; 12162 } 12163 12164 return SUCCESS; 12165} 12166 12167static void 12168do_neon_addsub_if_i (void) 12169{ 12170 if (try_vfp_nsyn (3, do_vfp_nsyn_add_sub) == SUCCESS) 12171 return; 12172 12173 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) 12174 return; 12175 12176 /* The "untyped" case can't happen. Do this to stop the "U" bit being 12177 affected if we specify unsigned args. */ 12178 neon_dyadic_misc (NT_untyped, N_IF_32 | N_I64, 0); 12179} 12180 12181/* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the 12182 result to be: 12183 V<op> A,B (A is operand 0, B is operand 2) 12184 to mean: 12185 V<op> A,B,A 12186 not: 12187 V<op> A,B,B 12188 so handle that case specially. */ 12189 12190static void 12191neon_exchange_operands (void) 12192{ 12193 void *scratch = alloca (sizeof (inst.operands[0])); 12194 if (inst.operands[1].present) 12195 { 12196 /* Swap operands[1] and operands[2]. */ 12197 memcpy (scratch, &inst.operands[1], sizeof (inst.operands[0])); 12198 inst.operands[1] = inst.operands[2]; 12199 memcpy (&inst.operands[2], scratch, sizeof (inst.operands[0])); 12200 } 12201 else 12202 { 12203 inst.operands[1] = inst.operands[2]; 12204 inst.operands[2] = inst.operands[0]; 12205 } 12206} 12207 12208static void 12209neon_compare (unsigned regtypes, unsigned immtypes, int invert) 12210{ 12211 if (inst.operands[2].isreg) 12212 { 12213 if (invert) 12214 neon_exchange_operands (); 12215 neon_dyadic_misc (NT_unsigned, regtypes, N_SIZ); 12216 } 12217 else 12218 { 12219 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); 12220 struct neon_type_el et = neon_check_type (2, rs, 12221 N_EQK | N_SIZ, immtypes | N_KEY); 12222 12223 inst.instruction = NEON_ENC_IMMED (inst.instruction); 12224 inst.instruction |= LOW4 (inst.operands[0].reg) << 12; 12225 inst.instruction |= HI1 (inst.operands[0].reg) << 22; 12226 inst.instruction |= LOW4 (inst.operands[1].reg); 12227 inst.instruction |= HI1 (inst.operands[1].reg) << 5; 12228 inst.instruction |= neon_quad (rs) << 6; 12229 inst.instruction |= (et.type == NT_float) << 10; 12230 inst.instruction |= neon_logbits (et.size) << 18; 12231 12232 inst.instruction = neon_dp_fixup (inst.instruction); 12233 } 12234} 12235 12236static void 12237do_neon_cmp (void) 12238{ 12239 neon_compare (N_SUF_32, N_S8 | N_S16 | N_S32 | N_F32, FALSE); 12240} 12241 12242static void 12243do_neon_cmp_inv (void) 12244{ 12245 neon_compare (N_SUF_32, N_S8 | N_S16 | N_S32 | N_F32, TRUE); 12246} 12247 12248static void 12249do_neon_ceq (void) 12250{ 12251 neon_compare (N_IF_32, N_IF_32, FALSE); 12252} 12253 12254/* For multiply instructions, we have the possibility of 16-bit or 32-bit 12255 scalars, which are encoded in 5 bits, M : Rm. 12256 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in 12257 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the 12258 index in M. */ 12259 12260static unsigned 12261neon_scalar_for_mul (unsigned scalar, unsigned elsize) 12262{ 12263 unsigned regno = NEON_SCALAR_REG (scalar); 12264 unsigned elno = NEON_SCALAR_INDEX (scalar); 12265 12266 switch (elsize) 12267 { 12268 case 16: 12269 if (regno > 7 || elno > 3) 12270 goto bad_scalar; 12271 return regno | (elno << 3); 12272 12273 case 32: 12274 if (regno > 15 || elno > 1) 12275 goto bad_scalar; 12276 return regno | (elno << 4); 12277 12278 default: 12279 bad_scalar: 12280 first_error (_("scalar out of range for multiply instruction")); 12281 } 12282 12283 return 0; 12284} 12285 12286/* Encode multiply / multiply-accumulate scalar instructions. */ 12287 12288static void 12289neon_mul_mac (struct neon_type_el et, int ubit) 12290{ 12291 unsigned scalar; 12292 12293 /* Give a more helpful error message if we have an invalid type. */ 12294 if (et.type == NT_invtype) 12295 return; 12296 12297 scalar = neon_scalar_for_mul (inst.operands[2].reg, et.size); 12298 inst.instruction |= LOW4 (inst.operands[0].reg) << 12; 12299 inst.instruction |= HI1 (inst.operands[0].reg) << 22; 12300 inst.instruction |= LOW4 (inst.operands[1].reg) << 16; 12301 inst.instruction |= HI1 (inst.operands[1].reg) << 7; 12302 inst.instruction |= LOW4 (scalar); 12303 inst.instruction |= HI1 (scalar) << 5; 12304 inst.instruction |= (et.type == NT_float) << 8; 12305 inst.instruction |= neon_logbits (et.size) << 20; 12306 inst.instruction |= (ubit != 0) << 24; 12307 12308 inst.instruction = neon_dp_fixup (inst.instruction); 12309} 12310 12311static void 12312do_neon_mac_maybe_scalar (void) 12313{ 12314 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls) == SUCCESS) 12315 return; 12316 12317 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) 12318 return; 12319 12320 if (inst.operands[2].isscalar) 12321 { 12322 enum neon_shape rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL); 12323 struct neon_type_el et = neon_check_type (3, rs, 12324 N_EQK, N_EQK, N_I16 | N_I32 | N_F32 | N_KEY); 12325 inst.instruction = NEON_ENC_SCALAR (inst.instruction); 12326 neon_mul_mac (et, neon_quad (rs)); 12327 } 12328 else 12329 { 12330 /* The "untyped" case can't happen. Do this to stop the "U" bit being 12331 affected if we specify unsigned args. */ 12332 neon_dyadic_misc (NT_untyped, N_IF_32, 0); 12333 } 12334} 12335 12336static void 12337do_neon_tst (void) 12338{ 12339 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); 12340 struct neon_type_el et = neon_check_type (3, rs, 12341 N_EQK, N_EQK, N_8 | N_16 | N_32 | N_KEY); 12342 neon_three_same (neon_quad (rs), 0, et.size); 12343} 12344 12345/* VMUL with 3 registers allows the P8 type. The scalar version supports the 12346 same types as the MAC equivalents. The polynomial type for this instruction 12347 is encoded the same as the integer type. */ 12348 12349static void 12350do_neon_mul (void) 12351{ 12352 if (try_vfp_nsyn (3, do_vfp_nsyn_mul) == SUCCESS) 12353 return; 12354 12355 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) 12356 return; 12357 12358 if (inst.operands[2].isscalar) 12359 do_neon_mac_maybe_scalar (); 12360 else 12361 neon_dyadic_misc (NT_poly, N_I8 | N_I16 | N_I32 | N_F32 | N_P8, 0); 12362} 12363 12364static void 12365do_neon_qdmulh (void) 12366{ 12367 if (inst.operands[2].isscalar) 12368 { 12369 enum neon_shape rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL); 12370 struct neon_type_el et = neon_check_type (3, rs, 12371 N_EQK, N_EQK, N_S16 | N_S32 | N_KEY); 12372 inst.instruction = NEON_ENC_SCALAR (inst.instruction); 12373 neon_mul_mac (et, neon_quad (rs)); 12374 } 12375 else 12376 { 12377 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); 12378 struct neon_type_el et = neon_check_type (3, rs, 12379 N_EQK, N_EQK, N_S16 | N_S32 | N_KEY); 12380 inst.instruction = NEON_ENC_INTEGER (inst.instruction); 12381 /* The U bit (rounding) comes from bit mask. */ 12382 neon_three_same (neon_quad (rs), 0, et.size); 12383 } 12384} 12385 12386static void 12387do_neon_fcmp_absolute (void) 12388{ 12389 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); 12390 neon_check_type (3, rs, N_EQK, N_EQK, N_F32 | N_KEY); 12391 /* Size field comes from bit mask. */ 12392 neon_three_same (neon_quad (rs), 1, -1); 12393} 12394 12395static void 12396do_neon_fcmp_absolute_inv (void) 12397{ 12398 neon_exchange_operands (); 12399 do_neon_fcmp_absolute (); 12400} 12401 12402static void 12403do_neon_step (void) 12404{ 12405 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); 12406 neon_check_type (3, rs, N_EQK, N_EQK, N_F32 | N_KEY); 12407 neon_three_same (neon_quad (rs), 0, -1); 12408} 12409 12410static void 12411do_neon_abs_neg (void) 12412{ 12413 enum neon_shape rs; 12414 struct neon_type_el et; 12415 12416 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg) == SUCCESS) 12417 return; 12418 12419 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) 12420 return; 12421 12422 rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); 12423 et = neon_check_type (2, rs, N_EQK, N_S8 | N_S16 | N_S32 | N_F32 | N_KEY); 12424 12425 inst.instruction |= LOW4 (inst.operands[0].reg) << 12; 12426 inst.instruction |= HI1 (inst.operands[0].reg) << 22; 12427 inst.instruction |= LOW4 (inst.operands[1].reg); 12428 inst.instruction |= HI1 (inst.operands[1].reg) << 5; 12429 inst.instruction |= neon_quad (rs) << 6; 12430 inst.instruction |= (et.type == NT_float) << 10; 12431 inst.instruction |= neon_logbits (et.size) << 18; 12432 12433 inst.instruction = neon_dp_fixup (inst.instruction); 12434} 12435 12436static void 12437do_neon_sli (void) 12438{ 12439 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); 12440 struct neon_type_el et = neon_check_type (2, rs, 12441 N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY); 12442 int imm = inst.operands[2].imm; 12443 constraint (imm < 0 || (unsigned)imm >= et.size, 12444 _("immediate out of range for insert")); 12445 neon_imm_shift (FALSE, 0, neon_quad (rs), et, imm); 12446} 12447 12448static void 12449do_neon_sri (void) 12450{ 12451 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); 12452 struct neon_type_el et = neon_check_type (2, rs, 12453 N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY); 12454 int imm = inst.operands[2].imm; 12455 constraint (imm < 1 || (unsigned)imm > et.size, 12456 _("immediate out of range for insert")); 12457 neon_imm_shift (FALSE, 0, neon_quad (rs), et, et.size - imm); 12458} 12459 12460static void 12461do_neon_qshlu_imm (void) 12462{ 12463 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); 12464 struct neon_type_el et = neon_check_type (2, rs, 12465 N_EQK | N_UNS, N_S8 | N_S16 | N_S32 | N_S64 | N_KEY); 12466 int imm = inst.operands[2].imm; 12467 constraint (imm < 0 || (unsigned)imm >= et.size, 12468 _("immediate out of range for shift")); 12469 /* Only encodes the 'U present' variant of the instruction. 12470 In this case, signed types have OP (bit 8) set to 0. 12471 Unsigned types have OP set to 1. */ 12472 inst.instruction |= (et.type == NT_unsigned) << 8; 12473 /* The rest of the bits are the same as other immediate shifts. */ 12474 neon_imm_shift (FALSE, 0, neon_quad (rs), et, imm); 12475} 12476 12477static void 12478do_neon_qmovn (void) 12479{ 12480 struct neon_type_el et = neon_check_type (2, NS_DQ, 12481 N_EQK | N_HLF, N_SU_16_64 | N_KEY); 12482 /* Saturating move where operands can be signed or unsigned, and the 12483 destination has the same signedness. */ 12484 inst.instruction = NEON_ENC_INTEGER (inst.instruction); 12485 if (et.type == NT_unsigned) 12486 inst.instruction |= 0xc0; 12487 else 12488 inst.instruction |= 0x80; 12489 neon_two_same (0, 1, et.size / 2); 12490} 12491 12492static void 12493do_neon_qmovun (void) 12494{ 12495 struct neon_type_el et = neon_check_type (2, NS_DQ, 12496 N_EQK | N_HLF | N_UNS, N_S16 | N_S32 | N_S64 | N_KEY); 12497 /* Saturating move with unsigned results. Operands must be signed. */ 12498 inst.instruction = NEON_ENC_INTEGER (inst.instruction); 12499 neon_two_same (0, 1, et.size / 2); 12500} 12501 12502static void 12503do_neon_rshift_sat_narrow (void) 12504{ 12505 /* FIXME: Types for narrowing. If operands are signed, results can be signed 12506 or unsigned. If operands are unsigned, results must also be unsigned. */ 12507 struct neon_type_el et = neon_check_type (2, NS_DQI, 12508 N_EQK | N_HLF, N_SU_16_64 | N_KEY); 12509 int imm = inst.operands[2].imm; 12510 /* This gets the bounds check, size encoding and immediate bits calculation 12511 right. */ 12512 et.size /= 2; 12513 12514 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for 12515 VQMOVN.I<size> <Dd>, <Qm>. */ 12516 if (imm == 0) 12517 { 12518 inst.operands[2].present = 0; 12519 inst.instruction = N_MNEM_vqmovn; 12520 do_neon_qmovn (); 12521 return; 12522 } 12523 12524 constraint (imm < 1 || (unsigned)imm > et.size, 12525 _("immediate out of range")); 12526 neon_imm_shift (TRUE, et.type == NT_unsigned, 0, et, et.size - imm); 12527} 12528 12529static void 12530do_neon_rshift_sat_narrow_u (void) 12531{ 12532 /* FIXME: Types for narrowing. If operands are signed, results can be signed 12533 or unsigned. If operands are unsigned, results must also be unsigned. */ 12534 struct neon_type_el et = neon_check_type (2, NS_DQI, 12535 N_EQK | N_HLF | N_UNS, N_S16 | N_S32 | N_S64 | N_KEY); 12536 int imm = inst.operands[2].imm; 12537 /* This gets the bounds check, size encoding and immediate bits calculation 12538 right. */ 12539 et.size /= 2; 12540 12541 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for 12542 VQMOVUN.I<size> <Dd>, <Qm>. */ 12543 if (imm == 0) 12544 { 12545 inst.operands[2].present = 0; 12546 inst.instruction = N_MNEM_vqmovun; 12547 do_neon_qmovun (); 12548 return; 12549 } 12550 12551 constraint (imm < 1 || (unsigned)imm > et.size, 12552 _("immediate out of range")); 12553 /* FIXME: The manual is kind of unclear about what value U should have in 12554 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it 12555 must be 1. */ 12556 neon_imm_shift (TRUE, 1, 0, et, et.size - imm); 12557} 12558 12559static void 12560do_neon_movn (void) 12561{ 12562 struct neon_type_el et = neon_check_type (2, NS_DQ, 12563 N_EQK | N_HLF, N_I16 | N_I32 | N_I64 | N_KEY); 12564 inst.instruction = NEON_ENC_INTEGER (inst.instruction); 12565 neon_two_same (0, 1, et.size / 2); 12566} 12567 12568static void 12569do_neon_rshift_narrow (void) 12570{ 12571 struct neon_type_el et = neon_check_type (2, NS_DQI, 12572 N_EQK | N_HLF, N_I16 | N_I32 | N_I64 | N_KEY); 12573 int imm = inst.operands[2].imm; 12574 /* This gets the bounds check, size encoding and immediate bits calculation 12575 right. */ 12576 et.size /= 2; 12577 12578 /* If immediate is zero then we are a pseudo-instruction for 12579 VMOVN.I<size> <Dd>, <Qm> */ 12580 if (imm == 0) 12581 { 12582 inst.operands[2].present = 0; 12583 inst.instruction = N_MNEM_vmovn; 12584 do_neon_movn (); 12585 return; 12586 } 12587 12588 constraint (imm < 1 || (unsigned)imm > et.size, 12589 _("immediate out of range for narrowing operation")); 12590 neon_imm_shift (FALSE, 0, 0, et, et.size - imm); 12591} 12592 12593static void 12594do_neon_shll (void) 12595{ 12596 /* FIXME: Type checking when lengthening. */ 12597 struct neon_type_el et = neon_check_type (2, NS_QDI, 12598 N_EQK | N_DBL, N_I8 | N_I16 | N_I32 | N_KEY); 12599 unsigned imm = inst.operands[2].imm; 12600 12601 if (imm == et.size) 12602 { 12603 /* Maximum shift variant. */ 12604 inst.instruction = NEON_ENC_INTEGER (inst.instruction); 12605 inst.instruction |= LOW4 (inst.operands[0].reg) << 12; 12606 inst.instruction |= HI1 (inst.operands[0].reg) << 22; 12607 inst.instruction |= LOW4 (inst.operands[1].reg); 12608 inst.instruction |= HI1 (inst.operands[1].reg) << 5; 12609 inst.instruction |= neon_logbits (et.size) << 18; 12610 12611 inst.instruction = neon_dp_fixup (inst.instruction); 12612 } 12613 else 12614 { 12615 /* A more-specific type check for non-max versions. */ 12616 et = neon_check_type (2, NS_QDI, 12617 N_EQK | N_DBL, N_SU_32 | N_KEY); 12618 inst.instruction = NEON_ENC_IMMED (inst.instruction); 12619 neon_imm_shift (TRUE, et.type == NT_unsigned, 0, et, imm); 12620 } 12621} 12622 12623/* Check the various types for the VCVT instruction, and return which version 12624 the current instruction is. */ 12625 12626static int 12627neon_cvt_flavour (enum neon_shape rs) 12628{ 12629#define CVT_VAR(C,X,Y) \ 12630 et = neon_check_type (2, rs, whole_reg | (X), whole_reg | (Y)); \ 12631 if (et.type != NT_invtype) \ 12632 { \ 12633 inst.error = NULL; \ 12634 return (C); \ 12635 } 12636 struct neon_type_el et; 12637 unsigned whole_reg = (rs == NS_FFI || rs == NS_FD || rs == NS_DF 12638 || rs == NS_FF) ? N_VFP : 0; 12639 /* The instruction versions which take an immediate take one register 12640 argument, which is extended to the width of the full register. Thus the 12641 "source" and "destination" registers must have the same width. Hack that 12642 here by making the size equal to the key (wider, in this case) operand. */ 12643 unsigned key = (rs == NS_QQI || rs == NS_DDI || rs == NS_FFI) ? N_KEY : 0; 12644 12645 CVT_VAR (0, N_S32, N_F32); 12646 CVT_VAR (1, N_U32, N_F32); 12647 CVT_VAR (2, N_F32, N_S32); 12648 CVT_VAR (3, N_F32, N_U32); 12649 12650 whole_reg = N_VFP; 12651 12652 /* VFP instructions. */ 12653 CVT_VAR (4, N_F32, N_F64); 12654 CVT_VAR (5, N_F64, N_F32); 12655 CVT_VAR (6, N_S32, N_F64 | key); 12656 CVT_VAR (7, N_U32, N_F64 | key); 12657 CVT_VAR (8, N_F64 | key, N_S32); 12658 CVT_VAR (9, N_F64 | key, N_U32); 12659 /* VFP instructions with bitshift. */ 12660 CVT_VAR (10, N_F32 | key, N_S16); 12661 CVT_VAR (11, N_F32 | key, N_U16); 12662 CVT_VAR (12, N_F64 | key, N_S16); 12663 CVT_VAR (13, N_F64 | key, N_U16); 12664 CVT_VAR (14, N_S16, N_F32 | key); 12665 CVT_VAR (15, N_U16, N_F32 | key); 12666 CVT_VAR (16, N_S16, N_F64 | key); 12667 CVT_VAR (17, N_U16, N_F64 | key); 12668 12669 return -1; 12670#undef CVT_VAR 12671} 12672 12673/* Neon-syntax VFP conversions. */ 12674 12675static void 12676do_vfp_nsyn_cvt (enum neon_shape rs, int flavour) 12677{ 12678 const char *opname = 0; 12679 12680 if (rs == NS_DDI || rs == NS_QQI || rs == NS_FFI) 12681 { 12682 /* Conversions with immediate bitshift. */ 12683 const char *enc[] = 12684 { 12685 "ftosls", 12686 "ftouls", 12687 "fsltos", 12688 "fultos", 12689 NULL, 12690 NULL, 12691 "ftosld", 12692 "ftould", 12693 "fsltod", 12694 "fultod", 12695 "fshtos", 12696 "fuhtos", 12697 "fshtod", 12698 "fuhtod", 12699 "ftoshs", 12700 "ftouhs", 12701 "ftoshd", 12702 "ftouhd" 12703 }; 12704 12705 if (flavour >= 0 && flavour < (int) ARRAY_SIZE (enc)) 12706 { 12707 opname = enc[flavour]; 12708 constraint (inst.operands[0].reg != inst.operands[1].reg, 12709 _("operands 0 and 1 must be the same register")); 12710 inst.operands[1] = inst.operands[2]; 12711 memset (&inst.operands[2], '\0', sizeof (inst.operands[2])); 12712 } 12713 } 12714 else 12715 { 12716 /* Conversions without bitshift. */ 12717 const char *enc[] = 12718 { 12719 "ftosizs", 12720 "ftouizs", 12721 "fsitos", 12722 "fuitos", 12723 "fcvtsd", 12724 "fcvtds", 12725 "ftosizd", 12726 "ftouizd", 12727 "fsitod", 12728 "fuitod" 12729 }; 12730 12731 if (flavour >= 0 && flavour < (int) ARRAY_SIZE (enc)) 12732 opname = enc[flavour]; 12733 } 12734 12735 if (opname) 12736 do_vfp_nsyn_opcode (opname); 12737} 12738 12739static void 12740do_vfp_nsyn_cvtz (void) 12741{ 12742 enum neon_shape rs = neon_select_shape (NS_FF, NS_FD, NS_NULL); 12743 int flavour = neon_cvt_flavour (rs); 12744 const char *enc[] = 12745 { 12746 "ftosizs", 12747 "ftouizs", 12748 NULL, 12749 NULL, 12750 NULL, 12751 NULL, 12752 "ftosizd", 12753 "ftouizd" 12754 }; 12755 12756 if (flavour >= 0 && flavour < (int) ARRAY_SIZE (enc) && enc[flavour]) 12757 do_vfp_nsyn_opcode (enc[flavour]); 12758} 12759 12760static void 12761do_neon_cvt (void) 12762{ 12763 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_FFI, NS_DD, NS_QQ, 12764 NS_FD, NS_DF, NS_FF, NS_NULL); 12765 int flavour = neon_cvt_flavour (rs); 12766 12767 /* VFP rather than Neon conversions. */ 12768 if (flavour >= 4) 12769 { 12770 do_vfp_nsyn_cvt (rs, flavour); 12771 return; 12772 } 12773 12774 switch (rs) 12775 { 12776 case NS_DDI: 12777 case NS_QQI: 12778 { 12779 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) 12780 return; 12781 12782 /* Fixed-point conversion with #0 immediate is encoded as an 12783 integer conversion. */ 12784 if (inst.operands[2].present && inst.operands[2].imm == 0) 12785 goto int_encode; 12786 unsigned immbits = 32 - inst.operands[2].imm; 12787 unsigned enctab[] = { 0x0000100, 0x1000100, 0x0, 0x1000000 }; 12788 inst.instruction = NEON_ENC_IMMED (inst.instruction); 12789 if (flavour != -1) 12790 inst.instruction |= enctab[flavour]; 12791 inst.instruction |= LOW4 (inst.operands[0].reg) << 12; 12792 inst.instruction |= HI1 (inst.operands[0].reg) << 22; 12793 inst.instruction |= LOW4 (inst.operands[1].reg); 12794 inst.instruction |= HI1 (inst.operands[1].reg) << 5; 12795 inst.instruction |= neon_quad (rs) << 6; 12796 inst.instruction |= 1 << 21; 12797 inst.instruction |= immbits << 16; 12798 12799 inst.instruction = neon_dp_fixup (inst.instruction); 12800 } 12801 break; 12802 12803 case NS_DD: 12804 case NS_QQ: 12805 int_encode: 12806 { 12807 unsigned enctab[] = { 0x100, 0x180, 0x0, 0x080 }; 12808 12809 inst.instruction = NEON_ENC_INTEGER (inst.instruction); 12810 12811 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) 12812 return; 12813 12814 if (flavour != -1) 12815 inst.instruction |= enctab[flavour]; 12816 12817 inst.instruction |= LOW4 (inst.operands[0].reg) << 12; 12818 inst.instruction |= HI1 (inst.operands[0].reg) << 22; 12819 inst.instruction |= LOW4 (inst.operands[1].reg); 12820 inst.instruction |= HI1 (inst.operands[1].reg) << 5; 12821 inst.instruction |= neon_quad (rs) << 6; 12822 inst.instruction |= 2 << 18; 12823 12824 inst.instruction = neon_dp_fixup (inst.instruction); 12825 } 12826 break; 12827 12828 default: 12829 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */ 12830 do_vfp_nsyn_cvt (rs, flavour); 12831 } 12832} 12833 12834static void 12835neon_move_immediate (void) 12836{ 12837 enum neon_shape rs = neon_select_shape (NS_DI, NS_QI, NS_NULL); 12838 struct neon_type_el et = neon_check_type (2, rs, 12839 N_I8 | N_I16 | N_I32 | N_I64 | N_F32 | N_KEY, N_EQK); 12840 unsigned immlo, immhi = 0, immbits; 12841 int op, cmode, float_p; 12842 12843 constraint (et.type == NT_invtype, 12844 _("operand size must be specified for immediate VMOV")); 12845 12846 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */ 12847 op = (inst.instruction & (1 << 5)) != 0; 12848 12849 immlo = inst.operands[1].imm; 12850 if (inst.operands[1].regisimm) 12851 immhi = inst.operands[1].reg; 12852 12853 constraint (et.size < 32 && (immlo & ~((1 << et.size) - 1)) != 0, 12854 _("immediate has bits set outside the operand size")); 12855 12856 float_p = inst.operands[1].immisfloat; 12857 12858 if ((cmode = neon_cmode_for_move_imm (immlo, immhi, float_p, &immbits, &op, 12859 et.size, et.type)) == FAIL) 12860 { 12861 /* Invert relevant bits only. */ 12862 neon_invert_size (&immlo, &immhi, et.size); 12863 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable 12864 with one or the other; those cases are caught by 12865 neon_cmode_for_move_imm. */ 12866 op = !op; 12867 if ((cmode = neon_cmode_for_move_imm (immlo, immhi, float_p, &immbits, 12868 &op, et.size, et.type)) == FAIL) 12869 { 12870 first_error (_("immediate out of range")); 12871 return; 12872 } 12873 } 12874 12875 inst.instruction &= ~(1 << 5); 12876 inst.instruction |= op << 5; 12877 12878 inst.instruction |= LOW4 (inst.operands[0].reg) << 12; 12879 inst.instruction |= HI1 (inst.operands[0].reg) << 22; 12880 inst.instruction |= neon_quad (rs) << 6; 12881 inst.instruction |= cmode << 8; 12882 12883 neon_write_immbits (immbits); 12884} 12885 12886static void 12887do_neon_mvn (void) 12888{ 12889 if (inst.operands[1].isreg) 12890 { 12891 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); 12892 12893 inst.instruction = NEON_ENC_INTEGER (inst.instruction); 12894 inst.instruction |= LOW4 (inst.operands[0].reg) << 12; 12895 inst.instruction |= HI1 (inst.operands[0].reg) << 22; 12896 inst.instruction |= LOW4 (inst.operands[1].reg); 12897 inst.instruction |= HI1 (inst.operands[1].reg) << 5; 12898 inst.instruction |= neon_quad (rs) << 6; 12899 } 12900 else 12901 { 12902 inst.instruction = NEON_ENC_IMMED (inst.instruction); 12903 neon_move_immediate (); 12904 } 12905 12906 inst.instruction = neon_dp_fixup (inst.instruction); 12907} 12908 12909/* Encode instructions of form: 12910 12911 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0| 12912 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | 12913 12914*/ 12915 12916static void 12917neon_mixed_length (struct neon_type_el et, unsigned size) 12918{ 12919 inst.instruction |= LOW4 (inst.operands[0].reg) << 12; 12920 inst.instruction |= HI1 (inst.operands[0].reg) << 22; 12921 inst.instruction |= LOW4 (inst.operands[1].reg) << 16; 12922 inst.instruction |= HI1 (inst.operands[1].reg) << 7; 12923 inst.instruction |= LOW4 (inst.operands[2].reg); 12924 inst.instruction |= HI1 (inst.operands[2].reg) << 5; 12925 inst.instruction |= (et.type == NT_unsigned) << 24; 12926 inst.instruction |= neon_logbits (size) << 20; 12927 12928 inst.instruction = neon_dp_fixup (inst.instruction); 12929} 12930 12931static void 12932do_neon_dyadic_long (void) 12933{ 12934 /* FIXME: Type checking for lengthening op. */ 12935 struct neon_type_el et = neon_check_type (3, NS_QDD, 12936 N_EQK | N_DBL, N_EQK, N_SU_32 | N_KEY); 12937 neon_mixed_length (et, et.size); 12938} 12939 12940static void 12941do_neon_abal (void) 12942{ 12943 struct neon_type_el et = neon_check_type (3, NS_QDD, 12944 N_EQK | N_INT | N_DBL, N_EQK, N_SU_32 | N_KEY); 12945 neon_mixed_length (et, et.size); 12946} 12947 12948static void 12949neon_mac_reg_scalar_long (unsigned regtypes, unsigned scalartypes) 12950{ 12951 if (inst.operands[2].isscalar) 12952 { 12953 struct neon_type_el et = neon_check_type (3, NS_QDS, 12954 N_EQK | N_DBL, N_EQK, regtypes | N_KEY); 12955 inst.instruction = NEON_ENC_SCALAR (inst.instruction); 12956 neon_mul_mac (et, et.type == NT_unsigned); 12957 } 12958 else 12959 { 12960 struct neon_type_el et = neon_check_type (3, NS_QDD, 12961 N_EQK | N_DBL, N_EQK, scalartypes | N_KEY); 12962 inst.instruction = NEON_ENC_INTEGER (inst.instruction); 12963 neon_mixed_length (et, et.size); 12964 } 12965} 12966 12967static void 12968do_neon_mac_maybe_scalar_long (void) 12969{ 12970 neon_mac_reg_scalar_long (N_S16 | N_S32 | N_U16 | N_U32, N_SU_32); 12971} 12972 12973static void 12974do_neon_dyadic_wide (void) 12975{ 12976 struct neon_type_el et = neon_check_type (3, NS_QQD, 12977 N_EQK | N_DBL, N_EQK | N_DBL, N_SU_32 | N_KEY); 12978 neon_mixed_length (et, et.size); 12979} 12980 12981static void 12982do_neon_dyadic_narrow (void) 12983{ 12984 struct neon_type_el et = neon_check_type (3, NS_QDD, 12985 N_EQK | N_DBL, N_EQK, N_I16 | N_I32 | N_I64 | N_KEY); 12986 /* Operand sign is unimportant, and the U bit is part of the opcode, 12987 so force the operand type to integer. */ 12988 et.type = NT_integer; 12989 neon_mixed_length (et, et.size / 2); 12990} 12991 12992static void 12993do_neon_mul_sat_scalar_long (void) 12994{ 12995 neon_mac_reg_scalar_long (N_S16 | N_S32, N_S16 | N_S32); 12996} 12997 12998static void 12999do_neon_vmull (void) 13000{ 13001 if (inst.operands[2].isscalar) 13002 do_neon_mac_maybe_scalar_long (); 13003 else 13004 { 13005 struct neon_type_el et = neon_check_type (3, NS_QDD, 13006 N_EQK | N_DBL, N_EQK, N_SU_32 | N_P8 | N_KEY); 13007 if (et.type == NT_poly) 13008 inst.instruction = NEON_ENC_POLY (inst.instruction); 13009 else 13010 inst.instruction = NEON_ENC_INTEGER (inst.instruction); 13011 /* For polynomial encoding, size field must be 0b00 and the U bit must be 13012 zero. Should be OK as-is. */ 13013 neon_mixed_length (et, et.size); 13014 } 13015} 13016 13017static void 13018do_neon_ext (void) 13019{ 13020 enum neon_shape rs = neon_select_shape (NS_DDDI, NS_QQQI, NS_NULL); 13021 struct neon_type_el et = neon_check_type (3, rs, 13022 N_EQK, N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY); 13023 unsigned imm = (inst.operands[3].imm * et.size) / 8; 13024 constraint (imm >= (neon_quad (rs) ? 16 : 8), _("shift out of range")); 13025 inst.instruction |= LOW4 (inst.operands[0].reg) << 12; 13026 inst.instruction |= HI1 (inst.operands[0].reg) << 22; 13027 inst.instruction |= LOW4 (inst.operands[1].reg) << 16; 13028 inst.instruction |= HI1 (inst.operands[1].reg) << 7; 13029 inst.instruction |= LOW4 (inst.operands[2].reg); 13030 inst.instruction |= HI1 (inst.operands[2].reg) << 5; 13031 inst.instruction |= neon_quad (rs) << 6; 13032 inst.instruction |= imm << 8; 13033 13034 inst.instruction = neon_dp_fixup (inst.instruction); 13035} 13036 13037static void 13038do_neon_rev (void) 13039{ 13040 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); 13041 struct neon_type_el et = neon_check_type (2, rs, 13042 N_EQK, N_8 | N_16 | N_32 | N_KEY); 13043 unsigned op = (inst.instruction >> 7) & 3; 13044 /* N (width of reversed regions) is encoded as part of the bitmask. We 13045 extract it here to check the elements to be reversed are smaller. 13046 Otherwise we'd get a reserved instruction. */ 13047 unsigned elsize = (op == 2) ? 16 : (op == 1) ? 32 : (op == 0) ? 64 : 0; 13048 assert (elsize != 0); 13049 constraint (et.size >= elsize, 13050 _("elements must be smaller than reversal region")); 13051 neon_two_same (neon_quad (rs), 1, et.size); 13052} 13053 13054static void 13055do_neon_dup (void) 13056{ 13057 if (inst.operands[1].isscalar) 13058 { 13059 enum neon_shape rs = neon_select_shape (NS_DS, NS_QS, NS_NULL); 13060 struct neon_type_el et = neon_check_type (2, rs, 13061 N_EQK, N_8 | N_16 | N_32 | N_KEY); 13062 unsigned sizebits = et.size >> 3; 13063 unsigned dm = NEON_SCALAR_REG (inst.operands[1].reg); 13064 int logsize = neon_logbits (et.size); 13065 unsigned x = NEON_SCALAR_INDEX (inst.operands[1].reg) << logsize; 13066 13067 if (vfp_or_neon_is_neon (NEON_CHECK_CC) == FAIL) 13068 return; 13069 13070 inst.instruction = NEON_ENC_SCALAR (inst.instruction); 13071 inst.instruction |= LOW4 (inst.operands[0].reg) << 12; 13072 inst.instruction |= HI1 (inst.operands[0].reg) << 22; 13073 inst.instruction |= LOW4 (dm); 13074 inst.instruction |= HI1 (dm) << 5; 13075 inst.instruction |= neon_quad (rs) << 6; 13076 inst.instruction |= x << 17; 13077 inst.instruction |= sizebits << 16; 13078 13079 inst.instruction = neon_dp_fixup (inst.instruction); 13080 } 13081 else 13082 { 13083 enum neon_shape rs = neon_select_shape (NS_DR, NS_QR, NS_NULL); 13084 struct neon_type_el et = neon_check_type (2, rs, 13085 N_8 | N_16 | N_32 | N_KEY, N_EQK); 13086 /* Duplicate ARM register to lanes of vector. */ 13087 inst.instruction = NEON_ENC_ARMREG (inst.instruction); 13088 switch (et.size) 13089 { 13090 case 8: inst.instruction |= 0x400000; break; 13091 case 16: inst.instruction |= 0x000020; break; 13092 case 32: inst.instruction |= 0x000000; break; 13093 default: break; 13094 } 13095 inst.instruction |= LOW4 (inst.operands[1].reg) << 12; 13096 inst.instruction |= LOW4 (inst.operands[0].reg) << 16; 13097 inst.instruction |= HI1 (inst.operands[0].reg) << 7; 13098 inst.instruction |= neon_quad (rs) << 21; 13099 /* The encoding for this instruction is identical for the ARM and Thumb 13100 variants, except for the condition field. */ 13101 do_vfp_cond_or_thumb (); 13102 } 13103} 13104 13105/* VMOV has particularly many variations. It can be one of: 13106 0. VMOV<c><q> <Qd>, <Qm> 13107 1. VMOV<c><q> <Dd>, <Dm> 13108 (Register operations, which are VORR with Rm = Rn.) 13109 2. VMOV<c><q>.<dt> <Qd>, #<imm> 13110 3. VMOV<c><q>.<dt> <Dd>, #<imm> 13111 (Immediate loads.) 13112 4. VMOV<c><q>.<size> <Dn[x]>, <Rd> 13113 (ARM register to scalar.) 13114 5. VMOV<c><q> <Dm>, <Rd>, <Rn> 13115 (Two ARM registers to vector.) 13116 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]> 13117 (Scalar to ARM register.) 13118 7. VMOV<c><q> <Rd>, <Rn>, <Dm> 13119 (Vector to two ARM registers.) 13120 8. VMOV.F32 <Sd>, <Sm> 13121 9. VMOV.F64 <Dd>, <Dm> 13122 (VFP register moves.) 13123 10. VMOV.F32 <Sd>, #imm 13124 11. VMOV.F64 <Dd>, #imm 13125 (VFP float immediate load.) 13126 12. VMOV <Rd>, <Sm> 13127 (VFP single to ARM reg.) 13128 13. VMOV <Sd>, <Rm> 13129 (ARM reg to VFP single.) 13130 14. VMOV <Rd>, <Re>, <Sn>, <Sm> 13131 (Two ARM regs to two VFP singles.) 13132 15. VMOV <Sd>, <Se>, <Rn>, <Rm> 13133 (Two VFP singles to two ARM regs.) 13134 13135 These cases can be disambiguated using neon_select_shape, except cases 1/9 13136 and 3/11 which depend on the operand type too. 13137 13138 All the encoded bits are hardcoded by this function. 13139 13140 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!). 13141 Cases 5, 7 may be used with VFPv2 and above. 13142 13143 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you 13144 can specify a type where it doesn't make sense to, and is ignored). 13145*/ 13146 13147static void 13148do_neon_mov (void) 13149{ 13150 enum neon_shape rs = neon_select_shape (NS_RRFF, NS_FFRR, NS_DRR, NS_RRD, 13151 NS_QQ, NS_DD, NS_QI, NS_DI, NS_SR, NS_RS, NS_FF, NS_FI, NS_RF, NS_FR, 13152 NS_NULL); 13153 struct neon_type_el et; 13154 const char *ldconst = 0; 13155 13156 switch (rs) 13157 { 13158 case NS_DD: /* case 1/9. */ 13159 et = neon_check_type (2, rs, N_EQK, N_F64 | N_KEY); 13160 /* It is not an error here if no type is given. */ 13161 inst.error = NULL; 13162 if (et.type == NT_float && et.size == 64) 13163 { 13164 do_vfp_nsyn_opcode ("fcpyd"); 13165 break; 13166 } 13167 /* fall through. */ 13168 13169 case NS_QQ: /* case 0/1. */ 13170 { 13171 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) 13172 return; 13173 /* The architecture manual I have doesn't explicitly state which 13174 value the U bit should have for register->register moves, but 13175 the equivalent VORR instruction has U = 0, so do that. */ 13176 inst.instruction = 0x0200110; 13177 inst.instruction |= LOW4 (inst.operands[0].reg) << 12; 13178 inst.instruction |= HI1 (inst.operands[0].reg) << 22; 13179 inst.instruction |= LOW4 (inst.operands[1].reg); 13180 inst.instruction |= HI1 (inst.operands[1].reg) << 5; 13181 inst.instruction |= LOW4 (inst.operands[1].reg) << 16; 13182 inst.instruction |= HI1 (inst.operands[1].reg) << 7; 13183 inst.instruction |= neon_quad (rs) << 6; 13184 13185 inst.instruction = neon_dp_fixup (inst.instruction); 13186 } 13187 break; 13188 13189 case NS_DI: /* case 3/11. */ 13190 et = neon_check_type (2, rs, N_EQK, N_F64 | N_KEY); 13191 inst.error = NULL; 13192 if (et.type == NT_float && et.size == 64) 13193 { 13194 /* case 11 (fconstd). */ 13195 ldconst = "fconstd"; 13196 goto encode_fconstd; 13197 } 13198 /* fall through. */ 13199 13200 case NS_QI: /* case 2/3. */ 13201 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) 13202 return; 13203 inst.instruction = 0x0800010; 13204 neon_move_immediate (); 13205 inst.instruction = neon_dp_fixup (inst.instruction); 13206 break; 13207 13208 case NS_SR: /* case 4. */ 13209 { 13210 unsigned bcdebits = 0; 13211 struct neon_type_el et = neon_check_type (2, NS_NULL, 13212 N_8 | N_16 | N_32 | N_KEY, N_EQK); 13213 int logsize = neon_logbits (et.size); 13214 unsigned dn = NEON_SCALAR_REG (inst.operands[0].reg); 13215 unsigned x = NEON_SCALAR_INDEX (inst.operands[0].reg); 13216 13217 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1), 13218 _(BAD_FPU)); 13219 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1) 13220 && et.size != 32, _(BAD_FPU)); 13221 constraint (et.type == NT_invtype, _("bad type for scalar")); 13222 constraint (x >= 64 / et.size, _("scalar index out of range")); 13223 13224 switch (et.size) 13225 { 13226 case 8: bcdebits = 0x8; break; 13227 case 16: bcdebits = 0x1; break; 13228 case 32: bcdebits = 0x0; break; 13229 default: ; 13230 } 13231 13232 bcdebits |= x << logsize; 13233 13234 inst.instruction = 0xe000b10; 13235 do_vfp_cond_or_thumb (); 13236 inst.instruction |= LOW4 (dn) << 16; 13237 inst.instruction |= HI1 (dn) << 7; 13238 inst.instruction |= inst.operands[1].reg << 12; 13239 inst.instruction |= (bcdebits & 3) << 5; 13240 inst.instruction |= (bcdebits >> 2) << 21; 13241 } 13242 break; 13243 13244 case NS_DRR: /* case 5 (fmdrr). */ 13245 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2), 13246 _(BAD_FPU)); 13247 13248 inst.instruction = 0xc400b10; 13249 do_vfp_cond_or_thumb (); 13250 inst.instruction |= LOW4 (inst.operands[0].reg); 13251 inst.instruction |= HI1 (inst.operands[0].reg) << 5; 13252 inst.instruction |= inst.operands[1].reg << 12; 13253 inst.instruction |= inst.operands[2].reg << 16; 13254 break; 13255 13256 case NS_RS: /* case 6. */ 13257 { 13258 struct neon_type_el et = neon_check_type (2, NS_NULL, 13259 N_EQK, N_S8 | N_S16 | N_U8 | N_U16 | N_32 | N_KEY); 13260 unsigned logsize = neon_logbits (et.size); 13261 unsigned dn = NEON_SCALAR_REG (inst.operands[1].reg); 13262 unsigned x = NEON_SCALAR_INDEX (inst.operands[1].reg); 13263 unsigned abcdebits = 0; 13264 13265 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1), 13266 _(BAD_FPU)); 13267 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1) 13268 && et.size != 32, _(BAD_FPU)); 13269 constraint (et.type == NT_invtype, _("bad type for scalar")); 13270 constraint (x >= 64 / et.size, _("scalar index out of range")); 13271 13272 switch (et.size) 13273 { 13274 case 8: abcdebits = (et.type == NT_signed) ? 0x08 : 0x18; break; 13275 case 16: abcdebits = (et.type == NT_signed) ? 0x01 : 0x11; break; 13276 case 32: abcdebits = 0x00; break; 13277 default: ; 13278 } 13279 13280 abcdebits |= x << logsize; 13281 inst.instruction = 0xe100b10; 13282 do_vfp_cond_or_thumb (); 13283 inst.instruction |= LOW4 (dn) << 16; 13284 inst.instruction |= HI1 (dn) << 7; 13285 inst.instruction |= inst.operands[0].reg << 12; 13286 inst.instruction |= (abcdebits & 3) << 5; 13287 inst.instruction |= (abcdebits >> 2) << 21; 13288 } 13289 break; 13290 13291 case NS_RRD: /* case 7 (fmrrd). */ 13292 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2), 13293 _(BAD_FPU)); 13294 13295 inst.instruction = 0xc500b10; 13296 do_vfp_cond_or_thumb (); 13297 inst.instruction |= inst.operands[0].reg << 12; 13298 inst.instruction |= inst.operands[1].reg << 16; 13299 inst.instruction |= LOW4 (inst.operands[2].reg); 13300 inst.instruction |= HI1 (inst.operands[2].reg) << 5; 13301 break; 13302 13303 case NS_FF: /* case 8 (fcpys). */ 13304 do_vfp_nsyn_opcode ("fcpys"); 13305 break; 13306 13307 case NS_FI: /* case 10 (fconsts). */ 13308 ldconst = "fconsts"; 13309 encode_fconstd: 13310 if (is_quarter_float (inst.operands[1].imm)) 13311 { 13312 inst.operands[1].imm = neon_qfloat_bits (inst.operands[1].imm); 13313 do_vfp_nsyn_opcode (ldconst); 13314 } 13315 else 13316 first_error (_("immediate out of range")); 13317 break; 13318 13319 case NS_RF: /* case 12 (fmrs). */ 13320 do_vfp_nsyn_opcode ("fmrs"); 13321 break; 13322 13323 case NS_FR: /* case 13 (fmsr). */ 13324 do_vfp_nsyn_opcode ("fmsr"); 13325 break; 13326 13327 /* The encoders for the fmrrs and fmsrr instructions expect three operands 13328 (one of which is a list), but we have parsed four. Do some fiddling to 13329 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2 13330 expect. */ 13331 case NS_RRFF: /* case 14 (fmrrs). */ 13332 constraint (inst.operands[3].reg != inst.operands[2].reg + 1, 13333 _("VFP registers must be adjacent")); 13334 inst.operands[2].imm = 2; 13335 memset (&inst.operands[3], '\0', sizeof (inst.operands[3])); 13336 do_vfp_nsyn_opcode ("fmrrs"); 13337 break; 13338 13339 case NS_FFRR: /* case 15 (fmsrr). */ 13340 constraint (inst.operands[1].reg != inst.operands[0].reg + 1, 13341 _("VFP registers must be adjacent")); 13342 inst.operands[1] = inst.operands[2]; 13343 inst.operands[2] = inst.operands[3]; 13344 inst.operands[0].imm = 2; 13345 memset (&inst.operands[3], '\0', sizeof (inst.operands[3])); 13346 do_vfp_nsyn_opcode ("fmsrr"); 13347 break; 13348 13349 default: 13350 abort (); 13351 } 13352} 13353 13354static void 13355do_neon_rshift_round_imm (void) 13356{ 13357 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); 13358 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_ALL | N_KEY); 13359 int imm = inst.operands[2].imm; 13360 13361 /* imm == 0 case is encoded as VMOV for V{R}SHR. */ 13362 if (imm == 0) 13363 { 13364 inst.operands[2].present = 0; 13365 do_neon_mov (); 13366 return; 13367 } 13368 13369 constraint (imm < 1 || (unsigned)imm > et.size, 13370 _("immediate out of range for shift")); 13371 neon_imm_shift (TRUE, et.type == NT_unsigned, neon_quad (rs), et, 13372 et.size - imm); 13373} 13374 13375static void 13376do_neon_movl (void) 13377{ 13378 struct neon_type_el et = neon_check_type (2, NS_QD, 13379 N_EQK | N_DBL, N_SU_32 | N_KEY); 13380 unsigned sizebits = et.size >> 3; 13381 inst.instruction |= sizebits << 19; 13382 neon_two_same (0, et.type == NT_unsigned, -1); 13383} 13384 13385static void 13386do_neon_trn (void) 13387{ 13388 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); 13389 struct neon_type_el et = neon_check_type (2, rs, 13390 N_EQK, N_8 | N_16 | N_32 | N_KEY); 13391 inst.instruction = NEON_ENC_INTEGER (inst.instruction); 13392 neon_two_same (neon_quad (rs), 1, et.size); 13393} 13394 13395static void 13396do_neon_zip_uzp (void) 13397{ 13398 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); 13399 struct neon_type_el et = neon_check_type (2, rs, 13400 N_EQK, N_8 | N_16 | N_32 | N_KEY); 13401 if (rs == NS_DD && et.size == 32) 13402 { 13403 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */ 13404 inst.instruction = N_MNEM_vtrn; 13405 do_neon_trn (); 13406 return; 13407 } 13408 neon_two_same (neon_quad (rs), 1, et.size); 13409} 13410 13411static void 13412do_neon_sat_abs_neg (void) 13413{ 13414 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); 13415 struct neon_type_el et = neon_check_type (2, rs, 13416 N_EQK, N_S8 | N_S16 | N_S32 | N_KEY); 13417 neon_two_same (neon_quad (rs), 1, et.size); 13418} 13419 13420static void 13421do_neon_pair_long (void) 13422{ 13423 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); 13424 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_32 | N_KEY); 13425 /* Unsigned is encoded in OP field (bit 7) for these instruction. */ 13426 inst.instruction |= (et.type == NT_unsigned) << 7; 13427 neon_two_same (neon_quad (rs), 1, et.size); 13428} 13429 13430static void 13431do_neon_recip_est (void) 13432{ 13433 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); 13434 struct neon_type_el et = neon_check_type (2, rs, 13435 N_EQK | N_FLT, N_F32 | N_U32 | N_KEY); 13436 inst.instruction |= (et.type == NT_float) << 8; 13437 neon_two_same (neon_quad (rs), 1, et.size); 13438} 13439 13440static void 13441do_neon_cls (void) 13442{ 13443 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); 13444 struct neon_type_el et = neon_check_type (2, rs, 13445 N_EQK, N_S8 | N_S16 | N_S32 | N_KEY); 13446 neon_two_same (neon_quad (rs), 1, et.size); 13447} 13448 13449static void 13450do_neon_clz (void) 13451{ 13452 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); 13453 struct neon_type_el et = neon_check_type (2, rs, 13454 N_EQK, N_I8 | N_I16 | N_I32 | N_KEY); 13455 neon_two_same (neon_quad (rs), 1, et.size); 13456} 13457 13458static void 13459do_neon_cnt (void) 13460{ 13461 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); 13462 struct neon_type_el et = neon_check_type (2, rs, 13463 N_EQK | N_INT, N_8 | N_KEY); 13464 neon_two_same (neon_quad (rs), 1, et.size); 13465} 13466 13467static void 13468do_neon_swp (void) 13469{ 13470 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); 13471 neon_two_same (neon_quad (rs), 1, -1); 13472} 13473 13474static void 13475do_neon_tbl_tbx (void) 13476{ 13477 unsigned listlenbits; 13478 neon_check_type (3, NS_DLD, N_EQK, N_EQK, N_8 | N_KEY); 13479 13480 if (inst.operands[1].imm < 1 || inst.operands[1].imm > 4) 13481 { 13482 first_error (_("bad list length for table lookup")); 13483 return; 13484 } 13485 13486 listlenbits = inst.operands[1].imm - 1; 13487 inst.instruction |= LOW4 (inst.operands[0].reg) << 12; 13488 inst.instruction |= HI1 (inst.operands[0].reg) << 22; 13489 inst.instruction |= LOW4 (inst.operands[1].reg) << 16; 13490 inst.instruction |= HI1 (inst.operands[1].reg) << 7; 13491 inst.instruction |= LOW4 (inst.operands[2].reg); 13492 inst.instruction |= HI1 (inst.operands[2].reg) << 5; 13493 inst.instruction |= listlenbits << 8; 13494 13495 inst.instruction = neon_dp_fixup (inst.instruction); 13496} 13497 13498static void 13499do_neon_ldm_stm (void) 13500{ 13501 /* P, U and L bits are part of bitmask. */ 13502 int is_dbmode = (inst.instruction & (1 << 24)) != 0; 13503 unsigned offsetbits = inst.operands[1].imm * 2; 13504 13505 if (inst.operands[1].issingle) 13506 { 13507 do_vfp_nsyn_ldm_stm (is_dbmode); 13508 return; 13509 } 13510 13511 constraint (is_dbmode && !inst.operands[0].writeback, 13512 _("writeback (!) must be used for VLDMDB and VSTMDB")); 13513 13514 constraint (inst.operands[1].imm < 1 || inst.operands[1].imm > 16, 13515 _("register list must contain at least 1 and at most 16 " 13516 "registers")); 13517 13518 inst.instruction |= inst.operands[0].reg << 16; 13519 inst.instruction |= inst.operands[0].writeback << 21; 13520 inst.instruction |= LOW4 (inst.operands[1].reg) << 12; 13521 inst.instruction |= HI1 (inst.operands[1].reg) << 22; 13522 13523 inst.instruction |= offsetbits; 13524 13525 do_vfp_cond_or_thumb (); 13526} 13527 13528static void 13529do_neon_ldr_str (void) 13530{ 13531 int is_ldr = (inst.instruction & (1 << 20)) != 0; 13532 13533 if (inst.operands[0].issingle) 13534 { 13535 if (is_ldr) 13536 do_vfp_nsyn_opcode ("flds"); 13537 else 13538 do_vfp_nsyn_opcode ("fsts"); 13539 } 13540 else 13541 { 13542 if (is_ldr) 13543 do_vfp_nsyn_opcode ("fldd"); 13544 else 13545 do_vfp_nsyn_opcode ("fstd"); 13546 } 13547} 13548 13549/* "interleave" version also handles non-interleaving register VLD1/VST1 13550 instructions. */ 13551 13552static void 13553do_neon_ld_st_interleave (void) 13554{ 13555 struct neon_type_el et = neon_check_type (1, NS_NULL, 13556 N_8 | N_16 | N_32 | N_64); 13557 unsigned alignbits = 0; 13558 unsigned idx; 13559 /* The bits in this table go: 13560 0: register stride of one (0) or two (1) 13561 1,2: register list length, minus one (1, 2, 3, 4). 13562 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>). 13563 We use -1 for invalid entries. */ 13564 const int typetable[] = 13565 { 13566 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */ 13567 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */ 13568 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */ 13569 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */ 13570 }; 13571 int typebits; 13572 13573 if (et.type == NT_invtype) 13574 return; 13575 13576 if (inst.operands[1].immisalign) 13577 switch (inst.operands[1].imm >> 8) 13578 { 13579 case 64: alignbits = 1; break; 13580 case 128: 13581 if (NEON_REGLIST_LENGTH (inst.operands[0].imm) == 3) 13582 goto bad_alignment; 13583 alignbits = 2; 13584 break; 13585 case 256: 13586 if (NEON_REGLIST_LENGTH (inst.operands[0].imm) == 3) 13587 goto bad_alignment; 13588 alignbits = 3; 13589 break; 13590 default: 13591 bad_alignment: 13592 first_error (_("bad alignment")); 13593 return; 13594 } 13595 13596 inst.instruction |= alignbits << 4; 13597 inst.instruction |= neon_logbits (et.size) << 6; 13598 13599 /* Bits [4:6] of the immediate in a list specifier encode register stride 13600 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of 13601 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look 13602 up the right value for "type" in a table based on this value and the given 13603 list style, then stick it back. */ 13604 idx = ((inst.operands[0].imm >> 4) & 7) 13605 | (((inst.instruction >> 8) & 3) << 3); 13606 13607 typebits = typetable[idx]; 13608 13609 constraint (typebits == -1, _("bad list type for instruction")); 13610 13611 inst.instruction &= ~0xf00; 13612 inst.instruction |= typebits << 8; 13613} 13614 13615/* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup. 13616 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0 13617 otherwise. The variable arguments are a list of pairs of legal (size, align) 13618 values, terminated with -1. */ 13619 13620static int 13621neon_alignment_bit (int size, int align, int *do_align, ...) 13622{ 13623 va_list ap; 13624 int result = FAIL, thissize, thisalign; 13625 13626 if (!inst.operands[1].immisalign) 13627 { 13628 *do_align = 0; 13629 return SUCCESS; 13630 } 13631 13632 va_start (ap, do_align); 13633 13634 do 13635 { 13636 thissize = va_arg (ap, int); 13637 if (thissize == -1) 13638 break; 13639 thisalign = va_arg (ap, int); 13640 13641 if (size == thissize && align == thisalign) 13642 result = SUCCESS; 13643 } 13644 while (result != SUCCESS); 13645 13646 va_end (ap); 13647 13648 if (result == SUCCESS) 13649 *do_align = 1; 13650 else 13651 first_error (_("unsupported alignment for instruction")); 13652 13653 return result; 13654} 13655 13656static void 13657do_neon_ld_st_lane (void) 13658{ 13659 struct neon_type_el et = neon_check_type (1, NS_NULL, N_8 | N_16 | N_32); 13660 int align_good, do_align = 0; 13661 int logsize = neon_logbits (et.size); 13662 int align = inst.operands[1].imm >> 8; 13663 int n = (inst.instruction >> 8) & 3; 13664 int max_el = 64 / et.size; 13665 13666 if (et.type == NT_invtype) 13667 return; 13668 13669 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != n + 1, 13670 _("bad list length")); 13671 constraint (NEON_LANE (inst.operands[0].imm) >= max_el, 13672 _("scalar index out of range")); 13673 constraint (n != 0 && NEON_REG_STRIDE (inst.operands[0].imm) == 2 13674 && et.size == 8, 13675 _("stride of 2 unavailable when element size is 8")); 13676 13677 switch (n) 13678 { 13679 case 0: /* VLD1 / VST1. */ 13680 align_good = neon_alignment_bit (et.size, align, &do_align, 16, 16, 13681 32, 32, -1); 13682 if (align_good == FAIL) 13683 return; 13684 if (do_align) 13685 { 13686 unsigned alignbits = 0; 13687 switch (et.size) 13688 { 13689 case 16: alignbits = 0x1; break; 13690 case 32: alignbits = 0x3; break; 13691 default: ; 13692 } 13693 inst.instruction |= alignbits << 4; 13694 } 13695 break; 13696 13697 case 1: /* VLD2 / VST2. */ 13698 align_good = neon_alignment_bit (et.size, align, &do_align, 8, 16, 16, 32, 13699 32, 64, -1); 13700 if (align_good == FAIL) 13701 return; 13702 if (do_align) 13703 inst.instruction |= 1 << 4; 13704 break; 13705 13706 case 2: /* VLD3 / VST3. */ 13707 constraint (inst.operands[1].immisalign, 13708 _("can't use alignment with this instruction")); 13709 break; 13710 13711 case 3: /* VLD4 / VST4. */ 13712 align_good = neon_alignment_bit (et.size, align, &do_align, 8, 32, 13713 16, 64, 32, 64, 32, 128, -1); 13714 if (align_good == FAIL) 13715 return; 13716 if (do_align) 13717 { 13718 unsigned alignbits = 0; 13719 switch (et.size) 13720 { 13721 case 8: alignbits = 0x1; break; 13722 case 16: alignbits = 0x1; break; 13723 case 32: alignbits = (align == 64) ? 0x1 : 0x2; break; 13724 default: ; 13725 } 13726 inst.instruction |= alignbits << 4; 13727 } 13728 break; 13729 13730 default: ; 13731 } 13732 13733 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */ 13734 if (n != 0 && NEON_REG_STRIDE (inst.operands[0].imm) == 2) 13735 inst.instruction |= 1 << (4 + logsize); 13736 13737 inst.instruction |= NEON_LANE (inst.operands[0].imm) << (logsize + 5); 13738 inst.instruction |= logsize << 10; 13739} 13740 13741/* Encode single n-element structure to all lanes VLD<n> instructions. */ 13742 13743static void 13744do_neon_ld_dup (void) 13745{ 13746 struct neon_type_el et = neon_check_type (1, NS_NULL, N_8 | N_16 | N_32); 13747 int align_good, do_align = 0; 13748 13749 if (et.type == NT_invtype) 13750 return; 13751 13752 switch ((inst.instruction >> 8) & 3) 13753 { 13754 case 0: /* VLD1. */ 13755 assert (NEON_REG_STRIDE (inst.operands[0].imm) != 2); 13756 align_good = neon_alignment_bit (et.size, inst.operands[1].imm >> 8, 13757 &do_align, 16, 16, 32, 32, -1); 13758 if (align_good == FAIL) 13759 return; 13760 switch (NEON_REGLIST_LENGTH (inst.operands[0].imm)) 13761 { 13762 case 1: break; 13763 case 2: inst.instruction |= 1 << 5; break; 13764 default: first_error (_("bad list length")); return; 13765 } 13766 inst.instruction |= neon_logbits (et.size) << 6; 13767 break; 13768 13769 case 1: /* VLD2. */ 13770 align_good = neon_alignment_bit (et.size, inst.operands[1].imm >> 8, 13771 &do_align, 8, 16, 16, 32, 32, 64, -1); 13772 if (align_good == FAIL) 13773 return; 13774 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 2, 13775 _("bad list length")); 13776 if (NEON_REG_STRIDE (inst.operands[0].imm) == 2) 13777 inst.instruction |= 1 << 5; 13778 inst.instruction |= neon_logbits (et.size) << 6; 13779 break; 13780 13781 case 2: /* VLD3. */ 13782 constraint (inst.operands[1].immisalign, 13783 _("can't use alignment with this instruction")); 13784 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 3, 13785 _("bad list length")); 13786 if (NEON_REG_STRIDE (inst.operands[0].imm) == 2) 13787 inst.instruction |= 1 << 5; 13788 inst.instruction |= neon_logbits (et.size) << 6; 13789 break; 13790 13791 case 3: /* VLD4. */ 13792 { 13793 int align = inst.operands[1].imm >> 8; 13794 align_good = neon_alignment_bit (et.size, align, &do_align, 8, 32, 13795 16, 64, 32, 64, 32, 128, -1); 13796 if (align_good == FAIL) 13797 return; 13798 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4, 13799 _("bad list length")); 13800 if (NEON_REG_STRIDE (inst.operands[0].imm) == 2) 13801 inst.instruction |= 1 << 5; 13802 if (et.size == 32 && align == 128) 13803 inst.instruction |= 0x3 << 6; 13804 else 13805 inst.instruction |= neon_logbits (et.size) << 6; 13806 } 13807 break; 13808 13809 default: ; 13810 } 13811 13812 inst.instruction |= do_align << 4; 13813} 13814 13815/* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those 13816 apart from bits [11:4]. */ 13817 13818static void 13819do_neon_ldx_stx (void) 13820{ 13821 switch (NEON_LANE (inst.operands[0].imm)) 13822 { 13823 case NEON_INTERLEAVE_LANES: 13824 inst.instruction = NEON_ENC_INTERLV (inst.instruction); 13825 do_neon_ld_st_interleave (); 13826 break; 13827 13828 case NEON_ALL_LANES: 13829 inst.instruction = NEON_ENC_DUP (inst.instruction); 13830 do_neon_ld_dup (); 13831 break; 13832 13833 default: 13834 inst.instruction = NEON_ENC_LANE (inst.instruction); 13835 do_neon_ld_st_lane (); 13836 } 13837 13838 /* L bit comes from bit mask. */ 13839 inst.instruction |= LOW4 (inst.operands[0].reg) << 12; 13840 inst.instruction |= HI1 (inst.operands[0].reg) << 22; 13841 inst.instruction |= inst.operands[1].reg << 16; 13842 13843 if (inst.operands[1].postind) 13844 { 13845 int postreg = inst.operands[1].imm & 0xf; 13846 constraint (!inst.operands[1].immisreg, 13847 _("post-index must be a register")); 13848 constraint (postreg == 0xd || postreg == 0xf, 13849 _("bad register for post-index")); 13850 inst.instruction |= postreg; 13851 } 13852 else if (inst.operands[1].writeback) 13853 { 13854 inst.instruction |= 0xd; 13855 } 13856 else 13857 inst.instruction |= 0xf; 13858 13859 if (thumb_mode) 13860 inst.instruction |= 0xf9000000; 13861 else 13862 inst.instruction |= 0xf4000000; 13863} 13864 13865 13866/* Overall per-instruction processing. */ 13867 13868/* We need to be able to fix up arbitrary expressions in some statements. 13869 This is so that we can handle symbols that are an arbitrary distance from 13870 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask), 13871 which returns part of an address in a form which will be valid for 13872 a data instruction. We do this by pushing the expression into a symbol 13873 in the expr_section, and creating a fix for that. */ 13874 13875static void 13876fix_new_arm (fragS * frag, 13877 int where, 13878 short int size, 13879 expressionS * exp, 13880 int pc_rel, 13881 int reloc) 13882{ 13883 fixS * new_fix; 13884 13885 switch (exp->X_op) 13886 { 13887 case O_constant: 13888 case O_symbol: 13889 case O_add: 13890 case O_subtract: 13891 new_fix = fix_new_exp (frag, where, size, exp, pc_rel, reloc); 13892 break; 13893 13894 default: 13895 new_fix = fix_new (frag, where, size, make_expr_symbol (exp), 0, 13896 pc_rel, reloc); 13897 break; 13898 } 13899 13900 /* Mark whether the fix is to a THUMB instruction, or an ARM 13901 instruction. */ 13902 new_fix->tc_fix_data = thumb_mode; 13903} 13904 13905/* Create a frg for an instruction requiring relaxation. */ 13906static void 13907output_relax_insn (void) 13908{ 13909 char * to; 13910 symbolS *sym; 13911 int offset; 13912 13913 /* The size of the instruction is unknown, so tie the debug info to the 13914 start of the instruction. */ 13915 dwarf2_emit_insn (0); 13916 13917 switch (inst.reloc.exp.X_op) 13918 { 13919 case O_symbol: 13920 sym = inst.reloc.exp.X_add_symbol; 13921 offset = inst.reloc.exp.X_add_number; 13922 break; 13923 case O_constant: 13924 sym = NULL; 13925 offset = inst.reloc.exp.X_add_number; 13926 break; 13927 default: 13928 sym = make_expr_symbol (&inst.reloc.exp); 13929 offset = 0; 13930 break; 13931 } 13932 to = frag_var (rs_machine_dependent, INSN_SIZE, THUMB_SIZE, 13933 inst.relax, sym, offset, NULL/*offset, opcode*/); 13934 md_number_to_chars (to, inst.instruction, THUMB_SIZE); 13935} 13936 13937/* Write a 32-bit thumb instruction to buf. */ 13938static void 13939put_thumb32_insn (char * buf, unsigned long insn) 13940{ 13941 md_number_to_chars (buf, insn >> 16, THUMB_SIZE); 13942 md_number_to_chars (buf + THUMB_SIZE, insn, THUMB_SIZE); 13943} 13944 13945static void 13946output_inst (const char * str) 13947{ 13948 char * to = NULL; 13949 13950 if (inst.error) 13951 { 13952 as_bad ("%s -- `%s'", inst.error, str); 13953 return; 13954 } 13955 if (inst.relax) { 13956 output_relax_insn(); 13957 return; 13958 } 13959 if (inst.size == 0) 13960 return; 13961 13962 to = frag_more (inst.size); 13963 13964 if (thumb_mode && (inst.size > THUMB_SIZE)) 13965 { 13966 assert (inst.size == (2 * THUMB_SIZE)); 13967 put_thumb32_insn (to, inst.instruction); 13968 } 13969 else if (inst.size > INSN_SIZE) 13970 { 13971 assert (inst.size == (2 * INSN_SIZE)); 13972 md_number_to_chars (to, inst.instruction, INSN_SIZE); 13973 md_number_to_chars (to + INSN_SIZE, inst.instruction, INSN_SIZE); 13974 } 13975 else 13976 md_number_to_chars (to, inst.instruction, inst.size); 13977 13978 if (inst.reloc.type != BFD_RELOC_UNUSED) 13979 fix_new_arm (frag_now, to - frag_now->fr_literal, 13980 inst.size, & inst.reloc.exp, inst.reloc.pc_rel, 13981 inst.reloc.type); 13982 13983 dwarf2_emit_insn (inst.size); 13984} 13985 13986/* Tag values used in struct asm_opcode's tag field. */ 13987enum opcode_tag 13988{ 13989 OT_unconditional, /* Instruction cannot be conditionalized. 13990 The ARM condition field is still 0xE. */ 13991 OT_unconditionalF, /* Instruction cannot be conditionalized 13992 and carries 0xF in its ARM condition field. */ 13993 OT_csuffix, /* Instruction takes a conditional suffix. */ 13994 OT_csuffixF, /* Some forms of the instruction take a conditional 13995 suffix, others place 0xF where the condition field 13996 would be. */ 13997 OT_cinfix3, /* Instruction takes a conditional infix, 13998 beginning at character index 3. (In 13999 unified mode, it becomes a suffix.) */ 14000 OT_cinfix3_deprecated, /* The same as OT_cinfix3. This is used for 14001 tsts, cmps, cmns, and teqs. */ 14002 OT_cinfix3_legacy, /* Legacy instruction takes a conditional infix at 14003 character index 3, even in unified mode. Used for 14004 legacy instructions where suffix and infix forms 14005 may be ambiguous. */ 14006 OT_csuf_or_in3, /* Instruction takes either a conditional 14007 suffix or an infix at character index 3. */ 14008 OT_odd_infix_unc, /* This is the unconditional variant of an 14009 instruction that takes a conditional infix 14010 at an unusual position. In unified mode, 14011 this variant will accept a suffix. */ 14012 OT_odd_infix_0 /* Values greater than or equal to OT_odd_infix_0 14013 are the conditional variants of instructions that 14014 take conditional infixes in unusual positions. 14015 The infix appears at character index 14016 (tag - OT_odd_infix_0). These are not accepted 14017 in unified mode. */ 14018}; 14019 14020/* Subroutine of md_assemble, responsible for looking up the primary 14021 opcode from the mnemonic the user wrote. STR points to the 14022 beginning of the mnemonic. 14023 14024 This is not simply a hash table lookup, because of conditional 14025 variants. Most instructions have conditional variants, which are 14026 expressed with a _conditional affix_ to the mnemonic. If we were 14027 to encode each conditional variant as a literal string in the opcode 14028 table, it would have approximately 20,000 entries. 14029 14030 Most mnemonics take this affix as a suffix, and in unified syntax, 14031 'most' is upgraded to 'all'. However, in the divided syntax, some 14032 instructions take the affix as an infix, notably the s-variants of 14033 the arithmetic instructions. Of those instructions, all but six 14034 have the infix appear after the third character of the mnemonic. 14035 14036 Accordingly, the algorithm for looking up primary opcodes given 14037 an identifier is: 14038 14039 1. Look up the identifier in the opcode table. 14040 If we find a match, go to step U. 14041 14042 2. Look up the last two characters of the identifier in the 14043 conditions table. If we find a match, look up the first N-2 14044 characters of the identifier in the opcode table. If we 14045 find a match, go to step CE. 14046 14047 3. Look up the fourth and fifth characters of the identifier in 14048 the conditions table. If we find a match, extract those 14049 characters from the identifier, and look up the remaining 14050 characters in the opcode table. If we find a match, go 14051 to step CM. 14052 14053 4. Fail. 14054 14055 U. Examine the tag field of the opcode structure, in case this is 14056 one of the six instructions with its conditional infix in an 14057 unusual place. If it is, the tag tells us where to find the 14058 infix; look it up in the conditions table and set inst.cond 14059 accordingly. Otherwise, this is an unconditional instruction. 14060 Again set inst.cond accordingly. Return the opcode structure. 14061 14062 CE. Examine the tag field to make sure this is an instruction that 14063 should receive a conditional suffix. If it is not, fail. 14064 Otherwise, set inst.cond from the suffix we already looked up, 14065 and return the opcode structure. 14066 14067 CM. Examine the tag field to make sure this is an instruction that 14068 should receive a conditional infix after the third character. 14069 If it is not, fail. Otherwise, undo the edits to the current 14070 line of input and proceed as for case CE. */ 14071 14072static const struct asm_opcode * 14073opcode_lookup (char **str) 14074{ 14075 char *end, *base; 14076 char *affix; 14077 const struct asm_opcode *opcode; 14078 const struct asm_cond *cond; 14079 char save[2]; 14080 bfd_boolean neon_supported; 14081 14082 neon_supported = ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1); 14083 14084 /* Scan up to the end of the mnemonic, which must end in white space, 14085 '.' (in unified mode, or for Neon instructions), or end of string. */ 14086 for (base = end = *str; *end != '\0'; end++) 14087 if (*end == ' ' || ((unified_syntax || neon_supported) && *end == '.')) 14088 break; 14089 14090 if (end == base) 14091 return 0; 14092 14093 /* Handle a possible width suffix and/or Neon type suffix. */ 14094 if (end[0] == '.') 14095 { 14096 int offset = 2; 14097 14098 /* The .w and .n suffixes are only valid if the unified syntax is in 14099 use. */ 14100 if (unified_syntax && end[1] == 'w') 14101 inst.size_req = 4; 14102 else if (unified_syntax && end[1] == 'n') 14103 inst.size_req = 2; 14104 else 14105 offset = 0; 14106 14107 inst.vectype.elems = 0; 14108 14109 *str = end + offset; 14110 14111 if (end[offset] == '.') 14112 { 14113 /* See if we have a Neon type suffix (possible in either unified or 14114 non-unified ARM syntax mode). */ 14115 if (parse_neon_type (&inst.vectype, str) == FAIL) 14116 return 0; 14117 } 14118 else if (end[offset] != '\0' && end[offset] != ' ') 14119 return 0; 14120 } 14121 else 14122 *str = end; 14123 14124 /* Look for unaffixed or special-case affixed mnemonic. */ 14125 opcode = hash_find_n (arm_ops_hsh, base, end - base); 14126 if (opcode) 14127 { 14128 /* step U */ 14129 if (opcode->tag < OT_odd_infix_0) 14130 { 14131 inst.cond = COND_ALWAYS; 14132 return opcode; 14133 } 14134 14135 if (unified_syntax) 14136 as_warn (_("conditional infixes are deprecated in unified syntax")); 14137 affix = base + (opcode->tag - OT_odd_infix_0); 14138 cond = hash_find_n (arm_cond_hsh, affix, 2); 14139 assert (cond); 14140 14141 inst.cond = cond->value; 14142 return opcode; 14143 } 14144 14145 /* Cannot have a conditional suffix on a mnemonic of less than two 14146 characters. */ 14147 if (end - base < 3) 14148 return 0; 14149 14150 /* Look for suffixed mnemonic. */ 14151 affix = end - 2; 14152 cond = hash_find_n (arm_cond_hsh, affix, 2); 14153 opcode = hash_find_n (arm_ops_hsh, base, affix - base); 14154 if (opcode && cond) 14155 { 14156 /* step CE */ 14157 switch (opcode->tag) 14158 { 14159 case OT_cinfix3_legacy: 14160 /* Ignore conditional suffixes matched on infix only mnemonics. */ 14161 break; 14162 14163 case OT_cinfix3: 14164 case OT_cinfix3_deprecated: 14165 case OT_odd_infix_unc: 14166 if (!unified_syntax) 14167 return 0; 14168 /* else fall through */ 14169 14170 case OT_csuffix: 14171 case OT_csuffixF: 14172 case OT_csuf_or_in3: 14173 inst.cond = cond->value; 14174 return opcode; 14175 14176 case OT_unconditional: 14177 case OT_unconditionalF: 14178 if (thumb_mode) 14179 { 14180 inst.cond = cond->value; 14181 } 14182 else 14183 { 14184 /* delayed diagnostic */ 14185 inst.error = BAD_COND; 14186 inst.cond = COND_ALWAYS; 14187 } 14188 return opcode; 14189 14190 default: 14191 return 0; 14192 } 14193 } 14194 14195 /* Cannot have a usual-position infix on a mnemonic of less than 14196 six characters (five would be a suffix). */ 14197 if (end - base < 6) 14198 return 0; 14199 14200 /* Look for infixed mnemonic in the usual position. */ 14201 affix = base + 3; 14202 cond = hash_find_n (arm_cond_hsh, affix, 2); 14203 if (!cond) 14204 return 0; 14205 14206 memcpy (save, affix, 2); 14207 memmove (affix, affix + 2, (end - affix) - 2); 14208 opcode = hash_find_n (arm_ops_hsh, base, (end - base) - 2); 14209 memmove (affix + 2, affix, (end - affix) - 2); 14210 memcpy (affix, save, 2); 14211 14212 if (opcode 14213 && (opcode->tag == OT_cinfix3 14214 || opcode->tag == OT_cinfix3_deprecated 14215 || opcode->tag == OT_csuf_or_in3 14216 || opcode->tag == OT_cinfix3_legacy)) 14217 { 14218 /* step CM */ 14219 if (unified_syntax 14220 && (opcode->tag == OT_cinfix3 14221 || opcode->tag == OT_cinfix3_deprecated)) 14222 as_warn (_("conditional infixes are deprecated in unified syntax")); 14223 14224 inst.cond = cond->value; 14225 return opcode; 14226 } 14227 14228 return 0; 14229} 14230 14231void 14232md_assemble (char *str) 14233{ 14234 char *p = str; 14235 const struct asm_opcode * opcode; 14236 14237 /* Align the previous label if needed. */ 14238 if (last_label_seen != NULL) 14239 { 14240 symbol_set_frag (last_label_seen, frag_now); 14241 S_SET_VALUE (last_label_seen, (valueT) frag_now_fix ()); 14242 S_SET_SEGMENT (last_label_seen, now_seg); 14243 } 14244 14245 memset (&inst, '\0', sizeof (inst)); 14246 inst.reloc.type = BFD_RELOC_UNUSED; 14247 14248 opcode = opcode_lookup (&p); 14249 if (!opcode) 14250 { 14251 /* It wasn't an instruction, but it might be a register alias of 14252 the form alias .req reg, or a Neon .dn/.qn directive. */ 14253 if (!create_register_alias (str, p) 14254 && !create_neon_reg_alias (str, p)) 14255 as_bad (_("bad instruction `%s'"), str); 14256 14257 return; 14258 } 14259 14260 if (opcode->tag == OT_cinfix3_deprecated) 14261 as_warn (_("s suffix on comparison instruction is deprecated")); 14262 14263 /* The value which unconditional instructions should have in place of the 14264 condition field. */ 14265 inst.uncond_value = (opcode->tag == OT_csuffixF) ? 0xf : -1; 14266 14267 if (thumb_mode) 14268 { 14269 arm_feature_set variant; 14270 14271 variant = cpu_variant; 14272 /* Only allow coprocessor instructions on Thumb-2 capable devices. */ 14273 if (!ARM_CPU_HAS_FEATURE (variant, arm_arch_t2)) 14274 ARM_CLEAR_FEATURE (variant, variant, fpu_any_hard); 14275 /* Check that this instruction is supported for this CPU. */ 14276 if (!opcode->tvariant 14277 || (thumb_mode == 1 14278 && !ARM_CPU_HAS_FEATURE (variant, *opcode->tvariant))) 14279 { 14280 as_bad (_("selected processor does not support `%s'"), str); 14281 return; 14282 } 14283 if (inst.cond != COND_ALWAYS && !unified_syntax 14284 && opcode->tencode != do_t_branch) 14285 { 14286 as_bad (_("Thumb does not support conditional execution")); 14287 return; 14288 } 14289 14290 if (!ARM_CPU_HAS_FEATURE (variant, arm_ext_v6t2) && !inst.size_req) 14291 { 14292 /* Implicit require narrow instructions on Thumb-1. This avoids 14293 relaxation accidentally introducing Thumb-2 instructions. */ 14294 if (opcode->tencode != do_t_blx && opcode->tencode != do_t_branch23) 14295 inst.size_req = 2; 14296 } 14297 14298 /* Check conditional suffixes. */ 14299 if (current_it_mask) 14300 { 14301 int cond; 14302 cond = current_cc ^ ((current_it_mask >> 4) & 1) ^ 1; 14303 current_it_mask <<= 1; 14304 current_it_mask &= 0x1f; 14305 /* The BKPT instruction is unconditional even in an IT block. */ 14306 if (!inst.error 14307 && cond != inst.cond && opcode->tencode != do_t_bkpt) 14308 { 14309 as_bad (_("incorrect condition in IT block")); 14310 return; 14311 } 14312 } 14313 else if (inst.cond != COND_ALWAYS && opcode->tencode != do_t_branch) 14314 { 14315 as_bad (_("thumb conditional instrunction not in IT block")); 14316 return; 14317 } 14318 14319 mapping_state (MAP_THUMB); 14320 inst.instruction = opcode->tvalue; 14321 14322 if (!parse_operands (p, opcode->operands)) 14323 opcode->tencode (); 14324 14325 /* Clear current_it_mask at the end of an IT block. */ 14326 if (current_it_mask == 0x10) 14327 current_it_mask = 0; 14328 14329 if (!(inst.error || inst.relax)) 14330 { 14331 assert (inst.instruction < 0xe800 || inst.instruction > 0xffff); 14332 inst.size = (inst.instruction > 0xffff ? 4 : 2); 14333 if (inst.size_req && inst.size_req != inst.size) 14334 { 14335 as_bad (_("cannot honor width suffix -- `%s'"), str); 14336 return; 14337 } 14338 } 14339 14340 /* Something has gone badly wrong if we try to relax a fixed size 14341 instruction. */ 14342 assert (inst.size_req == 0 || !inst.relax); 14343 14344 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, 14345 *opcode->tvariant); 14346 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly 14347 set those bits when Thumb-2 32-bit instructions are seen. ie. 14348 anything other than bl/blx. 14349 This is overly pessimistic for relaxable instructions. */ 14350 if ((inst.size == 4 && (inst.instruction & 0xf800e800) != 0xf000e800) 14351 || inst.relax) 14352 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, 14353 arm_ext_v6t2); 14354 } 14355 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1)) 14356 { 14357 /* Check that this instruction is supported for this CPU. */ 14358 if (!opcode->avariant || 14359 !ARM_CPU_HAS_FEATURE (cpu_variant, *opcode->avariant)) 14360 { 14361 as_bad (_("selected processor does not support `%s'"), str); 14362 return; 14363 } 14364 if (inst.size_req) 14365 { 14366 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str); 14367 return; 14368 } 14369 14370 mapping_state (MAP_ARM); 14371 inst.instruction = opcode->avalue; 14372 if (opcode->tag == OT_unconditionalF) 14373 inst.instruction |= 0xF << 28; 14374 else 14375 inst.instruction |= inst.cond << 28; 14376 inst.size = INSN_SIZE; 14377 if (!parse_operands (p, opcode->operands)) 14378 opcode->aencode (); 14379 /* Arm mode bx is marked as both v4T and v5 because it's still required 14380 on a hypothetical non-thumb v5 core. */ 14381 if (ARM_CPU_HAS_FEATURE (*opcode->avariant, arm_ext_v4t) 14382 || ARM_CPU_HAS_FEATURE (*opcode->avariant, arm_ext_v5)) 14383 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, arm_ext_v4t); 14384 else 14385 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, 14386 *opcode->avariant); 14387 } 14388 else 14389 { 14390 as_bad (_("attempt to use an ARM instruction on a Thumb-only processor " 14391 "-- `%s'"), str); 14392 return; 14393 } 14394 output_inst (str); 14395} 14396 14397/* Various frobbings of labels and their addresses. */ 14398 14399void 14400arm_start_line_hook (void) 14401{ 14402 last_label_seen = NULL; 14403} 14404 14405void 14406arm_frob_label (symbolS * sym) 14407{ 14408 last_label_seen = sym; 14409 14410 ARM_SET_THUMB (sym, thumb_mode); 14411 14412#if defined OBJ_COFF || defined OBJ_ELF 14413 ARM_SET_INTERWORK (sym, support_interwork); 14414#endif 14415 14416 /* Note - do not allow local symbols (.Lxxx) to be labeled 14417 as Thumb functions. This is because these labels, whilst 14418 they exist inside Thumb code, are not the entry points for 14419 possible ARM->Thumb calls. Also, these labels can be used 14420 as part of a computed goto or switch statement. eg gcc 14421 can generate code that looks like this: 14422 14423 ldr r2, [pc, .Laaa] 14424 lsl r3, r3, #2 14425 ldr r2, [r3, r2] 14426 mov pc, r2 14427 14428 .Lbbb: .word .Lxxx 14429 .Lccc: .word .Lyyy 14430 ..etc... 14431 .Laaa: .word Lbbb 14432 14433 The first instruction loads the address of the jump table. 14434 The second instruction converts a table index into a byte offset. 14435 The third instruction gets the jump address out of the table. 14436 The fourth instruction performs the jump. 14437 14438 If the address stored at .Laaa is that of a symbol which has the 14439 Thumb_Func bit set, then the linker will arrange for this address 14440 to have the bottom bit set, which in turn would mean that the 14441 address computation performed by the third instruction would end 14442 up with the bottom bit set. Since the ARM is capable of unaligned 14443 word loads, the instruction would then load the incorrect address 14444 out of the jump table, and chaos would ensue. */ 14445 if (label_is_thumb_function_name 14446 && (S_GET_NAME (sym)[0] != '.' || S_GET_NAME (sym)[1] != 'L') 14447 && (bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0) 14448 { 14449 /* When the address of a Thumb function is taken the bottom 14450 bit of that address should be set. This will allow 14451 interworking between Arm and Thumb functions to work 14452 correctly. */ 14453 14454 THUMB_SET_FUNC (sym, 1); 14455 14456 label_is_thumb_function_name = FALSE; 14457 } 14458 14459 dwarf2_emit_label (sym); 14460} 14461 14462int 14463arm_data_in_code (void) 14464{ 14465 if (thumb_mode && ! strncmp (input_line_pointer + 1, "data:", 5)) 14466 { 14467 *input_line_pointer = '/'; 14468 input_line_pointer += 5; 14469 *input_line_pointer = 0; 14470 return 1; 14471 } 14472 14473 return 0; 14474} 14475 14476char * 14477arm_canonicalize_symbol_name (char * name) 14478{ 14479 int len; 14480 14481 if (thumb_mode && (len = strlen (name)) > 5 14482 && streq (name + len - 5, "/data")) 14483 *(name + len - 5) = 0; 14484 14485 return name; 14486} 14487 14488/* Table of all register names defined by default. The user can 14489 define additional names with .req. Note that all register names 14490 should appear in both upper and lowercase variants. Some registers 14491 also have mixed-case names. */ 14492 14493#define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 } 14494#define REGNUM(p,n,t) REGDEF(p##n, n, t) 14495#define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t) 14496#define REGSET(p,t) \ 14497 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \ 14498 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \ 14499 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \ 14500 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t) 14501#define REGSETH(p,t) \ 14502 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \ 14503 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \ 14504 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \ 14505 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t) 14506#define REGSET2(p,t) \ 14507 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \ 14508 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \ 14509 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \ 14510 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t) 14511 14512static const struct reg_entry reg_names[] = 14513{ 14514 /* ARM integer registers. */ 14515 REGSET(r, RN), REGSET(R, RN), 14516 14517 /* ATPCS synonyms. */ 14518 REGDEF(a1,0,RN), REGDEF(a2,1,RN), REGDEF(a3, 2,RN), REGDEF(a4, 3,RN), 14519 REGDEF(v1,4,RN), REGDEF(v2,5,RN), REGDEF(v3, 6,RN), REGDEF(v4, 7,RN), 14520 REGDEF(v5,8,RN), REGDEF(v6,9,RN), REGDEF(v7,10,RN), REGDEF(v8,11,RN), 14521 14522 REGDEF(A1,0,RN), REGDEF(A2,1,RN), REGDEF(A3, 2,RN), REGDEF(A4, 3,RN), 14523 REGDEF(V1,4,RN), REGDEF(V2,5,RN), REGDEF(V3, 6,RN), REGDEF(V4, 7,RN), 14524 REGDEF(V5,8,RN), REGDEF(V6,9,RN), REGDEF(V7,10,RN), REGDEF(V8,11,RN), 14525 14526 /* Well-known aliases. */ 14527 REGDEF(wr, 7,RN), REGDEF(sb, 9,RN), REGDEF(sl,10,RN), REGDEF(fp,11,RN), 14528 REGDEF(ip,12,RN), REGDEF(sp,13,RN), REGDEF(lr,14,RN), REGDEF(pc,15,RN), 14529 14530 REGDEF(WR, 7,RN), REGDEF(SB, 9,RN), REGDEF(SL,10,RN), REGDEF(FP,11,RN), 14531 REGDEF(IP,12,RN), REGDEF(SP,13,RN), REGDEF(LR,14,RN), REGDEF(PC,15,RN), 14532 14533 /* Coprocessor numbers. */ 14534 REGSET(p, CP), REGSET(P, CP), 14535 14536 /* Coprocessor register numbers. The "cr" variants are for backward 14537 compatibility. */ 14538 REGSET(c, CN), REGSET(C, CN), 14539 REGSET(cr, CN), REGSET(CR, CN), 14540 14541 /* FPA registers. */ 14542 REGNUM(f,0,FN), REGNUM(f,1,FN), REGNUM(f,2,FN), REGNUM(f,3,FN), 14543 REGNUM(f,4,FN), REGNUM(f,5,FN), REGNUM(f,6,FN), REGNUM(f,7, FN), 14544 14545 REGNUM(F,0,FN), REGNUM(F,1,FN), REGNUM(F,2,FN), REGNUM(F,3,FN), 14546 REGNUM(F,4,FN), REGNUM(F,5,FN), REGNUM(F,6,FN), REGNUM(F,7, FN), 14547 14548 /* VFP SP registers. */ 14549 REGSET(s,VFS), REGSET(S,VFS), 14550 REGSETH(s,VFS), REGSETH(S,VFS), 14551 14552 /* VFP DP Registers. */ 14553 REGSET(d,VFD), REGSET(D,VFD), 14554 /* Extra Neon DP registers. */ 14555 REGSETH(d,VFD), REGSETH(D,VFD), 14556 14557 /* Neon QP registers. */ 14558 REGSET2(q,NQ), REGSET2(Q,NQ), 14559 14560 /* VFP control registers. */ 14561 REGDEF(fpsid,0,VFC), REGDEF(fpscr,1,VFC), REGDEF(fpexc,8,VFC), 14562 REGDEF(FPSID,0,VFC), REGDEF(FPSCR,1,VFC), REGDEF(FPEXC,8,VFC), 14563 REGDEF(fpinst,9,VFC), REGDEF(fpinst2,10,VFC), 14564 REGDEF(FPINST,9,VFC), REGDEF(FPINST2,10,VFC), 14565 REGDEF(mvfr0,7,VFC), REGDEF(mvfr1,6,VFC), 14566 REGDEF(MVFR0,7,VFC), REGDEF(MVFR1,6,VFC), 14567 14568 /* Maverick DSP coprocessor registers. */ 14569 REGSET(mvf,MVF), REGSET(mvd,MVD), REGSET(mvfx,MVFX), REGSET(mvdx,MVDX), 14570 REGSET(MVF,MVF), REGSET(MVD,MVD), REGSET(MVFX,MVFX), REGSET(MVDX,MVDX), 14571 14572 REGNUM(mvax,0,MVAX), REGNUM(mvax,1,MVAX), 14573 REGNUM(mvax,2,MVAX), REGNUM(mvax,3,MVAX), 14574 REGDEF(dspsc,0,DSPSC), 14575 14576 REGNUM(MVAX,0,MVAX), REGNUM(MVAX,1,MVAX), 14577 REGNUM(MVAX,2,MVAX), REGNUM(MVAX,3,MVAX), 14578 REGDEF(DSPSC,0,DSPSC), 14579 14580 /* iWMMXt data registers - p0, c0-15. */ 14581 REGSET(wr,MMXWR), REGSET(wR,MMXWR), REGSET(WR, MMXWR), 14582 14583 /* iWMMXt control registers - p1, c0-3. */ 14584 REGDEF(wcid, 0,MMXWC), REGDEF(wCID, 0,MMXWC), REGDEF(WCID, 0,MMXWC), 14585 REGDEF(wcon, 1,MMXWC), REGDEF(wCon, 1,MMXWC), REGDEF(WCON, 1,MMXWC), 14586 REGDEF(wcssf, 2,MMXWC), REGDEF(wCSSF, 2,MMXWC), REGDEF(WCSSF, 2,MMXWC), 14587 REGDEF(wcasf, 3,MMXWC), REGDEF(wCASF, 3,MMXWC), REGDEF(WCASF, 3,MMXWC), 14588 14589 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */ 14590 REGDEF(wcgr0, 8,MMXWCG), REGDEF(wCGR0, 8,MMXWCG), REGDEF(WCGR0, 8,MMXWCG), 14591 REGDEF(wcgr1, 9,MMXWCG), REGDEF(wCGR1, 9,MMXWCG), REGDEF(WCGR1, 9,MMXWCG), 14592 REGDEF(wcgr2,10,MMXWCG), REGDEF(wCGR2,10,MMXWCG), REGDEF(WCGR2,10,MMXWCG), 14593 REGDEF(wcgr3,11,MMXWCG), REGDEF(wCGR3,11,MMXWCG), REGDEF(WCGR3,11,MMXWCG), 14594 14595 /* XScale accumulator registers. */ 14596 REGNUM(acc,0,XSCALE), REGNUM(ACC,0,XSCALE), 14597}; 14598#undef REGDEF 14599#undef REGNUM 14600#undef REGSET 14601 14602/* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled 14603 within psr_required_here. */ 14604static const struct asm_psr psrs[] = 14605{ 14606 /* Backward compatibility notation. Note that "all" is no longer 14607 truly all possible PSR bits. */ 14608 {"all", PSR_c | PSR_f}, 14609 {"flg", PSR_f}, 14610 {"ctl", PSR_c}, 14611 14612 /* Individual flags. */ 14613 {"f", PSR_f}, 14614 {"c", PSR_c}, 14615 {"x", PSR_x}, 14616 {"s", PSR_s}, 14617 /* Combinations of flags. */ 14618 {"fs", PSR_f | PSR_s}, 14619 {"fx", PSR_f | PSR_x}, 14620 {"fc", PSR_f | PSR_c}, 14621 {"sf", PSR_s | PSR_f}, 14622 {"sx", PSR_s | PSR_x}, 14623 {"sc", PSR_s | PSR_c}, 14624 {"xf", PSR_x | PSR_f}, 14625 {"xs", PSR_x | PSR_s}, 14626 {"xc", PSR_x | PSR_c}, 14627 {"cf", PSR_c | PSR_f}, 14628 {"cs", PSR_c | PSR_s}, 14629 {"cx", PSR_c | PSR_x}, 14630 {"fsx", PSR_f | PSR_s | PSR_x}, 14631 {"fsc", PSR_f | PSR_s | PSR_c}, 14632 {"fxs", PSR_f | PSR_x | PSR_s}, 14633 {"fxc", PSR_f | PSR_x | PSR_c}, 14634 {"fcs", PSR_f | PSR_c | PSR_s}, 14635 {"fcx", PSR_f | PSR_c | PSR_x}, 14636 {"sfx", PSR_s | PSR_f | PSR_x}, 14637 {"sfc", PSR_s | PSR_f | PSR_c}, 14638 {"sxf", PSR_s | PSR_x | PSR_f}, 14639 {"sxc", PSR_s | PSR_x | PSR_c}, 14640 {"scf", PSR_s | PSR_c | PSR_f}, 14641 {"scx", PSR_s | PSR_c | PSR_x}, 14642 {"xfs", PSR_x | PSR_f | PSR_s}, 14643 {"xfc", PSR_x | PSR_f | PSR_c}, 14644 {"xsf", PSR_x | PSR_s | PSR_f}, 14645 {"xsc", PSR_x | PSR_s | PSR_c}, 14646 {"xcf", PSR_x | PSR_c | PSR_f}, 14647 {"xcs", PSR_x | PSR_c | PSR_s}, 14648 {"cfs", PSR_c | PSR_f | PSR_s}, 14649 {"cfx", PSR_c | PSR_f | PSR_x}, 14650 {"csf", PSR_c | PSR_s | PSR_f}, 14651 {"csx", PSR_c | PSR_s | PSR_x}, 14652 {"cxf", PSR_c | PSR_x | PSR_f}, 14653 {"cxs", PSR_c | PSR_x | PSR_s}, 14654 {"fsxc", PSR_f | PSR_s | PSR_x | PSR_c}, 14655 {"fscx", PSR_f | PSR_s | PSR_c | PSR_x}, 14656 {"fxsc", PSR_f | PSR_x | PSR_s | PSR_c}, 14657 {"fxcs", PSR_f | PSR_x | PSR_c | PSR_s}, 14658 {"fcsx", PSR_f | PSR_c | PSR_s | PSR_x}, 14659 {"fcxs", PSR_f | PSR_c | PSR_x | PSR_s}, 14660 {"sfxc", PSR_s | PSR_f | PSR_x | PSR_c}, 14661 {"sfcx", PSR_s | PSR_f | PSR_c | PSR_x}, 14662 {"sxfc", PSR_s | PSR_x | PSR_f | PSR_c}, 14663 {"sxcf", PSR_s | PSR_x | PSR_c | PSR_f}, 14664 {"scfx", PSR_s | PSR_c | PSR_f | PSR_x}, 14665 {"scxf", PSR_s | PSR_c | PSR_x | PSR_f}, 14666 {"xfsc", PSR_x | PSR_f | PSR_s | PSR_c}, 14667 {"xfcs", PSR_x | PSR_f | PSR_c | PSR_s}, 14668 {"xsfc", PSR_x | PSR_s | PSR_f | PSR_c}, 14669 {"xscf", PSR_x | PSR_s | PSR_c | PSR_f}, 14670 {"xcfs", PSR_x | PSR_c | PSR_f | PSR_s}, 14671 {"xcsf", PSR_x | PSR_c | PSR_s | PSR_f}, 14672 {"cfsx", PSR_c | PSR_f | PSR_s | PSR_x}, 14673 {"cfxs", PSR_c | PSR_f | PSR_x | PSR_s}, 14674 {"csfx", PSR_c | PSR_s | PSR_f | PSR_x}, 14675 {"csxf", PSR_c | PSR_s | PSR_x | PSR_f}, 14676 {"cxfs", PSR_c | PSR_x | PSR_f | PSR_s}, 14677 {"cxsf", PSR_c | PSR_x | PSR_s | PSR_f}, 14678}; 14679 14680/* Table of V7M psr names. */ 14681static const struct asm_psr v7m_psrs[] = 14682{ 14683 {"apsr", 0 }, {"APSR", 0 }, 14684 {"iapsr", 1 }, {"IAPSR", 1 }, 14685 {"eapsr", 2 }, {"EAPSR", 2 }, 14686 {"psr", 3 }, {"PSR", 3 }, 14687 {"xpsr", 3 }, {"XPSR", 3 }, {"xPSR", 3 }, 14688 {"ipsr", 5 }, {"IPSR", 5 }, 14689 {"epsr", 6 }, {"EPSR", 6 }, 14690 {"iepsr", 7 }, {"IEPSR", 7 }, 14691 {"msp", 8 }, {"MSP", 8 }, 14692 {"psp", 9 }, {"PSP", 9 }, 14693 {"primask", 16}, {"PRIMASK", 16}, 14694 {"basepri", 17}, {"BASEPRI", 17}, 14695 {"basepri_max", 18}, {"BASEPRI_MAX", 18}, 14696 {"faultmask", 19}, {"FAULTMASK", 19}, 14697 {"control", 20}, {"CONTROL", 20} 14698}; 14699 14700/* Table of all shift-in-operand names. */ 14701static const struct asm_shift_name shift_names [] = 14702{ 14703 { "asl", SHIFT_LSL }, { "ASL", SHIFT_LSL }, 14704 { "lsl", SHIFT_LSL }, { "LSL", SHIFT_LSL }, 14705 { "lsr", SHIFT_LSR }, { "LSR", SHIFT_LSR }, 14706 { "asr", SHIFT_ASR }, { "ASR", SHIFT_ASR }, 14707 { "ror", SHIFT_ROR }, { "ROR", SHIFT_ROR }, 14708 { "rrx", SHIFT_RRX }, { "RRX", SHIFT_RRX } 14709}; 14710 14711/* Table of all explicit relocation names. */ 14712#ifdef OBJ_ELF 14713static struct reloc_entry reloc_names[] = 14714{ 14715 { "got", BFD_RELOC_ARM_GOT32 }, { "GOT", BFD_RELOC_ARM_GOT32 }, 14716 { "gotoff", BFD_RELOC_ARM_GOTOFF }, { "GOTOFF", BFD_RELOC_ARM_GOTOFF }, 14717 { "plt", BFD_RELOC_ARM_PLT32 }, { "PLT", BFD_RELOC_ARM_PLT32 }, 14718 { "target1", BFD_RELOC_ARM_TARGET1 }, { "TARGET1", BFD_RELOC_ARM_TARGET1 }, 14719 { "target2", BFD_RELOC_ARM_TARGET2 }, { "TARGET2", BFD_RELOC_ARM_TARGET2 }, 14720 { "sbrel", BFD_RELOC_ARM_SBREL32 }, { "SBREL", BFD_RELOC_ARM_SBREL32 }, 14721 { "tlsgd", BFD_RELOC_ARM_TLS_GD32}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32}, 14722 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32}, 14723 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32}, 14724 { "gottpoff",BFD_RELOC_ARM_TLS_IE32}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32}, 14725 { "tpoff", BFD_RELOC_ARM_TLS_LE32}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32} 14726}; 14727#endif 14728 14729/* Table of all conditional affixes. 0xF is not defined as a condition code. */ 14730static const struct asm_cond conds[] = 14731{ 14732 {"eq", 0x0}, 14733 {"ne", 0x1}, 14734 {"cs", 0x2}, {"hs", 0x2}, 14735 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3}, 14736 {"mi", 0x4}, 14737 {"pl", 0x5}, 14738 {"vs", 0x6}, 14739 {"vc", 0x7}, 14740 {"hi", 0x8}, 14741 {"ls", 0x9}, 14742 {"ge", 0xa}, 14743 {"lt", 0xb}, 14744 {"gt", 0xc}, 14745 {"le", 0xd}, 14746 {"al", 0xe} 14747}; 14748 14749static struct asm_barrier_opt barrier_opt_names[] = 14750{ 14751 { "sy", 0xf }, 14752 { "un", 0x7 }, 14753 { "st", 0xe }, 14754 { "unst", 0x6 }, 14755 { "ish", 0xb }, 14756 { "sh", 0xb }, 14757 { "ishst", 0xa }, 14758 { "shst", 0xa }, 14759 { "nsh", 0x7 }, 14760 { "nshst", 0x6 }, 14761 { "osh", 0x3 }, 14762 { "oshst", 0x2 } 14763}; 14764 14765/* Table of ARM-format instructions. */ 14766 14767/* Macros for gluing together operand strings. N.B. In all cases 14768 other than OPS0, the trailing OP_stop comes from default 14769 zero-initialization of the unspecified elements of the array. */ 14770#define OPS0() { OP_stop, } 14771#define OPS1(a) { OP_##a, } 14772#define OPS2(a,b) { OP_##a,OP_##b, } 14773#define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, } 14774#define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, } 14775#define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, } 14776#define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, } 14777 14778/* These macros abstract out the exact format of the mnemonic table and 14779 save some repeated characters. */ 14780 14781/* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */ 14782#define TxCE(mnem, op, top, nops, ops, ae, te) \ 14783 { #mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \ 14784 THUMB_VARIANT, do_##ae, do_##te } 14785 14786/* Two variants of the above - TCE for a numeric Thumb opcode, tCE for 14787 a T_MNEM_xyz enumerator. */ 14788#define TCE(mnem, aop, top, nops, ops, ae, te) \ 14789 TxCE(mnem, aop, 0x##top, nops, ops, ae, te) 14790#define tCE(mnem, aop, top, nops, ops, ae, te) \ 14791 TxCE(mnem, aop, T_MNEM_##top, nops, ops, ae, te) 14792 14793/* Second most common sort of mnemonic: has a Thumb variant, takes a conditional 14794 infix after the third character. */ 14795#define TxC3(mnem, op, top, nops, ops, ae, te) \ 14796 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \ 14797 THUMB_VARIANT, do_##ae, do_##te } 14798#define TxC3w(mnem, op, top, nops, ops, ae, te) \ 14799 { #mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \ 14800 THUMB_VARIANT, do_##ae, do_##te } 14801#define TC3(mnem, aop, top, nops, ops, ae, te) \ 14802 TxC3(mnem, aop, 0x##top, nops, ops, ae, te) 14803#define TC3w(mnem, aop, top, nops, ops, ae, te) \ 14804 TxC3w(mnem, aop, 0x##top, nops, ops, ae, te) 14805#define tC3(mnem, aop, top, nops, ops, ae, te) \ 14806 TxC3(mnem, aop, T_MNEM_##top, nops, ops, ae, te) 14807#define tC3w(mnem, aop, top, nops, ops, ae, te) \ 14808 TxC3w(mnem, aop, T_MNEM_##top, nops, ops, ae, te) 14809 14810/* Mnemonic with a conditional infix in an unusual place. Each and every variant has to 14811 appear in the condition table. */ 14812#define TxCM_(m1, m2, m3, op, top, nops, ops, ae, te) \ 14813 { #m1 #m2 #m3, OPS##nops ops, sizeof(#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof(#m1) - 1, \ 14814 0x##op, top, ARM_VARIANT, THUMB_VARIANT, do_##ae, do_##te } 14815 14816#define TxCM(m1, m2, op, top, nops, ops, ae, te) \ 14817 TxCM_(m1, , m2, op, top, nops, ops, ae, te), \ 14818 TxCM_(m1, eq, m2, op, top, nops, ops, ae, te), \ 14819 TxCM_(m1, ne, m2, op, top, nops, ops, ae, te), \ 14820 TxCM_(m1, cs, m2, op, top, nops, ops, ae, te), \ 14821 TxCM_(m1, hs, m2, op, top, nops, ops, ae, te), \ 14822 TxCM_(m1, cc, m2, op, top, nops, ops, ae, te), \ 14823 TxCM_(m1, ul, m2, op, top, nops, ops, ae, te), \ 14824 TxCM_(m1, lo, m2, op, top, nops, ops, ae, te), \ 14825 TxCM_(m1, mi, m2, op, top, nops, ops, ae, te), \ 14826 TxCM_(m1, pl, m2, op, top, nops, ops, ae, te), \ 14827 TxCM_(m1, vs, m2, op, top, nops, ops, ae, te), \ 14828 TxCM_(m1, vc, m2, op, top, nops, ops, ae, te), \ 14829 TxCM_(m1, hi, m2, op, top, nops, ops, ae, te), \ 14830 TxCM_(m1, ls, m2, op, top, nops, ops, ae, te), \ 14831 TxCM_(m1, ge, m2, op, top, nops, ops, ae, te), \ 14832 TxCM_(m1, lt, m2, op, top, nops, ops, ae, te), \ 14833 TxCM_(m1, gt, m2, op, top, nops, ops, ae, te), \ 14834 TxCM_(m1, le, m2, op, top, nops, ops, ae, te), \ 14835 TxCM_(m1, al, m2, op, top, nops, ops, ae, te) 14836 14837#define TCM(m1,m2, aop, top, nops, ops, ae, te) \ 14838 TxCM(m1,m2, aop, 0x##top, nops, ops, ae, te) 14839#define tCM(m1,m2, aop, top, nops, ops, ae, te) \ 14840 TxCM(m1,m2, aop, T_MNEM_##top, nops, ops, ae, te) 14841 14842/* Mnemonic that cannot be conditionalized. The ARM condition-code 14843 field is still 0xE. Many of the Thumb variants can be executed 14844 conditionally, so this is checked separately. */ 14845#define TUE(mnem, op, top, nops, ops, ae, te) \ 14846 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \ 14847 THUMB_VARIANT, do_##ae, do_##te } 14848 14849/* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM 14850 condition code field. */ 14851#define TUF(mnem, op, top, nops, ops, ae, te) \ 14852 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \ 14853 THUMB_VARIANT, do_##ae, do_##te } 14854 14855/* ARM-only variants of all the above. */ 14856#define CE(mnem, op, nops, ops, ae) \ 14857 { #mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL } 14858 14859#define C3(mnem, op, nops, ops, ae) \ 14860 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL } 14861 14862/* Legacy mnemonics that always have conditional infix after the third 14863 character. */ 14864#define CL(mnem, op, nops, ops, ae) \ 14865 { #mnem, OPS##nops ops, OT_cinfix3_legacy, \ 14866 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL } 14867 14868/* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */ 14869#define cCE(mnem, op, nops, ops, ae) \ 14870 { #mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae } 14871 14872/* Legacy coprocessor instructions where conditional infix and conditional 14873 suffix are ambiguous. For consistency this includes all FPA instructions, 14874 not just the potentially ambiguous ones. */ 14875#define cCL(mnem, op, nops, ops, ae) \ 14876 { #mnem, OPS##nops ops, OT_cinfix3_legacy, \ 14877 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae } 14878 14879/* Coprocessor, takes either a suffix or a position-3 infix 14880 (for an FPA corner case). */ 14881#define C3E(mnem, op, nops, ops, ae) \ 14882 { #mnem, OPS##nops ops, OT_csuf_or_in3, \ 14883 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae } 14884 14885#define xCM_(m1, m2, m3, op, nops, ops, ae) \ 14886 { #m1 #m2 #m3, OPS##nops ops, \ 14887 sizeof(#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof(#m1) - 1, \ 14888 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL } 14889 14890#define CM(m1, m2, op, nops, ops, ae) \ 14891 xCM_(m1, , m2, op, nops, ops, ae), \ 14892 xCM_(m1, eq, m2, op, nops, ops, ae), \ 14893 xCM_(m1, ne, m2, op, nops, ops, ae), \ 14894 xCM_(m1, cs, m2, op, nops, ops, ae), \ 14895 xCM_(m1, hs, m2, op, nops, ops, ae), \ 14896 xCM_(m1, cc, m2, op, nops, ops, ae), \ 14897 xCM_(m1, ul, m2, op, nops, ops, ae), \ 14898 xCM_(m1, lo, m2, op, nops, ops, ae), \ 14899 xCM_(m1, mi, m2, op, nops, ops, ae), \ 14900 xCM_(m1, pl, m2, op, nops, ops, ae), \ 14901 xCM_(m1, vs, m2, op, nops, ops, ae), \ 14902 xCM_(m1, vc, m2, op, nops, ops, ae), \ 14903 xCM_(m1, hi, m2, op, nops, ops, ae), \ 14904 xCM_(m1, ls, m2, op, nops, ops, ae), \ 14905 xCM_(m1, ge, m2, op, nops, ops, ae), \ 14906 xCM_(m1, lt, m2, op, nops, ops, ae), \ 14907 xCM_(m1, gt, m2, op, nops, ops, ae), \ 14908 xCM_(m1, le, m2, op, nops, ops, ae), \ 14909 xCM_(m1, al, m2, op, nops, ops, ae) 14910 14911#define UE(mnem, op, nops, ops, ae) \ 14912 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL } 14913 14914#define UF(mnem, op, nops, ops, ae) \ 14915 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL } 14916 14917/* Neon data-processing. ARM versions are unconditional with cond=0xf. 14918 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we 14919 use the same encoding function for each. */ 14920#define NUF(mnem, op, nops, ops, enc) \ 14921 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \ 14922 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc } 14923 14924/* Neon data processing, version which indirects through neon_enc_tab for 14925 the various overloaded versions of opcodes. */ 14926#define nUF(mnem, op, nops, ops, enc) \ 14927 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM_##op, N_MNEM_##op, \ 14928 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc } 14929 14930/* Neon insn with conditional suffix for the ARM version, non-overloaded 14931 version. */ 14932#define NCE_tag(mnem, op, nops, ops, enc, tag) \ 14933 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \ 14934 THUMB_VARIANT, do_##enc, do_##enc } 14935 14936#define NCE(mnem, op, nops, ops, enc) \ 14937 NCE_tag(mnem, op, nops, ops, enc, OT_csuffix) 14938 14939#define NCEF(mnem, op, nops, ops, enc) \ 14940 NCE_tag(mnem, op, nops, ops, enc, OT_csuffixF) 14941 14942/* Neon insn with conditional suffix for the ARM version, overloaded types. */ 14943#define nCE_tag(mnem, op, nops, ops, enc, tag) \ 14944 { #mnem, OPS##nops ops, tag, N_MNEM_##op, N_MNEM_##op, \ 14945 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc } 14946 14947#define nCE(mnem, op, nops, ops, enc) \ 14948 nCE_tag(mnem, op, nops, ops, enc, OT_csuffix) 14949 14950#define nCEF(mnem, op, nops, ops, enc) \ 14951 nCE_tag(mnem, op, nops, ops, enc, OT_csuffixF) 14952 14953#define do_0 0 14954 14955/* Thumb-only, unconditional. */ 14956#define UT(mnem, op, nops, ops, te) TUE(mnem, 0, op, nops, ops, 0, te) 14957 14958static const struct asm_opcode insns[] = 14959{ 14960#define ARM_VARIANT &arm_ext_v1 /* Core ARM Instructions. */ 14961#define THUMB_VARIANT &arm_ext_v4t 14962 tCE(and, 0000000, and, 3, (RR, oRR, SH), arit, t_arit3c), 14963 tC3(ands, 0100000, ands, 3, (RR, oRR, SH), arit, t_arit3c), 14964 tCE(eor, 0200000, eor, 3, (RR, oRR, SH), arit, t_arit3c), 14965 tC3(eors, 0300000, eors, 3, (RR, oRR, SH), arit, t_arit3c), 14966 tCE(sub, 0400000, sub, 3, (RR, oRR, SH), arit, t_add_sub), 14967 tC3(subs, 0500000, subs, 3, (RR, oRR, SH), arit, t_add_sub), 14968 tCE(add, 0800000, add, 3, (RR, oRR, SHG), arit, t_add_sub), 14969 tC3(adds, 0900000, adds, 3, (RR, oRR, SHG), arit, t_add_sub), 14970 tCE(adc, 0a00000, adc, 3, (RR, oRR, SH), arit, t_arit3c), 14971 tC3(adcs, 0b00000, adcs, 3, (RR, oRR, SH), arit, t_arit3c), 14972 tCE(sbc, 0c00000, sbc, 3, (RR, oRR, SH), arit, t_arit3), 14973 tC3(sbcs, 0d00000, sbcs, 3, (RR, oRR, SH), arit, t_arit3), 14974 tCE(orr, 1800000, orr, 3, (RR, oRR, SH), arit, t_arit3c), 14975 tC3(orrs, 1900000, orrs, 3, (RR, oRR, SH), arit, t_arit3c), 14976 tCE(bic, 1c00000, bic, 3, (RR, oRR, SH), arit, t_arit3), 14977 tC3(bics, 1d00000, bics, 3, (RR, oRR, SH), arit, t_arit3), 14978 14979 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism 14980 for setting PSR flag bits. They are obsolete in V6 and do not 14981 have Thumb equivalents. */ 14982 tCE(tst, 1100000, tst, 2, (RR, SH), cmp, t_mvn_tst), 14983 tC3w(tsts, 1100000, tst, 2, (RR, SH), cmp, t_mvn_tst), 14984 CL(tstp, 110f000, 2, (RR, SH), cmp), 14985 tCE(cmp, 1500000, cmp, 2, (RR, SH), cmp, t_mov_cmp), 14986 tC3w(cmps, 1500000, cmp, 2, (RR, SH), cmp, t_mov_cmp), 14987 CL(cmpp, 150f000, 2, (RR, SH), cmp), 14988 tCE(cmn, 1700000, cmn, 2, (RR, SH), cmp, t_mvn_tst), 14989 tC3w(cmns, 1700000, cmn, 2, (RR, SH), cmp, t_mvn_tst), 14990 CL(cmnp, 170f000, 2, (RR, SH), cmp), 14991 14992 tCE(mov, 1a00000, mov, 2, (RR, SH), mov, t_mov_cmp), 14993 tC3(movs, 1b00000, movs, 2, (RR, SH), mov, t_mov_cmp), 14994 tCE(mvn, 1e00000, mvn, 2, (RR, SH), mov, t_mvn_tst), 14995 tC3(mvns, 1f00000, mvns, 2, (RR, SH), mov, t_mvn_tst), 14996 14997 tCE(ldr, 4100000, ldr, 2, (RR, ADDRGLDR),ldst, t_ldst), 14998 tC3(ldrb, 4500000, ldrb, 2, (RR, ADDRGLDR),ldst, t_ldst), 14999 tCE(str, 4000000, str, 2, (RR, ADDRGLDR),ldst, t_ldst), 15000 tC3(strb, 4400000, strb, 2, (RR, ADDRGLDR),ldst, t_ldst), 15001 15002 tCE(stm, 8800000, stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), 15003 tC3(stmia, 8800000, stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), 15004 tC3(stmea, 8800000, stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), 15005 tCE(ldm, 8900000, ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), 15006 tC3(ldmia, 8900000, ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), 15007 tC3(ldmfd, 8900000, ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), 15008 15009 TCE(swi, f000000, df00, 1, (EXPi), swi, t_swi), 15010 TCE(svc, f000000, df00, 1, (EXPi), swi, t_swi), 15011 tCE(b, a000000, b, 1, (EXPr), branch, t_branch), 15012 TCE(bl, b000000, f000f800, 1, (EXPr), bl, t_branch23), 15013 15014 /* Pseudo ops. */ 15015 tCE(adr, 28f0000, adr, 2, (RR, EXP), adr, t_adr), 15016 C3(adrl, 28f0000, 2, (RR, EXP), adrl), 15017 tCE(nop, 1a00000, nop, 1, (oI255c), nop, t_nop), 15018 15019 /* Thumb-compatibility pseudo ops. */ 15020 tCE(lsl, 1a00000, lsl, 3, (RR, oRR, SH), shift, t_shift), 15021 tC3(lsls, 1b00000, lsls, 3, (RR, oRR, SH), shift, t_shift), 15022 tCE(lsr, 1a00020, lsr, 3, (RR, oRR, SH), shift, t_shift), 15023 tC3(lsrs, 1b00020, lsrs, 3, (RR, oRR, SH), shift, t_shift), 15024 tCE(asr, 1a00040, asr, 3, (RR, oRR, SH), shift, t_shift), 15025 tC3(asrs, 1b00040, asrs, 3, (RR, oRR, SH), shift, t_shift), 15026 tCE(ror, 1a00060, ror, 3, (RR, oRR, SH), shift, t_shift), 15027 tC3(rors, 1b00060, rors, 3, (RR, oRR, SH), shift, t_shift), 15028 tCE(neg, 2600000, neg, 2, (RR, RR), rd_rn, t_neg), 15029 tC3(negs, 2700000, negs, 2, (RR, RR), rd_rn, t_neg), 15030 tCE(push, 92d0000, push, 1, (REGLST), push_pop, t_push_pop), 15031 tCE(pop, 8bd0000, pop, 1, (REGLST), push_pop, t_push_pop), 15032 15033 /* These may simplify to neg. */ 15034 TCE(rsb, 0600000, ebc00000, 3, (RR, oRR, SH), arit, t_rsb), 15035 TC3(rsbs, 0700000, ebd00000, 3, (RR, oRR, SH), arit, t_rsb), 15036 15037 TCE(rrx, 1a00060, ea4f0030, 2, (RR, RR), rd_rm, t_rd_rm), 15038 TCE(rrxs, 1b00060, ea5f0030, 2, (RR, RR), rd_rm, t_rd_rm), 15039 15040#undef THUMB_VARIANT 15041#define THUMB_VARIANT &arm_ext_v6 15042 TCE(cpy, 1a00000, 4600, 2, (RR, RR), rd_rm, t_cpy), 15043 15044 /* V1 instructions with no Thumb analogue prior to V6T2. */ 15045#undef THUMB_VARIANT 15046#define THUMB_VARIANT &arm_ext_v6t2 15047 TCE(teq, 1300000, ea900f00, 2, (RR, SH), cmp, t_mvn_tst), 15048 TC3w(teqs, 1300000, ea900f00, 2, (RR, SH), cmp, t_mvn_tst), 15049 CL(teqp, 130f000, 2, (RR, SH), cmp), 15050 15051 TC3(ldrt, 4300000, f8500e00, 2, (RR, ADDR), ldstt, t_ldstt), 15052 TC3(ldrbt, 4700000, f8100e00, 2, (RR, ADDR), ldstt, t_ldstt), 15053 TC3(strt, 4200000, f8400e00, 2, (RR, ADDR), ldstt, t_ldstt), 15054 TC3(strbt, 4600000, f8000e00, 2, (RR, ADDR), ldstt, t_ldstt), 15055 15056 TC3(stmdb, 9000000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm), 15057 TC3(stmfd, 9000000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm), 15058 15059 TC3(ldmdb, 9100000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm), 15060 TC3(ldmea, 9100000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm), 15061 15062 /* V1 instructions with no Thumb analogue at all. */ 15063 CE(rsc, 0e00000, 3, (RR, oRR, SH), arit), 15064 C3(rscs, 0f00000, 3, (RR, oRR, SH), arit), 15065 15066 C3(stmib, 9800000, 2, (RRw, REGLST), ldmstm), 15067 C3(stmfa, 9800000, 2, (RRw, REGLST), ldmstm), 15068 C3(stmda, 8000000, 2, (RRw, REGLST), ldmstm), 15069 C3(stmed, 8000000, 2, (RRw, REGLST), ldmstm), 15070 C3(ldmib, 9900000, 2, (RRw, REGLST), ldmstm), 15071 C3(ldmed, 9900000, 2, (RRw, REGLST), ldmstm), 15072 C3(ldmda, 8100000, 2, (RRw, REGLST), ldmstm), 15073 C3(ldmfa, 8100000, 2, (RRw, REGLST), ldmstm), 15074 15075#undef ARM_VARIANT 15076#define ARM_VARIANT &arm_ext_v2 /* ARM 2 - multiplies. */ 15077#undef THUMB_VARIANT 15078#define THUMB_VARIANT &arm_ext_v4t 15079 tCE(mul, 0000090, mul, 3, (RRnpc, RRnpc, oRR), mul, t_mul), 15080 tC3(muls, 0100090, muls, 3, (RRnpc, RRnpc, oRR), mul, t_mul), 15081 15082#undef THUMB_VARIANT 15083#define THUMB_VARIANT &arm_ext_v6t2 15084 TCE(mla, 0200090, fb000000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla), 15085 C3(mlas, 0300090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas), 15086 15087 /* Generic coprocessor instructions. */ 15088 TCE(cdp, e000000, ee000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp, cdp), 15089 TCE(ldc, c100000, ec100000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), 15090 TC3(ldcl, c500000, ec500000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), 15091 TCE(stc, c000000, ec000000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), 15092 TC3(stcl, c400000, ec400000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), 15093 TCE(mcr, e000010, ee000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg), 15094 TCE(mrc, e100010, ee100010, 6, (RCP, I7b, APSR_RR, RCN, RCN, oI7b), co_reg, co_reg), 15095 15096#undef ARM_VARIANT 15097#define ARM_VARIANT &arm_ext_v2s /* ARM 3 - swp instructions. */ 15098 CE(swp, 1000090, 3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn), 15099 C3(swpb, 1400090, 3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn), 15100 15101#undef ARM_VARIANT 15102#define ARM_VARIANT &arm_ext_v3 /* ARM 6 Status register instructions. */ 15103 TCE(mrs, 10f0000, f3ef8000, 2, (APSR_RR, RVC_PSR), mrs, t_mrs), 15104 TCE(msr, 120f000, f3808000, 2, (RVC_PSR, RR_EXi), msr, t_msr), 15105 15106#undef ARM_VARIANT 15107#define ARM_VARIANT &arm_ext_v3m /* ARM 7M long multiplies. */ 15108 TCE(smull, 0c00090, fb800000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull), 15109 CM(smull,s, 0d00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull), 15110 TCE(umull, 0800090, fba00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull), 15111 CM(umull,s, 0900090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull), 15112 TCE(smlal, 0e00090, fbc00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull), 15113 CM(smlal,s, 0f00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull), 15114 TCE(umlal, 0a00090, fbe00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull), 15115 CM(umlal,s, 0b00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull), 15116 15117#undef ARM_VARIANT 15118#define ARM_VARIANT &arm_ext_v4 /* ARM Architecture 4. */ 15119#undef THUMB_VARIANT 15120#define THUMB_VARIANT &arm_ext_v4t 15121 tC3(ldrh, 01000b0, ldrh, 2, (RR, ADDRGLDRS), ldstv4, t_ldst), 15122 tC3(strh, 00000b0, strh, 2, (RR, ADDRGLDRS), ldstv4, t_ldst), 15123 tC3(ldrsh, 01000f0, ldrsh, 2, (RR, ADDRGLDRS), ldstv4, t_ldst), 15124 tC3(ldrsb, 01000d0, ldrsb, 2, (RR, ADDRGLDRS), ldstv4, t_ldst), 15125 tCM(ld,sh, 01000f0, ldrsh, 2, (RR, ADDRGLDRS), ldstv4, t_ldst), 15126 tCM(ld,sb, 01000d0, ldrsb, 2, (RR, ADDRGLDRS), ldstv4, t_ldst), 15127 15128#undef ARM_VARIANT 15129#define ARM_VARIANT &arm_ext_v4t_5 15130 /* ARM Architecture 4T. */ 15131 /* Note: bx (and blx) are required on V5, even if the processor does 15132 not support Thumb. */ 15133 TCE(bx, 12fff10, 4700, 1, (RR), bx, t_bx), 15134 15135#undef ARM_VARIANT 15136#define ARM_VARIANT &arm_ext_v5 /* ARM Architecture 5T. */ 15137#undef THUMB_VARIANT 15138#define THUMB_VARIANT &arm_ext_v5t 15139 /* Note: blx has 2 variants; the .value coded here is for 15140 BLX(2). Only this variant has conditional execution. */ 15141 TCE(blx, 12fff30, 4780, 1, (RR_EXr), blx, t_blx), 15142 TUE(bkpt, 1200070, be00, 1, (oIffffb), bkpt, t_bkpt), 15143 15144#undef THUMB_VARIANT 15145#define THUMB_VARIANT &arm_ext_v6t2 15146 TCE(clz, 16f0f10, fab0f080, 2, (RRnpc, RRnpc), rd_rm, t_clz), 15147 TUF(ldc2, c100000, fc100000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), 15148 TUF(ldc2l, c500000, fc500000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), 15149 TUF(stc2, c000000, fc000000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), 15150 TUF(stc2l, c400000, fc400000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), 15151 TUF(cdp2, e000000, fe000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp, cdp), 15152 TUF(mcr2, e000010, fe000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg), 15153 TUF(mrc2, e100010, fe100010, 6, (RCP, I7b, APSR_RR, RCN, RCN, oI7b), co_reg, co_reg), 15154 15155#undef ARM_VARIANT 15156#define ARM_VARIANT &arm_ext_v5exp /* ARM Architecture 5TExP. */ 15157 TCE(smlabb, 1000080, fb100000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), 15158 TCE(smlatb, 10000a0, fb100020, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), 15159 TCE(smlabt, 10000c0, fb100010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), 15160 TCE(smlatt, 10000e0, fb100030, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), 15161 15162 TCE(smlawb, 1200080, fb300000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), 15163 TCE(smlawt, 12000c0, fb300010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), 15164 15165 TCE(smlalbb, 1400080, fbc00080, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal), 15166 TCE(smlaltb, 14000a0, fbc000a0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal), 15167 TCE(smlalbt, 14000c0, fbc00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal), 15168 TCE(smlaltt, 14000e0, fbc000b0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal), 15169 15170 TCE(smulbb, 1600080, fb10f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), 15171 TCE(smultb, 16000a0, fb10f020, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), 15172 TCE(smulbt, 16000c0, fb10f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), 15173 TCE(smultt, 16000e0, fb10f030, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), 15174 15175 TCE(smulwb, 12000a0, fb30f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), 15176 TCE(smulwt, 12000e0, fb30f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), 15177 15178 TCE(qadd, 1000050, fa80f080, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, rd_rm_rn), 15179 TCE(qdadd, 1400050, fa80f090, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, rd_rm_rn), 15180 TCE(qsub, 1200050, fa80f0a0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, rd_rm_rn), 15181 TCE(qdsub, 1600050, fa80f0b0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, rd_rm_rn), 15182 15183#undef ARM_VARIANT 15184#define ARM_VARIANT &arm_ext_v5e /* ARM Architecture 5TE. */ 15185 TUF(pld, 450f000, f810f000, 1, (ADDR), pld, t_pld), 15186 TC3(ldrd, 00000d0, e8500000, 3, (RRnpc, oRRnpc, ADDRGLDRS), ldrd, t_ldstd), 15187 TC3(strd, 00000f0, e8400000, 3, (RRnpc, oRRnpc, ADDRGLDRS), ldrd, t_ldstd), 15188 15189 TCE(mcrr, c400000, ec400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c), 15190 TCE(mrrc, c500000, ec500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c), 15191 15192#undef ARM_VARIANT 15193#define ARM_VARIANT &arm_ext_v5j /* ARM Architecture 5TEJ. */ 15194 TCE(bxj, 12fff20, f3c08f00, 1, (RR), bxj, t_bxj), 15195 15196#undef ARM_VARIANT 15197#define ARM_VARIANT &arm_ext_v6 /* ARM V6. */ 15198#undef THUMB_VARIANT 15199#define THUMB_VARIANT &arm_ext_v6 15200 TUF(cpsie, 1080000, b660, 2, (CPSF, oI31b), cpsi, t_cpsi), 15201 TUF(cpsid, 10c0000, b670, 2, (CPSF, oI31b), cpsi, t_cpsi), 15202 tCE(rev, 6bf0f30, rev, 2, (RRnpc, RRnpc), rd_rm, t_rev), 15203 tCE(rev16, 6bf0fb0, rev16, 2, (RRnpc, RRnpc), rd_rm, t_rev), 15204 tCE(revsh, 6ff0fb0, revsh, 2, (RRnpc, RRnpc), rd_rm, t_rev), 15205 tCE(sxth, 6bf0070, sxth, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), 15206 tCE(uxth, 6ff0070, uxth, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), 15207 tCE(sxtb, 6af0070, sxtb, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), 15208 tCE(uxtb, 6ef0070, uxtb, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), 15209 TUF(setend, 1010000, b650, 1, (ENDI), setend, t_setend), 15210 15211#undef THUMB_VARIANT 15212#define THUMB_VARIANT &arm_ext_v6t2 15213 TCE(ldrex, 1900f9f, e8500f00, 2, (RRnpc, ADDR), ldrex, t_ldrex), 15214 TCE(strex, 1800f90, e8400000, 3, (RRnpc, RRnpc, ADDR), strex, t_strex), 15215 TUF(mcrr2, c400000, fc400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c), 15216 TUF(mrrc2, c500000, fc500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c), 15217 15218 TCE(ssat, 6a00010, f3000000, 4, (RRnpc, I32, RRnpc, oSHllar),ssat, t_ssat), 15219 TCE(usat, 6e00010, f3800000, 4, (RRnpc, I31, RRnpc, oSHllar),usat, t_usat), 15220 15221/* ARM V6 not included in V7M (eg. integer SIMD). */ 15222#undef THUMB_VARIANT 15223#define THUMB_VARIANT &arm_ext_v6_notm 15224 TUF(cps, 1020000, f3af8100, 1, (I31b), imm0, t_cps), 15225 TCE(pkhbt, 6800010, eac00000, 4, (RRnpc, RRnpc, RRnpc, oSHll), pkhbt, t_pkhbt), 15226 TCE(pkhtb, 6800050, eac00020, 4, (RRnpc, RRnpc, RRnpc, oSHar), pkhtb, t_pkhtb), 15227 TCE(qadd16, 6200f10, fa90f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15228 TCE(qadd8, 6200f90, fa80f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15229 TCE(qaddsubx, 6200f30, faa0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15230 TCE(qsub16, 6200f70, fad0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15231 TCE(qsub8, 6200ff0, fac0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15232 TCE(qsubaddx, 6200f50, fae0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15233 TCE(sadd16, 6100f10, fa90f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15234 TCE(sadd8, 6100f90, fa80f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15235 TCE(saddsubx, 6100f30, faa0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15236 TCE(shadd16, 6300f10, fa90f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15237 TCE(shadd8, 6300f90, fa80f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15238 TCE(shaddsubx, 6300f30, faa0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15239 TCE(shsub16, 6300f70, fad0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15240 TCE(shsub8, 6300ff0, fac0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15241 TCE(shsubaddx, 6300f50, fae0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15242 TCE(ssub16, 6100f70, fad0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15243 TCE(ssub8, 6100ff0, fac0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15244 TCE(ssubaddx, 6100f50, fae0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15245 TCE(uadd16, 6500f10, fa90f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15246 TCE(uadd8, 6500f90, fa80f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15247 TCE(uaddsubx, 6500f30, faa0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15248 TCE(uhadd16, 6700f10, fa90f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15249 TCE(uhadd8, 6700f90, fa80f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15250 TCE(uhaddsubx, 6700f30, faa0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15251 TCE(uhsub16, 6700f70, fad0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15252 TCE(uhsub8, 6700ff0, fac0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15253 TCE(uhsubaddx, 6700f50, fae0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15254 TCE(uqadd16, 6600f10, fa90f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15255 TCE(uqadd8, 6600f90, fa80f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15256 TCE(uqaddsubx, 6600f30, faa0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15257 TCE(uqsub16, 6600f70, fad0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15258 TCE(uqsub8, 6600ff0, fac0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15259 TCE(uqsubaddx, 6600f50, fae0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15260 TCE(usub16, 6500f70, fad0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15261 TCE(usub8, 6500ff0, fac0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15262 TCE(usubaddx, 6500f50, fae0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15263 TUF(rfeia, 8900a00, e990c000, 1, (RRw), rfe, rfe), 15264 UF(rfeib, 9900a00, 1, (RRw), rfe), 15265 UF(rfeda, 8100a00, 1, (RRw), rfe), 15266 TUF(rfedb, 9100a00, e810c000, 1, (RRw), rfe, rfe), 15267 TUF(rfefd, 8900a00, e990c000, 1, (RRw), rfe, rfe), 15268 UF(rfefa, 9900a00, 1, (RRw), rfe), 15269 UF(rfeea, 8100a00, 1, (RRw), rfe), 15270 TUF(rfeed, 9100a00, e810c000, 1, (RRw), rfe, rfe), 15271 TCE(sxtah, 6b00070, fa00f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), 15272 TCE(sxtab16, 6800070, fa20f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), 15273 TCE(sxtab, 6a00070, fa40f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), 15274 TCE(sxtb16, 68f0070, fa2ff080, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), 15275 TCE(uxtah, 6f00070, fa10f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), 15276 TCE(uxtab16, 6c00070, fa30f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), 15277 TCE(uxtab, 6e00070, fa50f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), 15278 TCE(uxtb16, 6cf0070, fa3ff080, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), 15279 TCE(sel, 6800fb0, faa0f080, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15280 TCE(smlad, 7000010, fb200000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), 15281 TCE(smladx, 7000030, fb200010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), 15282 TCE(smlald, 7400010, fbc000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal), 15283 TCE(smlaldx, 7400030, fbc000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal), 15284 TCE(smlsd, 7000050, fb400000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), 15285 TCE(smlsdx, 7000070, fb400010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), 15286 TCE(smlsld, 7400050, fbd000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal), 15287 TCE(smlsldx, 7400070, fbd000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal), 15288 TCE(smmla, 7500010, fb500000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), 15289 TCE(smmlar, 7500030, fb500010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), 15290 TCE(smmls, 75000d0, fb600000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), 15291 TCE(smmlsr, 75000f0, fb600010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), 15292 TCE(smmul, 750f010, fb50f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), 15293 TCE(smmulr, 750f030, fb50f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), 15294 TCE(smuad, 700f010, fb20f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), 15295 TCE(smuadx, 700f030, fb20f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), 15296 TCE(smusd, 700f050, fb40f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), 15297 TCE(smusdx, 700f070, fb40f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), 15298 TUF(srsia, 8c00500, e980c000, 2, (oRRw, I31w), srs, srs), 15299 UF(srsib, 9c00500, 2, (oRRw, I31w), srs), 15300 UF(srsda, 8400500, 2, (oRRw, I31w), srs), 15301 TUF(srsdb, 9400500, e800c000, 2, (oRRw, I31w), srs, srs), 15302 TCE(ssat16, 6a00f30, f3200000, 3, (RRnpc, I16, RRnpc), ssat16, t_ssat16), 15303 TCE(umaal, 0400090, fbe00060, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal, t_mlal), 15304 TCE(usad8, 780f010, fb70f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), 15305 TCE(usada8, 7800010, fb700000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), 15306 TCE(usat16, 6e00f30, f3a00000, 3, (RRnpc, I15, RRnpc), usat16, t_usat16), 15307 15308#undef ARM_VARIANT 15309#define ARM_VARIANT &arm_ext_v6k 15310#undef THUMB_VARIANT 15311#define THUMB_VARIANT &arm_ext_v6k 15312 tCE(yield, 320f001, yield, 0, (), noargs, t_hint), 15313 tCE(wfe, 320f002, wfe, 0, (), noargs, t_hint), 15314 tCE(wfi, 320f003, wfi, 0, (), noargs, t_hint), 15315 tCE(sev, 320f004, sev, 0, (), noargs, t_hint), 15316 15317#undef THUMB_VARIANT 15318#define THUMB_VARIANT &arm_ext_v6_notm 15319 TCE(ldrexd, 1b00f9f, e8d0007f, 3, (RRnpc, oRRnpc, RRnpcb), ldrexd, t_ldrexd), 15320 TCE(strexd, 1a00f90, e8c00070, 4, (RRnpc, RRnpc, oRRnpc, RRnpcb), strexd, t_strexd), 15321 15322#undef THUMB_VARIANT 15323#define THUMB_VARIANT &arm_ext_v6t2 15324 TCE(ldrexb, 1d00f9f, e8d00f4f, 2, (RRnpc, RRnpcb), rd_rn, rd_rn), 15325 TCE(ldrexh, 1f00f9f, e8d00f5f, 2, (RRnpc, RRnpcb), rd_rn, rd_rn), 15326 TCE(strexb, 1c00f90, e8c00f40, 3, (RRnpc, RRnpc, ADDR), strex, rm_rd_rn), 15327 TCE(strexh, 1e00f90, e8c00f50, 3, (RRnpc, RRnpc, ADDR), strex, rm_rd_rn), 15328 TUF(clrex, 57ff01f, f3bf8f2f, 0, (), noargs, noargs), 15329 15330#undef ARM_VARIANT 15331#define ARM_VARIANT &arm_ext_v6z 15332 TCE(smc, 1600070, f7f08000, 1, (EXPi), smc, t_smc), 15333 15334#undef ARM_VARIANT 15335#define ARM_VARIANT &arm_ext_v6t2 15336 TCE(bfc, 7c0001f, f36f0000, 3, (RRnpc, I31, I32), bfc, t_bfc), 15337 TCE(bfi, 7c00010, f3600000, 4, (RRnpc, RRnpc_I0, I31, I32), bfi, t_bfi), 15338 TCE(sbfx, 7a00050, f3400000, 4, (RR, RR, I31, I32), bfx, t_bfx), 15339 TCE(ubfx, 7e00050, f3c00000, 4, (RR, RR, I31, I32), bfx, t_bfx), 15340 15341 TCE(mls, 0600090, fb000010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla), 15342 TCE(movw, 3000000, f2400000, 2, (RRnpc, HALF), mov16, t_mov16), 15343 TCE(movt, 3400000, f2c00000, 2, (RRnpc, HALF), mov16, t_mov16), 15344 TCE(rbit, 6ff0f30, fa90f0a0, 2, (RR, RR), rd_rm, t_rbit), 15345 15346 TC3(ldrht, 03000b0, f8300e00, 2, (RR, ADDR), ldsttv4, t_ldstt), 15347 TC3(ldrsht, 03000f0, f9300e00, 2, (RR, ADDR), ldsttv4, t_ldstt), 15348 TC3(ldrsbt, 03000d0, f9100e00, 2, (RR, ADDR), ldsttv4, t_ldstt), 15349 TC3(strht, 02000b0, f8200e00, 2, (RR, ADDR), ldsttv4, t_ldstt), 15350 15351 UT(cbnz, b900, 2, (RR, EXP), t_cbz), 15352 UT(cbz, b100, 2, (RR, EXP), t_cbz), 15353 /* ARM does not really have an IT instruction, so always allow it. */ 15354#undef ARM_VARIANT 15355#define ARM_VARIANT &arm_ext_v1 15356 TUE(it, 0, bf08, 1, (COND), it, t_it), 15357 TUE(itt, 0, bf0c, 1, (COND), it, t_it), 15358 TUE(ite, 0, bf04, 1, (COND), it, t_it), 15359 TUE(ittt, 0, bf0e, 1, (COND), it, t_it), 15360 TUE(itet, 0, bf06, 1, (COND), it, t_it), 15361 TUE(itte, 0, bf0a, 1, (COND), it, t_it), 15362 TUE(itee, 0, bf02, 1, (COND), it, t_it), 15363 TUE(itttt, 0, bf0f, 1, (COND), it, t_it), 15364 TUE(itett, 0, bf07, 1, (COND), it, t_it), 15365 TUE(ittet, 0, bf0b, 1, (COND), it, t_it), 15366 TUE(iteet, 0, bf03, 1, (COND), it, t_it), 15367 TUE(ittte, 0, bf0d, 1, (COND), it, t_it), 15368 TUE(itete, 0, bf05, 1, (COND), it, t_it), 15369 TUE(ittee, 0, bf09, 1, (COND), it, t_it), 15370 TUE(iteee, 0, bf01, 1, (COND), it, t_it), 15371 15372 /* Thumb2 only instructions. */ 15373#undef ARM_VARIANT 15374#define ARM_VARIANT NULL 15375 15376 TCE(addw, 0, f2000000, 3, (RR, RR, EXPi), 0, t_add_sub_w), 15377 TCE(subw, 0, f2a00000, 3, (RR, RR, EXPi), 0, t_add_sub_w), 15378 TCE(tbb, 0, e8d0f000, 1, (TB), 0, t_tb), 15379 TCE(tbh, 0, e8d0f010, 1, (TB), 0, t_tb), 15380 15381 /* Thumb-2 hardware division instructions (R and M profiles only). */ 15382#undef THUMB_VARIANT 15383#define THUMB_VARIANT &arm_ext_div 15384 TCE(sdiv, 0, fb90f0f0, 3, (RR, oRR, RR), 0, t_div), 15385 TCE(udiv, 0, fbb0f0f0, 3, (RR, oRR, RR), 0, t_div), 15386 15387 /* ARM V7 instructions. */ 15388#undef ARM_VARIANT 15389#define ARM_VARIANT &arm_ext_v7 15390#undef THUMB_VARIANT 15391#define THUMB_VARIANT &arm_ext_v7 15392 TUF(pli, 450f000, f910f000, 1, (ADDR), pli, t_pld), 15393 TCE(dbg, 320f0f0, f3af80f0, 1, (I15), dbg, t_dbg), 15394 TUF(dmb, 57ff050, f3bf8f50, 1, (oBARRIER), barrier, t_barrier), 15395 TUF(dsb, 57ff040, f3bf8f40, 1, (oBARRIER), barrier, t_barrier), 15396 TUF(isb, 57ff060, f3bf8f60, 1, (oBARRIER), barrier, t_barrier), 15397 15398#undef ARM_VARIANT 15399#define ARM_VARIANT &fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */ 15400 cCE(wfs, e200110, 1, (RR), rd), 15401 cCE(rfs, e300110, 1, (RR), rd), 15402 cCE(wfc, e400110, 1, (RR), rd), 15403 cCE(rfc, e500110, 1, (RR), rd), 15404 15405 cCL(ldfs, c100100, 2, (RF, ADDRGLDC), rd_cpaddr), 15406 cCL(ldfd, c108100, 2, (RF, ADDRGLDC), rd_cpaddr), 15407 cCL(ldfe, c500100, 2, (RF, ADDRGLDC), rd_cpaddr), 15408 cCL(ldfp, c508100, 2, (RF, ADDRGLDC), rd_cpaddr), 15409 15410 cCL(stfs, c000100, 2, (RF, ADDRGLDC), rd_cpaddr), 15411 cCL(stfd, c008100, 2, (RF, ADDRGLDC), rd_cpaddr), 15412 cCL(stfe, c400100, 2, (RF, ADDRGLDC), rd_cpaddr), 15413 cCL(stfp, c408100, 2, (RF, ADDRGLDC), rd_cpaddr), 15414 15415 cCL(mvfs, e008100, 2, (RF, RF_IF), rd_rm), 15416 cCL(mvfsp, e008120, 2, (RF, RF_IF), rd_rm), 15417 cCL(mvfsm, e008140, 2, (RF, RF_IF), rd_rm), 15418 cCL(mvfsz, e008160, 2, (RF, RF_IF), rd_rm), 15419 cCL(mvfd, e008180, 2, (RF, RF_IF), rd_rm), 15420 cCL(mvfdp, e0081a0, 2, (RF, RF_IF), rd_rm), 15421 cCL(mvfdm, e0081c0, 2, (RF, RF_IF), rd_rm), 15422 cCL(mvfdz, e0081e0, 2, (RF, RF_IF), rd_rm), 15423 cCL(mvfe, e088100, 2, (RF, RF_IF), rd_rm), 15424 cCL(mvfep, e088120, 2, (RF, RF_IF), rd_rm), 15425 cCL(mvfem, e088140, 2, (RF, RF_IF), rd_rm), 15426 cCL(mvfez, e088160, 2, (RF, RF_IF), rd_rm), 15427 15428 cCL(mnfs, e108100, 2, (RF, RF_IF), rd_rm), 15429 cCL(mnfsp, e108120, 2, (RF, RF_IF), rd_rm), 15430 cCL(mnfsm, e108140, 2, (RF, RF_IF), rd_rm), 15431 cCL(mnfsz, e108160, 2, (RF, RF_IF), rd_rm), 15432 cCL(mnfd, e108180, 2, (RF, RF_IF), rd_rm), 15433 cCL(mnfdp, e1081a0, 2, (RF, RF_IF), rd_rm), 15434 cCL(mnfdm, e1081c0, 2, (RF, RF_IF), rd_rm), 15435 cCL(mnfdz, e1081e0, 2, (RF, RF_IF), rd_rm), 15436 cCL(mnfe, e188100, 2, (RF, RF_IF), rd_rm), 15437 cCL(mnfep, e188120, 2, (RF, RF_IF), rd_rm), 15438 cCL(mnfem, e188140, 2, (RF, RF_IF), rd_rm), 15439 cCL(mnfez, e188160, 2, (RF, RF_IF), rd_rm), 15440 15441 cCL(abss, e208100, 2, (RF, RF_IF), rd_rm), 15442 cCL(abssp, e208120, 2, (RF, RF_IF), rd_rm), 15443 cCL(abssm, e208140, 2, (RF, RF_IF), rd_rm), 15444 cCL(abssz, e208160, 2, (RF, RF_IF), rd_rm), 15445 cCL(absd, e208180, 2, (RF, RF_IF), rd_rm), 15446 cCL(absdp, e2081a0, 2, (RF, RF_IF), rd_rm), 15447 cCL(absdm, e2081c0, 2, (RF, RF_IF), rd_rm), 15448 cCL(absdz, e2081e0, 2, (RF, RF_IF), rd_rm), 15449 cCL(abse, e288100, 2, (RF, RF_IF), rd_rm), 15450 cCL(absep, e288120, 2, (RF, RF_IF), rd_rm), 15451 cCL(absem, e288140, 2, (RF, RF_IF), rd_rm), 15452 cCL(absez, e288160, 2, (RF, RF_IF), rd_rm), 15453 15454 cCL(rnds, e308100, 2, (RF, RF_IF), rd_rm), 15455 cCL(rndsp, e308120, 2, (RF, RF_IF), rd_rm), 15456 cCL(rndsm, e308140, 2, (RF, RF_IF), rd_rm), 15457 cCL(rndsz, e308160, 2, (RF, RF_IF), rd_rm), 15458 cCL(rndd, e308180, 2, (RF, RF_IF), rd_rm), 15459 cCL(rnddp, e3081a0, 2, (RF, RF_IF), rd_rm), 15460 cCL(rnddm, e3081c0, 2, (RF, RF_IF), rd_rm), 15461 cCL(rnddz, e3081e0, 2, (RF, RF_IF), rd_rm), 15462 cCL(rnde, e388100, 2, (RF, RF_IF), rd_rm), 15463 cCL(rndep, e388120, 2, (RF, RF_IF), rd_rm), 15464 cCL(rndem, e388140, 2, (RF, RF_IF), rd_rm), 15465 cCL(rndez, e388160, 2, (RF, RF_IF), rd_rm), 15466 15467 cCL(sqts, e408100, 2, (RF, RF_IF), rd_rm), 15468 cCL(sqtsp, e408120, 2, (RF, RF_IF), rd_rm), 15469 cCL(sqtsm, e408140, 2, (RF, RF_IF), rd_rm), 15470 cCL(sqtsz, e408160, 2, (RF, RF_IF), rd_rm), 15471 cCL(sqtd, e408180, 2, (RF, RF_IF), rd_rm), 15472 cCL(sqtdp, e4081a0, 2, (RF, RF_IF), rd_rm), 15473 cCL(sqtdm, e4081c0, 2, (RF, RF_IF), rd_rm), 15474 cCL(sqtdz, e4081e0, 2, (RF, RF_IF), rd_rm), 15475 cCL(sqte, e488100, 2, (RF, RF_IF), rd_rm), 15476 cCL(sqtep, e488120, 2, (RF, RF_IF), rd_rm), 15477 cCL(sqtem, e488140, 2, (RF, RF_IF), rd_rm), 15478 cCL(sqtez, e488160, 2, (RF, RF_IF), rd_rm), 15479 15480 cCL(logs, e508100, 2, (RF, RF_IF), rd_rm), 15481 cCL(logsp, e508120, 2, (RF, RF_IF), rd_rm), 15482 cCL(logsm, e508140, 2, (RF, RF_IF), rd_rm), 15483 cCL(logsz, e508160, 2, (RF, RF_IF), rd_rm), 15484 cCL(logd, e508180, 2, (RF, RF_IF), rd_rm), 15485 cCL(logdp, e5081a0, 2, (RF, RF_IF), rd_rm), 15486 cCL(logdm, e5081c0, 2, (RF, RF_IF), rd_rm), 15487 cCL(logdz, e5081e0, 2, (RF, RF_IF), rd_rm), 15488 cCL(loge, e588100, 2, (RF, RF_IF), rd_rm), 15489 cCL(logep, e588120, 2, (RF, RF_IF), rd_rm), 15490 cCL(logem, e588140, 2, (RF, RF_IF), rd_rm), 15491 cCL(logez, e588160, 2, (RF, RF_IF), rd_rm), 15492 15493 cCL(lgns, e608100, 2, (RF, RF_IF), rd_rm), 15494 cCL(lgnsp, e608120, 2, (RF, RF_IF), rd_rm), 15495 cCL(lgnsm, e608140, 2, (RF, RF_IF), rd_rm), 15496 cCL(lgnsz, e608160, 2, (RF, RF_IF), rd_rm), 15497 cCL(lgnd, e608180, 2, (RF, RF_IF), rd_rm), 15498 cCL(lgndp, e6081a0, 2, (RF, RF_IF), rd_rm), 15499 cCL(lgndm, e6081c0, 2, (RF, RF_IF), rd_rm), 15500 cCL(lgndz, e6081e0, 2, (RF, RF_IF), rd_rm), 15501 cCL(lgne, e688100, 2, (RF, RF_IF), rd_rm), 15502 cCL(lgnep, e688120, 2, (RF, RF_IF), rd_rm), 15503 cCL(lgnem, e688140, 2, (RF, RF_IF), rd_rm), 15504 cCL(lgnez, e688160, 2, (RF, RF_IF), rd_rm), 15505 15506 cCL(exps, e708100, 2, (RF, RF_IF), rd_rm), 15507 cCL(expsp, e708120, 2, (RF, RF_IF), rd_rm), 15508 cCL(expsm, e708140, 2, (RF, RF_IF), rd_rm), 15509 cCL(expsz, e708160, 2, (RF, RF_IF), rd_rm), 15510 cCL(expd, e708180, 2, (RF, RF_IF), rd_rm), 15511 cCL(expdp, e7081a0, 2, (RF, RF_IF), rd_rm), 15512 cCL(expdm, e7081c0, 2, (RF, RF_IF), rd_rm), 15513 cCL(expdz, e7081e0, 2, (RF, RF_IF), rd_rm), 15514 cCL(expe, e788100, 2, (RF, RF_IF), rd_rm), 15515 cCL(expep, e788120, 2, (RF, RF_IF), rd_rm), 15516 cCL(expem, e788140, 2, (RF, RF_IF), rd_rm), 15517 cCL(expdz, e788160, 2, (RF, RF_IF), rd_rm), 15518 15519 cCL(sins, e808100, 2, (RF, RF_IF), rd_rm), 15520 cCL(sinsp, e808120, 2, (RF, RF_IF), rd_rm), 15521 cCL(sinsm, e808140, 2, (RF, RF_IF), rd_rm), 15522 cCL(sinsz, e808160, 2, (RF, RF_IF), rd_rm), 15523 cCL(sind, e808180, 2, (RF, RF_IF), rd_rm), 15524 cCL(sindp, e8081a0, 2, (RF, RF_IF), rd_rm), 15525 cCL(sindm, e8081c0, 2, (RF, RF_IF), rd_rm), 15526 cCL(sindz, e8081e0, 2, (RF, RF_IF), rd_rm), 15527 cCL(sine, e888100, 2, (RF, RF_IF), rd_rm), 15528 cCL(sinep, e888120, 2, (RF, RF_IF), rd_rm), 15529 cCL(sinem, e888140, 2, (RF, RF_IF), rd_rm), 15530 cCL(sinez, e888160, 2, (RF, RF_IF), rd_rm), 15531 15532 cCL(coss, e908100, 2, (RF, RF_IF), rd_rm), 15533 cCL(cossp, e908120, 2, (RF, RF_IF), rd_rm), 15534 cCL(cossm, e908140, 2, (RF, RF_IF), rd_rm), 15535 cCL(cossz, e908160, 2, (RF, RF_IF), rd_rm), 15536 cCL(cosd, e908180, 2, (RF, RF_IF), rd_rm), 15537 cCL(cosdp, e9081a0, 2, (RF, RF_IF), rd_rm), 15538 cCL(cosdm, e9081c0, 2, (RF, RF_IF), rd_rm), 15539 cCL(cosdz, e9081e0, 2, (RF, RF_IF), rd_rm), 15540 cCL(cose, e988100, 2, (RF, RF_IF), rd_rm), 15541 cCL(cosep, e988120, 2, (RF, RF_IF), rd_rm), 15542 cCL(cosem, e988140, 2, (RF, RF_IF), rd_rm), 15543 cCL(cosez, e988160, 2, (RF, RF_IF), rd_rm), 15544 15545 cCL(tans, ea08100, 2, (RF, RF_IF), rd_rm), 15546 cCL(tansp, ea08120, 2, (RF, RF_IF), rd_rm), 15547 cCL(tansm, ea08140, 2, (RF, RF_IF), rd_rm), 15548 cCL(tansz, ea08160, 2, (RF, RF_IF), rd_rm), 15549 cCL(tand, ea08180, 2, (RF, RF_IF), rd_rm), 15550 cCL(tandp, ea081a0, 2, (RF, RF_IF), rd_rm), 15551 cCL(tandm, ea081c0, 2, (RF, RF_IF), rd_rm), 15552 cCL(tandz, ea081e0, 2, (RF, RF_IF), rd_rm), 15553 cCL(tane, ea88100, 2, (RF, RF_IF), rd_rm), 15554 cCL(tanep, ea88120, 2, (RF, RF_IF), rd_rm), 15555 cCL(tanem, ea88140, 2, (RF, RF_IF), rd_rm), 15556 cCL(tanez, ea88160, 2, (RF, RF_IF), rd_rm), 15557 15558 cCL(asns, eb08100, 2, (RF, RF_IF), rd_rm), 15559 cCL(asnsp, eb08120, 2, (RF, RF_IF), rd_rm), 15560 cCL(asnsm, eb08140, 2, (RF, RF_IF), rd_rm), 15561 cCL(asnsz, eb08160, 2, (RF, RF_IF), rd_rm), 15562 cCL(asnd, eb08180, 2, (RF, RF_IF), rd_rm), 15563 cCL(asndp, eb081a0, 2, (RF, RF_IF), rd_rm), 15564 cCL(asndm, eb081c0, 2, (RF, RF_IF), rd_rm), 15565 cCL(asndz, eb081e0, 2, (RF, RF_IF), rd_rm), 15566 cCL(asne, eb88100, 2, (RF, RF_IF), rd_rm), 15567 cCL(asnep, eb88120, 2, (RF, RF_IF), rd_rm), 15568 cCL(asnem, eb88140, 2, (RF, RF_IF), rd_rm), 15569 cCL(asnez, eb88160, 2, (RF, RF_IF), rd_rm), 15570 15571 cCL(acss, ec08100, 2, (RF, RF_IF), rd_rm), 15572 cCL(acssp, ec08120, 2, (RF, RF_IF), rd_rm), 15573 cCL(acssm, ec08140, 2, (RF, RF_IF), rd_rm), 15574 cCL(acssz, ec08160, 2, (RF, RF_IF), rd_rm), 15575 cCL(acsd, ec08180, 2, (RF, RF_IF), rd_rm), 15576 cCL(acsdp, ec081a0, 2, (RF, RF_IF), rd_rm), 15577 cCL(acsdm, ec081c0, 2, (RF, RF_IF), rd_rm), 15578 cCL(acsdz, ec081e0, 2, (RF, RF_IF), rd_rm), 15579 cCL(acse, ec88100, 2, (RF, RF_IF), rd_rm), 15580 cCL(acsep, ec88120, 2, (RF, RF_IF), rd_rm), 15581 cCL(acsem, ec88140, 2, (RF, RF_IF), rd_rm), 15582 cCL(acsez, ec88160, 2, (RF, RF_IF), rd_rm), 15583 15584 cCL(atns, ed08100, 2, (RF, RF_IF), rd_rm), 15585 cCL(atnsp, ed08120, 2, (RF, RF_IF), rd_rm), 15586 cCL(atnsm, ed08140, 2, (RF, RF_IF), rd_rm), 15587 cCL(atnsz, ed08160, 2, (RF, RF_IF), rd_rm), 15588 cCL(atnd, ed08180, 2, (RF, RF_IF), rd_rm), 15589 cCL(atndp, ed081a0, 2, (RF, RF_IF), rd_rm), 15590 cCL(atndm, ed081c0, 2, (RF, RF_IF), rd_rm), 15591 cCL(atndz, ed081e0, 2, (RF, RF_IF), rd_rm), 15592 cCL(atne, ed88100, 2, (RF, RF_IF), rd_rm), 15593 cCL(atnep, ed88120, 2, (RF, RF_IF), rd_rm), 15594 cCL(atnem, ed88140, 2, (RF, RF_IF), rd_rm), 15595 cCL(atnez, ed88160, 2, (RF, RF_IF), rd_rm), 15596 15597 cCL(urds, ee08100, 2, (RF, RF_IF), rd_rm), 15598 cCL(urdsp, ee08120, 2, (RF, RF_IF), rd_rm), 15599 cCL(urdsm, ee08140, 2, (RF, RF_IF), rd_rm), 15600 cCL(urdsz, ee08160, 2, (RF, RF_IF), rd_rm), 15601 cCL(urdd, ee08180, 2, (RF, RF_IF), rd_rm), 15602 cCL(urddp, ee081a0, 2, (RF, RF_IF), rd_rm), 15603 cCL(urddm, ee081c0, 2, (RF, RF_IF), rd_rm), 15604 cCL(urddz, ee081e0, 2, (RF, RF_IF), rd_rm), 15605 cCL(urde, ee88100, 2, (RF, RF_IF), rd_rm), 15606 cCL(urdep, ee88120, 2, (RF, RF_IF), rd_rm), 15607 cCL(urdem, ee88140, 2, (RF, RF_IF), rd_rm), 15608 cCL(urdez, ee88160, 2, (RF, RF_IF), rd_rm), 15609 15610 cCL(nrms, ef08100, 2, (RF, RF_IF), rd_rm), 15611 cCL(nrmsp, ef08120, 2, (RF, RF_IF), rd_rm), 15612 cCL(nrmsm, ef08140, 2, (RF, RF_IF), rd_rm), 15613 cCL(nrmsz, ef08160, 2, (RF, RF_IF), rd_rm), 15614 cCL(nrmd, ef08180, 2, (RF, RF_IF), rd_rm), 15615 cCL(nrmdp, ef081a0, 2, (RF, RF_IF), rd_rm), 15616 cCL(nrmdm, ef081c0, 2, (RF, RF_IF), rd_rm), 15617 cCL(nrmdz, ef081e0, 2, (RF, RF_IF), rd_rm), 15618 cCL(nrme, ef88100, 2, (RF, RF_IF), rd_rm), 15619 cCL(nrmep, ef88120, 2, (RF, RF_IF), rd_rm), 15620 cCL(nrmem, ef88140, 2, (RF, RF_IF), rd_rm), 15621 cCL(nrmez, ef88160, 2, (RF, RF_IF), rd_rm), 15622 15623 cCL(adfs, e000100, 3, (RF, RF, RF_IF), rd_rn_rm), 15624 cCL(adfsp, e000120, 3, (RF, RF, RF_IF), rd_rn_rm), 15625 cCL(adfsm, e000140, 3, (RF, RF, RF_IF), rd_rn_rm), 15626 cCL(adfsz, e000160, 3, (RF, RF, RF_IF), rd_rn_rm), 15627 cCL(adfd, e000180, 3, (RF, RF, RF_IF), rd_rn_rm), 15628 cCL(adfdp, e0001a0, 3, (RF, RF, RF_IF), rd_rn_rm), 15629 cCL(adfdm, e0001c0, 3, (RF, RF, RF_IF), rd_rn_rm), 15630 cCL(adfdz, e0001e0, 3, (RF, RF, RF_IF), rd_rn_rm), 15631 cCL(adfe, e080100, 3, (RF, RF, RF_IF), rd_rn_rm), 15632 cCL(adfep, e080120, 3, (RF, RF, RF_IF), rd_rn_rm), 15633 cCL(adfem, e080140, 3, (RF, RF, RF_IF), rd_rn_rm), 15634 cCL(adfez, e080160, 3, (RF, RF, RF_IF), rd_rn_rm), 15635 15636 cCL(sufs, e200100, 3, (RF, RF, RF_IF), rd_rn_rm), 15637 cCL(sufsp, e200120, 3, (RF, RF, RF_IF), rd_rn_rm), 15638 cCL(sufsm, e200140, 3, (RF, RF, RF_IF), rd_rn_rm), 15639 cCL(sufsz, e200160, 3, (RF, RF, RF_IF), rd_rn_rm), 15640 cCL(sufd, e200180, 3, (RF, RF, RF_IF), rd_rn_rm), 15641 cCL(sufdp, e2001a0, 3, (RF, RF, RF_IF), rd_rn_rm), 15642 cCL(sufdm, e2001c0, 3, (RF, RF, RF_IF), rd_rn_rm), 15643 cCL(sufdz, e2001e0, 3, (RF, RF, RF_IF), rd_rn_rm), 15644 cCL(sufe, e280100, 3, (RF, RF, RF_IF), rd_rn_rm), 15645 cCL(sufep, e280120, 3, (RF, RF, RF_IF), rd_rn_rm), 15646 cCL(sufem, e280140, 3, (RF, RF, RF_IF), rd_rn_rm), 15647 cCL(sufez, e280160, 3, (RF, RF, RF_IF), rd_rn_rm), 15648 15649 cCL(rsfs, e300100, 3, (RF, RF, RF_IF), rd_rn_rm), 15650 cCL(rsfsp, e300120, 3, (RF, RF, RF_IF), rd_rn_rm), 15651 cCL(rsfsm, e300140, 3, (RF, RF, RF_IF), rd_rn_rm), 15652 cCL(rsfsz, e300160, 3, (RF, RF, RF_IF), rd_rn_rm), 15653 cCL(rsfd, e300180, 3, (RF, RF, RF_IF), rd_rn_rm), 15654 cCL(rsfdp, e3001a0, 3, (RF, RF, RF_IF), rd_rn_rm), 15655 cCL(rsfdm, e3001c0, 3, (RF, RF, RF_IF), rd_rn_rm), 15656 cCL(rsfdz, e3001e0, 3, (RF, RF, RF_IF), rd_rn_rm), 15657 cCL(rsfe, e380100, 3, (RF, RF, RF_IF), rd_rn_rm), 15658 cCL(rsfep, e380120, 3, (RF, RF, RF_IF), rd_rn_rm), 15659 cCL(rsfem, e380140, 3, (RF, RF, RF_IF), rd_rn_rm), 15660 cCL(rsfez, e380160, 3, (RF, RF, RF_IF), rd_rn_rm), 15661 15662 cCL(mufs, e100100, 3, (RF, RF, RF_IF), rd_rn_rm), 15663 cCL(mufsp, e100120, 3, (RF, RF, RF_IF), rd_rn_rm), 15664 cCL(mufsm, e100140, 3, (RF, RF, RF_IF), rd_rn_rm), 15665 cCL(mufsz, e100160, 3, (RF, RF, RF_IF), rd_rn_rm), 15666 cCL(mufd, e100180, 3, (RF, RF, RF_IF), rd_rn_rm), 15667 cCL(mufdp, e1001a0, 3, (RF, RF, RF_IF), rd_rn_rm), 15668 cCL(mufdm, e1001c0, 3, (RF, RF, RF_IF), rd_rn_rm), 15669 cCL(mufdz, e1001e0, 3, (RF, RF, RF_IF), rd_rn_rm), 15670 cCL(mufe, e180100, 3, (RF, RF, RF_IF), rd_rn_rm), 15671 cCL(mufep, e180120, 3, (RF, RF, RF_IF), rd_rn_rm), 15672 cCL(mufem, e180140, 3, (RF, RF, RF_IF), rd_rn_rm), 15673 cCL(mufez, e180160, 3, (RF, RF, RF_IF), rd_rn_rm), 15674 15675 cCL(dvfs, e400100, 3, (RF, RF, RF_IF), rd_rn_rm), 15676 cCL(dvfsp, e400120, 3, (RF, RF, RF_IF), rd_rn_rm), 15677 cCL(dvfsm, e400140, 3, (RF, RF, RF_IF), rd_rn_rm), 15678 cCL(dvfsz, e400160, 3, (RF, RF, RF_IF), rd_rn_rm), 15679 cCL(dvfd, e400180, 3, (RF, RF, RF_IF), rd_rn_rm), 15680 cCL(dvfdp, e4001a0, 3, (RF, RF, RF_IF), rd_rn_rm), 15681 cCL(dvfdm, e4001c0, 3, (RF, RF, RF_IF), rd_rn_rm), 15682 cCL(dvfdz, e4001e0, 3, (RF, RF, RF_IF), rd_rn_rm), 15683 cCL(dvfe, e480100, 3, (RF, RF, RF_IF), rd_rn_rm), 15684 cCL(dvfep, e480120, 3, (RF, RF, RF_IF), rd_rn_rm), 15685 cCL(dvfem, e480140, 3, (RF, RF, RF_IF), rd_rn_rm), 15686 cCL(dvfez, e480160, 3, (RF, RF, RF_IF), rd_rn_rm), 15687 15688 cCL(rdfs, e500100, 3, (RF, RF, RF_IF), rd_rn_rm), 15689 cCL(rdfsp, e500120, 3, (RF, RF, RF_IF), rd_rn_rm), 15690 cCL(rdfsm, e500140, 3, (RF, RF, RF_IF), rd_rn_rm), 15691 cCL(rdfsz, e500160, 3, (RF, RF, RF_IF), rd_rn_rm), 15692 cCL(rdfd, e500180, 3, (RF, RF, RF_IF), rd_rn_rm), 15693 cCL(rdfdp, e5001a0, 3, (RF, RF, RF_IF), rd_rn_rm), 15694 cCL(rdfdm, e5001c0, 3, (RF, RF, RF_IF), rd_rn_rm), 15695 cCL(rdfdz, e5001e0, 3, (RF, RF, RF_IF), rd_rn_rm), 15696 cCL(rdfe, e580100, 3, (RF, RF, RF_IF), rd_rn_rm), 15697 cCL(rdfep, e580120, 3, (RF, RF, RF_IF), rd_rn_rm), 15698 cCL(rdfem, e580140, 3, (RF, RF, RF_IF), rd_rn_rm), 15699 cCL(rdfez, e580160, 3, (RF, RF, RF_IF), rd_rn_rm), 15700 15701 cCL(pows, e600100, 3, (RF, RF, RF_IF), rd_rn_rm), 15702 cCL(powsp, e600120, 3, (RF, RF, RF_IF), rd_rn_rm), 15703 cCL(powsm, e600140, 3, (RF, RF, RF_IF), rd_rn_rm), 15704 cCL(powsz, e600160, 3, (RF, RF, RF_IF), rd_rn_rm), 15705 cCL(powd, e600180, 3, (RF, RF, RF_IF), rd_rn_rm), 15706 cCL(powdp, e6001a0, 3, (RF, RF, RF_IF), rd_rn_rm), 15707 cCL(powdm, e6001c0, 3, (RF, RF, RF_IF), rd_rn_rm), 15708 cCL(powdz, e6001e0, 3, (RF, RF, RF_IF), rd_rn_rm), 15709 cCL(powe, e680100, 3, (RF, RF, RF_IF), rd_rn_rm), 15710 cCL(powep, e680120, 3, (RF, RF, RF_IF), rd_rn_rm), 15711 cCL(powem, e680140, 3, (RF, RF, RF_IF), rd_rn_rm), 15712 cCL(powez, e680160, 3, (RF, RF, RF_IF), rd_rn_rm), 15713 15714 cCL(rpws, e700100, 3, (RF, RF, RF_IF), rd_rn_rm), 15715 cCL(rpwsp, e700120, 3, (RF, RF, RF_IF), rd_rn_rm), 15716 cCL(rpwsm, e700140, 3, (RF, RF, RF_IF), rd_rn_rm), 15717 cCL(rpwsz, e700160, 3, (RF, RF, RF_IF), rd_rn_rm), 15718 cCL(rpwd, e700180, 3, (RF, RF, RF_IF), rd_rn_rm), 15719 cCL(rpwdp, e7001a0, 3, (RF, RF, RF_IF), rd_rn_rm), 15720 cCL(rpwdm, e7001c0, 3, (RF, RF, RF_IF), rd_rn_rm), 15721 cCL(rpwdz, e7001e0, 3, (RF, RF, RF_IF), rd_rn_rm), 15722 cCL(rpwe, e780100, 3, (RF, RF, RF_IF), rd_rn_rm), 15723 cCL(rpwep, e780120, 3, (RF, RF, RF_IF), rd_rn_rm), 15724 cCL(rpwem, e780140, 3, (RF, RF, RF_IF), rd_rn_rm), 15725 cCL(rpwez, e780160, 3, (RF, RF, RF_IF), rd_rn_rm), 15726 15727 cCL(rmfs, e800100, 3, (RF, RF, RF_IF), rd_rn_rm), 15728 cCL(rmfsp, e800120, 3, (RF, RF, RF_IF), rd_rn_rm), 15729 cCL(rmfsm, e800140, 3, (RF, RF, RF_IF), rd_rn_rm), 15730 cCL(rmfsz, e800160, 3, (RF, RF, RF_IF), rd_rn_rm), 15731 cCL(rmfd, e800180, 3, (RF, RF, RF_IF), rd_rn_rm), 15732 cCL(rmfdp, e8001a0, 3, (RF, RF, RF_IF), rd_rn_rm), 15733 cCL(rmfdm, e8001c0, 3, (RF, RF, RF_IF), rd_rn_rm), 15734 cCL(rmfdz, e8001e0, 3, (RF, RF, RF_IF), rd_rn_rm), 15735 cCL(rmfe, e880100, 3, (RF, RF, RF_IF), rd_rn_rm), 15736 cCL(rmfep, e880120, 3, (RF, RF, RF_IF), rd_rn_rm), 15737 cCL(rmfem, e880140, 3, (RF, RF, RF_IF), rd_rn_rm), 15738 cCL(rmfez, e880160, 3, (RF, RF, RF_IF), rd_rn_rm), 15739 15740 cCL(fmls, e900100, 3, (RF, RF, RF_IF), rd_rn_rm), 15741 cCL(fmlsp, e900120, 3, (RF, RF, RF_IF), rd_rn_rm), 15742 cCL(fmlsm, e900140, 3, (RF, RF, RF_IF), rd_rn_rm), 15743 cCL(fmlsz, e900160, 3, (RF, RF, RF_IF), rd_rn_rm), 15744 cCL(fmld, e900180, 3, (RF, RF, RF_IF), rd_rn_rm), 15745 cCL(fmldp, e9001a0, 3, (RF, RF, RF_IF), rd_rn_rm), 15746 cCL(fmldm, e9001c0, 3, (RF, RF, RF_IF), rd_rn_rm), 15747 cCL(fmldz, e9001e0, 3, (RF, RF, RF_IF), rd_rn_rm), 15748 cCL(fmle, e980100, 3, (RF, RF, RF_IF), rd_rn_rm), 15749 cCL(fmlep, e980120, 3, (RF, RF, RF_IF), rd_rn_rm), 15750 cCL(fmlem, e980140, 3, (RF, RF, RF_IF), rd_rn_rm), 15751 cCL(fmlez, e980160, 3, (RF, RF, RF_IF), rd_rn_rm), 15752 15753 cCL(fdvs, ea00100, 3, (RF, RF, RF_IF), rd_rn_rm), 15754 cCL(fdvsp, ea00120, 3, (RF, RF, RF_IF), rd_rn_rm), 15755 cCL(fdvsm, ea00140, 3, (RF, RF, RF_IF), rd_rn_rm), 15756 cCL(fdvsz, ea00160, 3, (RF, RF, RF_IF), rd_rn_rm), 15757 cCL(fdvd, ea00180, 3, (RF, RF, RF_IF), rd_rn_rm), 15758 cCL(fdvdp, ea001a0, 3, (RF, RF, RF_IF), rd_rn_rm), 15759 cCL(fdvdm, ea001c0, 3, (RF, RF, RF_IF), rd_rn_rm), 15760 cCL(fdvdz, ea001e0, 3, (RF, RF, RF_IF), rd_rn_rm), 15761 cCL(fdve, ea80100, 3, (RF, RF, RF_IF), rd_rn_rm), 15762 cCL(fdvep, ea80120, 3, (RF, RF, RF_IF), rd_rn_rm), 15763 cCL(fdvem, ea80140, 3, (RF, RF, RF_IF), rd_rn_rm), 15764 cCL(fdvez, ea80160, 3, (RF, RF, RF_IF), rd_rn_rm), 15765 15766 cCL(frds, eb00100, 3, (RF, RF, RF_IF), rd_rn_rm), 15767 cCL(frdsp, eb00120, 3, (RF, RF, RF_IF), rd_rn_rm), 15768 cCL(frdsm, eb00140, 3, (RF, RF, RF_IF), rd_rn_rm), 15769 cCL(frdsz, eb00160, 3, (RF, RF, RF_IF), rd_rn_rm), 15770 cCL(frdd, eb00180, 3, (RF, RF, RF_IF), rd_rn_rm), 15771 cCL(frddp, eb001a0, 3, (RF, RF, RF_IF), rd_rn_rm), 15772 cCL(frddm, eb001c0, 3, (RF, RF, RF_IF), rd_rn_rm), 15773 cCL(frddz, eb001e0, 3, (RF, RF, RF_IF), rd_rn_rm), 15774 cCL(frde, eb80100, 3, (RF, RF, RF_IF), rd_rn_rm), 15775 cCL(frdep, eb80120, 3, (RF, RF, RF_IF), rd_rn_rm), 15776 cCL(frdem, eb80140, 3, (RF, RF, RF_IF), rd_rn_rm), 15777 cCL(frdez, eb80160, 3, (RF, RF, RF_IF), rd_rn_rm), 15778 15779 cCL(pols, ec00100, 3, (RF, RF, RF_IF), rd_rn_rm), 15780 cCL(polsp, ec00120, 3, (RF, RF, RF_IF), rd_rn_rm), 15781 cCL(polsm, ec00140, 3, (RF, RF, RF_IF), rd_rn_rm), 15782 cCL(polsz, ec00160, 3, (RF, RF, RF_IF), rd_rn_rm), 15783 cCL(pold, ec00180, 3, (RF, RF, RF_IF), rd_rn_rm), 15784 cCL(poldp, ec001a0, 3, (RF, RF, RF_IF), rd_rn_rm), 15785 cCL(poldm, ec001c0, 3, (RF, RF, RF_IF), rd_rn_rm), 15786 cCL(poldz, ec001e0, 3, (RF, RF, RF_IF), rd_rn_rm), 15787 cCL(pole, ec80100, 3, (RF, RF, RF_IF), rd_rn_rm), 15788 cCL(polep, ec80120, 3, (RF, RF, RF_IF), rd_rn_rm), 15789 cCL(polem, ec80140, 3, (RF, RF, RF_IF), rd_rn_rm), 15790 cCL(polez, ec80160, 3, (RF, RF, RF_IF), rd_rn_rm), 15791 15792 cCE(cmf, e90f110, 2, (RF, RF_IF), fpa_cmp), 15793 C3E(cmfe, ed0f110, 2, (RF, RF_IF), fpa_cmp), 15794 cCE(cnf, eb0f110, 2, (RF, RF_IF), fpa_cmp), 15795 C3E(cnfe, ef0f110, 2, (RF, RF_IF), fpa_cmp), 15796 15797 cCL(flts, e000110, 2, (RF, RR), rn_rd), 15798 cCL(fltsp, e000130, 2, (RF, RR), rn_rd), 15799 cCL(fltsm, e000150, 2, (RF, RR), rn_rd), 15800 cCL(fltsz, e000170, 2, (RF, RR), rn_rd), 15801 cCL(fltd, e000190, 2, (RF, RR), rn_rd), 15802 cCL(fltdp, e0001b0, 2, (RF, RR), rn_rd), 15803 cCL(fltdm, e0001d0, 2, (RF, RR), rn_rd), 15804 cCL(fltdz, e0001f0, 2, (RF, RR), rn_rd), 15805 cCL(flte, e080110, 2, (RF, RR), rn_rd), 15806 cCL(fltep, e080130, 2, (RF, RR), rn_rd), 15807 cCL(fltem, e080150, 2, (RF, RR), rn_rd), 15808 cCL(fltez, e080170, 2, (RF, RR), rn_rd), 15809 15810 /* The implementation of the FIX instruction is broken on some 15811 assemblers, in that it accepts a precision specifier as well as a 15812 rounding specifier, despite the fact that this is meaningless. 15813 To be more compatible, we accept it as well, though of course it 15814 does not set any bits. */ 15815 cCE(fix, e100110, 2, (RR, RF), rd_rm), 15816 cCL(fixp, e100130, 2, (RR, RF), rd_rm), 15817 cCL(fixm, e100150, 2, (RR, RF), rd_rm), 15818 cCL(fixz, e100170, 2, (RR, RF), rd_rm), 15819 cCL(fixsp, e100130, 2, (RR, RF), rd_rm), 15820 cCL(fixsm, e100150, 2, (RR, RF), rd_rm), 15821 cCL(fixsz, e100170, 2, (RR, RF), rd_rm), 15822 cCL(fixdp, e100130, 2, (RR, RF), rd_rm), 15823 cCL(fixdm, e100150, 2, (RR, RF), rd_rm), 15824 cCL(fixdz, e100170, 2, (RR, RF), rd_rm), 15825 cCL(fixep, e100130, 2, (RR, RF), rd_rm), 15826 cCL(fixem, e100150, 2, (RR, RF), rd_rm), 15827 cCL(fixez, e100170, 2, (RR, RF), rd_rm), 15828 15829 /* Instructions that were new with the real FPA, call them V2. */ 15830#undef ARM_VARIANT 15831#define ARM_VARIANT &fpu_fpa_ext_v2 15832 cCE(lfm, c100200, 3, (RF, I4b, ADDR), fpa_ldmstm), 15833 cCL(lfmfd, c900200, 3, (RF, I4b, ADDR), fpa_ldmstm), 15834 cCL(lfmea, d100200, 3, (RF, I4b, ADDR), fpa_ldmstm), 15835 cCE(sfm, c000200, 3, (RF, I4b, ADDR), fpa_ldmstm), 15836 cCL(sfmfd, d000200, 3, (RF, I4b, ADDR), fpa_ldmstm), 15837 cCL(sfmea, c800200, 3, (RF, I4b, ADDR), fpa_ldmstm), 15838 15839#undef ARM_VARIANT 15840#define ARM_VARIANT &fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */ 15841 /* Moves and type conversions. */ 15842 cCE(fcpys, eb00a40, 2, (RVS, RVS), vfp_sp_monadic), 15843 cCE(fmrs, e100a10, 2, (RR, RVS), vfp_reg_from_sp), 15844 cCE(fmsr, e000a10, 2, (RVS, RR), vfp_sp_from_reg), 15845 cCE(fmstat, ef1fa10, 0, (), noargs), 15846 cCE(fsitos, eb80ac0, 2, (RVS, RVS), vfp_sp_monadic), 15847 cCE(fuitos, eb80a40, 2, (RVS, RVS), vfp_sp_monadic), 15848 cCE(ftosis, ebd0a40, 2, (RVS, RVS), vfp_sp_monadic), 15849 cCE(ftosizs, ebd0ac0, 2, (RVS, RVS), vfp_sp_monadic), 15850 cCE(ftouis, ebc0a40, 2, (RVS, RVS), vfp_sp_monadic), 15851 cCE(ftouizs, ebc0ac0, 2, (RVS, RVS), vfp_sp_monadic), 15852 cCE(fmrx, ef00a10, 2, (RR, RVC), rd_rn), 15853 cCE(fmxr, ee00a10, 2, (RVC, RR), rn_rd), 15854 cCE(vmrs, ef00a10, 2, (APSR_RR, RVC), vfp_vmrs), 15855 cCE(vmsr, ee00a10, 2, (RVC, RR), vfp_vmsr), 15856 15857 /* Memory operations. */ 15858 cCE(flds, d100a00, 2, (RVS, ADDRGLDC), vfp_sp_ldst), 15859 cCE(fsts, d000a00, 2, (RVS, ADDRGLDC), vfp_sp_ldst), 15860 cCE(fldmias, c900a00, 2, (RRw, VRSLST), vfp_sp_ldstmia), 15861 cCE(fldmfds, c900a00, 2, (RRw, VRSLST), vfp_sp_ldstmia), 15862 cCE(fldmdbs, d300a00, 2, (RRw, VRSLST), vfp_sp_ldstmdb), 15863 cCE(fldmeas, d300a00, 2, (RRw, VRSLST), vfp_sp_ldstmdb), 15864 cCE(fldmiax, c900b00, 2, (RRw, VRDLST), vfp_xp_ldstmia), 15865 cCE(fldmfdx, c900b00, 2, (RRw, VRDLST), vfp_xp_ldstmia), 15866 cCE(fldmdbx, d300b00, 2, (RRw, VRDLST), vfp_xp_ldstmdb), 15867 cCE(fldmeax, d300b00, 2, (RRw, VRDLST), vfp_xp_ldstmdb), 15868 cCE(fstmias, c800a00, 2, (RRw, VRSLST), vfp_sp_ldstmia), 15869 cCE(fstmeas, c800a00, 2, (RRw, VRSLST), vfp_sp_ldstmia), 15870 cCE(fstmdbs, d200a00, 2, (RRw, VRSLST), vfp_sp_ldstmdb), 15871 cCE(fstmfds, d200a00, 2, (RRw, VRSLST), vfp_sp_ldstmdb), 15872 cCE(fstmiax, c800b00, 2, (RRw, VRDLST), vfp_xp_ldstmia), 15873 cCE(fstmeax, c800b00, 2, (RRw, VRDLST), vfp_xp_ldstmia), 15874 cCE(fstmdbx, d200b00, 2, (RRw, VRDLST), vfp_xp_ldstmdb), 15875 cCE(fstmfdx, d200b00, 2, (RRw, VRDLST), vfp_xp_ldstmdb), 15876 15877 /* Monadic operations. */ 15878 cCE(fabss, eb00ac0, 2, (RVS, RVS), vfp_sp_monadic), 15879 cCE(fnegs, eb10a40, 2, (RVS, RVS), vfp_sp_monadic), 15880 cCE(fsqrts, eb10ac0, 2, (RVS, RVS), vfp_sp_monadic), 15881 15882 /* Dyadic operations. */ 15883 cCE(fadds, e300a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), 15884 cCE(fsubs, e300a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic), 15885 cCE(fmuls, e200a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), 15886 cCE(fdivs, e800a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), 15887 cCE(fmacs, e000a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), 15888 cCE(fmscs, e100a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), 15889 cCE(fnmuls, e200a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic), 15890 cCE(fnmacs, e000a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic), 15891 cCE(fnmscs, e100a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic), 15892 15893 /* Comparisons. */ 15894 cCE(fcmps, eb40a40, 2, (RVS, RVS), vfp_sp_monadic), 15895 cCE(fcmpzs, eb50a40, 1, (RVS), vfp_sp_compare_z), 15896 cCE(fcmpes, eb40ac0, 2, (RVS, RVS), vfp_sp_monadic), 15897 cCE(fcmpezs, eb50ac0, 1, (RVS), vfp_sp_compare_z), 15898 15899#undef ARM_VARIANT 15900#define ARM_VARIANT &fpu_vfp_ext_v1 /* VFP V1 (Double precision). */ 15901 /* Moves and type conversions. */ 15902 cCE(fcpyd, eb00b40, 2, (RVD, RVD), vfp_dp_rd_rm), 15903 cCE(fcvtds, eb70ac0, 2, (RVD, RVS), vfp_dp_sp_cvt), 15904 cCE(fcvtsd, eb70bc0, 2, (RVS, RVD), vfp_sp_dp_cvt), 15905 cCE(fmdhr, e200b10, 2, (RVD, RR), vfp_dp_rn_rd), 15906 cCE(fmdlr, e000b10, 2, (RVD, RR), vfp_dp_rn_rd), 15907 cCE(fmrdh, e300b10, 2, (RR, RVD), vfp_dp_rd_rn), 15908 cCE(fmrdl, e100b10, 2, (RR, RVD), vfp_dp_rd_rn), 15909 cCE(fsitod, eb80bc0, 2, (RVD, RVS), vfp_dp_sp_cvt), 15910 cCE(fuitod, eb80b40, 2, (RVD, RVS), vfp_dp_sp_cvt), 15911 cCE(ftosid, ebd0b40, 2, (RVS, RVD), vfp_sp_dp_cvt), 15912 cCE(ftosizd, ebd0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt), 15913 cCE(ftouid, ebc0b40, 2, (RVS, RVD), vfp_sp_dp_cvt), 15914 cCE(ftouizd, ebc0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt), 15915 15916 /* Memory operations. */ 15917 cCE(fldd, d100b00, 2, (RVD, ADDRGLDC), vfp_dp_ldst), 15918 cCE(fstd, d000b00, 2, (RVD, ADDRGLDC), vfp_dp_ldst), 15919 cCE(fldmiad, c900b00, 2, (RRw, VRDLST), vfp_dp_ldstmia), 15920 cCE(fldmfdd, c900b00, 2, (RRw, VRDLST), vfp_dp_ldstmia), 15921 cCE(fldmdbd, d300b00, 2, (RRw, VRDLST), vfp_dp_ldstmdb), 15922 cCE(fldmead, d300b00, 2, (RRw, VRDLST), vfp_dp_ldstmdb), 15923 cCE(fstmiad, c800b00, 2, (RRw, VRDLST), vfp_dp_ldstmia), 15924 cCE(fstmead, c800b00, 2, (RRw, VRDLST), vfp_dp_ldstmia), 15925 cCE(fstmdbd, d200b00, 2, (RRw, VRDLST), vfp_dp_ldstmdb), 15926 cCE(fstmfdd, d200b00, 2, (RRw, VRDLST), vfp_dp_ldstmdb), 15927 15928 /* Monadic operations. */ 15929 cCE(fabsd, eb00bc0, 2, (RVD, RVD), vfp_dp_rd_rm), 15930 cCE(fnegd, eb10b40, 2, (RVD, RVD), vfp_dp_rd_rm), 15931 cCE(fsqrtd, eb10bc0, 2, (RVD, RVD), vfp_dp_rd_rm), 15932 15933 /* Dyadic operations. */ 15934 cCE(faddd, e300b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), 15935 cCE(fsubd, e300b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), 15936 cCE(fmuld, e200b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), 15937 cCE(fdivd, e800b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), 15938 cCE(fmacd, e000b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), 15939 cCE(fmscd, e100b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), 15940 cCE(fnmuld, e200b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), 15941 cCE(fnmacd, e000b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), 15942 cCE(fnmscd, e100b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), 15943 15944 /* Comparisons. */ 15945 cCE(fcmpd, eb40b40, 2, (RVD, RVD), vfp_dp_rd_rm), 15946 cCE(fcmpzd, eb50b40, 1, (RVD), vfp_dp_rd), 15947 cCE(fcmped, eb40bc0, 2, (RVD, RVD), vfp_dp_rd_rm), 15948 cCE(fcmpezd, eb50bc0, 1, (RVD), vfp_dp_rd), 15949 15950#undef ARM_VARIANT 15951#define ARM_VARIANT &fpu_vfp_ext_v2 15952 cCE(fmsrr, c400a10, 3, (VRSLST, RR, RR), vfp_sp2_from_reg2), 15953 cCE(fmrrs, c500a10, 3, (RR, RR, VRSLST), vfp_reg2_from_sp2), 15954 cCE(fmdrr, c400b10, 3, (RVD, RR, RR), vfp_dp_rm_rd_rn), 15955 cCE(fmrrd, c500b10, 3, (RR, RR, RVD), vfp_dp_rd_rn_rm), 15956 15957/* Instructions which may belong to either the Neon or VFP instruction sets. 15958 Individual encoder functions perform additional architecture checks. */ 15959#undef ARM_VARIANT 15960#define ARM_VARIANT &fpu_vfp_ext_v1xd 15961#undef THUMB_VARIANT 15962#define THUMB_VARIANT &fpu_vfp_ext_v1xd 15963 /* These mnemonics are unique to VFP. */ 15964 NCE(vsqrt, 0, 2, (RVSD, RVSD), vfp_nsyn_sqrt), 15965 NCE(vdiv, 0, 3, (RVSD, RVSD, RVSD), vfp_nsyn_div), 15966 nCE(vnmul, vnmul, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul), 15967 nCE(vnmla, vnmla, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul), 15968 nCE(vnmls, vnmls, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul), 15969 nCE(vcmp, vcmp, 2, (RVSD, RVSD_I0), vfp_nsyn_cmp), 15970 nCE(vcmpe, vcmpe, 2, (RVSD, RVSD_I0), vfp_nsyn_cmp), 15971 NCE(vpush, 0, 1, (VRSDLST), vfp_nsyn_push), 15972 NCE(vpop, 0, 1, (VRSDLST), vfp_nsyn_pop), 15973 NCE(vcvtz, 0, 2, (RVSD, RVSD), vfp_nsyn_cvtz), 15974 15975 /* Mnemonics shared by Neon and VFP. */ 15976 nCEF(vmul, vmul, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mul), 15977 nCEF(vmla, vmla, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mac_maybe_scalar), 15978 nCEF(vmls, vmls, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mac_maybe_scalar), 15979 15980 nCEF(vadd, vadd, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_addsub_if_i), 15981 nCEF(vsub, vsub, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_addsub_if_i), 15982 15983 NCEF(vabs, 1b10300, 2, (RNSDQ, RNSDQ), neon_abs_neg), 15984 NCEF(vneg, 1b10380, 2, (RNSDQ, RNSDQ), neon_abs_neg), 15985 15986 NCE(vldm, c900b00, 2, (RRw, VRSDLST), neon_ldm_stm), 15987 NCE(vldmia, c900b00, 2, (RRw, VRSDLST), neon_ldm_stm), 15988 NCE(vldmdb, d100b00, 2, (RRw, VRSDLST), neon_ldm_stm), 15989 NCE(vstm, c800b00, 2, (RRw, VRSDLST), neon_ldm_stm), 15990 NCE(vstmia, c800b00, 2, (RRw, VRSDLST), neon_ldm_stm), 15991 NCE(vstmdb, d000b00, 2, (RRw, VRSDLST), neon_ldm_stm), 15992 NCE(vldr, d100b00, 2, (RVSD, ADDRGLDC), neon_ldr_str), 15993 NCE(vstr, d000b00, 2, (RVSD, ADDRGLDC), neon_ldr_str), 15994 15995 nCEF(vcvt, vcvt, 3, (RNSDQ, RNSDQ, oI32b), neon_cvt), 15996 15997 /* NOTE: All VMOV encoding is special-cased! */ 15998 NCE(vmov, 0, 1, (VMOV), neon_mov), 15999 NCE(vmovq, 0, 1, (VMOV), neon_mov), 16000 16001#undef THUMB_VARIANT 16002#define THUMB_VARIANT &fpu_neon_ext_v1 16003#undef ARM_VARIANT 16004#define ARM_VARIANT &fpu_neon_ext_v1 16005 /* Data processing with three registers of the same length. */ 16006 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */ 16007 NUF(vaba, 0000710, 3, (RNDQ, RNDQ, RNDQ), neon_dyadic_i_su), 16008 NUF(vabaq, 0000710, 3, (RNQ, RNQ, RNQ), neon_dyadic_i_su), 16009 NUF(vhadd, 0000000, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su), 16010 NUF(vhaddq, 0000000, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su), 16011 NUF(vrhadd, 0000100, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su), 16012 NUF(vrhaddq, 0000100, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su), 16013 NUF(vhsub, 0000200, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su), 16014 NUF(vhsubq, 0000200, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su), 16015 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */ 16016 NUF(vqadd, 0000010, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i64_su), 16017 NUF(vqaddq, 0000010, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i64_su), 16018 NUF(vqsub, 0000210, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i64_su), 16019 NUF(vqsubq, 0000210, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i64_su), 16020 NUF(vrshl, 0000500, 3, (RNDQ, oRNDQ, RNDQ), neon_rshl), 16021 NUF(vrshlq, 0000500, 3, (RNQ, oRNQ, RNQ), neon_rshl), 16022 NUF(vqrshl, 0000510, 3, (RNDQ, oRNDQ, RNDQ), neon_rshl), 16023 NUF(vqrshlq, 0000510, 3, (RNQ, oRNQ, RNQ), neon_rshl), 16024 /* If not immediate, fall back to neon_dyadic_i64_su. 16025 shl_imm should accept I8 I16 I32 I64, 16026 qshl_imm should accept S8 S16 S32 S64 U8 U16 U32 U64. */ 16027 nUF(vshl, vshl, 3, (RNDQ, oRNDQ, RNDQ_I63b), neon_shl_imm), 16028 nUF(vshlq, vshl, 3, (RNQ, oRNQ, RNDQ_I63b), neon_shl_imm), 16029 nUF(vqshl, vqshl, 3, (RNDQ, oRNDQ, RNDQ_I63b), neon_qshl_imm), 16030 nUF(vqshlq, vqshl, 3, (RNQ, oRNQ, RNDQ_I63b), neon_qshl_imm), 16031 /* Logic ops, types optional & ignored. */ 16032 nUF(vand, vand, 2, (RNDQ, NILO), neon_logic), 16033 nUF(vandq, vand, 2, (RNQ, NILO), neon_logic), 16034 nUF(vbic, vbic, 2, (RNDQ, NILO), neon_logic), 16035 nUF(vbicq, vbic, 2, (RNQ, NILO), neon_logic), 16036 nUF(vorr, vorr, 2, (RNDQ, NILO), neon_logic), 16037 nUF(vorrq, vorr, 2, (RNQ, NILO), neon_logic), 16038 nUF(vorn, vorn, 2, (RNDQ, NILO), neon_logic), 16039 nUF(vornq, vorn, 2, (RNQ, NILO), neon_logic), 16040 nUF(veor, veor, 3, (RNDQ, oRNDQ, RNDQ), neon_logic), 16041 nUF(veorq, veor, 3, (RNQ, oRNQ, RNQ), neon_logic), 16042 /* Bitfield ops, untyped. */ 16043 NUF(vbsl, 1100110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield), 16044 NUF(vbslq, 1100110, 3, (RNQ, RNQ, RNQ), neon_bitfield), 16045 NUF(vbit, 1200110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield), 16046 NUF(vbitq, 1200110, 3, (RNQ, RNQ, RNQ), neon_bitfield), 16047 NUF(vbif, 1300110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield), 16048 NUF(vbifq, 1300110, 3, (RNQ, RNQ, RNQ), neon_bitfield), 16049 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F32. */ 16050 nUF(vabd, vabd, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su), 16051 nUF(vabdq, vabd, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su), 16052 nUF(vmax, vmax, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su), 16053 nUF(vmaxq, vmax, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su), 16054 nUF(vmin, vmin, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su), 16055 nUF(vminq, vmin, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su), 16056 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall 16057 back to neon_dyadic_if_su. */ 16058 nUF(vcge, vcge, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp), 16059 nUF(vcgeq, vcge, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp), 16060 nUF(vcgt, vcgt, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp), 16061 nUF(vcgtq, vcgt, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp), 16062 nUF(vclt, vclt, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp_inv), 16063 nUF(vcltq, vclt, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp_inv), 16064 nUF(vcle, vcle, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp_inv), 16065 nUF(vcleq, vcle, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp_inv), 16066 /* Comparison. Type I8 I16 I32 F32. */ 16067 nUF(vceq, vceq, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_ceq), 16068 nUF(vceqq, vceq, 3, (RNQ, oRNQ, RNDQ_I0), neon_ceq), 16069 /* As above, D registers only. */ 16070 nUF(vpmax, vpmax, 3, (RND, oRND, RND), neon_dyadic_if_su_d), 16071 nUF(vpmin, vpmin, 3, (RND, oRND, RND), neon_dyadic_if_su_d), 16072 /* Int and float variants, signedness unimportant. */ 16073 nUF(vmlaq, vmla, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mac_maybe_scalar), 16074 nUF(vmlsq, vmls, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mac_maybe_scalar), 16075 nUF(vpadd, vpadd, 3, (RND, oRND, RND), neon_dyadic_if_i_d), 16076 /* Add/sub take types I8 I16 I32 I64 F32. */ 16077 nUF(vaddq, vadd, 3, (RNQ, oRNQ, RNQ), neon_addsub_if_i), 16078 nUF(vsubq, vsub, 3, (RNQ, oRNQ, RNQ), neon_addsub_if_i), 16079 /* vtst takes sizes 8, 16, 32. */ 16080 NUF(vtst, 0000810, 3, (RNDQ, oRNDQ, RNDQ), neon_tst), 16081 NUF(vtstq, 0000810, 3, (RNQ, oRNQ, RNQ), neon_tst), 16082 /* VMUL takes I8 I16 I32 F32 P8. */ 16083 nUF(vmulq, vmul, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mul), 16084 /* VQD{R}MULH takes S16 S32. */ 16085 nUF(vqdmulh, vqdmulh, 3, (RNDQ, oRNDQ, RNDQ_RNSC), neon_qdmulh), 16086 nUF(vqdmulhq, vqdmulh, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qdmulh), 16087 nUF(vqrdmulh, vqrdmulh, 3, (RNDQ, oRNDQ, RNDQ_RNSC), neon_qdmulh), 16088 nUF(vqrdmulhq, vqrdmulh, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qdmulh), 16089 NUF(vacge, 0000e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute), 16090 NUF(vacgeq, 0000e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute), 16091 NUF(vacgt, 0200e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute), 16092 NUF(vacgtq, 0200e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute), 16093 NUF(vaclt, 0200e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute_inv), 16094 NUF(vacltq, 0200e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute_inv), 16095 NUF(vacle, 0000e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute_inv), 16096 NUF(vacleq, 0000e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute_inv), 16097 NUF(vrecps, 0000f10, 3, (RNDQ, oRNDQ, RNDQ), neon_step), 16098 NUF(vrecpsq, 0000f10, 3, (RNQ, oRNQ, RNQ), neon_step), 16099 NUF(vrsqrts, 0200f10, 3, (RNDQ, oRNDQ, RNDQ), neon_step), 16100 NUF(vrsqrtsq, 0200f10, 3, (RNQ, oRNQ, RNQ), neon_step), 16101 16102 /* Two address, int/float. Types S8 S16 S32 F32. */ 16103 NUF(vabsq, 1b10300, 2, (RNQ, RNQ), neon_abs_neg), 16104 NUF(vnegq, 1b10380, 2, (RNQ, RNQ), neon_abs_neg), 16105 16106 /* Data processing with two registers and a shift amount. */ 16107 /* Right shifts, and variants with rounding. 16108 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */ 16109 NUF(vshr, 0800010, 3, (RNDQ, oRNDQ, I64z), neon_rshift_round_imm), 16110 NUF(vshrq, 0800010, 3, (RNQ, oRNQ, I64z), neon_rshift_round_imm), 16111 NUF(vrshr, 0800210, 3, (RNDQ, oRNDQ, I64z), neon_rshift_round_imm), 16112 NUF(vrshrq, 0800210, 3, (RNQ, oRNQ, I64z), neon_rshift_round_imm), 16113 NUF(vsra, 0800110, 3, (RNDQ, oRNDQ, I64), neon_rshift_round_imm), 16114 NUF(vsraq, 0800110, 3, (RNQ, oRNQ, I64), neon_rshift_round_imm), 16115 NUF(vrsra, 0800310, 3, (RNDQ, oRNDQ, I64), neon_rshift_round_imm), 16116 NUF(vrsraq, 0800310, 3, (RNQ, oRNQ, I64), neon_rshift_round_imm), 16117 /* Shift and insert. Sizes accepted 8 16 32 64. */ 16118 NUF(vsli, 1800510, 3, (RNDQ, oRNDQ, I63), neon_sli), 16119 NUF(vsliq, 1800510, 3, (RNQ, oRNQ, I63), neon_sli), 16120 NUF(vsri, 1800410, 3, (RNDQ, oRNDQ, I64), neon_sri), 16121 NUF(vsriq, 1800410, 3, (RNQ, oRNQ, I64), neon_sri), 16122 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */ 16123 NUF(vqshlu, 1800610, 3, (RNDQ, oRNDQ, I63), neon_qshlu_imm), 16124 NUF(vqshluq, 1800610, 3, (RNQ, oRNQ, I63), neon_qshlu_imm), 16125 /* Right shift immediate, saturating & narrowing, with rounding variants. 16126 Types accepted S16 S32 S64 U16 U32 U64. */ 16127 NUF(vqshrn, 0800910, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow), 16128 NUF(vqrshrn, 0800950, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow), 16129 /* As above, unsigned. Types accepted S16 S32 S64. */ 16130 NUF(vqshrun, 0800810, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow_u), 16131 NUF(vqrshrun, 0800850, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow_u), 16132 /* Right shift narrowing. Types accepted I16 I32 I64. */ 16133 NUF(vshrn, 0800810, 3, (RND, RNQ, I32z), neon_rshift_narrow), 16134 NUF(vrshrn, 0800850, 3, (RND, RNQ, I32z), neon_rshift_narrow), 16135 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */ 16136 nUF(vshll, vshll, 3, (RNQ, RND, I32), neon_shll), 16137 /* CVT with optional immediate for fixed-point variant. */ 16138 nUF(vcvtq, vcvt, 3, (RNQ, RNQ, oI32b), neon_cvt), 16139 16140 nUF(vmvn, vmvn, 2, (RNDQ, RNDQ_IMVNb), neon_mvn), 16141 nUF(vmvnq, vmvn, 2, (RNQ, RNDQ_IMVNb), neon_mvn), 16142 16143 /* Data processing, three registers of different lengths. */ 16144 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */ 16145 NUF(vabal, 0800500, 3, (RNQ, RND, RND), neon_abal), 16146 NUF(vabdl, 0800700, 3, (RNQ, RND, RND), neon_dyadic_long), 16147 NUF(vaddl, 0800000, 3, (RNQ, RND, RND), neon_dyadic_long), 16148 NUF(vsubl, 0800200, 3, (RNQ, RND, RND), neon_dyadic_long), 16149 /* If not scalar, fall back to neon_dyadic_long. 16150 Vector types as above, scalar types S16 S32 U16 U32. */ 16151 nUF(vmlal, vmlal, 3, (RNQ, RND, RND_RNSC), neon_mac_maybe_scalar_long), 16152 nUF(vmlsl, vmlsl, 3, (RNQ, RND, RND_RNSC), neon_mac_maybe_scalar_long), 16153 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */ 16154 NUF(vaddw, 0800100, 3, (RNQ, oRNQ, RND), neon_dyadic_wide), 16155 NUF(vsubw, 0800300, 3, (RNQ, oRNQ, RND), neon_dyadic_wide), 16156 /* Dyadic, narrowing insns. Types I16 I32 I64. */ 16157 NUF(vaddhn, 0800400, 3, (RND, RNQ, RNQ), neon_dyadic_narrow), 16158 NUF(vraddhn, 1800400, 3, (RND, RNQ, RNQ), neon_dyadic_narrow), 16159 NUF(vsubhn, 0800600, 3, (RND, RNQ, RNQ), neon_dyadic_narrow), 16160 NUF(vrsubhn, 1800600, 3, (RND, RNQ, RNQ), neon_dyadic_narrow), 16161 /* Saturating doubling multiplies. Types S16 S32. */ 16162 nUF(vqdmlal, vqdmlal, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long), 16163 nUF(vqdmlsl, vqdmlsl, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long), 16164 nUF(vqdmull, vqdmull, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long), 16165 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types 16166 S16 S32 U16 U32. */ 16167 nUF(vmull, vmull, 3, (RNQ, RND, RND_RNSC), neon_vmull), 16168 16169 /* Extract. Size 8. */ 16170 NUF(vext, 0b00000, 4, (RNDQ, oRNDQ, RNDQ, I15), neon_ext), 16171 NUF(vextq, 0b00000, 4, (RNQ, oRNQ, RNQ, I15), neon_ext), 16172 16173 /* Two registers, miscellaneous. */ 16174 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */ 16175 NUF(vrev64, 1b00000, 2, (RNDQ, RNDQ), neon_rev), 16176 NUF(vrev64q, 1b00000, 2, (RNQ, RNQ), neon_rev), 16177 NUF(vrev32, 1b00080, 2, (RNDQ, RNDQ), neon_rev), 16178 NUF(vrev32q, 1b00080, 2, (RNQ, RNQ), neon_rev), 16179 NUF(vrev16, 1b00100, 2, (RNDQ, RNDQ), neon_rev), 16180 NUF(vrev16q, 1b00100, 2, (RNQ, RNQ), neon_rev), 16181 /* Vector replicate. Sizes 8 16 32. */ 16182 nCE(vdup, vdup, 2, (RNDQ, RR_RNSC), neon_dup), 16183 nCE(vdupq, vdup, 2, (RNQ, RR_RNSC), neon_dup), 16184 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */ 16185 NUF(vmovl, 0800a10, 2, (RNQ, RND), neon_movl), 16186 /* VMOVN. Types I16 I32 I64. */ 16187 nUF(vmovn, vmovn, 2, (RND, RNQ), neon_movn), 16188 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */ 16189 nUF(vqmovn, vqmovn, 2, (RND, RNQ), neon_qmovn), 16190 /* VQMOVUN. Types S16 S32 S64. */ 16191 nUF(vqmovun, vqmovun, 2, (RND, RNQ), neon_qmovun), 16192 /* VZIP / VUZP. Sizes 8 16 32. */ 16193 NUF(vzip, 1b20180, 2, (RNDQ, RNDQ), neon_zip_uzp), 16194 NUF(vzipq, 1b20180, 2, (RNQ, RNQ), neon_zip_uzp), 16195 NUF(vuzp, 1b20100, 2, (RNDQ, RNDQ), neon_zip_uzp), 16196 NUF(vuzpq, 1b20100, 2, (RNQ, RNQ), neon_zip_uzp), 16197 /* VQABS / VQNEG. Types S8 S16 S32. */ 16198 NUF(vqabs, 1b00700, 2, (RNDQ, RNDQ), neon_sat_abs_neg), 16199 NUF(vqabsq, 1b00700, 2, (RNQ, RNQ), neon_sat_abs_neg), 16200 NUF(vqneg, 1b00780, 2, (RNDQ, RNDQ), neon_sat_abs_neg), 16201 NUF(vqnegq, 1b00780, 2, (RNQ, RNQ), neon_sat_abs_neg), 16202 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */ 16203 NUF(vpadal, 1b00600, 2, (RNDQ, RNDQ), neon_pair_long), 16204 NUF(vpadalq, 1b00600, 2, (RNQ, RNQ), neon_pair_long), 16205 NUF(vpaddl, 1b00200, 2, (RNDQ, RNDQ), neon_pair_long), 16206 NUF(vpaddlq, 1b00200, 2, (RNQ, RNQ), neon_pair_long), 16207 /* Reciprocal estimates. Types U32 F32. */ 16208 NUF(vrecpe, 1b30400, 2, (RNDQ, RNDQ), neon_recip_est), 16209 NUF(vrecpeq, 1b30400, 2, (RNQ, RNQ), neon_recip_est), 16210 NUF(vrsqrte, 1b30480, 2, (RNDQ, RNDQ), neon_recip_est), 16211 NUF(vrsqrteq, 1b30480, 2, (RNQ, RNQ), neon_recip_est), 16212 /* VCLS. Types S8 S16 S32. */ 16213 NUF(vcls, 1b00400, 2, (RNDQ, RNDQ), neon_cls), 16214 NUF(vclsq, 1b00400, 2, (RNQ, RNQ), neon_cls), 16215 /* VCLZ. Types I8 I16 I32. */ 16216 NUF(vclz, 1b00480, 2, (RNDQ, RNDQ), neon_clz), 16217 NUF(vclzq, 1b00480, 2, (RNQ, RNQ), neon_clz), 16218 /* VCNT. Size 8. */ 16219 NUF(vcnt, 1b00500, 2, (RNDQ, RNDQ), neon_cnt), 16220 NUF(vcntq, 1b00500, 2, (RNQ, RNQ), neon_cnt), 16221 /* Two address, untyped. */ 16222 NUF(vswp, 1b20000, 2, (RNDQ, RNDQ), neon_swp), 16223 NUF(vswpq, 1b20000, 2, (RNQ, RNQ), neon_swp), 16224 /* VTRN. Sizes 8 16 32. */ 16225 nUF(vtrn, vtrn, 2, (RNDQ, RNDQ), neon_trn), 16226 nUF(vtrnq, vtrn, 2, (RNQ, RNQ), neon_trn), 16227 16228 /* Table lookup. Size 8. */ 16229 NUF(vtbl, 1b00800, 3, (RND, NRDLST, RND), neon_tbl_tbx), 16230 NUF(vtbx, 1b00840, 3, (RND, NRDLST, RND), neon_tbl_tbx), 16231 16232#undef THUMB_VARIANT 16233#define THUMB_VARIANT &fpu_vfp_v3_or_neon_ext 16234#undef ARM_VARIANT 16235#define ARM_VARIANT &fpu_vfp_v3_or_neon_ext 16236 /* Neon element/structure load/store. */ 16237 nUF(vld1, vld1, 2, (NSTRLST, ADDR), neon_ldx_stx), 16238 nUF(vst1, vst1, 2, (NSTRLST, ADDR), neon_ldx_stx), 16239 nUF(vld2, vld2, 2, (NSTRLST, ADDR), neon_ldx_stx), 16240 nUF(vst2, vst2, 2, (NSTRLST, ADDR), neon_ldx_stx), 16241 nUF(vld3, vld3, 2, (NSTRLST, ADDR), neon_ldx_stx), 16242 nUF(vst3, vst3, 2, (NSTRLST, ADDR), neon_ldx_stx), 16243 nUF(vld4, vld4, 2, (NSTRLST, ADDR), neon_ldx_stx), 16244 nUF(vst4, vst4, 2, (NSTRLST, ADDR), neon_ldx_stx), 16245 16246#undef THUMB_VARIANT 16247#define THUMB_VARIANT &fpu_vfp_ext_v3 16248#undef ARM_VARIANT 16249#define ARM_VARIANT &fpu_vfp_ext_v3 16250 cCE(fconsts, eb00a00, 2, (RVS, I255), vfp_sp_const), 16251 cCE(fconstd, eb00b00, 2, (RVD, I255), vfp_dp_const), 16252 cCE(fshtos, eba0a40, 2, (RVS, I16z), vfp_sp_conv_16), 16253 cCE(fshtod, eba0b40, 2, (RVD, I16z), vfp_dp_conv_16), 16254 cCE(fsltos, eba0ac0, 2, (RVS, I32), vfp_sp_conv_32), 16255 cCE(fsltod, eba0bc0, 2, (RVD, I32), vfp_dp_conv_32), 16256 cCE(fuhtos, ebb0a40, 2, (RVS, I16z), vfp_sp_conv_16), 16257 cCE(fuhtod, ebb0b40, 2, (RVD, I16z), vfp_dp_conv_16), 16258 cCE(fultos, ebb0ac0, 2, (RVS, I32), vfp_sp_conv_32), 16259 cCE(fultod, ebb0bc0, 2, (RVD, I32), vfp_dp_conv_32), 16260 cCE(ftoshs, ebe0a40, 2, (RVS, I16z), vfp_sp_conv_16), 16261 cCE(ftoshd, ebe0b40, 2, (RVD, I16z), vfp_dp_conv_16), 16262 cCE(ftosls, ebe0ac0, 2, (RVS, I32), vfp_sp_conv_32), 16263 cCE(ftosld, ebe0bc0, 2, (RVD, I32), vfp_dp_conv_32), 16264 cCE(ftouhs, ebf0a40, 2, (RVS, I16z), vfp_sp_conv_16), 16265 cCE(ftouhd, ebf0b40, 2, (RVD, I16z), vfp_dp_conv_16), 16266 cCE(ftouls, ebf0ac0, 2, (RVS, I32), vfp_sp_conv_32), 16267 cCE(ftould, ebf0bc0, 2, (RVD, I32), vfp_dp_conv_32), 16268 16269#undef THUMB_VARIANT 16270#undef ARM_VARIANT 16271#define ARM_VARIANT &arm_cext_xscale /* Intel XScale extensions. */ 16272 cCE(mia, e200010, 3, (RXA, RRnpc, RRnpc), xsc_mia), 16273 cCE(miaph, e280010, 3, (RXA, RRnpc, RRnpc), xsc_mia), 16274 cCE(miabb, e2c0010, 3, (RXA, RRnpc, RRnpc), xsc_mia), 16275 cCE(miabt, e2d0010, 3, (RXA, RRnpc, RRnpc), xsc_mia), 16276 cCE(miatb, e2e0010, 3, (RXA, RRnpc, RRnpc), xsc_mia), 16277 cCE(miatt, e2f0010, 3, (RXA, RRnpc, RRnpc), xsc_mia), 16278 cCE(mar, c400000, 3, (RXA, RRnpc, RRnpc), xsc_mar), 16279 cCE(mra, c500000, 3, (RRnpc, RRnpc, RXA), xsc_mra), 16280 16281#undef ARM_VARIANT 16282#define ARM_VARIANT &arm_cext_iwmmxt /* Intel Wireless MMX technology. */ 16283 cCE(tandcb, e13f130, 1, (RR), iwmmxt_tandorc), 16284 cCE(tandch, e53f130, 1, (RR), iwmmxt_tandorc), 16285 cCE(tandcw, e93f130, 1, (RR), iwmmxt_tandorc), 16286 cCE(tbcstb, e400010, 2, (RIWR, RR), rn_rd), 16287 cCE(tbcsth, e400050, 2, (RIWR, RR), rn_rd), 16288 cCE(tbcstw, e400090, 2, (RIWR, RR), rn_rd), 16289 cCE(textrcb, e130170, 2, (RR, I7), iwmmxt_textrc), 16290 cCE(textrch, e530170, 2, (RR, I7), iwmmxt_textrc), 16291 cCE(textrcw, e930170, 2, (RR, I7), iwmmxt_textrc), 16292 cCE(textrmub, e100070, 3, (RR, RIWR, I7), iwmmxt_textrm), 16293 cCE(textrmuh, e500070, 3, (RR, RIWR, I7), iwmmxt_textrm), 16294 cCE(textrmuw, e900070, 3, (RR, RIWR, I7), iwmmxt_textrm), 16295 cCE(textrmsb, e100078, 3, (RR, RIWR, I7), iwmmxt_textrm), 16296 cCE(textrmsh, e500078, 3, (RR, RIWR, I7), iwmmxt_textrm), 16297 cCE(textrmsw, e900078, 3, (RR, RIWR, I7), iwmmxt_textrm), 16298 cCE(tinsrb, e600010, 3, (RIWR, RR, I7), iwmmxt_tinsr), 16299 cCE(tinsrh, e600050, 3, (RIWR, RR, I7), iwmmxt_tinsr), 16300 cCE(tinsrw, e600090, 3, (RIWR, RR, I7), iwmmxt_tinsr), 16301 cCE(tmcr, e000110, 2, (RIWC_RIWG, RR), rn_rd), 16302 cCE(tmcrr, c400000, 3, (RIWR, RR, RR), rm_rd_rn), 16303 cCE(tmia, e200010, 3, (RIWR, RR, RR), iwmmxt_tmia), 16304 cCE(tmiaph, e280010, 3, (RIWR, RR, RR), iwmmxt_tmia), 16305 cCE(tmiabb, e2c0010, 3, (RIWR, RR, RR), iwmmxt_tmia), 16306 cCE(tmiabt, e2d0010, 3, (RIWR, RR, RR), iwmmxt_tmia), 16307 cCE(tmiatb, e2e0010, 3, (RIWR, RR, RR), iwmmxt_tmia), 16308 cCE(tmiatt, e2f0010, 3, (RIWR, RR, RR), iwmmxt_tmia), 16309 cCE(tmovmskb, e100030, 2, (RR, RIWR), rd_rn), 16310 cCE(tmovmskh, e500030, 2, (RR, RIWR), rd_rn), 16311 cCE(tmovmskw, e900030, 2, (RR, RIWR), rd_rn), 16312 cCE(tmrc, e100110, 2, (RR, RIWC_RIWG), rd_rn), 16313 cCE(tmrrc, c500000, 3, (RR, RR, RIWR), rd_rn_rm), 16314 cCE(torcb, e13f150, 1, (RR), iwmmxt_tandorc), 16315 cCE(torch, e53f150, 1, (RR), iwmmxt_tandorc), 16316 cCE(torcw, e93f150, 1, (RR), iwmmxt_tandorc), 16317 cCE(waccb, e0001c0, 2, (RIWR, RIWR), rd_rn), 16318 cCE(wacch, e4001c0, 2, (RIWR, RIWR), rd_rn), 16319 cCE(waccw, e8001c0, 2, (RIWR, RIWR), rd_rn), 16320 cCE(waddbss, e300180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16321 cCE(waddb, e000180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16322 cCE(waddbus, e100180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16323 cCE(waddhss, e700180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16324 cCE(waddh, e400180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16325 cCE(waddhus, e500180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16326 cCE(waddwss, eb00180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16327 cCE(waddw, e800180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16328 cCE(waddwus, e900180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16329 cCE(waligni, e000020, 4, (RIWR, RIWR, RIWR, I7), iwmmxt_waligni), 16330 cCE(walignr0, e800020, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16331 cCE(walignr1, e900020, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16332 cCE(walignr2, ea00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16333 cCE(walignr3, eb00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16334 cCE(wand, e200000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16335 cCE(wandn, e300000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16336 cCE(wavg2b, e800000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16337 cCE(wavg2br, e900000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16338 cCE(wavg2h, ec00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16339 cCE(wavg2hr, ed00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16340 cCE(wcmpeqb, e000060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16341 cCE(wcmpeqh, e400060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16342 cCE(wcmpeqw, e800060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16343 cCE(wcmpgtub, e100060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16344 cCE(wcmpgtuh, e500060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16345 cCE(wcmpgtuw, e900060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16346 cCE(wcmpgtsb, e300060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16347 cCE(wcmpgtsh, e700060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16348 cCE(wcmpgtsw, eb00060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16349 cCE(wldrb, c100000, 2, (RIWR, ADDR), iwmmxt_wldstbh), 16350 cCE(wldrh, c500000, 2, (RIWR, ADDR), iwmmxt_wldstbh), 16351 cCE(wldrw, c100100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw), 16352 cCE(wldrd, c500100, 2, (RIWR, ADDR), iwmmxt_wldstd), 16353 cCE(wmacs, e600100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16354 cCE(wmacsz, e700100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16355 cCE(wmacu, e400100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16356 cCE(wmacuz, e500100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16357 cCE(wmadds, ea00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16358 cCE(wmaddu, e800100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16359 cCE(wmaxsb, e200160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16360 cCE(wmaxsh, e600160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16361 cCE(wmaxsw, ea00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16362 cCE(wmaxub, e000160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16363 cCE(wmaxuh, e400160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16364 cCE(wmaxuw, e800160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16365 cCE(wminsb, e300160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16366 cCE(wminsh, e700160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16367 cCE(wminsw, eb00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16368 cCE(wminub, e100160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16369 cCE(wminuh, e500160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16370 cCE(wminuw, e900160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16371 cCE(wmov, e000000, 2, (RIWR, RIWR), iwmmxt_wmov), 16372 cCE(wmulsm, e300100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16373 cCE(wmulsl, e200100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16374 cCE(wmulum, e100100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16375 cCE(wmulul, e000100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16376 cCE(wor, e000000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16377 cCE(wpackhss, e700080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16378 cCE(wpackhus, e500080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16379 cCE(wpackwss, eb00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16380 cCE(wpackwus, e900080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16381 cCE(wpackdss, ef00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16382 cCE(wpackdus, ed00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16383 cCE(wrorh, e700040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), 16384 cCE(wrorhg, e700148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), 16385 cCE(wrorw, eb00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), 16386 cCE(wrorwg, eb00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), 16387 cCE(wrord, ef00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), 16388 cCE(wrordg, ef00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), 16389 cCE(wsadb, e000120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16390 cCE(wsadbz, e100120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16391 cCE(wsadh, e400120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16392 cCE(wsadhz, e500120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16393 cCE(wshufh, e0001e0, 3, (RIWR, RIWR, I255), iwmmxt_wshufh), 16394 cCE(wsllh, e500040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), 16395 cCE(wsllhg, e500148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), 16396 cCE(wsllw, e900040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), 16397 cCE(wsllwg, e900148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), 16398 cCE(wslld, ed00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), 16399 cCE(wslldg, ed00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), 16400 cCE(wsrah, e400040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), 16401 cCE(wsrahg, e400148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), 16402 cCE(wsraw, e800040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), 16403 cCE(wsrawg, e800148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), 16404 cCE(wsrad, ec00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), 16405 cCE(wsradg, ec00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), 16406 cCE(wsrlh, e600040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), 16407 cCE(wsrlhg, e600148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), 16408 cCE(wsrlw, ea00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), 16409 cCE(wsrlwg, ea00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), 16410 cCE(wsrld, ee00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), 16411 cCE(wsrldg, ee00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), 16412 cCE(wstrb, c000000, 2, (RIWR, ADDR), iwmmxt_wldstbh), 16413 cCE(wstrh, c400000, 2, (RIWR, ADDR), iwmmxt_wldstbh), 16414 cCE(wstrw, c000100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw), 16415 cCE(wstrd, c400100, 2, (RIWR, ADDR), iwmmxt_wldstd), 16416 cCE(wsubbss, e3001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16417 cCE(wsubb, e0001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16418 cCE(wsubbus, e1001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16419 cCE(wsubhss, e7001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16420 cCE(wsubh, e4001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16421 cCE(wsubhus, e5001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16422 cCE(wsubwss, eb001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16423 cCE(wsubw, e8001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16424 cCE(wsubwus, e9001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16425 cCE(wunpckehub,e0000c0, 2, (RIWR, RIWR), rd_rn), 16426 cCE(wunpckehuh,e4000c0, 2, (RIWR, RIWR), rd_rn), 16427 cCE(wunpckehuw,e8000c0, 2, (RIWR, RIWR), rd_rn), 16428 cCE(wunpckehsb,e2000c0, 2, (RIWR, RIWR), rd_rn), 16429 cCE(wunpckehsh,e6000c0, 2, (RIWR, RIWR), rd_rn), 16430 cCE(wunpckehsw,ea000c0, 2, (RIWR, RIWR), rd_rn), 16431 cCE(wunpckihb, e1000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16432 cCE(wunpckihh, e5000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16433 cCE(wunpckihw, e9000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16434 cCE(wunpckelub,e0000e0, 2, (RIWR, RIWR), rd_rn), 16435 cCE(wunpckeluh,e4000e0, 2, (RIWR, RIWR), rd_rn), 16436 cCE(wunpckeluw,e8000e0, 2, (RIWR, RIWR), rd_rn), 16437 cCE(wunpckelsb,e2000e0, 2, (RIWR, RIWR), rd_rn), 16438 cCE(wunpckelsh,e6000e0, 2, (RIWR, RIWR), rd_rn), 16439 cCE(wunpckelsw,ea000e0, 2, (RIWR, RIWR), rd_rn), 16440 cCE(wunpckilb, e1000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16441 cCE(wunpckilh, e5000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16442 cCE(wunpckilw, e9000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16443 cCE(wxor, e100000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16444 cCE(wzero, e300000, 1, (RIWR), iwmmxt_wzero), 16445 16446#undef ARM_VARIANT 16447#define ARM_VARIANT &arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */ 16448 cCE(torvscb, e13f190, 1, (RR), iwmmxt_tandorc), 16449 cCE(torvsch, e53f190, 1, (RR), iwmmxt_tandorc), 16450 cCE(torvscw, e93f190, 1, (RR), iwmmxt_tandorc), 16451 cCE(wabsb, e2001c0, 2, (RIWR, RIWR), rd_rn), 16452 cCE(wabsh, e6001c0, 2, (RIWR, RIWR), rd_rn), 16453 cCE(wabsw, ea001c0, 2, (RIWR, RIWR), rd_rn), 16454 cCE(wabsdiffb, e1001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16455 cCE(wabsdiffh, e5001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16456 cCE(wabsdiffw, e9001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16457 cCE(waddbhusl, e2001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16458 cCE(waddbhusm, e6001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16459 cCE(waddhc, e600180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16460 cCE(waddwc, ea00180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16461 cCE(waddsubhx, ea001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16462 cCE(wavg4, e400000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16463 cCE(wavg4r, e500000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16464 cCE(wmaddsn, ee00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16465 cCE(wmaddsx, eb00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16466 cCE(wmaddun, ec00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16467 cCE(wmaddux, e900100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16468 cCE(wmerge, e000080, 4, (RIWR, RIWR, RIWR, I7), iwmmxt_wmerge), 16469 cCE(wmiabb, e0000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16470 cCE(wmiabt, e1000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16471 cCE(wmiatb, e2000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16472 cCE(wmiatt, e3000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16473 cCE(wmiabbn, e4000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16474 cCE(wmiabtn, e5000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16475 cCE(wmiatbn, e6000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16476 cCE(wmiattn, e7000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16477 cCE(wmiawbb, e800120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16478 cCE(wmiawbt, e900120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16479 cCE(wmiawtb, ea00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16480 cCE(wmiawtt, eb00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16481 cCE(wmiawbbn, ec00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16482 cCE(wmiawbtn, ed00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16483 cCE(wmiawtbn, ee00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16484 cCE(wmiawttn, ef00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16485 cCE(wmulsmr, ef00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16486 cCE(wmulumr, ed00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16487 cCE(wmulwumr, ec000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16488 cCE(wmulwsmr, ee000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16489 cCE(wmulwum, ed000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16490 cCE(wmulwsm, ef000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16491 cCE(wmulwl, eb000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16492 cCE(wqmiabb, e8000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16493 cCE(wqmiabt, e9000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16494 cCE(wqmiatb, ea000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16495 cCE(wqmiatt, eb000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16496 cCE(wqmiabbn, ec000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16497 cCE(wqmiabtn, ed000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16498 cCE(wqmiatbn, ee000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16499 cCE(wqmiattn, ef000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16500 cCE(wqmulm, e100080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16501 cCE(wqmulmr, e300080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16502 cCE(wqmulwm, ec000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16503 cCE(wqmulwmr, ee000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16504 cCE(wsubaddhx, ed001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16505 16506#undef ARM_VARIANT 16507#define ARM_VARIANT &arm_cext_maverick /* Cirrus Maverick instructions. */ 16508 cCE(cfldrs, c100400, 2, (RMF, ADDRGLDC), rd_cpaddr), 16509 cCE(cfldrd, c500400, 2, (RMD, ADDRGLDC), rd_cpaddr), 16510 cCE(cfldr32, c100500, 2, (RMFX, ADDRGLDC), rd_cpaddr), 16511 cCE(cfldr64, c500500, 2, (RMDX, ADDRGLDC), rd_cpaddr), 16512 cCE(cfstrs, c000400, 2, (RMF, ADDRGLDC), rd_cpaddr), 16513 cCE(cfstrd, c400400, 2, (RMD, ADDRGLDC), rd_cpaddr), 16514 cCE(cfstr32, c000500, 2, (RMFX, ADDRGLDC), rd_cpaddr), 16515 cCE(cfstr64, c400500, 2, (RMDX, ADDRGLDC), rd_cpaddr), 16516 cCE(cfmvsr, e000450, 2, (RMF, RR), rn_rd), 16517 cCE(cfmvrs, e100450, 2, (RR, RMF), rd_rn), 16518 cCE(cfmvdlr, e000410, 2, (RMD, RR), rn_rd), 16519 cCE(cfmvrdl, e100410, 2, (RR, RMD), rd_rn), 16520 cCE(cfmvdhr, e000430, 2, (RMD, RR), rn_rd), 16521 cCE(cfmvrdh, e100430, 2, (RR, RMD), rd_rn), 16522 cCE(cfmv64lr, e000510, 2, (RMDX, RR), rn_rd), 16523 cCE(cfmvr64l, e100510, 2, (RR, RMDX), rd_rn), 16524 cCE(cfmv64hr, e000530, 2, (RMDX, RR), rn_rd), 16525 cCE(cfmvr64h, e100530, 2, (RR, RMDX), rd_rn), 16526 cCE(cfmval32, e200440, 2, (RMAX, RMFX), rd_rn), 16527 cCE(cfmv32al, e100440, 2, (RMFX, RMAX), rd_rn), 16528 cCE(cfmvam32, e200460, 2, (RMAX, RMFX), rd_rn), 16529 cCE(cfmv32am, e100460, 2, (RMFX, RMAX), rd_rn), 16530 cCE(cfmvah32, e200480, 2, (RMAX, RMFX), rd_rn), 16531 cCE(cfmv32ah, e100480, 2, (RMFX, RMAX), rd_rn), 16532 cCE(cfmva32, e2004a0, 2, (RMAX, RMFX), rd_rn), 16533 cCE(cfmv32a, e1004a0, 2, (RMFX, RMAX), rd_rn), 16534 cCE(cfmva64, e2004c0, 2, (RMAX, RMDX), rd_rn), 16535 cCE(cfmv64a, e1004c0, 2, (RMDX, RMAX), rd_rn), 16536 cCE(cfmvsc32, e2004e0, 2, (RMDS, RMDX), mav_dspsc), 16537 cCE(cfmv32sc, e1004e0, 2, (RMDX, RMDS), rd), 16538 cCE(cfcpys, e000400, 2, (RMF, RMF), rd_rn), 16539 cCE(cfcpyd, e000420, 2, (RMD, RMD), rd_rn), 16540 cCE(cfcvtsd, e000460, 2, (RMD, RMF), rd_rn), 16541 cCE(cfcvtds, e000440, 2, (RMF, RMD), rd_rn), 16542 cCE(cfcvt32s, e000480, 2, (RMF, RMFX), rd_rn), 16543 cCE(cfcvt32d, e0004a0, 2, (RMD, RMFX), rd_rn), 16544 cCE(cfcvt64s, e0004c0, 2, (RMF, RMDX), rd_rn), 16545 cCE(cfcvt64d, e0004e0, 2, (RMD, RMDX), rd_rn), 16546 cCE(cfcvts32, e100580, 2, (RMFX, RMF), rd_rn), 16547 cCE(cfcvtd32, e1005a0, 2, (RMFX, RMD), rd_rn), 16548 cCE(cftruncs32,e1005c0, 2, (RMFX, RMF), rd_rn), 16549 cCE(cftruncd32,e1005e0, 2, (RMFX, RMD), rd_rn), 16550 cCE(cfrshl32, e000550, 3, (RMFX, RMFX, RR), mav_triple), 16551 cCE(cfrshl64, e000570, 3, (RMDX, RMDX, RR), mav_triple), 16552 cCE(cfsh32, e000500, 3, (RMFX, RMFX, I63s), mav_shift), 16553 cCE(cfsh64, e200500, 3, (RMDX, RMDX, I63s), mav_shift), 16554 cCE(cfcmps, e100490, 3, (RR, RMF, RMF), rd_rn_rm), 16555 cCE(cfcmpd, e1004b0, 3, (RR, RMD, RMD), rd_rn_rm), 16556 cCE(cfcmp32, e100590, 3, (RR, RMFX, RMFX), rd_rn_rm), 16557 cCE(cfcmp64, e1005b0, 3, (RR, RMDX, RMDX), rd_rn_rm), 16558 cCE(cfabss, e300400, 2, (RMF, RMF), rd_rn), 16559 cCE(cfabsd, e300420, 2, (RMD, RMD), rd_rn), 16560 cCE(cfnegs, e300440, 2, (RMF, RMF), rd_rn), 16561 cCE(cfnegd, e300460, 2, (RMD, RMD), rd_rn), 16562 cCE(cfadds, e300480, 3, (RMF, RMF, RMF), rd_rn_rm), 16563 cCE(cfaddd, e3004a0, 3, (RMD, RMD, RMD), rd_rn_rm), 16564 cCE(cfsubs, e3004c0, 3, (RMF, RMF, RMF), rd_rn_rm), 16565 cCE(cfsubd, e3004e0, 3, (RMD, RMD, RMD), rd_rn_rm), 16566 cCE(cfmuls, e100400, 3, (RMF, RMF, RMF), rd_rn_rm), 16567 cCE(cfmuld, e100420, 3, (RMD, RMD, RMD), rd_rn_rm), 16568 cCE(cfabs32, e300500, 2, (RMFX, RMFX), rd_rn), 16569 cCE(cfabs64, e300520, 2, (RMDX, RMDX), rd_rn), 16570 cCE(cfneg32, e300540, 2, (RMFX, RMFX), rd_rn), 16571 cCE(cfneg64, e300560, 2, (RMDX, RMDX), rd_rn), 16572 cCE(cfadd32, e300580, 3, (RMFX, RMFX, RMFX), rd_rn_rm), 16573 cCE(cfadd64, e3005a0, 3, (RMDX, RMDX, RMDX), rd_rn_rm), 16574 cCE(cfsub32, e3005c0, 3, (RMFX, RMFX, RMFX), rd_rn_rm), 16575 cCE(cfsub64, e3005e0, 3, (RMDX, RMDX, RMDX), rd_rn_rm), 16576 cCE(cfmul32, e100500, 3, (RMFX, RMFX, RMFX), rd_rn_rm), 16577 cCE(cfmul64, e100520, 3, (RMDX, RMDX, RMDX), rd_rn_rm), 16578 cCE(cfmac32, e100540, 3, (RMFX, RMFX, RMFX), rd_rn_rm), 16579 cCE(cfmsc32, e100560, 3, (RMFX, RMFX, RMFX), rd_rn_rm), 16580 cCE(cfmadd32, e000600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad), 16581 cCE(cfmsub32, e100600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad), 16582 cCE(cfmadda32, e200600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad), 16583 cCE(cfmsuba32, e300600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad), 16584}; 16585#undef ARM_VARIANT 16586#undef THUMB_VARIANT 16587#undef TCE 16588#undef TCM 16589#undef TUE 16590#undef TUF 16591#undef TCC 16592#undef cCE 16593#undef cCL 16594#undef C3E 16595#undef CE 16596#undef CM 16597#undef UE 16598#undef UF 16599#undef UT 16600#undef NUF 16601#undef nUF 16602#undef NCE 16603#undef nCE 16604#undef OPS0 16605#undef OPS1 16606#undef OPS2 16607#undef OPS3 16608#undef OPS4 16609#undef OPS5 16610#undef OPS6 16611#undef do_0 16612 16613/* MD interface: bits in the object file. */ 16614 16615/* Turn an integer of n bytes (in val) into a stream of bytes appropriate 16616 for use in the a.out file, and stores them in the array pointed to by buf. 16617 This knows about the endian-ness of the target machine and does 16618 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte) 16619 2 (short) and 4 (long) Floating numbers are put out as a series of 16620 LITTLENUMS (shorts, here at least). */ 16621 16622void 16623md_number_to_chars (char * buf, valueT val, int n) 16624{ 16625 if (target_big_endian) 16626 number_to_chars_bigendian (buf, val, n); 16627 else 16628 number_to_chars_littleendian (buf, val, n); 16629} 16630 16631static valueT 16632md_chars_to_number (char * buf, int n) 16633{ 16634 valueT result = 0; 16635 unsigned char * where = (unsigned char *) buf; 16636 16637 if (target_big_endian) 16638 { 16639 while (n--) 16640 { 16641 result <<= 8; 16642 result |= (*where++ & 255); 16643 } 16644 } 16645 else 16646 { 16647 while (n--) 16648 { 16649 result <<= 8; 16650 result |= (where[n] & 255); 16651 } 16652 } 16653 16654 return result; 16655} 16656 16657/* MD interface: Sections. */ 16658 16659/* Estimate the size of a frag before relaxing. Assume everything fits in 16660 2 bytes. */ 16661 16662int 16663md_estimate_size_before_relax (fragS * fragp, 16664 segT segtype ATTRIBUTE_UNUSED) 16665{ 16666 fragp->fr_var = 2; 16667 return 2; 16668} 16669 16670/* Convert a machine dependent frag. */ 16671 16672void 16673md_convert_frag (bfd *abfd, segT asec ATTRIBUTE_UNUSED, fragS *fragp) 16674{ 16675 unsigned long insn; 16676 unsigned long old_op; 16677 char *buf; 16678 expressionS exp; 16679 fixS *fixp; 16680 int reloc_type; 16681 int pc_rel; 16682 int opcode; 16683 16684 buf = fragp->fr_literal + fragp->fr_fix; 16685 16686 old_op = bfd_get_16(abfd, buf); 16687 if (fragp->fr_symbol) { 16688 exp.X_op = O_symbol; 16689 exp.X_add_symbol = fragp->fr_symbol; 16690 } else { 16691 exp.X_op = O_constant; 16692 } 16693 exp.X_add_number = fragp->fr_offset; 16694 opcode = fragp->fr_subtype; 16695 switch (opcode) 16696 { 16697 case T_MNEM_ldr_pc: 16698 case T_MNEM_ldr_pc2: 16699 case T_MNEM_ldr_sp: 16700 case T_MNEM_str_sp: 16701 case T_MNEM_ldr: 16702 case T_MNEM_ldrb: 16703 case T_MNEM_ldrh: 16704 case T_MNEM_str: 16705 case T_MNEM_strb: 16706 case T_MNEM_strh: 16707 if (fragp->fr_var == 4) 16708 { 16709 insn = THUMB_OP32(opcode); 16710 if ((old_op >> 12) == 4 || (old_op >> 12) == 9) 16711 { 16712 insn |= (old_op & 0x700) << 4; 16713 } 16714 else 16715 { 16716 insn |= (old_op & 7) << 12; 16717 insn |= (old_op & 0x38) << 13; 16718 } 16719 insn |= 0x00000c00; 16720 put_thumb32_insn (buf, insn); 16721 reloc_type = BFD_RELOC_ARM_T32_OFFSET_IMM; 16722 } 16723 else 16724 { 16725 reloc_type = BFD_RELOC_ARM_THUMB_OFFSET; 16726 } 16727 pc_rel = (opcode == T_MNEM_ldr_pc2); 16728 break; 16729 case T_MNEM_adr: 16730 if (fragp->fr_var == 4) 16731 { 16732 insn = THUMB_OP32 (opcode); 16733 insn |= (old_op & 0xf0) << 4; 16734 put_thumb32_insn (buf, insn); 16735 reloc_type = BFD_RELOC_ARM_T32_ADD_PC12; 16736 } 16737 else 16738 { 16739 reloc_type = BFD_RELOC_ARM_THUMB_ADD; 16740 exp.X_add_number -= 4; 16741 } 16742 pc_rel = 1; 16743 break; 16744 case T_MNEM_mov: 16745 case T_MNEM_movs: 16746 case T_MNEM_cmp: 16747 case T_MNEM_cmn: 16748 if (fragp->fr_var == 4) 16749 { 16750 int r0off = (opcode == T_MNEM_mov 16751 || opcode == T_MNEM_movs) ? 0 : 8; 16752 insn = THUMB_OP32 (opcode); 16753 insn = (insn & 0xe1ffffff) | 0x10000000; 16754 insn |= (old_op & 0x700) << r0off; 16755 put_thumb32_insn (buf, insn); 16756 reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE; 16757 } 16758 else 16759 { 16760 reloc_type = BFD_RELOC_ARM_THUMB_IMM; 16761 } 16762 pc_rel = 0; 16763 break; 16764 case T_MNEM_b: 16765 if (fragp->fr_var == 4) 16766 { 16767 insn = THUMB_OP32(opcode); 16768 put_thumb32_insn (buf, insn); 16769 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH25; 16770 } 16771 else 16772 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH12; 16773 pc_rel = 1; 16774 break; 16775 case T_MNEM_bcond: 16776 if (fragp->fr_var == 4) 16777 { 16778 insn = THUMB_OP32(opcode); 16779 insn |= (old_op & 0xf00) << 14; 16780 put_thumb32_insn (buf, insn); 16781 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH20; 16782 } 16783 else 16784 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH9; 16785 pc_rel = 1; 16786 break; 16787 case T_MNEM_add_sp: 16788 case T_MNEM_add_pc: 16789 case T_MNEM_inc_sp: 16790 case T_MNEM_dec_sp: 16791 if (fragp->fr_var == 4) 16792 { 16793 /* ??? Choose between add and addw. */ 16794 insn = THUMB_OP32 (opcode); 16795 insn |= (old_op & 0xf0) << 4; 16796 put_thumb32_insn (buf, insn); 16797 if (opcode == T_MNEM_add_pc) 16798 reloc_type = BFD_RELOC_ARM_T32_IMM12; 16799 else 16800 reloc_type = BFD_RELOC_ARM_T32_ADD_IMM; 16801 } 16802 else 16803 reloc_type = BFD_RELOC_ARM_THUMB_ADD; 16804 pc_rel = 0; 16805 break; 16806 16807 case T_MNEM_addi: 16808 case T_MNEM_addis: 16809 case T_MNEM_subi: 16810 case T_MNEM_subis: 16811 if (fragp->fr_var == 4) 16812 { 16813 insn = THUMB_OP32 (opcode); 16814 insn |= (old_op & 0xf0) << 4; 16815 insn |= (old_op & 0xf) << 16; 16816 put_thumb32_insn (buf, insn); 16817 if (insn & (1 << 20)) 16818 reloc_type = BFD_RELOC_ARM_T32_ADD_IMM; 16819 else 16820 reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE; 16821 } 16822 else 16823 reloc_type = BFD_RELOC_ARM_THUMB_ADD; 16824 pc_rel = 0; 16825 break; 16826 default: 16827 abort(); 16828 } 16829 fixp = fix_new_exp (fragp, fragp->fr_fix, fragp->fr_var, &exp, pc_rel, 16830 reloc_type); 16831 fixp->fx_file = fragp->fr_file; 16832 fixp->fx_line = fragp->fr_line; 16833 fragp->fr_fix += fragp->fr_var; 16834} 16835 16836/* Return the size of a relaxable immediate operand instruction. 16837 SHIFT and SIZE specify the form of the allowable immediate. */ 16838static int 16839relax_immediate (fragS *fragp, int size, int shift) 16840{ 16841 offsetT offset; 16842 offsetT mask; 16843 offsetT low; 16844 16845 /* ??? Should be able to do better than this. */ 16846 if (fragp->fr_symbol) 16847 return 4; 16848 16849 low = (1 << shift) - 1; 16850 mask = (1 << (shift + size)) - (1 << shift); 16851 offset = fragp->fr_offset; 16852 /* Force misaligned offsets to 32-bit variant. */ 16853 if (offset & low) 16854 return 4; 16855 if (offset & ~mask) 16856 return 4; 16857 return 2; 16858} 16859 16860/* Get the address of a symbol during relaxation. */ 16861static addressT 16862relaxed_symbol_addr(fragS *fragp, long stretch) 16863{ 16864 fragS *sym_frag; 16865 addressT addr; 16866 symbolS *sym; 16867 16868 sym = fragp->fr_symbol; 16869 sym_frag = symbol_get_frag (sym); 16870 know (S_GET_SEGMENT (sym) != absolute_section 16871 || sym_frag == &zero_address_frag); 16872 addr = S_GET_VALUE (sym) + fragp->fr_offset; 16873 16874 /* If frag has yet to be reached on this pass, assume it will 16875 move by STRETCH just as we did. If this is not so, it will 16876 be because some frag between grows, and that will force 16877 another pass. */ 16878 16879 if (stretch != 0 16880 && sym_frag->relax_marker != fragp->relax_marker) 16881 addr += stretch; 16882 16883 return addr; 16884} 16885 16886/* Return the size of a relaxable adr pseudo-instruction or PC-relative 16887 load. */ 16888static int 16889relax_adr (fragS *fragp, asection *sec, long stretch) 16890{ 16891 addressT addr; 16892 offsetT val; 16893 16894 /* Assume worst case for symbols not known to be in the same section. */ 16895 if (!S_IS_DEFINED(fragp->fr_symbol) 16896 || sec != S_GET_SEGMENT (fragp->fr_symbol)) 16897 return 4; 16898 16899 val = relaxed_symbol_addr(fragp, stretch); 16900 addr = fragp->fr_address + fragp->fr_fix; 16901 addr = (addr + 4) & ~3; 16902 /* Force misaligned targets to 32-bit variant. */ 16903 if (val & 3) 16904 return 4; 16905 val -= addr; 16906 if (val < 0 || val > 1020) 16907 return 4; 16908 return 2; 16909} 16910 16911/* Return the size of a relaxable add/sub immediate instruction. */ 16912static int 16913relax_addsub (fragS *fragp, asection *sec) 16914{ 16915 char *buf; 16916 int op; 16917 16918 buf = fragp->fr_literal + fragp->fr_fix; 16919 op = bfd_get_16(sec->owner, buf); 16920 if ((op & 0xf) == ((op >> 4) & 0xf)) 16921 return relax_immediate (fragp, 8, 0); 16922 else 16923 return relax_immediate (fragp, 3, 0); 16924} 16925 16926 16927/* Return the size of a relaxable branch instruction. BITS is the 16928 size of the offset field in the narrow instruction. */ 16929 16930static int 16931relax_branch (fragS *fragp, asection *sec, int bits, long stretch) 16932{ 16933 addressT addr; 16934 offsetT val; 16935 offsetT limit; 16936 16937 /* Assume worst case for symbols not known to be in the same section. */ 16938 if (!S_IS_DEFINED(fragp->fr_symbol) 16939 || sec != S_GET_SEGMENT (fragp->fr_symbol)) 16940 return 4; 16941 16942 val = relaxed_symbol_addr(fragp, stretch); 16943 addr = fragp->fr_address + fragp->fr_fix + 4; 16944 val -= addr; 16945 16946 /* Offset is a signed value *2 */ 16947 limit = 1 << bits; 16948 if (val >= limit || val < -limit) 16949 return 4; 16950 return 2; 16951} 16952 16953 16954/* Relax a machine dependent frag. This returns the amount by which 16955 the current size of the frag should change. */ 16956 16957int 16958arm_relax_frag (asection *sec, fragS *fragp, long stretch) 16959{ 16960 int oldsize; 16961 int newsize; 16962 16963 oldsize = fragp->fr_var; 16964 switch (fragp->fr_subtype) 16965 { 16966 case T_MNEM_ldr_pc2: 16967 newsize = relax_adr(fragp, sec, stretch); 16968 break; 16969 case T_MNEM_ldr_pc: 16970 case T_MNEM_ldr_sp: 16971 case T_MNEM_str_sp: 16972 newsize = relax_immediate(fragp, 8, 2); 16973 break; 16974 case T_MNEM_ldr: 16975 case T_MNEM_str: 16976 newsize = relax_immediate(fragp, 5, 2); 16977 break; 16978 case T_MNEM_ldrh: 16979 case T_MNEM_strh: 16980 newsize = relax_immediate(fragp, 5, 1); 16981 break; 16982 case T_MNEM_ldrb: 16983 case T_MNEM_strb: 16984 newsize = relax_immediate(fragp, 5, 0); 16985 break; 16986 case T_MNEM_adr: 16987 newsize = relax_adr(fragp, sec, stretch); 16988 break; 16989 case T_MNEM_mov: 16990 case T_MNEM_movs: 16991 case T_MNEM_cmp: 16992 case T_MNEM_cmn: 16993 newsize = relax_immediate(fragp, 8, 0); 16994 break; 16995 case T_MNEM_b: 16996 newsize = relax_branch(fragp, sec, 11, stretch); 16997 break; 16998 case T_MNEM_bcond: 16999 newsize = relax_branch(fragp, sec, 8, stretch); 17000 break; 17001 case T_MNEM_add_sp: 17002 case T_MNEM_add_pc: 17003 newsize = relax_immediate (fragp, 8, 2); 17004 break; 17005 case T_MNEM_inc_sp: 17006 case T_MNEM_dec_sp: 17007 newsize = relax_immediate (fragp, 7, 2); 17008 break; 17009 case T_MNEM_addi: 17010 case T_MNEM_addis: 17011 case T_MNEM_subi: 17012 case T_MNEM_subis: 17013 newsize = relax_addsub (fragp, sec); 17014 break; 17015 default: 17016 abort(); 17017 } 17018 17019 fragp->fr_var = newsize; 17020 /* Freeze wide instructions that are at or before the same location as 17021 in the previous pass. This avoids infinite loops. 17022 Don't freeze them unconditionally because targets may be artificialy 17023 misaligned by the expansion of preceeding frags. */ 17024 if (stretch <= 0 && newsize > 2) 17025 { 17026 md_convert_frag (sec->owner, sec, fragp); 17027 frag_wane(fragp); 17028 } 17029 17030 return newsize - oldsize; 17031} 17032 17033/* Round up a section size to the appropriate boundary. */ 17034 17035valueT 17036md_section_align (segT segment ATTRIBUTE_UNUSED, 17037 valueT size) 17038{ 17039#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) 17040 if (OUTPUT_FLAVOR == bfd_target_aout_flavour) 17041 { 17042 /* For a.out, force the section size to be aligned. If we don't do 17043 this, BFD will align it for us, but it will not write out the 17044 final bytes of the section. This may be a bug in BFD, but it is 17045 easier to fix it here since that is how the other a.out targets 17046 work. */ 17047 int align; 17048 17049 align = bfd_get_section_alignment (stdoutput, segment); 17050 size = ((size + (1 << align) - 1) & ((valueT) -1 << align)); 17051 } 17052#endif 17053 17054 return size; 17055} 17056 17057/* This is called from HANDLE_ALIGN in write.c. Fill in the contents 17058 of an rs_align_code fragment. */ 17059 17060void 17061arm_handle_align (fragS * fragP) 17062{ 17063 static char const arm_noop[4] = { 0x00, 0x00, 0xa0, 0xe1 }; 17064 static char const thumb_noop[2] = { 0xc0, 0x46 }; 17065 static char const arm_bigend_noop[4] = { 0xe1, 0xa0, 0x00, 0x00 }; 17066 static char const thumb_bigend_noop[2] = { 0x46, 0xc0 }; 17067 17068 int bytes, fix, noop_size; 17069 char * p; 17070 const char * noop; 17071 17072 if (fragP->fr_type != rs_align_code) 17073 return; 17074 17075 bytes = fragP->fr_next->fr_address - fragP->fr_address - fragP->fr_fix; 17076 p = fragP->fr_literal + fragP->fr_fix; 17077 fix = 0; 17078 17079 if (bytes > MAX_MEM_FOR_RS_ALIGN_CODE) 17080 bytes &= MAX_MEM_FOR_RS_ALIGN_CODE; 17081 17082 if (fragP->tc_frag_data) 17083 { 17084 if (target_big_endian) 17085 noop = thumb_bigend_noop; 17086 else 17087 noop = thumb_noop; 17088 noop_size = sizeof (thumb_noop); 17089 } 17090 else 17091 { 17092 if (target_big_endian) 17093 noop = arm_bigend_noop; 17094 else 17095 noop = arm_noop; 17096 noop_size = sizeof (arm_noop); 17097 } 17098 17099 if (bytes & (noop_size - 1)) 17100 { 17101 fix = bytes & (noop_size - 1); 17102 memset (p, 0, fix); 17103 p += fix; 17104 bytes -= fix; 17105 } 17106 17107 while (bytes >= noop_size) 17108 { 17109 memcpy (p, noop, noop_size); 17110 p += noop_size; 17111 bytes -= noop_size; 17112 fix += noop_size; 17113 } 17114 17115 fragP->fr_fix += fix; 17116 fragP->fr_var = noop_size; 17117} 17118 17119/* Called from md_do_align. Used to create an alignment 17120 frag in a code section. */ 17121 17122void 17123arm_frag_align_code (int n, int max) 17124{ 17125 char * p; 17126 17127 /* We assume that there will never be a requirement 17128 to support alignments greater than 32 bytes. */ 17129 if (max > MAX_MEM_FOR_RS_ALIGN_CODE) 17130 as_fatal (_("alignments greater than 32 bytes not supported in .text sections.")); 17131 17132 p = frag_var (rs_align_code, 17133 MAX_MEM_FOR_RS_ALIGN_CODE, 17134 1, 17135 (relax_substateT) max, 17136 (symbolS *) NULL, 17137 (offsetT) n, 17138 (char *) NULL); 17139 *p = 0; 17140} 17141 17142/* Perform target specific initialisation of a frag. */ 17143 17144void 17145arm_init_frag (fragS * fragP) 17146{ 17147 /* Record whether this frag is in an ARM or a THUMB area. */ 17148 fragP->tc_frag_data = thumb_mode; 17149} 17150 17151#ifdef OBJ_ELF 17152/* When we change sections we need to issue a new mapping symbol. */ 17153 17154void 17155arm_elf_change_section (void) 17156{ 17157 flagword flags; 17158 segment_info_type *seginfo; 17159 17160 /* Link an unlinked unwind index table section to the .text section. */ 17161 if (elf_section_type (now_seg) == SHT_ARM_EXIDX 17162 && elf_linked_to_section (now_seg) == NULL) 17163 elf_linked_to_section (now_seg) = text_section; 17164 17165 if (!SEG_NORMAL (now_seg)) 17166 return; 17167 17168 flags = bfd_get_section_flags (stdoutput, now_seg); 17169 17170 /* We can ignore sections that only contain debug info. */ 17171 if ((flags & SEC_ALLOC) == 0) 17172 return; 17173 17174 seginfo = seg_info (now_seg); 17175 mapstate = seginfo->tc_segment_info_data.mapstate; 17176 marked_pr_dependency = seginfo->tc_segment_info_data.marked_pr_dependency; 17177} 17178 17179int 17180arm_elf_section_type (const char * str, size_t len) 17181{ 17182 if (len == 5 && strncmp (str, "exidx", 5) == 0) 17183 return SHT_ARM_EXIDX; 17184 17185 return -1; 17186} 17187 17188/* Code to deal with unwinding tables. */ 17189 17190static void add_unwind_adjustsp (offsetT); 17191 17192/* Cenerate and deferred unwind frame offset. */ 17193 17194static void 17195flush_pending_unwind (void) 17196{ 17197 offsetT offset; 17198 17199 offset = unwind.pending_offset; 17200 unwind.pending_offset = 0; 17201 if (offset != 0) 17202 add_unwind_adjustsp (offset); 17203} 17204 17205/* Add an opcode to this list for this function. Two-byte opcodes should 17206 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse 17207 order. */ 17208 17209static void 17210add_unwind_opcode (valueT op, int length) 17211{ 17212 /* Add any deferred stack adjustment. */ 17213 if (unwind.pending_offset) 17214 flush_pending_unwind (); 17215 17216 unwind.sp_restored = 0; 17217 17218 if (unwind.opcode_count + length > unwind.opcode_alloc) 17219 { 17220 unwind.opcode_alloc += ARM_OPCODE_CHUNK_SIZE; 17221 if (unwind.opcodes) 17222 unwind.opcodes = xrealloc (unwind.opcodes, 17223 unwind.opcode_alloc); 17224 else 17225 unwind.opcodes = xmalloc (unwind.opcode_alloc); 17226 } 17227 while (length > 0) 17228 { 17229 length--; 17230 unwind.opcodes[unwind.opcode_count] = op & 0xff; 17231 op >>= 8; 17232 unwind.opcode_count++; 17233 } 17234} 17235 17236/* Add unwind opcodes to adjust the stack pointer. */ 17237 17238static void 17239add_unwind_adjustsp (offsetT offset) 17240{ 17241 valueT op; 17242 17243 if (offset > 0x200) 17244 { 17245 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */ 17246 char bytes[5]; 17247 int n; 17248 valueT o; 17249 17250 /* Long form: 0xb2, uleb128. */ 17251 /* This might not fit in a word so add the individual bytes, 17252 remembering the list is built in reverse order. */ 17253 o = (valueT) ((offset - 0x204) >> 2); 17254 if (o == 0) 17255 add_unwind_opcode (0, 1); 17256 17257 /* Calculate the uleb128 encoding of the offset. */ 17258 n = 0; 17259 while (o) 17260 { 17261 bytes[n] = o & 0x7f; 17262 o >>= 7; 17263 if (o) 17264 bytes[n] |= 0x80; 17265 n++; 17266 } 17267 /* Add the insn. */ 17268 for (; n; n--) 17269 add_unwind_opcode (bytes[n - 1], 1); 17270 add_unwind_opcode (0xb2, 1); 17271 } 17272 else if (offset > 0x100) 17273 { 17274 /* Two short opcodes. */ 17275 add_unwind_opcode (0x3f, 1); 17276 op = (offset - 0x104) >> 2; 17277 add_unwind_opcode (op, 1); 17278 } 17279 else if (offset > 0) 17280 { 17281 /* Short opcode. */ 17282 op = (offset - 4) >> 2; 17283 add_unwind_opcode (op, 1); 17284 } 17285 else if (offset < 0) 17286 { 17287 offset = -offset; 17288 while (offset > 0x100) 17289 { 17290 add_unwind_opcode (0x7f, 1); 17291 offset -= 0x100; 17292 } 17293 op = ((offset - 4) >> 2) | 0x40; 17294 add_unwind_opcode (op, 1); 17295 } 17296} 17297 17298/* Finish the list of unwind opcodes for this function. */ 17299static void 17300finish_unwind_opcodes (void) 17301{ 17302 valueT op; 17303 17304 if (unwind.fp_used) 17305 { 17306 /* Adjust sp as necessary. */ 17307 unwind.pending_offset += unwind.fp_offset - unwind.frame_size; 17308 flush_pending_unwind (); 17309 17310 /* After restoring sp from the frame pointer. */ 17311 op = 0x90 | unwind.fp_reg; 17312 add_unwind_opcode (op, 1); 17313 } 17314 else 17315 flush_pending_unwind (); 17316} 17317 17318 17319/* Start an exception table entry. If idx is nonzero this is an index table 17320 entry. */ 17321 17322static void 17323start_unwind_section (const segT text_seg, int idx) 17324{ 17325 const char * text_name; 17326 const char * prefix; 17327 const char * prefix_once; 17328 const char * group_name; 17329 size_t prefix_len; 17330 size_t text_len; 17331 char * sec_name; 17332 size_t sec_name_len; 17333 int type; 17334 int flags; 17335 int linkonce; 17336 17337 if (idx) 17338 { 17339 prefix = ELF_STRING_ARM_unwind; 17340 prefix_once = ELF_STRING_ARM_unwind_once; 17341 type = SHT_ARM_EXIDX; 17342 } 17343 else 17344 { 17345 prefix = ELF_STRING_ARM_unwind_info; 17346 prefix_once = ELF_STRING_ARM_unwind_info_once; 17347 type = SHT_PROGBITS; 17348 } 17349 17350 text_name = segment_name (text_seg); 17351 if (streq (text_name, ".text")) 17352 text_name = ""; 17353 17354 if (strncmp (text_name, ".gnu.linkonce.t.", 17355 strlen (".gnu.linkonce.t.")) == 0) 17356 { 17357 prefix = prefix_once; 17358 text_name += strlen (".gnu.linkonce.t."); 17359 } 17360 17361 prefix_len = strlen (prefix); 17362 text_len = strlen (text_name); 17363 sec_name_len = prefix_len + text_len; 17364 sec_name = xmalloc (sec_name_len + 1); 17365 memcpy (sec_name, prefix, prefix_len); 17366 memcpy (sec_name + prefix_len, text_name, text_len); 17367 sec_name[prefix_len + text_len] = '\0'; 17368 17369 flags = SHF_ALLOC; 17370 linkonce = 0; 17371 group_name = 0; 17372 17373 /* Handle COMDAT group. */ 17374 if (prefix != prefix_once && (text_seg->flags & SEC_LINK_ONCE) != 0) 17375 { 17376 group_name = elf_group_name (text_seg); 17377 if (group_name == NULL) 17378 { 17379 as_bad ("Group section `%s' has no group signature", 17380 segment_name (text_seg)); 17381 ignore_rest_of_line (); 17382 return; 17383 } 17384 flags |= SHF_GROUP; 17385 linkonce = 1; 17386 } 17387 17388 obj_elf_change_section (sec_name, type, flags, 0, group_name, linkonce, 0); 17389 17390 /* Set the setion link for index tables. */ 17391 if (idx) 17392 elf_linked_to_section (now_seg) = text_seg; 17393} 17394 17395 17396/* Start an unwind table entry. HAVE_DATA is nonzero if we have additional 17397 personality routine data. Returns zero, or the index table value for 17398 and inline entry. */ 17399 17400static valueT 17401create_unwind_entry (int have_data) 17402{ 17403 int size; 17404 addressT where; 17405 char *ptr; 17406 /* The current word of data. */ 17407 valueT data; 17408 /* The number of bytes left in this word. */ 17409 int n; 17410 17411 finish_unwind_opcodes (); 17412 17413 /* Remember the current text section. */ 17414 unwind.saved_seg = now_seg; 17415 unwind.saved_subseg = now_subseg; 17416 17417 start_unwind_section (now_seg, 0); 17418 17419 if (unwind.personality_routine == NULL) 17420 { 17421 if (unwind.personality_index == -2) 17422 { 17423 if (have_data) 17424 as_bad (_("handerdata in cantunwind frame")); 17425 return 1; /* EXIDX_CANTUNWIND. */ 17426 } 17427 17428 /* Use a default personality routine if none is specified. */ 17429 if (unwind.personality_index == -1) 17430 { 17431 if (unwind.opcode_count > 3) 17432 unwind.personality_index = 1; 17433 else 17434 unwind.personality_index = 0; 17435 } 17436 17437 /* Space for the personality routine entry. */ 17438 if (unwind.personality_index == 0) 17439 { 17440 if (unwind.opcode_count > 3) 17441 as_bad (_("too many unwind opcodes for personality routine 0")); 17442 17443 if (!have_data) 17444 { 17445 /* All the data is inline in the index table. */ 17446 data = 0x80; 17447 n = 3; 17448 while (unwind.opcode_count > 0) 17449 { 17450 unwind.opcode_count--; 17451 data = (data << 8) | unwind.opcodes[unwind.opcode_count]; 17452 n--; 17453 } 17454 17455 /* Pad with "finish" opcodes. */ 17456 while (n--) 17457 data = (data << 8) | 0xb0; 17458 17459 return data; 17460 } 17461 size = 0; 17462 } 17463 else 17464 /* We get two opcodes "free" in the first word. */ 17465 size = unwind.opcode_count - 2; 17466 } 17467 else 17468 /* An extra byte is required for the opcode count. */ 17469 size = unwind.opcode_count + 1; 17470 17471 size = (size + 3) >> 2; 17472 if (size > 0xff) 17473 as_bad (_("too many unwind opcodes")); 17474 17475 frag_align (2, 0, 0); 17476 record_alignment (now_seg, 2); 17477 unwind.table_entry = expr_build_dot (); 17478 17479 /* Allocate the table entry. */ 17480 ptr = frag_more ((size << 2) + 4); 17481 memset(ptr, 0, (size << 2) + 4); 17482 where = frag_now_fix () - ((size << 2) + 4); 17483 17484 switch (unwind.personality_index) 17485 { 17486 case -1: 17487 /* ??? Should this be a PLT generating relocation? */ 17488 /* Custom personality routine. */ 17489 fix_new (frag_now, where, 4, unwind.personality_routine, 0, 1, 17490 BFD_RELOC_ARM_PREL31); 17491 17492 where += 4; 17493 ptr += 4; 17494 17495 /* Set the first byte to the number of additional words. */ 17496 data = size - 1; 17497 n = 3; 17498 break; 17499 17500 /* ABI defined personality routines. */ 17501 case 0: 17502 /* Three opcodes bytes are packed into the first word. */ 17503 data = 0x80; 17504 n = 3; 17505 break; 17506 17507 case 1: 17508 case 2: 17509 /* The size and first two opcode bytes go in the first word. */ 17510 data = ((0x80 + unwind.personality_index) << 8) | size; 17511 n = 2; 17512 break; 17513 17514 default: 17515 /* Should never happen. */ 17516 abort (); 17517 } 17518 17519 /* Pack the opcodes into words (MSB first), reversing the list at the same 17520 time. */ 17521 while (unwind.opcode_count > 0) 17522 { 17523 if (n == 0) 17524 { 17525 md_number_to_chars (ptr, data, 4); 17526 ptr += 4; 17527 n = 4; 17528 data = 0; 17529 } 17530 unwind.opcode_count--; 17531 n--; 17532 data = (data << 8) | unwind.opcodes[unwind.opcode_count]; 17533 } 17534 17535 /* Finish off the last word. */ 17536 if (n < 4) 17537 { 17538 /* Pad with "finish" opcodes. */ 17539 while (n--) 17540 data = (data << 8) | 0xb0; 17541 17542 md_number_to_chars (ptr, data, 4); 17543 } 17544 17545 if (!have_data) 17546 { 17547 /* Add an empty descriptor if there is no user-specified data. */ 17548 ptr = frag_more (4); 17549 md_number_to_chars (ptr, 0, 4); 17550 } 17551 17552 return 0; 17553} 17554 17555 17556/* Initialize the DWARF-2 unwind information for this procedure. */ 17557 17558void 17559tc_arm_frame_initial_instructions (void) 17560{ 17561 cfi_add_CFA_def_cfa (REG_SP, 0); 17562} 17563#endif /* OBJ_ELF */ 17564 17565/* Convert REGNAME to a DWARF-2 register number. */ 17566 17567int 17568tc_arm_regname_to_dw2regnum (char *regname) 17569{ 17570 int reg = arm_reg_parse (®name, REG_TYPE_RN); 17571 17572 if (reg == FAIL) 17573 return -1; 17574 17575 return reg; 17576} 17577 17578#ifdef TE_PE 17579void 17580tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size) 17581{ 17582 expressionS expr; 17583 17584 expr.X_op = O_secrel; 17585 expr.X_add_symbol = symbol; 17586 expr.X_add_number = 0; 17587 emit_expr (&expr, size); 17588} 17589#endif 17590 17591/* MD interface: Symbol and relocation handling. */ 17592 17593/* Return the address within the segment that a PC-relative fixup is 17594 relative to. For ARM, PC-relative fixups applied to instructions 17595 are generally relative to the location of the fixup plus 8 bytes. 17596 Thumb branches are offset by 4, and Thumb loads relative to PC 17597 require special handling. */ 17598 17599long 17600md_pcrel_from_section (fixS * fixP, segT seg) 17601{ 17602 offsetT base = fixP->fx_where + fixP->fx_frag->fr_address; 17603 17604 /* If this is pc-relative and we are going to emit a relocation 17605 then we just want to put out any pipeline compensation that the linker 17606 will need. Otherwise we want to use the calculated base. 17607 For WinCE we skip the bias for externals as well, since this 17608 is how the MS ARM-CE assembler behaves and we want to be compatible. */ 17609 if (fixP->fx_pcrel 17610 && ((fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != seg) 17611 || (arm_force_relocation (fixP) 17612#ifdef TE_WINCE 17613 && !S_IS_EXTERNAL (fixP->fx_addsy) 17614#endif 17615 ))) 17616 base = 0; 17617 17618 switch (fixP->fx_r_type) 17619 { 17620 /* PC relative addressing on the Thumb is slightly odd as the 17621 bottom two bits of the PC are forced to zero for the 17622 calculation. This happens *after* application of the 17623 pipeline offset. However, Thumb adrl already adjusts for 17624 this, so we need not do it again. */ 17625 case BFD_RELOC_ARM_THUMB_ADD: 17626 return base & ~3; 17627 17628 case BFD_RELOC_ARM_THUMB_OFFSET: 17629 case BFD_RELOC_ARM_T32_OFFSET_IMM: 17630 case BFD_RELOC_ARM_T32_ADD_PC12: 17631 case BFD_RELOC_ARM_T32_CP_OFF_IMM: 17632 return (base + 4) & ~3; 17633 17634 /* Thumb branches are simply offset by +4. */ 17635 case BFD_RELOC_THUMB_PCREL_BRANCH7: 17636 case BFD_RELOC_THUMB_PCREL_BRANCH9: 17637 case BFD_RELOC_THUMB_PCREL_BRANCH12: 17638 case BFD_RELOC_THUMB_PCREL_BRANCH20: 17639 case BFD_RELOC_THUMB_PCREL_BRANCH23: 17640 case BFD_RELOC_THUMB_PCREL_BRANCH25: 17641 case BFD_RELOC_THUMB_PCREL_BLX: 17642 return base + 4; 17643 17644 /* ARM mode branches are offset by +8. However, the Windows CE 17645 loader expects the relocation not to take this into account. */ 17646 case BFD_RELOC_ARM_PCREL_BRANCH: 17647 case BFD_RELOC_ARM_PCREL_CALL: 17648 case BFD_RELOC_ARM_PCREL_JUMP: 17649 case BFD_RELOC_ARM_PCREL_BLX: 17650 case BFD_RELOC_ARM_PLT32: 17651#ifdef TE_WINCE 17652 /* When handling fixups immediately, because we have already 17653 discovered the value of a symbol, or the address of the frag involved 17654 we must account for the offset by +8, as the OS loader will never see the reloc. 17655 see fixup_segment() in write.c 17656 The S_IS_EXTERNAL test handles the case of global symbols. 17657 Those need the calculated base, not just the pipe compensation the linker will need. */ 17658 if (fixP->fx_pcrel 17659 && fixP->fx_addsy != NULL 17660 && (S_GET_SEGMENT (fixP->fx_addsy) == seg) 17661 && (S_IS_EXTERNAL (fixP->fx_addsy) || !arm_force_relocation (fixP))) 17662 return base + 8; 17663 return base; 17664#else 17665 return base + 8; 17666#endif 17667 17668 /* ARM mode loads relative to PC are also offset by +8. Unlike 17669 branches, the Windows CE loader *does* expect the relocation 17670 to take this into account. */ 17671 case BFD_RELOC_ARM_OFFSET_IMM: 17672 case BFD_RELOC_ARM_OFFSET_IMM8: 17673 case BFD_RELOC_ARM_HWLITERAL: 17674 case BFD_RELOC_ARM_LITERAL: 17675 case BFD_RELOC_ARM_CP_OFF_IMM: 17676 return base + 8; 17677 17678 17679 /* Other PC-relative relocations are un-offset. */ 17680 default: 17681 return base; 17682 } 17683} 17684 17685/* Under ELF we need to default _GLOBAL_OFFSET_TABLE. 17686 Otherwise we have no need to default values of symbols. */ 17687 17688symbolS * 17689md_undefined_symbol (char * name ATTRIBUTE_UNUSED) 17690{ 17691#ifdef OBJ_ELF 17692 if (name[0] == '_' && name[1] == 'G' 17693 && streq (name, GLOBAL_OFFSET_TABLE_NAME)) 17694 { 17695 if (!GOT_symbol) 17696 { 17697 if (symbol_find (name)) 17698 as_bad ("GOT already in the symbol table"); 17699 17700 GOT_symbol = symbol_new (name, undefined_section, 17701 (valueT) 0, & zero_address_frag); 17702 } 17703 17704 return GOT_symbol; 17705 } 17706#endif 17707 17708 return 0; 17709} 17710 17711/* Subroutine of md_apply_fix. Check to see if an immediate can be 17712 computed as two separate immediate values, added together. We 17713 already know that this value cannot be computed by just one ARM 17714 instruction. */ 17715 17716static unsigned int 17717validate_immediate_twopart (unsigned int val, 17718 unsigned int * highpart) 17719{ 17720 unsigned int a; 17721 unsigned int i; 17722 17723 for (i = 0; i < 32; i += 2) 17724 if (((a = rotate_left (val, i)) & 0xff) != 0) 17725 { 17726 if (a & 0xff00) 17727 { 17728 if (a & ~ 0xffff) 17729 continue; 17730 * highpart = (a >> 8) | ((i + 24) << 7); 17731 } 17732 else if (a & 0xff0000) 17733 { 17734 if (a & 0xff000000) 17735 continue; 17736 * highpart = (a >> 16) | ((i + 16) << 7); 17737 } 17738 else 17739 { 17740 assert (a & 0xff000000); 17741 * highpart = (a >> 24) | ((i + 8) << 7); 17742 } 17743 17744 return (a & 0xff) | (i << 7); 17745 } 17746 17747 return FAIL; 17748} 17749 17750static int 17751validate_offset_imm (unsigned int val, int hwse) 17752{ 17753 if ((hwse && val > 255) || val > 4095) 17754 return FAIL; 17755 return val; 17756} 17757 17758/* Subroutine of md_apply_fix. Do those data_ops which can take a 17759 negative immediate constant by altering the instruction. A bit of 17760 a hack really. 17761 MOV <-> MVN 17762 AND <-> BIC 17763 ADC <-> SBC 17764 by inverting the second operand, and 17765 ADD <-> SUB 17766 CMP <-> CMN 17767 by negating the second operand. */ 17768 17769static int 17770negate_data_op (unsigned long * instruction, 17771 unsigned long value) 17772{ 17773 int op, new_inst; 17774 unsigned long negated, inverted; 17775 17776 negated = encode_arm_immediate (-value); 17777 inverted = encode_arm_immediate (~value); 17778 17779 op = (*instruction >> DATA_OP_SHIFT) & 0xf; 17780 switch (op) 17781 { 17782 /* First negates. */ 17783 case OPCODE_SUB: /* ADD <-> SUB */ 17784 new_inst = OPCODE_ADD; 17785 value = negated; 17786 break; 17787 17788 case OPCODE_ADD: 17789 new_inst = OPCODE_SUB; 17790 value = negated; 17791 break; 17792 17793 case OPCODE_CMP: /* CMP <-> CMN */ 17794 new_inst = OPCODE_CMN; 17795 value = negated; 17796 break; 17797 17798 case OPCODE_CMN: 17799 new_inst = OPCODE_CMP; 17800 value = negated; 17801 break; 17802 17803 /* Now Inverted ops. */ 17804 case OPCODE_MOV: /* MOV <-> MVN */ 17805 new_inst = OPCODE_MVN; 17806 value = inverted; 17807 break; 17808 17809 case OPCODE_MVN: 17810 new_inst = OPCODE_MOV; 17811 value = inverted; 17812 break; 17813 17814 case OPCODE_AND: /* AND <-> BIC */ 17815 new_inst = OPCODE_BIC; 17816 value = inverted; 17817 break; 17818 17819 case OPCODE_BIC: 17820 new_inst = OPCODE_AND; 17821 value = inverted; 17822 break; 17823 17824 case OPCODE_ADC: /* ADC <-> SBC */ 17825 new_inst = OPCODE_SBC; 17826 value = inverted; 17827 break; 17828 17829 case OPCODE_SBC: 17830 new_inst = OPCODE_ADC; 17831 value = inverted; 17832 break; 17833 17834 /* We cannot do anything. */ 17835 default: 17836 return FAIL; 17837 } 17838 17839 if (value == (unsigned) FAIL) 17840 return FAIL; 17841 17842 *instruction &= OPCODE_MASK; 17843 *instruction |= new_inst << DATA_OP_SHIFT; 17844 return value; 17845} 17846 17847/* Like negate_data_op, but for Thumb-2. */ 17848 17849static unsigned int 17850thumb32_negate_data_op (offsetT *instruction, unsigned int value) 17851{ 17852 int op, new_inst; 17853 int rd; 17854 unsigned int negated, inverted; 17855 17856 negated = encode_thumb32_immediate (-value); 17857 inverted = encode_thumb32_immediate (~value); 17858 17859 rd = (*instruction >> 8) & 0xf; 17860 op = (*instruction >> T2_DATA_OP_SHIFT) & 0xf; 17861 switch (op) 17862 { 17863 /* ADD <-> SUB. Includes CMP <-> CMN. */ 17864 case T2_OPCODE_SUB: 17865 new_inst = T2_OPCODE_ADD; 17866 value = negated; 17867 break; 17868 17869 case T2_OPCODE_ADD: 17870 new_inst = T2_OPCODE_SUB; 17871 value = negated; 17872 break; 17873 17874 /* ORR <-> ORN. Includes MOV <-> MVN. */ 17875 case T2_OPCODE_ORR: 17876 new_inst = T2_OPCODE_ORN; 17877 value = inverted; 17878 break; 17879 17880 case T2_OPCODE_ORN: 17881 new_inst = T2_OPCODE_ORR; 17882 value = inverted; 17883 break; 17884 17885 /* AND <-> BIC. TST has no inverted equivalent. */ 17886 case T2_OPCODE_AND: 17887 new_inst = T2_OPCODE_BIC; 17888 if (rd == 15) 17889 value = FAIL; 17890 else 17891 value = inverted; 17892 break; 17893 17894 case T2_OPCODE_BIC: 17895 new_inst = T2_OPCODE_AND; 17896 value = inverted; 17897 break; 17898 17899 /* ADC <-> SBC */ 17900 case T2_OPCODE_ADC: 17901 new_inst = T2_OPCODE_SBC; 17902 value = inverted; 17903 break; 17904 17905 case T2_OPCODE_SBC: 17906 new_inst = T2_OPCODE_ADC; 17907 value = inverted; 17908 break; 17909 17910 /* We cannot do anything. */ 17911 default: 17912 return FAIL; 17913 } 17914 17915 if (value == (unsigned int)FAIL) 17916 return FAIL; 17917 17918 *instruction &= T2_OPCODE_MASK; 17919 *instruction |= new_inst << T2_DATA_OP_SHIFT; 17920 return value; 17921} 17922 17923/* Read a 32-bit thumb instruction from buf. */ 17924static unsigned long 17925get_thumb32_insn (char * buf) 17926{ 17927 unsigned long insn; 17928 insn = md_chars_to_number (buf, THUMB_SIZE) << 16; 17929 insn |= md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE); 17930 17931 return insn; 17932} 17933 17934 17935/* We usually want to set the low bit on the address of thumb function 17936 symbols. In particular .word foo - . should have the low bit set. 17937 Generic code tries to fold the difference of two symbols to 17938 a constant. Prevent this and force a relocation when the first symbols 17939 is a thumb function. */ 17940int 17941arm_optimize_expr (expressionS *l, operatorT op, expressionS *r) 17942{ 17943 if (op == O_subtract 17944 && l->X_op == O_symbol 17945 && r->X_op == O_symbol 17946 && THUMB_IS_FUNC (l->X_add_symbol)) 17947 { 17948 l->X_op = O_subtract; 17949 l->X_op_symbol = r->X_add_symbol; 17950 l->X_add_number -= r->X_add_number; 17951 return 1; 17952 } 17953 /* Process as normal. */ 17954 return 0; 17955} 17956 17957void 17958md_apply_fix (fixS * fixP, 17959 valueT * valP, 17960 segT seg) 17961{ 17962 offsetT value = * valP; 17963 offsetT newval; 17964 unsigned int newimm; 17965 unsigned long temp; 17966 int sign; 17967 char * buf = fixP->fx_where + fixP->fx_frag->fr_literal; 17968 17969 assert (fixP->fx_r_type <= BFD_RELOC_UNUSED); 17970 17971 /* Note whether this will delete the relocation. */ 17972 17973 if (fixP->fx_addsy == 0 && !fixP->fx_pcrel) 17974 fixP->fx_done = 1; 17975 17976 /* On a 64-bit host, silently truncate 'value' to 32 bits for 17977 consistency with the behavior on 32-bit hosts. Remember value 17978 for emit_reloc. */ 17979 value &= 0xffffffff; 17980 value ^= 0x80000000; 17981 value -= 0x80000000; 17982 17983 *valP = value; 17984 fixP->fx_addnumber = value; 17985 17986 /* Same treatment for fixP->fx_offset. */ 17987 fixP->fx_offset &= 0xffffffff; 17988 fixP->fx_offset ^= 0x80000000; 17989 fixP->fx_offset -= 0x80000000; 17990 17991 switch (fixP->fx_r_type) 17992 { 17993 case BFD_RELOC_NONE: 17994 /* This will need to go in the object file. */ 17995 fixP->fx_done = 0; 17996 break; 17997 17998 case BFD_RELOC_ARM_IMMEDIATE: 17999 /* We claim that this fixup has been processed here, 18000 even if in fact we generate an error because we do 18001 not have a reloc for it, so tc_gen_reloc will reject it. */ 18002 fixP->fx_done = 1; 18003 18004 if (fixP->fx_addsy 18005 && ! S_IS_DEFINED (fixP->fx_addsy)) 18006 { 18007 as_bad_where (fixP->fx_file, fixP->fx_line, 18008 _("undefined symbol %s used as an immediate value"), 18009 S_GET_NAME (fixP->fx_addsy)); 18010 break; 18011 } 18012 18013 newimm = encode_arm_immediate (value); 18014 temp = md_chars_to_number (buf, INSN_SIZE); 18015 18016 /* If the instruction will fail, see if we can fix things up by 18017 changing the opcode. */ 18018 if (newimm == (unsigned int) FAIL 18019 && (newimm = negate_data_op (&temp, value)) == (unsigned int) FAIL) 18020 { 18021 as_bad_where (fixP->fx_file, fixP->fx_line, 18022 _("invalid constant (%lx) after fixup"), 18023 (unsigned long) value); 18024 break; 18025 } 18026 18027 newimm |= (temp & 0xfffff000); 18028 md_number_to_chars (buf, (valueT) newimm, INSN_SIZE); 18029 break; 18030 18031 case BFD_RELOC_ARM_ADRL_IMMEDIATE: 18032 { 18033 unsigned int highpart = 0; 18034 unsigned int newinsn = 0xe1a00000; /* nop. */ 18035 18036 newimm = encode_arm_immediate (value); 18037 temp = md_chars_to_number (buf, INSN_SIZE); 18038 18039 /* If the instruction will fail, see if we can fix things up by 18040 changing the opcode. */ 18041 if (newimm == (unsigned int) FAIL 18042 && (newimm = negate_data_op (& temp, value)) == (unsigned int) FAIL) 18043 { 18044 /* No ? OK - try using two ADD instructions to generate 18045 the value. */ 18046 newimm = validate_immediate_twopart (value, & highpart); 18047 18048 /* Yes - then make sure that the second instruction is 18049 also an add. */ 18050 if (newimm != (unsigned int) FAIL) 18051 newinsn = temp; 18052 /* Still No ? Try using a negated value. */ 18053 else if ((newimm = validate_immediate_twopart (- value, & highpart)) != (unsigned int) FAIL) 18054 temp = newinsn = (temp & OPCODE_MASK) | OPCODE_SUB << DATA_OP_SHIFT; 18055 /* Otherwise - give up. */ 18056 else 18057 { 18058 as_bad_where (fixP->fx_file, fixP->fx_line, 18059 _("unable to compute ADRL instructions for PC offset of 0x%lx"), 18060 (long) value); 18061 break; 18062 } 18063 18064 /* Replace the first operand in the 2nd instruction (which 18065 is the PC) with the destination register. We have 18066 already added in the PC in the first instruction and we 18067 do not want to do it again. */ 18068 newinsn &= ~ 0xf0000; 18069 newinsn |= ((newinsn & 0x0f000) << 4); 18070 } 18071 18072 newimm |= (temp & 0xfffff000); 18073 md_number_to_chars (buf, (valueT) newimm, INSN_SIZE); 18074 18075 highpart |= (newinsn & 0xfffff000); 18076 md_number_to_chars (buf + INSN_SIZE, (valueT) highpart, INSN_SIZE); 18077 } 18078 break; 18079 18080 case BFD_RELOC_ARM_OFFSET_IMM: 18081 if (!fixP->fx_done && seg->use_rela_p) 18082 value = 0; 18083 18084 case BFD_RELOC_ARM_LITERAL: 18085 sign = value >= 0; 18086 18087 if (value < 0) 18088 value = - value; 18089 18090 if (validate_offset_imm (value, 0) == FAIL) 18091 { 18092 if (fixP->fx_r_type == BFD_RELOC_ARM_LITERAL) 18093 as_bad_where (fixP->fx_file, fixP->fx_line, 18094 _("invalid literal constant: pool needs to be closer")); 18095 else 18096 as_bad_where (fixP->fx_file, fixP->fx_line, 18097 _("bad immediate value for offset (%ld)"), 18098 (long) value); 18099 break; 18100 } 18101 18102 newval = md_chars_to_number (buf, INSN_SIZE); 18103 newval &= 0xff7ff000; 18104 newval |= value | (sign ? INDEX_UP : 0); 18105 md_number_to_chars (buf, newval, INSN_SIZE); 18106 break; 18107 18108 case BFD_RELOC_ARM_OFFSET_IMM8: 18109 case BFD_RELOC_ARM_HWLITERAL: 18110 sign = value >= 0; 18111 18112 if (value < 0) 18113 value = - value; 18114 18115 if (validate_offset_imm (value, 1) == FAIL) 18116 { 18117 if (fixP->fx_r_type == BFD_RELOC_ARM_HWLITERAL) 18118 as_bad_where (fixP->fx_file, fixP->fx_line, 18119 _("invalid literal constant: pool needs to be closer")); 18120 else 18121 as_bad (_("bad immediate value for 8-bit offset (%ld)"), 18122 (long) value); 18123 break; 18124 } 18125 18126 newval = md_chars_to_number (buf, INSN_SIZE); 18127 newval &= 0xff7ff0f0; 18128 newval |= ((value >> 4) << 8) | (value & 0xf) | (sign ? INDEX_UP : 0); 18129 md_number_to_chars (buf, newval, INSN_SIZE); 18130 break; 18131 18132 case BFD_RELOC_ARM_T32_OFFSET_U8: 18133 if (value < 0 || value > 1020 || value % 4 != 0) 18134 as_bad_where (fixP->fx_file, fixP->fx_line, 18135 _("bad immediate value for offset (%ld)"), (long) value); 18136 value /= 4; 18137 18138 newval = md_chars_to_number (buf+2, THUMB_SIZE); 18139 newval |= value; 18140 md_number_to_chars (buf+2, newval, THUMB_SIZE); 18141 break; 18142 18143 case BFD_RELOC_ARM_T32_OFFSET_IMM: 18144 /* This is a complicated relocation used for all varieties of Thumb32 18145 load/store instruction with immediate offset: 18146 18147 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit, 18148 *4, optional writeback(W) 18149 (doubleword load/store) 18150 18151 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel 18152 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit 18153 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction) 18154 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit 18155 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit 18156 18157 Uppercase letters indicate bits that are already encoded at 18158 this point. Lowercase letters are our problem. For the 18159 second block of instructions, the secondary opcode nybble 18160 (bits 8..11) is present, and bit 23 is zero, even if this is 18161 a PC-relative operation. */ 18162 newval = md_chars_to_number (buf, THUMB_SIZE); 18163 newval <<= 16; 18164 newval |= md_chars_to_number (buf+THUMB_SIZE, THUMB_SIZE); 18165 18166 if ((newval & 0xf0000000) == 0xe0000000) 18167 { 18168 /* Doubleword load/store: 8-bit offset, scaled by 4. */ 18169 if (value >= 0) 18170 newval |= (1 << 23); 18171 else 18172 value = -value; 18173 if (value % 4 != 0) 18174 { 18175 as_bad_where (fixP->fx_file, fixP->fx_line, 18176 _("offset not a multiple of 4")); 18177 break; 18178 } 18179 value /= 4; 18180 if (value > 0xff) 18181 { 18182 as_bad_where (fixP->fx_file, fixP->fx_line, 18183 _("offset out of range")); 18184 break; 18185 } 18186 newval &= ~0xff; 18187 } 18188 else if ((newval & 0x000f0000) == 0x000f0000) 18189 { 18190 /* PC-relative, 12-bit offset. */ 18191 if (value >= 0) 18192 newval |= (1 << 23); 18193 else 18194 value = -value; 18195 if (value > 0xfff) 18196 { 18197 as_bad_where (fixP->fx_file, fixP->fx_line, 18198 _("offset out of range")); 18199 break; 18200 } 18201 newval &= ~0xfff; 18202 } 18203 else if ((newval & 0x00000100) == 0x00000100) 18204 { 18205 /* Writeback: 8-bit, +/- offset. */ 18206 if (value >= 0) 18207 newval |= (1 << 9); 18208 else 18209 value = -value; 18210 if (value > 0xff) 18211 { 18212 as_bad_where (fixP->fx_file, fixP->fx_line, 18213 _("offset out of range")); 18214 break; 18215 } 18216 newval &= ~0xff; 18217 } 18218 else if ((newval & 0x00000f00) == 0x00000e00) 18219 { 18220 /* T-instruction: positive 8-bit offset. */ 18221 if (value < 0 || value > 0xff) 18222 { 18223 as_bad_where (fixP->fx_file, fixP->fx_line, 18224 _("offset out of range")); 18225 break; 18226 } 18227 newval &= ~0xff; 18228 newval |= value; 18229 } 18230 else 18231 { 18232 /* Positive 12-bit or negative 8-bit offset. */ 18233 int limit; 18234 if (value >= 0) 18235 { 18236 newval |= (1 << 23); 18237 limit = 0xfff; 18238 } 18239 else 18240 { 18241 value = -value; 18242 limit = 0xff; 18243 } 18244 if (value > limit) 18245 { 18246 as_bad_where (fixP->fx_file, fixP->fx_line, 18247 _("offset out of range")); 18248 break; 18249 } 18250 newval &= ~limit; 18251 } 18252 18253 newval |= value; 18254 md_number_to_chars (buf, (newval >> 16) & 0xffff, THUMB_SIZE); 18255 md_number_to_chars (buf + THUMB_SIZE, newval & 0xffff, THUMB_SIZE); 18256 break; 18257 18258 case BFD_RELOC_ARM_SHIFT_IMM: 18259 newval = md_chars_to_number (buf, INSN_SIZE); 18260 if (((unsigned long) value) > 32 18261 || (value == 32 18262 && (((newval & 0x60) == 0) || (newval & 0x60) == 0x60))) 18263 { 18264 as_bad_where (fixP->fx_file, fixP->fx_line, 18265 _("shift expression is too large")); 18266 break; 18267 } 18268 18269 if (value == 0) 18270 /* Shifts of zero must be done as lsl. */ 18271 newval &= ~0x60; 18272 else if (value == 32) 18273 value = 0; 18274 newval &= 0xfffff07f; 18275 newval |= (value & 0x1f) << 7; 18276 md_number_to_chars (buf, newval, INSN_SIZE); 18277 break; 18278 18279 case BFD_RELOC_ARM_T32_IMMEDIATE: 18280 case BFD_RELOC_ARM_T32_ADD_IMM: 18281 case BFD_RELOC_ARM_T32_IMM12: 18282 case BFD_RELOC_ARM_T32_ADD_PC12: 18283 /* We claim that this fixup has been processed here, 18284 even if in fact we generate an error because we do 18285 not have a reloc for it, so tc_gen_reloc will reject it. */ 18286 fixP->fx_done = 1; 18287 18288 if (fixP->fx_addsy 18289 && ! S_IS_DEFINED (fixP->fx_addsy)) 18290 { 18291 as_bad_where (fixP->fx_file, fixP->fx_line, 18292 _("undefined symbol %s used as an immediate value"), 18293 S_GET_NAME (fixP->fx_addsy)); 18294 break; 18295 } 18296 18297 newval = md_chars_to_number (buf, THUMB_SIZE); 18298 newval <<= 16; 18299 newval |= md_chars_to_number (buf+2, THUMB_SIZE); 18300 18301 newimm = FAIL; 18302 if (fixP->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE 18303 || fixP->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM) 18304 { 18305 newimm = encode_thumb32_immediate (value); 18306 if (newimm == (unsigned int) FAIL) 18307 newimm = thumb32_negate_data_op (&newval, value); 18308 } 18309 if (fixP->fx_r_type != BFD_RELOC_ARM_T32_IMMEDIATE 18310 && newimm == (unsigned int) FAIL) 18311 { 18312 /* Turn add/sum into addw/subw. */ 18313 if (fixP->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM) 18314 newval = (newval & 0xfeffffff) | 0x02000000; 18315 18316 /* 12 bit immediate for addw/subw. */ 18317 if (value < 0) 18318 { 18319 value = -value; 18320 newval ^= 0x00a00000; 18321 } 18322 if (value > 0xfff) 18323 newimm = (unsigned int) FAIL; 18324 else 18325 newimm = value; 18326 } 18327 18328 if (newimm == (unsigned int)FAIL) 18329 { 18330 as_bad_where (fixP->fx_file, fixP->fx_line, 18331 _("invalid constant (%lx) after fixup"), 18332 (unsigned long) value); 18333 break; 18334 } 18335 18336 newval |= (newimm & 0x800) << 15; 18337 newval |= (newimm & 0x700) << 4; 18338 newval |= (newimm & 0x0ff); 18339 18340 md_number_to_chars (buf, (valueT) ((newval >> 16) & 0xffff), THUMB_SIZE); 18341 md_number_to_chars (buf+2, (valueT) (newval & 0xffff), THUMB_SIZE); 18342 break; 18343 18344 case BFD_RELOC_ARM_SMC: 18345 if (((unsigned long) value) > 0xffff) 18346 as_bad_where (fixP->fx_file, fixP->fx_line, 18347 _("invalid smc expression")); 18348 newval = md_chars_to_number (buf, INSN_SIZE); 18349 newval |= (value & 0xf) | ((value & 0xfff0) << 4); 18350 md_number_to_chars (buf, newval, INSN_SIZE); 18351 break; 18352 18353 case BFD_RELOC_ARM_SWI: 18354 if (fixP->tc_fix_data != 0) 18355 { 18356 if (((unsigned long) value) > 0xff) 18357 as_bad_where (fixP->fx_file, fixP->fx_line, 18358 _("invalid swi expression")); 18359 newval = md_chars_to_number (buf, THUMB_SIZE); 18360 newval |= value; 18361 md_number_to_chars (buf, newval, THUMB_SIZE); 18362 } 18363 else 18364 { 18365 if (((unsigned long) value) > 0x00ffffff) 18366 as_bad_where (fixP->fx_file, fixP->fx_line, 18367 _("invalid swi expression")); 18368 newval = md_chars_to_number (buf, INSN_SIZE); 18369 newval |= value; 18370 md_number_to_chars (buf, newval, INSN_SIZE); 18371 } 18372 break; 18373 18374 case BFD_RELOC_ARM_MULTI: 18375 if (((unsigned long) value) > 0xffff) 18376 as_bad_where (fixP->fx_file, fixP->fx_line, 18377 _("invalid expression in load/store multiple")); 18378 newval = value | md_chars_to_number (buf, INSN_SIZE); 18379 md_number_to_chars (buf, newval, INSN_SIZE); 18380 break; 18381 18382#ifdef OBJ_ELF 18383 case BFD_RELOC_ARM_PCREL_CALL: 18384 newval = md_chars_to_number (buf, INSN_SIZE); 18385 if ((newval & 0xf0000000) == 0xf0000000) 18386 temp = 1; 18387 else 18388 temp = 3; 18389 goto arm_branch_common; 18390 18391 case BFD_RELOC_ARM_PCREL_JUMP: 18392 case BFD_RELOC_ARM_PLT32: 18393#endif 18394 case BFD_RELOC_ARM_PCREL_BRANCH: 18395 temp = 3; 18396 goto arm_branch_common; 18397 18398 case BFD_RELOC_ARM_PCREL_BLX: 18399 temp = 1; 18400 arm_branch_common: 18401 /* We are going to store value (shifted right by two) in the 18402 instruction, in a 24 bit, signed field. Bits 26 through 32 either 18403 all clear or all set and bit 0 must be clear. For B/BL bit 1 must 18404 also be be clear. */ 18405 if (value & temp) 18406 as_bad_where (fixP->fx_file, fixP->fx_line, 18407 _("misaligned branch destination")); 18408 if ((value & (offsetT)0xfe000000) != (offsetT)0 18409 && (value & (offsetT)0xfe000000) != (offsetT)0xfe000000) 18410 as_bad_where (fixP->fx_file, fixP->fx_line, 18411 _("branch out of range")); 18412 18413 if (fixP->fx_done || !seg->use_rela_p) 18414 { 18415 newval = md_chars_to_number (buf, INSN_SIZE); 18416 newval |= (value >> 2) & 0x00ffffff; 18417 /* Set the H bit on BLX instructions. */ 18418 if (temp == 1) 18419 { 18420 if (value & 2) 18421 newval |= 0x01000000; 18422 else 18423 newval &= ~0x01000000; 18424 } 18425 md_number_to_chars (buf, newval, INSN_SIZE); 18426 } 18427 break; 18428 18429 case BFD_RELOC_THUMB_PCREL_BRANCH7: /* CBZ */ 18430 /* CBZ can only branch forward. */ 18431 18432 /* Attempts to use CBZ to branch to the next instruction 18433 (which, strictly speaking, are prohibited) will be turned into 18434 no-ops. 18435 18436 FIXME: It may be better to remove the instruction completely and 18437 perform relaxation. */ 18438 if (value == -2) 18439 { 18440 newval = md_chars_to_number (buf, THUMB_SIZE); 18441 newval = 0xbf00; /* NOP encoding T1 */ 18442 md_number_to_chars (buf, newval, THUMB_SIZE); 18443 } 18444 else 18445 { 18446 if (value & ~0x7e) 18447 as_bad_where (fixP->fx_file, fixP->fx_line, 18448 _("branch out of range")); 18449 18450 if (fixP->fx_done || !seg->use_rela_p) 18451 { 18452 newval = md_chars_to_number (buf, THUMB_SIZE); 18453 newval |= ((value & 0x3e) << 2) | ((value & 0x40) << 3); 18454 md_number_to_chars (buf, newval, THUMB_SIZE); 18455 } 18456 } 18457 break; 18458 18459 case BFD_RELOC_THUMB_PCREL_BRANCH9: /* Conditional branch. */ 18460 if ((value & ~0xff) && ((value & ~0xff) != ~0xff)) 18461 as_bad_where (fixP->fx_file, fixP->fx_line, 18462 _("branch out of range")); 18463 18464 if (fixP->fx_done || !seg->use_rela_p) 18465 { 18466 newval = md_chars_to_number (buf, THUMB_SIZE); 18467 newval |= (value & 0x1ff) >> 1; 18468 md_number_to_chars (buf, newval, THUMB_SIZE); 18469 } 18470 break; 18471 18472 case BFD_RELOC_THUMB_PCREL_BRANCH12: /* Unconditional branch. */ 18473 if ((value & ~0x7ff) && ((value & ~0x7ff) != ~0x7ff)) 18474 as_bad_where (fixP->fx_file, fixP->fx_line, 18475 _("branch out of range")); 18476 18477 if (fixP->fx_done || !seg->use_rela_p) 18478 { 18479 newval = md_chars_to_number (buf, THUMB_SIZE); 18480 newval |= (value & 0xfff) >> 1; 18481 md_number_to_chars (buf, newval, THUMB_SIZE); 18482 } 18483 break; 18484 18485 case BFD_RELOC_THUMB_PCREL_BRANCH20: 18486 if ((value & ~0x1fffff) && ((value & ~0x1fffff) != ~0x1fffff)) 18487 as_bad_where (fixP->fx_file, fixP->fx_line, 18488 _("conditional branch out of range")); 18489 18490 if (fixP->fx_done || !seg->use_rela_p) 18491 { 18492 offsetT newval2; 18493 addressT S, J1, J2, lo, hi; 18494 18495 S = (value & 0x00100000) >> 20; 18496 J2 = (value & 0x00080000) >> 19; 18497 J1 = (value & 0x00040000) >> 18; 18498 hi = (value & 0x0003f000) >> 12; 18499 lo = (value & 0x00000ffe) >> 1; 18500 18501 newval = md_chars_to_number (buf, THUMB_SIZE); 18502 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE); 18503 newval |= (S << 10) | hi; 18504 newval2 |= (J1 << 13) | (J2 << 11) | lo; 18505 md_number_to_chars (buf, newval, THUMB_SIZE); 18506 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE); 18507 } 18508 break; 18509 18510 case BFD_RELOC_THUMB_PCREL_BLX: 18511 case BFD_RELOC_THUMB_PCREL_BRANCH23: 18512 if ((value & ~0x3fffff) && ((value & ~0x3fffff) != ~0x3fffff)) 18513 as_bad_where (fixP->fx_file, fixP->fx_line, 18514 _("branch out of range")); 18515 18516 if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX) 18517 /* For a BLX instruction, make sure that the relocation is rounded up 18518 to a word boundary. This follows the semantics of the instruction 18519 which specifies that bit 1 of the target address will come from bit 18520 1 of the base address. */ 18521 value = (value + 1) & ~ 1; 18522 18523 if (fixP->fx_done || !seg->use_rela_p) 18524 { 18525 offsetT newval2; 18526 18527 newval = md_chars_to_number (buf, THUMB_SIZE); 18528 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE); 18529 newval |= (value & 0x7fffff) >> 12; 18530 newval2 |= (value & 0xfff) >> 1; 18531 md_number_to_chars (buf, newval, THUMB_SIZE); 18532 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE); 18533 } 18534 break; 18535 18536 case BFD_RELOC_THUMB_PCREL_BRANCH25: 18537 if ((value & ~0x1ffffff) && ((value & ~0x1ffffff) != ~0x1ffffff)) 18538 as_bad_where (fixP->fx_file, fixP->fx_line, 18539 _("branch out of range")); 18540 18541 if (fixP->fx_done || !seg->use_rela_p) 18542 { 18543 offsetT newval2; 18544 addressT S, I1, I2, lo, hi; 18545 18546 S = (value & 0x01000000) >> 24; 18547 I1 = (value & 0x00800000) >> 23; 18548 I2 = (value & 0x00400000) >> 22; 18549 hi = (value & 0x003ff000) >> 12; 18550 lo = (value & 0x00000ffe) >> 1; 18551 18552 I1 = !(I1 ^ S); 18553 I2 = !(I2 ^ S); 18554 18555 newval = md_chars_to_number (buf, THUMB_SIZE); 18556 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE); 18557 newval |= (S << 10) | hi; 18558 newval2 |= (I1 << 13) | (I2 << 11) | lo; 18559 md_number_to_chars (buf, newval, THUMB_SIZE); 18560 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE); 18561 } 18562 break; 18563 18564 case BFD_RELOC_8: 18565 if (fixP->fx_done || !seg->use_rela_p) 18566 md_number_to_chars (buf, value, 1); 18567 break; 18568 18569 case BFD_RELOC_16: 18570 if (fixP->fx_done || !seg->use_rela_p) 18571 md_number_to_chars (buf, value, 2); 18572 break; 18573 18574#ifdef OBJ_ELF 18575 case BFD_RELOC_ARM_TLS_GD32: 18576 case BFD_RELOC_ARM_TLS_LE32: 18577 case BFD_RELOC_ARM_TLS_IE32: 18578 case BFD_RELOC_ARM_TLS_LDM32: 18579 case BFD_RELOC_ARM_TLS_LDO32: 18580 S_SET_THREAD_LOCAL (fixP->fx_addsy); 18581 /* fall through */ 18582 18583 case BFD_RELOC_ARM_GOT32: 18584 case BFD_RELOC_ARM_GOTOFF: 18585 case BFD_RELOC_ARM_TARGET2: 18586 if (fixP->fx_done || !seg->use_rela_p) 18587 md_number_to_chars (buf, 0, 4); 18588 break; 18589#endif 18590 18591 case BFD_RELOC_RVA: 18592 case BFD_RELOC_32: 18593 case BFD_RELOC_ARM_TARGET1: 18594 case BFD_RELOC_ARM_ROSEGREL32: 18595 case BFD_RELOC_ARM_SBREL32: 18596 case BFD_RELOC_32_PCREL: 18597#ifdef TE_PE 18598 case BFD_RELOC_32_SECREL: 18599#endif 18600 if (fixP->fx_done || !seg->use_rela_p) 18601#ifdef TE_WINCE 18602 /* For WinCE we only do this for pcrel fixups. */ 18603 if (fixP->fx_done || fixP->fx_pcrel) 18604#endif 18605 md_number_to_chars (buf, value, 4); 18606 break; 18607 18608#ifdef OBJ_ELF 18609 case BFD_RELOC_ARM_PREL31: 18610 if (fixP->fx_done || !seg->use_rela_p) 18611 { 18612 newval = md_chars_to_number (buf, 4) & 0x80000000; 18613 if ((value ^ (value >> 1)) & 0x40000000) 18614 { 18615 as_bad_where (fixP->fx_file, fixP->fx_line, 18616 _("rel31 relocation overflow")); 18617 } 18618 newval |= value & 0x7fffffff; 18619 md_number_to_chars (buf, newval, 4); 18620 } 18621 break; 18622#endif 18623 18624 case BFD_RELOC_ARM_CP_OFF_IMM: 18625 case BFD_RELOC_ARM_T32_CP_OFF_IMM: 18626 if (value < -1023 || value > 1023 || (value & 3)) 18627 as_bad_where (fixP->fx_file, fixP->fx_line, 18628 _("co-processor offset out of range")); 18629 cp_off_common: 18630 sign = value >= 0; 18631 if (value < 0) 18632 value = -value; 18633 if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM 18634 || fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2) 18635 newval = md_chars_to_number (buf, INSN_SIZE); 18636 else 18637 newval = get_thumb32_insn (buf); 18638 newval &= 0xff7fff00; 18639 newval |= (value >> 2) | (sign ? INDEX_UP : 0); 18640 if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM 18641 || fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2) 18642 md_number_to_chars (buf, newval, INSN_SIZE); 18643 else 18644 put_thumb32_insn (buf, newval); 18645 break; 18646 18647 case BFD_RELOC_ARM_CP_OFF_IMM_S2: 18648 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2: 18649 if (value < -255 || value > 255) 18650 as_bad_where (fixP->fx_file, fixP->fx_line, 18651 _("co-processor offset out of range")); 18652 value *= 4; 18653 goto cp_off_common; 18654 18655 case BFD_RELOC_ARM_THUMB_OFFSET: 18656 newval = md_chars_to_number (buf, THUMB_SIZE); 18657 /* Exactly what ranges, and where the offset is inserted depends 18658 on the type of instruction, we can establish this from the 18659 top 4 bits. */ 18660 switch (newval >> 12) 18661 { 18662 case 4: /* PC load. */ 18663 /* Thumb PC loads are somewhat odd, bit 1 of the PC is 18664 forced to zero for these loads; md_pcrel_from has already 18665 compensated for this. */ 18666 if (value & 3) 18667 as_bad_where (fixP->fx_file, fixP->fx_line, 18668 _("invalid offset, target not word aligned (0x%08lX)"), 18669 (((unsigned long) fixP->fx_frag->fr_address 18670 + (unsigned long) fixP->fx_where) & ~3) 18671 + (unsigned long) value); 18672 18673 if (value & ~0x3fc) 18674 as_bad_where (fixP->fx_file, fixP->fx_line, 18675 _("invalid offset, value too big (0x%08lX)"), 18676 (long) value); 18677 18678 newval |= value >> 2; 18679 break; 18680 18681 case 9: /* SP load/store. */ 18682 if (value & ~0x3fc) 18683 as_bad_where (fixP->fx_file, fixP->fx_line, 18684 _("invalid offset, value too big (0x%08lX)"), 18685 (long) value); 18686 newval |= value >> 2; 18687 break; 18688 18689 case 6: /* Word load/store. */ 18690 if (value & ~0x7c) 18691 as_bad_where (fixP->fx_file, fixP->fx_line, 18692 _("invalid offset, value too big (0x%08lX)"), 18693 (long) value); 18694 newval |= value << 4; /* 6 - 2. */ 18695 break; 18696 18697 case 7: /* Byte load/store. */ 18698 if (value & ~0x1f) 18699 as_bad_where (fixP->fx_file, fixP->fx_line, 18700 _("invalid offset, value too big (0x%08lX)"), 18701 (long) value); 18702 newval |= value << 6; 18703 break; 18704 18705 case 8: /* Halfword load/store. */ 18706 if (value & ~0x3e) 18707 as_bad_where (fixP->fx_file, fixP->fx_line, 18708 _("invalid offset, value too big (0x%08lX)"), 18709 (long) value); 18710 newval |= value << 5; /* 6 - 1. */ 18711 break; 18712 18713 default: 18714 as_bad_where (fixP->fx_file, fixP->fx_line, 18715 "Unable to process relocation for thumb opcode: %lx", 18716 (unsigned long) newval); 18717 break; 18718 } 18719 md_number_to_chars (buf, newval, THUMB_SIZE); 18720 break; 18721 18722 case BFD_RELOC_ARM_THUMB_ADD: 18723 /* This is a complicated relocation, since we use it for all of 18724 the following immediate relocations: 18725 18726 3bit ADD/SUB 18727 8bit ADD/SUB 18728 9bit ADD/SUB SP word-aligned 18729 10bit ADD PC/SP word-aligned 18730 18731 The type of instruction being processed is encoded in the 18732 instruction field: 18733 18734 0x8000 SUB 18735 0x00F0 Rd 18736 0x000F Rs 18737 */ 18738 newval = md_chars_to_number (buf, THUMB_SIZE); 18739 { 18740 int rd = (newval >> 4) & 0xf; 18741 int rs = newval & 0xf; 18742 int subtract = !!(newval & 0x8000); 18743 18744 /* Check for HI regs, only very restricted cases allowed: 18745 Adjusting SP, and using PC or SP to get an address. */ 18746 if ((rd > 7 && (rd != REG_SP || rs != REG_SP)) 18747 || (rs > 7 && rs != REG_SP && rs != REG_PC)) 18748 as_bad_where (fixP->fx_file, fixP->fx_line, 18749 _("invalid Hi register with immediate")); 18750 18751 /* If value is negative, choose the opposite instruction. */ 18752 if (value < 0) 18753 { 18754 value = -value; 18755 subtract = !subtract; 18756 if (value < 0) 18757 as_bad_where (fixP->fx_file, fixP->fx_line, 18758 _("immediate value out of range")); 18759 } 18760 18761 if (rd == REG_SP) 18762 { 18763 if (value & ~0x1fc) 18764 as_bad_where (fixP->fx_file, fixP->fx_line, 18765 _("invalid immediate for stack address calculation")); 18766 newval = subtract ? T_OPCODE_SUB_ST : T_OPCODE_ADD_ST; 18767 newval |= value >> 2; 18768 } 18769 else if (rs == REG_PC || rs == REG_SP) 18770 { 18771 if (subtract || value & ~0x3fc) 18772 as_bad_where (fixP->fx_file, fixP->fx_line, 18773 _("invalid immediate for address calculation (value = 0x%08lX)"), 18774 (unsigned long) value); 18775 newval = (rs == REG_PC ? T_OPCODE_ADD_PC : T_OPCODE_ADD_SP); 18776 newval |= rd << 8; 18777 newval |= value >> 2; 18778 } 18779 else if (rs == rd) 18780 { 18781 if (value & ~0xff) 18782 as_bad_where (fixP->fx_file, fixP->fx_line, 18783 _("immediate value out of range")); 18784 newval = subtract ? T_OPCODE_SUB_I8 : T_OPCODE_ADD_I8; 18785 newval |= (rd << 8) | value; 18786 } 18787 else 18788 { 18789 if (value & ~0x7) 18790 as_bad_where (fixP->fx_file, fixP->fx_line, 18791 _("immediate value out of range")); 18792 newval = subtract ? T_OPCODE_SUB_I3 : T_OPCODE_ADD_I3; 18793 newval |= rd | (rs << 3) | (value << 6); 18794 } 18795 } 18796 md_number_to_chars (buf, newval, THUMB_SIZE); 18797 break; 18798 18799 case BFD_RELOC_ARM_THUMB_IMM: 18800 newval = md_chars_to_number (buf, THUMB_SIZE); 18801 if (value < 0 || value > 255) 18802 as_bad_where (fixP->fx_file, fixP->fx_line, 18803 _("invalid immediate: %ld is too large"), 18804 (long) value); 18805 newval |= value; 18806 md_number_to_chars (buf, newval, THUMB_SIZE); 18807 break; 18808 18809 case BFD_RELOC_ARM_THUMB_SHIFT: 18810 /* 5bit shift value (0..32). LSL cannot take 32. */ 18811 newval = md_chars_to_number (buf, THUMB_SIZE) & 0xf83f; 18812 temp = newval & 0xf800; 18813 if (value < 0 || value > 32 || (value == 32 && temp == T_OPCODE_LSL_I)) 18814 as_bad_where (fixP->fx_file, fixP->fx_line, 18815 _("invalid shift value: %ld"), (long) value); 18816 /* Shifts of zero must be encoded as LSL. */ 18817 if (value == 0) 18818 newval = (newval & 0x003f) | T_OPCODE_LSL_I; 18819 /* Shifts of 32 are encoded as zero. */ 18820 else if (value == 32) 18821 value = 0; 18822 newval |= value << 6; 18823 md_number_to_chars (buf, newval, THUMB_SIZE); 18824 break; 18825 18826 case BFD_RELOC_VTABLE_INHERIT: 18827 case BFD_RELOC_VTABLE_ENTRY: 18828 fixP->fx_done = 0; 18829 return; 18830 18831 case BFD_RELOC_ARM_MOVW: 18832 case BFD_RELOC_ARM_MOVT: 18833 case BFD_RELOC_ARM_THUMB_MOVW: 18834 case BFD_RELOC_ARM_THUMB_MOVT: 18835 if (fixP->fx_done || !seg->use_rela_p) 18836 { 18837 /* REL format relocations are limited to a 16-bit addend. */ 18838 if (!fixP->fx_done) 18839 { 18840 if (value < -0x1000 || value > 0xffff) 18841 as_bad_where (fixP->fx_file, fixP->fx_line, 18842 _("offset too big")); 18843 } 18844 else if (fixP->fx_r_type == BFD_RELOC_ARM_MOVT 18845 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT) 18846 { 18847 value >>= 16; 18848 } 18849 18850 if (fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW 18851 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT) 18852 { 18853 newval = get_thumb32_insn (buf); 18854 newval &= 0xfbf08f00; 18855 newval |= (value & 0xf000) << 4; 18856 newval |= (value & 0x0800) << 15; 18857 newval |= (value & 0x0700) << 4; 18858 newval |= (value & 0x00ff); 18859 put_thumb32_insn (buf, newval); 18860 } 18861 else 18862 { 18863 newval = md_chars_to_number (buf, 4); 18864 newval &= 0xfff0f000; 18865 newval |= value & 0x0fff; 18866 newval |= (value & 0xf000) << 4; 18867 md_number_to_chars (buf, newval, 4); 18868 } 18869 } 18870 return; 18871 18872 case BFD_RELOC_ARM_ALU_PC_G0_NC: 18873 case BFD_RELOC_ARM_ALU_PC_G0: 18874 case BFD_RELOC_ARM_ALU_PC_G1_NC: 18875 case BFD_RELOC_ARM_ALU_PC_G1: 18876 case BFD_RELOC_ARM_ALU_PC_G2: 18877 case BFD_RELOC_ARM_ALU_SB_G0_NC: 18878 case BFD_RELOC_ARM_ALU_SB_G0: 18879 case BFD_RELOC_ARM_ALU_SB_G1_NC: 18880 case BFD_RELOC_ARM_ALU_SB_G1: 18881 case BFD_RELOC_ARM_ALU_SB_G2: 18882 assert (!fixP->fx_done); 18883 if (!seg->use_rela_p) 18884 { 18885 bfd_vma insn; 18886 bfd_vma encoded_addend; 18887 bfd_vma addend_abs = abs (value); 18888 18889 /* Check that the absolute value of the addend can be 18890 expressed as an 8-bit constant plus a rotation. */ 18891 encoded_addend = encode_arm_immediate (addend_abs); 18892 if (encoded_addend == (unsigned int) FAIL) 18893 as_bad_where (fixP->fx_file, fixP->fx_line, 18894 _("the offset 0x%08lX is not representable"), 18895 (unsigned long) addend_abs); 18896 18897 /* Extract the instruction. */ 18898 insn = md_chars_to_number (buf, INSN_SIZE); 18899 18900 /* If the addend is positive, use an ADD instruction. 18901 Otherwise use a SUB. Take care not to destroy the S bit. */ 18902 insn &= 0xff1fffff; 18903 if (value < 0) 18904 insn |= 1 << 22; 18905 else 18906 insn |= 1 << 23; 18907 18908 /* Place the encoded addend into the first 12 bits of the 18909 instruction. */ 18910 insn &= 0xfffff000; 18911 insn |= encoded_addend; 18912 18913 /* Update the instruction. */ 18914 md_number_to_chars (buf, insn, INSN_SIZE); 18915 } 18916 break; 18917 18918 case BFD_RELOC_ARM_LDR_PC_G0: 18919 case BFD_RELOC_ARM_LDR_PC_G1: 18920 case BFD_RELOC_ARM_LDR_PC_G2: 18921 case BFD_RELOC_ARM_LDR_SB_G0: 18922 case BFD_RELOC_ARM_LDR_SB_G1: 18923 case BFD_RELOC_ARM_LDR_SB_G2: 18924 assert (!fixP->fx_done); 18925 if (!seg->use_rela_p) 18926 { 18927 bfd_vma insn; 18928 bfd_vma addend_abs = abs (value); 18929 18930 /* Check that the absolute value of the addend can be 18931 encoded in 12 bits. */ 18932 if (addend_abs >= 0x1000) 18933 as_bad_where (fixP->fx_file, fixP->fx_line, 18934 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"), 18935 (unsigned long) addend_abs); 18936 18937 /* Extract the instruction. */ 18938 insn = md_chars_to_number (buf, INSN_SIZE); 18939 18940 /* If the addend is negative, clear bit 23 of the instruction. 18941 Otherwise set it. */ 18942 if (value < 0) 18943 insn &= ~(1 << 23); 18944 else 18945 insn |= 1 << 23; 18946 18947 /* Place the absolute value of the addend into the first 12 bits 18948 of the instruction. */ 18949 insn &= 0xfffff000; 18950 insn |= addend_abs; 18951 18952 /* Update the instruction. */ 18953 md_number_to_chars (buf, insn, INSN_SIZE); 18954 } 18955 break; 18956 18957 case BFD_RELOC_ARM_LDRS_PC_G0: 18958 case BFD_RELOC_ARM_LDRS_PC_G1: 18959 case BFD_RELOC_ARM_LDRS_PC_G2: 18960 case BFD_RELOC_ARM_LDRS_SB_G0: 18961 case BFD_RELOC_ARM_LDRS_SB_G1: 18962 case BFD_RELOC_ARM_LDRS_SB_G2: 18963 assert (!fixP->fx_done); 18964 if (!seg->use_rela_p) 18965 { 18966 bfd_vma insn; 18967 bfd_vma addend_abs = abs (value); 18968 18969 /* Check that the absolute value of the addend can be 18970 encoded in 8 bits. */ 18971 if (addend_abs >= 0x100) 18972 as_bad_where (fixP->fx_file, fixP->fx_line, 18973 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"), 18974 (unsigned long) addend_abs); 18975 18976 /* Extract the instruction. */ 18977 insn = md_chars_to_number (buf, INSN_SIZE); 18978 18979 /* If the addend is negative, clear bit 23 of the instruction. 18980 Otherwise set it. */ 18981 if (value < 0) 18982 insn &= ~(1 << 23); 18983 else 18984 insn |= 1 << 23; 18985 18986 /* Place the first four bits of the absolute value of the addend 18987 into the first 4 bits of the instruction, and the remaining 18988 four into bits 8 .. 11. */ 18989 insn &= 0xfffff0f0; 18990 insn |= (addend_abs & 0xf) | ((addend_abs & 0xf0) << 4); 18991 18992 /* Update the instruction. */ 18993 md_number_to_chars (buf, insn, INSN_SIZE); 18994 } 18995 break; 18996 18997 case BFD_RELOC_ARM_LDC_PC_G0: 18998 case BFD_RELOC_ARM_LDC_PC_G1: 18999 case BFD_RELOC_ARM_LDC_PC_G2: 19000 case BFD_RELOC_ARM_LDC_SB_G0: 19001 case BFD_RELOC_ARM_LDC_SB_G1: 19002 case BFD_RELOC_ARM_LDC_SB_G2: 19003 assert (!fixP->fx_done); 19004 if (!seg->use_rela_p) 19005 { 19006 bfd_vma insn; 19007 bfd_vma addend_abs = abs (value); 19008 19009 /* Check that the absolute value of the addend is a multiple of 19010 four and, when divided by four, fits in 8 bits. */ 19011 if (addend_abs & 0x3) 19012 as_bad_where (fixP->fx_file, fixP->fx_line, 19013 _("bad offset 0x%08lX (must be word-aligned)"), 19014 (unsigned long) addend_abs); 19015 19016 if ((addend_abs >> 2) > 0xff) 19017 as_bad_where (fixP->fx_file, fixP->fx_line, 19018 _("bad offset 0x%08lX (must be an 8-bit number of words)"), 19019 (unsigned long) addend_abs); 19020 19021 /* Extract the instruction. */ 19022 insn = md_chars_to_number (buf, INSN_SIZE); 19023 19024 /* If the addend is negative, clear bit 23 of the instruction. 19025 Otherwise set it. */ 19026 if (value < 0) 19027 insn &= ~(1 << 23); 19028 else 19029 insn |= 1 << 23; 19030 19031 /* Place the addend (divided by four) into the first eight 19032 bits of the instruction. */ 19033 insn &= 0xfffffff0; 19034 insn |= addend_abs >> 2; 19035 19036 /* Update the instruction. */ 19037 md_number_to_chars (buf, insn, INSN_SIZE); 19038 } 19039 break; 19040 19041 case BFD_RELOC_UNUSED: 19042 default: 19043 as_bad_where (fixP->fx_file, fixP->fx_line, 19044 _("bad relocation fixup type (%d)"), fixP->fx_r_type); 19045 } 19046} 19047 19048/* Translate internal representation of relocation info to BFD target 19049 format. */ 19050 19051arelent * 19052tc_gen_reloc (asection *section, fixS *fixp) 19053{ 19054 arelent * reloc; 19055 bfd_reloc_code_real_type code; 19056 19057 reloc = xmalloc (sizeof (arelent)); 19058 19059 reloc->sym_ptr_ptr = xmalloc (sizeof (asymbol *)); 19060 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); 19061 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; 19062 19063 if (fixp->fx_pcrel) 19064 { 19065 if (section->use_rela_p) 19066 fixp->fx_offset -= md_pcrel_from_section (fixp, section); 19067 else 19068 fixp->fx_offset = reloc->address; 19069 } 19070 reloc->addend = fixp->fx_offset; 19071 19072 switch (fixp->fx_r_type) 19073 { 19074 case BFD_RELOC_8: 19075 if (fixp->fx_pcrel) 19076 { 19077 code = BFD_RELOC_8_PCREL; 19078 break; 19079 } 19080 19081 case BFD_RELOC_16: 19082 if (fixp->fx_pcrel) 19083 { 19084 code = BFD_RELOC_16_PCREL; 19085 break; 19086 } 19087 19088 case BFD_RELOC_32: 19089 if (fixp->fx_pcrel) 19090 { 19091 code = BFD_RELOC_32_PCREL; 19092 break; 19093 } 19094 19095 case BFD_RELOC_ARM_MOVW: 19096 if (fixp->fx_pcrel) 19097 { 19098 code = BFD_RELOC_ARM_MOVW_PCREL; 19099 break; 19100 } 19101 19102 case BFD_RELOC_ARM_MOVT: 19103 if (fixp->fx_pcrel) 19104 { 19105 code = BFD_RELOC_ARM_MOVT_PCREL; 19106 break; 19107 } 19108 19109 case BFD_RELOC_ARM_THUMB_MOVW: 19110 if (fixp->fx_pcrel) 19111 { 19112 code = BFD_RELOC_ARM_THUMB_MOVW_PCREL; 19113 break; 19114 } 19115 19116 case BFD_RELOC_ARM_THUMB_MOVT: 19117 if (fixp->fx_pcrel) 19118 { 19119 code = BFD_RELOC_ARM_THUMB_MOVT_PCREL; 19120 break; 19121 } 19122 19123 case BFD_RELOC_NONE: 19124 case BFD_RELOC_ARM_PCREL_BRANCH: 19125 case BFD_RELOC_ARM_PCREL_BLX: 19126 case BFD_RELOC_RVA: 19127 case BFD_RELOC_THUMB_PCREL_BRANCH7: 19128 case BFD_RELOC_THUMB_PCREL_BRANCH9: 19129 case BFD_RELOC_THUMB_PCREL_BRANCH12: 19130 case BFD_RELOC_THUMB_PCREL_BRANCH20: 19131 case BFD_RELOC_THUMB_PCREL_BRANCH23: 19132 case BFD_RELOC_THUMB_PCREL_BRANCH25: 19133 case BFD_RELOC_THUMB_PCREL_BLX: 19134 case BFD_RELOC_VTABLE_ENTRY: 19135 case BFD_RELOC_VTABLE_INHERIT: 19136#ifdef TE_PE 19137 case BFD_RELOC_32_SECREL: 19138#endif 19139 code = fixp->fx_r_type; 19140 break; 19141 19142 case BFD_RELOC_ARM_LITERAL: 19143 case BFD_RELOC_ARM_HWLITERAL: 19144 /* If this is called then the a literal has 19145 been referenced across a section boundary. */ 19146 as_bad_where (fixp->fx_file, fixp->fx_line, 19147 _("literal referenced across section boundary")); 19148 return NULL; 19149 19150#ifdef OBJ_ELF 19151 case BFD_RELOC_ARM_GOT32: 19152 case BFD_RELOC_ARM_GOTOFF: 19153 case BFD_RELOC_ARM_PLT32: 19154 case BFD_RELOC_ARM_TARGET1: 19155 case BFD_RELOC_ARM_ROSEGREL32: 19156 case BFD_RELOC_ARM_SBREL32: 19157 case BFD_RELOC_ARM_PREL31: 19158 case BFD_RELOC_ARM_TARGET2: 19159 case BFD_RELOC_ARM_TLS_LE32: 19160 case BFD_RELOC_ARM_TLS_LDO32: 19161 case BFD_RELOC_ARM_PCREL_CALL: 19162 case BFD_RELOC_ARM_PCREL_JUMP: 19163 case BFD_RELOC_ARM_ALU_PC_G0_NC: 19164 case BFD_RELOC_ARM_ALU_PC_G0: 19165 case BFD_RELOC_ARM_ALU_PC_G1_NC: 19166 case BFD_RELOC_ARM_ALU_PC_G1: 19167 case BFD_RELOC_ARM_ALU_PC_G2: 19168 case BFD_RELOC_ARM_LDR_PC_G0: 19169 case BFD_RELOC_ARM_LDR_PC_G1: 19170 case BFD_RELOC_ARM_LDR_PC_G2: 19171 case BFD_RELOC_ARM_LDRS_PC_G0: 19172 case BFD_RELOC_ARM_LDRS_PC_G1: 19173 case BFD_RELOC_ARM_LDRS_PC_G2: 19174 case BFD_RELOC_ARM_LDC_PC_G0: 19175 case BFD_RELOC_ARM_LDC_PC_G1: 19176 case BFD_RELOC_ARM_LDC_PC_G2: 19177 case BFD_RELOC_ARM_ALU_SB_G0_NC: 19178 case BFD_RELOC_ARM_ALU_SB_G0: 19179 case BFD_RELOC_ARM_ALU_SB_G1_NC: 19180 case BFD_RELOC_ARM_ALU_SB_G1: 19181 case BFD_RELOC_ARM_ALU_SB_G2: 19182 case BFD_RELOC_ARM_LDR_SB_G0: 19183 case BFD_RELOC_ARM_LDR_SB_G1: 19184 case BFD_RELOC_ARM_LDR_SB_G2: 19185 case BFD_RELOC_ARM_LDRS_SB_G0: 19186 case BFD_RELOC_ARM_LDRS_SB_G1: 19187 case BFD_RELOC_ARM_LDRS_SB_G2: 19188 case BFD_RELOC_ARM_LDC_SB_G0: 19189 case BFD_RELOC_ARM_LDC_SB_G1: 19190 case BFD_RELOC_ARM_LDC_SB_G2: 19191 code = fixp->fx_r_type; 19192 break; 19193 19194 case BFD_RELOC_ARM_TLS_GD32: 19195 case BFD_RELOC_ARM_TLS_IE32: 19196 case BFD_RELOC_ARM_TLS_LDM32: 19197 /* BFD will include the symbol's address in the addend. 19198 But we don't want that, so subtract it out again here. */ 19199 if (!S_IS_COMMON (fixp->fx_addsy)) 19200 reloc->addend -= (*reloc->sym_ptr_ptr)->value; 19201 code = fixp->fx_r_type; 19202 break; 19203#endif 19204 19205 case BFD_RELOC_ARM_IMMEDIATE: 19206 as_bad_where (fixp->fx_file, fixp->fx_line, 19207 _("internal relocation (type: IMMEDIATE) not fixed up")); 19208 return NULL; 19209 19210 case BFD_RELOC_ARM_ADRL_IMMEDIATE: 19211 as_bad_where (fixp->fx_file, fixp->fx_line, 19212 _("ADRL used for a symbol not defined in the same file")); 19213 return NULL; 19214 19215 case BFD_RELOC_ARM_OFFSET_IMM: 19216 if (section->use_rela_p) 19217 { 19218 code = fixp->fx_r_type; 19219 break; 19220 } 19221 19222 if (fixp->fx_addsy != NULL 19223 && !S_IS_DEFINED (fixp->fx_addsy) 19224 && S_IS_LOCAL (fixp->fx_addsy)) 19225 { 19226 as_bad_where (fixp->fx_file, fixp->fx_line, 19227 _("undefined local label `%s'"), 19228 S_GET_NAME (fixp->fx_addsy)); 19229 return NULL; 19230 } 19231 19232 as_bad_where (fixp->fx_file, fixp->fx_line, 19233 _("internal_relocation (type: OFFSET_IMM) not fixed up")); 19234 return NULL; 19235 19236 default: 19237 { 19238 char * type; 19239 19240 switch (fixp->fx_r_type) 19241 { 19242 case BFD_RELOC_NONE: type = "NONE"; break; 19243 case BFD_RELOC_ARM_OFFSET_IMM8: type = "OFFSET_IMM8"; break; 19244 case BFD_RELOC_ARM_SHIFT_IMM: type = "SHIFT_IMM"; break; 19245 case BFD_RELOC_ARM_SMC: type = "SMC"; break; 19246 case BFD_RELOC_ARM_SWI: type = "SWI"; break; 19247 case BFD_RELOC_ARM_MULTI: type = "MULTI"; break; 19248 case BFD_RELOC_ARM_CP_OFF_IMM: type = "CP_OFF_IMM"; break; 19249 case BFD_RELOC_ARM_T32_CP_OFF_IMM: type = "T32_CP_OFF_IMM"; break; 19250 case BFD_RELOC_ARM_THUMB_ADD: type = "THUMB_ADD"; break; 19251 case BFD_RELOC_ARM_THUMB_SHIFT: type = "THUMB_SHIFT"; break; 19252 case BFD_RELOC_ARM_THUMB_IMM: type = "THUMB_IMM"; break; 19253 case BFD_RELOC_ARM_THUMB_OFFSET: type = "THUMB_OFFSET"; break; 19254 default: type = _("<unknown>"); break; 19255 } 19256 as_bad_where (fixp->fx_file, fixp->fx_line, 19257 _("cannot represent %s relocation in this object file format"), 19258 type); 19259 return NULL; 19260 } 19261 } 19262 19263#ifdef OBJ_ELF 19264 if ((code == BFD_RELOC_32_PCREL || code == BFD_RELOC_32) 19265 && GOT_symbol 19266 && fixp->fx_addsy == GOT_symbol) 19267 { 19268 code = BFD_RELOC_ARM_GOTPC; 19269 reloc->addend = fixp->fx_offset = reloc->address; 19270 } 19271#endif 19272 19273 reloc->howto = bfd_reloc_type_lookup (stdoutput, code); 19274 19275 if (reloc->howto == NULL) 19276 { 19277 as_bad_where (fixp->fx_file, fixp->fx_line, 19278 _("cannot represent %s relocation in this object file format"), 19279 bfd_get_reloc_code_name (code)); 19280 return NULL; 19281 } 19282 19283 /* HACK: Since arm ELF uses Rel instead of Rela, encode the 19284 vtable entry to be used in the relocation's section offset. */ 19285 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) 19286 reloc->address = fixp->fx_offset; 19287 19288 return reloc; 19289} 19290 19291/* This fix_new is called by cons via TC_CONS_FIX_NEW. */ 19292 19293void 19294cons_fix_new_arm (fragS * frag, 19295 int where, 19296 int size, 19297 expressionS * exp) 19298{ 19299 bfd_reloc_code_real_type type; 19300 int pcrel = 0; 19301 19302 /* Pick a reloc. 19303 FIXME: @@ Should look at CPU word size. */ 19304 switch (size) 19305 { 19306 case 1: 19307 type = BFD_RELOC_8; 19308 break; 19309 case 2: 19310 type = BFD_RELOC_16; 19311 break; 19312 case 4: 19313 default: 19314 type = BFD_RELOC_32; 19315 break; 19316 case 8: 19317 type = BFD_RELOC_64; 19318 break; 19319 } 19320 19321#ifdef TE_PE 19322 if (exp->X_op == O_secrel) 19323 { 19324 exp->X_op = O_symbol; 19325 type = BFD_RELOC_32_SECREL; 19326 } 19327#endif 19328 19329 fix_new_exp (frag, where, (int) size, exp, pcrel, type); 19330} 19331 19332#if defined OBJ_COFF || defined OBJ_ELF 19333void 19334arm_validate_fix (fixS * fixP) 19335{ 19336 /* If the destination of the branch is a defined symbol which does not have 19337 the THUMB_FUNC attribute, then we must be calling a function which has 19338 the (interfacearm) attribute. We look for the Thumb entry point to that 19339 function and change the branch to refer to that function instead. */ 19340 if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BRANCH23 19341 && fixP->fx_addsy != NULL 19342 && S_IS_DEFINED (fixP->fx_addsy) 19343 && ! THUMB_IS_FUNC (fixP->fx_addsy)) 19344 { 19345 fixP->fx_addsy = find_real_start (fixP->fx_addsy); 19346 } 19347} 19348#endif 19349 19350int 19351arm_force_relocation (struct fix * fixp) 19352{ 19353#if defined (OBJ_COFF) && defined (TE_PE) 19354 if (fixp->fx_r_type == BFD_RELOC_RVA) 19355 return 1; 19356#endif 19357 19358 /* Resolve these relocations even if the symbol is extern or weak. */ 19359 if (fixp->fx_r_type == BFD_RELOC_ARM_IMMEDIATE 19360 || fixp->fx_r_type == BFD_RELOC_ARM_OFFSET_IMM 19361 || fixp->fx_r_type == BFD_RELOC_ARM_ADRL_IMMEDIATE 19362 || fixp->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM 19363 || fixp->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE 19364 || fixp->fx_r_type == BFD_RELOC_ARM_T32_IMM12 19365 || fixp->fx_r_type == BFD_RELOC_ARM_T32_ADD_PC12) 19366 return 0; 19367 19368 /* Always leave these relocations for the linker. */ 19369 if ((fixp->fx_r_type >= BFD_RELOC_ARM_ALU_PC_G0_NC 19370 && fixp->fx_r_type <= BFD_RELOC_ARM_LDC_SB_G2) 19371 || fixp->fx_r_type == BFD_RELOC_ARM_LDR_PC_G0) 19372 return 1; 19373 19374 /* Always generate relocations against function symbols. */ 19375 if (fixp->fx_r_type == BFD_RELOC_32 19376 && fixp->fx_addsy 19377 && (symbol_get_bfdsym (fixp->fx_addsy)->flags & BSF_FUNCTION)) 19378 return 1; 19379 19380 return generic_force_reloc (fixp); 19381} 19382 19383#if defined (OBJ_ELF) || defined (OBJ_COFF) 19384/* Relocations against function names must be left unadjusted, 19385 so that the linker can use this information to generate interworking 19386 stubs. The MIPS version of this function 19387 also prevents relocations that are mips-16 specific, but I do not 19388 know why it does this. 19389 19390 FIXME: 19391 There is one other problem that ought to be addressed here, but 19392 which currently is not: Taking the address of a label (rather 19393 than a function) and then later jumping to that address. Such 19394 addresses also ought to have their bottom bit set (assuming that 19395 they reside in Thumb code), but at the moment they will not. */ 19396 19397bfd_boolean 19398arm_fix_adjustable (fixS * fixP) 19399{ 19400 if (fixP->fx_addsy == NULL) 19401 return 1; 19402 19403 /* Preserve relocations against symbols with function type. */ 19404 if (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_FUNCTION) 19405 return 0; 19406 19407 if (THUMB_IS_FUNC (fixP->fx_addsy) 19408 && fixP->fx_subsy == NULL) 19409 return 0; 19410 19411 /* We need the symbol name for the VTABLE entries. */ 19412 if ( fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT 19413 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) 19414 return 0; 19415 19416 /* Don't allow symbols to be discarded on GOT related relocs. */ 19417 if (fixP->fx_r_type == BFD_RELOC_ARM_PLT32 19418 || fixP->fx_r_type == BFD_RELOC_ARM_GOT32 19419 || fixP->fx_r_type == BFD_RELOC_ARM_GOTOFF 19420 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_GD32 19421 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LE32 19422 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_IE32 19423 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDM32 19424 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDO32 19425 || fixP->fx_r_type == BFD_RELOC_ARM_TARGET2) 19426 return 0; 19427 19428 /* Similarly for group relocations. */ 19429 if ((fixP->fx_r_type >= BFD_RELOC_ARM_ALU_PC_G0_NC 19430 && fixP->fx_r_type <= BFD_RELOC_ARM_LDC_SB_G2) 19431 || fixP->fx_r_type == BFD_RELOC_ARM_LDR_PC_G0) 19432 return 0; 19433 19434 if (fixP->fx_r_type == BFD_RELOC_ARM_MOVW 19435 || fixP->fx_r_type == BFD_RELOC_ARM_MOVT 19436 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW 19437 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT) 19438 return 0; 19439 19440 return 1; 19441} 19442#endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */ 19443 19444#ifdef OBJ_ELF 19445 19446const char * 19447elf32_arm_target_format (void) 19448{ 19449#ifdef TE_SYMBIAN 19450 return (target_big_endian 19451 ? "elf32-bigarm-symbian" 19452 : "elf32-littlearm-symbian"); 19453#elif defined (TE_VXWORKS) 19454 return (target_big_endian 19455 ? "elf32-bigarm-vxworks" 19456 : "elf32-littlearm-vxworks"); 19457#else 19458 if (target_big_endian) 19459 return "elf32-bigarm"; 19460 else 19461 return "elf32-littlearm"; 19462#endif 19463} 19464 19465void 19466armelf_frob_symbol (symbolS * symp, 19467 int * puntp) 19468{ 19469 elf_frob_symbol (symp, puntp); 19470} 19471#endif 19472 19473/* MD interface: Finalization. */ 19474 19475/* A good place to do this, although this was probably not intended 19476 for this kind of use. We need to dump the literal pool before 19477 references are made to a null symbol pointer. */ 19478 19479void 19480arm_cleanup (void) 19481{ 19482 literal_pool * pool; 19483 19484 for (pool = list_of_pools; pool; pool = pool->next) 19485 { 19486 /* Put it at the end of the relevent section. */ 19487 subseg_set (pool->section, pool->sub_section); 19488#ifdef OBJ_ELF 19489 arm_elf_change_section (); 19490#endif 19491 s_ltorg (0); 19492 } 19493} 19494 19495/* Adjust the symbol table. This marks Thumb symbols as distinct from 19496 ARM ones. */ 19497 19498void 19499arm_adjust_symtab (void) 19500{ 19501#ifdef OBJ_COFF 19502 symbolS * sym; 19503 19504 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym)) 19505 { 19506 if (ARM_IS_THUMB (sym)) 19507 { 19508 if (THUMB_IS_FUNC (sym)) 19509 { 19510 /* Mark the symbol as a Thumb function. */ 19511 if ( S_GET_STORAGE_CLASS (sym) == C_STAT 19512 || S_GET_STORAGE_CLASS (sym) == C_LABEL) /* This can happen! */ 19513 S_SET_STORAGE_CLASS (sym, C_THUMBSTATFUNC); 19514 19515 else if (S_GET_STORAGE_CLASS (sym) == C_EXT) 19516 S_SET_STORAGE_CLASS (sym, C_THUMBEXTFUNC); 19517 else 19518 as_bad (_("%s: unexpected function type: %d"), 19519 S_GET_NAME (sym), S_GET_STORAGE_CLASS (sym)); 19520 } 19521 else switch (S_GET_STORAGE_CLASS (sym)) 19522 { 19523 case C_EXT: 19524 S_SET_STORAGE_CLASS (sym, C_THUMBEXT); 19525 break; 19526 case C_STAT: 19527 S_SET_STORAGE_CLASS (sym, C_THUMBSTAT); 19528 break; 19529 case C_LABEL: 19530 S_SET_STORAGE_CLASS (sym, C_THUMBLABEL); 19531 break; 19532 default: 19533 /* Do nothing. */ 19534 break; 19535 } 19536 } 19537 19538 if (ARM_IS_INTERWORK (sym)) 19539 coffsymbol (symbol_get_bfdsym (sym))->native->u.syment.n_flags = 0xFF; 19540 } 19541#endif 19542#ifdef OBJ_ELF 19543 symbolS * sym; 19544 char bind; 19545 19546 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym)) 19547 { 19548 if (ARM_IS_THUMB (sym)) 19549 { 19550 elf_symbol_type * elf_sym; 19551 19552 elf_sym = elf_symbol (symbol_get_bfdsym (sym)); 19553 bind = ELF_ST_BIND (elf_sym->internal_elf_sym.st_info); 19554 19555 if (! bfd_is_arm_special_symbol_name (elf_sym->symbol.name, 19556 BFD_ARM_SPECIAL_SYM_TYPE_ANY)) 19557 { 19558 /* If it's a .thumb_func, declare it as so, 19559 otherwise tag label as .code 16. */ 19560 if (THUMB_IS_FUNC (sym)) 19561 elf_sym->internal_elf_sym.st_info = 19562 ELF_ST_INFO (bind, STT_ARM_TFUNC); 19563 else if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4) 19564 elf_sym->internal_elf_sym.st_info = 19565 ELF_ST_INFO (bind, STT_ARM_16BIT); 19566 } 19567 } 19568 } 19569#endif 19570} 19571 19572/* MD interface: Initialization. */ 19573 19574static void 19575set_constant_flonums (void) 19576{ 19577 int i; 19578 19579 for (i = 0; i < NUM_FLOAT_VALS; i++) 19580 if (atof_ieee ((char *) fp_const[i], 'x', fp_values[i]) == NULL) 19581 abort (); 19582} 19583 19584/* Auto-select Thumb mode if it's the only available instruction set for the 19585 given architecture. */ 19586 19587static void 19588autoselect_thumb_from_cpu_variant (void) 19589{ 19590 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1)) 19591 opcode_select (16); 19592} 19593 19594void 19595md_begin (void) 19596{ 19597 unsigned mach; 19598 unsigned int i; 19599 19600 if ( (arm_ops_hsh = hash_new ()) == NULL 19601 || (arm_cond_hsh = hash_new ()) == NULL 19602 || (arm_shift_hsh = hash_new ()) == NULL 19603 || (arm_psr_hsh = hash_new ()) == NULL 19604 || (arm_v7m_psr_hsh = hash_new ()) == NULL 19605 || (arm_reg_hsh = hash_new ()) == NULL 19606 || (arm_reloc_hsh = hash_new ()) == NULL 19607 || (arm_barrier_opt_hsh = hash_new ()) == NULL) 19608 as_fatal (_("virtual memory exhausted")); 19609 19610 for (i = 0; i < sizeof (insns) / sizeof (struct asm_opcode); i++) 19611 hash_insert (arm_ops_hsh, insns[i].template, (PTR) (insns + i)); 19612 for (i = 0; i < sizeof (conds) / sizeof (struct asm_cond); i++) 19613 hash_insert (arm_cond_hsh, conds[i].template, (PTR) (conds + i)); 19614 for (i = 0; i < sizeof (shift_names) / sizeof (struct asm_shift_name); i++) 19615 hash_insert (arm_shift_hsh, shift_names[i].name, (PTR) (shift_names + i)); 19616 for (i = 0; i < sizeof (psrs) / sizeof (struct asm_psr); i++) 19617 hash_insert (arm_psr_hsh, psrs[i].template, (PTR) (psrs + i)); 19618 for (i = 0; i < sizeof (v7m_psrs) / sizeof (struct asm_psr); i++) 19619 hash_insert (arm_v7m_psr_hsh, v7m_psrs[i].template, (PTR) (v7m_psrs + i)); 19620 for (i = 0; i < sizeof (reg_names) / sizeof (struct reg_entry); i++) 19621 hash_insert (arm_reg_hsh, reg_names[i].name, (PTR) (reg_names + i)); 19622 for (i = 0; 19623 i < sizeof (barrier_opt_names) / sizeof (struct asm_barrier_opt); 19624 i++) 19625 hash_insert (arm_barrier_opt_hsh, barrier_opt_names[i].template, 19626 (PTR) (barrier_opt_names + i)); 19627#ifdef OBJ_ELF 19628 for (i = 0; i < sizeof (reloc_names) / sizeof (struct reloc_entry); i++) 19629 hash_insert (arm_reloc_hsh, reloc_names[i].name, (PTR) (reloc_names + i)); 19630#endif 19631 19632 set_constant_flonums (); 19633 19634 /* Set the cpu variant based on the command-line options. We prefer 19635 -mcpu= over -march= if both are set (as for GCC); and we prefer 19636 -mfpu= over any other way of setting the floating point unit. 19637 Use of legacy options with new options are faulted. */ 19638 if (legacy_cpu) 19639 { 19640 if (mcpu_cpu_opt || march_cpu_opt) 19641 as_bad (_("use of old and new-style options to set CPU type")); 19642 19643 mcpu_cpu_opt = legacy_cpu; 19644 } 19645 else if (!mcpu_cpu_opt) 19646 mcpu_cpu_opt = march_cpu_opt; 19647 19648 if (legacy_fpu) 19649 { 19650 if (mfpu_opt) 19651 as_bad (_("use of old and new-style options to set FPU type")); 19652 19653 mfpu_opt = legacy_fpu; 19654 } 19655 else if (!mfpu_opt) 19656 { 19657#if !(defined (TE_LINUX) || defined (TE_NetBSD) || defined (TE_VXWORKS)) 19658 /* Some environments specify a default FPU. If they don't, infer it 19659 from the processor. */ 19660 if (mcpu_fpu_opt) 19661 mfpu_opt = mcpu_fpu_opt; 19662 else 19663 mfpu_opt = march_fpu_opt; 19664#else 19665 mfpu_opt = &fpu_default; 19666#endif 19667 } 19668 19669 if (!mfpu_opt) 19670 { 19671 if (mcpu_cpu_opt != NULL) 19672 mfpu_opt = &fpu_default; 19673 else if (mcpu_fpu_opt != NULL && ARM_CPU_HAS_FEATURE (*mcpu_fpu_opt, arm_ext_v5)) 19674 mfpu_opt = &fpu_arch_vfp_v2; 19675 else 19676 mfpu_opt = &fpu_arch_fpa; 19677 } 19678 19679#ifdef CPU_DEFAULT 19680 if (!mcpu_cpu_opt) 19681 { 19682 mcpu_cpu_opt = &cpu_default; 19683 selected_cpu = cpu_default; 19684 } 19685#else 19686 if (mcpu_cpu_opt) 19687 selected_cpu = *mcpu_cpu_opt; 19688 else 19689 mcpu_cpu_opt = &arm_arch_any; 19690#endif 19691 19692 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt); 19693 19694 autoselect_thumb_from_cpu_variant (); 19695 19696 arm_arch_used = thumb_arch_used = arm_arch_none; 19697 19698#if defined OBJ_COFF || defined OBJ_ELF 19699 { 19700 unsigned int flags = 0; 19701 19702#if defined OBJ_ELF 19703 flags = meabi_flags; 19704 19705 switch (meabi_flags) 19706 { 19707 case EF_ARM_EABI_UNKNOWN: 19708#endif 19709 /* Set the flags in the private structure. */ 19710 if (uses_apcs_26) flags |= F_APCS26; 19711 if (support_interwork) flags |= F_INTERWORK; 19712 if (uses_apcs_float) flags |= F_APCS_FLOAT; 19713 if (pic_code) flags |= F_PIC; 19714 if (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_any_hard)) 19715 flags |= F_SOFT_FLOAT; 19716 19717 switch (mfloat_abi_opt) 19718 { 19719 case ARM_FLOAT_ABI_SOFT: 19720 case ARM_FLOAT_ABI_SOFTFP: 19721 flags |= F_SOFT_FLOAT; 19722 break; 19723 19724 case ARM_FLOAT_ABI_HARD: 19725 if (flags & F_SOFT_FLOAT) 19726 as_bad (_("hard-float conflicts with specified fpu")); 19727 break; 19728 } 19729 19730 /* Using pure-endian doubles (even if soft-float). */ 19731 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_endian_pure)) 19732 flags |= F_VFP_FLOAT; 19733 19734#if defined OBJ_ELF 19735 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_arch_maverick)) 19736 flags |= EF_ARM_MAVERICK_FLOAT; 19737 break; 19738 19739 case EF_ARM_EABI_VER4: 19740 case EF_ARM_EABI_VER5: 19741 /* No additional flags to set. */ 19742 break; 19743 19744 default: 19745 abort (); 19746 } 19747#endif 19748 bfd_set_private_flags (stdoutput, flags); 19749 19750 /* We have run out flags in the COFF header to encode the 19751 status of ATPCS support, so instead we create a dummy, 19752 empty, debug section called .arm.atpcs. */ 19753 if (atpcs) 19754 { 19755 asection * sec; 19756 19757 sec = bfd_make_section (stdoutput, ".arm.atpcs"); 19758 19759 if (sec != NULL) 19760 { 19761 bfd_set_section_flags 19762 (stdoutput, sec, SEC_READONLY | SEC_DEBUGGING /* | SEC_HAS_CONTENTS */); 19763 bfd_set_section_size (stdoutput, sec, 0); 19764 bfd_set_section_contents (stdoutput, sec, NULL, 0, 0); 19765 } 19766 } 19767 } 19768#endif 19769 19770 /* Record the CPU type as well. */ 19771 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2)) 19772 mach = bfd_mach_arm_iWMMXt2; 19773 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt)) 19774 mach = bfd_mach_arm_iWMMXt; 19775 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_xscale)) 19776 mach = bfd_mach_arm_XScale; 19777 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_maverick)) 19778 mach = bfd_mach_arm_ep9312; 19779 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v5e)) 19780 mach = bfd_mach_arm_5TE; 19781 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v5)) 19782 { 19783 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t)) 19784 mach = bfd_mach_arm_5T; 19785 else 19786 mach = bfd_mach_arm_5; 19787 } 19788 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4)) 19789 { 19790 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t)) 19791 mach = bfd_mach_arm_4T; 19792 else 19793 mach = bfd_mach_arm_4; 19794 } 19795 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v3m)) 19796 mach = bfd_mach_arm_3M; 19797 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v3)) 19798 mach = bfd_mach_arm_3; 19799 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v2s)) 19800 mach = bfd_mach_arm_2a; 19801 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v2)) 19802 mach = bfd_mach_arm_2; 19803 else 19804 mach = bfd_mach_arm_unknown; 19805 19806 bfd_set_arch_mach (stdoutput, TARGET_ARCH, mach); 19807} 19808 19809/* Command line processing. */ 19810 19811/* md_parse_option 19812 Invocation line includes a switch not recognized by the base assembler. 19813 See if it's a processor-specific option. 19814 19815 This routine is somewhat complicated by the need for backwards 19816 compatibility (since older releases of gcc can't be changed). 19817 The new options try to make the interface as compatible as 19818 possible with GCC. 19819 19820 New options (supported) are: 19821 19822 -mcpu=<cpu name> Assemble for selected processor 19823 -march=<architecture name> Assemble for selected architecture 19824 -mfpu=<fpu architecture> Assemble for selected FPU. 19825 -EB/-mbig-endian Big-endian 19826 -EL/-mlittle-endian Little-endian 19827 -k Generate PIC code 19828 -mthumb Start in Thumb mode 19829 -mthumb-interwork Code supports ARM/Thumb interworking 19830 19831 For now we will also provide support for: 19832 19833 -mapcs-32 32-bit Program counter 19834 -mapcs-26 26-bit Program counter 19835 -macps-float Floats passed in FP registers 19836 -mapcs-reentrant Reentrant code 19837 -matpcs 19838 (sometime these will probably be replaced with -mapcs=<list of options> 19839 and -matpcs=<list of options>) 19840 19841 The remaining options are only supported for back-wards compatibility. 19842 Cpu variants, the arm part is optional: 19843 -m[arm]1 Currently not supported. 19844 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor 19845 -m[arm]3 Arm 3 processor 19846 -m[arm]6[xx], Arm 6 processors 19847 -m[arm]7[xx][t][[d]m] Arm 7 processors 19848 -m[arm]8[10] Arm 8 processors 19849 -m[arm]9[20][tdmi] Arm 9 processors 19850 -mstrongarm[110[0]] StrongARM processors 19851 -mxscale XScale processors 19852 -m[arm]v[2345[t[e]]] Arm architectures 19853 -mall All (except the ARM1) 19854 FP variants: 19855 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions 19856 -mfpe-old (No float load/store multiples) 19857 -mvfpxd VFP Single precision 19858 -mvfp All VFP 19859 -mno-fpu Disable all floating point instructions 19860 19861 The following CPU names are recognized: 19862 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620, 19863 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700, 19864 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c, 19865 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9, 19866 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e, 19867 arm10t arm10e, arm1020t, arm1020e, arm10200e, 19868 strongarm, strongarm110, strongarm1100, strongarm1110, xscale. 19869 19870 */ 19871 19872const char * md_shortopts = "m:k"; 19873 19874#ifdef ARM_BI_ENDIAN 19875#define OPTION_EB (OPTION_MD_BASE + 0) 19876#define OPTION_EL (OPTION_MD_BASE + 1) 19877#else 19878#if TARGET_BYTES_BIG_ENDIAN 19879#define OPTION_EB (OPTION_MD_BASE + 0) 19880#else 19881#define OPTION_EL (OPTION_MD_BASE + 1) 19882#endif 19883#endif 19884 19885struct option md_longopts[] = 19886{ 19887#ifdef OPTION_EB 19888 {"EB", no_argument, NULL, OPTION_EB}, 19889#endif 19890#ifdef OPTION_EL 19891 {"EL", no_argument, NULL, OPTION_EL}, 19892#endif 19893 {NULL, no_argument, NULL, 0} 19894}; 19895 19896size_t md_longopts_size = sizeof (md_longopts); 19897 19898struct arm_option_table 19899{ 19900 char *option; /* Option name to match. */ 19901 char *help; /* Help information. */ 19902 int *var; /* Variable to change. */ 19903 int value; /* What to change it to. */ 19904 char *deprecated; /* If non-null, print this message. */ 19905}; 19906 19907struct arm_option_table arm_opts[] = 19908{ 19909 {"k", N_("generate PIC code"), &pic_code, 1, NULL}, 19910 {"mthumb", N_("assemble Thumb code"), &thumb_mode, 1, NULL}, 19911 {"mthumb-interwork", N_("support ARM/Thumb interworking"), 19912 &support_interwork, 1, NULL}, 19913 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26, 0, NULL}, 19914 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26, 1, NULL}, 19915 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float, 19916 1, NULL}, 19917 {"mapcs-reentrant", N_("re-entrant code"), &pic_code, 1, NULL}, 19918 {"matpcs", N_("code is ATPCS conformant"), &atpcs, 1, NULL}, 19919 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian, 1, NULL}, 19920 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian, 0, 19921 NULL}, 19922 19923 /* These are recognized by the assembler, but have no affect on code. */ 19924 {"mapcs-frame", N_("use frame pointer"), NULL, 0, NULL}, 19925 {"mapcs-stack-check", N_("use stack size checking"), NULL, 0, NULL}, 19926 {NULL, NULL, NULL, 0, NULL} 19927}; 19928 19929struct arm_legacy_option_table 19930{ 19931 char *option; /* Option name to match. */ 19932 const arm_feature_set **var; /* Variable to change. */ 19933 const arm_feature_set value; /* What to change it to. */ 19934 char *deprecated; /* If non-null, print this message. */ 19935}; 19936 19937const struct arm_legacy_option_table arm_legacy_opts[] = 19938{ 19939 /* DON'T add any new processors to this list -- we want the whole list 19940 to go away... Add them to the processors table instead. */ 19941 {"marm1", &legacy_cpu, ARM_ARCH_V1, N_("use -mcpu=arm1")}, 19942 {"m1", &legacy_cpu, ARM_ARCH_V1, N_("use -mcpu=arm1")}, 19943 {"marm2", &legacy_cpu, ARM_ARCH_V2, N_("use -mcpu=arm2")}, 19944 {"m2", &legacy_cpu, ARM_ARCH_V2, N_("use -mcpu=arm2")}, 19945 {"marm250", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")}, 19946 {"m250", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")}, 19947 {"marm3", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")}, 19948 {"m3", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")}, 19949 {"marm6", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm6")}, 19950 {"m6", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm6")}, 19951 {"marm600", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm600")}, 19952 {"m600", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm600")}, 19953 {"marm610", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm610")}, 19954 {"m610", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm610")}, 19955 {"marm620", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm620")}, 19956 {"m620", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm620")}, 19957 {"marm7", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7")}, 19958 {"m7", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7")}, 19959 {"marm70", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm70")}, 19960 {"m70", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm70")}, 19961 {"marm700", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700")}, 19962 {"m700", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700")}, 19963 {"marm700i", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700i")}, 19964 {"m700i", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700i")}, 19965 {"marm710", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710")}, 19966 {"m710", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710")}, 19967 {"marm710c", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710c")}, 19968 {"m710c", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710c")}, 19969 {"marm720", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm720")}, 19970 {"m720", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm720")}, 19971 {"marm7d", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7d")}, 19972 {"m7d", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7d")}, 19973 {"marm7di", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7di")}, 19974 {"m7di", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7di")}, 19975 {"marm7m", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")}, 19976 {"m7m", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")}, 19977 {"marm7dm", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")}, 19978 {"m7dm", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")}, 19979 {"marm7dmi", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")}, 19980 {"m7dmi", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")}, 19981 {"marm7100", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7100")}, 19982 {"m7100", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7100")}, 19983 {"marm7500", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500")}, 19984 {"m7500", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500")}, 19985 {"marm7500fe", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500fe")}, 19986 {"m7500fe", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500fe")}, 19987 {"marm7t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")}, 19988 {"m7t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")}, 19989 {"marm7tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")}, 19990 {"m7tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")}, 19991 {"marm710t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")}, 19992 {"m710t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")}, 19993 {"marm720t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")}, 19994 {"m720t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")}, 19995 {"marm740t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")}, 19996 {"m740t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")}, 19997 {"marm8", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm8")}, 19998 {"m8", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm8")}, 19999 {"marm810", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm810")}, 20000 {"m810", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm810")}, 20001 {"marm9", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")}, 20002 {"m9", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")}, 20003 {"marm9tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")}, 20004 {"m9tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")}, 20005 {"marm920", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")}, 20006 {"m920", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")}, 20007 {"marm940", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")}, 20008 {"m940", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")}, 20009 {"mstrongarm", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=strongarm")}, 20010 {"mstrongarm110", &legacy_cpu, ARM_ARCH_V4, 20011 N_("use -mcpu=strongarm110")}, 20012 {"mstrongarm1100", &legacy_cpu, ARM_ARCH_V4, 20013 N_("use -mcpu=strongarm1100")}, 20014 {"mstrongarm1110", &legacy_cpu, ARM_ARCH_V4, 20015 N_("use -mcpu=strongarm1110")}, 20016 {"mxscale", &legacy_cpu, ARM_ARCH_XSCALE, N_("use -mcpu=xscale")}, 20017 {"miwmmxt", &legacy_cpu, ARM_ARCH_IWMMXT, N_("use -mcpu=iwmmxt")}, 20018 {"mall", &legacy_cpu, ARM_ANY, N_("use -mcpu=all")}, 20019 20020 /* Architecture variants -- don't add any more to this list either. */ 20021 {"mv2", &legacy_cpu, ARM_ARCH_V2, N_("use -march=armv2")}, 20022 {"marmv2", &legacy_cpu, ARM_ARCH_V2, N_("use -march=armv2")}, 20023 {"mv2a", &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")}, 20024 {"marmv2a", &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")}, 20025 {"mv3", &legacy_cpu, ARM_ARCH_V3, N_("use -march=armv3")}, 20026 {"marmv3", &legacy_cpu, ARM_ARCH_V3, N_("use -march=armv3")}, 20027 {"mv3m", &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")}, 20028 {"marmv3m", &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")}, 20029 {"mv4", &legacy_cpu, ARM_ARCH_V4, N_("use -march=armv4")}, 20030 {"marmv4", &legacy_cpu, ARM_ARCH_V4, N_("use -march=armv4")}, 20031 {"mv4t", &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")}, 20032 {"marmv4t", &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")}, 20033 {"mv5", &legacy_cpu, ARM_ARCH_V5, N_("use -march=armv5")}, 20034 {"marmv5", &legacy_cpu, ARM_ARCH_V5, N_("use -march=armv5")}, 20035 {"mv5t", &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")}, 20036 {"marmv5t", &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")}, 20037 {"mv5e", &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")}, 20038 {"marmv5e", &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")}, 20039 20040 /* Floating point variants -- don't add any more to this list either. */ 20041 {"mfpe-old", &legacy_fpu, FPU_ARCH_FPE, N_("use -mfpu=fpe")}, 20042 {"mfpa10", &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa10")}, 20043 {"mfpa11", &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa11")}, 20044 {"mno-fpu", &legacy_fpu, ARM_ARCH_NONE, 20045 N_("use either -mfpu=softfpa or -mfpu=softvfp")}, 20046 20047 {NULL, NULL, ARM_ARCH_NONE, NULL} 20048}; 20049 20050struct arm_cpu_option_table 20051{ 20052 char *name; 20053 const arm_feature_set value; 20054 /* For some CPUs we assume an FPU unless the user explicitly sets 20055 -mfpu=... */ 20056 const arm_feature_set default_fpu; 20057 /* The canonical name of the CPU, or NULL to use NAME converted to upper 20058 case. */ 20059 const char *canonical_name; 20060}; 20061 20062/* This list should, at a minimum, contain all the cpu names 20063 recognized by GCC. */ 20064static const struct arm_cpu_option_table arm_cpus[] = 20065{ 20066 {"all", ARM_ANY, FPU_ARCH_FPA, NULL}, 20067 {"arm1", ARM_ARCH_V1, FPU_ARCH_FPA, NULL}, 20068 {"arm2", ARM_ARCH_V2, FPU_ARCH_FPA, NULL}, 20069 {"arm250", ARM_ARCH_V2S, FPU_ARCH_FPA, NULL}, 20070 {"arm3", ARM_ARCH_V2S, FPU_ARCH_FPA, NULL}, 20071 {"arm6", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, 20072 {"arm60", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, 20073 {"arm600", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, 20074 {"arm610", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, 20075 {"arm620", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, 20076 {"arm7", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, 20077 {"arm7m", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL}, 20078 {"arm7d", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, 20079 {"arm7dm", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL}, 20080 {"arm7di", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, 20081 {"arm7dmi", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL}, 20082 {"arm70", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, 20083 {"arm700", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, 20084 {"arm700i", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, 20085 {"arm710", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, 20086 {"arm710t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, 20087 {"arm720", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, 20088 {"arm720t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, 20089 {"arm740t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, 20090 {"arm710c", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, 20091 {"arm7100", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, 20092 {"arm7500", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, 20093 {"arm7500fe", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, 20094 {"arm7t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, 20095 {"arm7tdmi", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, 20096 {"arm7tdmi-s", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, 20097 {"arm8", ARM_ARCH_V4, FPU_ARCH_FPA, NULL}, 20098 {"arm810", ARM_ARCH_V4, FPU_ARCH_FPA, NULL}, 20099 {"strongarm", ARM_ARCH_V4, FPU_ARCH_FPA, NULL}, 20100 {"strongarm1", ARM_ARCH_V4, FPU_ARCH_FPA, NULL}, 20101 {"strongarm110", ARM_ARCH_V4, FPU_ARCH_FPA, NULL}, 20102 {"strongarm1100", ARM_ARCH_V4, FPU_ARCH_FPA, NULL}, 20103 {"strongarm1110", ARM_ARCH_V4, FPU_ARCH_FPA, NULL}, 20104 {"arm9", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, 20105 {"arm920", ARM_ARCH_V4T, FPU_ARCH_FPA, "ARM920T"}, 20106 {"arm920t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, 20107 {"arm922t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, 20108 {"arm940t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, 20109 {"arm9tdmi", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, 20110 /* For V5 or later processors we default to using VFP; but the user 20111 should really set the FPU type explicitly. */ 20112 {"arm9e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL}, 20113 {"arm9e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL}, 20114 {"arm926ej", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, "ARM926EJ-S"}, 20115 {"arm926ejs", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, "ARM926EJ-S"}, 20116 {"arm926ej-s", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, NULL}, 20117 {"arm946e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL}, 20118 {"arm946e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM946E-S"}, 20119 {"arm946e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL}, 20120 {"arm966e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL}, 20121 {"arm966e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM966E-S"}, 20122 {"arm966e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL}, 20123 {"arm968e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL}, 20124 {"arm10t", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL}, 20125 {"arm10tdmi", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL}, 20126 {"arm10e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL}, 20127 {"arm1020", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM1020E"}, 20128 {"arm1020t", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL}, 20129 {"arm1020e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL}, 20130 {"arm1022e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL}, 20131 {"arm1026ejs", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, "ARM1026EJ-S"}, 20132 {"arm1026ej-s", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, NULL}, 20133 {"arm1136js", ARM_ARCH_V6, FPU_NONE, "ARM1136J-S"}, 20134 {"arm1136j-s", ARM_ARCH_V6, FPU_NONE, NULL}, 20135 {"arm1136jfs", ARM_ARCH_V6, FPU_ARCH_VFP_V2, "ARM1136JF-S"}, 20136 {"arm1136jf-s", ARM_ARCH_V6, FPU_ARCH_VFP_V2, NULL}, 20137 {"mpcore", ARM_ARCH_V6K, FPU_ARCH_VFP_V2, NULL}, 20138 {"mpcorenovfp", ARM_ARCH_V6K, FPU_NONE, NULL}, 20139 {"arm1156t2-s", ARM_ARCH_V6T2, FPU_NONE, NULL}, 20140 {"arm1156t2f-s", ARM_ARCH_V6T2, FPU_ARCH_VFP_V2, NULL}, 20141 {"arm1176jz-s", ARM_ARCH_V6ZK, FPU_NONE, NULL}, 20142 {"arm1176jzf-s", ARM_ARCH_V6ZK, FPU_ARCH_VFP_V2, NULL}, 20143 {"cortex-a8", ARM_ARCH_V7A, ARM_FEATURE(0, FPU_VFP_V3 20144 | FPU_NEON_EXT_V1), 20145 NULL}, 20146 {"cortex-a9", ARM_ARCH_V7A, ARM_FEATURE(0, FPU_VFP_V3 20147 | FPU_NEON_EXT_V1), 20148 NULL}, 20149 {"cortex-r4", ARM_ARCH_V7R, FPU_NONE, NULL}, 20150 {"cortex-m3", ARM_ARCH_V7M, FPU_NONE, NULL}, 20151 /* ??? XSCALE is really an architecture. */ 20152 {"xscale", ARM_ARCH_XSCALE, FPU_ARCH_VFP_V2, NULL}, 20153 /* ??? iwmmxt is not a processor. */ 20154 {"iwmmxt", ARM_ARCH_IWMMXT, FPU_ARCH_VFP_V2, NULL}, 20155 {"iwmmxt2", ARM_ARCH_IWMMXT2,FPU_ARCH_VFP_V2, NULL}, 20156 {"i80200", ARM_ARCH_XSCALE, FPU_ARCH_VFP_V2, NULL}, 20157 /* Maverick */ 20158 {"ep9312", ARM_FEATURE(ARM_AEXT_V4T, ARM_CEXT_MAVERICK), FPU_ARCH_MAVERICK, "ARM920T"}, 20159 {NULL, ARM_ARCH_NONE, ARM_ARCH_NONE, NULL} 20160}; 20161 20162struct arm_arch_option_table 20163{ 20164 char *name; 20165 const arm_feature_set value; 20166 const arm_feature_set default_fpu; 20167}; 20168 20169/* This list should, at a minimum, contain all the architecture names 20170 recognized by GCC. */ 20171static const struct arm_arch_option_table arm_archs[] = 20172{ 20173 {"all", ARM_ANY, FPU_ARCH_FPA}, 20174 {"armv1", ARM_ARCH_V1, FPU_ARCH_FPA}, 20175 {"armv2", ARM_ARCH_V2, FPU_ARCH_FPA}, 20176 {"armv2a", ARM_ARCH_V2S, FPU_ARCH_FPA}, 20177 {"armv2s", ARM_ARCH_V2S, FPU_ARCH_FPA}, 20178 {"armv3", ARM_ARCH_V3, FPU_ARCH_FPA}, 20179 {"armv3m", ARM_ARCH_V3M, FPU_ARCH_FPA}, 20180 {"armv4", ARM_ARCH_V4, FPU_ARCH_FPA}, 20181 {"armv4xm", ARM_ARCH_V4xM, FPU_ARCH_FPA}, 20182 {"armv4t", ARM_ARCH_V4T, FPU_ARCH_FPA}, 20183 {"armv4txm", ARM_ARCH_V4TxM, FPU_ARCH_FPA}, 20184 {"armv5", ARM_ARCH_V5, FPU_ARCH_VFP}, 20185 {"armv5t", ARM_ARCH_V5T, FPU_ARCH_VFP}, 20186 {"armv5txm", ARM_ARCH_V5TxM, FPU_ARCH_VFP}, 20187 {"armv5te", ARM_ARCH_V5TE, FPU_ARCH_VFP}, 20188 {"armv5texp", ARM_ARCH_V5TExP, FPU_ARCH_VFP}, 20189 {"armv5tej", ARM_ARCH_V5TEJ, FPU_ARCH_VFP}, 20190 {"armv6", ARM_ARCH_V6, FPU_ARCH_VFP}, 20191 {"armv6j", ARM_ARCH_V6, FPU_ARCH_VFP}, 20192 {"armv6k", ARM_ARCH_V6K, FPU_ARCH_VFP}, 20193 {"armv6z", ARM_ARCH_V6Z, FPU_ARCH_VFP}, 20194 {"armv6zk", ARM_ARCH_V6ZK, FPU_ARCH_VFP}, 20195 {"armv6t2", ARM_ARCH_V6T2, FPU_ARCH_VFP}, 20196 {"armv6kt2", ARM_ARCH_V6KT2, FPU_ARCH_VFP}, 20197 {"armv6zt2", ARM_ARCH_V6ZT2, FPU_ARCH_VFP}, 20198 {"armv6zkt2", ARM_ARCH_V6ZKT2, FPU_ARCH_VFP}, 20199 {"armv7", ARM_ARCH_V7, FPU_ARCH_VFP}, 20200 /* The official spelling of the ARMv7 profile variants is the dashed form. 20201 Accept the non-dashed form for compatibility with old toolchains. */ 20202 {"armv7a", ARM_ARCH_V7A, FPU_ARCH_VFP}, 20203 {"armv7r", ARM_ARCH_V7R, FPU_ARCH_VFP}, 20204 {"armv7m", ARM_ARCH_V7M, FPU_ARCH_VFP}, 20205 {"armv7-a", ARM_ARCH_V7A, FPU_ARCH_VFP}, 20206 {"armv7-r", ARM_ARCH_V7R, FPU_ARCH_VFP}, 20207 {"armv7-m", ARM_ARCH_V7M, FPU_ARCH_VFP}, 20208 {"xscale", ARM_ARCH_XSCALE, FPU_ARCH_VFP}, 20209 {"iwmmxt", ARM_ARCH_IWMMXT, FPU_ARCH_VFP}, 20210 {"iwmmxt2", ARM_ARCH_IWMMXT2,FPU_ARCH_VFP}, 20211 {NULL, ARM_ARCH_NONE, ARM_ARCH_NONE} 20212}; 20213 20214/* ISA extensions in the co-processor space. */ 20215struct arm_option_cpu_value_table 20216{ 20217 char *name; 20218 const arm_feature_set value; 20219}; 20220 20221static const struct arm_option_cpu_value_table arm_extensions[] = 20222{ 20223 {"maverick", ARM_FEATURE (0, ARM_CEXT_MAVERICK)}, 20224 {"xscale", ARM_FEATURE (0, ARM_CEXT_XSCALE)}, 20225 {"iwmmxt", ARM_FEATURE (0, ARM_CEXT_IWMMXT)}, 20226 {"iwmmxt2", ARM_FEATURE (0, ARM_CEXT_IWMMXT2)}, 20227 {"sec", ARM_FEATURE (ARM_EXT_V6Z, 0)}, 20228 {NULL, ARM_ARCH_NONE} 20229}; 20230 20231/* This list should, at a minimum, contain all the fpu names 20232 recognized by GCC. */ 20233static const struct arm_option_cpu_value_table arm_fpus[] = 20234{ 20235 {"softfpa", FPU_NONE}, 20236 {"fpe", FPU_ARCH_FPE}, 20237 {"fpe2", FPU_ARCH_FPE}, 20238 {"fpe3", FPU_ARCH_FPA}, /* Third release supports LFM/SFM. */ 20239 {"fpa", FPU_ARCH_FPA}, 20240 {"fpa10", FPU_ARCH_FPA}, 20241 {"fpa11", FPU_ARCH_FPA}, 20242 {"arm7500fe", FPU_ARCH_FPA}, 20243 {"softvfp", FPU_ARCH_VFP}, 20244 {"softvfp+vfp", FPU_ARCH_VFP_V2}, 20245 {"vfp", FPU_ARCH_VFP_V2}, 20246 {"vfpv2", FPU_ARCH_VFP_V2}, 20247 {"vfp9", FPU_ARCH_VFP_V2}, 20248 {"vfp3", FPU_ARCH_VFP_V3}, 20249 {"vfpv3", FPU_ARCH_VFP_V3}, 20250 {"vfp10", FPU_ARCH_VFP_V2}, 20251 {"vfp10-r0", FPU_ARCH_VFP_V1}, 20252 {"vfpxd", FPU_ARCH_VFP_V1xD}, 20253 {"arm1020t", FPU_ARCH_VFP_V1}, 20254 {"arm1020e", FPU_ARCH_VFP_V2}, 20255 {"arm1136jfs", FPU_ARCH_VFP_V2}, 20256 {"arm1136jf-s", FPU_ARCH_VFP_V2}, 20257 {"maverick", FPU_ARCH_MAVERICK}, 20258 {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1}, 20259 {NULL, ARM_ARCH_NONE} 20260}; 20261 20262struct arm_option_value_table 20263{ 20264 char *name; 20265 long value; 20266}; 20267 20268static const struct arm_option_value_table arm_float_abis[] = 20269{ 20270 {"hard", ARM_FLOAT_ABI_HARD}, 20271 {"softfp", ARM_FLOAT_ABI_SOFTFP}, 20272 {"soft", ARM_FLOAT_ABI_SOFT}, 20273 {NULL, 0} 20274}; 20275 20276#ifdef OBJ_ELF 20277/* We only know how to output GNU and ver 4/5 (AAELF) formats. */ 20278static const struct arm_option_value_table arm_eabis[] = 20279{ 20280 {"gnu", EF_ARM_EABI_UNKNOWN}, 20281 {"4", EF_ARM_EABI_VER4}, 20282 {"5", EF_ARM_EABI_VER5}, 20283 {NULL, 0} 20284}; 20285#endif 20286 20287struct arm_long_option_table 20288{ 20289 char * option; /* Substring to match. */ 20290 char * help; /* Help information. */ 20291 int (* func) (char * subopt); /* Function to decode sub-option. */ 20292 char * deprecated; /* If non-null, print this message. */ 20293}; 20294 20295static int 20296arm_parse_extension (char * str, const arm_feature_set **opt_p) 20297{ 20298 arm_feature_set *ext_set = xmalloc (sizeof (arm_feature_set)); 20299 20300 /* Copy the feature set, so that we can modify it. */ 20301 *ext_set = **opt_p; 20302 *opt_p = ext_set; 20303 20304 while (str != NULL && *str != 0) 20305 { 20306 const struct arm_option_cpu_value_table * opt; 20307 char * ext; 20308 int optlen; 20309 20310 if (*str != '+') 20311 { 20312 as_bad (_("invalid architectural extension")); 20313 return 0; 20314 } 20315 20316 str++; 20317 ext = strchr (str, '+'); 20318 20319 if (ext != NULL) 20320 optlen = ext - str; 20321 else 20322 optlen = strlen (str); 20323 20324 if (optlen == 0) 20325 { 20326 as_bad (_("missing architectural extension")); 20327 return 0; 20328 } 20329 20330 for (opt = arm_extensions; opt->name != NULL; opt++) 20331 if (strncmp (opt->name, str, optlen) == 0) 20332 { 20333 ARM_MERGE_FEATURE_SETS (*ext_set, *ext_set, opt->value); 20334 break; 20335 } 20336 20337 if (opt->name == NULL) 20338 { 20339 as_bad (_("unknown architectural extnsion `%s'"), str); 20340 return 0; 20341 } 20342 20343 str = ext; 20344 }; 20345 20346 return 1; 20347} 20348 20349static int 20350arm_parse_cpu (char * str) 20351{ 20352 const struct arm_cpu_option_table * opt; 20353 char * ext = strchr (str, '+'); 20354 int optlen; 20355 20356 if (ext != NULL) 20357 optlen = ext - str; 20358 else 20359 optlen = strlen (str); 20360 20361 if (optlen == 0) 20362 { 20363 as_bad (_("missing cpu name `%s'"), str); 20364 return 0; 20365 } 20366 20367 for (opt = arm_cpus; opt->name != NULL; opt++) 20368 if (strncmp (opt->name, str, optlen) == 0) 20369 { 20370 mcpu_cpu_opt = &opt->value; 20371 mcpu_fpu_opt = &opt->default_fpu; 20372 if (opt->canonical_name) 20373 strcpy(selected_cpu_name, opt->canonical_name); 20374 else 20375 { 20376 int i; 20377 for (i = 0; i < optlen; i++) 20378 selected_cpu_name[i] = TOUPPER (opt->name[i]); 20379 selected_cpu_name[i] = 0; 20380 } 20381 20382 if (ext != NULL) 20383 return arm_parse_extension (ext, &mcpu_cpu_opt); 20384 20385 return 1; 20386 } 20387 20388 as_bad (_("unknown cpu `%s'"), str); 20389 return 0; 20390} 20391 20392static int 20393arm_parse_arch (char * str) 20394{ 20395 const struct arm_arch_option_table *opt; 20396 char *ext = strchr (str, '+'); 20397 int optlen; 20398 20399 if (ext != NULL) 20400 optlen = ext - str; 20401 else 20402 optlen = strlen (str); 20403 20404 if (optlen == 0) 20405 { 20406 as_bad (_("missing architecture name `%s'"), str); 20407 return 0; 20408 } 20409 20410 for (opt = arm_archs; opt->name != NULL; opt++) 20411 if (strncmp (opt->name, str, optlen) == 0) 20412 { 20413 march_cpu_opt = &opt->value; 20414 march_fpu_opt = &opt->default_fpu; 20415 strcpy(selected_cpu_name, opt->name); 20416 20417 if (ext != NULL) 20418 return arm_parse_extension (ext, &march_cpu_opt); 20419 20420 return 1; 20421 } 20422 20423 as_bad (_("unknown architecture `%s'\n"), str); 20424 return 0; 20425} 20426 20427static int 20428arm_parse_fpu (char * str) 20429{ 20430 const struct arm_option_cpu_value_table * opt; 20431 20432 for (opt = arm_fpus; opt->name != NULL; opt++) 20433 if (streq (opt->name, str)) 20434 { 20435 mfpu_opt = &opt->value; 20436 return 1; 20437 } 20438 20439 as_bad (_("unknown floating point format `%s'\n"), str); 20440 return 0; 20441} 20442 20443static int 20444arm_parse_float_abi (char * str) 20445{ 20446 const struct arm_option_value_table * opt; 20447 20448 for (opt = arm_float_abis; opt->name != NULL; opt++) 20449 if (streq (opt->name, str)) 20450 { 20451 mfloat_abi_opt = opt->value; 20452 return 1; 20453 } 20454 20455 as_bad (_("unknown floating point abi `%s'\n"), str); 20456 return 0; 20457} 20458 20459#ifdef OBJ_ELF 20460static int 20461arm_parse_eabi (char * str) 20462{ 20463 const struct arm_option_value_table *opt; 20464 20465 for (opt = arm_eabis; opt->name != NULL; opt++) 20466 if (streq (opt->name, str)) 20467 { 20468 meabi_flags = opt->value; 20469 return 1; 20470 } 20471 as_bad (_("unknown EABI `%s'\n"), str); 20472 return 0; 20473} 20474#endif 20475 20476struct arm_long_option_table arm_long_opts[] = 20477{ 20478 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"), 20479 arm_parse_cpu, NULL}, 20480 {"march=", N_("<arch name>\t assemble for architecture <arch name>"), 20481 arm_parse_arch, NULL}, 20482 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"), 20483 arm_parse_fpu, NULL}, 20484 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"), 20485 arm_parse_float_abi, NULL}, 20486#ifdef OBJ_ELF 20487 {"meabi=", N_("<ver>\t assemble for eabi version <ver>"), 20488 arm_parse_eabi, NULL}, 20489#endif 20490 {NULL, NULL, 0, NULL} 20491}; 20492 20493int 20494md_parse_option (int c, char * arg) 20495{ 20496 struct arm_option_table *opt; 20497 const struct arm_legacy_option_table *fopt; 20498 struct arm_long_option_table *lopt; 20499 20500 switch (c) 20501 { 20502#ifdef OPTION_EB 20503 case OPTION_EB: 20504 target_big_endian = 1; 20505 break; 20506#endif 20507 20508#ifdef OPTION_EL 20509 case OPTION_EL: 20510 target_big_endian = 0; 20511 break; 20512#endif 20513 20514 case 'a': 20515 /* Listing option. Just ignore these, we don't support additional 20516 ones. */ 20517 return 0; 20518 20519 default: 20520 for (opt = arm_opts; opt->option != NULL; opt++) 20521 { 20522 if (c == opt->option[0] 20523 && ((arg == NULL && opt->option[1] == 0) 20524 || streq (arg, opt->option + 1))) 20525 { 20526#if WARN_DEPRECATED 20527 /* If the option is deprecated, tell the user. */ 20528 if (opt->deprecated != NULL) 20529 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c, 20530 arg ? arg : "", _(opt->deprecated)); 20531#endif 20532 20533 if (opt->var != NULL) 20534 *opt->var = opt->value; 20535 20536 return 1; 20537 } 20538 } 20539 20540 for (fopt = arm_legacy_opts; fopt->option != NULL; fopt++) 20541 { 20542 if (c == fopt->option[0] 20543 && ((arg == NULL && fopt->option[1] == 0) 20544 || streq (arg, fopt->option + 1))) 20545 { 20546#if WARN_DEPRECATED 20547 /* If the option is deprecated, tell the user. */ 20548 if (fopt->deprecated != NULL) 20549 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c, 20550 arg ? arg : "", _(fopt->deprecated)); 20551#endif 20552 20553 if (fopt->var != NULL) 20554 *fopt->var = &fopt->value; 20555 20556 return 1; 20557 } 20558 } 20559 20560 for (lopt = arm_long_opts; lopt->option != NULL; lopt++) 20561 { 20562 /* These options are expected to have an argument. */ 20563 if (c == lopt->option[0] 20564 && arg != NULL 20565 && strncmp (arg, lopt->option + 1, 20566 strlen (lopt->option + 1)) == 0) 20567 { 20568#if WARN_DEPRECATED 20569 /* If the option is deprecated, tell the user. */ 20570 if (lopt->deprecated != NULL) 20571 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c, arg, 20572 _(lopt->deprecated)); 20573#endif 20574 20575 /* Call the sup-option parser. */ 20576 return lopt->func (arg + strlen (lopt->option) - 1); 20577 } 20578 } 20579 20580 return 0; 20581 } 20582 20583 return 1; 20584} 20585 20586void 20587md_show_usage (FILE * fp) 20588{ 20589 struct arm_option_table *opt; 20590 struct arm_long_option_table *lopt; 20591 20592 fprintf (fp, _(" ARM-specific assembler options:\n")); 20593 20594 for (opt = arm_opts; opt->option != NULL; opt++) 20595 if (opt->help != NULL) 20596 fprintf (fp, " -%-23s%s\n", opt->option, _(opt->help)); 20597 20598 for (lopt = arm_long_opts; lopt->option != NULL; lopt++) 20599 if (lopt->help != NULL) 20600 fprintf (fp, " -%s%s\n", lopt->option, _(lopt->help)); 20601 20602#ifdef OPTION_EB 20603 fprintf (fp, _("\ 20604 -EB assemble code for a big-endian cpu\n")); 20605#endif 20606 20607#ifdef OPTION_EL 20608 fprintf (fp, _("\ 20609 -EL assemble code for a little-endian cpu\n")); 20610#endif 20611} 20612 20613 20614#ifdef OBJ_ELF 20615typedef struct 20616{ 20617 int val; 20618 arm_feature_set flags; 20619} cpu_arch_ver_table; 20620 20621/* Mapping from CPU features to EABI CPU arch values. Table must be sorted 20622 least features first. */ 20623static const cpu_arch_ver_table cpu_arch_ver[] = 20624{ 20625 {1, ARM_ARCH_V4}, 20626 {2, ARM_ARCH_V4T}, 20627 {3, ARM_ARCH_V5}, 20628 {4, ARM_ARCH_V5TE}, 20629 {5, ARM_ARCH_V5TEJ}, 20630 {6, ARM_ARCH_V6}, 20631 {7, ARM_ARCH_V6Z}, 20632 {8, ARM_ARCH_V6K}, 20633 {9, ARM_ARCH_V6T2}, 20634 {10, ARM_ARCH_V7A}, 20635 {10, ARM_ARCH_V7R}, 20636 {10, ARM_ARCH_V7M}, 20637 {0, ARM_ARCH_NONE} 20638}; 20639 20640/* Set the public EABI object attributes. */ 20641static void 20642aeabi_set_public_attributes (void) 20643{ 20644 int arch; 20645 arm_feature_set flags; 20646 arm_feature_set tmp; 20647 const cpu_arch_ver_table *p; 20648 20649 /* Choose the architecture based on the capabilities of the requested cpu 20650 (if any) and/or the instructions actually used. */ 20651 ARM_MERGE_FEATURE_SETS (flags, arm_arch_used, thumb_arch_used); 20652 ARM_MERGE_FEATURE_SETS (flags, flags, *mfpu_opt); 20653 ARM_MERGE_FEATURE_SETS (flags, flags, selected_cpu); 20654 /*Allow the user to override the reported architecture. */ 20655 if (object_arch) 20656 { 20657 ARM_CLEAR_FEATURE (flags, flags, arm_arch_any); 20658 ARM_MERGE_FEATURE_SETS (flags, flags, *object_arch); 20659 } 20660 20661 tmp = flags; 20662 arch = 0; 20663 for (p = cpu_arch_ver; p->val; p++) 20664 { 20665 if (ARM_CPU_HAS_FEATURE (tmp, p->flags)) 20666 { 20667 arch = p->val; 20668 ARM_CLEAR_FEATURE (tmp, tmp, p->flags); 20669 } 20670 } 20671 20672 /* Tag_CPU_name. */ 20673 if (selected_cpu_name[0]) 20674 { 20675 char *p; 20676 20677 p = selected_cpu_name; 20678 if (strncmp(p, "armv", 4) == 0) 20679 { 20680 int i; 20681 20682 p += 4; 20683 for (i = 0; p[i]; i++) 20684 p[i] = TOUPPER (p[i]); 20685 } 20686 bfd_elf_add_proc_attr_string (stdoutput, 5, p); 20687 } 20688 /* Tag_CPU_arch. */ 20689 bfd_elf_add_proc_attr_int (stdoutput, 6, arch); 20690 /* Tag_CPU_arch_profile. */ 20691 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v7a)) 20692 bfd_elf_add_proc_attr_int (stdoutput, 7, 'A'); 20693 else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v7r)) 20694 bfd_elf_add_proc_attr_int (stdoutput, 7, 'R'); 20695 else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v7m)) 20696 bfd_elf_add_proc_attr_int (stdoutput, 7, 'M'); 20697 /* Tag_ARM_ISA_use. */ 20698 if (ARM_CPU_HAS_FEATURE (arm_arch_used, arm_arch_full)) 20699 bfd_elf_add_proc_attr_int (stdoutput, 8, 1); 20700 /* Tag_THUMB_ISA_use. */ 20701 if (ARM_CPU_HAS_FEATURE (thumb_arch_used, arm_arch_full)) 20702 bfd_elf_add_proc_attr_int (stdoutput, 9, 20703 ARM_CPU_HAS_FEATURE (thumb_arch_used, arm_arch_t2) ? 2 : 1); 20704 /* Tag_VFP_arch. */ 20705 if (ARM_CPU_HAS_FEATURE (thumb_arch_used, fpu_vfp_ext_v3) 20706 || ARM_CPU_HAS_FEATURE (arm_arch_used, fpu_vfp_ext_v3)) 20707 bfd_elf_add_proc_attr_int (stdoutput, 10, 3); 20708 else if (ARM_CPU_HAS_FEATURE (thumb_arch_used, fpu_vfp_ext_v2) 20709 || ARM_CPU_HAS_FEATURE (arm_arch_used, fpu_vfp_ext_v2)) 20710 bfd_elf_add_proc_attr_int (stdoutput, 10, 2); 20711 else if (ARM_CPU_HAS_FEATURE (thumb_arch_used, fpu_vfp_ext_v1) 20712 || ARM_CPU_HAS_FEATURE (arm_arch_used, fpu_vfp_ext_v1) 20713 || ARM_CPU_HAS_FEATURE (thumb_arch_used, fpu_vfp_ext_v1xd) 20714 || ARM_CPU_HAS_FEATURE (arm_arch_used, fpu_vfp_ext_v1xd)) 20715 bfd_elf_add_proc_attr_int (stdoutput, 10, 1); 20716 /* Tag_WMMX_arch. */ 20717 if (ARM_CPU_HAS_FEATURE (thumb_arch_used, arm_cext_iwmmxt) 20718 || ARM_CPU_HAS_FEATURE (arm_arch_used, arm_cext_iwmmxt)) 20719 bfd_elf_add_proc_attr_int (stdoutput, 11, 1); 20720 /* Tag_NEON_arch. */ 20721 if (ARM_CPU_HAS_FEATURE (thumb_arch_used, fpu_neon_ext_v1) 20722 || ARM_CPU_HAS_FEATURE (arm_arch_used, fpu_neon_ext_v1)) 20723 bfd_elf_add_proc_attr_int (stdoutput, 12, 1); 20724} 20725 20726/* Add the default contents for the .ARM.attributes section. */ 20727void 20728arm_md_end (void) 20729{ 20730 if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4) 20731 return; 20732 20733 aeabi_set_public_attributes (); 20734} 20735#endif /* OBJ_ELF */ 20736 20737 20738/* Parse a .cpu directive. */ 20739 20740static void 20741s_arm_cpu (int ignored ATTRIBUTE_UNUSED) 20742{ 20743 const struct arm_cpu_option_table *opt; 20744 char *name; 20745 char saved_char; 20746 20747 name = input_line_pointer; 20748 while (*input_line_pointer && !ISSPACE(*input_line_pointer)) 20749 input_line_pointer++; 20750 saved_char = *input_line_pointer; 20751 *input_line_pointer = 0; 20752 20753 /* Skip the first "all" entry. */ 20754 for (opt = arm_cpus + 1; opt->name != NULL; opt++) 20755 if (streq (opt->name, name)) 20756 { 20757 mcpu_cpu_opt = &opt->value; 20758 selected_cpu = opt->value; 20759 if (opt->canonical_name) 20760 strcpy(selected_cpu_name, opt->canonical_name); 20761 else 20762 { 20763 int i; 20764 for (i = 0; opt->name[i]; i++) 20765 selected_cpu_name[i] = TOUPPER (opt->name[i]); 20766 selected_cpu_name[i] = 0; 20767 } 20768 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt); 20769 *input_line_pointer = saved_char; 20770 demand_empty_rest_of_line (); 20771 return; 20772 } 20773 as_bad (_("unknown cpu `%s'"), name); 20774 *input_line_pointer = saved_char; 20775 ignore_rest_of_line (); 20776} 20777 20778 20779/* Parse a .arch directive. */ 20780 20781static void 20782s_arm_arch (int ignored ATTRIBUTE_UNUSED) 20783{ 20784 const struct arm_arch_option_table *opt; 20785 char saved_char; 20786 char *name; 20787 20788 name = input_line_pointer; 20789 while (*input_line_pointer && !ISSPACE(*input_line_pointer)) 20790 input_line_pointer++; 20791 saved_char = *input_line_pointer; 20792 *input_line_pointer = 0; 20793 20794 /* Skip the first "all" entry. */ 20795 for (opt = arm_archs + 1; opt->name != NULL; opt++) 20796 if (streq (opt->name, name)) 20797 { 20798 mcpu_cpu_opt = &opt->value; 20799 selected_cpu = opt->value; 20800 strcpy(selected_cpu_name, opt->name); 20801 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt); 20802 *input_line_pointer = saved_char; 20803 demand_empty_rest_of_line (); 20804 return; 20805 } 20806 20807 as_bad (_("unknown architecture `%s'\n"), name); 20808 *input_line_pointer = saved_char; 20809 ignore_rest_of_line (); 20810} 20811 20812/* Parse a .arch_extension directive. */ 20813 20814static void 20815s_arm_arch_extension (int ignored ATTRIBUTE_UNUSED) 20816{ 20817 const struct arm_option_cpu_value_table *opt; 20818 char saved_char; 20819 char *name; 20820 20821 name = input_line_pointer; 20822 while (*input_line_pointer && !ISSPACE(*input_line_pointer)) 20823 input_line_pointer++; 20824 saved_char = *input_line_pointer; 20825 *input_line_pointer = 0; 20826 20827 for (opt = arm_extensions; opt->name != NULL; opt++) 20828 if (streq (opt->name, name)) 20829 { 20830 ARM_MERGE_FEATURE_SETS (cpu_variant, cpu_variant, opt->value); 20831 *input_line_pointer = saved_char; 20832 demand_empty_rest_of_line (); 20833 return; 20834 } 20835 20836 as_bad (_("unknown architecture `%s'\n"), name); 20837 *input_line_pointer = saved_char; 20838 ignore_rest_of_line (); 20839} 20840 20841/* Parse a .object_arch directive. */ 20842 20843static void 20844s_arm_object_arch (int ignored ATTRIBUTE_UNUSED) 20845{ 20846 const struct arm_arch_option_table *opt; 20847 char saved_char; 20848 char *name; 20849 20850 name = input_line_pointer; 20851 while (*input_line_pointer && !ISSPACE(*input_line_pointer)) 20852 input_line_pointer++; 20853 saved_char = *input_line_pointer; 20854 *input_line_pointer = 0; 20855 20856 /* Skip the first "all" entry. */ 20857 for (opt = arm_archs + 1; opt->name != NULL; opt++) 20858 if (streq (opt->name, name)) 20859 { 20860 object_arch = &opt->value; 20861 *input_line_pointer = saved_char; 20862 demand_empty_rest_of_line (); 20863 return; 20864 } 20865 20866 as_bad (_("unknown architecture `%s'\n"), name); 20867 *input_line_pointer = saved_char; 20868 ignore_rest_of_line (); 20869} 20870 20871 20872/* Parse a .fpu directive. */ 20873 20874static void 20875s_arm_fpu (int ignored ATTRIBUTE_UNUSED) 20876{ 20877 const struct arm_option_cpu_value_table *opt; 20878 char saved_char; 20879 char *name; 20880 20881 name = input_line_pointer; 20882 while (*input_line_pointer && !ISSPACE(*input_line_pointer)) 20883 input_line_pointer++; 20884 saved_char = *input_line_pointer; 20885 *input_line_pointer = 0; 20886 20887 for (opt = arm_fpus; opt->name != NULL; opt++) 20888 if (streq (opt->name, name)) 20889 { 20890 mfpu_opt = &opt->value; 20891 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt); 20892 *input_line_pointer = saved_char; 20893 demand_empty_rest_of_line (); 20894 return; 20895 } 20896 20897 as_bad (_("unknown floating point format `%s'\n"), name); 20898 *input_line_pointer = saved_char; 20899 ignore_rest_of_line (); 20900} 20901 20902/* Copy symbol information. */ 20903void 20904arm_copy_symbol_attributes (symbolS *dest, symbolS *src) 20905{ 20906 ARM_GET_FLAG (dest) = ARM_GET_FLAG (src); 20907} 20908