Instruction/ARM/EmulateInstructionARM.cpp

1177     uint32_t Rd; // the destination register
1181       Rd = 7;
1185       Rd = Bits32(opcode, 15, 12);
1195     if (Rd == GetFramePointerRegisterNumber())
1203     if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_r0 + Rd,
1238     uint32_t Rd; // the destination register
1241       Rd = 7;
1244       Rd = 12;
1251     if (Rd == GetFramePointerRegisterNumber())
1259     if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_r0 + Rd, sp))
1298     uint32_t Rd; // the destination register
1302       Rd = Bit32(opcode, 7) << 3 | Bits32(opcode, 2, 0);
1305       if (Rd == 15 && InITBlock() && !LastInITBlock())
1309       Rd = Bits32(opcode, 2, 0);
1316       Rd = Bits32(opcode, 11, 8);
1320       if (setflags && (BadReg(Rd) || BadReg(Rm)))
1324       if (!setflags && (Rd == 15 || Rm == 15 || (Rd == 13 && Rm == 13)))
1328       Rd = Bits32(opcode, 15, 12);
1332       // if Rd == '1111' && S == '1' then SEE SUBS PC, LR and related
1334       if (Rd == 15 && setflags)
1344     // The context specifies that Rm is to be moved into Rd.
1346     if (Rd == 13)
1348     else if (Rd == GetFramePointerRegisterNumber() && Rm == 13)
1356     if (!WriteCoreRegOptionalFlags(context, result, Rd, setflags))
1386     uint32_t Rd;    // the destination register
1387     uint32_t imm32; // the immediate value to be written to Rd
1395       Rd = Bits32(opcode, 10, 8);
1403       Rd = Bits32(opcode, 11, 8);
1406       if (BadReg(Rd))
1412       // d = UInt(Rd); setflags = FALSE; imm32 = ZeroExtend(imm4:i:imm3:imm8,
1414       Rd = Bits32(opcode, 11, 8);
1423       if (BadReg(Rd))
1428       // d = UInt(Rd); setflags = (S == '1'); (imm32, carry) =
1430       Rd = Bits32(opcode, 15, 12);
1434       // if Rd == '1111' && S == '1' then SEE SUBS PC, LR and related
1436       if ((Rd == 15) && setflags)
1442       // d = UInt(Rd); setflags = FALSE; imm32 = ZeroExtend(imm4:imm12, 32);
1443       Rd = Bits32(opcode, 15, 12);
1450       if (Rd == 15)
1459     // The context specifies that an immediate is to be moved into Rd.
1464     if (!WriteCoreRegOptionalFlags(context, result, Rd, setflags, carry))
1518       // d = UInt(Rd); n = UInt(Rn); m = UInt(Rm); setflags = FALSE;
1531       // d = UInt(Rd); n = UInt(Rn); m = UInt(Rm); setflags = (S == '1');
1628     uint32_t Rd;    // the destination register
1634       Rd = Bits32(opcode, 11, 8);
1639       Rd = Bits32(opcode, 15, 12);
1643       // if Rd == '1111' && S == '1' then SEE SUBS PC, LR and related
1645       if (Rd == 15 && setflags)
1653     // The context specifies that an immediate is to be moved into Rd.
1658     if (!WriteCoreRegOptionalFlags(context, result, Rd, setflags, carry))
1690     uint32_t Rd; // the destination register
1697       Rd = Bits32(opcode, 2, 0);
1706       Rd = Bits32(opcode, 11, 8);
1711       if (BadReg(Rd) || BadReg(Rm))
1715       Rd = Bits32(opcode, 15, 12);
1734     // The context specifies that an immediate is to be moved into Rd.
1739     if (!WriteCoreRegOptionalFlags(context, result, Rd, setflags, carry))
1867       // d = UInt(Rd); setflags = FALSE; imm32 = ZeroExtend(imm8:'00', 32);
1881       // d = UInt(Rd); setflags = (S == "1"); imm32 =
1887       // if Rd == "1111" && S == "1" then SEE CMN (immediate);
1898       // d = UInt(Rd); setflags = FALSE; imm32 = ZeroExtend(i:imm3:imm8, 32);
2379 // If Rd == 13 => A sub operation to adjust the SP -- allocate space for local
2407     uint32_t Rd;
2412       Rd = 13;
2417       Rd = Bits32(opcode, 11, 8);
2420       if (Rd == 15 && setflags)
2422       if (Rd == 15 && !setflags)
2426       Rd = Bits32(opcode, 11, 8);
2429       if (Rd == 15)
2433       Rd = Bits32(opcode, 15, 12);
2437       // if Rd == '1111' && S == '1' then SEE SUBS PC, LR and related
2439       if (Rd == 15 && setflags)
2448     if (Rd == 13) {
2459     if (!WriteCoreRegOptionalFlags(context, res.result, Rd, setflags,
3048       // d = UInt(Rd); n = UInt(Rn); setflags = !InITBlock(); imm32 =
3068       // if Rd == '1111' && S == '1' then SEE CMN (immediate);
3069       // d = UInt(Rd); n = UInt(Rn); setflags = (S == '1'); imm32 =
3088       // d = UInt(Rd); n = UInt(Rn); setflags = FALSE; imm32 =
3165     uint32_t Rd, Rn;
3171       Rd = Bits32(opcode, 15, 12);
3188     if (Rd == 13)
3190     else if (Rd == GetFramePointerRegisterNumber())
3199     if (!WriteCoreRegOptionalFlags(context, res.result, Rd, setflags,
3231     uint32_t Rd, Rn, Rm;
3237       Rd = Bits32(opcode, 2, 0);
3245       Rd = Rn = Bit32(opcode, 7) << 3 | Bits32(opcode, 2, 0);
3252       if (Rd == 15 && InITBlock() && !LastInITBlock())
3256       Rd = Bits32(opcode, 15, 12);
3289     if (!WriteCoreRegOptionalFlags(context, res.result, Rd, setflags,
3766     uint32_t Rd;    // the destination register
3788       Rd = Bits32(opcode, 2, 0);
3799       Rd = Bits32(opcode, 11, 8);
3803       if (BadReg(Rd) || BadReg(Rm))
3807       Rd = Bits32(opcode, 15, 12);
3833     // The context specifies that an immediate is to be moved into Rd.
3838     if (!WriteCoreRegOptionalFlags(context, result, Rd, setflags, carry))
3855     uint32_t Rd; // the destination register
3863       Rd = Bits32(opcode, 2, 0);
3864       Rn = Rd;
3869       Rd = Bits32(opcode, 11, 8);
3873       if (BadReg(Rd) || BadReg(Rn) || BadReg(Rm))
3877       Rd = Bits32(opcode, 15, 12);
3881       if (Rd == 15 || Rn == 15 || Rm == 15)
3904     // The context specifies that an immediate is to be moved into Rd.
3909     if (!WriteCoreRegOptionalFlags(context, result, Rd, setflags, carry))
5830     uint32_t Rd, Rn;
5836       Rd = Bits32(opcode, 11, 8);
5840       if (BadReg(Rd) || BadReg(Rn))
5844       Rd = Bits32(opcode, 15, 12);
5849       if (Rd == 15 && setflags)
5867     if (!WriteCoreRegOptionalFlags(context, res.result, Rd, setflags,
5900     uint32_t Rd, Rn, Rm;
5906       Rd = Rn = Bits32(opcode, 2, 0);
5913       Rd = Bits32(opcode, 11, 8);
5918       if (BadReg(Rd) || BadReg(Rn) || BadReg(Rm))
5922       Rd = Bits32(opcode, 15, 12);
5928       if (Rd == 15 && setflags)
5954     if (!WriteCoreRegOptionalFlags(context, res.result, Rd, setflags,
5979     uint32_t Rd;
5984       Rd = Bits32(opcode, 10, 8);
5990       Rd = Bits32(opcode, 11, 8);
5993       if (BadReg(Rd))
5998       Rd = Bits32(opcode, 15, 12);
6017     if (!WriteCoreReg(context, result, Rd))
6047     uint32_t Rd, Rn;
6054       Rd = Bits32(opcode, 11, 8);
6060       // if Rd == '1111' && S == '1' then SEE TST (immediate);
6061       if (Rd == 15 && setflags)
6063       if (Rd == 13 || (Rd == 15 && !setflags) || BadReg(Rn))
6067       Rd = Bits32(opcode, 15, 12);
6074       if (Rd == 15 && setflags)
6092     if (!WriteCoreRegOptionalFlags(context, result, Rd, setflags, carry))
6123     uint32_t Rd, Rn, Rm;
6130       Rd = Rn = Bits32(opcode, 2, 0);
6137       Rd = Bits32(opcode, 11, 8);
6142       // if Rd == '1111' && S == '1' then SEE TST (register);
6143       if (Rd == 15 && setflags)
6145       if (Rd == 13 || (Rd == 15 && !setflags) || BadReg(Rn) || BadReg(Rm))
6149       Rd = Bits32(opcode, 15, 12);
6155       if (Rd == 15 && setflags)
6181     if (!WriteCoreRegOptionalFlags(context, result, Rd, setflags, carry))
6212     uint32_t Rd, Rn;
6219       Rd = Bits32(opcode, 11, 8);
6225       if (BadReg(Rd) || BadReg(Rn))
6229       Rd = Bits32(opcode, 15, 12);
6236       // if Rd == '1111' && S == '1' then SEE SUBS PC, LR and related
6238       if (Rd == 15 && setflags)
6256     if (!WriteCoreRegOptionalFlags(context, result, Rd, setflags, carry))
6288     uint32_t Rd, Rn, Rm;
6295       Rd = Rn = Bits32(opcode, 2, 0);
6302       Rd = Bits32(opcode, 11, 8);
6307       if (BadReg(Rd) || BadReg(Rn) || BadReg(Rm))
6311       Rd = Bits32(opcode, 15, 12);
6317       // if Rd == '1111' && S == '1' then SEE SUBS PC, LR and related
6319       if (Rd == 15 && setflags)
6345     if (!WriteCoreRegOptionalFlags(context, result, Rd, setflags, carry))
8372       // d = UInt(Rd); m = UInt(Rm); rotation = 0;
8380       // d = UInt(Rd); m = UInt(Rm); rotation = UInt(rotate:'000');
8392       // d = UInt(Rd); m = UInt(Rm); rotation = UInt(rotate:'000');
8457       // d = UInt(Rd); m = UInt(Rm); rotation = 0;
8465       // d = UInt(Rd); m = UInt(Rm); rotation = UInt(rotate:'000');
8477       // d = UInt(Rd); m = UInt(Rm); rotation = UInt(rotate:'000');
8542       // d = UInt(Rd); m = UInt(Rm); rotation = 0;
8550       // d = UInt(Rd); m = UInt(Rm); rotation = UInt(rotate:'000');
8562       // d = UInt(Rd); m = UInt(Rm); rotation = UInt(rotate:'000');
8624       // d = UInt(Rd); m = UInt(Rm); rotation = 0;
8632       // d = UInt(Rd); m = UInt(Rm); rotation = UInt(rotate:'000');
8644       // d = UInt(Rd); m = UInt(Rm); rotation = UInt(rotate:'000');
8854     uint32_t Rd, Rn;
8861       Rd = Bits32(opcode, 11, 8);
8867       // if Rd == '1111' && S == '1' then SEE TEQ (immediate);
8868       if (Rd == 15 && setflags)
8870       if (Rd == 13 || (Rd == 15 && !setflags) || BadReg(Rn))
8874       Rd = Bits32(opcode, 15, 12);
8881       // if Rd == '1111' && S == '1' then SEE SUBS PC, LR and related
8883       if (Rd == 15 && setflags)
8901     if (!WriteCoreRegOptionalFlags(context, result, Rd, setflags, carry))
8933     uint32_t Rd, Rn, Rm;
8940       Rd = Rn = Bits32(opcode, 2, 0);
8947       Rd = Bits32(opcode, 11, 8);
8952       // if Rd == '1111' && S == '1' then SEE TEQ (register);
8953       if (Rd == 15 && setflags)
8955       if (Rd == 13 || (Rd == 15 && !setflags) || BadReg(Rn) || BadReg(Rm))
8959       Rd = Bits32(opcode, 15, 12);
8965       // if Rd == '1111' && S == '1' then SEE SUBS PC, LR and related
8967       if (Rd == 15 && setflags)
8993     if (!WriteCoreRegOptionalFlags(context, result, Rd, setflags, carry))
9023     uint32_t Rd, Rn;
9030       Rd = Bits32(opcode, 11, 8);
9039       if (BadReg(Rd) || Rn == 13)
9043       Rd = Bits32(opcode, 15, 12);
9050       if (Rd == 15 && setflags)
9068     if (!WriteCoreRegOptionalFlags(context, result, Rd, setflags, carry))
9100     uint32_t Rd, Rn, Rm;
9107       Rd = Rn = Bits32(opcode, 2, 0);
9114       Rd = Bits32(opcode, 11, 8);
9122       if (BadReg(Rd) || Rn == 13 || BadReg(Rm))
9126       Rd = Bits32(opcode, 15, 12);
9132       if (Rd == 15 && setflags)
9158     if (!WriteCoreRegOptionalFlags(context, result, Rd, setflags, carry))
9187   uint32_t Rd; // the destination register
9194     Rd = Bits32(opcode, 2, 0);
9200     Rd = Bits32(opcode, 11, 8);
9204     if (BadReg(Rd) || BadReg(Rn))
9208     Rd = Bits32(opcode, 15, 12);
9213     // if Rd == '1111' && S == '1' then SEE SUBS PC, LR and related
9215     if (Rd == 15 && setflags)
9232   return WriteCoreRegOptionalFlags(context, res.result, Rd, setflags,
9260   uint32_t Rd; // the destination register
9268     Rd = Bits32(opcode, 11, 8);
9274     if (BadReg(Rd) || BadReg(Rn) || BadReg(Rm))
9278     Rd = Bits32(opcode, 15, 12);
9284     // if Rd == '1111' && S == '1' then SEE SUBS PC, LR and related
9286     if (Rd == 15 && setflags)
9310   return WriteCoreRegOptionalFlags(context, res.result, Rd, setflags,
9338   uint32_t Rd; // the destination register
9345     Rd = Bits32(opcode, 15, 12);
9350     // if Rd == '1111' && S == '1' then SEE SUBS PC, LR and related
9352     if (Rd == 15 && setflags)
9369   return WriteCoreRegOptionalFlags(context, res.result, Rd, setflags,
9398   uint32_t Rd; // the destination register
9406     Rd = Bits32(opcode, 15, 12);
9412     // if Rd == '1111' && S == '1' then SEE SUBS PC, LR and related
9414     if (Rd == 15 && setflags)
9438   return WriteCoreRegOptionalFlags(context, res.result, Rd, setflags,
9467   uint32_t Rd; // the destination register
9474     Rd = Bits32(opcode, 11, 8);
9478     if (BadReg(Rd) || BadReg(Rn))
9482     Rd = Bits32(opcode, 15, 12);
9487     // if Rd == '1111' && S == '1' then SEE SUBS PC, LR and related
9489     if (Rd == 15 && setflags)
9506   return WriteCoreRegOptionalFlags(context, res.result, Rd, setflags,
9536   uint32_t Rd; // the destination register
9544     Rd = Rn = Bits32(opcode, 2, 0);
9551     Rd = Bits32(opcode, 11, 8);
9556     if (BadReg(Rd) || BadReg(Rn) || BadReg(Rm))
9560     Rd = Bits32(opcode, 15, 12);
9566     // if Rd == '1111' && S == '1' then SEE SUBS PC, LR and related
9568     if (Rd == 15 && setflags)
9592   return WriteCoreRegOptionalFlags(context, res.result, Rd, setflags,
9616   uint32_t Rd; // the destination register
9623     Rd = Bits32(opcode, 2, 0);
9629     Rd = Rn = Bits32(opcode, 10, 8);
9634     Rd = Bits32(opcode, 11, 8);
9639     // if Rd == '1111' && S == '1' then SEE CMP (immediate);
9640     if (Rd == 15 && setflags)
9648     if (Rd == 13 || (Rd == 15 && !setflags) || Rn == 15)
9652     Rd = Bits32(opcode, 11, 8);
9665     if (BadReg(Rd))
9682   return WriteCoreRegOptionalFlags(context, res.result, Rd, setflags,
9710     uint32_t Rd; // the destination register
9717       Rd = Bits32(opcode, 15, 12);
9730       // if Rd == '1111' && S == '1' then SEE SUBS PC, LR and related
9732       if (Rd == 15 && setflags)
9746     if (Rd == 13)
9756     if (!WriteCoreRegOptionalFlags(context, res.result, Rd, setflags,
10049       // d = UInt(Rd); m = UInt(Rm); setflags = (S == '1');
10068       // d = UInt(Rd); m = UInt(Rm); setflags = (S == '1');
10073       // if Rd == '1111' && S == '1' then SEE SUBS PC, LR and related
10146       // d = UInt(Rd); n = UInt(Rn); m = UInt(Rm); s = UInt(Rs);
10244       // d = UInt(Rd); n = UInt(Rn); m = UInt(Rm); setflags = !InITBlock();
10257       // d = UInt(Rd); n = UInt(Rn); m = UInt(Rm); setflags = (S =="1");
10263       // if Rd == "1111" && S == "1" then SEE CMP (register);
10284       // d = UInt(Rd); n = UInt(Rn); m = UInt(Rm); setflags = (S == '1');
10290       // if Rd == '1111' && S == '1' then SEE SUBS PC, LR and related
10372       // d = UInt(Rd); t = UInt(Rt); n = UInt(Rn); imm32 =
10391       // d = UInt(Rd); t = UInt(Rt); n = UInt(Rn); imm32 = Zeros(32); // Zero
12881        "sub{s}<c> <Rd>, sp, <Rm>{,<shift>}"},
12930        &EmulateInstructionARM::EmulateADCImm, "adc{s}<c> <Rd>, <Rn>, #const"},
12934        "adc{s}<c> <Rd>, <Rn>, <Rm> {,<shift>}"},
12938        "add{s}<c> <Rd>, <Rn>, #const"},
12942        "add{s}<c> <Rd>, <Rn>, <Rm> {,<shift>}"},
12946        "add{s}<c> <Rd>, <Rn>, <Rm>, <type> <RS>"},
12949        &EmulateInstructionARM::EmulateADR, "add<c> <Rd>, PC, #<const>"},
12951        &EmulateInstructionARM::EmulateADR, "sub<c> <Rd>, PC, #<const>"},
12954        &EmulateInstructionARM::EmulateANDImm, "and{s}<c> <Rd>, <Rn>, #const"},
12958        "and{s}<c> <Rd>, <Rn>, <Rm> {,<shift>}"},
12961        &EmulateInstructionARM::EmulateBICImm, "bic{s}<c> <Rd>, <Rn>, #const"},
12965        "bic{s}<c> <Rd>, <Rn>, <Rm> {,<shift>}"},
12968        &EmulateInstructionARM::EmulateEORImm, "eor{s}<c> <Rd>, <Rn>, #const"},
12972        "eor{s}<c> <Rd>, <Rn>, <Rm> {,<shift>}"},
12975        &EmulateInstructionARM::EmulateORRImm, "orr{s}<c> <Rd>, <Rn>, #const"},
12979        "orr{s}<c> <Rd>, <Rn>, <Rm> {,<shift>}"},
12982        &EmulateInstructionARM::EmulateRSBImm, "rsb{s}<c> <Rd>, <Rn>, #<const>"},
12986        "rsb{s}<c> <Rd>, <Rn>, <Rm> {,<shift>}"},
12989        &EmulateInstructionARM::EmulateRSCImm, "rsc{s}<c> <Rd>, <Rn>, #<const>"},
12993        "rsc{s}<c> <Rd>, <Rn>, <Rm> {,<shift>}"},
12996        &EmulateInstructionARM::EmulateSBCImm, "sbc{s}<c> <Rd>, <Rn>, #<const>"},
13000        "sbc{s}<c> <Rd>, <Rn>, <Rm> {,<shift>}"},
13004        "sub{s}<c> <Rd>, <Rn>, #<const>"},
13007        &EmulateInstructionARM::EmulateSUBSPImm, "sub{s}<c> <Rd>, sp, #<const>"},
13011        "sub{s}<c> <Rd>, <Rn>, <Rm>{,<shift>}"},
13027        &EmulateInstructionARM::EmulateMOVRdImm, "mov{s}<c> <Rd>, #<const>"},
13029        &EmulateInstructionARM::EmulateMOVRdImm, "movw<c> <Rd>, #<imm16>"},
13032        &EmulateInstructionARM::EmulateMOVRdRm, "mov{s}<c> <Rd>, <Rm>"},
13035        &EmulateInstructionARM::EmulateMVNImm, "mvn{s}<c> <Rd>, #<const>"},
13039        "mvn{s}<c> <Rd>, <Rm> {,<shift>}"},
13054        &EmulateInstructionARM::EmulateASRImm, "asr{s}<c> <Rd>, <Rm>, #imm"},
13057        &EmulateInstructionARM::EmulateASRReg, "asr{s}<c> <Rd>, <Rn>, <Rm>"},
13060        &EmulateInstructionARM::EmulateLSLImm, "lsl{s}<c> <Rd>, <Rm>, #imm"},
13063        &EmulateInstructionARM::EmulateLSLReg, "lsl{s}<c> <Rd>, <Rn>, <Rm>"},
13066        &EmulateInstructionARM::EmulateLSRImm, "lsr{s}<c> <Rd>, <Rm>, #imm"},
13069        &EmulateInstructionARM::EmulateLSRReg, "lsr{s}<c> <Rd>, <Rn>, <Rm>"},
13072        &EmulateInstructionARM::EmulateRRX, "rrx{s}<c> <Rd>, <Rm>"},
13075        &EmulateInstructionARM::EmulateRORImm, "ror{s}<c> <Rd>, <Rm>, #imm"},
13078        &EmulateInstructionARM::EmulateRORReg, "ror{s}<c> <Rd>, <Rn>, <Rm>"},
13081        &EmulateInstructionARM::EmulateMUL, "mul{s}<c> <Rd>,<R>,<Rm>"},
13172        &EmulateInstructionARM::EmulateSTREX, "strex<c> <Rd>, <Rt>, [<Rn>]"},
13202        &EmulateInstructionARM::EmulateSXTB, "sxtb<c> <Rd>,<Rm>{,<rotation>}"},
13204        &EmulateInstructionARM::EmulateSXTH, "sxth<c> <Rd>,<Rm>{,<rotation>}"},
13206        &EmulateInstructionARM::EmulateUXTB, "uxtb<c> <Rd>,<Rm>{,<rotation>}"},
13208        &EmulateInstructionARM::EmulateUXTH, "uxth<c> <Rd>,<Rm>{,<rotation>}"},
13264        "sub{s}<c> <Rd>, sp, <Rm>{,<shift>}"},
13275        &EmulateInstructionARM::EmulateADDSPImm, "add<c> <Rd>, sp, #imm"},
13346        &EmulateInstructionARM::EmulateADCImm, "adc{s}<c> <Rd>, <Rn>, #<const>"},
13352        "adc{s}<c>.w <Rd>, <Rn>, <Rm> {,<shift>}"},
13355        &EmulateInstructionARM::EmulateADDReg, "adds|add<c> <Rd>, <Rn>, <Rm>"},
13362        &EmulateInstructionARM::EmulateADR, "add<c> <Rd>, PC, #<const>"},
13364        &EmulateInstructionARM::EmulateADR, "sub<c> <Rd>, PC, #<const>"},
13366        &EmulateInstructionARM::EmulateADR, "add<c> <Rd>, PC, #<const>"},
13369        &EmulateInstructionARM::EmulateANDImm, "and{s}<c> <Rd>, <Rn>, #<const>"},
13375        "and{s}<c>.w <Rd>, <Rn>, <Rm> {,<shift>}"},
13378        &EmulateInstructionARM::EmulateBICImm, "bic{s}<c> <Rd>, <Rn>, #<const>"},
13384        "bic{s}<c>.w <Rd>, <Rn>, <Rm> {,<shift>}"},
13387        &EmulateInstructionARM::EmulateEORImm, "eor{s}<c> <Rd>, <Rn>, #<const>"},
13393        "eor{s}<c>.w <Rd>, <Rn>, <Rm> {,<shift>}"},
13396        &EmulateInstructionARM::EmulateORRImm, "orr{s}<c> <Rd>, <Rn>, #<const>"},
13402        "orr{s}<c>.w <Rd>, <Rn>, <Rm> {,<shift>}"},
13405        &EmulateInstructionARM::EmulateRSBImm, "rsbs|rsb<c> <Rd>, <Rn>, #0"},
13408        "rsb{s}<c>.w <Rd>, <Rn>, #<const>"},
13412        "rsb{s}<c>.w <Rd>, <Rn>, <Rm> {,<shift>}"},
13415        &EmulateInstructionARM::EmulateSBCImm, "sbc{s}<c> <Rd>, <Rn>, #<const>"},
13421        "sbc{s}<c>.w <Rd>, <Rn>, <Rm> {,<shift>}"},
13425        "adds|add<c> <Rd>,<Rn>,#<imm3>"},
13430        "add{s}<c>.w <Rd>,<Rn>,#<const>"},
13433        "addw<c> <Rd>,<Rn>,#<imm12>"},
13437        "subs|sub<c> <Rd>, <Rn> #imm3"},
13442        "sub{s}<c>.w <Rd>, <Rn>, #<const>"},
13445        "subw<c> <Rd>, <Rn>, #imm12"},
13448        &EmulateInstructionARM::EmulateSUBSPImm, "sub{s}.w <Rd>, sp, #<const>"},
13450        &EmulateInstructionARM::EmulateSUBSPImm, "subw<c> <Rd>, sp, #imm12"},
13453        &EmulateInstructionARM::EmulateSUBReg, "subs|sub<c> <Rd>, <Rn>, <Rm>"},
13456        "sub{s}<c>.w <Rd>, <Rn>, <Rm>{,<shift>}"},
13474        &EmulateInstructionARM::EmulateMOVRdRm, "mov<c> <Rd>, <Rm>"},
13477        &EmulateInstructionARM::EmulateMOVRdRm, "movs <Rd>, <Rm>"},
13478       // mov{s}<c>.w <Rd>, <Rm>
13480        &EmulateInstructionARM::EmulateMOVRdRm, "mov{s}<c>.w <Rd>, <Rm>"},
13483        &EmulateInstructionARM::EmulateMOVRdImm, "movs|mov<c> <Rd>, #imm8"},
13485        &EmulateInstructionARM::EmulateMOVRdImm, "mov{s}<c>.w <Rd>, #<const>"},
13487        &EmulateInstructionARM::EmulateMOVRdImm, "movw<c> <Rd>,#<imm16>"},
13490        &EmulateInstructionARM::EmulateMVNImm, "mvn{s} <Rd>, #<const>"},
13493        &EmulateInstructionARM::EmulateMVNReg, "mvns|mvn<c> <Rd>, <Rm>"},
13496        "mvn{s}<c>.w <Rd>, <Rm> {,<shift>}"},
13521        &EmulateInstructionARM::EmulateASRImm, "asrs|asr<c> <Rd>, <Rm>, #imm"},
13523        &EmulateInstructionARM::EmulateASRImm, "asr{s}<c>.w <Rd>, <Rm>, #imm"},
13528        &EmulateInstructionARM::EmulateASRReg, "asr{s}<c>.w <Rd>, <Rn>, <Rm>"},
13531        &EmulateInstructionARM::EmulateLSLImm, "lsls|lsl<c> <Rd>, <Rm>, #imm"},
13533        &EmulateInstructionARM::EmulateLSLImm, "lsl{s}<c>.w <Rd>, <Rm>, #imm"},
13538        &EmulateInstructionARM::EmulateLSLReg, "lsl{s}<c>.w <Rd>, <Rn>, <Rm>"},
13541        &EmulateInstructionARM::EmulateLSRImm, "lsrs|lsr<c> <Rd>, <Rm>, #imm"},
13543        &EmulateInstructionARM::EmulateLSRImm, "lsr{s}<c>.w <Rd>, <Rm>, #imm"},
13548        &EmulateInstructionARM::EmulateLSRReg, "lsr{s}<c>.w <Rd>, <Rn>, <Rm>"},
13551        &EmulateInstructionARM::EmulateRRX, "rrx{s}<c>.w <Rd>, <Rm>"},
13554        &EmulateInstructionARM::EmulateRORImm, "ror{s}<c>.w <Rd>, <Rm>, #imm"},
13559        &EmulateInstructionARM::EmulateRORReg, "ror{s}<c>.w <Rd>, <Rn>, <Rm>"},
13565        &EmulateInstructionARM::EmulateMUL, "mul<c> <Rd>,<Rn>,<Rm>"},
13726        "strex<c> <Rd>, <Rt>, [<Rn{,#<imm>}]"},
13747        &EmulateInstructionARM::EmulateSXTB, "sxtb<c> <Rd>,<Rm>"},
13749        &EmulateInstructionARM::EmulateSXTB, "sxtb<c>.w <Rd>,<Rm>{,<rotation>}"},
13751        &EmulateInstructionARM::EmulateSXTH, "sxth<c> <Rd>,<Rm>"},
13753        &EmulateInstructionARM::EmulateSXTH, "sxth<c>.w <Rd>,<Rm>{,<rotation>}"},
13755        &EmulateInstructionARM::EmulateUXTB, "uxtb<c> <Rd>,<Rm>"},
13757        &EmulateInstructionARM::EmulateUXTB, "uxtb<c>.w <Rd>,<Rm>{,<rotation>}"},
13759        &EmulateInstructionARM::EmulateUXTH, "uxth<c> <Rd>,<Rm>"},
13761        &EmulateInstructionARM::EmulateUXTH, "uxth<c>.w <Rd>,<Rm>{,<rotation>}"},
14241 // Write the result to the ARM core register Rd, and optionally update the
14260     Context &context, const uint32_t result, const uint32_t Rd, bool setflags,
14262   if (Rd == 15) {
14268     switch (Rd) {
14279       reg_num = dwarf_r0 + Rd;