1//===-- EmulateInstructionARM.h ---------------------------------*- C++ -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8 9#ifndef lldb_EmulateInstructionARM_h_ 10#define lldb_EmulateInstructionARM_h_ 11 12#include "Plugins/Process/Utility/ARMDefines.h" 13#include "lldb/Core/EmulateInstruction.h" 14#include "lldb/Utility/ConstString.h" 15#include "lldb/Utility/Status.h" 16 17namespace lldb_private { 18 19// ITSession - Keep track of the IT Block progression. 20class ITSession { 21public: 22 ITSession() : ITCounter(0), ITState(0) {} 23 ~ITSession() {} 24 25 // InitIT - Initializes ITCounter/ITState. 26 bool InitIT(uint32_t bits7_0); 27 28 // ITAdvance - Updates ITCounter/ITState as IT Block progresses. 29 void ITAdvance(); 30 31 // InITBlock - Returns true if we're inside an IT Block. 32 bool InITBlock(); 33 34 // LastInITBlock - Returns true if we're the last instruction inside an IT 35 // Block. 36 bool LastInITBlock(); 37 38 // GetCond - Gets condition bits for the current thumb instruction. 39 uint32_t GetCond(); 40 41private: 42 uint32_t ITCounter; // Possible values: 0, 1, 2, 3, 4. 43 uint32_t ITState; // A2.5.2 Consists of IT[7:5] and IT[4:0] initially. 44}; 45 46class EmulateInstructionARM : public EmulateInstruction { 47public: 48 enum ARMEncoding { 49 eEncodingA1, 50 eEncodingA2, 51 eEncodingA3, 52 eEncodingA4, 53 eEncodingA5, 54 eEncodingT1, 55 eEncodingT2, 56 eEncodingT3, 57 eEncodingT4, 58 eEncodingT5 59 }; 60 61 static void Initialize(); 62 63 static void Terminate(); 64 65 static lldb_private::ConstString GetPluginNameStatic(); 66 67 static const char *GetPluginDescriptionStatic(); 68 69 static lldb_private::EmulateInstruction * 70 CreateInstance(const lldb_private::ArchSpec &arch, InstructionType inst_type); 71 72 static bool 73 SupportsEmulatingInstructionsOfTypeStatic(InstructionType inst_type) { 74 switch (inst_type) { 75 case eInstructionTypeAny: 76 case eInstructionTypePrologueEpilogue: 77 case eInstructionTypePCModifying: 78 return true; 79 80 case eInstructionTypeAll: 81 return false; 82 } 83 return false; 84 } 85 86 lldb_private::ConstString GetPluginName() override { 87 return GetPluginNameStatic(); 88 } 89 90 uint32_t GetPluginVersion() override { return 1; } 91 92 bool SetTargetTriple(const ArchSpec &arch) override; 93 94 enum Mode { eModeInvalid = -1, eModeARM, eModeThumb }; 95 96 EmulateInstructionARM(const ArchSpec &arch) 97 : EmulateInstruction(arch), m_arm_isa(0), m_opcode_mode(eModeInvalid), 98 m_opcode_cpsr(0), m_it_session(), m_ignore_conditions(false) { 99 SetArchitecture(arch); 100 } 101 102 // EmulateInstructionARM (const ArchSpec &arch, 103 // bool ignore_conditions, 104 // void *baton, 105 // ReadMemory read_mem_callback, 106 // WriteMemory write_mem_callback, 107 // ReadRegister read_reg_callback, 108 // WriteRegister write_reg_callback) : 109 // EmulateInstruction (arch, 110 // ignore_conditions, 111 // baton, 112 // read_mem_callback, 113 // write_mem_callback, 114 // read_reg_callback, 115 // write_reg_callback), 116 // m_arm_isa (0), 117 // m_opcode_mode (eModeInvalid), 118 // m_opcode_cpsr (0), 119 // m_it_session () 120 // { 121 // } 122 123 bool SupportsEmulatingInstructionsOfType(InstructionType inst_type) override { 124 return SupportsEmulatingInstructionsOfTypeStatic(inst_type); 125 } 126 127 virtual bool SetArchitecture(const ArchSpec &arch); 128 129 bool ReadInstruction() override; 130 131 bool SetInstruction(const Opcode &insn_opcode, const Address &inst_addr, 132 Target *target) override; 133 134 bool EvaluateInstruction(uint32_t evaluate_options) override; 135 136 InstructionCondition GetInstructionCondition() override; 137 138 bool TestEmulation(Stream *out_stream, ArchSpec &arch, 139 OptionValueDictionary *test_data) override; 140 141 bool GetRegisterInfo(lldb::RegisterKind reg_kind, uint32_t reg_num, 142 RegisterInfo ®_info) override; 143 144 bool CreateFunctionEntryUnwind(UnwindPlan &unwind_plan) override; 145 146 uint32_t ArchVersion(); 147 148 bool ConditionPassed(const uint32_t opcode); 149 150 uint32_t CurrentCond(const uint32_t opcode); 151 152 // InITBlock - Returns true if we're in Thumb mode and inside an IT Block. 153 bool InITBlock(); 154 155 // LastInITBlock - Returns true if we're in Thumb mode and the last 156 // instruction inside an IT Block. 157 bool LastInITBlock(); 158 159 bool BadMode(uint32_t mode); 160 161 bool CurrentModeIsPrivileged(); 162 163 void CPSRWriteByInstr(uint32_t value, uint32_t bytemask, 164 bool affect_execstate); 165 166 bool BranchWritePC(const Context &context, uint32_t addr); 167 168 bool BXWritePC(Context &context, uint32_t addr); 169 170 bool LoadWritePC(Context &context, uint32_t addr); 171 172 bool ALUWritePC(Context &context, uint32_t addr); 173 174 Mode CurrentInstrSet(); 175 176 bool SelectInstrSet(Mode arm_or_thumb); 177 178 bool WriteBits32Unknown(int n); 179 180 bool WriteBits32UnknownToMemory(lldb::addr_t address); 181 182 bool UnalignedSupport(); 183 184 typedef struct { 185 uint32_t result; 186 uint8_t carry_out; 187 uint8_t overflow; 188 } AddWithCarryResult; 189 190 AddWithCarryResult AddWithCarry(uint32_t x, uint32_t y, uint8_t carry_in); 191 192 // Helper method to read the content of an ARM core register. 193 uint32_t ReadCoreReg(uint32_t regnum, bool *success); 194 195 // See A8.6.96 MOV (immediate) Operation. 196 // Default arguments are specified for carry and overflow parameters, which 197 // means 198 // not to update the respective flags even if setflags is true. 199 bool WriteCoreRegOptionalFlags(Context &context, const uint32_t result, 200 const uint32_t Rd, bool setflags, 201 const uint32_t carry = ~0u, 202 const uint32_t overflow = ~0u); 203 204 bool WriteCoreReg(Context &context, const uint32_t result, 205 const uint32_t Rd) { 206 // Don't set the flags. 207 return WriteCoreRegOptionalFlags(context, result, Rd, false); 208 } 209 210 // See A8.6.35 CMP (immediate) Operation. 211 // Default arguments are specified for carry and overflow parameters, which 212 // means 213 // not to update the respective flags. 214 bool WriteFlags(Context &context, const uint32_t result, 215 const uint32_t carry = ~0u, const uint32_t overflow = ~0u); 216 217 inline uint64_t MemARead(EmulateInstruction::Context &context, 218 lldb::addr_t address, uint32_t size, 219 uint64_t fail_value, bool *success_ptr) { 220 // This is a stub function corresponding to "MemA[]" in the ARM manual 221 // pseudocode, for 222 // aligned reads from memory. Since we are not trying to write a full 223 // hardware simulator, and since 224 // we are running in User mode (rather than Kernel mode) and therefore won't 225 // have access to many of the 226 // system registers we would need in order to fully implement this function, 227 // we will just call 228 // ReadMemoryUnsigned from here. In the future, if we decide we do need to 229 // do more faithful emulation of 230 // the hardware, we can update this function appropriately. 231 232 return ReadMemoryUnsigned(context, address, size, fail_value, success_ptr); 233 } 234 235 inline bool MemAWrite(EmulateInstruction::Context &context, 236 lldb::addr_t address, uint64_t data_val, uint32_t size) 237 238 { 239 // This is a stub function corresponding to "MemA[]" in the ARM manual 240 // pseudocode, for 241 // aligned writes to memory. Since we are not trying to write a full 242 // hardware simulator, and since 243 // we are running in User mode (rather than Kernel mode) and therefore won't 244 // have access to many of the 245 // system registers we would need in order to fully implement this function, 246 // we will just call 247 // WriteMemoryUnsigned from here. In the future, if we decide we do need to 248 // do more faithful emulation of 249 // the hardware, we can update this function appropriately. 250 251 return WriteMemoryUnsigned(context, address, data_val, size); 252 } 253 254 inline uint64_t MemURead(EmulateInstruction::Context &context, 255 lldb::addr_t address, uint32_t size, 256 uint64_t fail_value, bool *success_ptr) { 257 // This is a stub function corresponding to "MemU[]" in the ARM manual 258 // pseudocode, for 259 // unaligned reads from memory. Since we are not trying to write a full 260 // hardware simulator, and since 261 // we are running in User mode (rather than Kernel mode) and therefore won't 262 // have access to many of the 263 // system registers we would need in order to fully implement this function, 264 // we will just call 265 // ReadMemoryUnsigned from here. In the future, if we decide we do need to 266 // do more faithful emulation of 267 // the hardware, we can update this function appropriately. 268 269 return ReadMemoryUnsigned(context, address, size, fail_value, success_ptr); 270 } 271 272 inline bool MemUWrite(EmulateInstruction::Context &context, 273 lldb::addr_t address, uint64_t data_val, uint32_t size) 274 275 { 276 // This is a stub function corresponding to "MemU[]" in the ARM manual 277 // pseudocode, for 278 // unaligned writes to memory. Since we are not trying to write a full 279 // hardware simulator, and since 280 // we are running in User mode (rather than Kernel mode) and therefore won't 281 // have access to many of the 282 // system registers we would need in order to fully implement this function, 283 // we will just call 284 // WriteMemoryUnsigned from here. In the future, if we decide we do need to 285 // do more faithful emulation of 286 // the hardware, we can update this function appropriately. 287 288 return WriteMemoryUnsigned(context, address, data_val, size); 289 } 290 291protected: 292 // Typedef for the callback function used during the emulation. 293 // Pass along (ARMEncoding)encoding as the callback data. 294 enum ARMInstrSize { eSize16, eSize32 }; 295 296 typedef struct { 297 uint32_t mask; 298 uint32_t value; 299 uint32_t variants; 300 EmulateInstructionARM::ARMEncoding encoding; 301 uint32_t vfp_variants; 302 ARMInstrSize size; 303 bool (EmulateInstructionARM::*callback)( 304 const uint32_t opcode, 305 const EmulateInstructionARM::ARMEncoding encoding); 306 const char *name; 307 } ARMOpcode; 308 309 uint32_t GetFramePointerRegisterNumber() const; 310 311 uint32_t GetFramePointerDWARFRegisterNumber() const; 312 313 static ARMOpcode *GetARMOpcodeForInstruction(const uint32_t opcode, 314 uint32_t isa_mask); 315 316 static ARMOpcode *GetThumbOpcodeForInstruction(const uint32_t opcode, 317 uint32_t isa_mask); 318 319 // A8.6.123 PUSH 320 bool EmulatePUSH(const uint32_t opcode, const ARMEncoding encoding); 321 322 // A8.6.122 POP 323 bool EmulatePOP(const uint32_t opcode, const ARMEncoding encoding); 324 325 // A8.6.8 ADD (SP plus immediate) 326 bool EmulateADDRdSPImm(const uint32_t opcode, const ARMEncoding encoding); 327 328 // A8.6.97 MOV (register) -- Rd == r7|ip and Rm == sp 329 bool EmulateMOVRdSP(const uint32_t opcode, const ARMEncoding encoding); 330 331 // A8.6.97 MOV (register) -- move from r8-r15 to r0-r7 332 bool EmulateMOVLowHigh(const uint32_t opcode, const ARMEncoding encoding); 333 334 // A8.6.59 LDR (literal) 335 bool EmulateLDRRtPCRelative(const uint32_t opcode, 336 const ARMEncoding encoding); 337 338 // A8.6.8 ADD (SP plus immediate) 339 bool EmulateADDSPImm(const uint32_t opcode, const ARMEncoding encoding); 340 341 // A8.6.9 ADD (SP plus register) 342 bool EmulateADDSPRm(const uint32_t opcode, const ARMEncoding encoding); 343 344 // A8.6.23 BL, BLX (immediate) 345 bool EmulateBLXImmediate(const uint32_t opcode, const ARMEncoding encoding); 346 347 // A8.6.24 BLX (register) 348 bool EmulateBLXRm(const uint32_t opcode, const ARMEncoding encoding); 349 350 // A8.6.25 BX 351 bool EmulateBXRm(const uint32_t opcode, const ARMEncoding encoding); 352 353 // A8.6.26 BXJ 354 bool EmulateBXJRm(const uint32_t opcode, const ARMEncoding encoding); 355 356 // A8.6.212 SUB (immediate, ARM) -- Rd == r7 and Rm == ip 357 bool EmulateSUBR7IPImm(const uint32_t opcode, const ARMEncoding encoding); 358 359 // A8.6.215 SUB (SP minus immediate) -- Rd == ip 360 bool EmulateSUBIPSPImm(const uint32_t opcode, const ARMEncoding encoding); 361 362 // A8.6.215 SUB (SP minus immediate) 363 bool EmulateSUBSPImm(const uint32_t opcode, const ARMEncoding encoding); 364 365 // A8.6.216 SUB (SP minus register) 366 bool EmulateSUBSPReg(const uint32_t opcode, const ARMEncoding encoding); 367 368 // A8.6.194 STR (immediate, ARM) -- Rn == sp 369 bool EmulateSTRRtSP(const uint32_t opcode, const ARMEncoding encoding); 370 371 // A8.6.355 VPUSH 372 bool EmulateVPUSH(const uint32_t opcode, const ARMEncoding encoding); 373 374 // A8.6.354 VPOP 375 bool EmulateVPOP(const uint32_t opcode, const ARMEncoding encoding); 376 377 // A8.6.218 SVC (previously SWI) 378 bool EmulateSVC(const uint32_t opcode, const ARMEncoding encoding); 379 380 // A8.6.50 IT 381 bool EmulateIT(const uint32_t opcode, const ARMEncoding encoding); 382 383 // NOP 384 bool EmulateNop(const uint32_t opcode, const ARMEncoding encoding); 385 386 // A8.6.16 B 387 bool EmulateB(const uint32_t opcode, const ARMEncoding encoding); 388 389 // A8.6.27 CBNZ, CBZ 390 bool EmulateCB(const uint32_t opcode, const ARMEncoding encoding); 391 392 // A8.6.226 TBB, TBH 393 bool EmulateTB(const uint32_t opcode, const ARMEncoding encoding); 394 395 // A8.6.4 ADD (immediate, Thumb) 396 bool EmulateADDImmThumb(const uint32_t opcode, const ARMEncoding encoding); 397 398 // A8.6.5 ADD (immediate, ARM) 399 bool EmulateADDImmARM(const uint32_t opcode, const ARMEncoding encoding); 400 401 // A8.6.6 ADD (register) 402 bool EmulateADDReg(const uint32_t opcode, const ARMEncoding encoding); 403 404 // A8.6.7 ADD (register-shifted register) 405 bool EmulateADDRegShift(const uint32_t opcode, const ARMEncoding encoding); 406 407 // A8.6.97 MOV (register) 408 bool EmulateMOVRdRm(const uint32_t opcode, const ARMEncoding encoding); 409 410 // A8.6.96 MOV (immediate) 411 bool EmulateMOVRdImm(const uint32_t opcode, const ARMEncoding encoding); 412 413 // A8.6.35 CMP (immediate) 414 bool EmulateCMPImm(const uint32_t opcode, const ARMEncoding encoding); 415 416 // A8.6.36 CMP (register) 417 bool EmulateCMPReg(const uint32_t opcode, const ARMEncoding encoding); 418 419 // A8.6.14 ASR (immediate) 420 bool EmulateASRImm(const uint32_t opcode, const ARMEncoding encoding); 421 422 // A8.6.15 ASR (register) 423 bool EmulateASRReg(const uint32_t opcode, const ARMEncoding encoding); 424 425 // A8.6.88 LSL (immediate) 426 bool EmulateLSLImm(const uint32_t opcode, const ARMEncoding encoding); 427 428 // A8.6.89 LSL (register) 429 bool EmulateLSLReg(const uint32_t opcode, const ARMEncoding encoding); 430 431 // A8.6.90 LSR (immediate) 432 bool EmulateLSRImm(const uint32_t opcode, const ARMEncoding encoding); 433 434 // A8.6.91 LSR (register) 435 bool EmulateLSRReg(const uint32_t opcode, const ARMEncoding encoding); 436 437 // A8.6.139 ROR (immediate) 438 bool EmulateRORImm(const uint32_t opcode, const ARMEncoding encoding); 439 440 // A8.6.140 ROR (register) 441 bool EmulateRORReg(const uint32_t opcode, const ARMEncoding encoding); 442 443 // A8.6.141 RRX 444 bool EmulateRRX(const uint32_t opcode, const ARMEncoding encoding); 445 446 // Helper method for ASR, LSL, LSR, ROR (immediate), and RRX 447 bool EmulateShiftImm(const uint32_t opcode, const ARMEncoding encoding, 448 ARM_ShifterType shift_type); 449 450 // Helper method for ASR, LSL, LSR, and ROR (register) 451 bool EmulateShiftReg(const uint32_t opcode, const ARMEncoding encoding, 452 ARM_ShifterType shift_type); 453 454 // LOAD FUNCTIONS 455 456 // A8.6.53 LDM/LDMIA/LDMFD 457 bool EmulateLDM(const uint32_t opcode, const ARMEncoding encoding); 458 459 // A8.6.54 LDMDA/LDMFA 460 bool EmulateLDMDA(const uint32_t opcode, const ARMEncoding encoding); 461 462 // A8.6.55 LDMDB/LDMEA 463 bool EmulateLDMDB(const uint32_t opcode, const ARMEncoding encoding); 464 465 // A8.6.56 LDMIB/LDMED 466 bool EmulateLDMIB(const uint32_t opcode, const ARMEncoding encoding); 467 468 // A8.6.57 LDR (immediate, Thumb) -- Encoding T1 469 bool EmulateLDRRtRnImm(const uint32_t opcode, const ARMEncoding encoding); 470 471 // A8.6.58 LDR (immediate, ARM) - Encoding A1 472 bool EmulateLDRImmediateARM(const uint32_t opcode, 473 const ARMEncoding encoding); 474 475 // A8.6.59 LDR (literal) 476 bool EmulateLDRLiteral(const uint32_t, const ARMEncoding encoding); 477 478 // A8.6.60 LDR (register) - Encoding T1, T2, A1 479 bool EmulateLDRRegister(const uint32_t opcode, const ARMEncoding encoding); 480 481 // A8.6.61 LDRB (immediate, Thumb) - Encoding T1, T2, T3 482 bool EmulateLDRBImmediate(const uint32_t opcode, const ARMEncoding encoding); 483 484 // A8.6.62 LDRB (immediate, ARM) 485 bool EmulateLDRBImmediateARM(const uint32_t opcode, 486 const ARMEncoding encoding); 487 488 // A8.6.63 LDRB (literal) - Encoding T1, A1 489 bool EmulateLDRBLiteral(const uint32_t opcode, const ARMEncoding encoding); 490 491 // A8.6.64 LDRB (register) - Encoding T1, T2, A1 492 bool EmulateLDRBRegister(const uint32_t opcode, const ARMEncoding encoding); 493 494 // A8.6.65 LDRBT 495 bool EmulateLDRBT(const uint32_t opcode, const ARMEncoding encoding); 496 497 // A8.6.66 LDRD (immediate) 498 bool EmulateLDRDImmediate(const uint32_t opcode, const ARMEncoding encoding); 499 500 // A8.6.67 501 bool EmulateLDRDLiteral(const uint32_t opcode, const ARMEncoding encoding); 502 503 // A8.6.68 LDRD (register) 504 bool EmulateLDRDRegister(const uint32_t opcode, const ARMEncoding encoding); 505 506 // A8.6.69 LDREX 507 bool EmulateLDREX(const uint32_t opcode, const ARMEncoding encoding); 508 509 // A8.6.70 LDREXB 510 bool EmulateLDREXB(const uint32_t opcode, const ARMEncoding encoding); 511 512 // A8.6.71 LDREXD 513 bool EmulateLDREXD(const uint32_t opcode, const ARMEncoding encoding); 514 515 // A8.6.72 LDREXH 516 bool EmulateLDREXH(const uint32_t opcode, const ARMEncoding encoding); 517 518 // A8.6.73 LDRH (immediate, Thumb) - Encoding T1, T2, T3 519 bool EmulateLDRHImmediate(const uint32_t opcode, const ARMEncoding encoding); 520 521 // A8.6.74 LDRS (immediate, ARM) 522 bool EmulateLDRHImmediateARM(const uint32_t opcode, 523 const ARMEncoding encoding); 524 525 // A8.6.75 LDRH (literal) - Encoding T1, A1 526 bool EmulateLDRHLiteral(const uint32_t opcode, const ARMEncoding encoding); 527 528 // A8.6.76 LDRH (register) - Encoding T1, T2, A1 529 bool EmulateLDRHRegister(const uint32_t opcode, const ARMEncoding encoding); 530 531 // A8.6.77 LDRHT 532 bool EmulateLDRHT(const uint32_t opcode, const ARMEncoding encoding); 533 534 // A8.6.78 LDRSB (immediate) - Encoding T1, T2, A1 535 bool EmulateLDRSBImmediate(const uint32_t opcode, const ARMEncoding encoding); 536 537 // A8.6.79 LDRSB (literal) - Encoding T1, A1 538 bool EmulateLDRSBLiteral(const uint32_t opcode, const ARMEncoding encoding); 539 540 // A8.6.80 LDRSB (register) - Encoding T1, T2, A1 541 bool EmulateLDRSBRegister(const uint32_t opcode, const ARMEncoding encoding); 542 543 // A8.6.81 LDRSBT 544 bool EmulateLDRSBT(const uint32_t opcode, const ARMEncoding encoding); 545 546 // A8.6.82 LDRSH (immediate) - Encoding T1, T2, A1 547 bool EmulateLDRSHImmediate(const uint32_t opcode, const ARMEncoding encoding); 548 549 // A8.6.83 LDRSH (literal) - Encoding T1, A1 550 bool EmulateLDRSHLiteral(const uint32_t opcode, const ARMEncoding encoding); 551 552 // A8.6.84 LDRSH (register) - Encoding T1, T2, A1 553 bool EmulateLDRSHRegister(const uint32_t opcode, const ARMEncoding encoding); 554 555 // A8.6.85 LDRSHT 556 bool EmulateLDRSHT(const uint32_t opcode, const ARMEncoding encoding); 557 558 // A8.6.86 559 bool EmulateLDRT(const uint32_t opcode, const ARMEncoding encoding); 560 561 // STORE FUNCTIONS 562 563 // A8.6.189 STM/STMIA/STMEA 564 bool EmulateSTM(const uint32_t opcode, const ARMEncoding encoding); 565 566 // A8.6.190 STMDA/STMED 567 bool EmulateSTMDA(const uint32_t opcode, const ARMEncoding encoding); 568 569 // A8.6.191 STMDB/STMFD 570 bool EmulateSTMDB(const uint32_t opcode, const ARMEncoding encoding); 571 572 // A8.6.192 STMIB/STMFA 573 bool EmulateSTMIB(const uint32_t opcode, const ARMEncoding encoding); 574 575 // A8.6.193 STR (immediate, Thumb) 576 bool EmulateSTRThumb(const uint32_t opcode, const ARMEncoding encoding); 577 578 // A8.6.194 STR (immediate, ARM) 579 bool EmulateSTRImmARM(const uint32_t opcode, const ARMEncoding encoding); 580 581 // A8.6.195 STR (register) 582 bool EmulateSTRRegister(const uint32_t opcode, const ARMEncoding encoding); 583 584 // A8.6.196 STRB (immediate, Thumb) 585 bool EmulateSTRBThumb(const uint32_t opcode, const ARMEncoding encoding); 586 587 // A8.6.197 STRB (immediate, ARM) 588 bool EmulateSTRBImmARM(const uint32_t opcode, const ARMEncoding encoding); 589 590 // A8.6.198 STRB (register) 591 bool EmulateSTRBReg(const uint32_t opcode, const ARMEncoding encoding); 592 593 // A8.6.199 STRBT 594 bool EmulateSTRBT(const uint32_t opcode, const ARMEncoding encoding); 595 596 // A8.6.200 STRD (immediate) 597 bool EmulateSTRDImm(const uint32_t opcode, const ARMEncoding encoding); 598 599 // A8.6.201 STRD (register) 600 bool EmulateSTRDReg(const uint32_t opcode, const ARMEncoding encoding); 601 602 // A8.6.202 STREX 603 bool EmulateSTREX(const uint32_t opcode, const ARMEncoding encoding); 604 605 // A8.6.203 STREXB 606 bool EmulateSTREXB(const uint32_t opcode, const ARMEncoding encoding); 607 608 // A8.6.204 STREXD 609 bool EmulateSTREXD(const uint32_t opcode, const ARMEncoding encoding); 610 611 // A8.6.205 STREXH 612 bool EmulateSTREXH(const uint32_t opcode, const ARMEncoding encoding); 613 614 // A8.6.206 STRH (immediate, Thumb) 615 bool EmulateSTRHImmThumb(const uint32_t opcode, const ARMEncoding encoding); 616 617 // A8.6.207 STRH (immediate, ARM) 618 bool EmulateSTRHImmARM(const uint32_t opcode, const ARMEncoding encoding); 619 620 // A8.6.208 STRH (register) 621 bool EmulateSTRHRegister(const uint32_t opcode, const ARMEncoding encoding); 622 623 // A8.6.209 STRHT 624 bool EmulateSTRHT(const uint32_t opcode, const ARMEncoding encoding); 625 626 // A8.6.210 STRT 627 bool EmulateSTRT(const uint32_t opcode, const ARMEncoding encoding); 628 629 // A8.6.1 ADC (immediate) 630 bool EmulateADCImm(const uint32_t opcode, const ARMEncoding encoding); 631 632 // A8.6.2 ADC (Register) 633 bool EmulateADCReg(const uint32_t opcode, const ARMEncoding encoding); 634 635 // A8.6.10 ADR 636 bool EmulateADR(const uint32_t opcode, const ARMEncoding encoding); 637 638 // A8.6.11 AND (immediate) 639 bool EmulateANDImm(const uint32_t opcode, const ARMEncoding encoding); 640 641 // A8.6.12 AND (register) 642 bool EmulateANDReg(const uint32_t opcode, const ARMEncoding encoding); 643 644 // A8.6.19 BIC (immediate) 645 bool EmulateBICImm(const uint32_t opcode, const ARMEncoding encoding); 646 647 // A8.6.20 BIC (register) 648 bool EmulateBICReg(const uint32_t opcode, const ARMEncoding encoding); 649 650 // A8.6.26 BXJ 651 bool EmulateBXJ(const uint32_t opcode, const ARMEncoding encoding); 652 653 // A8.6.32 CMN (immediate) 654 bool EmulateCMNImm(const uint32_t opcode, const ARMEncoding encoding); 655 656 // A8.6.33 CMN (register) 657 bool EmulateCMNReg(const uint32_t opcode, const ARMEncoding encoding); 658 659 // A8.6.44 EOR (immediate) 660 bool EmulateEORImm(const uint32_t opcode, const ARMEncoding encoding); 661 662 // A8.6.45 EOR (register) 663 bool EmulateEORReg(const uint32_t opcode, const ARMEncoding encoding); 664 665 // A8.6.105 MUL 666 bool EmulateMUL(const uint32_t opcode, const ARMEncoding encoding); 667 668 // A8.6.106 MVN (immediate) 669 bool EmulateMVNImm(const uint32_t opcode, const ARMEncoding encoding); 670 671 // A8.6.107 MVN (register) 672 bool EmulateMVNReg(const uint32_t opcode, const ARMEncoding encoding); 673 674 // A8.6.113 ORR (immediate) 675 bool EmulateORRImm(const uint32_t opcode, const ARMEncoding encoding); 676 677 // A8.6.114 ORR (register) 678 bool EmulateORRReg(const uint32_t opcode, const ARMEncoding encoding); 679 680 // A8.6.117 PLD (immediate, literal) - Encoding T1, T2, T3, A1 681 bool EmulatePLDImmediate(const uint32_t opcode, const ARMEncoding encoding); 682 683 // A8.6.119 PLI (immediate,literal) - Encoding T3, A1 684 bool EmulatePLIImmediate(const uint32_t opcode, const ARMEncoding encoding); 685 686 // A8.6.120 PLI (register) - Encoding T1, A1 687 bool EmulatePLIRegister(const uint32_t opcode, const ARMEncoding encoding); 688 689 // A8.6.141 RSB (immediate) 690 bool EmulateRSBImm(const uint32_t opcode, const ARMEncoding encoding); 691 692 // A8.6.142 RSB (register) 693 bool EmulateRSBReg(const uint32_t opcode, const ARMEncoding encoding); 694 695 // A8.6.144 RSC (immediate) 696 bool EmulateRSCImm(const uint32_t opcode, const ARMEncoding encoding); 697 698 // A8.6.145 RSC (register) 699 bool EmulateRSCReg(const uint32_t opcode, const ARMEncoding encoding); 700 701 // A8.6.150 SBC (immediate) 702 bool EmulateSBCImm(const uint32_t opcode, const ARMEncoding encoding); 703 704 // A8.6.151 SBC (register) 705 bool EmulateSBCReg(const uint32_t opcode, const ARMEncoding encoding); 706 707 // A8.6.211 SUB (immediate, Thumb) 708 bool EmulateSUBImmThumb(const uint32_t opcode, const ARMEncoding encoding); 709 710 // A8.6.212 SUB (immediate, ARM) 711 bool EmulateSUBImmARM(const uint32_t opcode, const ARMEncoding encoding); 712 713 // A8.6.213 SUB (register) 714 bool EmulateSUBReg(const uint32_t opcode, const ARMEncoding encoding); 715 716 // A8.6.214 SUB (register-shifted register) 717 bool EmulateSUBRegShift(const uint32_t opcode, const ARMEncoding encoding); 718 719 // A8.6.222 SXTB - Encoding T1 720 bool EmulateSXTB(const uint32_t opcode, const ARMEncoding encoding); 721 722 // A8.6.224 SXTH - EncodingT1 723 bool EmulateSXTH(const uint32_t opcode, const ARMEncoding encoding); 724 725 // A8.6.227 TEQ (immediate) - Encoding A1 726 bool EmulateTEQImm(const uint32_t opcode, const ARMEncoding encoding); 727 728 // A8.6.228 TEQ (register) - Encoding A1 729 bool EmulateTEQReg(const uint32_t opcode, const ARMEncoding encoding); 730 731 // A8.6.230 TST (immediate) - Encoding A1 732 bool EmulateTSTImm(const uint32_t opcode, const ARMEncoding encoding); 733 734 // A8.6.231 TST (register) - Encoding T1, A1 735 bool EmulateTSTReg(const uint32_t opcode, const ARMEncoding encoding); 736 737 // A8.6.262 UXTB - Encoding T1 738 bool EmulateUXTB(const uint32_t opcode, const ARMEncoding encoding); 739 740 // A8.6.264 UXTH - Encoding T1 741 bool EmulateUXTH(const uint32_t opcode, const ARMEncoding encoding); 742 743 // B6.1.8 RFE 744 bool EmulateRFE(const uint32_t opcode, const ARMEncoding encoding); 745 746 // A8.6.319 VLDM 747 bool EmulateVLDM(const uint32_t opcode, const ARMEncoding encoding); 748 749 // A8.6.399 VSTM 750 bool EmulateVSTM(const uint32_t opcode, const ARMEncoding encoding); 751 752 // A8.6.307 VLD1 (multiple single elements) 753 bool EmulateVLD1Multiple(const uint32_t opcode, const ARMEncoding encoding); 754 755 // A8.6.308 VLD1 (single element to one lane) 756 bool EmulateVLD1Single(const uint32_t opcode, const ARMEncoding encoding); 757 758 // A8.6.309 VLD1 (single element to all lanes) 759 bool EmulateVLD1SingleAll(const uint32_t opcode, const ARMEncoding encoding); 760 761 // A8.6.391 VST1 (multiple single elements) 762 bool EmulateVST1Multiple(const uint32_t opcode, const ARMEncoding encoding); 763 764 // A8.6.392 VST1 (single element from one lane) 765 bool EmulateVST1Single(const uint32_t opcode, const ARMEncoding encoding); 766 767 // A8.6.317 VLDR 768 bool EmulateVLDR(const uint32_t opcode, const ARMEncoding encoding); 769 770 // A8.6.400 VSTR 771 bool EmulateVSTR(const uint32_t opcode, const ARMEncoding encoding); 772 773 // B6.2.13 SUBS PC, LR and related instructions 774 bool EmulateSUBSPcLrEtc(const uint32_t opcode, const ARMEncoding encoding); 775 776 uint32_t m_arm_isa; 777 Mode m_opcode_mode; 778 uint32_t m_opcode_cpsr; 779 uint32_t m_new_inst_cpsr; // This can get updated by the opcode. 780 ITSession m_it_session; 781 bool m_ignore_conditions; 782}; 783 784} // namespace lldb_private 785 786#endif // lldb_EmulateInstructionARM_h_ 787