Searched refs:RREG32_SOC15_IP (Results 1 - 13 of 13) sorted by relevance
/linux-master/drivers/gpu/drm/amd/amdgpu/ |
H A D | sdma_v6_0.c | 341 rb_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL)); 344 ib_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_IB_CNTL)); 407 f32_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL)); 440 rb_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL)); 486 doorbell = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL)); 487 doorbell_offset = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL_OFFSET)); 511 temp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_WATCHDOG_CNTL)); 518 temp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UTCL1_CNTL)); 524 temp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UTCL1_PAGE)); 534 temp = RREG32_SOC15_IP(G [all...] |
H A D | sdma_v5_0.c | 304 wptr = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI)); 306 wptr |= RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR)); 551 rb_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL)); 554 ib_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL)); 686 rb_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL)); 707 wptr_poll_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, 740 doorbell = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL)); 741 doorbell_offset = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, 798 ib_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL));
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H A D | sdma_v5_2.c | 360 rb_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL)); 363 ib_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL)); 493 rb_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL)); 514 wptr_poll_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, 543 doorbell = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL)); 544 doorbell_offset = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET)); 578 temp = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL)); 584 temp = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE)); 602 ib_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL));
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H A D | soc15_common.h | 70 #define RREG32_SOC15_IP(ip, reg) __RREG32_SOC15_RLC__(reg, 0, ip##_HWIP, 0) macro
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H A D | amdgpu_gmc.c | 903 RREG32_SOC15_IP(GC, reg) : 904 RREG32_SOC15_IP(MMHUB, reg);
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H A D | amdgpu_amdkfd_gfx_v10_3.c | 338 (*dump)[i++][1] = RREG32_SOC15_IP(GC, addr); \
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H A D | gmc_v9_0.c | 497 tmp = RREG32_SOC15_IP(MMHUB, reg); 525 tmp = RREG32_SOC15_IP(MMHUB, reg);
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H A D | amdgpu_amdkfd_gfx_v10.c | 352 (*dump)[i++][1] = RREG32_SOC15_IP(GC, addr); \
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H A D | amdgpu_amdkfd_gfx_v9.c | 969 reg_val = RREG32_SOC15_IP(GC, SOC15_REG_OFFSET(GC, inst, mmSPI_CSQ_WF_ACTIVE_COUNT_0) +
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H A D | gfx_v11_0.c | 5824 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 5832 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 5881 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); 5889 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); 6107 tmp = RREG32_SOC15_IP(GC, target); 6117 tmp = RREG32_SOC15_IP(GC, target);
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H A D | soc15.c | 463 RREG32_SOC15_IP(GC, reg) : RREG32(reg);
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H A D | gfx_v10_0.c | 8929 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 8935 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 8982 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); 8988 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); 9207 tmp = RREG32_SOC15_IP(GC, target); 9217 tmp = RREG32_SOC15_IP(GC, target);
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H A D | gfx_v9_0.c | 5755 mec_int_cntl = RREG32_SOC15_IP(GC,mec_int_cntl_reg); 5761 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg);
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