Searched refs:RREG32_SMC (Results 1 - 25 of 28) sorted by relevance

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/linux-master/drivers/gpu/drm/radeon/
H A Dsi_smc.c115 u32 tmp = RREG32_SMC(SMC_SYSCON_RESET_CNTL);
131 tmp = RREG32_SMC(SMC_SYSCON_RESET_CNTL);
145 u32 tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0);
154 u32 tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0);
163 u32 rst = RREG32_SMC(SMC_SYSCON_RESET_CNTL);
164 u32 clk = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0);
202 tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0);
H A Dci_smc.c116 u32 tmp = RREG32_SMC(SMC_SYSCON_RESET_CNTL);
124 u32 tmp = RREG32_SMC(SMC_SYSCON_RESET_CNTL);
139 u32 tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0);
148 u32 tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0);
157 u32 clk = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0);
158 u32 pc_c = RREG32_SMC(SMC_PC_C);
176 tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0);
H A Dtrinity_dpm.c330 value = RREG32_SMC(GFX_POWER_GATING_CNTL);
458 if (RREG32_SMC(CC_SMU_TST_EFUSE1_MISC) & RB_BACKEND_DISABLE_MASK)
459 WREG32_SMC(SMU_SCRATCH_A, (RREG32_SMC(SMU_SCRATCH_A) | 0x01));
474 value = RREG32_SMC(PM_I_CNTL_1);
479 value = RREG32_SMC(SMU_S_PG_CNTL);
484 value = RREG32_SMC(SMU_S_PG_CNTL);
488 value = RREG32_SMC(PM_I_CNTL_1);
548 value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_0 + ix);
558 value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_PG_CNTL + ix);
570 value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_
[all...]
H A Dci_dpm.c554 data = RREG32_SMC(config_regs->offset);
856 tmp = RREG32_SMC(CG_THERMAL_INT);
864 tmp = RREG32_SMC(CG_THERMAL_CTRL);
879 u32 thermal_int = RREG32_SMC(CG_THERMAL_INT);
911 tmp = (RREG32_SMC(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK) >> FDO_PWM_MODE_SHIFT;
913 tmp = (RREG32_SMC(CG_FDO_CTRL2) & TMIN_MASK) >> TMIN_SHIFT;
918 tmp = RREG32_SMC(CG_FDO_CTRL2) & ~TMIN_MASK;
922 tmp = RREG32_SMC(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK;
943 duty100 = (RREG32_SMC(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT;
987 tmp = (RREG32_SMC(CG_MULT_THERMAL_CTR
[all...]
H A Dkv_smc.c60 *enable_mask = RREG32_SMC(SMC_SYSCON_MSG_ARG_0);
H A Dkv_dpm.c173 data = RREG32_SMC(config_regs->offset);
487 u32 tmp = RREG32_SMC(GENERAL_PWRMGT);
502 u32 sclk_pwrmgt_cntl = RREG32_SMC(SCLK_PWRMGT_CNTL);
512 u32 sclk_pwrmgt_cntl = RREG32_SMC(SCLK_PWRMGT_CNTL);
1018 thermal_int = RREG32_SMC(CG_THERMAL_INT_CTRL);
2237 nbdpmconfig1 = RREG32_SMC(NB_DPM_CONFIG_1);
2264 tmp = RREG32_SMC(CG_THERMAL_INT_CTRL);
2602 (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) & CURR_SCLK_INDEX_MASK) >>
2611 tmp = (RREG32_SMC(SMU_VOLTAGE_STATUS) & SMU_VOLTAGE_CURRENT_LEVEL_MASK) >>
2625 (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDE
[all...]
H A Dcik.c207 temp = (RREG32_SMC(CG_MULT_THERMAL_STATUS) & CTF_TEMP_MASK) >>
224 temp = RREG32_SMC(0xC0300E0C);
1710 if (RREG32_SMC(GENERAL_PWRMGT) & GPU_COUNTER_CLK)
1713 if (RREG32_SMC(CG_CLKPIN_CNTL) & XTALIN_DIVIDE)
9419 tmp = RREG32_SMC(cntl_reg);
9425 if (RREG32_SMC(status_reg) & DCLK_STATUS)
9459 if (RREG32_SMC(CG_ECLK_STATUS) & ECLK_STATUS)
9466 tmp = RREG32_SMC(CG_ECLK_CNTL);
9472 if (RREG32_SMC(CG_ECLK_STATUS) & ECLK_STATUS)
9738 orig = data = RREG32_SMC(THM_CLK_CNT
[all...]
H A Dradeon.h2518 #define RREG32_SMC(reg) tn_smc_rreg(rdev, (reg)) macro
2550 uint32_t tmp_ = RREG32_SMC(reg); \
H A Dni.c856 u32 temp = RREG32_SMC(TN_CURRENT_GNB_TEMP) & 0x7ff;
/linux-master/drivers/gpu/drm/amd/pm/legacy-dpm/
H A Dsi_smc.c113 u32 tmp = RREG32_SMC(SMC_SYSCON_RESET_CNTL);
129 tmp = RREG32_SMC(SMC_SYSCON_RESET_CNTL) |
143 u32 tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0);
155 u32 rst = RREG32_SMC(SMC_SYSCON_RESET_CNTL);
156 u32 clk = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0);
194 tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0);
H A Dkv_smc.c63 *enable_mask = RREG32_SMC(ixSMC_SYSCON_MSG_ARG_0);
H A Dkv_dpm.c414 data = RREG32_SMC(config_regs->offset);
715 u32 tmp = RREG32_SMC(ixGENERAL_PWRMGT);
730 u32 sclk_pwrmgt_cntl = RREG32_SMC(ixSCLK_PWRMGT_CNTL);
741 u32 sclk_pwrmgt_cntl = RREG32_SMC(ixSCLK_PWRMGT_CNTL);
2497 nbdpmconfig1 = RREG32_SMC(ixNB_DPM_CONFIG_1);
2526 tmp = RREG32_SMC(ixCG_THERMAL_INT_CTRL);
2858 (RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX) &
2868 tmp = (RREG32_SMC(ixSMU_VOLTAGE_STATUS) &
2943 temp = RREG32_SMC(0xC0300E0C);
3123 cg_thermal_int = RREG32_SMC(ixCG_THERMAL_INT_CTR
[all...]
H A Dsi_dpm.c2846 data = RREG32_SMC(offset);
7559 cg_thermal_int = RREG32_SMC(CG_THERMAL_INT);
7564 cg_thermal_int = RREG32_SMC(CG_THERMAL_INT);
7576 cg_thermal_int = RREG32_SMC(CG_THERMAL_INT);
7581 cg_thermal_int = RREG32_SMC(CG_THERMAL_INT);
/linux-master/drivers/gpu/drm/amd/amdgpu/
H A Dvi.c555 tmp = RREG32_SMC(ixCG_CLKPIN_CNTL_2);
559 tmp = RREG32_SMC(ixCG_CLKPIN_CNTL);
605 rom_cntl = RREG32_SMC(ixROM_CNTL);
994 tmp = RREG32_SMC(cntl_reg);
1005 tmp = RREG32_SMC(status_reg);
1081 if (RREG32_SMC(reg_status) & status_mask)
1089 tmp = RREG32_SMC(reg_ctrl);
1095 if (RREG32_SMC(reg_status) & status_mask)
1187 orig = data = RREG32_SMC(ixTHM_CLK_CNTL);
1194 orig = data = RREG32_SMC(ixMISC_CLK_CTR
[all...]
H A Dcik.c922 if (RREG32_SMC(ixGENERAL_PWRMGT) & GENERAL_PWRMGT__GPU_COUNTER_CLK_MASK)
925 if (RREG32_SMC(ixCG_CLKPIN_CNTL) & CG_CLKPIN_CNTL__XTALIN_DIVIDE_MASK)
982 rom_cntl = RREG32_SMC(ixROM_CNTL);
1464 tmp = RREG32_SMC(cntl_reg);
1471 if (RREG32_SMC(status_reg) & CG_DCLK_STATUS__DCLK_STATUS_MASK)
1506 if (RREG32_SMC(ixCG_ECLK_STATUS) & CG_ECLK_STATUS__ECLK_STATUS_MASK)
1513 tmp = RREG32_SMC(ixCG_ECLK_CNTL);
1520 if (RREG32_SMC(ixCG_ECLK_STATUS) & CG_ECLK_STATUS__ECLK_STATUS_MASK)
1791 orig = data = RREG32_SMC(ixTHM_CLK_CNTL);
1799 orig = data = RREG32_SMC(ixMISC_CLK_CTR
[all...]
H A Dvce_v3_0.c373 tmp = (RREG32_SMC(ixVCE_HARVEST_FUSE_MACRO__ADDRESS) &
377 tmp = (RREG32_SMC(ixCC_HARVEST_FUSES) &
840 data = RREG32_SMC(ixCURRENT_PG_STATUS_APU);
842 data = RREG32_SMC(ixCURRENT_PG_STATUS);
H A Duvd_v4_2.c733 if (!(RREG32_SMC(ixCURRENT_PG_STATUS) &
744 if (RREG32_SMC(ixCURRENT_PG_STATUS) &
H A Duvd_v6_0.c363 (RREG32_SMC(ixCC_HARVEST_FUSES) & CC_HARVEST_FUSES__UVD_DISABLE_MASK))
1510 data = RREG32_SMC(ixCURRENT_PG_STATUS_APU);
1512 data = RREG32_SMC(ixCURRENT_PG_STATUS);
H A Damdgpu_cgs.c66 return RREG32_SMC(index);
H A Duvd_v5_0.c848 if (RREG32_SMC(ixCURRENT_PG_STATUS) &
H A Damdgpu.h1284 #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg)) macro
1315 u32 tmp = RREG32_SMC(_Reg); \
H A Dvce_v4_0.c904 u32 tmp = RREG32_SMC(ixGCK_DFS_BYPASS_CNTL);
H A Duvd_v7_0.c1713 u32 tmp = RREG32_SMC(ixGCK_DFS_BYPASS_CNTL);
H A Damdgpu_debugfs.c785 value = RREG32_SMC(*pos);
H A Dsi.c1882 if ((RREG32_SMC(CG_VCEPLL_FUNC_CNTL) & mask) == mask)

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