#
bb87e511 |
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15-Feb-2024 |
Ilpo Järvinen <ilpo.jarvinen@linux.intel.com> |
drm/amdgpu: Use RMW accessors for changing LNKCTL2 Convert open coded RMW accesses for LNKCTL2 to use pcie_capability_clear_and_set_word() which makes its easier to understand what the code tries to do. LNKCTL2 is not really owned by any driver because it is a collection of control bits that PCI core might need to touch. RMW accessors already have support for proper locking for a selected set of registers (LNKCTL2 is not yet among them but likely will be in the future) to avoid losing concurrent updates. Acked-by: Alex Deucher <alexander.deucher@amd.com> Suggested-by: Lukas Wunner <lukas@wunner.de> Signed-off-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
1a6513de |
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23-Oct-2023 |
Mario Limonciello <mario.limonciello@amd.com> |
drm/amd: Move AMD_IS_APU check for ASPM into top level function There is no need for every ASIC driver to perform the same check. Move the duplicated code into amdgpu_device_should_use_aspm(). Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
ce7d8811 |
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17-Jul-2023 |
Ilpo Järvinen <ilpo.jarvinen@linux.intel.com> |
drm/amdgpu: Use RMW accessors for changing LNKCTL Don't assume that only the driver would be accessing LNKCTL. ASPM policy changes can trigger write to LNKCTL outside of driver's control. And in the case of upstream bridge, the driver does not even own the device it's changing the registers for. Use RMW capability accessors which do proper locking to avoid losing concurrent updates to the register value. Suggested-by: Lukas Wunner <lukas@wunner.de> Fixes: a2e73f56fa62 ("drm/amdgpu: Add support for CIK parts") Fixes: 62a37553414a ("drm/amdgpu: add si implementation v10") Link: https://lore.kernel.org/r/20230717120503.15276-6-ilpo.jarvinen@linux.intel.com Signed-off-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Alex Deucher <alexander.deucher@amd.com>
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#
d51ac6d0 |
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23-May-2022 |
Le Ma <le.ma@amd.com> |
drm/amdgpu: add xcc index argument to select_sh_se function v2 v1: To support multiple XCD case (Le) v2: introduce xcc index to gfx_v11_0_select_sh_se (Hawking) Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
0ab5d711 |
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16-Feb-2022 |
Mario Limonciello <mario.limonciello@amd.com> |
drm/amd: Refactor `amdgpu_aspm` to be evaluated per device Evaluating `pcie_aspm_enabled` as part of driver probe has the implication that if one PCIe bridge with an AMD GPU connected doesn't support ASPM then none of them do. This is an invalid assumption as the PCIe core will configure ASPM for individual PCIe bridges. Create a new helper function that can be called by individual dGPUs to react to the `amdgpu_aspm` module parameter without having negative results for other dGPUs on the PCIe bus. Suggested-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
06cf9bd6 |
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12-Jan-2022 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: don't do resets on APUs which don't support it It can cause a hang. This is normally not enabled for GPU hangs on these asics, but was recently enabled for handling aborted suspends. This causes hangs on some platforms on suspend. Fixes: daf8de0874ab5b ("drm/amdgpu: always reset the asic in suspend (v2)") Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1858 Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
e8309d50 |
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12-Jan-2022 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: don't do resets on APUs which don't support it It can cause a hang. This is normally not enabled for GPU hangs on these asics, but was recently enabled for handling aborted suspends. This causes hangs on some platforms on suspend. Fixes: daf8de0874ab5b ("drm/amdgpu: always reset the asic in suspend (v2)") Cc: stable@vger.kernel.org Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1858 Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
733ee71a |
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18-Jun-2021 |
Ryan Taylor <Ryan.Taylor@amd.com> |
drm/amdgpu: replace dce_virtual with amdgpu_vkms (v3) Move dce_virtual into amdgpu_vkms and update all references to dce_virtual with amdgpu_vkms. v2: Removed more references to dce_virtual. v3: Restored display modes from previous implementation. Signed-off-by: Ryan Taylor <Ryan.Taylor@amd.com> Reported-by: kernel test robot <lkp@intel.com> Suggested-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
6f786950 |
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02-Feb-2021 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu/codec: drop the internal codec index And just use the ioctl index. They are the same. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
3b246e8b |
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07-Jan-2021 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: add video decode/encode cap tables and asic callbacks (v3) For each asic family. Will be used to populate tables for the new INFO ioctl query. v2: add max_pixels_per_frame to handle the portrait case v3: fix copy paste typos Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> (v1) Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
44ab8bb0 |
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04-Feb-2021 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu/cik: minor clean up of reset code Drop duplicate reset method logging, whitespace changes. Acked-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
580577fb |
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04-Dec-2020 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu/cik: enable BACO reset on Bonaire Works now that the BACO sequence is fixed. Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
2a4776a7 |
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28-Oct-2020 |
Evan Quan <evan.quan@amd.com> |
drm/amd/pm: enable baco reset for Hawaii Which can be used for S4(hibernation) support. Signed-off-by: Evan Quan <evan.quan@amd.com> Tested-by: Sandeep Raghuraman <sandy.8925@gmail.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
0134022f |
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28-Oct-2020 |
Evan Quan <evan.quan@amd.com> |
drm/amd/pm: enable baco reset for Hawaii Which can be used for S4(hibernation) support. Signed-off-by: Evan Quan <evan.quan@amd.com> Tested-by: Sandeep Raghuraman <sandy.8925@gmail.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
819515c7 |
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19-Aug-2020 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: add pre_asic_init callback for CIK Nothing to do for this family. Acked-by: Nirmoy Das <nirmoy.das@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
11043b7a |
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10-Aug-2020 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: note what type of reset we are using When we reset the GPU, note what type of reset will be used. This makes debugging different reset scenarios more clear as the driver may use different reset methods depending on conditions on the system. Acked-by: Nirmoy Das <nirmoy.das@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
273da6ff |
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14-Jul-2020 |
Wenhui Sheng <Wenhui.Sheng@amd.com> |
drm/amdgpu: add module parameter choose reset mode Default value is auto, doesn't change original reset method logic. v2: change to use parameter reset_method v3: add warn msg if specified mode isn't supported Signed-off-by: Likun Gao <Likun.Gao@amd.com> Signed-off-by: Wenhui Sheng <Wenhui.Sheng@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
028cfb24 |
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10-Apr-2020 |
Evan Quan <evan.quan@amd.com> |
drm/amdgpu: fix wrong vram lost counter increment V2 Vram lost counter is wrongly increased by two during baco reset. V2: assumed vram lost for mode1 reset on all ASICs Signed-off-by: Evan Quan <evan.quan@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
dadce777 |
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10-Apr-2020 |
Evan Quan <evan.quan@amd.com> |
drm/amdgpu: fix wrong vram lost counter increment V2 Vram lost counter is wrongly increased by two during baco reset. V2: assumed vram lost for mode1 reset on all ASICs Signed-off-by: Evan Quan <evan.quan@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
3aa0115d |
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03-Mar-2020 |
Monk Liu <Monk.Liu@amd.com> |
drm/amdgpu: cleanup all virtualization detection routine we need to move virt detection much earlier because: 1) HW team confirms us that RCC_IOV_FUNC_IDENTIFIER will always be at DE5 (dw) mmio offset from vega10, this way there is no need to implement detect_hw_virt() routine in each nbio/chip file. for VI SRIOV chip (tonga & fiji), the BIF_IOV_FUNC_IDENTIFIER is at 0x1503 2) we need to acknowledged we are SRIOV VF before we do IP discovery because the IP discovery content will be updated by host everytime after it recieved a new coming "REQ_GPU_INIT_DATA" request from guest (there will be patches for this new handshake soon). Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Emily Deng <Emily.Deng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
9530273e |
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07-Jan-2020 |
Evan Quan <evan.quan@amd.com> |
drm/amd/powerplay: cover the powerplay implementation details V3 This can save users much troubles. As they do not actually need to care whether swSMU or traditional powerplay routine should be used. V2: apply the fixes to vi.c and cik.c also V3: squash in oops fix Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
5149f082 |
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25-Nov-2019 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: flag vram lost on baco reset for VI/CIK VI/CIK BACO was inflight when this fix landed for SOC15/NV. Add the fix to VI/CIK as well. Acked-by: Evan Quan <evan.quan@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
dea8b900 |
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25-Nov-2019 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: flag vram lost on baco reset for VI/CIK VI/CIK BACO was inflight when this fix landed for SOC15/NV. Add the fix to VI/CIK as well. Acked-by: Evan Quan <evan.quan@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
88027c89 |
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17-Nov-2019 |
Frederick Lawler <fred@fredlawl.com> |
drm/amdgpu: Prefer pcie_capability_read_word() Commit 8c0d3a02c130 ("PCI: Add accessors for PCI Express Capability") added accessors for the PCI Express Capability so that drivers didn't need to be aware of differences between v1 and v2 of the PCI Express Capability. Replace pci_read_config_word() and pci_write_config_word() calls with pcie_capability_read_word() and pcie_capability_write_word(). [bhelgaas: fix a couple remaining instances in cik.c] Link: https://lore.kernel.org/r/20191118003513.10852-1-fred@fredlawl.com Signed-off-by: Frederick Lawler <fred@fredlawl.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
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#
35e768e2 |
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21-Nov-2019 |
Bjorn Helgaas <bhelgaas@google.com> |
drm/amdgpu: Replace numbers with PCI_EXP_LNKCTL2 definitions Replace hard-coded magic numbers with the descriptive PCI_EXP_LNKCTL2 definitions. No functional change intended. Link: https://lore.kernel.org/r/20191112173503.176611-4-helgaas@kernel.org Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
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#
19d7a95a |
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20-Nov-2019 |
Bjorn Helgaas <bhelgaas@google.com> |
drm/amdgpu: Correct Transmit Margin masks Previously we masked PCIe Link Control 2 register values with "7 << 9", which was apparently intended to be the Transmit Margin field, but instead was the high order bit of Transmit Margin, the Enter Modified Compliance bit, and the Compliance SOS bit. Correct the mask to "7 << 7", which is the Transmit Margin field. Link: https://lore.kernel.org/r/20191112173503.176611-3-helgaas@kernel.org Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
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#
0d0c07ee |
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04-Oct-2019 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: add supports_baco callback for CIK asics. BACO - Bus Active, Chip Off Check the BACO capabilities from the powerplay table. Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
664fe85a |
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22-Oct-2019 |
Marek Olšák <marek.olsak@amd.com> |
drm/amdgpu: Allow reading more status registers on si/cik Allow userspace to read the same status registers for every family. Based on commit c7890fea, added any of these registers if defined in the include files of each architecture. Signed-off-by: Marek Olšák <marek.olsak@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
97c002be |
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11-Mar-2019 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: enable BACO reset for SMU7 based dGPUs (v2) Use BACO to reset the GPU if supported on SMU7 based dGPUs. v2: don't use baco on CI parts Reviewed-by: Evan Quan <evan.quan@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
6d0f50da |
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23-Jul-2019 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: add reset_method asic callback for cik CIK always uses the legacy pci based reset. Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
47b757fb |
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09-Jun-2019 |
Sam Ravnborg <sam@ravnborg.org> |
drm/amd: drop use of drmP.h in remaining files With this commit drm/amd/ has no longer any uses of the deprecated drmP.h header file. Signed-off-by: Sam Ravnborg <sam@ravnborg.org> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Cc: "Christian König" <christian.koenig@amd.com> Cc: "David (ChunMing) Zhou" <David1.Zhou@amd.com> Cc: David Airlie <airlied@linux.ie> Cc: Daniel Vetter <daniel@ffwll.ch> Link: https://patchwork.freedesktop.org/patch/msgid/20190609220757.10862-11-sam@ravnborg.org
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#
dcea6e65 |
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30-Apr-2019 |
Kent Russell <kent.russell@amd.com> |
drm/amdgpu: Add PCIe replay count sysfs file Add a sysfs file for reporting the number of PCIe replays (NAKs). This returns the sum of NAKs received and NAKs generated Signed-off-by: Kent Russell <kent.russell@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
bc4b539e |
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16-Jan-2019 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: remove old CI DPM implementation The power smu7 powerplay code is much more robust and has been the default for a while now. Remove the old code. Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
3fcc10d7 |
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31-Oct-2018 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu/cik: add need_reset_on_init asic callback for CIK (v2) CIK chips require a reset if the driver was previously loaded because the SMU can only be loaded once between each reset. v2: rebase Reviewed-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
b45e18ac |
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03-Jan-2019 |
Kent Russell <kent.russell@amd.com> |
drm/amdgpu: Add sysfs file for PCIe usage v5 Add a sysfs file that reports the number of bytes transmitted and received in the last second. This can be used to approximate the PCIe bandwidth usage over the last second. v2: Clarify use of mps as estimation of bandwidth v3: Don't make the file on APUs v4: Early exit for APUs in the read function, change output to display "packets-received packets-sent mps" v5: fix missing header for si (Alex) Signed-off-by: Kent Russell <kent.russell@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
4e2c1ac2 |
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19-Nov-2018 |
Oak Zeng <ozeng@amd.com> |
drm/amdgpu: Doorbell index initialization for ASICs before vega10 Initialize doorbell index for asics vi and cik v2: Use enum definition instead of hardcoded number Signed-off-by: Oak Zeng <ozeng@amd.com> Suggested-by: Felix Kuehling <Felix.Kuehling@amd.com> Suggested-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
3089aa22 |
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30-Sep-2018 |
Rex Zhu <Rex.Zhu@amd.com> |
drm/amdgpu: Change SI/CI gfx/sdma/smu init sequence initialize gfx/sdma before dpm features enabled. Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
586092ab |
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23-Jul-2018 |
Jia-Ju Bai <baijiaju1990@gmail.com> |
gpu: drm: amdgpu: Replace mdelay with msleep in cik_pcie_gen3_enable() cik_pcie_gen3_enable() is only called by cik_common_hw_init(), which is never called in atomic context. cik_pcie_gen3_enable() calls mdelay() to busily wait, which is not necessary. mdelay() can be replaced with msleep(). This is found by a static analysis tool named DCNS written by myself. Signed-off-by: Jia-Ju Bai <baijiaju1990@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
3120e2a3 |
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30-May-2018 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu/pp: switch the default dpm implementation for CI Switch hawaii and bonaire to use powerplay rather than the old dpm implementation. Powerplay supports more features and is better maintained. Ultimately, we can drop the older dpm implementation like we did for other older asics. Reviewed-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Rex Zhu <rezhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
b7acb46f |
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29-Mar-2018 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu/cik: implement asic need_full_reset callback Used to check on a per SoC basis whether the SoC needs a full reset of a per IP soft reset. Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
b905090d |
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12-Mar-2018 |
Rex Zhu <Rex.Zhu@amd.com> |
drm/amdgpu: Remove wrapper layer of smu ip functions 1. delete amdgpu_powerplay.c used for wrapping smu ip functions 2. delete struct pp_instance, 3. make struct hwmgr as the smu hw handle. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
5494d864 |
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09-Mar-2018 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: move getting pcie info to common code No need to replicate it in several places. Reviewed-by: Rex Zhu <rezhu@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
19aede77 |
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09-Mar-2018 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: move firmware loading type setup to common code No need to replicate it in several places. Reviewed-by: Rex Zhu <rezhu@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
69882565 |
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19-Jan-2018 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: add optional ring to *_hdp callbacks This adds an optional ring to the invalidate_hdp and flush_hdp callbacks. If the ring isn't specified or the emit_wreg function not available the HDP operation will be done with the CPU otherwise by writing on the ring. Signed-off-by: Christian König <christian.koenig@amd.com> Acked-by: Chunming Zhou <david1.zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
13854c60 |
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06-Sep-2017 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: add HDP asic callbacks for CIK Needed to flush and invalidate the HDP block using the CPU. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Samuel Li <Samuel.Li@amd.com>
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#
041d9d93 |
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15-Dec-2017 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: rename amdgpu_get_pcie_info add device to the name for consistency. Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
2990a1fc |
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15-Dec-2017 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: rename ip block helper functions add device to the name for consistency. Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
8111c387 |
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14-Dec-2017 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: rename amdgpu_pci_config_reset add device for consistency with other functions in this file. Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
9c3f2b54 |
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14-Dec-2017 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: rename amdgpu_program_register_sequence add device for consistency with other functions in this file. Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
c47b41a7 |
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03-Nov-2017 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: remove nonsense const u32 cast on ARRAY_SIZE result Not sure what that should originally been good for, but it doesn't seem to make any sense any more. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
aca31681 |
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21-Nov-2017 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: used cached gca values for cik_read_register Using the cached values has less latency for bare metal and prevents reading back bogus values if the engine is powergated. This was implemented for VI and SI, but somehow CIK got missed. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
9355c0e8 |
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10-Aug-2017 |
Alex Deucher <alexdeucher@gmail.com> |
drm/amdgpu/cik: add IP modules for DC for APUs Enable DC for DCE8 APUs. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
4562236b |
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12-Sep-2017 |
Harry Wentland <harry.wentland@amd.com> |
drm/amd/dc: Add dc display driver (v2) Supported DCE versions: 8.0, 10.0, 11.0, 11.2 v2: rebase against 4.11 Signed-off-by: Harry Wentland <harry.wentland@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
ba997709 |
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09-Nov-2015 |
Yong Zhao <yong.zhao@amd.com> |
drm/amdgpu: Correctly establish the suspend/resume hook for amdkfd Signed-off-by: Yong Zhao <yong.zhao@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Oded Gabbay <oded.gabbay@gmail.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
97fcc76b |
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11-Apr-2017 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: drop support for untouched registers I couldn't figure out what this was original good for, but we don't use it any more. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
248a1d6f |
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23-Apr-2017 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
drm/amd: fix include notation and remove -Iinclude/drm flag Include <drm/*.h> instead of relative path from include/drm, then remove the -Iinclude/drm compiler flag. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Link: http://patchwork.freedesktop.org/patch/msgid/1493009447-31524-4-git-send-email-yamada.masahiro@socionext.com
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#
e635ee07 |
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01-Nov-2016 |
Huang Rui <ray.huang@amd.com> |
drm/amdgpu: use new flag to handle different firmware loading method This patch introduces a new flag named "amdgpu_firmware_load_type" to handle different firmware loading method. Since Vega10, there are three ways to load firmware. It would be better to use a flag and a fw_load_type kernel parameter to configure it. Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
bbf282d8 |
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03-Mar-2017 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: add asic callback to get memsize register Newer asics use different registers so abstract it. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
c836fec5 |
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10-Feb-2017 |
Jim Qu <Jim.Qu@amd.com> |
drm/amd/amdgpu: post card if there is real hw resetting performed Check whether we need to post rather than whether the asic is posted. There are some cases (e.g., GPU reset or resume from hibernate) where we need to force post even if the asic has been posted. Signed-off-by: Jim Qu <Jim.Qu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
ca6d3503 |
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25-Jan-2017 |
Rex Zhu <Rex.Zhu@amd.com> |
drm/amdgpu: enable vce pg feature on Kv. Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
c8394f38 |
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08-Jan-2017 |
Xiangliang Yu <Xiangliang.Yu@amd.com> |
drm/amdgpu: remove detect_hw_virtualization interface Call detection function driectly, so remove the interface. V2: ci and si also need to call the detect function. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Monk Liu <monk.liu@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
5a5099cb |
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09-Jan-2017 |
Xiangliang Yu <Xiangliang.Yu@amd.com> |
drm/amdgpu/virt: rename fieldes of virtualization structure Use acronym to rename fields to make easy to spell out. Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
72a57438 |
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21-Oct-2016 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: consolidate atom scratch reg handling for hangs Move from asic specific code to common atom code. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
a1255107 |
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13-Oct-2016 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: rework IP block registration (v2) This makes it easier to replace specific IP blocks on asics for handling virtual_dce, DAL, etc. and for building IP lists for hw or tables. This also stored the status information in the same structure. v2: split out spelling fix into a separate patch add a function to add IPs to the list Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
4e99a44e |
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30-Mar-2016 |
Monk Liu <Monk.Liu@amd.com> |
drm/amdgpu:changes of virtualization cases probe (v3) 1,Changes on virtualization detections 2,Don't load smu & mc firmware if using sr-iov bios 3,skip vPost for sriov & force vPost if dev pass-through v2: agd: squash in Rays's fix for the missed SI case v3: agd: squash in additional fixes for CIK, SI, cleanup Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
9accf2fd |
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10-Aug-2016 |
Emily Deng <Emily.Deng@amd.com> |
drm/amdgpu: Change the virtual_display type from int to char*. For virtual display feature, as there may be multiple GPUs, for user could choose whiche GPU need to enable this feature, change the type of virtual_display from int to char*. The variable will be set like this virtual_display="xxxx:xx:xx.x;xxxx:xx:xx.x;". Signed-off-by: Emily Deng <Emily.Deng@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
d06b7e1c |
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08-Aug-2016 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: move vsync_timer_enabled setup to dce virtual early_init Put it in one place. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
a6be7570 |
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07-Aug-2016 |
Emily Deng <Emily.Deng@amd.com> |
drm/amdgpu: Set ip_blocks according variable amdgpu_virtual_display. For virtual display feature, if user set the option "amdgpu.virtual_display=1" when load amdgpu.ko. Then need to set the ip_blocks with virtual display ip blocks. And when enable virtual display, the amdgpu_dal need to be set to zero. Signed-off-by: Emily Deng <Emily.Deng@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
e9ed3a67 |
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07-Aug-2016 |
Emily Deng <Emily.Deng@amd.com> |
drm/amdgpu: Define virtual display ip blocks. For virtual display feature, define virtual display ip blocks, and set dce_virtual_ip_funcs to DCE block. Signed-off-by: Emily Deng <Emily.Deng@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
004e29cc |
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11-Jul-2016 |
Edward O'Callaghan <funfunctor@folklore1984.net> |
drivers/amdgpu: Use canonical form in branch predicates Found-by: Coccinelle Signed-off-by: Edward O'Callaghan <funfunctor@folklore1984.net> Reviewed-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
9559ef5b |
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28-Jun-2016 |
Tom St Denis <tom.stdenis@amd.com> |
drm/amd/gfx: add instance field to select_se_sh (v3) Add ability to specify instance in select_se_sh callback. Defaults to 0xffffffff all over the driver. (v2) Don't enable INSTANCE_BROADCAST by default (v3) Style changes Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
05fb7291 |
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20-Jun-2016 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: move select_se_sh into the gfx struct It's gfx IP specific, not asic specific, so move to a gfx callback. Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
b95e31fd |
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07-Jul-2016 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: move get_gpu_clock_counter into the gfx struct It's gfx IP specific, not asic specific, so move to a gfx callback. Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
4b7d97ac |
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21-Jun-2016 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: drop wait_for_mc_idle asic callback Only used in the gmc IP modules so just call the local function directly. Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
b314f9a9 |
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05-Jun-2016 |
Chunming Zhou <David1.Zhou@amd.com> |
drm/amdgpu: enable BUS master after pci reset Re-enable bus mastering after GPU reset. We disable it at the top of these functions, so balance them by re-enabling it. Signed-off-by: Chunming Zhou <David1.Zhou@amd.com> eviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
89a31827 |
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05-Jun-2016 |
Chunming Zhou <David1.Zhou@amd.com> |
drm/amdgpu: add return value for pci config reset So we know whether or not the reset succeeded. Signed-off-by: Chunming Zhou <David1.Zhou@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
048765ad |
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11-Jun-2016 |
Andres Rodriguez <andres.rodriguez@amd.com> |
amdgpu: fix asic initialization for virtualized environments (v2) When executing in a PCI passthrough based virtuzliation environemnt, the hypervisor will usually attempt to send a PCIe bus reset signal to the ASIC when the VM reboots. In this scenario, the card is not correctly initialized, but we still consider it to be posted. Therefore, in a passthrough based environemnt we should always post the card to guarantee it is in a good state for driver initialization. However, if we are operating in SR-IOV mode it is up to the GIM driver to manage the asic state, therefore we should not post the card (and shouldn't be able to do it either). v2: add missing semi-colon Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Andres Rodriguez <andres.rodriguez@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
88a907d6 |
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04-May-2016 |
Tom St Denis <tom.stdenis@amd.com> |
drm/amd/amdgpu: Add name field to amd_ip_funcs (v2) Add name that we can print out in kernel messages to aid in debugging. v2: drop DAL changes for upstream Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
7dae69a2 |
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03-May-2016 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: fetch cu_info once at init Fetch this info once at init and just store the results for future requests. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
16a7989a |
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28-Mar-2016 |
Tom St Denis <tom.stdenis@amd.com> |
drm/amd/amdgpu: Drop print_status callbacks. First patch in series to move to user mode debug tools we're removing the print_status callbacks. These functions were unused at the moment anyway. Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
eca2240f |
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19-Mar-2016 |
Nils Wallménius <nils.wallmenius@gmail.com> |
drm/amdgpu: mark amdgpu_allowed_register_entry tables as 'const' Signed-off-by: Nils Wallménius <nils.wallmenius@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
0bf5df3b |
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04-Mar-2016 |
Nils Wallménius <nils.wallmenius@gmail.com> |
drm/amdgpu: delete set-but-not-read member has_uvd from amdgpu_device Clean up leftover from radeon code. Signed-off-by: Nils Wallménius <nils.wallmenius@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
ceb5bc86 |
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14-Oct-2015 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: clean up asic level reset for CI Drop soft reset, always use pci config reset. Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Ken Wang <Qingqing.Wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
e3b04bc7 |
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05-Feb-2016 |
Alex Deucher <alexander.deucher@amd.com> |
drma/dmgpu: move cg and pg flags into shared headers So they can be used by powerplay. Reviewed-by: Eric Huang <JinHuiEric.Huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
76ecb2c7 |
|
04-Feb-2016 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu/cik: don't mess with aspm if gpu is root bus Pcie registers may not be available in a virtualized environment. Reviewed-by: monk liu <monk.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
d0dd7f0c |
|
11-Nov-2015 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: store pcie gen mask and link width We'll need this later for pcie dpm. Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
1f7371b2 |
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02-Dec-2015 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amd/powerplay: add basic powerplay framework amdgpu_pp_ip_funcs is introduced to handle the two code paths, the legacy one and the new powerplay implementation. CONFIG_DRM_AMD_POWERPLAY kernel configuration option is introduced for the powerplay component. v4: squash in fixes v3: register debugfs file when powerplay module enable v2: add amdgpu_ucode_init_bo in hw init when amdgpu_powerplay enable. Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Jammy Zhou <Jammy.Zhou@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
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#
1eb22bd3 |
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24-Nov-2015 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: add read_bios_from_rom callback for CI parts Read the vbios image directly from the rom. Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Monk Liu <monk.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
e79d5c08 |
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06-Oct-2015 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: check before checking pci bridge registers Make sure we are not the root device before attempting to read the pcie bridge registers to check the pcie gen speeed. Fixes a crash when the device is passed through to a VM. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
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#
2f7d10b3 |
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21-Jul-2015 |
Jammy Zhou <Jammy.Zhou@amd.com> |
drm/amdgpu: merge amdgpu_family.h into amd_shared.h (v2) Make the definitions common for all driver components v2: fix kfd Signed-off-by: Jammy Zhou <Jammy.Zhou@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
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#
130e0371 |
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12-Jun-2015 |
Oded Gabbay <oded.gabbay@gmail.com> |
drm/amdgpu: Add H/W agnostic amdgpu <--> amdkfd interface This patch adds an interface file between amdgpu and amdkfd. This interface file is H/W agnostic, thus containing functions that operate the same for any AMD APU/GPU H/W generation. The functions in this interface mirror (some) of the functions in radeon_kfd.c (the radeon<-->amdkfd interface file). The main functions are: - amdgpu_amdkfd_init - initialize the amdkfd module - amdgpu_amdkfd_load_interface - load the H/W interface according to the currently probed device - amdgpu_amdkfd_device_probe - probe the device in amdkfd - amdgpu_amdkfd_device_init - initialize the device in amdkfd - amdgpu_amdkfd_interrupt - call the ISR of amdkfd - amdgpu_amdkfd_suspend - suspend callback from amdgpu - amdgpu_amdkfd_resume - resume callback from amdgpu This patch also modifies the relevant amdgpu files, to use this new interface. Signed-off-by: Oded Gabbay <oded.gabbay@gmail.com>
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#
d8d090b7 |
|
26-Jun-2015 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: allocate ip_block_enabled memory in common code Remove duplication across asic families and make it symmetric with the freeing of the code in amdgpu_device.c Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
5fc3aeeb |
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22-May-2015 |
yanyang1 <young.yang@amd.com> |
drm/amdgpu: rename amdgpu_ip_funcs to amd_ip_funcs (v2) The structure is renamed and moved to amd_shared.h to make the component independent. This makes it easier to add new components in the future. v2: fix include path Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com> Signed-off-by: yanyang1 <young.yang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
a2e73f56 |
|
20-Apr-2015 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: Add support for CIK parts This patch adds support for CIK parts. These parts are also supported by radeon which is the preferred option, so there is a config option to enable support for CIK parts in amdgpu for testing. Acked-by: Christian König <christian.koenig@amd.com> Acked-by: Jammy Zhou <Jammy.Zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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