/linux-master/drivers/media/radio/wl128x/ |
H A D | fmdrv_rx.c | 70 ret = fmc_send_cmd(fmdev, FLAG_GET, REG_RD, NULL, 2, NULL, NULL); 102 ret = fmc_send_cmd(fmdev, FREQ_SET, REG_RD, NULL, 2, &curr_frq, &resp_len); 174 ret = fmc_send_cmd(fmdev, FREQ_SET, REG_RD, NULL, 214 ret = fmc_send_cmd(fmdev, FLAG_GET, REG_RD, NULL, 2, NULL, NULL); 270 ret = fmc_send_cmd(fmdev, FREQ_SET, REG_RD, NULL, 2, 516 ret = fmc_send_cmd(fmdev, RSSI_LVL_GET, REG_RD, NULL, 2, 607 ret = fmc_send_cmd(fmdev, MOST_MODE_SET, REG_RD, NULL, 2, 687 ret = fmc_send_cmd(fmdev, FLAG_GET, REG_RD, NULL, 2,
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H A D | fmdrv_common.h | 15 #define REG_RD 0x1 macro
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H A D | fmdrv_common.c | 568 if (!fm_send_cmd(fmdev, FLAG_GET, REG_RD, NULL, sizeof(flag), NULL)) 620 if (!fm_send_cmd(fmdev, RDS_DATA_GET, REG_RD, NULL, 965 if (!fm_send_cmd(fmdev, FREQ_SET, REG_RD, NULL, sizeof(payload), NULL)) 1337 if (fmc_send_cmd(fmdev, ASIC_ID_GET, REG_RD, NULL, 1341 if (fmc_send_cmd(fmdev, ASIC_VER_GET, REG_RD, NULL,
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H A D | fmdrv_tx.c | 359 ret = fmc_send_cmd(fmdev, READ_FMANT_TUNE_VALUE, REG_RD,
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/linux-master/drivers/net/ethernet/broadcom/bnx2x/ |
H A D | bnx2x_init.h | 210 u32 curr_cos = REG_RD(bp, QM_REG_QVOQIDX_0 + q_num * 4); 237 reg_bit_map = REG_RD(bp, reg_addr); 242 reg_bit_map = REG_RD(bp, reg_addr); 250 reg_bit_map = REG_RD(bp, reg_addr); 681 reg_val = REG_RD(bp, mcp_attn_ctl_regs[i].addr); 744 reg_val = REG_RD(bp, bnx2x_blocks_parity_data[i]. 755 reg_val = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_MCP);
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H A D | bnx2x_main.c | 632 data[i] = REG_RD(bp, src_addr + i*4); 740 regs[j] = REG_RD(bp, bar_storm_intmem[storm] + 792 val = REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER); 793 if (val == REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER)) 813 mark = REG_RD(bp, addr); 821 mark = REG_RD(bp, addr); 834 data[word] = htonl(REG_RD(bp, offset + 4*word)); 842 data[word] = htonl(REG_RD(bp, offset + 4*word)); 858 u32 val = REG_RD(bp, addr); 885 if (REG_RD(b [all...] |
H A D | bnx2x_link.c | 222 u32 val = REG_RD(bp, reg); 231 u32 val = REG_RD(bp, reg); 254 REG_RD(bp, params->lfa_base + 269 link_status = REG_RD(bp, params->shmem_base + 298 saved_val = REG_RD(bp, params->lfa_base + 307 saved_val = REG_RD(bp, params->lfa_base + 316 saved_val = REG_RD(bp, params->lfa_base + 326 cur_speed_cap_mask = REG_RD(bp, params->lfa_base + 339 REG_RD(bp, params->lfa_base + 349 eee_status = REG_RD(b [all...] |
H A D | bnx2x_init_ops.h | 262 REG_RD(bp, addr); 518 val = REG_RD(bp, write_arb_addr[i].l); 522 val = REG_RD(bp, write_arb_addr[i].add); 526 val = REG_RD(bp, write_arb_addr[i].ubound); 587 val = REG_RD(bp, PCIE_REG_PCIER_TL_HDR_FC_ST);
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H A D | bnx2x_ethtool.c | 879 *p++ = REG_RD(bp, addr); 908 *p++ = REG_RD(bp, idle_reg_addrs[i].addr + j*4); 917 *p++ = REG_RD(bp, reg_addrs[i].addr + j*4); 925 *p++ = REG_RD(bp, wreg_addr_p->addr + i*4); 932 *p++ = REG_RD(bp, addr + j*4); 1120 mbi = REG_RD(bp, ext_dev_info_offset + 1270 val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB); 1303 val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB); 1325 val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE); 1337 val = REG_RD(b [all...] |
H A D | bnx2x_self_test.c | 2955 REG_RD(bp, rec->reg1 + i * rec->incr); 2957 REG_RD(bp, rec->reg1 + i * rec->incr + 4); 2995 if ((REG_RD(bp, (rec->reg2 + i * 4)) & 0x1) != 0x1) 2999 REG_RD(bp, (rec->reg1 + i * rec->incr)); 3000 REG_RD(bp, (rec->reg1 + i * rec->incr + 4)); 3002 REG_RD(bp, (rec->reg1 + i * rec->incr + 8)); 3003 REG_RD(bp, (rec->reg1 + i * rec->incr + 12)); 3017 rec->pred_args.val2 = REG_RD(bp, rec->reg3 + i * 4); 3072 rec.pred_args.val1 = REG_RD(bp, rec.reg1); 3087 REG_RD(b [all...] |
H A D | bnx2x.h | 171 #define REG_RD(bp, offset) readl(REG_ADDR(bp, offset)) macro 212 #define SHMEM_RD(bp, field) REG_RD(bp, SHMEM_ADDR(bp, field)) 217 #define SHMEM2_RD(bp, field) REG_RD(bp, SHMEM2_ADDR(bp, field)) 224 #define MF_CFG_RD(bp, field) REG_RD(bp, MF_CFG_ADDR(bp, field)) 227 #define MF2_CFG_RD(bp, field) REG_RD(bp, MF2_CFG_ADDR(bp, field)) 233 #define EMAC_RD(bp, reg) REG_RD(bp, emac_base + reg) 2081 val = REG_RD(bp, reg);
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H A D | bnx2x_cmn.h | 700 u32 result = REG_RD(bp, hc_addr); 709 u32 result = REG_RD(bp, igu_addr);
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H A D | bnx2x_stats.c | 863 estats->eee_tx_lpi += REG_RD(bp, lpi_reg); 1633 REG_RD(bp, NIG_REG_STAT0_BRB_DISCARD + port*0x38); 1635 REG_RD(bp, NIG_REG_STAT0_BRB_TRUNCATE + port*0x38);
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H A D | bnx2x_sriov.c | 730 val = REG_RD(bp, IGU_REG_VF_CONFIGURATION); 1086 val = REG_RD(bp, IGU_REG_MAPPING_MEMORY + sb_id * 4); 1155 val = REG_RD(bp, PCICFG_OFFSET + GRC_CONFIG_REG_PF_INIT_VF); 1979 val = REG_RD(bp, IGU_REG_VF_CONFIGURATION);
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H A D | bnx2x_dcb.c | 54 /* helpers: read/write len bytes from addr into buff by REG_RD/REG_WR */ 60 *buff = REG_RD(bp, addr + i);
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H A D | bnx2x_cmn.c | 2382 loaded_fw = REG_RD(bp, XSEM_REG_PRAM);
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/linux-master/arch/x86/crypto/ |
H A D | sha1_avx2_x86_64_asm.S | 88 #define REG_RD %rax define 111 .set RD, REG_RD
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/linux-master/drivers/scsi/bnx2i/ |
H A D | bnx2i.h | 128 #define REG_RD(__hba, offset) \ macro
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H A D | bnx2i_hwi.c | 2724 config2 = REG_RD(ep->hba, BNX2_MQ_CONFIG2);
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/linux-master/drivers/net/ethernet/qlogic/qed/ |
H A D | qed_dev.c | 2492 if (REG_RD(p_hwfn, addr)) { 2505 while (!REG_RD(p_hwfn, addr) && count--) 2508 if (REG_RD(p_hwfn, addr)) 3565 p_hwfn->hw_info.opaque_fid = (u16)REG_RD(p_hwfn, 3568 p_hwfn->hw_info.concrete_fid = REG_RD(p_hwfn, PXP_PF_ME_CONCRETE_ADDR); 4670 if (REG_RD(p_hwfn, PXP_PF_ME_OPAQUE_ADDR) == 0xffffffff) {
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H A D | qed_vf.c | 451 p_hwfn->hw_info.opaque_fid = (u16)REG_RD(p_hwfn, reg); 454 p_hwfn->hw_info.concrete_fid = REG_RD(p_hwfn, reg);
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H A D | qed_hw.c | 234 u32 val = REG_RD(p_hwfn, bar_addr);
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H A D | qed.h | 961 #define REG_RD(cdev, offset) readl(REG_ADDR(cdev, offset)) macro
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H A D | qed_int.c | 2295 intr_status_lo = REG_RD(p_hwfn, 2298 intr_status_hi = REG_RD(p_hwfn,
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