Searched refs:REG_RD (Results 1 - 24 of 24) sorted by relevance

/linux-master/drivers/media/radio/wl128x/
H A Dfmdrv_rx.c70 ret = fmc_send_cmd(fmdev, FLAG_GET, REG_RD, NULL, 2, NULL, NULL);
102 ret = fmc_send_cmd(fmdev, FREQ_SET, REG_RD, NULL, 2, &curr_frq, &resp_len);
174 ret = fmc_send_cmd(fmdev, FREQ_SET, REG_RD, NULL,
214 ret = fmc_send_cmd(fmdev, FLAG_GET, REG_RD, NULL, 2, NULL, NULL);
270 ret = fmc_send_cmd(fmdev, FREQ_SET, REG_RD, NULL, 2,
516 ret = fmc_send_cmd(fmdev, RSSI_LVL_GET, REG_RD, NULL, 2,
607 ret = fmc_send_cmd(fmdev, MOST_MODE_SET, REG_RD, NULL, 2,
687 ret = fmc_send_cmd(fmdev, FLAG_GET, REG_RD, NULL, 2,
H A Dfmdrv_common.h15 #define REG_RD 0x1 macro
H A Dfmdrv_common.c568 if (!fm_send_cmd(fmdev, FLAG_GET, REG_RD, NULL, sizeof(flag), NULL))
620 if (!fm_send_cmd(fmdev, RDS_DATA_GET, REG_RD, NULL,
965 if (!fm_send_cmd(fmdev, FREQ_SET, REG_RD, NULL, sizeof(payload), NULL))
1337 if (fmc_send_cmd(fmdev, ASIC_ID_GET, REG_RD, NULL,
1341 if (fmc_send_cmd(fmdev, ASIC_VER_GET, REG_RD, NULL,
H A Dfmdrv_tx.c359 ret = fmc_send_cmd(fmdev, READ_FMANT_TUNE_VALUE, REG_RD,
/linux-master/drivers/net/ethernet/broadcom/bnx2x/
H A Dbnx2x_init.h210 u32 curr_cos = REG_RD(bp, QM_REG_QVOQIDX_0 + q_num * 4);
237 reg_bit_map = REG_RD(bp, reg_addr);
242 reg_bit_map = REG_RD(bp, reg_addr);
250 reg_bit_map = REG_RD(bp, reg_addr);
681 reg_val = REG_RD(bp, mcp_attn_ctl_regs[i].addr);
744 reg_val = REG_RD(bp, bnx2x_blocks_parity_data[i].
755 reg_val = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_MCP);
H A Dbnx2x_main.c632 data[i] = REG_RD(bp, src_addr + i*4);
740 regs[j] = REG_RD(bp, bar_storm_intmem[storm] +
792 val = REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER);
793 if (val == REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER))
813 mark = REG_RD(bp, addr);
821 mark = REG_RD(bp, addr);
834 data[word] = htonl(REG_RD(bp, offset + 4*word));
842 data[word] = htonl(REG_RD(bp, offset + 4*word));
858 u32 val = REG_RD(bp, addr);
885 if (REG_RD(b
[all...]
H A Dbnx2x_link.c222 u32 val = REG_RD(bp, reg);
231 u32 val = REG_RD(bp, reg);
254 REG_RD(bp, params->lfa_base +
269 link_status = REG_RD(bp, params->shmem_base +
298 saved_val = REG_RD(bp, params->lfa_base +
307 saved_val = REG_RD(bp, params->lfa_base +
316 saved_val = REG_RD(bp, params->lfa_base +
326 cur_speed_cap_mask = REG_RD(bp, params->lfa_base +
339 REG_RD(bp, params->lfa_base +
349 eee_status = REG_RD(b
[all...]
H A Dbnx2x_init_ops.h262 REG_RD(bp, addr);
518 val = REG_RD(bp, write_arb_addr[i].l);
522 val = REG_RD(bp, write_arb_addr[i].add);
526 val = REG_RD(bp, write_arb_addr[i].ubound);
587 val = REG_RD(bp, PCIE_REG_PCIER_TL_HDR_FC_ST);
H A Dbnx2x_ethtool.c879 *p++ = REG_RD(bp, addr);
908 *p++ = REG_RD(bp, idle_reg_addrs[i].addr + j*4);
917 *p++ = REG_RD(bp, reg_addrs[i].addr + j*4);
925 *p++ = REG_RD(bp, wreg_addr_p->addr + i*4);
932 *p++ = REG_RD(bp, addr + j*4);
1120 mbi = REG_RD(bp, ext_dev_info_offset +
1270 val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB);
1303 val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB);
1325 val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE);
1337 val = REG_RD(b
[all...]
H A Dbnx2x_self_test.c2955 REG_RD(bp, rec->reg1 + i * rec->incr);
2957 REG_RD(bp, rec->reg1 + i * rec->incr + 4);
2995 if ((REG_RD(bp, (rec->reg2 + i * 4)) & 0x1) != 0x1)
2999 REG_RD(bp, (rec->reg1 + i * rec->incr));
3000 REG_RD(bp, (rec->reg1 + i * rec->incr + 4));
3002 REG_RD(bp, (rec->reg1 + i * rec->incr + 8));
3003 REG_RD(bp, (rec->reg1 + i * rec->incr + 12));
3017 rec->pred_args.val2 = REG_RD(bp, rec->reg3 + i * 4);
3072 rec.pred_args.val1 = REG_RD(bp, rec.reg1);
3087 REG_RD(b
[all...]
H A Dbnx2x.h171 #define REG_RD(bp, offset) readl(REG_ADDR(bp, offset)) macro
212 #define SHMEM_RD(bp, field) REG_RD(bp, SHMEM_ADDR(bp, field))
217 #define SHMEM2_RD(bp, field) REG_RD(bp, SHMEM2_ADDR(bp, field))
224 #define MF_CFG_RD(bp, field) REG_RD(bp, MF_CFG_ADDR(bp, field))
227 #define MF2_CFG_RD(bp, field) REG_RD(bp, MF2_CFG_ADDR(bp, field))
233 #define EMAC_RD(bp, reg) REG_RD(bp, emac_base + reg)
2081 val = REG_RD(bp, reg);
H A Dbnx2x_cmn.h700 u32 result = REG_RD(bp, hc_addr);
709 u32 result = REG_RD(bp, igu_addr);
H A Dbnx2x_stats.c863 estats->eee_tx_lpi += REG_RD(bp, lpi_reg);
1633 REG_RD(bp, NIG_REG_STAT0_BRB_DISCARD + port*0x38);
1635 REG_RD(bp, NIG_REG_STAT0_BRB_TRUNCATE + port*0x38);
H A Dbnx2x_sriov.c730 val = REG_RD(bp, IGU_REG_VF_CONFIGURATION);
1086 val = REG_RD(bp, IGU_REG_MAPPING_MEMORY + sb_id * 4);
1155 val = REG_RD(bp, PCICFG_OFFSET + GRC_CONFIG_REG_PF_INIT_VF);
1979 val = REG_RD(bp, IGU_REG_VF_CONFIGURATION);
H A Dbnx2x_dcb.c54 /* helpers: read/write len bytes from addr into buff by REG_RD/REG_WR */
60 *buff = REG_RD(bp, addr + i);
H A Dbnx2x_cmn.c2382 loaded_fw = REG_RD(bp, XSEM_REG_PRAM);
/linux-master/arch/x86/crypto/
H A Dsha1_avx2_x86_64_asm.S88 #define REG_RD %rax define
111 .set RD, REG_RD
/linux-master/drivers/scsi/bnx2i/
H A Dbnx2i.h128 #define REG_RD(__hba, offset) \ macro
H A Dbnx2i_hwi.c2724 config2 = REG_RD(ep->hba, BNX2_MQ_CONFIG2);
/linux-master/drivers/net/ethernet/qlogic/qed/
H A Dqed_dev.c2492 if (REG_RD(p_hwfn, addr)) {
2505 while (!REG_RD(p_hwfn, addr) && count--)
2508 if (REG_RD(p_hwfn, addr))
3565 p_hwfn->hw_info.opaque_fid = (u16)REG_RD(p_hwfn,
3568 p_hwfn->hw_info.concrete_fid = REG_RD(p_hwfn, PXP_PF_ME_CONCRETE_ADDR);
4670 if (REG_RD(p_hwfn, PXP_PF_ME_OPAQUE_ADDR) == 0xffffffff) {
H A Dqed_vf.c451 p_hwfn->hw_info.opaque_fid = (u16)REG_RD(p_hwfn, reg);
454 p_hwfn->hw_info.concrete_fid = REG_RD(p_hwfn, reg);
H A Dqed_hw.c234 u32 val = REG_RD(p_hwfn, bar_addr);
H A Dqed.h961 #define REG_RD(cdev, offset) readl(REG_ADDR(cdev, offset)) macro
H A Dqed_int.c2295 intr_status_lo = REG_RD(p_hwfn,
2298 intr_status_hi = REG_RD(p_hwfn,

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