1// SPDX-License-Identifier: GPL-2.0
2#include <linux/kernel.h>
3#include <linux/netdevice.h>
4#include "bnx2x.h"
5
6#define NA 0xCD
7
8#define IDLE_CHK_E1			0x01
9#define IDLE_CHK_E1H			0x02
10#define IDLE_CHK_E2			0x04
11#define IDLE_CHK_E3A0			0x08
12#define IDLE_CHK_E3B0			0x10
13
14#define IDLE_CHK_ERROR			1
15#define IDLE_CHK_ERROR_NO_TRAFFIC	2
16#define IDLE_CHK_WARNING		3
17
18#define MAX_FAIL_MSG 256
19
20/* statistics and error reporting */
21static int idle_chk_errors, idle_chk_warnings;
22
23/* masks for all chip types */
24static int is_e1, is_e1h, is_e2, is_e3a0, is_e3b0;
25
26/* struct for the argument list for a predicate in the self test databasei */
27struct st_pred_args {
28	u32 val1; /* value read from first register */
29	u32 val2; /* value read from second register, if applicable */
30	u32 imm1; /* 1st value in predicate condition, left-to-right */
31	u32 imm2; /* 2nd value in predicate condition, left-to-right */
32	u32 imm3; /* 3rd value in predicate condition, left-to-right */
33	u32 imm4; /* 4th value in predicate condition, left-to-right */
34};
35
36/* struct representing self test record - a single test */
37struct st_record {
38	u8 chip_mask;
39	u8 macro;
40	u32 reg1;
41	u32 reg2;
42	u16 loop;
43	u16 incr;
44	int (*bnx2x_predicate)(struct st_pred_args *pred_args);
45	u32 reg3;
46	u8 severity;
47	char *fail_msg;
48	struct st_pred_args pred_args;
49};
50
51/* predicates for self test */
52static int peq(struct st_pred_args *args)
53{
54	return (args->val1 == args->imm1);
55}
56
57static int pneq(struct st_pred_args *args)
58{
59	return (args->val1 != args->imm1);
60}
61
62static int pand_neq(struct st_pred_args *args)
63{
64	return ((args->val1 & args->imm1) != args->imm2);
65}
66
67static int pand_neq_x2(struct st_pred_args *args)
68{
69	return (((args->val1 & args->imm1) != args->imm2) &&
70		((args->val1 & args->imm3) != args->imm4));
71}
72
73static int pneq_err(struct st_pred_args *args)
74{
75	return ((args->val1 != args->imm1) && (idle_chk_errors > args->imm2));
76}
77
78static int pgt(struct st_pred_args *args)
79{
80	return (args->val1 > args->imm1);
81}
82
83static int pneq_r2(struct st_pred_args *args)
84{
85	return (args->val1 != args->val2);
86}
87
88static int plt_sub_r2(struct st_pred_args *args)
89{
90	return (args->val1 < (args->val2 - args->imm1));
91}
92
93static int pne_sub_r2(struct st_pred_args *args)
94{
95	return (args->val1 != (args->val2 - args->imm1));
96}
97
98static int prsh_and_neq(struct st_pred_args *args)
99{
100	return (((args->val1 >> args->imm1) & args->imm2) != args->imm3);
101}
102
103static int peq_neq_r2(struct st_pred_args *args)
104{
105	return ((args->val1 == args->imm1) && (args->val2 != args->imm2));
106}
107
108static int peq_neq_neq_r2(struct st_pred_args *args)
109{
110	return ((args->val1 == args->imm1) && (args->val2 != args->imm2) &&
111		(args->val2 != args->imm3));
112}
113
114/* struct holding the database of self test checks (registers and predicates) */
115/* lines start from 2 since line 1 is heading in csv */
116#define ST_DB_LINES 468
117static struct st_record st_database[ST_DB_LINES] = {
118/*line 2*/{(0x3), 1, 0x2114,
119	NA, 1, 0, pand_neq,
120	NA, IDLE_CHK_ERROR,
121	"PCIE: ucorr_err_status is not 0",
122	{NA, NA, 0x0FF010, 0, NA, NA} },
123
124/*line 3*/{(0x3), 1, 0x2114,
125	NA, 1, 0, pand_neq,
126	NA, IDLE_CHK_WARNING,
127	"PCIE: ucorr_err_status - Unsupported request error",
128	{NA, NA, 0x100000, 0, NA, NA} },
129
130/*line 4*/{(0x3), 1, 0x2120,
131	NA, 1, 0, pand_neq_x2,
132	NA, IDLE_CHK_WARNING,
133	"PCIE: corr_err_status is not 0x2000",
134	{NA, NA, 0x31C1, 0x2000, 0x31C1, 0} },
135
136/*line 5*/{(0x3), 1, 0x2814,
137	NA, 1, 0, pand_neq,
138	NA, IDLE_CHK_ERROR,
139	"PCIE: attentions register is not 0x40100",
140	{NA, NA, ~0x40100, 0, NA, NA} },
141
142/*line 6*/{(0x2), 1, 0x281c,
143	NA, 1, 0, pand_neq,
144	NA, IDLE_CHK_ERROR,
145	"PCIE: attentions register is not 0x40040100",
146	{NA, NA, ~0x40040100, 0, NA, NA} },
147
148/*line 7*/{(0x2), 1, 0x2820,
149	NA, 1, 0, pand_neq,
150	NA, IDLE_CHK_ERROR,
151	"PCIE: attentions register is not 0x40040100",
152	{NA, NA, ~0x40040100, 0, NA, NA} },
153
154/*line 8*/{(0x3), 1, PXP2_REG_PGL_EXP_ROM2,
155	NA, 1, 0, pneq,
156	NA, IDLE_CHK_WARNING,
157	"PXP2: There are outstanding read requests. Not all completios have arrived for read requests on tags that are marked with 0",
158	{NA, NA, 0xffffffff, NA, NA, NA} },
159
160/*line 9*/{(0x3), 2, 0x212c,
161	NA, 4, 4, pneq_err,
162	NA, IDLE_CHK_WARNING,
163	"PCIE: error packet header is not 0",
164	{NA, NA, 0, NA, NA, NA} },
165
166/*line 10*/{(0x1C), 1, 0x2104,
167	NA, 1, 0, pand_neq,
168	NA, IDLE_CHK_ERROR,
169	"PCIE: ucorr_err_status is not 0",
170	{NA, NA, 0x0FD010, 0, NA, NA} },
171
172/*line 11*/{(0x1C), 1, 0x2104,
173	NA, 1, 0, pand_neq,
174	NA, IDLE_CHK_WARNING,
175	"PCIE: ucorr_err_status - Unsupported request error",
176	{NA, NA, 0x100000, 0, NA, NA} },
177
178/*line 12*/{(0x1C), 1, 0x2104,
179	NA, 1, 0, pand_neq,
180	NA, IDLE_CHK_WARNING,
181	"PCIE: ucorr_err_status - Flow Control Protocol Error",
182	{NA, NA, 0x2000, 0, NA, NA} },
183
184/*line 13*/{(0x1C), 1, 0x2110,
185	NA, 1, 0, pand_neq_x2,
186	NA, IDLE_CHK_WARNING,
187	"PCIE: corr_err_status is not 0x2000",
188	{NA, NA, 0x31C1, 0x2000, 0x31C1, 0} },
189
190/*line 14*/{(0x1C), 1, 0x2814,
191	NA, 1, 0, pand_neq,
192	NA, IDLE_CHK_WARNING,
193	"PCIE: TTX_BRIDGE_FORWARD_ERR - Received master request while BME was 0",
194	{NA, NA, 0x2000000, 0, NA, NA} },
195
196/*line 15*/{(0x1C), 1, 0x2814,
197	NA, 1, 0, pand_neq,
198	NA, IDLE_CHK_ERROR,
199	"PCIE: Func 0 1: attentions register is not 0x2040902",
200	{NA, NA, ~0x2040902, 0, NA, NA} },
201
202/*line 16*/{(0x1C), 1, 0x2854,
203	NA, 1, 0, pand_neq,
204	NA, IDLE_CHK_ERROR,
205	"PCIE: Func 2 3 4: attentions register is not 0x10240902",
206	{NA, NA, ~0x10240902, 0, NA, NA} },
207
208/*line 17*/{(0x1C), 1, 0x285c,
209	NA, 1, 0, pand_neq,
210	NA, IDLE_CHK_ERROR,
211	"PCIE: Func 5 6 7: attentions register is not 0x10240902",
212	{NA, NA, ~0x10240902, 0, NA, NA} },
213
214/*line 18*/{(0x18), 1, 0x3040,
215	NA, 1, 0, pand_neq,
216	NA, IDLE_CHK_ERROR,
217	"PCIE: Overflow in DLP2TLP buffer",
218	{NA, NA, 0x2, 0, NA, NA} },
219
220/*line 19*/{(0x1C), 1, PXP2_REG_PGL_EXP_ROM2,
221	NA, 1, 0, pneq,
222	NA, IDLE_CHK_WARNING,
223	"PXP2: There are outstanding read requests for tags 0-31. Not all completios have arrived for read requests on tags that are marked with 0",
224	{NA, NA, 0xffffffff, NA, NA, NA} },
225
226/*line 20*/{(0x1C), 2, 0x211c,
227	NA, 4, 4, pneq_err,
228	NA, IDLE_CHK_WARNING,
229	"PCIE: error packet header is not 0",
230	{NA, NA, 0, NA, NA, NA} },
231
232/*line 21*/{(0x1C), 1, PGLUE_B_REG_INCORRECT_RCV_DETAILS,
233	NA, 1, 0, pneq,
234	NA, IDLE_CHK_ERROR,
235	"PGLUE_B: Packet received from PCIe not according to the rules",
236	{NA, NA, 0, NA, NA, NA} },
237
238/*line 22*/{(0x1C), 1, PGLUE_B_REG_WAS_ERROR_VF_31_0,
239	NA, 1, 0, pneq,
240	NA, IDLE_CHK_WARNING,
241	"PGLUE_B: was_error for VFs 0-31 is not 0",
242	{NA, NA, 0, NA, NA, NA} },
243
244/*line 23*/{(0x1C), 1, PGLUE_B_REG_WAS_ERROR_VF_63_32,
245	NA, 1, 0, pneq,
246	NA, IDLE_CHK_WARNING,
247	"PGLUE_B: was_error for VFs 32-63 is not 0",
248	{NA, NA, 0, NA, NA, NA} },
249
250/*line 24*/{(0x1C), 1, PGLUE_B_REG_WAS_ERROR_VF_95_64,
251	NA, 1, 0, pneq,
252	NA, IDLE_CHK_WARNING,
253	"PGLUE_B: was_error for VFs 64-95 is not 0",
254	{NA, NA, 0, NA, NA, NA} },
255
256/*line 25*/{(0x1C), 1, PGLUE_B_REG_WAS_ERROR_VF_127_96,
257	NA, 1, 0, pneq,
258	NA, IDLE_CHK_WARNING,
259	"PGLUE_B: was_error for VFs 96-127 is not 0",
260	{NA, NA, 0, NA, NA, NA} },
261
262/*line 26*/{(0x1C), 1, PGLUE_B_REG_WAS_ERROR_PF_7_0,
263	NA, 1, 0, pneq,
264	NA, IDLE_CHK_WARNING,
265	"PGLUE_B: was_error for PFs 0-7 is not 0",
266	{NA, NA, 0, NA, NA, NA} },
267
268/*line 27*/{(0x1C), 1, PGLUE_B_REG_RX_ERR_DETAILS,
269	NA, 1, 0, pneq,
270	NA, IDLE_CHK_WARNING,
271	"PGLUE_B: Completion received with error. (2:0) - PFID. (3) - VF_VALID. (9:4) - VFID. (11:10) - Error code : 0 - Completion Timeout; 1 - Unsupported Request; 2 - Completer Abort. (12) - valid bit",
272	{NA, NA, 0, NA, NA, NA} },
273
274/*line 28*/{(0x1C), 1, PGLUE_B_REG_RX_TCPL_ERR_DETAILS,
275	NA, 1, 0, pneq,
276	NA, IDLE_CHK_WARNING,
277	"PGLUE_B: ATS TCPL received with error. (2:0) - PFID. (3) - VF_VALID. (9:4) - VFID. (11:10) - Error code : 0 - Completion Timeout ; 1 - Unsupported Request; 2 - Completer Abort. (16:12) - OTB Entry ID. (17) - valid bit",
278	{NA, NA, 0, NA, NA, NA} },
279
280/*line 29*/{(0x1C), 1, PGLUE_B_REG_TX_ERR_WR_ADD_31_0,
281	NA, 1, 0, pneq,
282	NA, IDLE_CHK_WARNING,
283	"PGLUE_B: Error in master write. Address(31:0) is not 0",
284	{NA, NA, 0, NA, NA, NA} },
285
286/*line 30*/{(0x1C), 1, PGLUE_B_REG_TX_ERR_WR_ADD_63_32,
287	NA, 1, 0, pneq,
288	NA, IDLE_CHK_WARNING,
289	"PGLUE_B: Error in master write. Address(63:32) is not 0",
290	{NA, NA, 0, NA, NA, NA} },
291
292/*line 31*/{(0x1C), 1, PGLUE_B_REG_TX_ERR_WR_DETAILS,
293	NA, 1, 0, pneq,
294	NA, IDLE_CHK_WARNING,
295	"PGLUE_B: Error in master write. Error details register is not 0. (4:0) VQID. (23:21) - PFID. (24) - VF_VALID. (30:25) - VFID",
296	{NA, NA, 0, NA, NA, NA} },
297
298/*line 32*/{(0x1C), 1, PGLUE_B_REG_TX_ERR_WR_DETAILS2,
299	NA, 1, 0, pneq,
300	NA, IDLE_CHK_WARNING,
301	"PGLUE_B: Error in master write. Error details 2nd register is not 0. (21) - was_error set; (22) - BME cleared; (23) - FID_enable cleared; (24) - VF with parent PF FLR_request or IOV_disable_request",
302	{NA, NA, 0, NA, NA, NA} },
303
304/*line 33*/{(0x1C), 1, PGLUE_B_REG_TX_ERR_RD_ADD_31_0,
305	NA, 1, 0, pneq,
306	NA, IDLE_CHK_WARNING,
307	"PGLUE: Error in master read address(31:0) is not 0",
308	{NA, NA, 0, NA, NA, NA} },
309
310/*line 34*/{(0x1C), 1, PGLUE_B_REG_TX_ERR_RD_ADD_63_32,
311	NA, 1, 0, pneq,
312	NA, IDLE_CHK_WARNING,
313	"PGLUE_B: Error in master read address(63:32) is not 0",
314	{NA, NA, 0, NA, NA, NA} },
315
316/*line 35*/{(0x1C), 1, PGLUE_B_REG_TX_ERR_RD_DETAILS,
317	NA, 1, 0, pneq,
318	NA, IDLE_CHK_WARNING,
319	"PGLUE_B: Error in master read Error details register is not 0. (4:0) VQID. (23:21) - PFID. (24) - VF_VALID. (30:25) - VFID",
320	{NA, NA, 0, NA, NA, NA} },
321
322/*line 36*/{(0x1C), 1, PGLUE_B_REG_TX_ERR_RD_DETAILS2,
323	NA, 1, 0, pneq,
324	NA, IDLE_CHK_WARNING,
325	"PGLUE_B: Error in master read Error details 2nd register is not 0. (21) - was_error set; (22) - BME cleared; (23) - FID_enable cleared; (24) - VF with parent PF FLR_request or IOV_disable_request",
326	{NA, NA, 0, NA, NA, NA} },
327
328/*line 37*/{(0x1C), 1, PGLUE_B_REG_VF_LENGTH_VIOLATION_DETAILS,
329	NA, 1, 0, pneq,
330	NA, IDLE_CHK_WARNING,
331	"PGLUE_B: Target VF length violation access",
332	{NA, NA, 0, NA, NA, NA} },
333
334/*line 38*/{(0x1C), 1, PGLUE_B_REG_VF_GRC_SPACE_VIOLATION_DETAILS,
335	NA, 1, 0, pneq,
336	NA, IDLE_CHK_WARNING,
337	"PGLUE_B: Target VF GRC space access failed permission check",
338	{NA, NA, 0, NA, NA, NA} },
339
340/*line 39*/{(0x1C), 1, PGLUE_B_REG_TAGS_63_32,
341	NA, 1, 0, pneq,
342	NA, IDLE_CHK_WARNING,
343	"PGLUE_B: There are outstanding read requests for tags 32-63. Not all completios have arrived for read requests on tags that are marked with 0",
344	{NA, NA, 0xffffffff, NA, NA, NA} },
345
346/*line 40*/{(0x1C), 3, PXP_REG_HST_VF_DISABLED_ERROR_VALID,
347	PXP_REG_HST_VF_DISABLED_ERROR_DATA, 1, 0, pneq,
348	NA, IDLE_CHK_WARNING,
349	"PXP: Access to disabled VF took place",
350	{NA, NA, 0, NA, NA, NA} },
351
352/*line 41*/{(0x1C), 1, PXP_REG_HST_PER_VIOLATION_VALID,
353	NA, 1, 0, pneq,
354	NA, IDLE_CHK_WARNING,
355	"PXP: Zone A permission violation occurred",
356	{NA, NA, 0, NA, NA, NA} },
357
358/*line 42*/{(0x1C), 1, PXP_REG_HST_INCORRECT_ACCESS_VALID,
359	NA, 1, 0, pneq,
360	NA, IDLE_CHK_WARNING,
361	"PXP: Incorrect transaction took place",
362	{NA, NA, 0, NA, NA, NA} },
363
364/*line 43*/{(0x1C), 1, PXP2_REG_RD_CPL_ERR_DETAILS,
365	NA, 1, 0, pneq,
366	NA, IDLE_CHK_WARNING,
367	"PXP2: Completion received with error. Error details register is not 0. (15:0) - ECHO. (28:16) - Sub Request length plus start_offset_2_0 minus 1",
368	{NA, NA, 0, NA, NA, NA} },
369
370/*line 44*/{(0x1C), 1, PXP2_REG_RD_CPL_ERR_DETAILS2,
371	NA, 1, 0, pneq,
372	NA, IDLE_CHK_WARNING,
373	"PXP2: Completion received with error. Error details 2nd register is not 0. (4:0) - VQ ID. (8:5) - client ID. (9) - valid bit",
374	{NA, NA, 0, NA, NA, NA} },
375
376/*line 45*/{(0x1F), 1, PXP2_REG_RQ_VQ0_ENTRY_CNT,
377	NA, 1, 0, pneq,
378	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
379	"PXP2: VQ0 is not empty",
380	{NA, NA, 0, NA, NA, NA} },
381
382/*line 46*/{(0x1F), 1, PXP2_REG_RQ_VQ1_ENTRY_CNT,
383	NA, 1, 0, pneq,
384	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
385	"PXP2: VQ1 is not empty",
386	{NA, NA, 0, NA, NA, NA} },
387
388/*line 47*/{(0x1F), 1, PXP2_REG_RQ_VQ2_ENTRY_CNT,
389	NA, 1, 0, pneq,
390	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
391	"PXP2: VQ2 is not empty",
392	{NA, NA, 0, NA, NA, NA} },
393
394/*line 48*/{(0x1F), 1, PXP2_REG_RQ_VQ3_ENTRY_CNT,
395	NA, 1, 0, pgt,
396	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
397	"PXP2: VQ3 is not empty",
398	{NA, NA, 2, NA, NA, NA} },
399
400/*line 49*/{(0x1F), 1, PXP2_REG_RQ_VQ4_ENTRY_CNT,
401	NA, 1, 0, pneq,
402	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
403	"PXP2: VQ4 is not empty",
404	{NA, NA, 0, NA, NA, NA} },
405
406/*line 50*/{(0x1F), 1, PXP2_REG_RQ_VQ5_ENTRY_CNT,
407	NA, 1, 0, pneq,
408	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
409	"PXP2: VQ5 is not empty",
410	{NA, NA, 0, NA, NA, NA} },
411
412/*line 51*/{(0x1F), 1, PXP2_REG_RQ_VQ6_ENTRY_CNT,
413	NA, 1, 0, pneq,
414	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
415	"PXP2: VQ6 is not empty",
416	{NA, NA, 0, NA, NA, NA} },
417
418/*line 52*/{(0x1F), 1, PXP2_REG_RQ_VQ7_ENTRY_CNT,
419	NA, 1, 0, pneq,
420	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
421	"PXP2: VQ7 is not empty",
422	{NA, NA, 0, NA, NA, NA} },
423
424/*line 53*/{(0x1F), 1, PXP2_REG_RQ_VQ8_ENTRY_CNT,
425	NA, 1, 0, pneq,
426	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
427	"PXP2: VQ8 is not empty",
428	{NA, NA, 0, NA, NA, NA} },
429
430/*line 54*/{(0x1F), 1, PXP2_REG_RQ_VQ9_ENTRY_CNT,
431	NA, 1, 0, pneq,
432	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
433	"PXP2: VQ9 is not empty",
434	{NA, NA, 0, NA, NA, NA} },
435
436/*line 55*/{(0x1F), 1, PXP2_REG_RQ_VQ10_ENTRY_CNT,
437	NA, 1, 0, pneq,
438	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
439	"PXP2: VQ10 is not empty",
440	{NA, NA, 0, NA, NA, NA} },
441
442/*line 56*/{(0x1F), 1, PXP2_REG_RQ_VQ11_ENTRY_CNT,
443	NA, 1, 0, pneq,
444	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
445	"PXP2: VQ11 is not empty",
446	{NA, NA, 0, NA, NA, NA} },
447
448/*line 57*/{(0x1F), 1, PXP2_REG_RQ_VQ12_ENTRY_CNT,
449	NA, 1, 0, pneq,
450	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
451	"PXP2: VQ12 is not empty",
452	{NA, NA, 0, NA, NA, NA} },
453
454/*line 58*/{(0x1F), 1, PXP2_REG_RQ_VQ13_ENTRY_CNT,
455	NA, 1, 0, pneq,
456	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
457	"PXP2: VQ13 is not empty",
458	{NA, NA, 0, NA, NA, NA} },
459
460/*line 59*/{(0x1F), 1, PXP2_REG_RQ_VQ14_ENTRY_CNT,
461	NA, 1, 0, pneq,
462	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
463	"PXP2: VQ14 is not empty",
464	{NA, NA, 0, NA, NA, NA} },
465
466/*line 60*/{(0x1F), 1, PXP2_REG_RQ_VQ15_ENTRY_CNT,
467	NA, 1, 0, pneq,
468	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
469	"PXP2: VQ15 is not empty",
470	{NA, NA, 0, NA, NA, NA} },
471
472/*line 61*/{(0x1F), 1, PXP2_REG_RQ_VQ16_ENTRY_CNT,
473	NA, 1, 0, pneq,
474	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
475	"PXP2: VQ16 is not empty",
476	{NA, NA, 0, NA, NA, NA} },
477
478/*line 62*/{(0x1F), 1, PXP2_REG_RQ_VQ17_ENTRY_CNT,
479	NA, 1, 0, pneq,
480	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
481	"PXP2: VQ17 is not empty",
482	{NA, NA, 0, NA, NA, NA} },
483
484/*line 63*/{(0x1F), 1, PXP2_REG_RQ_VQ18_ENTRY_CNT,
485	NA, 1, 0, pneq,
486	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
487	"PXP2: VQ18 is not empty",
488	{NA, NA, 0, NA, NA, NA} },
489
490/*line 64*/{(0x1F), 1, PXP2_REG_RQ_VQ19_ENTRY_CNT,
491	NA, 1, 0, pneq,
492	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
493	"PXP2: VQ19 is not empty",
494	{NA, NA, 0, NA, NA, NA} },
495
496/*line 65*/{(0x1F), 1, PXP2_REG_RQ_VQ20_ENTRY_CNT,
497	NA, 1, 0, pneq,
498	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
499	"PXP2: VQ20 is not empty",
500	{NA, NA, 0, NA, NA, NA} },
501
502/*line 66*/{(0x1F), 1, PXP2_REG_RQ_VQ21_ENTRY_CNT,
503	NA, 1, 0, pneq,
504	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
505	"PXP2: VQ21 is not empty",
506	{NA, NA, 0, NA, NA, NA} },
507
508/*line 67*/{(0x1F), 1, PXP2_REG_RQ_VQ22_ENTRY_CNT,
509	NA, 1, 0, pneq,
510	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
511	"PXP2: VQ22 is not empty",
512	{NA, NA, 0, NA, NA, NA} },
513
514/*line 68*/{(0x1F), 1, PXP2_REG_RQ_VQ23_ENTRY_CNT,
515	NA, 1, 0, pneq,
516	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
517	"PXP2: VQ23 is not empty",
518	{NA, NA, 0, NA, NA, NA} },
519
520/*line 69*/{(0x1F), 1, PXP2_REG_RQ_VQ24_ENTRY_CNT,
521	NA, 1, 0, pneq,
522	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
523	"PXP2: VQ24 is not empty",
524	{NA, NA, 0, NA, NA, NA} },
525
526/*line 70*/{(0x1F), 1, PXP2_REG_RQ_VQ25_ENTRY_CNT,
527	NA, 1, 0, pneq,
528	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
529	"PXP2: VQ25 is not empty",
530	{NA, NA, 0, NA, NA, NA} },
531
532/*line 71*/{(0x1F), 1, PXP2_REG_RQ_VQ26_ENTRY_CNT,
533	NA, 1, 0, pneq,
534	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
535	"PXP2: VQ26 is not empty",
536	{NA, NA, 0, NA, NA, NA} },
537
538/*line 72*/{(0x1F), 1, PXP2_REG_RQ_VQ27_ENTRY_CNT,
539	NA, 1, 0, pneq,
540	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
541	"PXP2: VQ27 is not empty",
542	{NA, NA, 0, NA, NA, NA} },
543
544/*line 73*/{(0x1F), 1, PXP2_REG_RQ_VQ28_ENTRY_CNT,
545	NA, 1, 0, pneq,
546	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
547	"PXP2: VQ28 is not empty",
548	{NA, NA, 0, NA, NA, NA} },
549
550/*line 74*/{(0x1F), 1, PXP2_REG_RQ_VQ29_ENTRY_CNT,
551	NA, 1, 0, pneq,
552	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
553	"PXP2: VQ29 is not empty",
554	{NA, NA, 0, NA, NA, NA} },
555
556/*line 75*/{(0x1F), 1, PXP2_REG_RQ_VQ30_ENTRY_CNT,
557	NA, 1, 0, pneq,
558	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
559	"PXP2: VQ30 is not empty",
560	{NA, NA, 0, NA, NA, NA} },
561
562/*line 76*/{(0x1F), 1, PXP2_REG_RQ_VQ31_ENTRY_CNT,
563	NA, 1, 0, pneq,
564	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
565	"PXP2: VQ31 is not empty",
566	{NA, NA, 0, NA, NA, NA} },
567
568/*line 77*/{(0x1F), 1, PXP2_REG_RQ_UFIFO_NUM_OF_ENTRY,
569	NA, 1, 0, pneq,
570	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
571	"PXP2: rq_ufifo_num_of_entry is not 0",
572	{NA, NA, 0, NA, NA, NA} },
573
574/*line 78*/{(0x1F), 1, PXP2_REG_RQ_RBC_DONE,
575	NA, 1, 0, pneq,
576	NA, IDLE_CHK_ERROR,
577	"PXP2: rq_rbc_done is not 1",
578	{NA, NA, 1, NA, NA, NA} },
579
580/*line 79*/{(0x1F), 1, PXP2_REG_RQ_CFG_DONE,
581	NA, 1, 0, pneq,
582	NA, IDLE_CHK_ERROR,
583	"PXP2: rq_cfg_done is not 1",
584	{NA, NA, 1, NA, NA, NA} },
585
586/*line 80*/{(0x3), 1, PXP2_REG_PSWRQ_BW_CREDIT,
587	NA, 1, 0, pneq,
588	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
589	"PXP2: rq_read_credit and rq_write_credit are not 3",
590	{NA, NA, 0x1B, NA, NA, NA} },
591
592/*line 81*/{(0x1F), 1, PXP2_REG_RD_START_INIT,
593	NA, 1, 0, pneq,
594	NA, IDLE_CHK_ERROR,
595	"PXP2: rd_start_init is not 1",
596	{NA, NA, 1, NA, NA, NA} },
597
598/*line 82*/{(0x1F), 1, PXP2_REG_RD_INIT_DONE,
599	NA, 1, 0, pneq,
600	NA, IDLE_CHK_ERROR,
601	"PXP2: rd_init_done is not 1",
602	{NA, NA, 1, NA, NA, NA} },
603
604/*line 83*/{(0x1F), 3, PXP2_REG_RD_SR_CNT,
605	PXP2_REG_RD_SR_NUM_CFG, 1, 0, pne_sub_r2,
606	NA, IDLE_CHK_WARNING,
607	"PXP2: rd_sr_cnt is not equal to rd_sr_num_cfg",
608	{NA, NA, 1, NA, NA, NA} },
609
610/*line 84*/{(0x1F), 3, PXP2_REG_RD_BLK_CNT,
611	PXP2_REG_RD_BLK_NUM_CFG, 1, 0, pneq_r2,
612	NA, IDLE_CHK_WARNING,
613	"PXP2: rd_blk_cnt is not equal to rd_blk_num_cfg",
614	{NA, NA, NA, NA, NA, NA} },
615
616/*line 85*/{(0x1F), 3, PXP2_REG_RD_SR_CNT,
617	PXP2_REG_RD_SR_NUM_CFG, 1, 0, plt_sub_r2,
618	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
619	"PXP2: There are more than two unused SRs",
620	{NA, NA, 3, NA, NA, NA} },
621
622/*line 86*/{(0x1F), 3, PXP2_REG_RD_BLK_CNT,
623	PXP2_REG_RD_BLK_NUM_CFG, 1, 0, plt_sub_r2,
624	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
625	"PXP2: There are more than two unused blocks",
626	{NA, NA, 2, NA, NA, NA} },
627
628/*line 87*/{(0x1F), 1, PXP2_REG_RD_PORT_IS_IDLE_0,
629	NA, 1, 0, pneq,
630	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
631	"PXP2: P0 All delivery ports are not idle",
632	{NA, NA, 1, NA, NA, NA} },
633
634/*line 88*/{(0x1F), 1, PXP2_REG_RD_PORT_IS_IDLE_1,
635	NA, 1, 0, pneq,
636	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
637	"PXP2: P1 All delivery ports are not idle",
638	{NA, NA, 1, NA, NA, NA} },
639
640/*line 89*/{(0x1F), 2, PXP2_REG_RD_ALMOST_FULL_0,
641	NA, 11, 4, pneq,
642	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
643	"PXP2: rd_almost_full is not 0",
644	{NA, NA, 0, NA, NA, NA} },
645
646/*line 90*/{(0x1F), 1, PXP2_REG_RD_DISABLE_INPUTS,
647	NA, 1, 0, pneq,
648	NA, IDLE_CHK_ERROR,
649	"PXP2: PSWRD inputs are disabled",
650	{NA, NA, 0, NA, NA, NA} },
651
652/*line 91*/{(0x1F), 1, PXP2_REG_HST_HEADER_FIFO_STATUS,
653	NA, 1, 0, pneq,
654	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
655	"PXP2: HST header FIFO status is not 0",
656	{NA, NA, 0, NA, NA, NA} },
657
658/*line 92*/{(0x1F), 1, PXP2_REG_HST_DATA_FIFO_STATUS,
659	NA, 1, 0, pneq,
660	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
661	"PXP2: HST data FIFO status is not 0",
662	{NA, NA, 0, NA, NA, NA} },
663
664/*line 93*/{(0x3), 1, PXP2_REG_PGL_WRITE_BLOCKED,
665	NA, 1, 0, pneq,
666	NA, IDLE_CHK_ERROR,
667	"PXP2: pgl_write_blocked is not 0",
668	{NA, NA, 0, NA, NA, NA} },
669
670/*line 94*/{(0x3), 1, PXP2_REG_PGL_READ_BLOCKED,
671	NA, 1, 0, pneq,
672	NA, IDLE_CHK_ERROR,
673	"PXP2: pgl_read_blocked is not 0",
674	{NA, NA, 0, NA, NA, NA} },
675
676/*line 95*/{(0x1C), 1, PXP2_REG_PGL_WRITE_BLOCKED,
677	NA, 1, 0, pneq,
678	NA, IDLE_CHK_WARNING,
679	"PXP2: pgl_write_blocked is not 0",
680	{NA, NA, 0, NA, NA, NA} },
681
682/*line 96*/{(0x1C), 1, PXP2_REG_PGL_READ_BLOCKED,
683	NA, 1, 0, pneq,
684	NA, IDLE_CHK_WARNING,
685	"PXP2: pgl_read_blocked is not 0",
686	{NA, NA, 0, NA, NA, NA} },
687
688/*line 97*/{(0x1F), 1, PXP2_REG_PGL_TXW_CDTS,
689	NA, 1, 0, prsh_and_neq,
690	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
691	"PXP2: There is data which is ready",
692	{NA, NA, 17, 1, 0, NA} },
693
694/*line 98*/{(0x1F), 1, PXP_REG_HST_ARB_IS_IDLE,
695	NA, 1, 0, pneq,
696	NA, IDLE_CHK_WARNING,
697	"PXP: HST arbiter is not idle",
698	{NA, NA, 1, NA, NA, NA} },
699
700/*line 99*/{(0x1F), 1, PXP_REG_HST_CLIENTS_WAITING_TO_ARB,
701	NA, 1, 0, pneq,
702	NA, IDLE_CHK_WARNING,
703	"PXP: HST one of the clients is waiting for delivery",
704	{NA, NA, 0, NA, NA, NA} },
705
706/*line 100*/{(0x1E), 1, PXP_REG_HST_DISCARD_INTERNAL_WRITES_STATUS,
707	NA, 1, 0, pneq,
708	NA, IDLE_CHK_WARNING,
709	"PXP: HST Close the gates: Discarding internal writes",
710	{NA, NA, 0, NA, NA, NA} },
711
712/*line 101*/{(0x1E), 1, PXP_REG_HST_DISCARD_DOORBELLS_STATUS,
713	NA, 1, 0, pneq,
714	NA, IDLE_CHK_WARNING,
715	"PXP: HST Close the gates: Discarding doorbells",
716	{NA, NA, 0, NA, NA, NA} },
717
718/*line 102*/{(0x1C), 1, PXP2_REG_RQ_GARB,
719	NA, 1, 0, pand_neq,
720	NA, IDLE_CHK_WARNING,
721	"PXP2: PSWRQ Close the gates is asserted. Check AEU AFTER_INVERT registers for parity errors",
722	{NA, NA, 0x1000, 0, NA, NA} },
723
724/*line 103*/{(0x1F), 1, DMAE_REG_GO_C0,
725	NA, 1, 0, pneq,
726	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
727	"DMAE: command 0 go is not 0",
728	{NA, NA, 0, NA, NA, NA} },
729
730/*line 104*/{(0x1F), 1, DMAE_REG_GO_C1,
731	NA, 1, 0, pneq,
732	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
733	"DMAE: command 1 go is not 0",
734	{NA, NA, 0, NA, NA, NA} },
735
736/*line 105*/{(0x1F), 1, DMAE_REG_GO_C2,
737	NA, 1, 0, pneq,
738	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
739	"DMAE: command 2 go is not 0",
740	{NA, NA, 0, NA, NA, NA} },
741
742/*line 106*/{(0x1F), 1, DMAE_REG_GO_C3,
743	NA, 1, 0, pneq,
744	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
745	"DMAE: command 3 go is not 0",
746	{NA, NA, 0, NA, NA, NA} },
747
748/*line 107*/{(0x1F), 1, DMAE_REG_GO_C4,
749	NA, 1, 0, pneq,
750	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
751	"DMAE: command 4 go is not 0",
752	{NA, NA, 0, NA, NA, NA} },
753
754/*line 108*/{(0x1F), 1, DMAE_REG_GO_C5,
755	NA, 1, 0, pneq,
756	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
757	"DMAE: command 5 go is not 0",
758	{NA, NA, 0, NA, NA, NA} },
759
760/*line 109*/{(0x1F), 1, DMAE_REG_GO_C6,
761	NA, 1, 0, pneq,
762	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
763	"DMAE: command 6 go is not 0",
764	{NA, NA, 0, NA, NA, NA} },
765
766/*line 110*/{(0x1F), 1, DMAE_REG_GO_C7,
767	NA, 1, 0, pneq,
768	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
769	"DMAE: command 7 go is not 0",
770	{NA, NA, 0, NA, NA, NA} },
771
772/*line 111*/{(0x1F), 1, DMAE_REG_GO_C8,
773	NA, 1, 0, pneq,
774	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
775	"DMAE: command 8 go is not 0",
776	{NA, NA, 0, NA, NA, NA} },
777
778/*line 112*/{(0x1F), 1, DMAE_REG_GO_C9,
779	NA, 1, 0, pneq,
780	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
781	"DMAE: command 9 go is not 0",
782	{NA, NA, 0, NA, NA, NA} },
783
784/*line 113*/{(0x1F), 1, DMAE_REG_GO_C10,
785	NA, 1, 0, pneq,
786	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
787	"DMAE: command 10 go is not 0",
788	{NA, NA, 0, NA, NA, NA} },
789
790/*line 114*/{(0x1F), 1, DMAE_REG_GO_C11,
791	NA, 1, 0, pneq,
792	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
793	"DMAE: command 11 go is not 0",
794	{NA, NA, 0, NA, NA, NA} },
795
796/*line 115*/{(0x1F), 1, DMAE_REG_GO_C12,
797	NA, 1, 0, pneq,
798	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
799	"DMAE: command 12 go is not 0",
800	{NA, NA, 0, NA, NA, NA} },
801
802/*line 116*/{(0x1F), 1, DMAE_REG_GO_C13,
803	NA, 1, 0, pneq,
804	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
805	"DMAE: command 13 go is not 0",
806	{NA, NA, 0, NA, NA, NA} },
807
808/*line 117*/{(0x1F), 1, DMAE_REG_GO_C14,
809	NA, 1, 0, pneq,
810	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
811	"DMAE: command 14 go is not 0",
812	{NA, NA, 0, NA, NA, NA} },
813
814/*line 118*/{(0x1F), 1, DMAE_REG_GO_C15,
815	NA, 1, 0, pneq,
816	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
817	"DMAE: command 15 go is not 0",
818	{NA, NA, 0, NA, NA, NA} },
819
820/*line 119*/{(0x1F), 1, CFC_REG_ERROR_VECTOR,
821	NA, 1, 0, pneq,
822	NA, IDLE_CHK_ERROR,
823	"CFC: error vector is not 0",
824	{NA, NA, 0, NA, NA, NA} },
825
826/*line 120*/{(0x1F), 1, CFC_REG_NUM_LCIDS_ARRIVING,
827	NA, 1, 0, pneq,
828	NA, IDLE_CHK_ERROR,
829	"CFC: number of arriving LCIDs is not 0",
830	{NA, NA, 0, NA, NA, NA} },
831
832/*line 121*/{(0x1F), 1, CFC_REG_NUM_LCIDS_ALLOC,
833	NA, 1, 0, pneq,
834	NA, IDLE_CHK_ERROR,
835	"CFC: number of alloc LCIDs is not 0",
836	{NA, NA, 0, NA, NA, NA} },
837
838/*line 122*/{(0x1F), 1, CFC_REG_NUM_LCIDS_LEAVING,
839	NA, 1, 0, pneq,
840	NA, IDLE_CHK_ERROR,
841	"CFC: number of leaving LCIDs is not 0",
842	{NA, NA, 0, NA, NA, NA} },
843
844/*line 123*/{(0x1F), 7, CFC_REG_INFO_RAM,
845	CFC_REG_CID_CAM, (CFC_REG_INFO_RAM_SIZE >> 4), 16, peq_neq_neq_r2,
846	CFC_REG_ACTIVITY_COUNTER, IDLE_CHK_ERROR_NO_TRAFFIC,
847	"CFC: AC is neither 0 nor 2 on connType 0 (ETH)",
848	{NA, NA, 0, 0, 2, NA} },
849
850/*line 124*/{(0x1F), 7, CFC_REG_INFO_RAM,
851	CFC_REG_CID_CAM, (CFC_REG_INFO_RAM_SIZE >> 4), 16, peq_neq_r2,
852	CFC_REG_ACTIVITY_COUNTER, IDLE_CHK_ERROR_NO_TRAFFIC,
853	"CFC: AC is not 0 on connType 1 (TOE)",
854	{NA, NA, 1, 0, NA, NA} },
855
856/*line 125*/{(0x1F), 7, CFC_REG_INFO_RAM,
857	CFC_REG_CID_CAM, (CFC_REG_INFO_RAM_SIZE >> 4), 16, peq_neq_r2,
858	CFC_REG_ACTIVITY_COUNTER, IDLE_CHK_ERROR_NO_TRAFFIC,
859	"CFC: AC is not 0 on connType 3 (iSCSI)",
860	{NA, NA, 3, 0, NA, NA} },
861
862/*line 126*/{(0x1F), 7, CFC_REG_INFO_RAM,
863	CFC_REG_CID_CAM, (CFC_REG_INFO_RAM_SIZE >> 4), 16, peq_neq_r2,
864	CFC_REG_ACTIVITY_COUNTER, IDLE_CHK_ERROR_NO_TRAFFIC,
865	"CFC: AC is not 0 on connType 4 (FCoE)",
866	{NA, NA, 4, 0, NA, NA} },
867
868/*line 127*/{(0x1F), 2, QM_REG_QTASKCTR_0,
869	NA, 64, 4, pneq,
870	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
871	"QM: Queue is not empty",
872	{NA, NA, 0, NA, NA, NA} },
873
874/*line 128*/{(0xF), 3, QM_REG_VOQCREDIT_0,
875	QM_REG_VOQINITCREDIT_0, 1, 0, pneq_r2,
876	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
877	"QM: VOQ_0, VOQ credit is not equal to initial credit",
878	{NA, NA, NA, NA, NA, NA} },
879
880/*line 129*/{(0xF), 3, QM_REG_VOQCREDIT_1,
881	QM_REG_VOQINITCREDIT_1, 1, 0, pneq_r2,
882	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
883	"QM: VOQ_1, VOQ credit is not equal to initial credit",
884	{NA, NA, NA, NA, NA, NA} },
885
886/*line 130*/{(0xF), 3, QM_REG_VOQCREDIT_4,
887	QM_REG_VOQINITCREDIT_4, 1, 0, pneq_r2,
888	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
889	"QM: VOQ_4, VOQ credit is not equal to initial credit",
890	{NA, NA, NA, NA, NA, NA} },
891
892/*line 131*/{(0x3), 3, QM_REG_PORT0BYTECRD,
893	QM_REG_BYTECRDINITVAL, 1, 0, pneq_r2,
894	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
895	"QM: P0 Byte credit is not equal to initial credit",
896	{NA, NA, NA, NA, NA, NA} },
897
898/*line 132*/{(0x3), 3, QM_REG_PORT1BYTECRD,
899	QM_REG_BYTECRDINITVAL, 1, 0, pneq_r2,
900	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
901	"QM: P1 Byte credit is not equal to initial credit",
902	{NA, NA, NA, NA, NA, NA} },
903
904/*line 133*/{(0x1F), 1, CCM_REG_CAM_OCCUP,
905	NA, 1, 0, pneq,
906	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
907	"CCM: XX protection CAM is not empty",
908	{NA, NA, 0, NA, NA, NA} },
909
910/*line 134*/{(0x1F), 1, TCM_REG_CAM_OCCUP,
911	NA, 1, 0, pneq,
912	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
913	"TCM: XX protection CAM is not empty",
914	{NA, NA, 0, NA, NA, NA} },
915
916/*line 135*/{(0x1F), 1, UCM_REG_CAM_OCCUP,
917	NA, 1, 0, pneq,
918	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
919	"UCM: XX protection CAM is not empty",
920	{NA, NA, 0, NA, NA, NA} },
921
922/*line 136*/{(0x1F), 1, XCM_REG_CAM_OCCUP,
923	NA, 1, 0, pneq,
924	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
925	"XCM: XX protection CAM is not empty",
926	{NA, NA, 0, NA, NA, NA} },
927
928/*line 137*/{(0x1F), 1, BRB1_REG_NUM_OF_FULL_BLOCKS,
929	NA, 1, 0, pneq,
930	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
931	"BRB1: BRB is not empty",
932	{NA, NA, 0, NA, NA, NA} },
933
934/*line 138*/{(0x1F), 1, CSEM_REG_SLEEP_THREADS_VALID,
935	NA, 1, 0, pneq,
936	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
937	"CSEM: There are sleeping threads",
938	{NA, NA, 0, NA, NA, NA} },
939
940/*line 139*/{(0x1F), 1, TSEM_REG_SLEEP_THREADS_VALID,
941	NA, 1, 0, pneq,
942	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
943	"TSEM: There are sleeping threads",
944	{NA, NA, 0, NA, NA, NA} },
945
946/*line 140*/{(0x1F), 1, USEM_REG_SLEEP_THREADS_VALID,
947	NA, 1, 0, pneq,
948	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
949	"USEM: There are sleeping threads",
950	{NA, NA, 0, NA, NA, NA} },
951
952/*line 141*/{(0x1F), 1, XSEM_REG_SLEEP_THREADS_VALID,
953	NA, 1, 0, pneq,
954	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
955	"XSEM: There are sleeping threads",
956	{NA, NA, 0, NA, NA, NA} },
957
958/*line 142*/{(0x1F), 1, CSEM_REG_SLOW_EXT_STORE_EMPTY,
959	NA, 1, 0, pneq,
960	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
961	"CSEM: External store FIFO is not empty",
962	{NA, NA, 1, NA, NA, NA} },
963
964/*line 143*/{(0x1F), 1, TSEM_REG_SLOW_EXT_STORE_EMPTY,
965	NA, 1, 0, pneq,
966	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
967	"TSEM: External store FIFO is not empty",
968	{NA, NA, 1, NA, NA, NA} },
969
970/*line 144*/{(0x1F), 1, USEM_REG_SLOW_EXT_STORE_EMPTY,
971	NA, 1, 0, pneq,
972	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
973	"USEM: External store FIFO is not empty",
974	{NA, NA, 1, NA, NA, NA} },
975
976/*line 145*/{(0x1F), 1, XSEM_REG_SLOW_EXT_STORE_EMPTY,
977	NA, 1, 0, pneq,
978	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
979	"XSEM: External store FIFO is not empty",
980	{NA, NA, 1, NA, NA, NA} },
981
982/*line 146*/{(0x1F), 1, CSDM_REG_SYNC_PARSER_EMPTY,
983	NA, 1, 0, pneq,
984	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
985	"CSDM: Parser serial FIFO is not empty",
986	{NA, NA, 1, NA, NA, NA} },
987
988/*line 147*/{(0x1F), 1, TSDM_REG_SYNC_PARSER_EMPTY,
989	NA, 1, 0, pneq,
990	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
991	"TSDM: Parser serial FIFO is not empty",
992	{NA, NA, 1, NA, NA, NA} },
993
994/*line 148*/{(0x1F), 1, USDM_REG_SYNC_PARSER_EMPTY,
995	NA, 1, 0, pneq,
996	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
997	"USDM: Parser serial FIFO is not empty",
998	{NA, NA, 1, NA, NA, NA} },
999
1000/*line 149*/{(0x1F), 1, XSDM_REG_SYNC_PARSER_EMPTY,
1001	NA, 1, 0, pneq,
1002	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
1003	"XSDM: Parser serial FIFO is not empty",
1004	{NA, NA, 1, NA, NA, NA} },
1005
1006/*line 150*/{(0x1F), 1, CSDM_REG_SYNC_SYNC_EMPTY,
1007	NA, 1, 0, pneq,
1008	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
1009	"CSDM: Parser SYNC serial FIFO is not empty",
1010	{NA, NA, 1, NA, NA, NA} },
1011
1012/*line 151*/{(0x1F), 1, TSDM_REG_SYNC_SYNC_EMPTY,
1013	NA, 1, 0, pneq,
1014	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
1015	"TSDM: Parser SYNC serial FIFO is not empty",
1016	{NA, NA, 1, NA, NA, NA} },
1017
1018/*line 152*/{(0x1F), 1, USDM_REG_SYNC_SYNC_EMPTY,
1019	NA, 1, 0, pneq,
1020	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
1021	"USDM: Parser SYNC serial FIFO is not empty",
1022	{NA, NA, 1, NA, NA, NA} },
1023
1024/*line 153*/{(0x1F), 1, XSDM_REG_SYNC_SYNC_EMPTY,
1025	NA, 1, 0, pneq,
1026	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
1027	"XSDM: Parser SYNC serial FIFO is not empty",
1028	{NA, NA, 1, NA, NA, NA} },
1029
1030/*line 154*/{(0x1F), 1, CSDM_REG_RSP_PXP_CTRL_RDATA_EMPTY,
1031	NA, 1, 0, pneq,
1032	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
1033	"CSDM: pxp_ctrl rd_data fifo is not empty in sdm_dma_rsp block",
1034	{NA, NA, 1, NA, NA, NA} },
1035
1036/*line 155*/{(0x1F), 1, TSDM_REG_RSP_PXP_CTRL_RDATA_EMPTY,
1037	NA, 1, 0, pneq,
1038	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
1039	"TSDM: pxp_ctrl rd_data fifo is not empty in sdm_dma_rsp block",
1040	{NA, NA, 1, NA, NA, NA} },
1041
1042/*line 156*/{(0x1F), 1, USDM_REG_RSP_PXP_CTRL_RDATA_EMPTY,
1043	NA, 1, 0, pneq,
1044	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
1045	"USDM: pxp_ctrl rd_data fifo is not empty in sdm_dma_rsp block",
1046	{NA, NA, 1, NA, NA, NA} },
1047
1048/*line 157*/{(0x1F), 1, XSDM_REG_RSP_PXP_CTRL_RDATA_EMPTY,
1049	NA, 1, 0, pneq,
1050	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
1051	"XSDM: pxp_ctrl rd_data fifo is not empty in sdm_dma_rsp block",
1052	{NA, NA, 1, NA, NA, NA} },
1053
1054/*line 158*/{(0x1F), 1, DORQ_REG_DQ_FILL_LVLF,
1055	NA, 1, 0, pneq,
1056	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
1057	"DORQ: DORQ queue is not empty",
1058	{NA, NA, 0, NA, NA, NA} },
1059
1060/*line 159*/{(0x1F), 1, CFC_REG_CFC_INT_STS,
1061	NA, 1, 0, pneq,
1062	NA, IDLE_CHK_ERROR,
1063	"CFC: Interrupt status is not 0",
1064	{NA, NA, 0, NA, NA, NA} },
1065
1066/*line 160*/{(0x1F), 1, CDU_REG_CDU_INT_STS,
1067	NA, 1, 0, pneq,
1068	NA, IDLE_CHK_ERROR,
1069	"CDU: Interrupt status is not 0",
1070	{NA, NA, 0, NA, NA, NA} },
1071
1072/*line 161*/{(0x1F), 1, CCM_REG_CCM_INT_STS,
1073	NA, 1, 0, pneq,
1074	NA, IDLE_CHK_ERROR,
1075	"CCM: Interrupt status is not 0",
1076	{NA, NA, 0, NA, NA, NA} },
1077
1078/*line 162*/{(0x1F), 1, TCM_REG_TCM_INT_STS,
1079	NA, 1, 0, pneq,
1080	NA, IDLE_CHK_ERROR,
1081	"TCM: Interrupt status is not 0",
1082	{NA, NA, 0, NA, NA, NA} },
1083
1084/*line 163*/{(0x1F), 1, UCM_REG_UCM_INT_STS,
1085	NA, 1, 0, pneq,
1086	NA, IDLE_CHK_ERROR,
1087	"UCM: Interrupt status is not 0",
1088	{NA, NA, 0, NA, NA, NA} },
1089
1090/*line 164*/{(0x1F), 1, XCM_REG_XCM_INT_STS,
1091	NA, 1, 0, pneq,
1092	NA, IDLE_CHK_ERROR,
1093	"XCM: Interrupt status is not 0",
1094	{NA, NA, 0, NA, NA, NA} },
1095
1096/*line 165*/{(0xF), 1, PBF_REG_PBF_INT_STS,
1097	NA, 1, 0, pneq,
1098	NA, IDLE_CHK_ERROR,
1099	"PBF: Interrupt status is not 0",
1100	{NA, NA, 0, NA, NA, NA} },
1101
1102/*line 166*/{(0x1F), 1, TM_REG_TM_INT_STS,
1103	NA, 1, 0, pneq,
1104	NA, IDLE_CHK_ERROR,
1105	"TIMERS: Interrupt status is not 0",
1106	{NA, NA, 0, NA, NA, NA} },
1107
1108/*line 167*/{(0x1F), 1, DORQ_REG_DORQ_INT_STS,
1109	NA, 1, 0, pneq,
1110	NA, IDLE_CHK_ERROR,
1111	"DORQ: Interrupt status is not 0",
1112	{NA, NA, 0, NA, NA, NA} },
1113
1114/*line 168*/{(0x1F), 1, SRC_REG_SRC_INT_STS,
1115	NA, 1, 0, pneq,
1116	NA, IDLE_CHK_ERROR,
1117	"SRCH: Interrupt status is not 0",
1118	{NA, NA, 0, NA, NA, NA} },
1119
1120/*line 169*/{(0x1F), 1, PRS_REG_PRS_INT_STS,
1121	NA, 1, 0, pneq,
1122	NA, IDLE_CHK_ERROR,
1123	"PRS: Interrupt status is not 0",
1124	{NA, NA, 0, NA, NA, NA} },
1125
1126/*line 170*/{(0x1F), 1, BRB1_REG_BRB1_INT_STS,
1127	NA, 1, 0, pand_neq,
1128	NA, IDLE_CHK_ERROR,
1129	"BRB1: Interrupt status is not 0",
1130	{NA, NA, ~0xFC00, 0, NA, NA} },
1131
1132/*line 171*/{(0x1F), 1, GRCBASE_XPB + PB_REG_PB_INT_STS,
1133	NA, 1, 0, pneq,
1134	NA, IDLE_CHK_ERROR,
1135	"XPB: Interrupt status is not 0",
1136	{NA, NA, 0, NA, NA, NA} },
1137
1138/*line 172*/{(0x1F), 1, GRCBASE_UPB + PB_REG_PB_INT_STS,
1139	NA, 1, 0, pneq,
1140	NA, IDLE_CHK_ERROR,
1141	"UPB: Interrupt status is not 0",
1142	{NA, NA, 0, NA, NA, NA} },
1143
1144/*line 173*/{(0x1), 1, PXP2_REG_PXP2_INT_STS,
1145	NA, 1, 0, pneq,
1146	NA, IDLE_CHK_WARNING,
1147	"PXP2: Interrupt status 0 is not 0",
1148	{NA, NA, 0, NA, NA, NA} },
1149
1150/*line 174*/{(0x1E), 1, PXP2_REG_PXP2_INT_STS_0,
1151	NA, 1, 0, pneq,
1152	NA, IDLE_CHK_WARNING,
1153	"PXP2: Interrupt status 0 is not 0",
1154	{NA, NA, 0, NA, NA, NA} },
1155
1156/*line 175*/{(0x1E), 1, PXP2_REG_PXP2_INT_STS_1,
1157	NA, 1, 0, pneq,
1158	NA, IDLE_CHK_WARNING,
1159	"PXP2: Interrupt status 1 is not 0",
1160	{NA, NA, 0, NA, NA, NA} },
1161
1162/*line 176*/{(0x1F), 1, QM_REG_QM_INT_STS,
1163	NA, 1, 0, pneq,
1164	NA, IDLE_CHK_ERROR,
1165	"QM: Interrupt status is not 0",
1166	{NA, NA, 0, NA, NA, NA} },
1167
1168/*line 177*/{(0x1F), 1, PXP_REG_PXP_INT_STS_0,
1169	NA, 1, 0, pneq,
1170	NA, IDLE_CHK_WARNING,
1171	"PXP: P0 Interrupt status is not 0",
1172	{NA, NA, 0, NA, NA, NA} },
1173
1174/*line 178*/{(0x1F), 1, PXP_REG_PXP_INT_STS_1,
1175	NA, 1, 0, pneq,
1176	NA, IDLE_CHK_WARNING,
1177	"PXP: P1 Interrupt status is not 0",
1178	{NA, NA, 0, NA, NA, NA} },
1179
1180/*line 179*/{(0x1C), 1, PGLUE_B_REG_PGLUE_B_INT_STS,
1181	NA, 1, 0, pneq,
1182	NA, IDLE_CHK_WARNING,
1183	"PGLUE_B: Interrupt status is not 0",
1184	{NA, NA, 0, NA, NA, NA} },
1185
1186/*line 180*/{(0x1F), 1, DORQ_REG_RSPA_CRD_CNT,
1187	NA, 1, 0, pneq,
1188	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
1189	"DORQ: Credit to XCM is not full",
1190	{NA, NA, 2, NA, NA, NA} },
1191
1192/*line 181*/{(0x1F), 1, DORQ_REG_RSPB_CRD_CNT,
1193	NA, 1, 0, pneq,
1194	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
1195	"DORQ: Credit to UCM is not full",
1196	{NA, NA, 2, NA, NA, NA} },
1197
1198/*line 182*/{(0x3), 1, QM_REG_VOQCRDERRREG,
1199	NA, 1, 0, pneq,
1200	NA, IDLE_CHK_ERROR,
1201	"QM: Credit error register is not 0 (byte or credit overflow/underflow)",
1202	{NA, NA, 0, NA, NA, NA} },
1203
1204/*line 183*/{(0x1F), 1, DORQ_REG_DQ_FULL_ST,
1205	NA, 1, 0, pneq,
1206	NA, IDLE_CHK_ERROR,
1207	"DORQ: DORQ queue is full",
1208	{NA, NA, 0, NA, NA, NA} },
1209
1210/*line 184*/{(0x1F), 1, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0,
1211	NA, 1, 0, pand_neq,
1212	NA, IDLE_CHK_WARNING,
1213	"AEU: P0 AFTER_INVERT_1 is not 0",
1214	{NA, NA, ~0xCFFC, 0, NA, NA} },
1215
1216/*line 185*/{(0x1F), 1, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0,
1217	NA, 1, 0, pneq,
1218	NA, IDLE_CHK_ERROR,
1219	"AEU: P0 AFTER_INVERT_2 is not 0",
1220	{NA, NA, 0, NA, NA, NA} },
1221
1222/*line 186*/{(0x1F), 1, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0,
1223	NA, 1, 0, pand_neq,
1224	NA, IDLE_CHK_ERROR,
1225	"AEU: P0 AFTER_INVERT_3 is not 0",
1226	{NA, NA, ~0xFFFF0000, 0, NA, NA} },
1227
1228/*line 187*/{(0x1F), 1, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0,
1229	NA, 1, 0, pand_neq,
1230	NA, IDLE_CHK_ERROR,
1231	"AEU: P0 AFTER_INVERT_4 is not 0",
1232	{NA, NA, ~0x801FFFFF, 0, NA, NA} },
1233
1234/*line 188*/{(0x3), 1, MISC_REG_AEU_AFTER_INVERT_1_FUNC_1,
1235	NA, 1, 0, pand_neq,
1236	NA, IDLE_CHK_WARNING,
1237	"AEU: P1 AFTER_INVERT_1 is not 0",
1238	{NA, NA, ~0xCFFC, 0, NA, NA} },
1239
1240/*line 189*/{(0x3), 1, MISC_REG_AEU_AFTER_INVERT_2_FUNC_1,
1241	NA, 1, 0, pneq,
1242	NA, IDLE_CHK_ERROR,
1243	"AEU: P1 AFTER_INVERT_2 is not 0",
1244	{NA, NA, 0, NA, NA, NA} },
1245
1246/*line 190*/{(0x3), 1, MISC_REG_AEU_AFTER_INVERT_3_FUNC_1,
1247	NA, 1, 0, pand_neq,
1248	NA, IDLE_CHK_ERROR,
1249	"AEU: P1 AFTER_INVERT_3 is not 0",
1250	{NA, NA, ~0xFFFF0000, 0, NA, NA} },
1251
1252/*line 191*/{(0x3), 1, MISC_REG_AEU_AFTER_INVERT_4_FUNC_1,
1253	NA, 1, 0, pand_neq,
1254	NA, IDLE_CHK_ERROR,
1255	"AEU: P1 AFTER_INVERT_4 is not 0",
1256	{NA, NA, ~0x801FFFFF, 0, NA, NA} },
1257
1258/*line 192*/{(0x1F), 1, MISC_REG_AEU_AFTER_INVERT_1_MCP,
1259	NA, 1, 0, pand_neq,
1260	NA, IDLE_CHK_WARNING,
1261	"AEU: MCP AFTER_INVERT_1 is not 0",
1262	{NA, NA, ~0xCFFC, 0, NA, NA} },
1263
1264/*line 193*/{(0x1F), 1, MISC_REG_AEU_AFTER_INVERT_2_MCP,
1265	NA, 1, 0, pneq,
1266	NA, IDLE_CHK_ERROR,
1267	"AEU: MCP AFTER_INVERT_2 is not 0",
1268	{NA, NA, 0, NA, NA, NA} },
1269
1270/*line 194*/{(0x1F), 1, MISC_REG_AEU_AFTER_INVERT_3_MCP,
1271	NA, 1, 0, pand_neq,
1272	NA, IDLE_CHK_ERROR,
1273	"AEU: MCP AFTER_INVERT_3 is not 0",
1274	{NA, NA, ~0xFFFF0000, 0, NA, NA} },
1275
1276/*line 195*/{(0x1F), 1, MISC_REG_AEU_AFTER_INVERT_4_MCP,
1277	NA, 1, 0, pand_neq,
1278	NA, IDLE_CHK_ERROR,
1279	"AEU: MCP AFTER_INVERT_4 is not 0",
1280	{NA, NA, ~0x801FFFFF, 0, NA, NA} },
1281
1282/*line 196*/{(0xF), 5, PBF_REG_P0_CREDIT,
1283	PBF_REG_P0_INIT_CRD, 1, 0, pneq_r2,
1284	PBF_REG_DISABLE_NEW_TASK_PROC_P0, IDLE_CHK_ERROR_NO_TRAFFIC,
1285	"PBF: P0 credit is not equal to init_crd",
1286	{NA, NA, NA, NA, NA, NA} },
1287
1288/*line 197*/{(0xF), 5, PBF_REG_P1_CREDIT,
1289	PBF_REG_P1_INIT_CRD, 1, 0, pneq_r2,
1290	PBF_REG_DISABLE_NEW_TASK_PROC_P1, IDLE_CHK_ERROR_NO_TRAFFIC,
1291	"PBF: P1 credit is not equal to init_crd",
1292	{NA, NA, NA, NA, NA, NA} },
1293
1294/*line 198*/{(0xF), 3, PBF_REG_P4_CREDIT,
1295	PBF_REG_P4_INIT_CRD, 1, 0, pneq_r2,
1296	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
1297	"PBF: P4 credit is not equal to init_crd",
1298	{NA, NA, NA, NA, NA, NA} },
1299
1300/*line 199*/{(0x10), 5, PBF_REG_CREDIT_Q0,
1301	PBF_REG_INIT_CRD_Q0, 1, 0, pneq_r2,
1302	PBF_REG_DISABLE_NEW_TASK_PROC_Q0, IDLE_CHK_ERROR_NO_TRAFFIC,
1303	"PBF: Q0 credit is not equal to init_crd",
1304	{NA, NA, NA, NA, NA, NA} },
1305
1306/*line 200*/{(0x10), 5, PBF_REG_CREDIT_Q1,
1307	PBF_REG_INIT_CRD_Q1, 1, 0, pneq_r2,
1308	PBF_REG_DISABLE_NEW_TASK_PROC_Q1, IDLE_CHK_ERROR_NO_TRAFFIC,
1309	"PBF: Q1 credit is not equal to init_crd",
1310	{NA, NA, NA, NA, NA, NA} },
1311
1312/*line 201*/{(0x10), 5, PBF_REG_CREDIT_Q2,
1313	PBF_REG_INIT_CRD_Q2, 1, 0, pneq_r2,
1314	PBF_REG_DISABLE_NEW_TASK_PROC_Q2, IDLE_CHK_ERROR_NO_TRAFFIC,
1315	"PBF: Q2 credit is not equal to init_crd",
1316	{NA, NA, NA, NA, NA, NA} },
1317
1318/*line 202*/{(0x10), 5, PBF_REG_CREDIT_Q3,
1319	PBF_REG_INIT_CRD_Q3, 1, 0, pneq_r2,
1320	PBF_REG_DISABLE_NEW_TASK_PROC_Q3, IDLE_CHK_ERROR_NO_TRAFFIC,
1321	"PBF: Q3 credit is not equal to init_crd",
1322	{NA, NA, NA, NA, NA, NA} },
1323
1324/*line 203*/{(0x10), 5, PBF_REG_CREDIT_Q4,
1325	PBF_REG_INIT_CRD_Q4, 1, 0, pneq_r2,
1326	PBF_REG_DISABLE_NEW_TASK_PROC_Q4, IDLE_CHK_ERROR_NO_TRAFFIC,
1327	"PBF: Q4 credit is not equal to init_crd",
1328	{NA, NA, NA, NA, NA, NA} },
1329
1330/*line 204*/{(0x10), 5, PBF_REG_CREDIT_Q5,
1331	PBF_REG_INIT_CRD_Q5, 1, 0, pneq_r2,
1332	PBF_REG_DISABLE_NEW_TASK_PROC_Q5, IDLE_CHK_ERROR_NO_TRAFFIC,
1333	"PBF: Q5 credit is not equal to init_crd",
1334	{NA, NA, NA, NA, NA, NA} },
1335
1336/*line 205*/{(0x10), 3, PBF_REG_CREDIT_LB_Q,
1337	PBF_REG_INIT_CRD_LB_Q, 1, 0, pneq_r2,
1338	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
1339	"PBF: LB Q credit is not equal to init_crd",
1340	{NA, NA, NA, NA, NA, NA} },
1341
1342/*line 206*/{(0xF), 1, PBF_REG_P0_TASK_CNT,
1343	NA, 1, 0, pneq,
1344	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
1345	"PBF: P0 task_cnt is not 0",
1346	{NA, NA, 0, NA, NA, NA} },
1347
1348/*line 207*/{(0xF), 1, PBF_REG_P1_TASK_CNT,
1349	NA, 1, 0, pneq,
1350	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
1351	"PBF: P1 task_cnt is not 0",
1352	{NA, NA, 0, NA, NA, NA} },
1353
1354/*line 208*/{(0xF), 1, PBF_REG_P4_TASK_CNT,
1355	NA, 1, 0, pneq,
1356	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
1357	"PBF: P4 task_cnt is not 0",
1358	{NA, NA, 0, NA, NA, NA} },
1359
1360/*line 209*/{(0x10), 1, PBF_REG_TASK_CNT_Q0,
1361	NA, 1, 0, pneq,
1362	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
1363	"PBF: Q0 task_cnt is not 0",
1364	{NA, NA, 0, NA, NA, NA} },
1365
1366/*line 210*/{(0x10), 1, PBF_REG_TASK_CNT_Q1,
1367	NA, 1, 0, pneq,
1368	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
1369	"PBF: Q1 task_cnt is not 0",
1370	{NA, NA, 0, NA, NA, NA} },
1371
1372/*line 211*/{(0x10), 1, PBF_REG_TASK_CNT_Q2,
1373	NA, 1, 0, pneq,
1374	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
1375	"PBF: Q2 task_cnt is not 0",
1376	{NA, NA, 0, NA, NA, NA} },
1377
1378/*line 212*/{(0x10), 1, PBF_REG_TASK_CNT_Q3,
1379	NA, 1, 0, pneq,
1380	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
1381	"PBF: Q3 task_cnt is not 0",
1382	{NA, NA, 0, NA, NA, NA} },
1383
1384/*line 213*/{(0x10), 1, PBF_REG_TASK_CNT_Q4,
1385	NA, 1, 0, pneq,
1386	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
1387	"PBF: Q4 task_cnt is not 0",
1388	{NA, NA, 0, NA, NA, NA} },
1389
1390/*line 214*/{(0x10), 1, PBF_REG_TASK_CNT_Q5,
1391	NA, 1, 0, pneq,
1392	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
1393	"PBF: Q5 task_cnt is not 0",
1394	{NA, NA, 0, NA, NA, NA} },
1395
1396/*line 215*/{(0x10), 1, PBF_REG_TASK_CNT_LB_Q,
1397	NA, 1, 0, pneq,
1398	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
1399	"PBF: LB Q task_cnt is not 0",
1400	{NA, NA, 0, NA, NA, NA} },
1401
1402/*line 216*/{(0x1F), 1, XCM_REG_CFC_INIT_CRD,
1403	NA, 1, 0, pneq,
1404	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
1405	"XCM: CFC_INIT_CRD is not 1",
1406	{NA, NA, 1, NA, NA, NA} },
1407
1408/*line 217*/{(0x1F), 1, UCM_REG_CFC_INIT_CRD,
1409	NA, 1, 0, pneq,
1410	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
1411	"UCM: CFC_INIT_CRD is not 1",
1412	{NA, NA, 1, NA, NA, NA} },
1413
1414/*line 218*/{(0x1F), 1, TCM_REG_CFC_INIT_CRD,
1415	NA, 1, 0, pneq,
1416	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
1417	"TCM: CFC_INIT_CRD is not 1",
1418	{NA, NA, 1, NA, NA, NA} },
1419
1420/*line 219*/{(0x1F), 1, CCM_REG_CFC_INIT_CRD,
1421	NA, 1, 0, pneq,
1422	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
1423	"CCM: CFC_INIT_CRD is not 1",
1424	{NA, NA, 1, NA, NA, NA} },
1425
1426/*line 220*/{(0x1F), 1, XCM_REG_XQM_INIT_CRD,
1427	NA, 1, 0, pneq,
1428	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
1429	"XCM: XQM_INIT_CRD is not 32",
1430	{NA, NA, 32, NA, NA, NA} },
1431
1432/*line 221*/{(0x1F), 1, UCM_REG_UQM_INIT_CRD,
1433	NA, 1, 0, pneq,
1434	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
1435	"UCM: UQM_INIT_CRD is not 32",
1436	{NA, NA, 32, NA, NA, NA} },
1437
1438/*line 222*/{(0x1F), 1, TCM_REG_TQM_INIT_CRD,
1439	NA, 1, 0, pneq,
1440	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
1441	"TCM: TQM_INIT_CRD is not 32",
1442	{NA, NA, 32, NA, NA, NA} },
1443
1444/*line 223*/{(0x1F), 1, CCM_REG_CQM_INIT_CRD,
1445	NA, 1, 0, pneq,
1446	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
1447	"CCM: CQM_INIT_CRD is not 32",
1448	{NA, NA, 32, NA, NA, NA} },
1449
1450/*line 224*/{(0x1F), 1, XCM_REG_TM_INIT_CRD,
1451	NA, 1, 0, pneq,
1452	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
1453	"XCM: TM_INIT_CRD is not 4",
1454	{NA, NA, 4, NA, NA, NA} },
1455
1456/*line 225*/{(0x1F), 1, UCM_REG_TM_INIT_CRD,
1457	NA, 1, 0, pneq,
1458	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
1459	"UCM: TM_INIT_CRD is not 4",
1460	{NA, NA, 4, NA, NA, NA} },
1461
1462/*line 226*/{(0x1F), 1, XCM_REG_FIC0_INIT_CRD,
1463	NA, 1, 0, pneq,
1464	NA, IDLE_CHK_WARNING,
1465	"XCM: FIC0_INIT_CRD is not 64",
1466	{NA, NA, 64, NA, NA, NA} },
1467
1468/*line 227*/{(0x1F), 1, UCM_REG_FIC0_INIT_CRD,
1469	NA, 1, 0, pneq,
1470	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
1471	"UCM: FIC0_INIT_CRD is not 64",
1472	{NA, NA, 64, NA, NA, NA} },
1473
1474/*line 228*/{(0x1F), 1, TCM_REG_FIC0_INIT_CRD,
1475	NA, 1, 0, pneq,
1476	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
1477	"TCM: FIC0_INIT_CRD is not 64",
1478	{NA, NA, 64, NA, NA, NA} },
1479
1480/*line 229*/{(0x1F), 1, CCM_REG_FIC0_INIT_CRD,
1481	NA, 1, 0, pneq,
1482	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
1483	"CCM: FIC0_INIT_CRD is not 64",
1484	{NA, NA, 64, NA, NA, NA} },
1485
1486/*line 230*/{(0x1F), 1, XCM_REG_FIC1_INIT_CRD,
1487	NA, 1, 0, pneq,
1488	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
1489	"XCM: FIC1_INIT_CRD is not 64",
1490	{NA, NA, 64, NA, NA, NA} },
1491
1492/*line 231*/{(0x1F), 1, UCM_REG_FIC1_INIT_CRD,
1493	NA, 1, 0, pneq,
1494	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
1495	"UCM: FIC1_INIT_CRD is not 64",
1496	{NA, NA, 64, NA, NA, NA} },
1497
1498/*line 232*/{(0x1F), 1, TCM_REG_FIC1_INIT_CRD,
1499	NA, 1, 0, pneq,
1500	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
1501	"TCM: FIC1_INIT_CRD is not 64",
1502	{NA, NA, 64, NA, NA, NA} },
1503
1504/*line 233*/{(0x1F), 1, CCM_REG_FIC1_INIT_CRD,
1505	NA, 1, 0, pneq,
1506	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
1507	"CCM: FIC1_INIT_CRD is not 64",
1508	{NA, NA, 64, NA, NA, NA} },
1509
1510/*line 234*/{(0x1), 1, XCM_REG_XX_FREE,
1511	NA, 1, 0, pneq,
1512	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
1513	"XCM: XX_FREE differs from expected 31",
1514	{NA, NA, 31, NA, NA, NA} },
1515
1516/*line 235*/{(0x1E), 1, XCM_REG_XX_FREE,
1517	NA, 1, 0, pneq,
1518	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
1519	"XCM: XX_FREE differs from expected 32",
1520	{NA, NA, 32, NA, NA, NA} },
1521
1522/*line 236*/{(0x1F), 1, UCM_REG_XX_FREE,
1523	NA, 1, 0, pneq,
1524	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
1525	"UCM: XX_FREE differs from expected 27",
1526	{NA, NA, 27, NA, NA, NA} },
1527
1528/*line 237*/{(0x7), 1, TCM_REG_XX_FREE,
1529	NA, 1, 0, pneq,
1530	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
1531	"TCM: XX_FREE differs from expected 32",
1532	{NA, NA, 32, NA, NA, NA} },
1533
1534/*line 238*/{(0x18), 1, TCM_REG_XX_FREE,
1535	NA, 1, 0, pneq,
1536	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
1537	"TCM: XX_FREE differs from expected 29",
1538	{NA, NA, 29, NA, NA, NA} },
1539
1540/*line 239*/{(0x1F), 1, CCM_REG_XX_FREE,
1541	NA, 1, 0, pneq,
1542	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
1543	"CCM: XX_FREE differs from expected 24",
1544	{NA, NA, 24, NA, NA, NA} },
1545
1546/*line 240*/{(0x1F), 1, XSEM_REG_FAST_MEMORY + 0x18000,
1547	NA, 1, 0, pneq,
1548	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
1549	"XSEM: FOC0 credit less than initial credit",
1550	{NA, NA, 0, NA, NA, NA} },
1551
1552/*line 241*/{(0x1F), 1, XSEM_REG_FAST_MEMORY + 0x18040,
1553	NA, 1, 0, pneq,
1554	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
1555	"XSEM: FOC1 credit less than initial credit",
1556	{NA, NA, 24, NA, NA, NA} },
1557
1558/*line 242*/{(0x1F), 1, XSEM_REG_FAST_MEMORY + 0x18080,
1559	NA, 1, 0, pneq,
1560	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
1561	"XSEM: FOC2 credit less than initial credit",
1562	{NA, NA, 12, NA, NA, NA} },
1563
1564/*line 243*/{(0x1F), 1, USEM_REG_FAST_MEMORY + 0x18000,
1565	NA, 1, 0, pneq,
1566	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
1567	"USEM: FOC0 credit less than initial credit",
1568	{NA, NA, 26, NA, NA, NA} },
1569
1570/*line 244*/{(0x1F), 1, USEM_REG_FAST_MEMORY + 0x18040,
1571	NA, 1, 0, pneq,
1572	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
1573	"USEM: FOC1 credit less than initial credit",
1574	{NA, NA, 78, NA, NA, NA} },
1575
1576/*line 245*/{(0x1F), 1, USEM_REG_FAST_MEMORY + 0x18080,
1577	NA, 1, 0, pneq,
1578	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
1579	"USEM: FOC2 credit less than initial credit",
1580	{NA, NA, 16, NA, NA, NA} },
1581
1582/*line 246*/{(0x1F), 1, USEM_REG_FAST_MEMORY + 0x180C0,
1583	NA, 1, 0, pneq,
1584	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
1585	"USEM: FOC3 credit less than initial credit",
1586	{NA, NA, 32, NA, NA, NA} },
1587
1588/*line 247*/{(0x1F), 1, TSEM_REG_FAST_MEMORY + 0x18000,
1589	NA, 1, 0, pneq,
1590	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
1591	"TSEM: FOC0 credit less than initial credit",
1592	{NA, NA, 52, NA, NA, NA} },
1593
1594/*line 248*/{(0x1F), 1, TSEM_REG_FAST_MEMORY + 0x18040,
1595	NA, 1, 0, pneq,
1596	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
1597	"TSEM: FOC1 credit less than initial credit",
1598	{NA, NA, 24, NA, NA, NA} },
1599
1600/*line 249*/{(0x1F), 1, TSEM_REG_FAST_MEMORY + 0x18080,
1601	NA, 1, 0, pneq,
1602	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
1603	"TSEM: FOC2 credit less than initial credit",
1604	{NA, NA, 12, NA, NA, NA} },
1605
1606/*line 250*/{(0x1F), 1, TSEM_REG_FAST_MEMORY + 0x180C0,
1607	NA, 1, 0, pneq,
1608	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
1609	"TSEM: FOC3 credit less than initial credit",
1610	{NA, NA, 32, NA, NA, NA} },
1611
1612/*line 251*/{(0x1F), 1, CSEM_REG_FAST_MEMORY + 0x18000,
1613	NA, 1, 0, pneq,
1614	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
1615	"CSEM: FOC0 credit less than initial credit",
1616	{NA, NA, 16, NA, NA, NA} },
1617
1618/*line 252*/{(0x1F), 1, CSEM_REG_FAST_MEMORY + 0x18040,
1619	NA, 1, 0, pneq,
1620	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
1621	"CSEM: FOC1 credit less than initial credit",
1622	{NA, NA, 18, NA, NA, NA} },
1623
1624/*line 253*/{(0x1F), 1, CSEM_REG_FAST_MEMORY + 0x18080,
1625	NA, 1, 0, pneq,
1626	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
1627	"CSEM: FOC2 credit less than initial credit",
1628	{NA, NA, 48, NA, NA, NA} },
1629
1630/*line 254*/{(0x1F), 1, CSEM_REG_FAST_MEMORY + 0x180C0,
1631	NA, 1, 0, pneq,
1632	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
1633	"CSEM: FOC3 credit less than initial credit",
1634	{NA, NA, 14, NA, NA, NA} },
1635
1636/*line 255*/{(0x1F), 1, PRS_REG_TSDM_CURRENT_CREDIT,
1637	NA, 1, 0, pneq,
1638	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
1639	"PRS: TSDM current credit is not 0",
1640	{NA, NA, 0, NA, NA, NA} },
1641
1642/*line 256*/{(0x1F), 1, PRS_REG_TCM_CURRENT_CREDIT,
1643	NA, 1, 0, pneq,
1644	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
1645	"PRS: TCM current credit is not 0",
1646	{NA, NA, 0, NA, NA, NA} },
1647
1648/*line 257*/{(0x1F), 1, PRS_REG_CFC_LD_CURRENT_CREDIT,
1649	NA, 1, 0, pneq,
1650	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
1651	"PRS: CFC_LD current credit is not 0",
1652	{NA, NA, 0, NA, NA, NA} },
1653
1654/*line 258*/{(0x1F), 1, PRS_REG_CFC_SEARCH_CURRENT_CREDIT,
1655	NA, 1, 0, pneq,
1656	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
1657	"PRS: CFC_SEARCH current credit is not 0",
1658	{NA, NA, 0, NA, NA, NA} },
1659
1660/*line 259*/{(0x1F), 1, PRS_REG_SRC_CURRENT_CREDIT,
1661	NA, 1, 0, pneq,
1662	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
1663	"PRS: SRCH current credit is not 0",
1664	{NA, NA, 0, NA, NA, NA} },
1665
1666/*line 260*/{(0x1F), 1, PRS_REG_PENDING_BRB_PRS_RQ,
1667	NA, 1, 0, pneq,
1668	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
1669	"PRS: PENDING_BRB_PRS_RQ is not 0",
1670	{NA, NA, 0, NA, NA, NA} },
1671
1672/*line 261*/{(0x1F), 2, PRS_REG_PENDING_BRB_CAC0_RQ,
1673	NA, 5, 4, pneq,
1674	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
1675	"PRS: PENDING_BRB_CAC_RQ is not 0",
1676	{NA, NA, 0, NA, NA, NA} },
1677
1678/*line 262*/{(0x1F), 1, PRS_REG_SERIAL_NUM_STATUS_LSB,
1679	NA, 1, 0, pneq,
1680	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
1681	"PRS: SERIAL_NUM_STATUS_LSB is not 0",
1682	{NA, NA, 0, NA, NA, NA} },
1683
1684/*line 263*/{(0x1F), 1, PRS_REG_SERIAL_NUM_STATUS_MSB,
1685	NA, 1, 0, pneq,
1686	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
1687	"PRS: SERIAL_NUM_STATUS_MSB is not 0",
1688	{NA, NA, 0, NA, NA, NA} },
1689
1690/*line 264*/{(0x1F), 1, CDU_REG_ERROR_DATA,
1691	NA, 1, 0, pneq,
1692	NA, IDLE_CHK_ERROR,
1693	"CDU: ERROR_DATA is not 0",
1694	{NA, NA, 0, NA, NA, NA} },
1695
1696/*line 265*/{(0x1F), 1, CCM_REG_STORM_LENGTH_MIS,
1697	NA, 1, 0, pneq,
1698	NA, IDLE_CHK_ERROR,
1699	"CCM: STORM declared message length unequal to actual",
1700	{NA, NA, 0, NA, NA, NA} },
1701
1702/*line 266*/{(0x1F), 1, CCM_REG_CSDM_LENGTH_MIS,
1703	NA, 1, 0, pneq,
1704	NA, IDLE_CHK_ERROR,
1705	"CCM: CSDM declared message length unequal to actual",
1706	{NA, NA, 0, NA, NA, NA} },
1707
1708/*line 267*/{(0x1F), 1, CCM_REG_TSEM_LENGTH_MIS,
1709	NA, 1, 0, pneq,
1710	NA, IDLE_CHK_ERROR,
1711	"CCM: TSEM declared message length unequal to actual",
1712	{NA, NA, 0, NA, NA, NA} },
1713
1714/*line 268*/{(0x1F), 1, CCM_REG_XSEM_LENGTH_MIS,
1715	NA, 1, 0, pneq,
1716	NA, IDLE_CHK_ERROR,
1717	"CCM: XSEM declared message length unequal to actual",
1718	{NA, NA, 0, NA, NA, NA} },
1719
1720/*line 269*/{(0x1F), 1, CCM_REG_USEM_LENGTH_MIS,
1721	NA, 1, 0, pneq,
1722	NA, IDLE_CHK_ERROR,
1723	"CCM: USEM declared message length unequal to actual",
1724	{NA, NA, 0, NA, NA, NA} },
1725
1726/*line 270*/{(0x1F), 1, CCM_REG_PBF_LENGTH_MIS,
1727	NA, 1, 0, pneq,
1728	NA, IDLE_CHK_ERROR,
1729	"CCM: PBF declared message length unequal to actual",
1730	{NA, NA, 0, NA, NA, NA} },
1731
1732/*line 271*/{(0x1F), 1, TCM_REG_STORM_LENGTH_MIS,
1733	NA, 1, 0, pneq,
1734	NA, IDLE_CHK_ERROR,
1735	"TCM: STORM declared message length unequal to actual",
1736	{NA, NA, 0, NA, NA, NA} },
1737
1738/*line 272*/{(0x1F), 1, TCM_REG_TSDM_LENGTH_MIS,
1739	NA, 1, 0, pneq,
1740	NA, IDLE_CHK_ERROR,
1741	"TCM: TSDM declared message length unequal to actual",
1742	{NA, NA, 0, NA, NA, NA} },
1743
1744/*line 273*/{(0x1F), 1, TCM_REG_PRS_LENGTH_MIS,
1745	NA, 1, 0, pneq,
1746	NA, IDLE_CHK_ERROR,
1747	"TCM: PRS declared message length unequal to actual",
1748	{NA, NA, 0, NA, NA, NA} },
1749
1750/*line 274*/{(0x1F), 1, TCM_REG_PBF_LENGTH_MIS,
1751	NA, 1, 0, pneq,
1752	NA, IDLE_CHK_ERROR,
1753	"TCM: PBF declared message length unequal to actual",
1754	{NA, NA, 0, NA, NA, NA} },
1755
1756/*line 275*/{(0x1F), 1, TCM_REG_USEM_LENGTH_MIS,
1757	NA, 1, 0, pneq,
1758	NA, IDLE_CHK_ERROR,
1759	"TCM: USEM declared message length unequal to actual",
1760	{NA, NA, 0, NA, NA, NA} },
1761
1762/*line 276*/{(0x1F), 1, TCM_REG_CSEM_LENGTH_MIS,
1763	NA, 1, 0, pneq,
1764	NA, IDLE_CHK_ERROR,
1765	"TCM: CSEM declared message length unequal to actual",
1766	{NA, NA, 0, NA, NA, NA} },
1767
1768/*line 277*/{(0x1F), 1, UCM_REG_STORM_LENGTH_MIS,
1769	NA, 1, 0, pneq,
1770	NA, IDLE_CHK_ERROR,
1771	"UCM: STORM declared message length unequal to actual",
1772	{NA, NA, 0, NA, NA, NA} },
1773
1774/*line 278*/{(0x1F), 1, UCM_REG_USDM_LENGTH_MIS,
1775	NA, 1, 0, pneq,
1776	NA, IDLE_CHK_ERROR,
1777	"UCM: USDM declared message length unequal to actual",
1778	{NA, NA, 0, NA, NA, NA} },
1779
1780/*line 279*/{(0x1F), 1, UCM_REG_TSEM_LENGTH_MIS,
1781	NA, 1, 0, pneq,
1782	NA, IDLE_CHK_ERROR,
1783	"UCM: TSEM declared message length unequal to actual",
1784	{NA, NA, 0, NA, NA, NA} },
1785
1786/*line 280*/{(0x1F), 1, UCM_REG_CSEM_LENGTH_MIS,
1787	NA, 1, 0, pneq,
1788	NA, IDLE_CHK_ERROR,
1789	"UCM: CSEM declared message length unequal to actual",
1790	{NA, NA, 0, NA, NA, NA} },
1791
1792/*line 281*/{(0x1F), 1, UCM_REG_XSEM_LENGTH_MIS,
1793	NA, 1, 0, pneq,
1794	NA, IDLE_CHK_ERROR,
1795	"UCM: XSEM declared message length unequal to actual",
1796	{NA, NA, 0, NA, NA, NA} },
1797
1798/*line 282*/{(0x1F), 1, UCM_REG_DORQ_LENGTH_MIS,
1799	NA, 1, 0, pneq,
1800	NA, IDLE_CHK_ERROR,
1801	"UCM: DORQ declared message length unequal to actual",
1802	{NA, NA, 0, NA, NA, NA} },
1803
1804/*line 283*/{(0x1F), 1, XCM_REG_STORM_LENGTH_MIS,
1805	NA, 1, 0, pneq,
1806	NA, IDLE_CHK_ERROR,
1807	"XCM: STORM declared message length unequal to actual",
1808	{NA, NA, 0, NA, NA, NA} },
1809
1810/*line 284*/{(0x1F), 1, XCM_REG_XSDM_LENGTH_MIS,
1811	NA, 1, 0, pneq,
1812	NA, IDLE_CHK_ERROR,
1813	"XCM: XSDM declared message length unequal to actual",
1814	{NA, NA, 0, NA, NA, NA} },
1815
1816/*line 285*/{(0x1F), 1, XCM_REG_TSEM_LENGTH_MIS,
1817	NA, 1, 0, pneq,
1818	NA, IDLE_CHK_ERROR,
1819	"XCM: TSEM declared message length unequal to actual",
1820	{NA, NA, 0, NA, NA, NA} },
1821
1822/*line 286*/{(0x1F), 1, XCM_REG_CSEM_LENGTH_MIS,
1823	NA, 1, 0, pneq,
1824	NA, IDLE_CHK_ERROR,
1825	"XCM: CSEM declared message length unequal to actual",
1826	{NA, NA, 0, NA, NA, NA} },
1827
1828/*line 287*/{(0x1F), 1, XCM_REG_USEM_LENGTH_MIS,
1829	NA, 1, 0, pneq,
1830	NA, IDLE_CHK_ERROR,
1831	"XCM: USEM declared message length unequal to actual",
1832	{NA, NA, 0, NA, NA, NA} },
1833
1834/*line 288*/{(0x1F), 1, XCM_REG_DORQ_LENGTH_MIS,
1835	NA, 1, 0, pneq,
1836	NA, IDLE_CHK_ERROR,
1837	"XCM: DORQ declared message length unequal to actual",
1838	{NA, NA, 0, NA, NA, NA} },
1839
1840/*line 289*/{(0x1F), 1, XCM_REG_PBF_LENGTH_MIS,
1841	NA, 1, 0, pneq,
1842	NA, IDLE_CHK_ERROR,
1843	"XCM: PBF declared message length unequal to actual",
1844	{NA, NA, 0, NA, NA, NA} },
1845
1846/*line 290*/{(0x1F), 1, XCM_REG_NIG0_LENGTH_MIS,
1847	NA, 1, 0, pneq,
1848	NA, IDLE_CHK_ERROR,
1849	"XCM: NIG0 declared message length unequal to actual",
1850	{NA, NA, 0, NA, NA, NA} },
1851
1852/*line 291*/{(0x1F), 1, XCM_REG_NIG1_LENGTH_MIS,
1853	NA, 1, 0, pneq,
1854	NA, IDLE_CHK_ERROR,
1855	"XCM: NIG1 declared message length unequal to actual",
1856	{NA, NA, 0, NA, NA, NA} },
1857
1858/*line 292*/{(0x1F), 1, QM_REG_XQM_WRC_FIFOLVL,
1859	NA, 1, 0, pneq,
1860	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
1861	"QM: XQM wrc_fifolvl is not 0",
1862	{NA, NA, 0, NA, NA, NA} },
1863
1864/*line 293*/{(0x1F), 1, QM_REG_UQM_WRC_FIFOLVL,
1865	NA, 1, 0, pneq,
1866	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
1867	"QM: UQM wrc_fifolvl is not 0",
1868	{NA, NA, 0, NA, NA, NA} },
1869
1870/*line 294*/{(0x1F), 1, QM_REG_TQM_WRC_FIFOLVL,
1871	NA, 1, 0, pneq,
1872	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
1873	"QM: TQM wrc_fifolvl is not 0",
1874	{NA, NA, 0, NA, NA, NA} },
1875
1876/*line 295*/{(0x1F), 1, QM_REG_CQM_WRC_FIFOLVL,
1877	NA, 1, 0, pneq,
1878	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
1879	"QM: CQM wrc_fifolvl is not 0",
1880	{NA, NA, 0, NA, NA, NA} },
1881
1882/*line 296*/{(0x1F), 1, QM_REG_QSTATUS_LOW,
1883	NA, 1, 0, pneq,
1884	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
1885	"QM: QSTATUS_LOW is not 0",
1886	{NA, NA, 0, NA, NA, NA} },
1887
1888/*line 297*/{(0x1F), 1, QM_REG_QSTATUS_HIGH,
1889	NA, 1, 0, pneq,
1890	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
1891	"QM: QSTATUS_HIGH is not 0",
1892	{NA, NA, 0, NA, NA, NA} },
1893
1894/*line 298*/{(0x1F), 1, QM_REG_PAUSESTATE0,
1895	NA, 1, 0, pneq,
1896	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
1897	"QM: PAUSESTATE0 is not 0",
1898	{NA, NA, 0, NA, NA, NA} },
1899
1900/*line 299*/{(0x1F), 1, QM_REG_PAUSESTATE1,
1901	NA, 1, 0, pneq,
1902	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
1903	"QM: PAUSESTATE1 is not 0",
1904	{NA, NA, 0, NA, NA, NA} },
1905
1906/*line 300*/{(0x1F), 1, QM_REG_OVFQNUM,
1907	NA, 1, 0, pneq,
1908	NA, IDLE_CHK_ERROR,
1909	"QM: OVFQNUM is not 0",
1910	{NA, NA, 0, NA, NA, NA} },
1911
1912/*line 301*/{(0x1F), 1, QM_REG_OVFERROR,
1913	NA, 1, 0, pneq,
1914	NA, IDLE_CHK_ERROR,
1915	"QM: OVFERROR is not 0",
1916	{NA, NA, 0, NA, NA, NA} },
1917
1918/*line 302*/{(0x1F), 6, QM_REG_PTRTBL,
1919	NA, 64, 8, pneq_r2,
1920	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
1921	"QM: read and write variables not equal",
1922	{NA, NA, NA, NA, NA, NA} },
1923
1924/*line 303*/{(0x1F), 1, BRB1_REG_BRB1_PRTY_STS,
1925	NA, 1, 0, pand_neq,
1926	NA, IDLE_CHK_WARNING,
1927	"BRB1: parity status is not 0",
1928	{NA, NA, ~0x8, 0, NA, NA} },
1929
1930/*line 304*/{(0x1F), 1, CDU_REG_CDU_PRTY_STS,
1931	NA, 1, 0, pneq,
1932	NA, IDLE_CHK_WARNING,
1933	"CDU: parity status is not 0",
1934	{NA, NA, 0, NA, NA, NA} },
1935
1936/*line 305*/{(0x1F), 1, CFC_REG_CFC_PRTY_STS,
1937	NA, 1, 0, pand_neq,
1938	NA, IDLE_CHK_WARNING,
1939	"CFC: parity status is not 0",
1940	{NA, NA, ~0x2, 0, NA, NA} },
1941
1942/*line 306*/{(0x1F), 1, CSDM_REG_CSDM_PRTY_STS,
1943	NA, 1, 0, pneq,
1944	NA, IDLE_CHK_WARNING,
1945	"CSDM: parity status is not 0",
1946	{NA, NA, 0, NA, NA, NA} },
1947
1948/*line 307*/{(0x3), 1, DBG_REG_DBG_PRTY_STS,
1949	NA, 1, 0, pneq,
1950	NA, IDLE_CHK_WARNING,
1951	"DBG: parity status is not 0",
1952	{NA, NA, 0, NA, NA, NA} },
1953
1954/*line 308*/{(0x1F), 1, DMAE_REG_DMAE_PRTY_STS,
1955	NA, 1, 0, pneq,
1956	NA, IDLE_CHK_WARNING,
1957	"DMAE: parity status is not 0",
1958	{NA, NA, 0, NA, NA, NA} },
1959
1960/*line 309*/{(0x1F), 1, DORQ_REG_DORQ_PRTY_STS,
1961	NA, 1, 0, pneq,
1962	NA, IDLE_CHK_WARNING,
1963	"DORQ: parity status is not 0",
1964	{NA, NA, 0, NA, NA, NA} },
1965
1966/*line 310*/{(0x1), 1, TCM_REG_TCM_PRTY_STS,
1967	NA, 1, 0, pand_neq,
1968	NA, IDLE_CHK_WARNING,
1969	"TCM: parity status is not 0",
1970	{NA, NA, ~0x3ffc0, 0, NA, NA} },
1971
1972/*line 311*/{(0x1E), 1, TCM_REG_TCM_PRTY_STS,
1973	NA, 1, 0, pneq,
1974	NA, IDLE_CHK_WARNING,
1975	"TCM: parity status is not 0",
1976	{NA, NA, 0, NA, NA, NA} },
1977
1978/*line 312*/{(0x1), 1, CCM_REG_CCM_PRTY_STS,
1979	NA, 1, 0, pand_neq,
1980	NA, IDLE_CHK_WARNING,
1981	"CCM: parity status is not 0",
1982	{NA, NA, ~0x3ffc0, 0, NA, NA} },
1983
1984/*line 313*/{(0x1E), 1, CCM_REG_CCM_PRTY_STS,
1985	NA, 1, 0, pneq,
1986	NA, IDLE_CHK_WARNING,
1987	"CCM: parity status is not 0",
1988	{NA, NA, 0, NA, NA, NA} },
1989
1990/*line 314*/{(0x1), 1, UCM_REG_UCM_PRTY_STS,
1991	NA, 1, 0, pand_neq,
1992	NA, IDLE_CHK_WARNING,
1993	"UCM: parity status is not 0",
1994	{NA, NA, ~0x3ffc0, 0, NA, NA} },
1995
1996/*line 315*/{(0x1E), 1, UCM_REG_UCM_PRTY_STS,
1997	NA, 1, 0, pneq,
1998	NA, IDLE_CHK_WARNING,
1999	"UCM: parity status is not 0",
2000	{NA, NA, 0, NA, NA, NA} },
2001
2002/*line 316*/{(0x1), 1, XCM_REG_XCM_PRTY_STS,
2003	NA, 1, 0, pand_neq,
2004	NA, IDLE_CHK_WARNING,
2005	"XCM: parity status is not 0",
2006	{NA, NA, ~0x3ffc0, 0, NA, NA} },
2007
2008/*line 317*/{(0x1E), 1, XCM_REG_XCM_PRTY_STS,
2009	NA, 1, 0, pneq,
2010	NA, IDLE_CHK_WARNING,
2011	"XCM: parity status is not 0",
2012	{NA, NA, 0, NA, NA, NA} },
2013
2014/*line 318*/{(0x1), 1, HC_REG_HC_PRTY_STS,
2015	NA, 1, 0, pand_neq,
2016	NA, IDLE_CHK_WARNING,
2017	"HC: parity status is not 0",
2018	{NA, NA, ~0x1, 0, NA, NA} },
2019
2020/*line 319*/{(0x1), 1, MISC_REG_MISC_PRTY_STS,
2021	NA, 1, 0, pand_neq,
2022	NA, IDLE_CHK_WARNING,
2023	"MISC: parity status is not 0",
2024	{NA, NA, ~0x1, 0, NA, NA} },
2025
2026/*line 320*/{(0x1F), 1, PRS_REG_PRS_PRTY_STS,
2027	NA, 1, 0, pneq,
2028	NA, IDLE_CHK_WARNING,
2029	"PRS: parity status is not 0",
2030	{NA, NA, 0, NA, NA, NA} },
2031
2032/*line 321*/{(0x1F), 1, PXP_REG_PXP_PRTY_STS,
2033	NA, 1, 0, pneq,
2034	NA, IDLE_CHK_WARNING,
2035	"PXP: parity status is not 0",
2036	{NA, NA, 0, NA, NA, NA} },
2037
2038/*line 322*/{(0x1F), 1, QM_REG_QM_PRTY_STS,
2039	NA, 1, 0, pneq,
2040	NA, IDLE_CHK_WARNING,
2041	"QM: parity status is not 0",
2042	{NA, NA, 0, NA, NA, NA} },
2043
2044/*line 323*/{(0x1), 1, SRC_REG_SRC_PRTY_STS,
2045	NA, 1, 0, pand_neq,
2046	NA, IDLE_CHK_WARNING,
2047	"SRCH: parity status is not 0",
2048	{NA, NA, ~0x4, 0, NA, NA} },
2049
2050/*line 324*/{(0x1F), 1, TSDM_REG_TSDM_PRTY_STS,
2051	NA, 1, 0, pneq,
2052	NA, IDLE_CHK_WARNING,
2053	"TSDM: parity status is not 0",
2054	{NA, NA, 0, NA, NA, NA} },
2055
2056/*line 325*/{(0x1F), 1, USDM_REG_USDM_PRTY_STS,
2057	NA, 1, 0, pand_neq,
2058	NA, IDLE_CHK_WARNING,
2059	"USDM: parity status is not 0",
2060	{NA, NA, ~0x20, 0, NA, NA} },
2061
2062/*line 326*/{(0x1F), 1, XSDM_REG_XSDM_PRTY_STS,
2063	NA, 1, 0, pneq,
2064	NA, IDLE_CHK_WARNING,
2065	"XSDM: parity status is not 0",
2066	{NA, NA, 0, NA, NA, NA} },
2067
2068/*line 327*/{(0x1F), 1, GRCBASE_XPB + PB_REG_PB_PRTY_STS,
2069	NA, 1, 0, pneq,
2070	NA, IDLE_CHK_WARNING,
2071	"XPB: parity status is not 0",
2072	{NA, NA, 0, NA, NA, NA} },
2073
2074/*line 328*/{(0x1F), 1, GRCBASE_UPB + PB_REG_PB_PRTY_STS,
2075	NA, 1, 0, pneq,
2076	NA, IDLE_CHK_WARNING,
2077	"UPB: parity status is not 0",
2078	{NA, NA, 0, NA, NA, NA} },
2079
2080/*line 329*/{(0x1F), 1, CSEM_REG_CSEM_PRTY_STS_0,
2081	NA, 1, 0, pneq,
2082	NA, IDLE_CHK_WARNING,
2083	"CSEM: parity status 0 is not 0",
2084	{NA, NA, 0, NA, NA, NA} },
2085
2086/*line 330*/{(0x1), 1, PXP2_REG_PXP2_PRTY_STS_0,
2087	NA, 1, 0, pand_neq,
2088	NA, IDLE_CHK_WARNING,
2089	"PXP2: parity status 0 is not 0",
2090	{NA, NA, ~0xfff40020, 0, NA, NA} },
2091
2092/*line 331*/{(0x1E), 1, PXP2_REG_PXP2_PRTY_STS_0,
2093	NA, 1, 0, pand_neq,
2094	NA, IDLE_CHK_WARNING,
2095	"PXP2: parity status 0 is not 0",
2096	{NA, NA, ~0x20, 0, NA, NA} },
2097
2098/*line 332*/{(0x1F), 1, TSEM_REG_TSEM_PRTY_STS_0,
2099	NA, 1, 0, pneq,
2100	NA, IDLE_CHK_WARNING,
2101	"TSEM: parity status 0 is not 0",
2102	{NA, NA, 0, NA, NA, NA} },
2103
2104/*line 333*/{(0x1F), 1, USEM_REG_USEM_PRTY_STS_0,
2105	NA, 1, 0, pneq,
2106	NA, IDLE_CHK_WARNING,
2107	"USEM: parity status 0 is not 0",
2108	{NA, NA, 0, NA, NA, NA} },
2109
2110/*line 334*/{(0x1F), 1, XSEM_REG_XSEM_PRTY_STS_0,
2111	NA, 1, 0, pneq,
2112	NA, IDLE_CHK_WARNING,
2113	"XSEM: parity status 0 is not 0",
2114	{NA, NA, 0, NA, NA, NA} },
2115
2116/*line 335*/{(0x1F), 1, CSEM_REG_CSEM_PRTY_STS_1,
2117	NA, 1, 0, pneq,
2118	NA, IDLE_CHK_WARNING,
2119	"CSEM: parity status 1 is not 0",
2120	{NA, NA, 0, NA, NA, NA} },
2121
2122/*line 336*/{(0x1), 1, PXP2_REG_PXP2_PRTY_STS_1,
2123	NA, 1, 0, pand_neq,
2124	NA, IDLE_CHK_WARNING,
2125	"PXP2: parity status 1 is not 0",
2126	{NA, NA, ~0x20, 0, NA, NA} },
2127
2128/*line 337*/{(0x1E), 1, PXP2_REG_PXP2_PRTY_STS_1,
2129	NA, 1, 0, pneq,
2130	NA, IDLE_CHK_WARNING,
2131	"PXP2: parity status 1 is not 0",
2132	{NA, NA, 0, NA, NA, NA} },
2133
2134/*line 338*/{(0x1F), 1, TSEM_REG_TSEM_PRTY_STS_1,
2135	NA, 1, 0, pneq,
2136	NA, IDLE_CHK_WARNING,
2137	"TSEM: parity status 1 is not 0",
2138	{NA, NA, 0, NA, NA, NA} },
2139
2140/*line 339*/{(0x1F), 1, USEM_REG_USEM_PRTY_STS_1,
2141	NA, 1, 0, pneq,
2142	NA, IDLE_CHK_WARNING,
2143	"USEM: parity status 1 is not 0",
2144	{NA, NA, 0, NA, NA, NA} },
2145
2146/*line 340*/{(0x1F), 1, XSEM_REG_XSEM_PRTY_STS_1,
2147	NA, 1, 0, pneq,
2148	NA, IDLE_CHK_WARNING,
2149	"XSEM: parity status 1 is not 0",
2150	{NA, NA, 0, NA, NA, NA} },
2151
2152/*line 341*/{(0x1C), 1, PGLUE_B_REG_PGLUE_B_PRTY_STS,
2153	NA, 1, 0, pneq,
2154	NA, IDLE_CHK_WARNING,
2155	"PGLUE_B: parity status is not 0",
2156	{NA, NA, 0, NA, NA, NA} },
2157
2158/*line 342*/{(0x2), 2, QM_REG_QTASKCTR_EXT_A_0,
2159	NA, 64, 4, pneq,
2160	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
2161	"QM: Q_EXT_A (upper 64 queues), Queue is not empty",
2162	{NA, NA, 0, NA, NA, NA} },
2163
2164/*line 343*/{(0x2), 1, QM_REG_QSTATUS_LOW_EXT_A,
2165	NA, 1, 0, pneq,
2166	NA, IDLE_CHK_ERROR,
2167	"QM: QSTATUS_LOW_EXT_A is not 0",
2168	{NA, NA, 0, NA, NA, NA} },
2169
2170/*line 344*/{(0x2), 1, QM_REG_QSTATUS_HIGH_EXT_A,
2171	NA, 1, 0, pneq,
2172	NA, IDLE_CHK_ERROR,
2173	"QM: QSTATUS_HIGH_EXT_A is not 0",
2174	{NA, NA, 0, NA, NA, NA} },
2175
2176/*line 345*/{(0x1E), 1, QM_REG_PAUSESTATE2,
2177	NA, 1, 0, pneq,
2178	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
2179	"QM: PAUSESTATE2 is not 0",
2180	{NA, NA, 0, NA, NA, NA} },
2181
2182/*line 346*/{(0x1E), 1, QM_REG_PAUSESTATE3,
2183	NA, 1, 0, pneq,
2184	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
2185	"QM: PAUSESTATE3 is not 0",
2186	{NA, NA, 0, NA, NA, NA} },
2187
2188/*line 347*/{(0x2), 1, QM_REG_PAUSESTATE4,
2189	NA, 1, 0, pneq,
2190	NA, IDLE_CHK_ERROR,
2191	"QM: PAUSESTATE4 is not 0",
2192	{NA, NA, 0, NA, NA, NA} },
2193
2194/*line 348*/{(0x2), 1, QM_REG_PAUSESTATE5,
2195	NA, 1, 0, pneq,
2196	NA, IDLE_CHK_ERROR,
2197	"QM: PAUSESTATE5 is not 0",
2198	{NA, NA, 0, NA, NA, NA} },
2199
2200/*line 349*/{(0x2), 1, QM_REG_PAUSESTATE6,
2201	NA, 1, 0, pneq,
2202	NA, IDLE_CHK_ERROR,
2203	"QM: PAUSESTATE6 is not 0",
2204	{NA, NA, 0, NA, NA, NA} },
2205
2206/*line 350*/{(0x2), 1, QM_REG_PAUSESTATE7,
2207	NA, 1, 0, pneq,
2208	NA, IDLE_CHK_ERROR,
2209	"QM: PAUSESTATE7 is not 0",
2210	{NA, NA, 0, NA, NA, NA} },
2211
2212/*line 351*/{(0x2), 6, QM_REG_PTRTBL_EXT_A,
2213	NA, 64, 8, pneq_r2,
2214	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
2215	"QM: read and write variables not equal in ext table",
2216	{NA, NA, NA, NA, NA, NA} },
2217
2218/*line 352*/{(0x1E), 1, MISC_REG_AEU_SYS_KILL_OCCURRED,
2219	NA, NA, NA, pneq,
2220	NA, IDLE_CHK_ERROR,
2221	"MISC: system kill occurred;",
2222	{NA, NA, 0, NA, NA, NA} },
2223
2224/*line 353*/{(0x1E), 1, MISC_REG_AEU_SYS_KILL_STATUS_0,
2225	NA, NA, NA, pneq,
2226	NA, IDLE_CHK_ERROR,
2227	"MISC: system kill occurred; status_0 register",
2228	{NA, NA, 0, NA, NA, NA} },
2229
2230/*line 354*/{(0x1E), 1, MISC_REG_AEU_SYS_KILL_STATUS_1,
2231	NA, NA, NA, pneq,
2232	NA, IDLE_CHK_ERROR,
2233	"MISC: system kill occurred; status_1 register",
2234	{NA, NA, 0, NA, NA, NA} },
2235
2236/*line 355*/{(0x1E), 1, MISC_REG_AEU_SYS_KILL_STATUS_2,
2237	NA, NA, NA, pneq,
2238	NA, IDLE_CHK_ERROR,
2239	"MISC: system kill occurred; status_2 register",
2240	{NA, NA, 0, NA, NA, NA} },
2241
2242/*line 356*/{(0x1E), 1, MISC_REG_AEU_SYS_KILL_STATUS_3,
2243	NA, NA, NA, pneq,
2244	NA, IDLE_CHK_ERROR,
2245	"MISC: system kill occurred; status_3 register",
2246	{NA, NA, 0, NA, NA, NA} },
2247
2248/*line 357*/{(0x1E), 1, MISC_REG_PCIE_HOT_RESET,
2249	NA, NA, NA, pneq,
2250	NA, IDLE_CHK_WARNING,
2251	"MISC: pcie_rst_b was asserted without perst assertion",
2252	{NA, NA, 0, NA, NA, NA} },
2253
2254/*line 358*/{(0x1F), 1, NIG_REG_NIG_INT_STS_0,
2255	NA, NA, NA, pand_neq,
2256	NA, IDLE_CHK_ERROR,
2257	"NIG: interrupt 0 is active",
2258	{NA, NA, ~0x300, 0, NA, NA} },
2259
2260/*line 359*/{(0x1F), 1, NIG_REG_NIG_INT_STS_0,
2261	NA, NA, NA, peq,
2262	NA, IDLE_CHK_WARNING,
2263	"NIG: Access to BMAC while not active. If tested on FPGA, ignore this warning",
2264	{NA, NA, 0x300, NA, NA, NA} },
2265
2266/*line 360*/{(0x1F), 1, NIG_REG_NIG_INT_STS_1,
2267	NA, NA, NA, pand_neq,
2268	NA, IDLE_CHK_ERROR,
2269	"NIG: interrupt 1 is active",
2270	{NA, NA, 0x783FF03, 0, NA, NA} },
2271
2272/*line 361*/{(0x1F), 1, NIG_REG_NIG_INT_STS_1,
2273	NA, NA, NA, pand_neq,
2274	NA, IDLE_CHK_WARNING,
2275	"NIG: port cos was paused too long",
2276	{NA, NA, ~0x783FF0F, 0, NA, NA} },
2277
2278/*line 362*/{(0x1F), 1, NIG_REG_NIG_INT_STS_1,
2279	NA, NA, NA, pand_neq,
2280	NA, IDLE_CHK_WARNING,
2281	"NIG: Got packets w/o Outer-VLAN in MF mode",
2282	{NA, NA, 0xC, 0, NA, NA} },
2283
2284/*line 363*/{(0x2), 1, NIG_REG_NIG_PRTY_STS,
2285	NA, NA, NA, pand_neq,
2286	NA, IDLE_CHK_ERROR,
2287	"NIG: parity interrupt is active",
2288	{NA, NA, ~0xFFC00000, 0, NA, NA} },
2289
2290/*line 364*/{(0x1C), 1, NIG_REG_NIG_PRTY_STS_0,
2291	NA, NA, NA, pand_neq,
2292	NA, IDLE_CHK_ERROR,
2293	"NIG: parity 0 interrupt is active",
2294	{NA, NA, ~0xFFC00000, 0, NA, NA} },
2295
2296/*line 365*/{(0x4), 1, NIG_REG_NIG_PRTY_STS_1,
2297	NA, NA, NA, pand_neq,
2298	NA, IDLE_CHK_ERROR,
2299	"NIG: parity 1 interrupt is active",
2300	{NA, NA, 0xff, 0, NA, NA} },
2301
2302/*line 366*/{(0x18), 1, NIG_REG_NIG_PRTY_STS_1,
2303	NA, NA, NA, pneq,
2304	NA, IDLE_CHK_ERROR,
2305	"NIG: parity 1 interrupt is active",
2306	{NA, NA, 0, NA, NA, NA} },
2307
2308/*line 367*/{(0x1F), 1, TSEM_REG_TSEM_INT_STS_0,
2309	NA, NA, NA, pand_neq,
2310	NA, IDLE_CHK_WARNING,
2311	"TSEM: interrupt 0 is active",
2312	{NA, NA, ~0x10000000, 0, NA, NA} },
2313
2314/*line 368*/{(0x1F), 1, TSEM_REG_TSEM_INT_STS_0,
2315	NA, NA, NA, peq,
2316	NA, IDLE_CHK_WARNING,
2317	"TSEM: interrupt 0 is active",
2318	{NA, NA, 0x10000000, NA, NA, NA} },
2319
2320/*line 369*/{(0x1F), 1, TSEM_REG_TSEM_INT_STS_1,
2321	NA, NA, NA, pneq,
2322	NA, IDLE_CHK_ERROR,
2323	"TSEM: interrupt 1 is active",
2324	{NA, NA, 0, NA, NA, NA} },
2325
2326/*line 370*/{(0x1F), 1, CSEM_REG_CSEM_INT_STS_0,
2327	NA, NA, NA, pand_neq,
2328	NA, IDLE_CHK_WARNING,
2329	"CSEM: interrupt 0 is active",
2330	{NA, NA, ~0x10000000, 0, NA, NA} },
2331
2332/*line 371*/{(0x1F), 1, CSEM_REG_CSEM_INT_STS_0,
2333	NA, NA, NA, peq,
2334	NA, IDLE_CHK_WARNING,
2335	"CSEM: interrupt 0 is active",
2336	{NA, NA, 0x10000000, NA, NA, NA} },
2337
2338/*line 372*/{(0x1F), 1, CSEM_REG_CSEM_INT_STS_1,
2339	NA, NA, NA, pneq,
2340	NA, IDLE_CHK_ERROR,
2341	"CSEM: interrupt 1 is active",
2342	{NA, NA, 0, NA, NA, NA} },
2343
2344/*line 373*/{(0x1F), 1, USEM_REG_USEM_INT_STS_0,
2345	NA, NA, NA, pand_neq,
2346	NA, IDLE_CHK_WARNING,
2347	"USEM: interrupt 0 is active",
2348	{NA, NA, ~0x10000000, 0, NA, NA} },
2349
2350/*line 374*/{(0x1F), 1, USEM_REG_USEM_INT_STS_0,
2351	NA, NA, NA, peq,
2352	NA, IDLE_CHK_WARNING,
2353	"USEM: interrupt 0 is active",
2354	{NA, NA, 0x10000000, NA, NA, NA} },
2355
2356/*line 375*/{(0x1F), 1, USEM_REG_USEM_INT_STS_1,
2357	NA, NA, NA, pneq,
2358	NA, IDLE_CHK_ERROR,
2359	"USEM: interrupt 1 is active",
2360	{NA, NA, 0, NA, NA, NA} },
2361
2362/*line 376*/{(0x1F), 1, XSEM_REG_XSEM_INT_STS_0,
2363	NA, NA, NA, pand_neq,
2364	NA, IDLE_CHK_WARNING,
2365	"XSEM: interrupt 0 is active",
2366	{NA, NA, ~0x10000000, 0, NA, NA} },
2367
2368/*line 377*/{(0x1F), 1, XSEM_REG_XSEM_INT_STS_0,
2369	NA, NA, NA, peq,
2370	NA, IDLE_CHK_WARNING,
2371	"XSEM: interrupt 0 is active",
2372	{NA, NA, 0x10000000, NA, NA, NA} },
2373
2374/*line 378*/{(0x1F), 1, XSEM_REG_XSEM_INT_STS_1,
2375	NA, NA, NA, pneq,
2376	NA, IDLE_CHK_ERROR,
2377	"XSEM: interrupt 1 is active",
2378	{NA, NA, 0, NA, NA, NA} },
2379
2380/*line 379*/{(0x1F), 1, TSDM_REG_TSDM_INT_STS_0,
2381	NA, NA, NA, pneq,
2382	NA, IDLE_CHK_ERROR,
2383	"TSDM: interrupt 0 is active",
2384	{NA, NA, 0, NA, NA, NA} },
2385
2386/*line 380*/{(0x1F), 1, TSDM_REG_TSDM_INT_STS_1,
2387	NA, NA, NA, pneq,
2388	NA, IDLE_CHK_ERROR,
2389	"TSDM: interrupt 0 is active",
2390	{NA, NA, 0, NA, NA, NA} },
2391
2392/*line 381*/{(0x1F), 1, CSDM_REG_CSDM_INT_STS_0,
2393	NA, NA, NA, pneq,
2394	NA, IDLE_CHK_ERROR,
2395	"CSDM: interrupt 0 is active",
2396	{NA, NA, 0, NA, NA, NA} },
2397
2398/*line 382*/{(0x1F), 1, CSDM_REG_CSDM_INT_STS_1,
2399	NA, NA, NA, pneq,
2400	NA, IDLE_CHK_ERROR,
2401	"CSDM: interrupt 0 is active",
2402	{NA, NA, 0, NA, NA, NA} },
2403
2404/*line 383*/{(0x1F), 1, USDM_REG_USDM_INT_STS_0,
2405	NA, NA, NA, pneq,
2406	NA, IDLE_CHK_ERROR,
2407	"USDM: interrupt 0 is active",
2408	{NA, NA, 0, NA, NA, NA} },
2409
2410/*line 384*/{(0x1F), 1, USDM_REG_USDM_INT_STS_1,
2411	NA, NA, NA, pneq,
2412	NA, IDLE_CHK_ERROR,
2413	"USDM: interrupt 0 is active",
2414	{NA, NA, 0, NA, NA, NA} },
2415
2416/*line 385*/{(0x1F), 1, XSDM_REG_XSDM_INT_STS_0,
2417	NA, NA, NA, pneq,
2418	NA, IDLE_CHK_ERROR,
2419	"XSDM: interrupt 0 is active",
2420	{NA, NA, 0, NA, NA, NA} },
2421
2422/*line 386*/{(0x1F), 1, XSDM_REG_XSDM_INT_STS_1,
2423	NA, NA, NA, pneq,
2424	NA, IDLE_CHK_ERROR,
2425	"XSDM: interrupt 0 is active",
2426	{NA, NA, 0, NA, NA, NA} },
2427
2428/*line 387*/{(0x2), 1, HC_REG_HC_PRTY_STS,
2429	NA, 1, 0, pneq,
2430	NA, IDLE_CHK_WARNING,
2431	"HC: parity status is not 0",
2432	{NA, NA, 0, NA, NA, NA} },
2433
2434/*line 388*/{(0x1E), 1, MISC_REG_MISC_PRTY_STS,
2435	NA, 1, 0, pneq,
2436	NA, IDLE_CHK_WARNING,
2437	"MISC: parity status is not 0",
2438	{NA, NA, 0, NA, NA, NA} },
2439
2440/*line 389*/{(0x1E), 1, SRC_REG_SRC_PRTY_STS,
2441	NA, 1, 0, pneq,
2442	NA, IDLE_CHK_WARNING,
2443	"SRCH: parity status is not 0",
2444	{NA, NA, 0, NA, NA, NA} },
2445
2446/*line 390*/{(0xC), 3, QM_REG_BYTECRD0,
2447	QM_REG_BYTECRDINITVAL, 1, 0, pneq_r2,
2448	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
2449	"QM: Byte credit 0 is not equal to initial credit",
2450	{NA, NA, NA, NA, NA, NA} },
2451
2452/*line 391*/{(0xC), 3, QM_REG_BYTECRD1,
2453	QM_REG_BYTECRDINITVAL, 1, 0, pneq_r2,
2454	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
2455	"QM: Byte credit 1 is not equal to initial credit",
2456	{NA, NA, NA, NA, NA, NA} },
2457
2458/*line 392*/{(0xC), 3, QM_REG_BYTECRD2,
2459	QM_REG_BYTECRDINITVAL, 1, 0, pneq_r2,
2460	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
2461	"QM: Byte credit 2 is not equal to initial credit",
2462	{NA, NA, NA, NA, NA, NA} },
2463
2464/*line 393*/{(0x1C), 1, QM_REG_VOQCRDERRREG,
2465	NA, 1, 0, pand_neq,
2466	NA, IDLE_CHK_ERROR,
2467	"QM: VOQ credit error register is not 0 (VOQ credit overflow/underflow)",
2468	{NA, NA, 0xFFFF, 0, NA, NA} },
2469
2470/*line 394*/{(0x1C), 1, QM_REG_BYTECRDERRREG,
2471	NA, 1, 0, pand_neq,
2472	NA, IDLE_CHK_ERROR,
2473	"QM: Byte credit error register is not 0 (Byte credit overflow/underflow)",
2474	{NA, NA, 0xFFF, 0, NA, NA} },
2475
2476/*line 395*/{(0x1C), 1, PGLUE_B_REG_FLR_REQUEST_VF_31_0,
2477	NA, 1, 0, pneq,
2478	NA, IDLE_CHK_WARNING,
2479	"PGL: FLR request is set for VF addresses 31-0",
2480	{NA, NA, 0, NA, NA, NA} },
2481
2482/*line 396*/{(0x1C), 1, PGLUE_B_REG_FLR_REQUEST_VF_63_32,
2483	NA, 1, 0, pneq,
2484	NA, IDLE_CHK_WARNING,
2485	"PGL: FLR request is set for VF addresses 63-32",
2486	{NA, NA, 0, NA, NA, NA} },
2487
2488/*line 397*/{(0x1C), 1, PGLUE_B_REG_FLR_REQUEST_VF_95_64,
2489	NA, 1, 0, pneq,
2490	NA, IDLE_CHK_WARNING,
2491	"PGL: FLR request is set for VF addresses 95-64",
2492	{NA, NA, 0, NA, NA, NA} },
2493
2494/*line 398*/{(0x1C), 1, PGLUE_B_REG_FLR_REQUEST_VF_127_96,
2495	NA, 1, 0, pneq,
2496	NA, IDLE_CHK_WARNING,
2497	"PGL: FLR request is set for VF addresses 127-96",
2498	{NA, NA, 0, NA, NA, NA} },
2499
2500/*line 399*/{(0x1C), 1, PGLUE_B_REG_FLR_REQUEST_PF_7_0,
2501	NA, 1, 0, pneq,
2502	NA, IDLE_CHK_WARNING,
2503	"PGL: FLR request is set for PF addresses 7-0",
2504	{NA, NA, 0, NA, NA, NA} },
2505
2506/*line 400*/{(0x1C), 1, PGLUE_B_REG_SR_IOV_DISABLED_REQUEST,
2507	NA, 1, 0, pneq,
2508	NA, IDLE_CHK_WARNING,
2509	"PGL: SR-IOV disable request is set",
2510	{NA, NA, 0, NA, NA, NA} },
2511
2512/*line 401*/{(0x1C), 1, PGLUE_B_REG_CFG_SPACE_A_REQUEST,
2513	NA, 1, 0, pneq,
2514	NA, IDLE_CHK_WARNING,
2515	"PGL: Cfg-Space A request is set",
2516	{NA, NA, 0, NA, NA, NA} },
2517
2518/*line 402*/{(0x1C), 1, PGLUE_B_REG_CFG_SPACE_B_REQUEST,
2519	NA, 1, 0, pneq,
2520	NA, IDLE_CHK_WARNING,
2521	"PGL: Cfg-Space B request is set",
2522	{NA, NA, 0, NA, NA, NA} },
2523
2524/*line 403*/{(0x1C), 1, IGU_REG_ERROR_HANDLING_DATA_VALID,
2525	NA, NA, 0, pneq,
2526	NA, IDLE_CHK_WARNING,
2527	"IGU: some unauthorized commands arrived to the IGU. Use igu_dump_fifo utility for more details",
2528	{NA, NA, 0, NA, NA, NA} },
2529
2530/*line 404*/{(0x1C), 1, IGU_REG_ATTN_WRITE_DONE_PENDING,
2531	NA, NA, NA, pneq,
2532	NA, IDLE_CHK_WARNING,
2533	"IGU attention message write done pending is not empty",
2534	{NA, NA, 0, NA, NA, NA} },
2535
2536/*line 405*/{(0x1C), 1, IGU_REG_WRITE_DONE_PENDING,
2537	NA, 5, 4, pneq,
2538	NA, IDLE_CHK_WARNING,
2539	"IGU MSI/MSIX message write done pending is not empty",
2540	{NA, NA, 0, NA, NA, NA} },
2541
2542/*line 406*/{(0x1C), 1, IGU_REG_IGU_PRTY_STS,
2543	NA, 1, 0, pneq,
2544	NA, IDLE_CHK_WARNING,
2545	"IGU: parity status is not 0",
2546	{NA, NA, 0, NA, NA, NA} },
2547
2548/*line 407*/{(0x1E), 3, MISC_REG_GRC_TIMEOUT_ATTN,
2549	MISC_REG_AEU_AFTER_INVERT_4_FUNC_0, 1, 0, pand_neq,
2550	NA, IDLE_CHK_ERROR,
2551	"MISC_REG_GRC_TIMEOUT_ATTN: GRC timeout attention parameters (FUNC_0)",
2552	{NA, NA, 0x4000000, 0, NA, NA} },
2553
2554/*line 408*/{(0x1C), 3, MISC_REG_GRC_TIMEOUT_ATTN_FULL_FID,
2555	MISC_REG_AEU_AFTER_INVERT_4_FUNC_0, 1, 0, pand_neq,
2556	NA, IDLE_CHK_ERROR,
2557	"MISC_REG_GRC_TIMEOUT_ATTN_FULL_FID: GRC timeout attention FID (FUNC_0)",
2558	{NA, NA, 0x4000000, 0, NA, NA} },
2559
2560/*line 409*/{(0x1E), 3, MISC_REG_GRC_TIMEOUT_ATTN,
2561	MISC_REG_AEU_AFTER_INVERT_4_FUNC_1, 1, 0, pand_neq,
2562	NA, IDLE_CHK_ERROR,
2563	"MISC_REG_GRC_TIMEOUT_ATTN: GRC timeout attention parameters (FUNC_1)",
2564	{NA, NA, 0x4000000, 0, NA, NA} },
2565
2566/*line 410*/{(0x1C), 3, MISC_REG_GRC_TIMEOUT_ATTN_FULL_FID,
2567	MISC_REG_AEU_AFTER_INVERT_4_FUNC_1, 1, 0, pand_neq,
2568	NA, IDLE_CHK_ERROR,
2569	"MISC_REG_GRC_TIMEOUT_ATTN_FULL_FID: GRC timeout attention FID (FUNC_1)",
2570	{NA, NA, 0x4000000, 0, NA, NA} },
2571
2572/*line 411*/{(0x1E), 3, MISC_REG_GRC_TIMEOUT_ATTN,
2573	MISC_REG_AEU_AFTER_INVERT_4_MCP, 1, 0, pand_neq,
2574	NA, IDLE_CHK_ERROR,
2575	"MISC_REG_GRC_TIMEOUT_ATTN: GRC timeout attention parameters (MCP)",
2576	{NA, NA, 0x4000000, 0, NA, NA} },
2577
2578/*line 412*/{(0x1C), 3, MISC_REG_GRC_TIMEOUT_ATTN_FULL_FID,
2579	MISC_REG_AEU_AFTER_INVERT_4_MCP, 1, 0, pand_neq,
2580	NA, IDLE_CHK_ERROR,
2581	"MISC_REG_GRC_TIMEOUT_ATTN_FULL_FID: GRC timeout attention FID (MCP)",
2582	{NA, NA, 0x4000000, 0, NA, NA} },
2583
2584/*line 413*/{(0x1C), 1, IGU_REG_SILENT_DROP,
2585	NA, 1, 0, pneq,
2586	NA, IDLE_CHK_ERROR,
2587	"Some messages were not executed in the IGU",
2588	{NA, NA, 0, NA, NA, NA} },
2589
2590/*line 414*/{(0x1C), 1, PXP2_REG_PSWRQ_BW_CREDIT,
2591	NA, 1, 0, pneq,
2592	NA, IDLE_CHK_ERROR,
2593	"PXP2: rq_read_credit and rq_write_credit are not 5",
2594	{NA, NA, 0x2D, NA, NA, NA} },
2595
2596/*line 415*/{(0x1C), 1, IGU_REG_SB_CTRL_FSM,
2597	NA, 1, 0, pneq,
2598	NA, IDLE_CHK_WARNING,
2599	"IGU: block is not in idle. SB_CTRL_FSM should be zero in idle state",
2600	{NA, NA, 0, NA, NA, NA} },
2601
2602/*line 416*/{(0x1C), 1, IGU_REG_INT_HANDLE_FSM,
2603	NA, 1, 0, pneq,
2604	NA, IDLE_CHK_WARNING,
2605	"IGU: block is not in idle. INT_HANDLE_FSM should be zero in idle state",
2606	{NA, NA, 0, NA, NA, NA} },
2607
2608/*line 417*/{(0x1C), 1, IGU_REG_ATTN_FSM,
2609	NA, 1, 0, pand_neq,
2610	NA, IDLE_CHK_WARNING,
2611	"IGU: block is not in idle. SB_ATTN_FSMshould be zeroor two in idle state",
2612	{NA, NA, ~0x2, 0, NA, NA} },
2613
2614/*line 418*/{(0x1C), 1, IGU_REG_CTRL_FSM,
2615	NA, 1, 0, pand_neq,
2616	NA, IDLE_CHK_WARNING,
2617	"IGU: block is not in idle. SB_CTRL_FSM should be zero in idle state",
2618	{NA, NA, ~0x1, 0, NA, NA} },
2619
2620/*line 419*/{(0x1C), 1, IGU_REG_PXP_ARB_FSM,
2621	NA, 1, 0, pand_neq,
2622	NA, IDLE_CHK_WARNING,
2623	"IGU: block is not in idle. SB_ARB_FSM should be zero in idle state",
2624	{NA, NA, ~0x1, 0, NA, NA} },
2625
2626/*line 420*/{(0x1C), 1, IGU_REG_PENDING_BITS_STATUS,
2627	NA, 5, 4, pneq,
2628	NA, IDLE_CHK_WARNING,
2629	"IGU: block is not in idle. There are pending write done",
2630	{NA, NA, 0, NA, NA, NA} },
2631
2632/*line 421*/{(0x10), 3, QM_REG_VOQCREDIT_0,
2633	QM_REG_VOQINITCREDIT_0, 1, 0, pneq_r2,
2634	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
2635	"QM: VOQ_0, VOQ credit is not equal to initial credit",
2636	{NA, NA, NA, NA, NA, NA} },
2637
2638/*line 422*/{(0x10), 3, QM_REG_VOQCREDIT_1,
2639	QM_REG_VOQINITCREDIT_1, 1, 0, pneq_r2,
2640	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
2641	"QM: VOQ_1, VOQ credit is not equal to initial credit",
2642	{NA, NA, NA, NA, NA, NA} },
2643
2644/*line 423*/{(0x10), 3, QM_REG_VOQCREDIT_2,
2645	QM_REG_VOQINITCREDIT_2, 1, 0, pneq_r2,
2646	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
2647	"QM: VOQ_2, VOQ credit is not equal to initial credit",
2648	{NA, NA, NA, NA, NA, NA} },
2649
2650/*line 424*/{(0x10), 3, QM_REG_VOQCREDIT_3,
2651	QM_REG_VOQINITCREDIT_3, 1, 0, pneq_r2,
2652	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
2653	"QM: VOQ_3, VOQ credit is not equal to initial credit",
2654	{NA, NA, NA, NA, NA, NA} },
2655
2656/*line 425*/{(0x10), 3, QM_REG_VOQCREDIT_4,
2657	QM_REG_VOQINITCREDIT_4, 1, 0, pneq_r2,
2658	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
2659	"QM: VOQ_4, VOQ credit is not equal to initial credit",
2660	{NA, NA, NA, NA, NA, NA} },
2661
2662/*line 426*/{(0x10), 3, QM_REG_VOQCREDIT_5,
2663	QM_REG_VOQINITCREDIT_5, 1, 0, pneq_r2,
2664	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
2665	"QM: VOQ_5, VOQ credit is not equal to initial credit",
2666	{NA, NA, NA, NA, NA, NA} },
2667
2668/*line 427*/{(0x10), 3, QM_REG_VOQCREDIT_6,
2669	QM_REG_VOQINITCREDIT_6, 1, 0, pneq_r2,
2670	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
2671	"QM: VOQ_6 (LB VOQ), VOQ credit is not equal to initial credit",
2672	{NA, NA, NA, NA, NA, NA} },
2673
2674/*line 428*/{(0x10), 3, QM_REG_BYTECRD0,
2675	QM_REG_BYTECRDINITVAL, 1, 0, pneq_r2,
2676	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
2677	"QM: Byte credit 0 is not equal to initial credit",
2678	{NA, NA, NA, NA, NA, NA} },
2679
2680/*line 429*/{(0x10), 3, QM_REG_BYTECRD1,
2681	QM_REG_BYTECRDINITVAL, 1, 0, pneq_r2,
2682	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
2683	"QM: Byte credit 1 is not equal to initial credit",
2684	{NA, NA, NA, NA, NA, NA} },
2685
2686/*line 430*/{(0x10), 3, QM_REG_BYTECRD2,
2687	QM_REG_BYTECRDINITVAL, 1, 0, pneq_r2,
2688	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
2689	"QM: Byte credit 2 is not equal to initial credit",
2690	{NA, NA, NA, NA, NA, NA} },
2691
2692/*line 431*/{(0x10), 3, QM_REG_BYTECRD3,
2693	QM_REG_BYTECRDINITVAL, 1, 0, pneq_r2,
2694	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
2695	"QM: Byte credit 3 is not equal to initial credit",
2696	{NA, NA, NA, NA, NA, NA} },
2697
2698/*line 432*/{(0x10), 3, QM_REG_BYTECRD4,
2699	QM_REG_BYTECRDINITVAL, 1, 0, pneq_r2,
2700	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
2701	"QM: Byte credit 4 is not equal to initial credit",
2702	{NA, NA, NA, NA, NA, NA} },
2703
2704/*line 433*/{(0x10), 3, QM_REG_BYTECRD5,
2705	QM_REG_BYTECRDINITVAL, 1, 0, pneq_r2,
2706	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
2707	"QM: Byte credit 5 is not equal to initial credit",
2708	{NA, NA, NA, NA, NA, NA} },
2709
2710/*line 434*/{(0x10), 3, QM_REG_BYTECRD6,
2711	QM_REG_BYTECRDINITVAL, 1, 0, pneq_r2,
2712	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
2713	"QM: Byte credit 6 is not equal to initial credit",
2714	{NA, NA, NA, NA, NA, NA} },
2715
2716/*line 435*/{(0x10), 1, QM_REG_FWVOQ0TOHWVOQ,
2717	NA, 1, 0, peq,
2718	NA, IDLE_CHK_ERROR,
2719	"QM: FwVoq0 is mapped to HwVoq7 (non-TX HwVoq)",
2720	{NA, NA, 0x7, NA, NA, NA} },
2721
2722/*line 436*/{(0x10), 1, QM_REG_FWVOQ1TOHWVOQ,
2723	NA, 1, 0, peq,
2724	NA, IDLE_CHK_ERROR,
2725	"QM: FwVoq1 is mapped to HwVoq7 (non-TX HwVoq)",
2726	{NA, NA, 0x7, NA, NA, NA} },
2727
2728/*line 437*/{(0x10), 1, QM_REG_FWVOQ2TOHWVOQ,
2729	NA, 1, 0, peq,
2730	NA, IDLE_CHK_ERROR,
2731	"QM: FwVoq2 is mapped to HwVoq7 (non-TX HwVoq)",
2732	{NA, NA, 0x7, NA, NA, NA} },
2733
2734/*line 438*/{(0x10), 1, QM_REG_FWVOQ3TOHWVOQ,
2735	NA, 1, 0, peq,
2736	NA, IDLE_CHK_ERROR,
2737	"QM: FwVoq3 is mapped to HwVoq7 (non-TX HwVoq)",
2738	{NA, NA, 0x7, NA, NA, NA} },
2739
2740/*line 439*/{(0x10), 1, QM_REG_FWVOQ4TOHWVOQ,
2741	NA, 1, 0, peq,
2742	NA, IDLE_CHK_ERROR,
2743	"QM: FwVoq4 is mapped to HwVoq7 (non-TX HwVoq)",
2744	{NA, NA, 0x7, NA, NA, NA} },
2745
2746/*line 440*/{(0x10), 1, QM_REG_FWVOQ5TOHWVOQ,
2747	NA, 1, 0, peq,
2748	NA, IDLE_CHK_ERROR,
2749	"QM: FwVoq5 is mapped to HwVoq7 (non-TX HwVoq)",
2750	{NA, NA, 0x7, NA, NA, NA} },
2751
2752/*line 441*/{(0x10), 1, QM_REG_FWVOQ6TOHWVOQ,
2753	NA, 1, 0, peq,
2754	NA, IDLE_CHK_ERROR,
2755	"QM: FwVoq6 is mapped to HwVoq7 (non-TX HwVoq)",
2756	{NA, NA, 0x7, NA, NA, NA} },
2757
2758/*line 442*/{(0x10), 1, QM_REG_FWVOQ7TOHWVOQ,
2759	NA, 1, 0, peq,
2760	NA, IDLE_CHK_ERROR,
2761	"QM: FwVoq7 is mapped to HwVoq7 (non-TX HwVoq)",
2762	{NA, NA, 0x7, NA, NA, NA} },
2763
2764/*line 443*/{(0x1F), 1, NIG_REG_INGRESS_EOP_PORT0_EMPTY,
2765	NA, 1, 0, pneq,
2766	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
2767	"NIG: Port 0 EOP FIFO is not empty",
2768	{NA, NA, 1, NA, NA, NA} },
2769
2770/*line 444*/{(0x1F), 1, NIG_REG_INGRESS_EOP_PORT1_EMPTY,
2771	NA, 1, 0, pneq,
2772	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
2773	"NIG: Port 1 EOP FIFO is not empty",
2774	{NA, NA, 1, NA, NA, NA} },
2775
2776/*line 445*/{(0x1F), 1, NIG_REG_INGRESS_EOP_LB_EMPTY,
2777	NA, 1, 0, pneq,
2778	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
2779	"NIG: LB EOP FIFO is not empty",
2780	{NA, NA, 1, NA, NA, NA} },
2781
2782/*line 446*/{(0x1F), 1, NIG_REG_INGRESS_RMP0_DSCR_EMPTY,
2783	NA, 1, 0, pneq,
2784	NA, IDLE_CHK_WARNING,
2785	"NIG: Port 0 RX MCP descriptor FIFO is not empty",
2786	{NA, NA, 1, NA, NA, NA} },
2787
2788/*line 447*/{(0x1F), 1, NIG_REG_INGRESS_RMP1_DSCR_EMPTY,
2789	NA, 1, 0, pneq,
2790	NA, IDLE_CHK_WARNING,
2791	"NIG: Port 1 RX MCP descriptor FIFO is not empty",
2792	{NA, NA, 1, NA, NA, NA} },
2793
2794/*line 448*/{(0x1F), 1, NIG_REG_INGRESS_LB_PBF_DELAY_EMPTY,
2795	NA, 1, 0, pneq,
2796	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
2797	"NIG: PBF LB FIFO is not empty",
2798	{NA, NA, 1, NA, NA, NA} },
2799
2800/*line 449*/{(0x1F), 1, NIG_REG_EGRESS_MNG0_FIFO_EMPTY,
2801	NA, 1, 0, pneq,
2802	NA, IDLE_CHK_WARNING,
2803	"NIG: Port 0 TX MCP FIFO is not empty",
2804	{NA, NA, 1, NA, NA, NA} },
2805
2806/*line 450*/{(0x1F), 1, NIG_REG_EGRESS_MNG1_FIFO_EMPTY,
2807	NA, 1, 0, pneq,
2808	NA, IDLE_CHK_WARNING,
2809	"NIG: Port 1 TX MCP FIFO is not empty",
2810	{NA, NA, 1, NA, NA, NA} },
2811
2812/*line 451*/{(0x1F), 1, NIG_REG_EGRESS_DEBUG_FIFO_EMPTY,
2813	NA, 1, 0, pneq,
2814	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
2815	"NIG: Debug FIFO is not empty",
2816	{NA, NA, 1, NA, NA, NA} },
2817
2818/*line 452*/{(0x1F), 1, NIG_REG_EGRESS_DELAY0_EMPTY,
2819	NA, 1, 0, pneq,
2820	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
2821	"NIG: PBF IF0 FIFO is not empty",
2822	{NA, NA, 1, NA, NA, NA} },
2823
2824/*line 453*/{(0x1F), 1, NIG_REG_EGRESS_DELAY1_EMPTY,
2825	NA, 1, 0, pneq,
2826	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
2827	"NIG: PBF IF1 FIFO is not empty",
2828	{NA, NA, 1, NA, NA, NA} },
2829
2830/*line 454*/{(0x1F), 1, NIG_REG_LLH0_FIFO_EMPTY,
2831	NA, 1, 0, pneq,
2832	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
2833	"NIG: Port 0 RX LLH FIFO is not empty",
2834	{NA, NA, 1, NA, NA, NA} },
2835
2836/*line 455*/{(0x1F), 1, NIG_REG_LLH1_FIFO_EMPTY,
2837	NA, 1, 0, pneq,
2838	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
2839	"NIG: Port 1 RX LLH FIFO is not empty",
2840	{NA, NA, 1, NA, NA, NA} },
2841
2842/*line 456*/{(0x1C), 1, NIG_REG_P0_TX_MNG_HOST_FIFO_EMPTY,
2843	NA, 1, 0, pneq,
2844	NA, IDLE_CHK_WARNING,
2845	"NIG: Port 0 TX MCP FIFO for traffic going to the host is not empty",
2846	{NA, NA, 1, NA, NA, NA} },
2847
2848/*line 457*/{(0x1C), 1, NIG_REG_P1_TX_MNG_HOST_FIFO_EMPTY,
2849	NA, 1, 0, pneq,
2850	NA, IDLE_CHK_WARNING,
2851	"NIG: Port 1 TX MCP FIFO for traffic going to the host is not empty",
2852	{NA, NA, 1, NA, NA, NA} },
2853
2854/*line 458*/{(0x1C), 1, NIG_REG_P0_TLLH_FIFO_EMPTY,
2855	NA, 1, 0, pneq,
2856	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
2857	"NIG: Port 0 TX LLH FIFO is not empty",
2858	{NA, NA, 1, NA, NA, NA} },
2859
2860/*line 459*/{(0x1C), 1, NIG_REG_P1_TLLH_FIFO_EMPTY,
2861	NA, 1, 0, pneq,
2862	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
2863	"NIG: Port 1 TX LLH FIFO is not empty",
2864	{NA, NA, 1, NA, NA, NA} },
2865
2866/*line 460*/{(0x1C), 1, NIG_REG_P0_HBUF_DSCR_EMPTY,
2867	NA, 1, 0, pneq,
2868	NA, IDLE_CHK_WARNING,
2869	"NIG: Port 0 RX MCP descriptor FIFO for traffic from the host is not empty",
2870	{NA, NA, 1, NA, NA, NA} },
2871
2872/*line 461*/{(0x1C), 1, NIG_REG_P1_HBUF_DSCR_EMPTY,
2873	NA, 1, 0, pneq,
2874	NA, IDLE_CHK_WARNING,
2875	"NIG: Port 1 RX MCP descriptor FIFO for traffic from the host is not empty",
2876	{NA, NA, 1, NA, NA, NA} },
2877
2878/*line 462*/{(0x18), 1, NIG_REG_P0_RX_MACFIFO_EMPTY,
2879	NA, 1, 0, pneq,
2880	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
2881	"NIG: Port 0 RX MAC interface FIFO is not empty",
2882	{NA, NA, 1, NA, NA, NA} },
2883
2884/*line 463*/{(0x18), 1, NIG_REG_P1_RX_MACFIFO_EMPTY,
2885	NA, 1, 0, pneq,
2886	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
2887	"NIG: Port 1 RX MAC interface FIFO is not empty",
2888	{NA, NA, 1, NA, NA, NA} },
2889
2890/*line 464*/{(0x18), 1, NIG_REG_P0_TX_MACFIFO_EMPTY,
2891	NA, 1, 0, pneq,
2892	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
2893	"NIG: Port 0 TX MAC interface FIFO is not empty",
2894	{NA, NA, 1, NA, NA, NA} },
2895
2896/*line 465*/{(0x18), 1, NIG_REG_P1_TX_MACFIFO_EMPTY,
2897	NA, 1, 0, pneq,
2898	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
2899	"NIG: Port 1 TX MAC interface FIFO is not empty",
2900	{NA, NA, 1, NA, NA, NA} },
2901
2902/*line 466*/{(0x10), 1, NIG_REG_EGRESS_DELAY2_EMPTY,
2903	NA, 1, 0, pneq,
2904	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
2905	"NIG: PBF IF2 FIFO is not empty",
2906	{NA, NA, 1, NA, NA, NA} },
2907
2908/*line 467*/{(0x10), 1, NIG_REG_EGRESS_DELAY3_EMPTY,
2909	NA, 1, 0, pneq,
2910	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
2911	"NIG: PBF IF3 FIFO is not empty",
2912	{NA, NA, 1, NA, NA, NA} },
2913
2914/*line 468*/{(0x10), 1, NIG_REG_EGRESS_DELAY4_EMPTY,
2915	NA, 1, 0, pneq,
2916	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
2917	"NIG: PBF IF4 FIFO is not empty",
2918	{NA, NA, 1, NA, NA, NA} },
2919
2920/*line 469*/{(0x10), 1, NIG_REG_EGRESS_DELAY5_EMPTY,
2921	NA, 1, 0, pneq,
2922	NA, IDLE_CHK_ERROR_NO_TRAFFIC,
2923	"NIG: PBF IF5 FIFO is not empty",
2924	{NA, NA, 1, NA, NA, NA} },
2925};
2926
2927/* handle self test fails according to severity and type */
2928static void bnx2x_self_test_log(struct bnx2x *bp, u8 severity, char *message)
2929{
2930	switch (severity) {
2931	case IDLE_CHK_ERROR:
2932		BNX2X_ERR("ERROR %s", message);
2933		idle_chk_errors++;
2934		break;
2935	case IDLE_CHK_ERROR_NO_TRAFFIC:
2936		DP(NETIF_MSG_HW, "INFO %s", message);
2937		break;
2938	case IDLE_CHK_WARNING:
2939		DP(NETIF_MSG_HW, "WARNING %s", message);
2940		idle_chk_warnings++;
2941		break;
2942	}
2943}
2944
2945/* specific test for QM rd/wr pointers and rd/wr banks */
2946static void bnx2x_idle_chk6(struct bnx2x *bp,
2947			    struct st_record *rec, char *message)
2948{
2949	u32 rd_ptr, wr_ptr, rd_bank, wr_bank;
2950	int i;
2951
2952	for (i = 0; i < rec->loop; i++) {
2953		/* read regs */
2954		rec->pred_args.val1 =
2955			REG_RD(bp, rec->reg1 + i * rec->incr);
2956		rec->pred_args.val2 =
2957			REG_RD(bp, rec->reg1 + i * rec->incr + 4);
2958
2959		/* calc read and write pointers */
2960		rd_ptr = ((rec->pred_args.val1 & 0x3FFFFFC0) >> 6);
2961		wr_ptr = ((((rec->pred_args.val1 & 0xC0000000) >> 30) & 0x3) |
2962			((rec->pred_args.val2 & 0x3FFFFF) << 2));
2963
2964		/* perfrom pointer test */
2965		if (rd_ptr != wr_ptr) {
2966			snprintf(message, MAX_FAIL_MSG,
2967				 "QM: PTRTBL entry %d- rd_ptr is not equal to wr_ptr. Values are 0x%x and 0x%x\n",
2968				 i, rd_ptr, wr_ptr);
2969			bnx2x_self_test_log(bp, rec->severity, message);
2970		}
2971
2972		/* calculate read and write banks */
2973		rd_bank = ((rec->pred_args.val1 & 0x30) >> 4);
2974		wr_bank = (rec->pred_args.val1 & 0x03);
2975
2976		/* perform bank test */
2977		if (rd_bank != wr_bank) {
2978			snprintf(message, MAX_FAIL_MSG,
2979				 "QM: PTRTBL entry %d - rd_bank is not equal to wr_bank. Values are 0x%x 0x%x\n",
2980				 i, rd_bank, wr_bank);
2981			bnx2x_self_test_log(bp, rec->severity, message);
2982		}
2983	}
2984}
2985
2986/* specific test for cfc info ram and cid cam */
2987static void bnx2x_idle_chk7(struct bnx2x *bp,
2988			    struct st_record *rec, char *message)
2989{
2990	int i;
2991
2992	/* iterate through lcids */
2993	for (i = 0; i < rec->loop; i++) {
2994		/* make sure cam entry is valid (bit 0) */
2995		if ((REG_RD(bp, (rec->reg2 + i * 4)) & 0x1) != 0x1)
2996			continue;
2997
2998		/* get connection type (multiple reads due to widebus) */
2999		REG_RD(bp, (rec->reg1 + i * rec->incr));
3000		REG_RD(bp, (rec->reg1 + i * rec->incr + 4));
3001		rec->pred_args.val1 =
3002			REG_RD(bp, (rec->reg1 + i * rec->incr + 8));
3003		REG_RD(bp, (rec->reg1 + i * rec->incr + 12));
3004
3005		/* obtain connection type */
3006		if (is_e1 || is_e1h) {
3007			/* E1 E1H (bits 4..7) */
3008			rec->pred_args.val1 &= 0x78;
3009			rec->pred_args.val1 >>= 3;
3010		} else {
3011			/* E2 E3A0 E3B0 (bits 26..29) */
3012			rec->pred_args.val1 &= 0x1E000000;
3013			rec->pred_args.val1 >>= 25;
3014		}
3015
3016		/* get activity counter value */
3017		rec->pred_args.val2 = REG_RD(bp, rec->reg3 + i * 4);
3018
3019		/* validate ac value is legal for con_type at idle state */
3020		if (rec->bnx2x_predicate(&rec->pred_args)) {
3021			snprintf(message, MAX_FAIL_MSG,
3022				 "%s. Values are 0x%x 0x%x\n", rec->fail_msg,
3023				 rec->pred_args.val1, rec->pred_args.val2);
3024			bnx2x_self_test_log(bp, rec->severity, message);
3025		}
3026	}
3027}
3028
3029/* self test procedure
3030 * scan auto-generated database
3031 * for each line:
3032 * 1.	compare chip mask
3033 * 2.	determine type (according to maro number)
3034 * 3.	read registers
3035 * 4.	call predicate
3036 * 5.	collate results and statistics
3037 */
3038int bnx2x_idle_chk(struct bnx2x *bp)
3039{
3040	u16 i;				/* loop counter */
3041	u16 st_ind;			/* self test database access index */
3042	struct st_record rec;		/* current record variable */
3043	char message[MAX_FAIL_MSG];	/* message to log */
3044
3045	/*init stats*/
3046	idle_chk_errors = 0;
3047	idle_chk_warnings = 0;
3048
3049	/*create masks for all chip types*/
3050	is_e1	= CHIP_IS_E1(bp);
3051	is_e1h	= CHIP_IS_E1H(bp);
3052	is_e2	= CHIP_IS_E2(bp);
3053	is_e3a0	= CHIP_IS_E3A0(bp);
3054	is_e3b0	= CHIP_IS_E3B0(bp);
3055
3056	/*database main loop*/
3057	for (st_ind = 0; st_ind < ST_DB_LINES; st_ind++) {
3058		rec = st_database[st_ind];
3059
3060		/*check if test applies to chip*/
3061		if (!((rec.chip_mask & IDLE_CHK_E1) && is_e1) &&
3062		    !((rec.chip_mask & IDLE_CHK_E1H) && is_e1h) &&
3063		    !((rec.chip_mask & IDLE_CHK_E2) && is_e2) &&
3064		    !((rec.chip_mask & IDLE_CHK_E3A0) && is_e3a0) &&
3065		    !((rec.chip_mask & IDLE_CHK_E3B0) && is_e3b0))
3066			continue;
3067
3068		/* identify macro */
3069		switch (rec.macro) {
3070		case 1:
3071			/* read single reg and call predicate */
3072			rec.pred_args.val1 = REG_RD(bp, rec.reg1);
3073			DP(BNX2X_MSG_IDLE, "mac1 add %x\n", rec.reg1);
3074			if (rec.bnx2x_predicate(&rec.pred_args)) {
3075				snprintf(message, sizeof(message),
3076					 "%s.Value is 0x%x\n", rec.fail_msg,
3077					 rec.pred_args.val1);
3078				bnx2x_self_test_log(bp, rec.severity, message);
3079			}
3080			break;
3081		case 2:
3082			/* read repeatedly starting from reg1 and call
3083			 * predicate after each read
3084			 */
3085			for (i = 0; i < rec.loop; i++) {
3086				rec.pred_args.val1 =
3087					REG_RD(bp, rec.reg1 + i * rec.incr);
3088				DP(BNX2X_MSG_IDLE, "mac2 add %x\n", rec.reg1);
3089				if (rec.bnx2x_predicate(&rec.pred_args)) {
3090					snprintf(message, sizeof(message),
3091						 "%s. Value is 0x%x in loop %d\n",
3092						 rec.fail_msg,
3093						 rec.pred_args.val1, i);
3094					bnx2x_self_test_log(bp, rec.severity,
3095							    message);
3096				}
3097			}
3098			break;
3099		case 3:
3100			/* read two regs and call predicate */
3101			rec.pred_args.val1 = REG_RD(bp, rec.reg1);
3102			rec.pred_args.val2 = REG_RD(bp, rec.reg2);
3103			DP(BNX2X_MSG_IDLE, "mac3 add1 %x add2 %x\n",
3104			   rec.reg1, rec.reg2);
3105			if (rec.bnx2x_predicate(&rec.pred_args)) {
3106				snprintf(message, sizeof(message),
3107					 "%s. Values are 0x%x 0x%x\n",
3108					 rec.fail_msg, rec.pred_args.val1,
3109					 rec.pred_args.val2);
3110				bnx2x_self_test_log(bp, rec.severity, message);
3111			}
3112			break;
3113		case 4:
3114			/*unused to-date*/
3115			for (i = 0; i < rec.loop; i++) {
3116				rec.pred_args.val1 =
3117					REG_RD(bp, rec.reg1 + i * rec.incr);
3118				rec.pred_args.val2 =
3119					(REG_RD(bp,
3120						rec.reg2 + i * rec.incr)) >> 1;
3121				if (rec.bnx2x_predicate(&rec.pred_args)) {
3122					snprintf(message, sizeof(message),
3123						 "%s. Values are 0x%x 0x%x in loop %d\n",
3124						 rec.fail_msg,
3125						 rec.pred_args.val1,
3126						 rec.pred_args.val2, i);
3127					bnx2x_self_test_log(bp, rec.severity,
3128							    message);
3129				}
3130			}
3131			break;
3132		case 5:
3133			/* compare two regs, pending
3134			 * the value of a condition reg
3135			 */
3136			rec.pred_args.val1 = REG_RD(bp, rec.reg1);
3137			rec.pred_args.val2 = REG_RD(bp, rec.reg2);
3138			DP(BNX2X_MSG_IDLE, "mac3 add1 %x add2 %x add3 %x\n",
3139			   rec.reg1, rec.reg2, rec.reg3);
3140			if (REG_RD(bp, rec.reg3) != 0) {
3141				if (rec.bnx2x_predicate(&rec.pred_args)) {
3142					snprintf(message, sizeof(message),
3143						 "%s. Values are 0x%x 0x%x\n",
3144						 rec.fail_msg,
3145						 rec.pred_args.val1,
3146						 rec.pred_args.val2);
3147					bnx2x_self_test_log(bp, rec.severity,
3148							    message);
3149				}
3150			}
3151			break;
3152		case 6:
3153			/* compare read and write pointers
3154			 * and read and write banks in QM
3155			 */
3156			bnx2x_idle_chk6(bp, &rec, message);
3157			break;
3158		case 7:
3159			/* compare cfc info cam with cid cam */
3160			bnx2x_idle_chk7(bp, &rec, message);
3161			break;
3162		default:
3163			DP(BNX2X_MSG_IDLE,
3164			   "unknown macro in self test data base. macro %d line %d",
3165			   rec.macro, st_ind);
3166		}
3167	}
3168
3169	/* abort if interface is not running */
3170	if (!netif_running(bp->dev))
3171		return idle_chk_errors;
3172
3173	/* return value accorindg to statistics */
3174	if (idle_chk_errors == 0) {
3175		DP(BNX2X_MSG_IDLE,
3176		   "completed successfully (logged %d warnings)\n",
3177		   idle_chk_warnings);
3178	} else {
3179		BNX2X_ERR("failed (with %d errors, %d warnings)\n",
3180			  idle_chk_errors, idle_chk_warnings);
3181	}
3182	return idle_chk_errors;
3183}
3184