Searched refs:PIPE_C (Results 1 - 25 of 27) sorted by path

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/linux-master/drivers/gpu/drm/i915/display/
H A Dg4x_dp.c1392 intel_encoder->pipe_mask = BIT(PIPE_C);
H A Dg4x_hdmi.c768 intel_encoder->pipe_mask = BIT(PIPE_C);
H A Di9xx_wm.c283 case PIPE_C:
788 FW_WM_VLV(wm->pipe[PIPE_C].plane[PLANE_SPRITE1], SPRITEF) |
789 FW_WM_VLV(wm->pipe[PIPE_C].plane[PLANE_SPRITE0], SPRITEE));
791 FW_WM_VLV(wm->pipe[PIPE_C].plane[PLANE_PRIMARY], PLANEC) |
792 FW_WM(wm->pipe[PIPE_C].plane[PLANE_CURSOR], CURSORC));
795 FW_WM(wm->pipe[PIPE_C].plane[PLANE_SPRITE1] >> 8, SPRITEF_HI) |
796 FW_WM(wm->pipe[PIPE_C].plane[PLANE_SPRITE0] >> 8, SPRITEE_HI) |
797 FW_WM(wm->pipe[PIPE_C].plane[PLANE_PRIMARY] >> 8, PLANEC_HI) |
1652 wm_state->cxsr = crtc->pipe != PIPE_C && num_active_planes == 1;
1823 case PIPE_C
[all...]
H A Dicl_dsi.c815 case PIPE_C:
1703 *pipe = PIPE_C;
H A Dintel_cursor.c488 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_C &&
H A Dintel_ddi.c533 case PIPE_C:
799 *pipe_mask = BIT(PIPE_C);
H A Dintel_display.c2734 (pipe == PIPE_B || pipe == PIPE_C))
3469 pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D);
3471 pipes = BIT(PIPE_B) | BIT(PIPE_C);
3622 trans_pipe = PIPE_C;
H A Dintel_display_device.c129 [PIPE_C] = CHV_CURSOR_C_OFFSET, \
136 [PIPE_C] = IVB_CURSOR_C_OFFSET, \
143 [PIPE_C] = IVB_CURSOR_C_OFFSET, \
374 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
408 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
428 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
445 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
468 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
492 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \
548 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \
[all...]
H A Dintel_display_irq.c444 case PIPE_C:
942 pipe = PIPE_C;
H A Dintel_display_limits.h19 PIPE_C, enumerator in enum:pipe
36 TRANSCODER_C = PIPE_C,
H A Dintel_display_power_map.c150 .irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
394 .irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
473 .irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
576 .irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
789 .irq_pipe_mask = BIT(PIPE_C),
940 .irq_pipe_mask = BIT(PIPE_C),
1083 .irq_pipe_mask = BIT(PIPE_C),
1178 .irq_pipe_mask = BIT(PIPE_C),
1352 .irq_pipe_mask = BIT(PIPE_C),
1509 .irq_pipe_mask = BIT(PIPE_C),
[all...]
H A Dintel_display_power_well.c1489 assert_pll_disabled(dev_priv, PIPE_C);
H A Dintel_display_trace.h49 __entry->frame[PIPE_C], __entry->scanline[PIPE_C])
78 __entry->frame[PIPE_C], __entry->scanline[PIPE_C])
185 __entry->frame[PIPE_C], __entry->scanline[PIPE_C])
H A Dintel_dmc.c450 for (pipe = PIPE_C; pipe <= PIPE_D; pipe++)
H A Dintel_dpio_phy.c697 case PIPE_C:
709 case PIPE_C:
H A Dintel_fdi.c145 crtc = intel_crtc_for_pipe(i915, PIPE_C);
223 other_crtc = intel_crtc_for_pipe(dev_priv, PIPE_C);
236 case PIPE_C:
425 intel_de_read(dev_priv, FDI_RX_CTL(PIPE_C)) &
453 case PIPE_C:
H A Dintel_pipe_crc.c180 case PIPE_C:
241 case PIPE_C:
H A Dintel_psr.c1729 case PIPE_C:
H A Dskl_universal_plane.c2053 if (DISPLAY_VER(dev_priv) == 9 && pipe == PIPE_C)
2261 return pipe != PIPE_C;
2263 return pipe != PIPE_C &&
H A Dskl_watermark.c878 .active_pipes = BIT(PIPE_C),
880 [PIPE_C] = BIT(DBUF_S2),
884 .active_pipes = BIT(PIPE_A) | BIT(PIPE_C),
887 [PIPE_C] = BIT(DBUF_S2),
891 .active_pipes = BIT(PIPE_B) | BIT(PIPE_C),
894 [PIPE_C] = BIT(DBUF_S2),
898 .active_pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
902 [PIPE_C] = BIT(DBUF_S2),
941 .active_pipes = BIT(PIPE_C),
943 [PIPE_C]
[all...]
H A Dvlv_dsi.c995 if (drm_WARN_ON(display->drm, tmp > PIPE_C))
/linux-master/drivers/gpu/drm/i915/gvt/
H A Dcmd_parser.c1294 [4] = {PIPE_C, PLANE_A, PRIMARY_C_FLIP_DONE},
1295 [5] = {PIPE_C, PLANE_B, SPRITE_C_FLIP_DONE},
1353 info->pipe = PIPE_C;
1368 info->pipe = PIPE_C;
H A Ddisplay.c58 pipe = PIPE_C;
631 [PIPE_C] = PIPE_C_VBLANK,
635 if (pipe < PIPE_A || pipe > PIPE_C)
H A Dhandlers.c894 calc_index(offset, _FDI_RXA_CTL, _FDI_RXB_CTL, 0, FDI_RX_CTL(PIPE_C))
897 calc_index(offset, _FDI_TXA_CTL, _FDI_TXB_CTL, 0, FDI_TX_CTL(PIPE_C))
900 calc_index(offset, _FDI_RXA_IMR, _FDI_RXB_IMR, 0, FDI_RX_IMR(PIPE_C))
1008 calc_index(offset, _DSPASURF, _DSPBSURF, 0, DSPSURF(PIPE_C))
1031 calc_index(offset, _SPRA_SURF, _SPRB_SURF, 0, SPRSURF(PIPE_C))
2282 MMIO_DH(DSPSURF(PIPE_C), D_ALL, NULL, pri_surf_mmio_write);
2283 MMIO_DH(REG_50080(PIPE_C, PLANE_PRIMARY), D_ALL, NULL,
2291 MMIO_DH(SPRSURF(PIPE_C), D_ALL, NULL, spr_surf_mmio_write);
2292 MMIO_DH(REG_50080(PIPE_C, PLANE_SPRITE0), D_ALL, NULL,
2313 MMIO_DH(FDI_RX_IIR(PIPE_C), D_AL
[all...]
H A Dinterrupt.c509 DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(de_pipe_c, GEN8_DE_PIPE_ISR(PIPE_C));

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