Searched refs:MCF_MBAR (Results 1 - 8 of 8) sorted by last modified time

/linux-master/arch/m68k/include/asm/
H A Dm54xxsim.h14 #define IOMEMBASE MCF_MBAR
24 #define MCFICM_INTC0 (MCF_MBAR + 0x700) /* Base for Interrupt Ctrl 0 */
39 #define MCFUART_BASE0 (MCF_MBAR + 0x8600) /* Base address UART0 */
40 #define MCFUART_BASE1 (MCF_MBAR + 0x8700) /* Base address UART1 */
41 #define MCFUART_BASE2 (MCF_MBAR + 0x8800) /* Base address UART2 */
42 #define MCFUART_BASE3 (MCF_MBAR + 0x8900) /* Base address UART3 */
58 #define MCFSLT_TIMER0 (MCF_MBAR + 0x900) /* Base addr TIMER0 */
59 #define MCFSLT_TIMER1 (MCF_MBAR + 0x910) /* Base addr TIMER1 */
64 #define MCFGPIO_PODR (MCF_MBAR + 0xA00)
65 #define MCFGPIO_PDDR (MCF_MBAR
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H A Dm54xxgpt.h20 #define MCF_GPT_GMS0 (MCF_MBAR + 0x000800)
21 #define MCF_GPT_GCIR0 (MCF_MBAR + 0x000804)
22 #define MCF_GPT_GPWM0 (MCF_MBAR + 0x000808)
23 #define MCF_GPT_GSR0 (MCF_MBAR + 0x00080C)
24 #define MCF_GPT_GMS1 (MCF_MBAR + 0x000810)
25 #define MCF_GPT_GCIR1 (MCF_MBAR + 0x000814)
26 #define MCF_GPT_GPWM1 (MCF_MBAR + 0x000818)
27 #define MCF_GPT_GSR1 (MCF_MBAR + 0x00081C)
28 #define MCF_GPT_GMS2 (MCF_MBAR + 0x000820)
29 #define MCF_GPT_GCIR2 (MCF_MBAR
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H A Dm5407sim.h27 #define MCFSIM_RSR (MCF_MBAR + 0x00) /* Reset Status */
28 #define MCFSIM_SYPCR (MCF_MBAR + 0x01) /* System Protection */
29 #define MCFSIM_SWIVR (MCF_MBAR + 0x02) /* SW Watchdog intr */
30 #define MCFSIM_SWSR (MCF_MBAR + 0x03) /* SW Watchdog service*/
31 #define MCFSIM_PAR (MCF_MBAR + 0x04) /* Pin Assignment */
32 #define MCFSIM_IRQPAR (MCF_MBAR + 0x06) /* Intr Assignment */
33 #define MCFSIM_PLLCR (MCF_MBAR + 0x08) /* PLL Ctrl */
34 #define MCFSIM_MPARK (MCF_MBAR + 0x0C) /* BUS Master Ctrl */
35 #define MCFSIM_IPR (MCF_MBAR + 0x40) /* Interrupt Pending */
36 #define MCFSIM_IMR (MCF_MBAR
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H A Dm5307sim.h27 #define MCFSIM_RSR (MCF_MBAR + 0x00) /* Reset Status reg */
28 #define MCFSIM_SYPCR (MCF_MBAR + 0x01) /* System Protection */
29 #define MCFSIM_SWIVR (MCF_MBAR + 0x02) /* SW Watchdog intr */
30 #define MCFSIM_SWSR (MCF_MBAR + 0x03) /* SW Watchdog service*/
31 #define MCFSIM_PAR (MCF_MBAR + 0x04) /* Pin Assignment */
32 #define MCFSIM_IRQPAR (MCF_MBAR + 0x06) /* Itr Assignment */
33 #define MCFSIM_PLLCR (MCF_MBAR + 0x08) /* PLL Ctrl Reg */
34 #define MCFSIM_MPARK (MCF_MBAR + 0x0C) /* BUS Master Ctrl */
35 #define MCFSIM_IPR (MCF_MBAR + 0x40) /* Interrupt Pend */
36 #define MCFSIM_IMR (MCF_MBAR
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H A Dm5272sim.h25 #define MCFSIM_SCR (MCF_MBAR + 0x04) /* SIM Config reg */
26 #define MCFSIM_SPR (MCF_MBAR + 0x06) /* System Protection */
27 #define MCFSIM_PMR (MCF_MBAR + 0x08) /* Power Management */
28 #define MCFSIM_APMR (MCF_MBAR + 0x0e) /* Active Low Power */
29 #define MCFSIM_DIR (MCF_MBAR + 0x10) /* Device Identity */
31 #define MCFSIM_ICR1 (MCF_MBAR + 0x20) /* Intr Ctrl reg 1 */
32 #define MCFSIM_ICR2 (MCF_MBAR + 0x24) /* Intr Ctrl reg 2 */
33 #define MCFSIM_ICR3 (MCF_MBAR + 0x28) /* Intr Ctrl reg 3 */
34 #define MCFSIM_ICR4 (MCF_MBAR + 0x2c) /* Intr Ctrl reg 4 */
36 #define MCFSIM_ISR (MCF_MBAR
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H A Dm525xsim.h35 #define MCFSIM_RSR (MCF_MBAR + 0x00) /* Reset Status */
36 #define MCFSIM_SYPCR (MCF_MBAR + 0x01) /* System Protection */
37 #define MCFSIM_SWIVR (MCF_MBAR + 0x02) /* SW Watchdog intr */
38 #define MCFSIM_SWSR (MCF_MBAR + 0x03) /* SW Watchdog srv */
39 #define MCFSIM_MPARK (MCF_MBAR + 0x0C) /* BUS Master Ctrl */
40 #define MCFSIM_IPR (MCF_MBAR + 0x40) /* Interrupt Pending */
41 #define MCFSIM_IMR (MCF_MBAR + 0x44) /* Interrupt Mask */
42 #define MCFSIM_ICR0 (MCF_MBAR + 0x4c) /* Intr Ctrl reg 0 */
43 #define MCFSIM_ICR1 (MCF_MBAR + 0x4d) /* Intr Ctrl reg 1 */
44 #define MCFSIM_ICR2 (MCF_MBAR
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H A Dm5206sim.h25 #define MCFSIM_SIMR (MCF_MBAR + 0x03) /* SIM Config reg */
26 #define MCFSIM_ICR1 (MCF_MBAR + 0x14) /* Intr Ctrl reg 1 */
27 #define MCFSIM_ICR2 (MCF_MBAR + 0x15) /* Intr Ctrl reg 2 */
28 #define MCFSIM_ICR3 (MCF_MBAR + 0x16) /* Intr Ctrl reg 3 */
29 #define MCFSIM_ICR4 (MCF_MBAR + 0x17) /* Intr Ctrl reg 4 */
30 #define MCFSIM_ICR5 (MCF_MBAR + 0x18) /* Intr Ctrl reg 5 */
31 #define MCFSIM_ICR6 (MCF_MBAR + 0x19) /* Intr Ctrl reg 6 */
32 #define MCFSIM_ICR7 (MCF_MBAR + 0x1a) /* Intr Ctrl reg 7 */
33 #define MCFSIM_ICR8 (MCF_MBAR + 0x1b) /* Intr Ctrl reg 8 */
34 #define MCFSIM_ICR9 (MCF_MBAR
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H A Dcoldfire.h43 #define MCF_MBAR CONFIG_MBAR macro

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