1285101Semaste/* SPDX-License-Identifier: GPL-2.0 */ 2285101Semaste/****************************************************************************/ 3353358Sdim 4353358Sdim/* 5353358Sdim * m5307sim.h -- ColdFire 5307 System Integration Module support. 6285101Semaste * 7285101Semaste * (C) Copyright 1999, Moreton Bay Ventures Pty Ltd. 8285101Semaste * (C) Copyright 1999, Lineo (www.lineo.com) 9285101Semaste * 10353358Sdim * Modified by David W. Miller for the MCF5307 Eval Board. 11353358Sdim */ 12285101Semaste 13285101Semaste/****************************************************************************/ 14285101Semaste#ifndef m5307sim_h 15285101Semaste#define m5307sim_h 16285101Semaste/****************************************************************************/ 17285101Semaste 18285101Semaste#define CPU_NAME "COLDFIRE(m5307)" 19353358Sdim#define CPU_INSTR_PER_JIFFY 3 20353358Sdim#define MCF_BUSCLK (MCF_CLK / 2) 21353358Sdim 22285101Semaste#include <asm/m53xxacr.h> 23314564Sdim 24314564Sdim/* 25353358Sdim * Define the 5307 SIM register set addresses. 26353358Sdim */ 27314564Sdim#define MCFSIM_RSR (MCF_MBAR + 0x00) /* Reset Status reg */ 28285101Semaste#define MCFSIM_SYPCR (MCF_MBAR + 0x01) /* System Protection */ 29285101Semaste#define MCFSIM_SWIVR (MCF_MBAR + 0x02) /* SW Watchdog intr */ 30314564Sdim#define MCFSIM_SWSR (MCF_MBAR + 0x03) /* SW Watchdog service*/ 31314564Sdim#define MCFSIM_PAR (MCF_MBAR + 0x04) /* Pin Assignment */ 32353358Sdim#define MCFSIM_IRQPAR (MCF_MBAR + 0x06) /* Itr Assignment */ 33353358Sdim#define MCFSIM_PLLCR (MCF_MBAR + 0x08) /* PLL Ctrl Reg */ 34314564Sdim#define MCFSIM_MPARK (MCF_MBAR + 0x0C) /* BUS Master Ctrl */ 35344779Sdim#define MCFSIM_IPR (MCF_MBAR + 0x40) /* Interrupt Pend */ 36314564Sdim#define MCFSIM_IMR (MCF_MBAR + 0x44) /* Interrupt Mask */ 37285101Semaste#define MCFSIM_AVR (MCF_MBAR + 0x4b) /* Autovector Ctrl */ 38285101Semaste#define MCFSIM_ICR0 (MCF_MBAR + 0x4c) /* Intr Ctrl reg 0 */ 39314564Sdim#define MCFSIM_ICR1 (MCF_MBAR + 0x4d) /* Intr Ctrl reg 1 */ 40314564Sdim#define MCFSIM_ICR2 (MCF_MBAR + 0x4e) /* Intr Ctrl reg 2 */ 41353358Sdim#define MCFSIM_ICR3 (MCF_MBAR + 0x4f) /* Intr Ctrl reg 3 */ 42353358Sdim#define MCFSIM_ICR4 (MCF_MBAR + 0x50) /* Intr Ctrl reg 4 */ 43353358Sdim#define MCFSIM_ICR5 (MCF_MBAR + 0x51) /* Intr Ctrl reg 5 */ 44314564Sdim#define MCFSIM_ICR6 (MCF_MBAR + 0x52) /* Intr Ctrl reg 6 */ 45344779Sdim#define MCFSIM_ICR7 (MCF_MBAR + 0x53) /* Intr Ctrl reg 7 */ 46314564Sdim#define MCFSIM_ICR8 (MCF_MBAR + 0x54) /* Intr Ctrl reg 8 */ 47314564Sdim#define MCFSIM_ICR9 (MCF_MBAR + 0x55) /* Intr Ctrl reg 9 */ 48285101Semaste#define MCFSIM_ICR10 (MCF_MBAR + 0x56) /* Intr Ctrl reg 10 */ 49285101Semaste#define MCFSIM_ICR11 (MCF_MBAR + 0x57) /* Intr Ctrl reg 11 */ 50314564Sdim 51314564Sdim#define MCFSIM_CSAR0 (MCF_MBAR + 0x80) /* CS 0 Address reg */ 52353358Sdim#define MCFSIM_CSMR0 (MCF_MBAR + 0x84) /* CS 0 Mask reg */ 53353358Sdim#define MCFSIM_CSCR0 (MCF_MBAR + 0x8a) /* CS 0 Control reg */ 54353358Sdim#define MCFSIM_CSAR1 (MCF_MBAR + 0x8c) /* CS 1 Address reg */ 55296417Sdim#define MCFSIM_CSMR1 (MCF_MBAR + 0x90) /* CS 1 Mask reg */ 56296417Sdim#define MCFSIM_CSCR1 (MCF_MBAR + 0x96) /* CS 1 Control reg */ 57314564Sdim 58285101Semaste#ifdef CONFIG_OLDMASK 59314564Sdim#define MCFSIM_CSBAR (MCF_MBAR + 0x98) /* CS Base Address */ 60285101Semaste#define MCFSIM_CSBAMR (MCF_MBAR + 0x9c) /* CS Base Mask */ 61314564Sdim#define MCFSIM_CSMR2 (MCF_MBAR + 0x9e) /* CS 2 Mask reg */ 62353358Sdim#define MCFSIM_CSCR2 (MCF_MBAR + 0xa2) /* CS 2 Control reg */ 63353358Sdim#define MCFSIM_CSMR3 (MCF_MBAR + 0xaa) /* CS 3 Mask reg */ 64353358Sdim#define MCFSIM_CSCR3 (MCF_MBAR + 0xae) /* CS 3 Control reg */ 65314564Sdim#define MCFSIM_CSMR4 (MCF_MBAR + 0xb6) /* CS 4 Mask reg */ 66353358Sdim#define MCFSIM_CSCR4 (MCF_MBAR + 0xba) /* CS 4 Control reg */ 67353358Sdim#define MCFSIM_CSMR5 (MCF_MBAR + 0xc2) /* CS 5 Mask reg */ 68285101Semaste#define MCFSIM_CSCR5 (MCF_MBAR + 0xc6) /* CS 5 Control reg */ 69285101Semaste#define MCFSIM_CSMR6 (MCF_MBAR + 0xce) /* CS 6 Mask reg */ 70353358Sdim#define MCFSIM_CSCR6 (MCF_MBAR + 0xd2) /* CS 6 Control reg */ 71353358Sdim#define MCFSIM_CSMR7 (MCF_MBAR + 0xda) /* CS 7 Mask reg */ 72285101Semaste#define MCFSIM_CSCR7 (MCF_MBAR + 0xde) /* CS 7 Control reg */ 73353358Sdim#else 74353358Sdim#define MCFSIM_CSAR2 (MCF_MBAR + 0x98) /* CS 2 Address reg */ 75353358Sdim#define MCFSIM_CSMR2 (MCF_MBAR + 0x9c) /* CS 2 Mask reg */ 76314564Sdim#define MCFSIM_CSCR2 (MCF_MBAR + 0xa2) /* CS 2 Control reg */ 77353358Sdim#define MCFSIM_CSAR3 (MCF_MBAR + 0xa4) /* CS 3 Address reg */ 78353358Sdim#define MCFSIM_CSMR3 (MCF_MBAR + 0xa8) /* CS 3 Mask reg */ 79314564Sdim#define MCFSIM_CSCR3 (MCF_MBAR + 0xae) /* CS 3 Control reg */ 80285101Semaste#define MCFSIM_CSAR4 (MCF_MBAR + 0xb0) /* CS 4 Address reg */ 81285101Semaste#define MCFSIM_CSMR4 (MCF_MBAR + 0xb4) /* CS 4 Mask reg */ 82314564Sdim#define MCFSIM_CSCR4 (MCF_MBAR + 0xba) /* CS 4 Control reg */ 83353358Sdim#define MCFSIM_CSAR5 (MCF_MBAR + 0xbc) /* CS 5 Address reg */ 84353358Sdim#define MCFSIM_CSMR5 (MCF_MBAR + 0xc0) /* CS 5 Mask reg */ 85314564Sdim#define MCFSIM_CSCR5 (MCF_MBAR + 0xc6) /* CS 5 Control reg */ 86285101Semaste#define MCFSIM_CSAR6 (MCF_MBAR + 0xc8) /* CS 6 Address reg */ 87285101Semaste#define MCFSIM_CSMR6 (MCF_MBAR + 0xcc) /* CS 6 Mask reg */ 88314564Sdim#define MCFSIM_CSCR6 (MCF_MBAR + 0xd2) /* CS 6 Control reg */ 89353358Sdim#define MCFSIM_CSAR7 (MCF_MBAR + 0xd4) /* CS 7 Address reg */ 90353358Sdim#define MCFSIM_CSMR7 (MCF_MBAR + 0xd8) /* CS 7 Mask reg */ 91314564Sdim#define MCFSIM_CSCR7 (MCF_MBAR + 0xde) /* CS 7 Control reg */ 92285101Semaste#endif /* CONFIG_OLDMASK */ 93285101Semaste 94314564Sdim#define MCFSIM_DCR (MCF_MBAR + 0x100) /* DRAM Control */ 95353358Sdim#define MCFSIM_DACR0 (MCF_MBAR + 0x108) /* DRAM Addr/Ctrl 0 */ 96353358Sdim#define MCFSIM_DMR0 (MCF_MBAR + 0x10c) /* DRAM Mask 0 */ 97314564Sdim#define MCFSIM_DACR1 (MCF_MBAR + 0x110) /* DRAM Addr/Ctrl 1 */ 98285101Semaste#define MCFSIM_DMR1 (MCF_MBAR + 0x114) /* DRAM Mask 1 */ 99285101Semaste 100314564Sdim/* 101353358Sdim * Timer module. 102353358Sdim */ 103353358Sdim#define MCFTIMER_BASE1 (MCF_MBAR + 0x140) /* Base of TIMER1 */ 104314564Sdim#define MCFTIMER_BASE2 (MCF_MBAR + 0x180) /* Base of TIMER2 */ 105285101Semaste 106285101Semaste#define MCFSIM_PADDR (MCF_MBAR + 0x244) 107314564Sdim#define MCFSIM_PADAT (MCF_MBAR + 0x248) 108353358Sdim 109353358Sdim/* 110314564Sdim * DMA unit base addresses. 111344779Sdim */ 112314564Sdim#define MCFDMA_BASE0 (MCF_MBAR + 0x300) /* Base address DMA 0 */ 113314564Sdim#define MCFDMA_BASE1 (MCF_MBAR + 0x340) /* Base address DMA 1 */ 114285101Semaste#define MCFDMA_BASE2 (MCF_MBAR + 0x380) /* Base address DMA 2 */ 115285101Semaste#define MCFDMA_BASE3 (MCF_MBAR + 0x3C0) /* Base address DMA 3 */ 116314564Sdim 117353358Sdim/* 118353358Sdim * UART module. 119353358Sdim */ 120314564Sdim#if defined(CONFIG_NETtel) || defined(CONFIG_SECUREEDGEMP3) 121314564Sdim#define MCFUART_BASE0 (MCF_MBAR + 0x200) /* Base address UART0 */ 122314564Sdim#define MCFUART_BASE1 (MCF_MBAR + 0x1c0) /* Base address UART1 */ 123314564Sdim#else 124285101Semaste#define MCFUART_BASE0 (MCF_MBAR + 0x1c0) /* Base address UART0 */ 125285101Semaste#define MCFUART_BASE1 (MCF_MBAR + 0x200) /* Base address UART1 */ 126314564Sdim#endif 127353358Sdim 128353358Sdim/* 129314564Sdim * Generic GPIO support 130285101Semaste */ 131285101Semaste#define MCFGPIO_PIN_MAX 16 132314564Sdim#define MCFGPIO_IRQ_MAX -1 133353358Sdim#define MCFGPIO_IRQ_VECBASE -1 134353358Sdim 135314564Sdim 136285101Semaste/* Definition offset address for CS2-7 -- old mask 5307 */ 137285101Semaste 138314564Sdim#define MCF5307_CS2 (0x400000) 139353358Sdim#define MCF5307_CS3 (0x600000) 140353358Sdim#define MCF5307_CS4 (0x800000) 141353358Sdim#define MCF5307_CS5 (0xA00000) 142314564Sdim#define MCF5307_CS6 (0xC00000) 143314564Sdim#define MCF5307_CS7 (0xE00000) 144285101Semaste 145285101Semaste 146314564Sdim/* 147353358Sdim * Some symbol defines for the above... 148353358Sdim */ 149314564Sdim#define MCFSIM_SWDICR MCFSIM_ICR0 /* Watchdog timer ICR */ 150296417Sdim#define MCFSIM_TIMER1ICR MCFSIM_ICR1 /* Timer 1 ICR */ 151296417Sdim#define MCFSIM_TIMER2ICR MCFSIM_ICR2 /* Timer 2 ICR */ 152314564Sdim#define MCFSIM_I2CICR MCFSIM_ICR3 /* I2C ICR */ 153353358Sdim#define MCFSIM_UART1ICR MCFSIM_ICR4 /* UART 1 ICR */ 154353358Sdim#define MCFSIM_UART2ICR MCFSIM_ICR5 /* UART 2 ICR */ 155314564Sdim#define MCFSIM_DMA0ICR MCFSIM_ICR6 /* DMA 0 ICR */ 156285101Semaste#define MCFSIM_DMA1ICR MCFSIM_ICR7 /* DMA 1 ICR */ 157285101Semaste#define MCFSIM_DMA2ICR MCFSIM_ICR8 /* DMA 2 ICR */ 158353358Sdim#define MCFSIM_DMA3ICR MCFSIM_ICR9 /* DMA 3 ICR */ 159353358Sdim 160285101Semaste/* 161353358Sdim * Some symbol defines for the Parallel Port Pin Assignment Register 162353358Sdim */ 163285101Semaste#define MCFSIM_PAR_DREQ0 0x40 /* Set to select DREQ0 input */ 164353358Sdim /* Clear to select par I/O */ 165353358Sdim#define MCFSIM_PAR_DREQ1 0x20 /* Select DREQ1 input */ 166285101Semaste /* Clear to select par I/O */ 167353358Sdim 168353358Sdim/* 169285101Semaste * Defines for the IRQPAR Register 170353358Sdim */ 171353358Sdim#define IRQ5_LEVEL4 0x80 172285101Semaste#define IRQ3_LEVEL6 0x40 173353358Sdim#define IRQ1_LEVEL2 0x20 174353358Sdim 175285101Semaste/* 176353358Sdim * Define system peripheral IRQ usage. 177353358Sdim */ 178353358Sdim#define MCF_IRQ_I2C0 29 /* I2C, Level 5 */ 179353358Sdim#define MCF_IRQ_TIMER 30 /* Timer0, Level 6 */ 180353358Sdim#define MCF_IRQ_PROFILER 31 /* Timer1, Level 7 */ 181353358Sdim#define MCF_IRQ_UART0 73 /* UART0 */ 182353358Sdim#define MCF_IRQ_UART1 74 /* UART1 */ 183353358Sdim 184353358Sdim/* 185353358Sdim * I2C module 186353358Sdim */ 187353358Sdim#define MCFI2C_BASE0 (MCF_MBAR + 0x280) 188353358Sdim#define MCFI2C_SIZE0 0x40 189353358Sdim 190353358Sdim/****************************************************************************/ 191353358Sdim#endif /* m5307sim_h */ 192353358Sdim