include/asm/m525xsim.h

35 #define MCFSIM_RSR		(MCF_MBAR + 0x00)	/* Reset Status */
36 #define MCFSIM_SYPCR		(MCF_MBAR + 0x01)	/* System Protection */
37 #define MCFSIM_SWIVR		(MCF_MBAR + 0x02)	/* SW Watchdog intr */
38 #define MCFSIM_SWSR		(MCF_MBAR + 0x03)	/* SW Watchdog srv */
39 #define MCFSIM_MPARK		(MCF_MBAR + 0x0C)	/* BUS Master Ctrl */
40 #define MCFSIM_IPR		(MCF_MBAR + 0x40)	/* Interrupt Pending */
41 #define MCFSIM_IMR		(MCF_MBAR + 0x44)	/* Interrupt Mask */
42 #define MCFSIM_ICR0		(MCF_MBAR + 0x4c)	/* Intr Ctrl reg 0 */
43 #define MCFSIM_ICR1		(MCF_MBAR + 0x4d)	/* Intr Ctrl reg 1 */
44 #define MCFSIM_ICR2		(MCF_MBAR + 0x4e)	/* Intr Ctrl reg 2 */
45 #define MCFSIM_ICR3		(MCF_MBAR + 0x4f)	/* Intr Ctrl reg 3 */
46 #define MCFSIM_ICR4		(MCF_MBAR + 0x50)	/* Intr Ctrl reg 4 */
47 #define MCFSIM_ICR5		(MCF_MBAR + 0x51)	/* Intr Ctrl reg 5 */
48 #define MCFSIM_ICR6		(MCF_MBAR + 0x52)	/* Intr Ctrl reg 6 */
49 #define MCFSIM_ICR7		(MCF_MBAR + 0x53)	/* Intr Ctrl reg 7 */
50 #define MCFSIM_ICR8		(MCF_MBAR + 0x54)	/* Intr Ctrl reg 8 */
51 #define MCFSIM_ICR9		(MCF_MBAR + 0x55)	/* Intr Ctrl reg 9 */
52 #define MCFSIM_ICR10		(MCF_MBAR + 0x56)	/* Intr Ctrl reg 10 */
53 #define MCFSIM_ICR11		(MCF_MBAR + 0x57)	/* Intr Ctrl reg 11 */
55 #define MCFSIM_CSAR0		(MCF_MBAR + 0x80)	/* CS 0 Address reg */
56 #define MCFSIM_CSMR0		(MCF_MBAR + 0x84)	/* CS 0 Mask reg */
57 #define MCFSIM_CSCR0		(MCF_MBAR + 0x8a)	/* CS 0 Control reg */
58 #define MCFSIM_CSAR1		(MCF_MBAR + 0x8c)	/* CS 1 Address reg */
59 #define MCFSIM_CSMR1		(MCF_MBAR + 0x90)	/* CS 1 Mask reg */
60 #define MCFSIM_CSCR1		(MCF_MBAR + 0x96)	/* CS 1 Control reg */
61 #define MCFSIM_CSAR2		(MCF_MBAR + 0x98)	/* CS 2 Address reg */
62 #define MCFSIM_CSMR2		(MCF_MBAR + 0x9c)	/* CS 2 Mask reg */
63 #define MCFSIM_CSCR2		(MCF_MBAR + 0xa2)	/* CS 2 Control reg */
64 #define MCFSIM_CSAR3		(MCF_MBAR + 0xa4)	/* CS 3 Address reg */
65 #define MCFSIM_CSMR3		(MCF_MBAR + 0xa8)	/* CS 3 Mask reg */
66 #define MCFSIM_CSCR3		(MCF_MBAR + 0xae)	/* CS 3 Control reg */
67 #define MCFSIM_CSAR4		(MCF_MBAR + 0xb0)	/* CS 4 Address reg */
68 #define MCFSIM_CSMR4		(MCF_MBAR + 0xb4)	/* CS 4 Mask reg */
69 #define MCFSIM_CSCR4		(MCF_MBAR + 0xba)	/* CS 4 Control reg */
71 #define MCFSIM_DCR		(MCF_MBAR + 0x100)	/* DRAM Control */
72 #define MCFSIM_DACR0		(MCF_MBAR + 0x108)	/* DRAM 0 Addr/Ctrl */
73 #define MCFSIM_DMR0		(MCF_MBAR + 0x10c)	/* DRAM 0 Mask */
74 #define MCFSIM_DACR1		(MCF_MBAR + 0x110)	/* DRAM 1 Addr/Ctrl */
75 #define MCFSIM_DMR1		(MCF_MBAR + 0x114)	/* DRAM 1 Mask */
97 #define MCFTIMER_BASE1		(MCF_MBAR + 0x140)	/* Base of TIMER1 */
98 #define MCFTIMER_BASE2		(MCF_MBAR + 0x180)	/* Base of TIMER2 */
103 #define MCFUART_BASE0		(MCF_MBAR + 0x1c0)	/* Base address UART0 */
104 #define MCFUART_BASE1		(MCF_MBAR + 0x200)	/* Base address UART1 */
109 #define MCFQSPI_BASE		(MCF_MBAR + 0x400)	/* Base address QSPI */
127 #define MCFI2C_BASE0		(MCF_MBAR + 0x280)	/* Base address I2C0 */
136 #define MCFDMA_BASE0		(MCF_MBAR + 0x300)	/* Base address DMA 0 */
137 #define MCFDMA_BASE1		(MCF_MBAR + 0x340)	/* Base address DMA 1 */
138 #define MCFDMA_BASE2		(MCF_MBAR + 0x380)	/* Base address DMA 2 */
139 #define MCFDMA_BASE3		(MCF_MBAR + 0x3C0)	/* Base address DMA 3 */