Lines Matching refs:MCF_MBAR
25 #define MCFSIM_SIMR (MCF_MBAR + 0x03) /* SIM Config reg */
26 #define MCFSIM_ICR1 (MCF_MBAR + 0x14) /* Intr Ctrl reg 1 */
27 #define MCFSIM_ICR2 (MCF_MBAR + 0x15) /* Intr Ctrl reg 2 */
28 #define MCFSIM_ICR3 (MCF_MBAR + 0x16) /* Intr Ctrl reg 3 */
29 #define MCFSIM_ICR4 (MCF_MBAR + 0x17) /* Intr Ctrl reg 4 */
30 #define MCFSIM_ICR5 (MCF_MBAR + 0x18) /* Intr Ctrl reg 5 */
31 #define MCFSIM_ICR6 (MCF_MBAR + 0x19) /* Intr Ctrl reg 6 */
32 #define MCFSIM_ICR7 (MCF_MBAR + 0x1a) /* Intr Ctrl reg 7 */
33 #define MCFSIM_ICR8 (MCF_MBAR + 0x1b) /* Intr Ctrl reg 8 */
34 #define MCFSIM_ICR9 (MCF_MBAR + 0x1c) /* Intr Ctrl reg 9 */
35 #define MCFSIM_ICR10 (MCF_MBAR + 0x1d) /* Intr Ctrl reg 10 */
36 #define MCFSIM_ICR11 (MCF_MBAR + 0x1e) /* Intr Ctrl reg 11 */
37 #define MCFSIM_ICR12 (MCF_MBAR + 0x1f) /* Intr Ctrl reg 12 */
38 #define MCFSIM_ICR13 (MCF_MBAR + 0x20) /* Intr Ctrl reg 13 */
40 #define MCFSIM_ICR14 (MCF_MBAR + 0x21) /* Intr Ctrl reg 14 */
41 #define MCFSIM_ICR15 (MCF_MBAR + 0x22) /* Intr Ctrl reg 15 */
44 #define MCFSIM_IMR (MCF_MBAR + 0x36) /* Interrupt Mask */
45 #define MCFSIM_IPR (MCF_MBAR + 0x3a) /* Interrupt Pending */
47 #define MCFSIM_RSR (MCF_MBAR + 0x40) /* Reset Status */
48 #define MCFSIM_SYPCR (MCF_MBAR + 0x41) /* System Protection */
50 #define MCFSIM_SWIVR (MCF_MBAR + 0x42) /* SW Watchdog intr */
51 #define MCFSIM_SWSR (MCF_MBAR + 0x43) /* SW Watchdog srv */
53 #define MCFSIM_DCRR (MCF_MBAR + 0x46) /* DRAM Refresh reg (r/w) */
54 #define MCFSIM_DCTR (MCF_MBAR + 0x4a) /* DRAM Timing reg (r/w) */
55 #define MCFSIM_DAR0 (MCF_MBAR + 0x4c) /* DRAM 0 Address reg(r/w) */
56 #define MCFSIM_DMR0 (MCF_MBAR + 0x50) /* DRAM 0 Mask reg (r/w) */
57 #define MCFSIM_DCR0 (MCF_MBAR + 0x57) /* DRAM 0 Control reg (r/w) */
58 #define MCFSIM_DAR1 (MCF_MBAR + 0x58) /* DRAM 1 Address reg (r/w) */
59 #define MCFSIM_DMR1 (MCF_MBAR + 0x5c) /* DRAM 1 Mask reg (r/w) */
60 #define MCFSIM_DCR1 (MCF_MBAR + 0x63) /* DRAM 1 Control reg (r/w) */
62 #define MCFSIM_CSAR0 (MCF_MBAR + 0x64) /* CS 0 Address reg */
63 #define MCFSIM_CSMR0 (MCF_MBAR + 0x68) /* CS 0 Mask reg */
64 #define MCFSIM_CSCR0 (MCF_MBAR + 0x6e) /* CS 0 Control reg */
65 #define MCFSIM_CSAR1 (MCF_MBAR + 0x70) /* CS 1 Address reg */
66 #define MCFSIM_CSMR1 (MCF_MBAR + 0x74) /* CS 1 Mask reg */
67 #define MCFSIM_CSCR1 (MCF_MBAR + 0x7a) /* CS 1 Control reg */
68 #define MCFSIM_CSAR2 (MCF_MBAR + 0x7c) /* CS 2 Address reg */
69 #define MCFSIM_CSMR2 (MCF_MBAR + 0x80) /* CS 2 Mask reg */
70 #define MCFSIM_CSCR2 (MCF_MBAR + 0x86) /* CS 2 Control reg */
71 #define MCFSIM_CSAR3 (MCF_MBAR + 0x88) /* CS 3 Address reg */
72 #define MCFSIM_CSMR3 (MCF_MBAR + 0x8c) /* CS 3 Mask reg */
73 #define MCFSIM_CSCR3 (MCF_MBAR + 0x92) /* CS 3 Control reg */
74 #define MCFSIM_CSAR4 (MCF_MBAR + 0x94) /* CS 4 Address reg */
75 #define MCFSIM_CSMR4 (MCF_MBAR + 0x98) /* CS 4 Mask reg */
76 #define MCFSIM_CSCR4 (MCF_MBAR + 0x9e) /* CS 4 Control reg */
77 #define MCFSIM_CSAR5 (MCF_MBAR + 0xa0) /* CS 5 Address reg */
78 #define MCFSIM_CSMR5 (MCF_MBAR + 0xa4) /* CS 5 Mask reg */
79 #define MCFSIM_CSCR5 (MCF_MBAR + 0xaa) /* CS 5 Control reg */
80 #define MCFSIM_CSAR6 (MCF_MBAR + 0xac) /* CS 6 Address reg */
81 #define MCFSIM_CSMR6 (MCF_MBAR + 0xb0) /* CS 6 Mask reg */
82 #define MCFSIM_CSCR6 (MCF_MBAR + 0xb6) /* CS 6 Control reg */
83 #define MCFSIM_CSAR7 (MCF_MBAR + 0xb8) /* CS 7 Address reg */
84 #define MCFSIM_CSMR7 (MCF_MBAR + 0xbc) /* CS 7 Mask reg */
85 #define MCFSIM_CSCR7 (MCF_MBAR + 0xc2) /* CS 7 Control reg */
86 #define MCFSIM_DMCR (MCF_MBAR + 0xc6) /* Default control */
89 #define MCFSIM_PAR (MCF_MBAR + 0xca) /* Pin Assignment */
91 #define MCFSIM_PAR (MCF_MBAR + 0xcb) /* Pin Assignment */
94 #define MCFTIMER_BASE1 (MCF_MBAR + 0x100) /* Base of TIMER1 */
95 #define MCFTIMER_BASE2 (MCF_MBAR + 0x120) /* Base of TIMER2 */
97 #define MCFSIM_PADDR (MCF_MBAR + 0x1c5) /* Parallel Direction (r/w) */
98 #define MCFSIM_PADAT (MCF_MBAR + 0x1c9) /* Parallel Port Value (r/w) */
100 #define MCFDMA_BASE0 (MCF_MBAR + 0x200) /* Base address DMA 0 */
101 #define MCFDMA_BASE1 (MCF_MBAR + 0x240) /* Base address DMA 1 */
104 #define MCFUART_BASE0 (MCF_MBAR + 0x180) /* Base address UART0 */
105 #define MCFUART_BASE1 (MCF_MBAR + 0x140) /* Base address UART1 */
107 #define MCFUART_BASE0 (MCF_MBAR + 0x140) /* Base address UART0 */
108 #define MCFUART_BASE1 (MCF_MBAR + 0x180) /* Base address UART1 */
154 #define MCFI2C_BASE0 (MCF_MBAR + 0x1e0)