Searched refs:HCFG (Results 1 - 11 of 11) sorted by last modified time
| /linux-master/sound/pci/emu10k1/ |
| H A D | emumixer.c | 1872 ucontrol->value.integer.value[0] = inl(emu->port + HCFG) & HCFG_GPOUT0 ? 1 : 0;
1903 reg = inl(emu->port + HCFG);
1909 outl(reg | val, emu->port + HCFG);
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| H A D | emu10k1_main.c | 146 HCFG_MUTEBUTTONENABLE, emu->port + HCFG);
274 HCFG_AUDIOENABLE, emu->port + HCFG);
276 * Hokay, setup HCFG
287 HCFG_AUTOMUTE | HCFG_JOYENABLE, emu->port + HCFG);
289 outl(HCFG_AUTOMUTE | HCFG_JOYENABLE, emu->port + HCFG);
295 outl(HCFG_LOCKTANKCACHE_MASK | HCFG_AUTOMUTE, emu->port + HCFG);
298 outl(HCFG_LOCKTANKCACHE_MASK | HCFG_AUTOMUTE | HCFG_JOYENABLE, emu->port + HCFG);
313 unsigned int reg = inl(emu->port + HCFG);
314 outl(reg | HCFG_GPOUT2, emu->port + HCFG);
316 outl(reg | HCFG_GPOUT1 | HCFG_GPOUT2, emu->port + HCFG);
[all...] |
| H A D | emufx.c | 2418 outl(HCFG_LOCKTANKCACHE_MASK | inl(emu->port + HCFG), emu->port + HCFG);
2436 outl(inl(emu->port + HCFG) & ~HCFG_LOCKTANKCACHE_MASK, emu->port + HCFG);
2704 outl(HCFG_LOCKTANKCACHE_MASK | inl(emu->port + HCFG), emu->port + HCFG);
2707 outl(inl(emu->port + HCFG) & ~HCFG_LOCKTANKCACHE_MASK, emu->port + HCFG);
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| H A D | emu10k1x.c | 77 #define HCFG 0x14 /* Hardware config register */ macro
747 outl(HCFG_LOCKSOUNDCACHE, chip->port + HCFG);
958 outl(HCFG_LOCKSOUNDCACHE|HCFG_AUDIOENABLE, chip->port+HCFG);
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| /linux-master/include/sound/ |
| H A D | emu10k1.h | 189 #define HCFG 0x14 /* Hardware config register */ macro
233 /* Rest of HCFG 0x0000000f same as below. LOCKSOUNDCACHE etc. */
259 SUB_REG(HCFG, LOCKTANKCACHE, 0x00000004) /* 1 = Cancel bustmaster accesses to tankcache */
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| /linux-master/drivers/usb/dwc2/ |
| H A D | hcd_ddma.c | 158 hcfg = dwc2_readl(hsotg, HCFG);
170 dwc2_writel(hsotg, hcfg, HCFG);
182 hcfg = dwc2_readl(hsotg, HCFG);
191 dwc2_writel(hsotg, hcfg, HCFG);
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| H A D | hw.h | 658 #define HCFG HSOTG_REG(0x0400) macro
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| H A D | hcd.c | 2154 hcfg = dwc2_readl(hsotg, HCFG);
2156 dwc2_writel(hsotg, hcfg, HCFG);
2184 hcfg = dwc2_readl(hsotg, HCFG);
2186 dwc2_writel(hsotg, hcfg, HCFG);
3602 hcfg = dwc2_readl(hsotg, HCFG);
3604 dwc2_writel(hsotg, hcfg, HCFG);
5121 hcfg = dwc2_readl(hsotg, HCFG);
5416 hr->hcfg = dwc2_readl(hsotg, HCFG);
5459 dwc2_writel(hsotg, hr->hcfg, HCFG);
5630 /* Restore GUSBCFG, HCFG */
[all...] |
| H A D | hcd_intr.c | 272 hcfg = dwc2_readl(hsotg, HCFG);
280 "FS_PHY programming HCFG to 6 MHz\n");
285 dwc2_writel(hsotg, hcfg, HCFG);
291 "FS_PHY programming HCFG to 48 MHz\n");
296 dwc2_writel(hsotg, hcfg, HCFG);
379 hcfg = dwc2_readl(hsotg, HCFG);
381 dwc2_writel(hsotg, hcfg, HCFG);
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| H A D | core.c | 181 /* Restore GUSBCFG and HCFG/DCFG */
185 dwc2_writel(hsotg, hr->hcfg, HCFG);
625 addr = hsotg->regs + HCFG;
626 dev_dbg(hsotg->dev, "HCFG @0x%08lX : 0x%08X\n",
627 (unsigned long)addr, dwc2_readl(hsotg, HCFG));
953 * Initializes the FSLSPClkSel field of the HCFG register depending on the
971 dev_dbg(hsotg->dev, "Initializing HCFG.FSLSPClkSel to %08x\n", val);
972 hcfg = dwc2_readl(hsotg, HCFG);
975 dwc2_writel(hsotg, hcfg, HCFG);
1020 * Program DCFG.DevSpd or HCFG
[all...] |
| H A D | debugfs.c | 539 dump_register(HCFG),
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Completed in 231 milliseconds