/linux-master/drivers/gpu/drm/amd/display/dc/dcn10/ |
H A D | dcn10_stream_encoder.c | 765 REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP0_ENABLE, info_frame->vsc.valid); 766 REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP2_ENABLE, info_frame->spd.valid); 767 REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP3_ENABLE, info_frame->hdrsmd.valid); 768 REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP5_ENABLE, info_frame->adaptive_sync.valid); 777 value = REG_READ(DP_SEC_CNTL); 779 REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1); 871 value = REG_READ(DP_SEC_CNTL); 873 REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1); 883 REG_SET_10(DP_SEC_CNTL, 0, 898 value = REG_READ(DP_SEC_CNTL); [all...] |
H A D | dcn10_link_encoder.h | 61 SRI(DP_SEC_CNTL, DP, id), \ 103 uint32_t DP_SEC_CNTL; member in struct:dcn10_link_enc_registers
|
H A D | dcn10_stream_encoder.h | 85 SRI(DP_SEC_CNTL, DP, id), \ 135 uint32_t DP_SEC_CNTL; member in struct:dcn10_stream_enc_registers
|
/linux-master/drivers/gpu/drm/amd/display/dc/dcn30/ |
H A D | dcn30_dio_stream_encoder.c | 377 REG_UPDATE(DP_SEC_CNTL, 404 REG_GET(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, &s->sec_stream_enable); 497 REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP0_ENABLE, info_frame->vsc.valid); 498 REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP2_ENABLE, info_frame->spd.valid); 499 REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP3_ENABLE, info_frame->hdrsmd.valid); 500 REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP5_ENABLE, info_frame->adaptive_sync.valid); 509 value = REG_READ(DP_SEC_CNTL); 511 REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1); 518 REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
|
H A D | dcn30_dio_link_encoder.h | 50 SRI(DP_SEC_CNTL, DP, id), \
|
H A D | dcn30_dio_stream_encoder.h | 87 SRI(DP_SEC_CNTL, DP, id), \
|
/linux-master/drivers/gpu/drm/amd/display/dc/dce/ |
H A D | dce_stream_encoder.c | 858 REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP0_ENABLE, info_frame->vsc.valid); 859 REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP2_ENABLE, info_frame->spd.valid); 860 REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP3_ENABLE, info_frame->hdrsmd.valid); 869 value = REG_READ(DP_SEC_CNTL); 871 REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1); 882 REG_SET_7(DP_SEC_CNTL, 0, 895 value = REG_READ(DP_SEC_CNTL); 897 REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1); 1403 REG_UPDATE(DP_SEC_CNTL, DP_SEC_ASP_ENABLE, 1); 1406 REG_UPDATE_2(DP_SEC_CNTL, [all...] |
H A D | dce_stream_encoder.h | 87 SRI(DP_SEC_CNTL, DP, id), \ 155 SE_SF(DP_SEC_CNTL, DP_SEC_GSP0_ENABLE, mask_sh),\ 156 SE_SF(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, mask_sh),\ 157 SE_SF(DP_SEC_CNTL, DP_SEC_GSP1_ENABLE, mask_sh),\ 158 SE_SF(DP_SEC_CNTL, DP_SEC_GSP2_ENABLE, mask_sh),\ 159 SE_SF(DP_SEC_CNTL, DP_SEC_GSP3_ENABLE, mask_sh),\ 160 SE_SF(DP_SEC_CNTL, DP_SEC_AVI_ENABLE, mask_sh),\ 161 SE_SF(DP_SEC_CNTL, DP_SEC_MPG_ENABLE, mask_sh),\ 199 SE_SF(DP_SEC_CNTL, DP_SEC_ASP_ENABLE, mask_sh),\ 200 SE_SF(DP_SEC_CNTL, DP_SEC_ATP_ENABL 659 uint32_t DP_SEC_CNTL; member in struct:dce110_stream_enc_registers [all...] |
H A D | dce_link_encoder.h | 68 SRI(DP_SEC_CNTL, DP, id), \ 101 SRI(DP_SEC_CNTL, DP, id), \ 178 uint32_t DP_SEC_CNTL; member in struct:dce110_link_enc_registers
|
/linux-master/drivers/gpu/drm/amd/display/dc/dcn301/ |
H A D | dcn301_dio_link_encoder.h | 51 SRI(DP_SEC_CNTL, DP, id), \
|
/linux-master/drivers/gpu/drm/amd/display/dc/dcn20/ |
H A D | dcn20_stream_encoder.c | 318 //REG_UPDATE(DP_SEC_CNTL, 337 REG_UPDATE_2(DP_SEC_CNTL, 342 REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP7_ENABLE, 0); 364 REG_GET(DP_SEC_CNTL, DP_SEC_GSP7_ENABLE, &s->sec_gsp_pps_enable); 365 REG_GET(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, &s->sec_stream_enable); 456 REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
|
/linux-master/drivers/gpu/drm/amd/display/dc/dcn32/ |
H A D | dcn32_dio_stream_encoder.c | 414 REG_GET(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, &s->sec_stream_enable);
|
/linux-master/drivers/gpu/drm/amd/display/dc/dcn314/ |
H A D | dcn314_dio_stream_encoder.c | 409 REG_GET(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, &s->sec_stream_enable);
|
H A D | dcn314_dio_stream_encoder.h | 88 SRI(DP_SEC_CNTL, DP, id), \
|
/linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn35/ |
H A D | dcn35_resource.h | 118 SRI_ARR(DP_SEC_CNTL, DP, id), \
|
/linux-master/drivers/gpu/drm/amd/display/dc/dcn35/ |
H A D | dcn35_dio_stream_encoder.h | 87 SRI(DP_SEC_CNTL, DP, id), \
|
/linux-master/drivers/gpu/drm/amd/amdgpu/ |
H A D | dce_v6_0.c | 1653 tmp = REG_SET_FIELD(tmp, DP_SEC_CNTL, DP_SEC_ASP_ENABLE, 1); 1654 tmp = REG_SET_FIELD(tmp, DP_SEC_CNTL, DP_SEC_ATP_ENABLE, 1); 1655 tmp = REG_SET_FIELD(tmp, DP_SEC_CNTL, DP_SEC_AIP_ENABLE, 1); 1656 tmp = REG_SET_FIELD(tmp, DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
|
/linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn32/ |
H A D | dcn32_resource.h | 286 SRI_ARR(DP_PIXEL_FORMAT, DP, id), SRI_ARR(DP_SEC_CNTL, DP, id), \ 326 SRI_ARR(DP_SEC_CNTL, DP, id), SRI_ARR(DP_VID_STREAM_CNTL, DP, id), \
|