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473eb67c |
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02-Aug-2023 |
Qingqing Zhuo <Qingqing.Zhuo@amd.com> |
drm/amd/display: Update DCN10 for DCN35 support [Why & How] Update DCN10 files for DCN35 usage. Signed-off-by: Qingqing Zhuo <Qingqing.Zhuo@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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e42ce136 |
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01-Mar-2022 |
Dillon Varone <dillon.varone@amd.com> |
drm/amd/display: Fix USBC link creation [Description] Add USBC connector ID to align with new VBIOS parsing. Add seperate DCN321 link encoder due to different PHY version affecting DP ALT related registers. Signed-off-by: Dillon Varone <dillon.varone@amd.com> Acked-by: Jerry Zuo <jerry.zuo@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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8788e066 |
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28-Jan-2022 |
Wenjing Liu <wenjing.liu@amd.com> |
drm/amd/display: add set dp lane settings to link_hwss [why] Factor set dp lane settings to link_hwss. v2: fix statement with no effect warning (Alex) Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Stylon Wang <stylon.wang@amd.com> Signed-off-by: Wenjing Liu <wenjing.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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bdd1a21b |
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09-Sep-2021 |
Liu, Zhan <Zhan.Liu@amd.com> |
drm/amd/display: Fix B0 USB-C DP Alt mode [Why] Starting from B0, along with RDPCSTX, RDPCSPIPE registers are also used. [How] Make sure RDPCSPIPE registers are programmed correctly. Reviewed-by: Charlene Liu <charlene.liu@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Zhan Liu <Zhan.Liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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45d65c0f |
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09-Sep-2021 |
Liu, Zhan <Zhan.Liu@amd.com> |
drm/amd/display: Fix B0 USB-C DP Alt mode [Why] Starting from B0, along with RDPCSTX, RDPCSPIPE registers are also used. [How] Make sure RDPCSPIPE registers are programmed correctly. Reviewed-by: Charlene Liu <charlene.liu@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Zhan Liu <Zhan.Liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org (cherry picked from commit bdd1a21b52557ea8f61d0a5dc2f77151b576eb70)
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8fe44c08 |
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21-Jun-2021 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu/display: fold DRM_AMD_DC_DCN3_1 into DRM_AMD_DC_DCN No need for a separate flag now that DCN3.1 is not in bring up. Fold into DRM_AMD_DC_DCN like previous DCN IPs. Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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cbaf919f |
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19-May-2021 |
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> |
drm/amd/display: Add DCN3.1 DIO Add support for the DIO (Display IO) block of DCN3.1 which controls legacy HDMI/DP stream/link encoding. HW Blocks: +--------+ +--------+ | DIO | | DCCG | +--------+ +--------+ Includes some updates to core logic for link encoder assignment and future support for new high bandwidth output. v2: squash in unused variable fix (Alex) Acked-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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166590cc |
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25-Jan-2021 |
Derek Lai <Derek.Lai@amd.com> |
drm/amd/display: Add DIG_CLOCK_PATTERN in the transmitter control [Why and How] VBIOS program DIG_CLK_PATTERN using engine ID instead of PHY ID. Workaround by writing value for 0x1f (for HDMI) after calling vbios. Signed-off-by: Derek Lai <Derek.Lai@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Anson Jacob <Anson.Jacob@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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20f2ffe5 |
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02-Nov-2020 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: fold CONFIG_DRM_AMD_DC_DCN3* into CONFIG_DRM_AMD_DC_DCN (v3) Avoids confusion in configurations. v2: fix build when CONFIG_DRM_AMD_DC_DCN is disabled v3: rebase on latest code Reviewed-by: Luben Tuikov <luben.tuikov@amd.com> (v1) Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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3a83e4e6 |
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29-Sep-2020 |
Roman Li <Roman.Li@amd.com> |
drm/amd/display: Add dcn3.01 support to DC (v2) Update dc for vangogh support. v2: fix compilation without DCN 301 set. Signed-off-by: Roman Li <Roman.Li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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09821499 |
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19-Jul-2020 |
Igor Kravchenko <Igor.Kravchenko@amd.com> |
drm/amd/display: Read VBIOS Golden Settings Tbl [Why] For ver.4.4 and higher VBIOS contains default setting table. {How] Read Golden Settings Table from VBIOS, apply Aux tuning parameters. Signed-off-by: Igor Kravchenko <Igor.Kravchenko@amd.com> Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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6224220d |
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19-Jul-2020 |
Igor Kravchenko <Igor.Kravchenko@amd.com> |
drm/amd/display: Read VBIOS Golden Settings Tbl [Why] For ver.4.4 and higher VBIOS contains default setting table. {How] Read Golden Settings Table from VBIOS, apply Aux tuning parameters. Signed-off-by: Igor Kravchenko <Igor.Kravchenko@amd.com> Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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be547111 |
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22-May-2020 |
Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> |
drm/amd/display: Add DCN3 DIO Add support for the DIO (Display IO) block of DCN3, which entails our stream and link encoders. HW Blocks: +--------+ | DIO | +--------+ Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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8ccf0e20 |
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05-Apr-2020 |
Wenjing Liu <wenjing.liu@amd.com> |
drm/amd/display: determine USB C DP2 mode only when USB DP Alt is enabled [why] When display is connected with a native DP port, DP2 mode register value is a don't care. Driver mistakenly reduce max supported lane count to 2 lane based on the don't care value. [how] Add additional check only if USB C DP alt mode is enabled, we will determine max lane count supported based on current mode. Signed-off-by: Wenjing Liu <wenjing.liu@amd.com> Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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18952c8e |
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20-Jan-2020 |
Charlene Liu <Charlene.Liu@amd.com> |
drm/amd/display: guard DPPHY_Internal_ctrl [why] this register not exist in some asic, based on request remove this from dc. [how] add guard for sanization. Signed-off-by: Charlene Liu <Charlene.Liu@amd.com> Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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a771ded8 |
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27-Nov-2019 |
Roman Li <Roman.Li@amd.com> |
drm/amd/display: add missing dcn link encoder regs [Why] The earlier change: "check phy dpalt lane count config" uses link encoder registers not defined properly. That caused regression with mst-enabled display not lighting up. [How] Add missing reg definitions. Signed-off-by: Roman Li <Roman.Li@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
1da37801 |
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06-Nov-2019 |
Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> |
drm/amd/display: Drop CONFIG_DRM_AMD_DC_DCN2_0 and DSC_SUPPORTED [Why] DCN2 and DSC are stable enough to be build by default. So drop the flags. [How] Remove them using the unifdef tool. The following commands were executed in sequence: $ find -name '*.c' -exec unifdef -m -DCONFIG_DRM_AMD_DC_DSC_SUPPORT -DCONFIG_DRM_AMD_DC_DCN2_0 -UCONFIG_TRIM_DRM_AMD_DC_DCN2_0 '{}' ';' $ find -name '*.h' -exec unifdef -m -DCONFIG_DRM_AMD_DC_DSC_SUPPORT -DCONFIG_DRM_AMD_DC_DCN2_0 -UCONFIG_TRIM_DRM_AMD_DC_DCN2_0 '{}' ';' In addition: * Remove from kconfig, and replace any dependencies with DCN1_0. * Remove from any makefiles. * Fix and cleanup NV defninitions in dal_asic_id.h * Expand DCN1 ifdef to include DCN2 code in the following files: * clk_mgr/clk_mgr.c: dc_clk_mgr_create() * core/dc_resources.c: dc_create_resource_pool() * dce/dce_dmcu.c: dcn20_*lock_phy() * dce/dce_dmcu.c: dcn20_funcs * dce/dce_dmcu.c: dcn20_dmcu_create() * gpio/hw_factory.c: dal_hw_factory_init() * gpio/hw_translate.c: dal_hw_translate_init() Signed-off-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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c7e06b0d |
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11-Oct-2019 |
Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> |
drm/amd/display: handle dp is usb-c This patch adds handling of dp is usb-c, it is not tested but is needed to support dp over usb-c Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Reviewed-by: Roman Li <Roman.Li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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91c665bd |
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02-Oct-2019 |
Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> |
drm/amd/display: create dcn21_link_encoder files [Why] DCN20 and DCN21 have different phy programming sequences. [How] Create a separate dcn21_link_encoder for Renoir Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Reviewed-by: Roman Li <Roman.Li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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f537d474 |
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05-Sep-2019 |
Lewis Huang <Lewis.Huang@amd.com> |
drm/amd/display: check phy dpalt lane count config [Why] Type-c PHY config is not align with dpcd lane count. When those values didn't match, it cause driver do link training with 4 lane but phy only can output 2 lane. The link trainig always fail. [How] 1. Modify get_max_link_cap function. According DPALT_DP4 to update max lane count. 2. Add dp_mst_verify_link_cap to handle MST case because we didn't call dp_mst_verify_link_cap for MST case. Signed-off-by: Lewis Huang <Lewis.Huang@amd.com> Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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78d9b95e |
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07-Aug-2019 |
Charlene Liu <charlene.liu@amd.com> |
drm/amd/display: set av_mute in hw_init for HDMI [Description] OS will reserve HW state in UEFI mode. Driver init_hw reset to RGB which caused HDMI green in YCbCr mode. read HW blank_color based on acc_mode. Signed-off-by: Charlene Liu <charlene.liu@amd.com> Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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b5b1f455 |
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10-Jul-2019 |
Eric Yang <Eric.Yang2@amd.com> |
drm/amd/display: Enable type C hotplug [Why and How] We want to change where timing is done for alt mode. Some of the commented out #ifs are needed for DCN20 so we enable them for that case. Signed-off-by: Eric Yang <Eric.Yang2@amd.com> Reviewed-by: Eric Yang <eric.yang2@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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ca4d9b3a |
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07-May-2019 |
Harry Wentland <harry.wentland@amd.com> |
drm/amd/display: Add DCN2 DIO Add support for the DIO (Display IO) block of DCN2, which entails our stream and link encoders. HW Blocks: +--------+ | DIO | +--------+ Signed-off-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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68f1a00c |
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19-Jan-2019 |
Anthony Koo <Anthony.Koo@amd.com> |
drm/amd/display: interface to check if timing can be seamless [Why] Need to figure out whether a timing we want to commit matches something that GOP already programmed, in which case we can decide to some optimizations [How] 1. Add way to check for DIG FE 2. Add way to check for matching OTG timing 3. Add way to check for matching pixel clock (if possible) - Currently only support DP for pixel clock, since it is easy to calc Signed-off-by: Anthony Koo <Anthony.Koo@amd.com> Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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2ee7c03c |
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03-Dec-2018 |
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> |
drm/amd/display: Rename configure_encoder to enc1_configure_encoder Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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ac99243c |
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24-Jun-2018 |
Yongqiang Sun <yongqiang.sun@amd.com> |
drm/amd/display: expose dcn10_aux_initialize in header Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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1bd493e3 |
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18-Jun-2018 |
Tony Cheng <tony.cheng@amd.com> |
drm/amd/display: Expose configure_encoder for link_encoder Signed-off-by: Tony Cheng <tony.cheng@amd.com> Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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8e8539c2 |
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18-Jun-2018 |
Charlene Liu <charlene.liu@amd.com> |
drm/amd/display: Define couple extra DCN registers Signed-off-by: Charlene Liu <charlene.liu@amd.com> Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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f0cd0a34 |
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26-Apr-2018 |
Eric Bernstein <eric.bernstein@amd.com> |
drm/amd/display: DCN1 link encoder Create DCN1 link encoder files and update AUX and HPD register access. Signed-off-by: Eric Bernstein <eric.bernstein@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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